JP2022031325A - Semiconductor device and equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an advantageous technology for increasing the value of a semiconductor device.

SOLUTION: In a semiconductor device, a first chip in which a plurality of pixel circuits are arranged in a matrix of J rows and K columns and a second chip in which a plurality of electric circuits are arranged in a matrix of T rows and U columns are stacked, each of the plurality of electric circuits processes a signal generated by the plurality of pixel circuits, and the pixel circuit in the a-th row and the e1-th column is connected to the electric circuit in the p-th row and the v-th column, and the pixel circuit in the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column, and the pixel circuit in the a-th row and the g1-th column is connected to the electric circuit in the r-th row and the v-th column. The pixel circuit in the a-th row and the h-th column is connected to the electric circuit in the s-th row and the v-th column, and J<T and K<U are satisfied, and f1 and g1 are integers between e1 and h1, and q and r are integers between p and s.

SELECTED DRAWING: Figure 2

COPYRIGHT: (C)2022,JPO&INPIT

Description

The present invention relates to a semiconductor device in which a plurality of chips are laminated.

By using an image pickup device in which a chip including a pixel circuit and a chip including an electric circuit for processing a signal from the pixel circuit are laminated, the value of the image pickup device can be significantly improved. Patent Documents 1 and 2 disclose that a substrate having a plurality of row circuits and a substrate having a pixel portion are laminated.

Japanese Unexamined Patent Publication No. 2012-104684 Japanese Unexamined Patent Publication No. 2013-51674

The characteristics of the electric circuit that processes the signal may vary depending on the position of the electric circuit. Depending on the correspondence between the electric circuit and the pixel circuit, unevenness (shading) may occur in the image due to variations in the characteristics of the electric circuit. Therefore, it is necessary to improve the performance of semiconductor devices, which mainly focus on image quality. Therefore, an object of the present invention is to provide an advantageous technique for improving the performance of a semiconductor device.

The means for solving the above problems are a first chip in which a plurality of pixel circuits are arranged in a matrix of J rows and K columns, and a first chip in which a plurality of electric circuits are arranged in a matrix of T rows and U columns. It is a semiconductor device in which two chips and two chips are laminated, and each of the plurality of electric circuits processes a signal generated by the plurality of pixel circuits, and is the ath row and the first of the plurality of pixel circuits. The pixel circuit of the e1 column is connected to the electric circuit of the pth row and the vth column of the plurality of electric circuits, and the pixel circuit of the ath row and the f1 column of the plurality of pixel circuits is , The qth row and vth column electric circuit of the plurality of electric circuits is connected, and the ath row and g1st column pixel circuits of the plurality of pixel circuits are the plurality of electric circuits. The pixel circuit in the ath row and the h1th column of the plurality of pixel circuits is connected to the electric circuit in the rth row and the vth column of the plurality of electric circuits. And connected to the electric circuit of the vth column, T <J and U <K, f1 and g1 are integers between e1 and h1, and q and r are integers between p and s. It is characterized by being.

An object of the present invention is to provide an advantageous technique for improving the performance of a semiconductor device.

The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device. The schematic diagram explaining an embodiment of a semiconductor device.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the following description and drawings, common reference numerals are given to common configurations across a plurality of drawings. Therefore, a common configuration will be described with reference to each other with reference to a plurality of drawings, and the description of the configuration with a common reference numeral will be omitted as appropriate.

FIG. 1A shows a semiconductor device APR. All or part of the semiconductor device APR is a semiconductor device IC which is a laminate of chip 1 and chip 2. The semiconductor device APR of this example is a photoelectric conversion device that can be used as, for example, an image sensor, an AF (Auto Focus) sensor, a photometric sensor, or a distance measuring sensor. In the semiconductor device APR, a chip 1 in which a plurality of pixel circuits 10 are arranged in a matrix and a chip 2 in which a plurality of electric circuits 20 are arranged in a matrix are laminated. In addition, another chip may be laminated on the side opposite to the chip 1 with respect to the chip 2. A DRAM cell array can be placed on this other chip. The DRAM cell array can store signals processed by a plurality of electric circuits 20.

The chip 1 has a wiring structure including a semiconductor layer 11 provided with a plurality of semiconductor elements (not shown) constituting the plurality of pixel circuits 10 and a wiring layer (not shown) of the M layer constituting the plurality of pixel circuits 10. 12 and. The chip 2 has a wiring structure including a semiconductor layer 21 provided with a plurality of semiconductor elements (not shown) constituting the plurality of electric circuits 20 and an N layer wiring layer (not shown) constituting the plurality of electric circuits 20. 22 and.

The wiring structure 12 is arranged between the semiconductor layer 11 and the semiconductor layer 21. The wiring structure 22 is arranged between the wiring structure 12 and the semiconductor layer 21.

Although the details will be described later, the pixel circuit 10 includes a photoelectric conversion element, and typically further includes an amplification element. The electric circuit 20 is an electric circuit having a function of processing a signal from the pixel circuit 10. The electric circuit 20 can further have a function other than signal processing.

FIG. 1B shows a device EQP equipped with a semiconductor device APR. The semiconductor device IC has a pixel area PX in which pixel CCTs including the pixel circuit 10 are arranged in a matrix. The pixel CCT can include a microlens and a color filter in addition to the photoelectric conversion element and the amplification element. The semiconductor device IC can have a peripheral area PR around the pixel area PX. A circuit other than the pixel circuit 10 can be arranged in the peripheral area PR. In addition to the semiconductor device IC, the semiconductor device APR can include a package PKG for storing the semiconductor device IC. The equipment EQP may further include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a storage device MMRY, and a mechanical device MCNH. Details of the device EQP will be described later.

(First Embodiment)
The first embodiment will be described with reference to FIG. FIG. 2A shows the arrangement of a plurality of pixel circuits 10 arranged in a matrix of rows J and columns K on the chip 1. Practically, J ≧ 100 and K ≧ 100, and more preferably J ≧ 1000 and K ≧ 1000. The J line of the pixel circuit 10 includes the a1 to a4 lines, the b1 to b4 lines, the c1 to c4 lines, and the d1 to d4 lines in this order. The first a1 to a4th rows include the first a1st row, the a2nd row, the a3rd row, and the a4th row in this order, and these are collectively referred to as the ath row. The b1 to b4 lines are collectively referred to as the bth line, the c1 to c4 lines are collectively referred to as the cth line, and the d1 to d4 lines are collectively referred to as the dth line. a, b, c, and d are positive integers, and a <b <c <d. a1, a2, a3, and a4 are positive integers, and a1 <a2 <a3 <a4. For example, if the plurality of pixel circuits 10 shown in FIG. 2A are all pixel circuits 10, a1 = 1, a2 = 2, a3 = 3, a4 = 4, b1 = 5, b4 = 8 , C1 = 9, c4 = 12, d1 = 13, d4J = 16. In the description, it is assumed that the lines a1 to d4 are adjacent to each other. When the rows are adjacent, a2 = 1 + a1, a3 = 1 + a2, a4 = 1 + a3, b1 = 1 + a4, c1 = 1 + b4, d1 = 1 + c4. However, it does not deny that there is a line (not shown) between the two lines.

The K column of the pixel circuit 10 includes the first column, the f1 column, the g1 column, the h1 column, the e2 column, the f2 column, the g2 column, and the h2 column in this order. That is, e1, f1, g1, h1, e2, f2, g2, and h2 are positive integers, and e1 <f1 <g1 <h1 <e2 <f2 <g2 <h2. Similarly, h2 <e3 <f3 <g3 <h3 <e4 <f4 <g4 <h4. be. For example, if the plurality of pixel circuits 10 shown in FIG. 2A are all pixel circuits 10, e1 = 1, f1 = 2, g1 = 3, h1 = 4, e2 = 5, f2 = 6. , G2 = 7, h2 = 8, h5 = K = 20. In the description, it is assumed that the lines e1 to h5 are adjacent to each other. When the columns are adjacent, f1 = 1 + e1, g1 = 1 + f1, h1 = 1 + g1, and e2 = 1 + h4, e3 = 1 + h2, e4 = 1 + h3, e5 = 1 + h4. However, it does not deny that there is a column (not shown) between the two columns.

In the following description, the pixel circuit 10 in the αth row and the βth column is referred to as a pixel circuit 10 (α, β). The angle formed by the rows and columns of the pixel circuit 10 is not limited to 90 degrees, but may be 60 to 120 degrees, or may form a matrix in a parallel quadrilateral shape.

Two or more pixel circuits 10 of the pixel circuits 10 in the same row are commonly connected to the signal line 14. The signal line 14 extends along the direction in which the pixel circuits 10 in the same row are arranged. For example, the pixel circuits 10 (a1, e1), 10 (b1, e1), 10 (c1, e1), and 10 (d1, e1) in the first row are connected to a common signal line 14. All the pixel circuits 10 of the pixel circuits 10 in the same row may be connected in common to one signal line 14, but a signal in which two or more pixel circuits 10 of the pixel circuits 10 in the same row are commonly connected. There may be a plurality of lines 14. For example, the pixel circuits 10 (a2, e1), 10 (b2, e1), 10 (c2, e1), and 10 (d2, e1) in the first row are signals to which the pixel circuits 10 (a1, e1) are connected. It may be commonly connected to a signal line 14 different from the line 14. The plurality of pixel circuits 10 connected to the plurality of signal lines 14 are sequentially selected from the pixel circuits 10 to be read out to the signal lines 14 and are read out respectively. By reading the signals from the pixel circuits 10 in the same row in parallel on the plurality of signal lines 14, the signal reading can be speeded up.

FIG. 2B shows the arrangement of a plurality of electric circuits 20 arranged in a matrix of T rows and U columns on the chip 2. Here, T <J and U <K. Practically, T ≧ 10 and U ≧ 10, and more preferably T ≦ 1000 and U ≦ 1000. The T row of the electric circuit 20 includes the qth row, the qth row, the rth row, and the sth row in this order. That is, p, q, r, and s are positive integers and p <q <r <s. For example, if the plurality of electric circuits 20 shown in FIG. 2B are all electric circuits 20, p = 1, q = 2, r = 3, and s = T = 4. In the description, it is assumed that the lines p to s are adjacent to each other. When the rows are adjacent, q = 1 + p, r = 1 + q, s = 1 + r. However, it does not deny that there is a line (not shown) between the two lines.

The U column of the electric circuit 20 includes the vth column, the wth column, the xth column, the yth column, and the zth column in this order. That is, v, w, x, y, and z are positive integers and v <w <x <y <z. For example, if the plurality of electric circuits 20 shown in FIG. 2B are all electric circuits 20, then v = 1, w = 2, x = 3, y = 4, z = U = 5. .. In the description, it is assumed that the columns v to z are adjacent to each other. When the columns are adjacent, w = 1 + v, x = 1 + w, y = 1 + x, z = 1 + y. However, it does not deny that there is a column (not shown) between the two columns.

In the following description, the electric circuit 20 in the γ row and the δ column is referred to as an electric circuit 20 (γ, δ). The angle formed by the rows and columns of the electric circuit 20 is not limited to 90 degrees, and may be 60 to 120 degrees, or may form a matrix in a parallel quadrilateral shape.

The electric circuit 20 in the vth column includes the electric circuit 20 (p, v) in the pth row, the electric circuit 20 (q, v) in the qth row, the electric circuit 20 (r, v) in the rth row, and s. Includes line electrical circuit 20 (s, v). The electric circuit 20 in the wth column includes the electric circuit 20 (p, w) in the pth row, the electric circuit 20 (q, w) in the qth row, the electric circuit 20 (r, w) in the rth row, and s. Includes line electrical circuit 20 (s, v).

Each of the plurality of pixel circuits 10 is connected to any one of the plurality of electric circuits 20. The wiring structure 12 is provided with a plurality of conductive portions 13 as shown in FIG. 2 (a), and the wiring structure 22 is provided with a plurality of conductive portions 23 as shown in FIG. 2 (b). There is. By joining the conductive portion 13 and the conductive portion 23, each of the plurality of pixel circuits 10 is electrically connected to the plurality of electric circuits 20 via the conductive portion 13 and the conductive portion 23.

A set of pixel circuits 10 connected to the same electric circuit 20 is referred to as a pixel group 15. In this example, the pixel group 15 is composed of J pixel circuits 10. In one pixel group 15, all the pixel circuits 10 belonging to this one pixel group 15 are connected to the same electric circuit 20. Then, the pixel circuit 10 included in the pixel group 15 other than the pixel group 15 is not connected to the same electric circuit 20. In the present embodiment, a plurality of pixel circuits 10 of the pixel circuits 10 in the same row form a pixel group 15. In this example, all the pixel circuits 10 in the same row belong to one pixel group 15. For example, all the pixel circuits 10 in the first column belong to the pixel group 15e1. In FIG. 2A, the pixel group 15 composed of the pixel circuits 10 in the β column is expressed as the pixel group 15β (β is e1, f1, e2, etc.).

FIG. 2B shows which of the plurality of pixel groups 15 is connected to each of the electric circuits 20 via the conductive portion 23 corresponding to the electric circuit 20. For example, the electric circuit 20 (p, v) is connected to the pixel group 15e1, and the electric circuit 20 (q, v) is connected to the pixel group 15f1. The electric circuit 20 (r, v) is connected to the pixel group 15f1, and the electric circuit 20 (s, v) is connected to the pixel group 15g1. For example, the electric circuit 20 (p, w) is connected to the pixel group 15e2, and the electric circuit 20 (q, w) is connected to the pixel group 15f2. The electric circuit 20 (r, w) is connected to the pixel group 15g2, and the electric circuit 20 (s, w) is connected to the pixel group 15h2. For example, the electric circuit 20 (p, x) is connected to the pixel group 15e3, and the electric circuit 20 (q, x) is connected to the pixel group 15f3. The electric circuit 20 (r, x) is connected to the pixel group 15g3, and the electric circuit 20 (s, x) is connected to the pixel group 15h3.

In the example shown in FIGS. 2A and 2B, all the pixel circuits 10 of the pixel circuits 10 in the same row belong to the same pixel group 15. Therefore, all the pixel circuits 10 in the first row are connected to the electric circuit 20 (p, v), and all the pixel circuits 10 in the f1 row are connected to the electric circuit 20 (q, v). All the pixel circuits 10 in the g1 column are connected to the electric circuit 20 (r, v), and all the pixel circuits 10 in the h1 column are connected to the electric circuit 20 (s, v). All the pixel circuits 10 in the second column are connected to the electric circuit 20 (p, w), and all the pixel circuits 10 in the f2 column are connected to the electric circuit 20 (q, w). All the pixel circuits 10 in the g2 column are connected to the electric circuit 20 (r, w), and all the pixel circuits 10 in the h2 column are connected to the electric circuit 20 (s, w). All the pixel circuits 10 in the third column are connected to the electric circuit 20 (p, x), and all the pixel circuits 10 in the f3 column are connected to the electric circuit 20 (q, x). All the pixel circuits 10 in the g3 column are connected to the electric circuit 20 (r, x), and all the pixel circuits 10 in the h3 column are connected to the electric circuit 20 (s, x).

In the present embodiment, since e1 <f1 <g1 <h1 and p <q <r <s, when the column numbers of the electric circuits 20 are the same, the larger the column numbers of the pixel circuits 10, the more connected. The line number of the electric circuit 20 becomes large.

The connection relationship between the plurality of pixel circuits 10 and the plurality of electric circuits 20 will be described. In the example shown in FIGS. 2 (a) and 2 (b), all the pixel circuits 10 in the a row are connected to the electric circuit 20 (i, j), and all the pixel circuits 10 in the b row are electric circuits. It is connected to 20 (k, j), and all the pixel circuits 10 in the cth column are connected to the electric circuit 20 (s, j). All the pixel circuits 10 in the d-th column are connected to the electric circuit 20 (i, r), all the pixel circuits 10 in the e-th column are connected to the electric circuit 20 (k, r), and all the pixel circuits 10 in the f-th column are connected. The pixel circuit 10 is connected to the electric circuit 20 (s, r). All the pixel circuits 10 in the g-th column are connected to the electric circuit 20 (i, t), all the pixel circuits 10 in the h-th column are connected to the electric circuit 20 (k, t), and all the pixel circuits 10 in the q-th column are connected to the electric circuit 20 (k, t). The pixel circuit 10 is connected to the electric circuit 20 (s, t).

In the present embodiment, since e1 <f1 <g1 <h1, when the column numbers of the electric circuits 20 are the same, the larger the column number of the pixel circuit 10, the larger the row number of the connected electric circuit 20. Will be.

Since h1 <e2, when the column number of the pixel circuit 10 becomes large (from the h1 column to the e2 column), the column number of the connected electric circuit 20 changes (from the vth column to the wth column). Become). The number of columns of the pixel circuit 10 assigned to the electric circuit 20 in the same column is e2-e1, which is equal to the number of rows T of the electric circuit 20 included in the same column (T = e2-e1). In other words, the row of the connected electric circuit 20 changes for each number of rows of the pixel circuit 10 equal to T.

In the present embodiment, two pixel circuits 10 (for example, columns e1 and e2) to which electric circuits 20 in the same row (for example, row p) and adjacent columns (for example, columns v and w) are connected, respectively, are connected. There are pixel circuits 10 for T-1 rows between them.

Further, the pixel circuit 10 in column K is assigned to any electric circuit 20 for each column. Therefore, T × U = K can be obtained. In order to increase the degree of parallelism of signal processing, it is preferable that J ≦ K, so J ≦ T × U. Further, since T <J and U <K, T × U <J × K. Therefore, T × U—K <J × K—T × U is satisfied. When this is transformed, T × U <(J + 1) × K / 2, and since J + 1≈J, T × U <J × K / 2. Therefore, when the connection method of the present embodiment is adopted, it is preferable to satisfy J ≦ T × U <J × K / 2.

The idea of the first embodiment is to bring the distance between the two electric circuits 20 to which the pixel circuits 10 in the adjacent rows (for example, the e1 row and the f1 row) are connected to each other. That is, each of the adjacent pixel circuits 10 is connected to the adjacent electric circuit 20. Specifically, the pixel circuit 10 of four columns (for example, columns e1 to h1) of the same row (for example, row a) and the same column (for example, column v) connected to the pixel circuit 10 of four columns. Pay attention to the electric circuit 20 for four rows (for example, the ps to s rows). The pixel circuit 10 in the middle row (first row, g1 row) of the four rows of pixel circuits 10 is the rows at both ends of the four rows of pixel circuits 10 (first row, h1 row). It is closer to the pixel circuits 10 in the rows at both ends (first row, h1 row) than the pixel circuits 10 in the above. The electric circuit 20 in the middle row (the qth row and the rth row) of the four electric circuits 20 is the row at both ends of the four electric circuits 20 (the pth row and the sth row). It is closer to the electric circuits 20 in the rows (pth row, sth row) at both ends than the electric circuits 20 in the above. The pixel circuit 10 in the middle column (f1 column, g1 column) of the pixel circuits 10 for four columns is the middle column (qth column, r) in the electric circuit 20 for four rows. It is connected to the electric circuit 20 (row). By doing so, the arrangement order of the pixel circuits 10 for four columns and the arrangement order of the electric circuits 20 for four rows to which each of the pixel circuits 10 for four columns are connected are similar or match. By doing so, the influence of the difference in the characteristics of signal processing by the electric circuit 20 can be reduced. Regarding the electric circuit 20 for four rows, the characteristic difference between the electric circuit 20 in the middle row and the electric circuit 20 in one end row, and the characteristics between the electric circuit 20 in the middle row and the electric circuit 20 in the other end row. The difference is referred to as a first characteristic difference. The characteristic difference between the electric circuit 20 in one row and the electric circuit 20 in the other end row is referred to as a second characteristic difference. This characteristic difference is due to the wiring length and the like, and the characteristic difference between the two electric circuits 20 is proportional to the distance. Therefore, the first characteristic difference is smaller than the second characteristic difference. With respect to the pixel circuits 10 for four rows, the output difference between the pixel circuit 10 in the middle row and the pixel circuit 10 in one end row, and the output difference between the pixel circuit 10 in the other end row and the pixel circuit 10 in the middle row. Corresponds to the first characteristic difference. Therefore, in order to reduce the output difference of the signals corresponding to the two pixel circuits 10, it is preferable that the smaller the distance between the two pixel circuits 10, the smaller the distance between the two corresponding electric circuits 20. It is. As a result, a good image with small shading can be obtained.

This corresponds to f1 and g1 being integers between e1 and h1 and q and r being integers between p and s. In particular, it is preferable that g1 is an integer between f1 and h1 and r is an integer between q and s. It is also preferable that f1 is an integer between e1 and g1 and q is an integer between p and r. Here, the relationship between the pixel circuit 10 in the ath row and the electric circuit 20 in the vth column is illustrated, but the same applies to the bth row, the cth row, and the dth row, and the wth column, the xth column, and so on. The same applies to the y-th column and the z-th column.

(Second Embodiment)
The second embodiment will be described with reference to FIG. The points that may be the same as those of other embodiments will be omitted. FIG. 3A shows the arrangement of the pixel circuit 10 as in FIG. 2A, and FIG. 3B shows the arrangement of the electric circuit 20 as in FIG. 2B. In the second embodiment, the connection relationship of the electric circuits 20 in the w-th row and the y-th row is different from that in the first embodiment.

All the pixel circuits 10 of the pixel circuits 10 in the same row belong to the same pixel group 15. Therefore, all the pixel circuits 10 in the g1 column are connected to the electric circuit 20 (r, v), and all the pixel circuits 10 in the h1 column are connected to the electric circuit 20 (s, v). All the pixel circuits 10 in the second column are connected to the electric circuit 20 (s, w), and all the pixel circuits 10 in the f2 column are connected to the electric circuit 20 (r, w). All the pixel circuits 10 in the g2 column are connected to the electric circuit 20 (q, w), and all the pixel circuits 10 in the h2 column are connected to the electric circuit 20 (p, w). All the pixel circuits 10 in the third column are connected to the electric circuit 20 (p, x), and all the pixel circuits 10 in the f3 column are connected to the electric circuit 20 (q, x). All the pixel circuits 10 in the g3 column are connected to the electric circuit 20 (r, x), and all the pixel circuits 10 in the h3 column are connected to the electric circuit 20 (s, x).

For the pixel circuits 10 in the first column to the h1 column, as the column number of the pixel circuit 10 increases, the row number of the corresponding electric circuit 20 increases from the p-th row to the s-th row. However, for the pixel circuits 10 in the second column to the h2 column, as the column number of the pixel circuit 10 increases, the row number of the corresponding electric circuit 20 decreases from the sth row to the pth row. As for the pixel circuits 10 in columns e3 to h3, the row numbers of the corresponding electric circuits 20 increase from the p-th row to the s-th row as the column numbers of the pixel circuits 10 increase. For the pixel circuits 10 in columns e4 to h4, as the column number of the pixel circuit 10 increases, the row number of the corresponding electric circuit 20 decreases from the s row to the p row. In this way, as the column number of the pixel circuit 10 increases, the row number of the corresponding electric circuit 20 repeats increasing and decreasing in a cycle.

The idea of the second embodiment is to make the distance between the two electric circuits 20 to which the pixel circuits 10 of the adjacent rows (for example, the h1 row and the e2 row) are connected to each other closer than those of the first embodiment. For example, the pixel group 15h1 is connected to the electric circuit 20 (s, v), and the pixel group 15e2 close to the pixel group 15h1 is the electric circuit 20 (s, w) close to the electric circuit 20 (s, v). It is connected to the. The pixel group 15f2 is connected to the electric circuit 20 (r, w), the pixel group 15g2 is connected to the electric circuit 20 (q, w), and the pixel group 15h2 is connected to the electric circuit 20 (p, w). It is connected to w). Of particular note is the electric circuit 20 to which the pixel circuit 10 and the pixel circuit 10 in the second row are connected. The h1st column and the e2nd column are close to each other. In this example, the h1 column and the e2 column are adjacent to each other (e2 = h1 + 1), but at least the pair of the h1 column and the e2 column is closer than the pair of the g1 column and the f2 column. It can be said that it is doing. Then, the electric circuit 20 (s, v) to which the pixel group 15h1 in the first column is connected and the electric circuit 20 (s, w) to which the pixel group 15e2 in the e2 column is connected are in the same row (s row). Is. Further, the electric circuit 20 (s, v) and the electric circuit 20 (s, w) are adjacent rows (vth row and wth row). Therefore, it can be said that the electric circuit 20 (s, v) and the electric circuit 20 (s, w) are close to each other. By doing so, since the signal corresponding to the adjacent pixel circuit 10 can be processed by the adjacent electric circuit 20 having a small characteristic difference, the output difference of the signal corresponding to the adjacent pixel circuit 10 can be reduced. As a result, a good image with small shading can be obtained.

(Third Embodiment)
The third embodiment will be described with reference to FIG. The points that may be the same as those of other embodiments will be omitted. FIG. 4A shows the arrangement of the pixel circuit 10 as in FIG. 2A, and FIG. 4B shows the arrangement of the electric circuit 20 as in FIG. 2B. In the third embodiment, the rows of the electric circuit 20 are configured as the first p1 to s1 rows and the second p2 to s2 rows. p1 <q1 <r1 <s1 <p2 <q2 <r2 <s2. In the third embodiment, the a1 to b4 rows of the pixel circuit 10 are assigned to the pixel groups 15e11 to 15h51, and the c1 to d4 rows of the pixel circuit 10 are assigned to the pixel groups 15e12 to 15h52. The pixel groups 15e11 to 15h51 are connected to the electric circuit 20 in rows p1 to s1 and columns v to z. For example, the pixel circuit 10 (c, e1) in the c-th row and the e1 column is connected to the electric circuit 20 (p2, v) in the p2 row and the v-th column. The pixel groups 15e12 to 15h52 are connected to the electric circuit 20 in rows p2 to s2 and columns v to z. Further, the pixel circuit 10 (c, f1) in the c-th row and the f1 column is connected to the electric circuit 20 (q2, v) in the q2 row and the v-th column. The pixel circuit 10 (c, g1) in the c-th row and the g1 column is connected to the electric circuit 20 (r2, v) in the r2 row and the v-th column. According to the third embodiment, since the pixel circuit 10 in the same column can perform signal processing in parallel by the electric circuit 20 in the rows p1 to s1 and the electric circuit 20 in the rows p2 to s2, signal processing can be performed. Can be speeded up.

(Fourth Embodiment)
The fourth embodiment will be described with reference to FIG. The points that may be the same as those of other embodiments will be omitted. 5 (a) shows the arrangement of the pixel circuit 10 as in FIG. 2 (a), and FIG. 5 (b) shows the arrangement of the electric circuit 20 as in FIG. 2 (b). In the fourth embodiment, as in the second embodiment, the electric circuit 20 to which the pixel groups composed of the columns close to each other in the pixel circuit 10 are connected is close to each other in the third embodiment. ing. That is, the pixel group 15h11 and the pixel group 15e21 that are close to each other are connected to the electric circuit 20 (s1, v) and the electric circuit 20 (s1, w) in the same row (s1st row), respectively. Similarly, the pixel group 15h12 and the pixel group 15e22 that are close to each other are connected to the electric circuit 20 (s2, v) and the electric circuit 20 (s2, w) in the same row (s1st row), respectively.

(Fifth Embodiment)
The fifth embodiment will be described with reference to FIG. The points that may be the same as those of other embodiments will be omitted. FIG. 6A shows the arrangement of the pixel circuit 10 as in FIG. 2A, and FIG. 6B shows the arrangement of the electric circuit 20 as in FIG. 2B. In the fifth embodiment, in the fourth embodiment, the electric circuits 20 to which the pixel groups close to each other are connected are close to each other. That is, the pixel groups 15h11 and the pixel groups 15h12, which are composed of the pixel circuits 10 in the same row (for example, the h1st row) and are close to each other, are close to each other. Then, the pixel group 15h11 and the pixel group 15h12 are in the electric circuit 20 (s1, v) and the electric circuit 20 (p2, v) in the adjacent rows (s1st row and p2th row) in the same column (v column), respectively. It is connected. Similarly, the pixel group 15e21 and the pixel group 15e22 that are close to each other are the electric circuit 20 (s1, w) and the electric circuit 20 (p2, w) in the adjacent rows (th1st row and p2nd row) in the same column (wth column). ) And are connected to each.

(Sixth Embodiment)
The sixth embodiment is a form common to the first to fifth embodiments. FIG. 7 shows an equivalent circuit of the semiconductor device shown in FIG. FIG. 7 shows a pixel circuit 10 for 8 rows (for example, rows a1 to b4) and 3 columns (for example, columns e1 to g1) of the pixel circuits 10 shown in FIG. Further, FIG. 7 shows an electric circuit 20 for three rows (for example, rows p to r) and one column (for example, column v) of the electric circuits 20 shown in FIG.

The pixel circuit 10 of the chip 1 has four (λ) signal lines 14a, 14b, 14c, and 14d with respect to the pixel circuit 10 in one row. The signal lines 14a, 14b, 14c, and 14d are collectively referred to as the signal line 14. The pixel circuit 10 of the first line (the first line a1) of the line a is connected to the signal line 14a. The pixel circuits 10 in the second, third, and fourth rows (thirds a2, a3, a4) of the ath row are connected to the signal lines 14b, 14c, and 14d in order. For the pixel circuit 10 on the λ + 1st line and thereafter, the pixel circuit 10 on the (ρ × λ + 1) line (ρ is a natural number) is connected to the signal line 14a. The pixel circuits 10 on the (ρ × λ + 2) line, the (ρ × λ + 3) line, and the (ρ × λ + 4) line are connected to the signal lines 14b, 14c, and 14d in that order. When there are J pixels in one row, J / λ pixel circuits 10 are commonly connected to one signal line 14a. The connection relationship between the pixel circuit 10 and the signal line 14 is the same in the other rows of the pixel circuit 10.

A set of pixel circuits 10 connected to the same electric circuit 20 is referred to as a pixel group 15. A set of λ pixel circuits 10 connected to different λ signal lines and arranged continuously is called a pixel set 16. In this example, the pixel group 15 consists of J rows (J) of pixels and may include J / λ pixel sets 16. In one pixel group 15, all the pixel circuits 10 belonging to the one pixel group 15 are connected to the same electric circuit 20. Then, the pixel circuit 10 included in the pixel group 15 other than the pixel group 15 is not connected to the same electric circuit 20.

A current source 120 is connected to each of the signal lines 14a to 14d of the signal line 14. The current source 120 supplies a current to each signal line of the signal line 14 via the connection portion 300. Although the current source 120 of this example is provided on the chip 2, it may be provided on the chip 1.

Each of the signal lines 14 is connected to the electric circuit 20 via the connection portion 300. In the example of FIG. 7, each row of the pixel circuit 10 is connected to different electric circuits 20-1, 20-2, and 20-3.

The electric circuit 20 has an input unit 210, a main unit 220, and an output unit 230. The input unit 210 has at least λ input terminals. The λ signal lines 14a, 14b, 14c, 14d included in the signal line 14 are connected to the λ input terminals of the input unit 210. The main unit 220 processes, for example, a signal from the pixel circuit 10. Therefore, the main unit 220 can also be referred to as a signal processing unit. The input unit 210 sequentially selects the signal lines 14a, 14b, 14c, 14d of the signal line 14, and the main unit 220 sequentially processes the signals of the signal lines 14a, 14b, 14c, 14d. The output unit 230 outputs a signal from the electric circuit 20.

FIG. 7 shows the order in which signals are processed for the plurality of pixel circuits 10 from 01 to 08. First, the first pixel set 16 is selected by a scanning circuit (not shown). For example, the signal of the pixel circuit 10 in the (ρ × λ + 1) line, the signal of the pixel circuit 10 in the (ρ × λ + 2) line, the signal of the pixel circuit 10 in the (ρ × λ + 3) line, the (ρ × λ + 4) line. The signals of the pixel circuit 10 of the eye are sequentially processed (orders 01 to 04). Next, the next pixel set 16 is selected by a scanning circuit (not shown). That is, the signal of the pixel circuit 10 in the ((ρ + 1) × λ + 1) line, the signal of the pixel circuit 10 in the ((ρ + 1) × λ + 2) line, the signal of the pixel circuit 10 in the ((ρ + 1) × λ + 3) line, The signal of the pixel circuit 10 on the ((ρ + 1) × λ + 4) line is read out to the signal line 14. Then, by the input unit 210 and the main unit 220, the signal of the pixel circuit 10 in the ((ρ + 1) × λ + 2) line, the signal of the pixel circuit 10 in the ((ρ + 1) × λ + 3) line, ((ρ + 1) × λ + 4). The signals of the pixel circuit 10 in the row are sequentially processed (orders 05 to 08).

If the pixel circuits 10 are in the same row, signal processing can be performed in parallel by a plurality of electric circuits 20 corresponding to the pixel circuits 10 in each column. For example, the signal processing of the pixel circuit 10 in the (ρ × λ + 1) line to the (ρ × λ + 4) line is performed in parallel by the electric circuit 20-1, the electric circuit 20-2, and the electric circuit 20-3. Can be done. Similarly, the signal processing of the pixel circuit 10 in the ((ρ + 1) × λ + 1) line to the ((ρ + 1) × λ + 4) line is performed by the electric circuit 20-1, the electric circuit 20-2, and the electric circuit 20-. It can be done in parallel with 3. The processing of the signal of the pixel circuit 10 in the (ρ × λ + 1) line to the (ρ × λ + 4) line is the signal of the pixel circuit 10 in the ((ρ + 1) × λ + 1) line to the ((ρ + 1) × λ + 4) line. It is performed at a different timing from the processing of.

FIG. 8 shows an example of an equivalent circuit of the pixel circuit 10. The pixel circuit 10 includes photoelectric conversion elements 601a and 601b which are photodiodes. One microlens (not shown) and light transmitted through a color filter are incident on the photoelectric conversion elements 601a and 601b. That is, the wavelengths of the light incident on the photoelectric conversion element 601a and the light incident on the photoelectric conversion element 601b are substantially the same. The photoelectric conversion element 601a is connected to the charge detection unit 605 via the transfer transistor 603a. The charge detection unit 605 has a floating diffusion structure. Further, the gate of the transfer transistor 603a is connected to a scanning circuit (not shown) via a control line 650. The photoelectric conversion element 601b is connected to the charge detection unit 605 via the transfer transistor 603b. Further, the gate of the transfer transistor 603b is connected to a scanning circuit (not shown) via a control line 655.

The charge detection unit 605 is connected to the reset transistor 606 and the gate of the amplification transistor 607. The power supply voltage Vdd is supplied to the reset transistor 606 and the amplification transistor 607. The gate of the reset transistor 606 is connected to a scanning circuit (not shown) via a control line 660.

The amplification transistor 607 is connected to the selection transistor 608. The gate of the selection transistor 608 is connected to a vertical scanning circuit (not shown) via a control line 665. The selection transistor 608 is connected to any signal line of the signal line 14. In the above-described embodiment, the semiconductor element connected to the conductive portion 13 is a selection transistor 608, and when the selection transistor 608 is omitted, it is an amplification transistor 607.

FIG. 9 shows an example of an equivalent circuit of the electric circuit 20. The selection circuit 240 provided in the input unit 210 is, for example, a multiplexer. The semiconductor element connected to the conductive portion 23 in the above-described embodiment may be an input transistor of a multiplexer. The electric circuit 20 of this example may include an analog-to-digital converter of a sequential comparison type (SAR) as a main unit 220. The pixel signal PIX selected by the selection circuit 240 is input to the inverting input terminal (−) of the comparison circuit 260 of the main unit 220 via the auxiliary circuit 250 provided in the input unit 210. The auxiliary circuit 250 can be a sample / hold circuit and / or an amplifier circuit. The reference signal REF is input to the non-inverting input terminal (+) of the comparison circuit 260. The reference signal REF is supplied from the signal generation circuit 290. The signal generation circuit 290 may include a digital-to-analog converter (DAC). Only a part of the signal generation circuit 290 may be included in the electric circuit 20 arranged in a matrix, and the remaining part may be arranged in the peripheral area PR (see FIG. 1). The comparison circuit 260 outputs a comparison signal CMP showing a comparison result of the magnitude relationship between the pixel signal PIX and the reference signal REF. The comparison signal CMP is taken into the storage circuit 270. The storage circuit 270 is a digital memory. The comparison circuit 260 and the storage circuit 270 are synchronized by the synchronization signal CLK from the signal generation circuit 290. The signal generation circuit 290 can operate in response to the signal captured in the storage circuit 270. A digital signal DIG is held in the storage circuit 270. The output unit 230 includes a selection transistor selected by a scanning circuit (not shown), and when the selection transistor selected by the scanning circuit is turned ON, data is read from the desired electric circuit 20 to a reading circuit (not shown). Is done. A digital signal (data) is output from the output circuit 280 provided in the output unit 230. The output circuit 280 may include, for example, a sense amplifier. The output circuit 280 can also include a parallel-serial converter and an interface circuit for transmitting a low voltage differential signal (LVDS). However, it is preferable that these interface circuits are provided outside the electric circuit 20.

The reference signal REF1 of the first signal level is input, and the first comparison signal CMP1 indicating the comparison result is taken into the memory as the high-order bit. Next, a reference signal REF2 having a second signal level different from that of the first signal level is input based on the first comparison signal CMP1, and the second comparison signal CMP2 indicating the comparison result is taken into the memory as a middle bit. Next, a reference signal REF3 having a third signal level different from the second signal level is input based on the second comparison signal CMP2, and the third comparison signal CMP3 indicating the comparison result is taken into the memory as the lower bits. In this way, a plurality of bits of digital signal DIG can be obtained by repeating the comparison a plurality of times.

It should be noted that the electric circuit 20 can also perform an inclined analog-to-digital conversion. In that case, the signal generation circuit 290 generates a lamp signal as a reference signal REF and a count signal (not shown). The comparison circuit 260 inverts the output of the comparison signal CMP at the timing when the comparison result between the reference signal REF and the pixel signal PIX changes. When the storage circuit 270 captures the count signal at the timing of inversion of the comparison signal CMP, a digital signal DIG corresponding to the count value of the count signal can be obtained.

(7th Embodiment)
As the seventh embodiment, an example of the operation of the semiconductor device described in the sixth embodiment will be described. In the operation shown in FIG. 10, a plurality of operations are performed in parallel as follows.
(1) Parallel operation of reading the N signal corresponding to the pixel circuit 10 on the first line and reading the N signal corresponding to the pixel circuit 10 on the second line (2) N corresponding to the pixel circuit 10 on the first line. Parallel operation of signal AD conversion and N signal readout corresponding to the second line pixel circuit 10 (3) N signal AD conversion corresponding to the fourth line pixel circuit 10 and the first line pixel circuit Parallel operation with the reading of the A + B signal corresponding to 10 (4) Parallel operation with the reading of the A + B signal corresponding to the pixel circuit 10 on the first line and the reading of the A + B signal corresponding to the pixel circuit 10 on the second line (4) 5) Parallel operation of AD conversion of the A + B signal corresponding to the pixel circuit 10 on the first line and reading of the A + B signal corresponding to the pixel circuit 10 on the second line By this parallel operation, the main unit 220 is once AD. The waiting period from the completion of the conversion to the next AD conversion can be shortened. As a result, the period required for AD conversion of the signals output by all the pixel circuits 10 can be shortened. Therefore, it is possible to advance the increase in the frame rate of the semiconductor device APR.

A case where both the focus detection mode and the image pickup mode are performed as the operation of the image pickup device will be described.

The operation of FIG. 11 is an operation in which the semiconductor device APR outputs a signal for focus detection and a signal for imaging. Hereinafter, the points different from the operation shown in FIG. 10 will be mainly described.

The operation of reading the N signal from the pixel circuit 10 of each row is the same as the operation shown in FIG. The operation of AD conversion of the N signal of the pixel circuit 10 of each row is the same as the operation shown in FIG.

The operation of reading out the A signal corresponding to the pixel circuit 10 of each row will be described. At time t9, the vertical scanning circuit sets the signal PTXA output to the pixel circuit 10 on the first line to the High level. As a result, the electric charge accumulated by the photoelectric conversion element 601a is transferred to the electric charge detection unit 605 via the transfer transistor 603a. As a result, the charge detection unit 605 has a potential corresponding to the charge of the photoelectric conversion element 601a. The A signal of the pixel circuit 10 in the first row is output to the signal line 14a in each column. This A signal is a first signal based on the signal of only a part of the photoelectric conversion elements among the plurality of photoelectric conversion elements. This first signal can be used as a signal for focus detection.

At time t10, the vertical scanning circuit sets the signal PTXA output to the pixel circuit 10 on the second line to the High level. As a result, the A signal of the pixel circuit 10 in the second row is output to the signal line 14b in each column.

At time t11, the vertical scanning circuit sets the signal PTXA output to the pixel circuit 10 on the third row to the High level. As a result, the A signal of the pixel circuit 10 in the third row is output to the signal line 14c in each column.

At time t12, the vertical scanning circuit sets the signal PTXA output to the pixel circuit 10 on the fourth line to the High level. As a result, the A signal of the pixel circuit 10 in the fourth row is output to the signal line 14d in each column.

The operation of AD conversion of the A signal corresponding to the pixel circuit 10 of each line will be described.

At time t17, the input unit 210 outputs the signal of the signal line 14a, that is, the A signal of the pixel circuit 10 on the first line to the main unit 220. The main unit 220a converts the A signal of the pixel circuit 10 on the first line into a digital signal.

At time t18, the input unit 210 outputs the signal of the signal line 14b, that is, the A signal of the pixel circuit 10 on the second line to the main unit 220. The main unit 220 converts the A signal of the pixel circuit 10 on the second line into a digital signal.

At time t19, the input unit 210 outputs the signal of the signal line 14c, that is, the A signal of the pixel circuit 10 on the third line to the main unit 220. The main unit 220 converts the A signal of the pixel circuit 10 on the third line into a digital signal.

At time t20, the input unit 210a outputs the signal of the signal line 14d, that is, the A signal of the pixel circuit 10 on the fourth line to the main unit 220. The main unit 220 converts the A signal of the pixel circuit 10 on the fourth line into a digital signal.

The operation of reading the A + B signal of the pixel circuit 10 of each line will be described.

At time t18, the vertical scanning circuit sets the signals PTXA and PTXB output to the pixel circuit 10 on the first line to the High level. As a result, the charges accumulated by the photoelectric conversion elements 601a and 601b are transferred to the charge detection unit 605 via the transfer transistors 603a and 603b. As a result, the A + B signal of the pixel circuit 10 on the first line is output to the signal line 14a.

At time t19, the vertical scanning circuit sets the signals PTXA and PTXB output to the pixel circuit 10 on the second row to the High level. As a result, the charges accumulated by the photoelectric conversion elements 601a and 601b are transferred to the charge detection unit 605 via the transfer transistors 603a and 603b. As a result, the A + B signal of the pixel circuit 10 on the second line is output to the signal line 14b.

At time t20, the vertical scanning circuit sets the signals PTXA and PTXB output to the pixel circuit 10 on the third row to the High level. As a result, the charges accumulated by the photoelectric conversion elements 601a and 601b are transferred to the charge detection unit 605 via the transfer transistors 603a and 603b. As a result, the A + B signal of the pixel circuit 10 on the third line is output to the signal line 14c.

At time t21, the vertical scanning circuit sets the signals PTXA and PTXB output to the pixel circuit 10 on the fourth line to the High level. As a result, the charges accumulated by the photoelectric conversion elements 601a and 601b are transferred to the charge detection unit 605 via the transfer transistors 603a and 603b. As a result, the A + B signal of the pixel circuit 10 on the fourth line is output to the signal line 14d.

The operation of AD conversion of the A + B signal of the pixel circuit 10 of each line will be described.

At time t26, the input unit 210 outputs the signal of the signal line 14a, that is, the A + B signal of the pixel circuit 10 on the first line to the main unit 220. The main unit 220 converts the A + B signal of the pixel circuit 10 on the first line into a digital signal.

At time t27, the input unit 210a outputs the signal of the signal line 14b, that is, the A + B signal of the pixel circuit 10 on the second line to the main unit 220. The main unit 220 converts the A + B signal of the pixel circuit 10 on the second line into a digital signal.

At time t28, the input unit 210a outputs the signal of the signal line 14c, that is, the A + B signal of the pixel circuit 10 on the third line to the main unit 220. The main unit 220 converts the A + B signal of the pixel circuit 10 on the third line into a digital signal.

At time t29, the input unit 210a outputs the signal of the signal line 14d, that is, the A + B signal of the pixel circuit 10 on the fourth line to the main unit 220. The main unit 220 converts the A + B signal of the pixel circuit 10 on the fourth line into a digital signal.

After that, the vertical scanning circuit sets the signal PSEL (5) of the pixel circuit 10 on the fifth row to the High level. After that, the same operation is repeated.

In this way, the image pickup apparatus of this embodiment can obtain a digital signal based on the N signal of each pixel, a digital signal based on the A signal of each pixel, and a digital signal based on the A + B signal of each pixel. ..

In the present embodiment, it is possible to realize high speed by the parallel operation performed by the semiconductor device APR in the operation shown in FIG. In the operation shown in FIG. 11, a plurality of operations are performed in parallel as follows.
(1) Parallel operation of reading the N signal corresponding to the pixel circuit 10 on the first line and reading the N signal corresponding to the pixel circuit 10 on the second line (2) N corresponding to the pixel circuit 10 on the first line. Parallel operation of signal AD conversion and N signal readout corresponding to the second line pixel circuit 10 (3) N signal AD conversion corresponding to the fourth line pixel circuit 10 and the first line pixel circuit Parallel operation with the reading of the A signal corresponding to 10 (4) Parallel operation with the reading of the A signal corresponding to the pixel circuit 10 on the first line and the reading of the A signal corresponding to the pixel circuit 10 on the second line (4) 5) Parallel operation of AD conversion of the A signal corresponding to the pixel circuit 10 on the first line and reading of the A signal corresponding to the pixel circuit 10 on the second line (6) Corresponding to the pixel circuit 10 on the fourth line. Parallel operation of AD conversion of A signal and reading of A + B signal corresponding to the pixel circuit 10 of the first line (7) Reading of the A + B signal corresponding to the pixel circuit 10 of the first line and the pixel circuit of the second line. Parallel operation with reading the A + B signal corresponding to 10 (8) Parallel operation with AD conversion of the A + B signal corresponding to the pixel circuit 10 on the first line and reading of the A signal corresponding to the pixel circuit 10 on the second line. By this parallel operation, the waiting period from the completion of one AD conversion by the main unit 220 to the next AD conversion can be shortened. As a result, the period required for AD conversion of the signals output by all the pixel circuits 10 can be shortened. Therefore, it is possible to advance the increase in the frame rate of the image pickup apparatus.

The present embodiment is not limited to this example. For example, in one frame period, it is possible to connect to the pixel to which the color filter of the first color is arranged and not to connect to the pixel to which the color filter of the second color is arranged. Focusing on a row of pixels in which the R and G color filters are arranged, the input unit 210 mainly includes signal lines 14a and 14c to which the pixels having the R color filter, which is the first color, are connected. Connect to 220. On the other hand, during the one frame period, the input unit 210 does not connect the signal lines 14b and 14d to which the pixels having the color filter of G, which is the second color, are connected to the main unit 220. In this configuration, the pixel signal input to the main unit 220 can be a signal corresponding to only one color. As a result, it is possible to obtain the effect that the correction of the AD conversion of the main unit 220 and the correction after the AD conversion can be simplified.

Further, in this embodiment, one electric circuit 20 is provided corresponding to one row of pixel circuits 10, but the present invention is not limited to this example. A plurality of electric circuits 20 may be provided for one row of pixel circuits 10. For example, an electric circuit 20 connected to the signal lines 14a and 14b and another electric circuit 20 connected to the signal lines 14c and 14d may be provided. Further, one electric circuit 20 may be shared by a plurality of pixel strings.

(8th Embodiment)
An eighth embodiment will be described with reference to FIG. The points that may be the same as those of other embodiments will be omitted. The eighth embodiment is a form common to the first to seventh embodiments. Eighth embodiment relates to a signal output from the electric circuit 20 after the processing is performed by the electric circuit 20. FIG. 12A shows the connection relationship between the pixel circuit 10 and the electric circuit 20, and FIG. 10B describes the output from the electric circuit 20.

FIG. 12A shows the pixel circuits 10 in rows a1 to a4 and columns e1 to h4. Further, the electric circuit 20 in rows p to s, columns v and w is shown. In FIG. 12A, numbers such as signals R11 and Gr11 corresponding to the signals generated by the pixel circuit 10 are assigned. Note that R, B, Gr, and Gb correspond to the colors indicated by the signals, R means red, B means blue, and Gr and Gb mean green, but the colors indicated by the signals are limited to these. is not. The connection relationship between the pixel circuit 10 and the electric circuit 20 is the same as that of any of the first to seventh embodiments.

The signal processing in the electric circuit 20 is performed in parallel by the plurality of electric circuits 20, but the reading of the signal from the plurality of electric circuits 20 is performed by sequentially selecting the electric circuit 20 to output the signal.

FIG. 12B shows the timing of signal processing in the electric circuit 20 and signal output from the electric circuit 20. At times t1 to t2, the signals R11, Gr11, R12, G12, R13, Gr13, R14, and Gr14 of the pixel circuit 10 in the first row are processed in parallel in each electric circuit 20. Next, at times t2 to t3, the electric circuit 20 to output the signal is sequentially selected. In this example, among the pixel circuits 10 in the a1 row, the f1 column and the g1 column are read from the e1 column so that the column numbers increase in order. That is, the signals R11, Gr11, R12, G12, R13, Gr13, R14, and Gr14 are read out in this order. Next, at times t3 to t4, and at times t1 to t2, the processing of the signals Gb11, B11, Gb12, B12, Gb13, B13, Gb14, and B14 of the pixel circuit 10 in the second row in each electric circuit 20 is performed in parallel. Will be done. Next, at times t4 to t5, the electric circuit 20 to output the signal is sequentially selected. In this example, in the pixel circuit 10 of the second row, the first column and the fg1 column are read from the e1 column so that the column numbers increase in order. That is, the signals Gb11, B11, Gb12, B12, Gb13, B13, Gb14, and B14 are read out in this order. Similarly, at times t5 to t6, the signal processing of the pixel circuit 10 in the third row is performed in parallel, and at times t6 to t7, the signal output of the pixel circuit 10 in the third row is output from the e1 column. , The column numbers are sequentially increased. At times t7 to t8, the signal processing of the pixel circuit 10 in the a4th row is performed in parallel, and at times t8 to t9, the signal output of the pixel circuit 10 in the a4th row is output from the e1 column to the column. It is performed sequentially so that the numbers increase in order.

In this way, when the signals corresponding to the pixel circuits 10 in the same row are read out in the order of the columns, the signals corresponding to the pixel circuits 10 in the same row can be processed in parallel. In this case, mainly as described in the first embodiment, the order in which the four columns of the pixel circuit 10 are arranged and the order in which the four rows of the corresponding electric circuit 20 are arranged are aligned, so that the electric circuit is arranged. The influence of the characteristic difference of 20 can be reduced.

When reading the data corresponding to the plurality of pixel circuits 10 as in the eighth embodiment, the data of the pixel circuits 10 in the same row (for example, the a1 row) is input to a plurality of columns (for example, the v-th column and the w-th column). Read from the electric circuit 20 of. Then, after that, the data of the pixel circuit 10 of another row (for example, the second row) is read out. By doing so, the data of the pixel circuit 10 can be output for each line of the pixel circuit 10, so that data transmission and image processing can be performed at high speed and efficiently.

When the connection form as in the second embodiment is adopted, the pixel circuits 10 are connected so that the data of the pixel circuits 10 in the same row (for example, the first row) are output in the column order of the pixel circuits 10. Data may be output from the appropriate electric circuit 20.

(9th Embodiment)
A ninth embodiment will be described with reference to FIG. The points that may be the same as those of other embodiments will be omitted. The ninth embodiment is a modification of the eighth embodiment. 13 (a) shows the connection relationship between the pixel circuit 10 and the electric circuit 20 as in FIG. 12 (a), and FIG. 13 (b) shows the output from the electric circuit 20 as in FIG. 12 (b). Explaining.

The ninth embodiment is different from the eighth embodiment in that two outputs from the electric circuit 20 are provided as shown in FIG. 13 (a). The output destinations from the electric circuits 20 of the pth line and the qth line and the output destinations from the electric circuits 20 of the rth line and the sth line are different. Regarding the electric circuit 20 in the same row, the output destination of the electric circuit 20 may be the same in the v-th column and the w-th column, or may be different, and is the same in this example.

FIG. 13B shows the timing of signal processing in the electric circuit 20 and signal output from the electric circuit 20. The signal processing at the times t1 to t2 and the time t3 to t4 is the same as that of the eighth embodiment. At times t2 to t3, first, for the electric circuit 20 in the vth column, the signal output from the electric circuit 20 in the pth row and the signal output from the electric circuit 20 in the rth row are performed in parallel. Next, the signal output from the electric circuit 20 in the qth row and the signal output from the electric circuit 20 in the sth row are performed in parallel. In the latter half of the time t2 to t3, the signal output from the electric circuit 20 in the qth row and the signal output from the electric circuit 20 in the s row are performed in parallel for the electric circuit 20 in the wth column. Next, the signal output from the electric circuit 20 in the qth row and the signal output from the electric circuit 20 in the sth row are performed in parallel. As a result, the time t2 to t3 required to output the signal for one line of the pixel circuit 10 can be shortened as compared with the eighth embodiment. As a result, high-speed signal output becomes possible, and imaging with a high frame rate becomes possible.

(10th Embodiment)
The tenth embodiment will be described with reference to FIG. The points that may be the same as those of other embodiments will be omitted. The tenth embodiment is a modification of the ninth embodiment. 14 (a) shows the connection relationship between the pixel circuit 10 and the electric circuit 20 as in FIG. 13 (a), and FIG. 14 (b) shows the output from the electric circuit 20 as in FIG. 13 (b). Explaining.

The output destination from the electric circuit 20 in the p-th row and the output destination from the electric circuit 20 in the q-th row are different. The output destination from the electric circuit 20 in the r-th row and the output destination from the electric circuit 20 in the s-th row are different. The output destinations from the electric circuit 20 in the p-th row and the r-th row are the same, and the output destinations from the electric circuit 20 in the q-th row and the s-th row are the same. Regarding the electric circuit 20 in the same row, the output destination of the electric circuit 20 may be the same in the v-th column and the w-th column, or may be different, and is the same in this example.

FIG. 14B shows the timing of signal processing in the electric circuit 20 and signal output from the electric circuit 20. The signal processing at the times t1 to t2 and the times t3 to t4 is the same as that of the ninth embodiment. At times t2 to t3, first, for the electric circuit 20 in the vth column, the signal output from the electric circuit 20 in the pth row and the signal output from the electric circuit 20 in the qth row are performed in parallel. Next, the signal output from the electric circuit 20 in the r-th row and the signal output from the electric circuit 20 in the s-th row are performed in parallel. In the latter half of the time t2 to t3, the signal output from the electric circuit 20 in the pth row and the signal output from the electric circuit 20 in the qth row are performed in parallel for the electric circuit 20 in the wth column. Next, the signal output from the electric circuit 20 in the r-th row and the signal output from the electric circuit 20 in the s-th row are performed in parallel. As a result, high-speed signal output becomes possible, and image pickup with a high frame rate becomes possible, which is the same as that of the ninth embodiment.

In the ninth embodiment, the signals of the pixel circuits 10 in the adjacent rows are output at different timings in any combination of the two rows. For example, paying attention to the set of the signal R11 and the signal Gr11, both are output at different timings, and even if the set of the signal Gr11 and the signal R12 is paid attention to, both are output with different timings. On the other hand, in the tenth embodiment, the signal of the pixel circuit 10 in the adjacent row is output at the same time (for example, the signal R11 and the signal Gr11), and the signal of the pixel circuit 10 in the adjacent row is output at different timings. (For example, signal Gr11 and signal R12) are mixed. Therefore, in the pixel circuit 10, there may be a set of columns having a large output difference between adjacent columns and a set of columns having a small output difference. If the factor that the output fluctuates on the time axis such as jitter is relatively large, it is preferable to output as in the ninth embodiment to reduce the variation in the output timing of the adjacent column.

Focusing on two signals continuously output from the same output system in the tenth embodiment, the distance between the pixel circuits 10 corresponding to any of the two signals is uniform. For example, the signals R11, R12, R13, and R14 are signals of every other line of the pixel circuit 10. On the other hand, in the ninth embodiment, paying attention to two signals continuously output from the same output system, the intervals of the pixel circuits 10 corresponding to the two signals are different. For example, the signal R11 and the signal Gr11 are signals of the pixel circuit 10 in the adjacent row, while the signal Gr11 and the signal R13 are signals of the pixel circuit 10 separated by two rows. Therefore, if the output characteristics are different for each output system, the output difference will be different for each column of the adjacent pixel circuits 10. If the characteristic difference of the output system is relatively large, it is preferable to output as in the tenth embodiment to reduce the variation in the output difference of the adjacent columns. Further, when processing the data output from the semiconductor device APR, the algorithm can be optimized by processing using the data of the adjacent pixels. Therefore, rather than continuously outputting the data of the separated pixels such as the signal Gr11 and the signal R13 of the ninth embodiment, the data of the adjacent pixels such as the signal Gr11 and the signal Gr12 of the tenth embodiment are continuously output. It is preferable to output.

(11th Embodiment)
The eleventh embodiment is an embodiment common to the first to tenth embodiments, but is particularly suitable for the ninth embodiment or the tenth embodiment.

FIG. 15 shows the layout of the chip 2. FIG. 15 shows the electric circuit 20 of the first line, the q1 line, the r1 line, the s1 line, the p2 line, the q2 line, and the s2 line. The electric circuits 20 are arranged in the v-th column, the w-th column, and the x-th column. Here, s1 <q1 <r1 <s1 <p2 <q2 <s2. Each of the electric circuits 20 is connected to one of the plurality of pixel groups 15 schematically shown. As described in the first embodiment in the eleventh embodiment, the column number of the corresponding electric circuit 20 increases as the column number of the pixel group 15 increases.

In the eleventh embodiment, a plurality of readout circuits 441 and 442 are provided so as to sandwich the plurality of rows of the electric circuit 20 in the direction in which the rows of the electric circuit 20 are arranged. The output signal of the electric circuit 20 is input to the read circuits 441 and 442. The signals read by the read circuits 441 and 442 are transferred to the interface circuits 451 and 452, converted into a predetermined data format by the interface circuits 451 and 452, and output from the semiconductor device. The interface circuits 451 and 452 can include interface circuits such as a parallel-serial converter and a low voltage differential signaling (LVDS).

The electric circuit 20 of the first line, the r1 line, the p2 line, and the s2 line is connected to the read circuit 441 on the upper side. The electric circuit 20 of the q1st row, the s1st row, and the q2th row is connected to the lower read circuit 442. As a result, signals from a plurality of lines of the electric circuit 20 can be output in parallel. For example, the signal output from the electric circuit 20 on the first line and the signal output from the electric circuit 20 on the q1 line can be performed in parallel.

(12th Embodiment)
A twelfth embodiment will be described with reference to FIG. The points that may be the same as those of other embodiments will be omitted. The twelfth embodiment is a modification of the eleventh embodiment. In the twelfth embodiment, the electric circuit 20 in rows p1, q1, r1, and s1 is connected to the pixel group 15 in the odd-numbered columns, and the electric circuit 20 in the rows p2, q2, and s2 is connected to the pixel group 15 in the even-numbered columns. It is connected to the. For the first, q1, r1, and s1 rows, the column number of the corresponding electric circuit 20 increases as the column number (odd number column) of the pixel group 15 increases. For the p2, q2, and s2 rows, the column number of the corresponding electric circuit 20 increases as the column number (even column) of the pixel group 15 increases. In the present embodiment, the electric circuit 20 in the rows p1 to s1 is connected to the upper read circuit 441, and the electric circuit 20 in the rows p2 to s2 is connected to the lower read circuit 442. In the eleventh embodiment, the output line connected to the electric circuit 20 and the read circuit 441 intersects with the output line connected to the electric circuit 20 and the read circuit 442. On the other hand, in the twelfth embodiment, the output line connected to the electric circuit 20 and the read circuit 441 and the output line connected to the electric circuit 20 and the read circuit 442 do not have to intersect. Therefore, the wiring structure 22 provided with the output line can be simplified, the cost can be reduced, and the unfavorable influence on data transmission such as crosstalk can be reduced.

(13th Embodiment)
The thirteenth embodiment will be described with reference to FIG. The points that may be the same as those of other embodiments will be omitted. The thirteenth embodiment may be combined with the first to twelfth embodiments, and may be particularly combined with the eleventh embodiment and the twelfth embodiment. FIG. 17 shows the layout of the chip 2. A plurality of scanning circuits 461 and 462 are provided so as to sandwich the plurality of rows of the electric circuit 20 in the direction in which the rows of the electric circuit 20 are arranged. A scanning circuit 463 is provided between the plurality of rows of the electric circuit 20 and the outer edge of the chip 2 in the direction in which the rows of the electric circuits 20 are arranged. In this example, the read circuit 441 is arranged between the scanning circuit 461 and the outer edge of the chip 2, but the scanning circuit 461 may be arranged between the reading circuit 441 and the outer edge of the chip 2. Although the read circuit 442 is arranged between the scanning circuit 462 and the outer edge of the chip 2, the scanning circuit 462 may be arranged between the reading circuit 442 and the outer edge of the chip 2.

The scanning circuits 461 and 462 are connected to the electric circuit 20, and perform scanning for selecting the column to which the electric circuit 20 to output the signal belongs from the plurality of electric circuits 20. The scanning circuit 463 is connected to the electric circuit 20, and selects the line to which the electric circuit 20 to output the signal belongs from the plurality of electric circuits 20. A signal is read from the electric circuit 20 selected by the scanning circuits 461 and 462 and the scanning circuit 463 to the reading circuits 441 and 442. The scanning circuits 461, 462, and 463 can be configured by a decoder and a shift register. A drive circuit 47 is provided between the plurality of rows of the electric circuit 20 and the outer edge of the chip 2 in the direction in which the rows of the electric circuits 20 are lined up. The drive circuit 47 supplies power to each of the plurality of electric circuits 20 to drive the electric circuit 20.

The signal generation circuit 48 is, for example, a part of the signal generation circuit 290 described with reference to FIG. 9, and generates a synchronization signal CLK and a reference signal REF and supplies them to the electric circuit 20. The signal generation circuit 48 can also generate a synchronization signal or a reference signal supplied to a circuit other than the comparison circuit 260 of the electric circuit 20 and supply it to the electric circuit 20.

(14th Embodiment)
When the size of the chip 2 is larger than, for example, 33 mm, when the chip 2 is manufactured, the exposure in photolithography may be divided into a plurality of exposure regions for exposure (divided exposure). preferable. The dimension referred to here may be the width in the direction in which the rows of the electric circuits 20 are lined up. In particular, when the chip 2 is exposed by an ArF exposure apparatus (which may be immersion), split exposure is suitable. When performing split exposure, it is preferable to set the boundary of a plurality of exposure regions at a position between the plurality of electric circuits 20 so that one electric circuit 20 is not divided. Typically, the boundary of the exposed area is near the center of the chip 2. The wiring for connecting the electric circuit 20 and the readout circuits 441, 442, the scanning circuits 461, 462, 463, the drive circuit 47, and the signal generation circuit 48 described in the eleventh to thirteenth embodiments is wired in the chip 2. It is a global wiring with a long length. In the split exposure, it is preferable to perform the joint exposure so that the resist pattern corresponding to the global wiring is connected. Since these global wirings are driven with low impedance, the influence on the output characteristics is small even if the joint exposure is performed. On the other hand, since the interface circuits 451 and 452 operate at a higher frequency than these global wirings, it is not preferable to connect them to the interface circuits 451 and 452 by connecting exposure. Therefore, as shown in FIGS. 15 to 17, it is preferable that the interface circuits 451, 452 are separated from the vicinity of the center where the boundary of the exposure region is located. For example, if U is an even number, the interface circuit 451 is located between the U / 2nd row electric circuit 20 and the outer edge of the chip 2 in the U row electric circuit 20 in the direction in which the electric circuit 20 rows are lined up. , 452 are preferably not arranged. If U is an odd number, it is preferable that the interface circuits 451 and 452 are not arranged between the electric circuit 20 in the second row (U + 1) / 2 and the outer edge of the chip 2 in the direction in which the rows of the electric circuits 20 are arranged. In the examples of FIGS. 15 and 16, U is 3, and in the direction in which the rows of the electric circuits 20 are arranged, the interface circuits 451 and 452 are not arranged on the outer edge of the w row corresponding to the second row and the chip 2. .. The interface circuits 451 and 452 are arranged between the v-th row or the x-th row and the outer edge of the chip 2.

(15th Embodiment)
The thirteenth embodiment will be described with reference to FIG. The points that may be the same as those of other embodiments will be omitted. FIG. 18 shows the layout of the circuit of the chip 2 as in FIGS. 15 and 16.

In the fifteenth embodiment, the readout circuits 443 and 444 are arranged between a part of the electric circuits 20 arranged in a matrix and a part of the electric circuits 20 arranged in a matrix. This makes it possible to output more data at the same time. For example, the data of the first color pixel can be read from the read circuit 441, the data of the second color pixel can be read from the read circuit 442, and the data of the fourth color pixel can be read from the 443 and 443. Alternatively, the read circuit 441 and the read circuit 442 can read the data of the first color pixel, the read circuit 443 can read the data of the second color pixel, and the read circuit 444 can read the data of the third color pixel. ..

(16th Embodiment)
The sixteenth embodiment will be described with reference to FIG. The points that may be the same as those of other embodiments will be omitted. FIG. 19A is a planar layout of the chip 1, and a plurality of pixel circuits 10 are connected to a common scanning line 50 for each row. The scanning line 50 commonly supplies a transfer signal TX such as the signal PTX described in the seventh embodiment, a selection signal SEL such as the signal PSEL, and a reset signal RES such as the signal PRESS to a plurality of pixel circuits 10 on the same line. The transfer signal TX, the selection signal SEL, and the reset signal RES are collectively referred to as a scanning signal.

FIG. 19B is a planar layout of the chip 2. Scanning circuits 401, 402, and 403 are arranged on the chip 2. The scanning circuit 401 is arranged between the plurality of electric circuits 20 in the direction in which the rows of the electric circuits 20 are lined up. The scanning circuits 402 and 403 are arranged between the electric circuit 20 of Fukunest and the outer edge of the chip 2 in the direction in which the rows of the electric circuits 20 are lined up. At least one of the scanning circuits 401, 402, and 403 may be provided on the chip 2. It should be noted that any of the scanning circuits 401, 402, and 403 can be provided on the chip 1 without being provided on the chip 2.

The scanning circuits 401, 402, and 403 are connected to the conductive portion 23, and the scanning line 50 is connected to the conductive portion 13. The scanning circuits 401, 402, and 403 are connected to the scanning line 50 via the conductive portions 23 and 13, and supply the above-mentioned scanning signal to the scanning line 50.

The pixel circuits 10 in rows e1 to e5 are connected to the scanning line 50. The scanning line 50 has a central portion 51, a portion 52 at one end, and a portion 53 at the other end. A plurality of pixel circuits 10 are connected to both sides of the central portion 51. For example, the portion 51 is located between a portion where the pixel circuit 10 in the second row is connected to the scanning line 50 and a portion where the pixel circuit 10 in the fourth row is connected to the scanning line 50. Alternatively, the portion 51 is located between the portion where the pixel circuit 10 in the first row is connected to the scanning line 50 and the portion where the pixel circuit 10 in the e5 row is connected to the scanning line 50. All the pixel circuits 10 in the same row are connected to the portion between the one end portion 52 and the other end portion 53 of the scanning line 50. That is, the pixel circuit 10 is not connected to the portion 52 of the scanning line 50 on the side opposite to the portion 53, and the pixel circuit 10 is connected to the portion 53 of the scanning line 50 on the side opposite to the portion 52. Not connected.

Wiring (including conductive portions 13 and 23) from the scanning circuit 401 is connected to the central portion 51. Within the scan line 50, the position of the portion 51 to which the scan circuit 401 is connected is between the two rows of the pixel circuit 10. As a result, the portion 51 is scanned into the pixel circuits 10 in rows e1 and e2 located on one side of the portion 51 and the pixel circuits 10 in rows e4 and e5 located on the other side of the portion 51. Supply a signal. As a result, the pixel circuit 10 farthest from the portion of the scanning line 50 to which the scanning signal is supplied, as compared with the case where the scanning signal is supplied to only one of the one end portion 52 and the other end portion 53 of the scanning line 50. The distance to can be reduced. Therefore, the delay of the scanning signal in the farthest pixel circuit 10 can be reduced, and high-speed reading from the pixel circuit 10 becomes possible. Therefore, it is possible to reduce the delay in selecting, processing, and outputting signals in parallel in the plurality of electric circuits 20, and improve the performance of the electric circuits 20.

In this example, the scanning circuit 402 is connected to the portion 52 via the conductive portions 13 and 23, and the scanning circuit 402 also supplies the scanning signal synchronized with the scanning circuit 401 to the scanning line 50. Further, the scanning circuit 403 is connected to the portion 53 via the conductive portions 13 and 23, and the scanning signal synchronized with the scanning circuit 401 is also supplied to the scanning line 50 from the scanning circuit 403. In this case, the read operation of the pixel circuit 10 can be made faster. The scanning circuit 401 may be omitted, and the scanning signal may be supplied from the scanning circuit 402 and the scanning circuit 403 to the portions 52 and 53. Further, the scanning circuit 401 may be omitted, and the scanning signal may be supplied from the scanning circuit 402 and / or the scanning circuit 403 to the portion 51. However, in order to improve the delay of the scanning signal, it is preferable to connect the scanning circuit 401 to the portion 51.

(17th Embodiment)
The 17th embodiment will be described with reference to FIG. The 17th embodiment includes an example and a modification of the 16th embodiment. The description of other embodiments, in particular, which may be the same as those of the 16th embodiment, will be omitted.

The first example shown in FIG. 20 (a) corresponds to the perspective view of the 17th embodiment.

In the second example shown in FIG. 20 (b), the scanning circuits 402 and 403 are omitted, and the scanning circuit 401 is connected to the central portion (corresponding to the portion 51) of the scanning line 50.

In the third example shown in FIG. 20 (c), the scanning circuits 402 and 403 are provided on the chip 1. A plurality of pixel circuits 10 are located between the scanning circuit 402 and the scanning circuit 403 in the direction in which the rows of the pixel circuits 10 are arranged. In other words, the scanning circuits 402 and 403 are located between the plurality of pixel circuits 10 and the outer edge of the chip 1 in the direction in which the rows of the pixel circuits 10 are lined up. By doing so, the distance between the scanning circuits 402 and 403 and the scanning line 50 of the chip 1 can be shortened, so that the driving of the pixel circuit 10 can be speeded up.

In the fourth example shown in FIG. 20 (d), the scanning line 50 is arranged not on the chip 1 but on the chip 2. That is, the scanning line 50 is a global wiring composed of a wiring layer included in the wiring structure 22 of the chip 2. Then, the central portion (corresponding to the portion 51) of the scanning line 50 provided on the chip 2 is connected to each of the plurality of pixel circuits 10 via the conductive portions 13 and 23 (not shown). In such a form, the number of the conductive portions 13 and 14 is required to be several times the number of the pixel circuits 10 (depending on the number of types of scanning signals). Therefore, the semiconductor device APR may become complicated and the cost may increase. Therefore, the scanning line 50 is preferably provided in the wiring structure 12 of the chip 1.

(18th Embodiment)
The eighteenth embodiment will be described with reference to FIG. 21. The points that may be the same as those of other embodiments will be omitted. The eighteenth embodiment is a form common to the first to seventeenth embodiments. The eighteenth embodiment relates to the connection between the conductive portion 13 and the conductive portion 23.

FIG. 21A shows a cross-sectional view of the semiconductor device IC. The wiring structure 12 of the chip 1 and the wiring structure 22 of the chip 2 are located between the semiconductor layer 11 of the chip 1 and the semiconductor layer 21 of the chip 2. The wiring structure 12 has M-layer wiring layers 121 and 122. The wiring layers 121 and 122 may be Cu wiring layers. In this example, the wiring layer 122 includes the conductive portion 13. The conductive portion 13 is embedded in a recess formed in the interlayer insulating film and has a damascene structure (dual damascene structure in this example). The wiring structure 22 has N layers of wiring layers 221, 222. The number of wiring layers (N) of the wiring structure 22 may be larger than the number of wiring layers (M) of the wiring structure 12 (M> N). By doing so, the cost of the semiconductor device APR can be reduced while improving the performance of the pixel circuit 10 and the electric circuit 20. The wiring layers 221 and 222 can be Cu wiring layers. In this example, the wiring layer 222 includes the conductive portion 23. The conductive portion 23 is embedded in a recess formed in the interlayer insulating film and has a damascene structure (dual damascene structure in this example). The conductive portion 13 and the conductive portion 23 are joined to each other. An interlayer insulating film having a recess in which the conductive portion 13 is embedded and an interlayer insulating film having a recess in which the conductive portion 23 is embedded are also bonded (contacted). Due to the positional deviation between the conductive portion 13 and the conductive portion 23, the difference in dimensions, and the like, the conductive portion 13 faces an interlayer insulating film having a recess in which the conductive portion 23 is embedded. The conductive portion 23 faces an interlayer insulating film having a recess in which the conductive portion 13 is embedded. The contact surfaces of the conductive portions 13 and 23 and the interlayer insulating film are shown by the joint surface 30. According to this example, since the dimensions of the conductive portions 13 and 23 can be reduced, many connection portions between the pixel circuit 10 and the electric circuit 20 can be provided, and more pixel circuits 10 can be processed in parallel by the plurality of electric circuits 20. can do.

The semiconductor layer 11 is provided with a charge detection unit 605 for the photoelectric conversion element 601 via a transfer transistor 603. The chip 1 has a back-illuminated light-receiving structure. The conductive portion 13 is connected to the semiconductor element of the pixel circuit 10 via the wiring layer 121. The semiconductor element of the pixel circuit 10 to which the conductive portion 13 is connected is, for example, a transistor, but may be a diode, a resistor, or a capacitance. In this example, the conductive portion 13 is connected to the selection transistor 608. The semiconductor layer 11 is provided with a charge detection unit 605 for the photoelectric conversion element 601 via a transfer transistor 603. The conductive portion 23 is connected to the semiconductor element of the electric circuit 20 via the wiring layer 221. The semiconductor element of the electric circuit 20 to which the conductive portion 23 is connected is, for example, a transistor, but may be a diode, a resistor, or a capacitance. In this example, the conductive portion 23 is connected to the selection circuit 240. The transistor used in the electric circuit 20 may have a silicide layer such as cobalt silicide or nickel silicide. Further, the gate electrode may be a metal gate, and the gate insulating film may be a high-k insulating film. The transistor used in the electric circuit 20 may be a planar MOSFET or a Fin-FET. The thickness of the gate insulating film of the transistor provided on the semiconductor layer 21 may be of a plurality of types. A transistor having a thick gate insulating film is used in a circuit such as a power supply system or an analog system that requires high withstand voltage, and a transistor having a thin gate insulating film is used in a circuit such as a digital system that requires high speed. The semiconductor layer 11 is about 1 to 10 μm, and the semiconductor layer 21 can be about the same as the semiconductor layer 11 or thicker than the semiconductor layer 11. The thickness of the semiconductor layer 11 is, for example, 50 to 800 μm.

FIG. 21B also shows a cross-sectional view of the semiconductor device APR. The example shown in FIG. 21 (b) differs from the example of FIG. 21 (a) in that the conductive portion 13 and the conductive portion 23 are not in contact with each other. The conductive portion 13 faces an interlayer insulating film having a recess in which the conductive portion 23 is embedded. The interlayer insulating film having the recess in which the conductive portion 13 is embedded and the interlayer insulating film having the recess in which the conductive portion 23 is embedded are also separated from each other. A bump 33 that comes into contact with both the conductive portion 13 and the conductive portion 23 is provided. The bump 33 needs to have a size of about several uμ to several tens of uμ, but in the above-described first to 18 embodiments, the number of electric circuits 20 can be reduced from the number of pixel circuits 10, so the bump 33 is used. However, a certain level of performance can be obtained.

FIG. 21C also shows a cross-sectional view of the semiconductor device APR. The example shown in FIG. 21 (b) differs from the example of FIG. 21 (a) in that the conductive portion 13 and the conductive portion 23 are not in contact with each other. An adhesive layer 34 for adhering an interlayer insulating film between the wiring structure 12 and the wiring structure 22 is provided. The joint surface 30 of the adhesive layer 34 is a contact surface between the adhesive layer on the wiring structure 12 side and the adhesive layer on the wiring structure 22 side. The conductive portion 13 and the conductive portion 23 are connected by a through electrode 35 penetrating the semiconductor layer 21. In this example, since the through electrode is provided on the semiconductor layer 21 instead of the semiconductor layer 11, the through electrode 35 does not hinder the integration of the pixel circuit 10, and the damage to the semiconductor layer 11 can be suppressed. can. However, since the through electrode 35 can hinder the integration of the electric circuit 20, it is desirable to adopt the example of FIG. 21A described above.

(19th Embodiment)
As the nineteenth embodiment, the device EQP shown in FIG. 1 (a) will be described in detail. The semiconductor device APR may include a package PKG accommodating the semiconductor device IC in addition to the semiconductor device IC which is a laminate of the chips 1 and 2. The package PKG is a bonding wire or bump that connects a substrate on which a semiconductor device IC is fixed, a lid such as glass facing the semiconductor device IC, and a terminal provided on the substrate and a terminal provided on the semiconductor device IC. And the like, and may include.

The equipment EQP may further include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, and a storage device MMRY. The optical system OPT is an image formed on a semiconductor device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the semiconductor device APR, and is a semiconductor device such as an ASIC. The processing device PRCS processes the signal output from the semiconductor device APR, and is a semiconductor device such as a CPU or an ASIC for forming an AFE (analog front end) or a DFE (digital front end). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device APR. The storage device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device APR. The storage device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCNH has a moving part or a propulsion part such as a motor or an engine. In the device EQP, the signal output from the semiconductor device APR is displayed on the display device DSPL, or transmitted to the outside by a communication device (not shown) included in the device EQP. Therefore, it is preferable that the device EQP further includes a storage device MMRY and a processing device PRCS in addition to the storage circuit unit and the arithmetic circuit unit of the semiconductor device APR.

The device EQP shown in FIG. 1 (a) can be an electronic device such as an information terminal (for example, a smartphone or a wearable terminal) or a camera (for example, an interchangeable lens camera, a compact camera, a video camera, a surveillance camera) having a shooting function. .. The mechanical device MCHN in the camera can drive the components of the optical system OPT for zooming, focusing, and shutter operation. Further, the device EQP may be a transport device (mobile body) such as a vehicle, a ship, or a flying object. The mechanical device MCHN in the transportation equipment can be used as a mobile device. The device EQP as a transport device is suitable for transporting a semiconductor device APR and for assisting and / or automating operation (maneuvering) by a photographing function. The processing device PRCS for assisting and / or automating the operation (maneuvering) can perform processing for operating the mechanical device MCNH as a mobile device based on the information obtained by the semiconductor device APR.

The semiconductor device APR according to the embodiment described above can provide high value to its designer, manufacturer, seller, purchaser and / or user. Therefore, if the semiconductor device APR is mounted on the device EQP, the device EQP value can be increased. Therefore, in manufacturing and selling the device EQP, it is advantageous to decide to mount the semiconductor device APR of the present embodiment on the device EQP in order to increase the value of the device EQP.

The embodiments described above can be appropriately changed as long as they do not deviate from the technical idea. It should be noted that the disclosure content of the embodiment includes not only what is specified in the present specification but also all matters that can be grasped from the present specification and the drawings attached to the present specification. Further, the configurations having the same name but different reference numerals can be distinguished as the first configuration, the second configuration, the third configuration, and the like.

APR semiconductor device 1 chip 10 pixel circuit 2 chip 20 electric circuit

One means is to stack a plurality of conductive parts, a first chip in which a plurality of pixel circuits are arranged in a plurality of rows and columns, and a second chip in which a plurality of signal lines and a plurality of electric circuits are arranged. In the semiconductor device, the first signal line among the plurality of signal lines is connected to the pixel circuit in the ath row and the first column, and the first signal line is among the plurality of conductive portions. The second signal line among the plurality of signal lines is connected to the first electric circuit in the plurality of electric circuits via the first conductive portion of the above, and the second signal line in the plurality of signal lines is connected to the pixel circuit in the second row. The two signal lines are connected to the second electric circuit in the plurality of electric circuits via the second conductive portion in the plurality of conductive portions, and the third signal line in the plurality of signal lines is The third signal line is connected to the pixel circuit of the third row, and the third signal line is connected to the third electric circuit in the plurality of electric circuits via the third conductive portion among the plurality of conductive portions, and the plurality of electric circuits are connected to the third electric circuit. The fourth signal line among the signal lines of the above is connected to the pixel circuit of the fourth row, and the fourth signal line is connected to the plurality of electric circuits via the fourth conductive portion of the plurality of conductive portions. The second signal line and the third signal line are connected to the fourth electric circuit in the circuit, and are arranged between the first signal line and the fourth signal line, and the direction along the ath line. The first virtual line extending in the above passes through the first conductive portion and the fourth conductive portion, and the second virtual line extending in the direction passes the second conductive portion and the third conductive portion. As you can see, the semiconductor device is characterized in that the length between the first conductive portion and the fourth conductive portion is longer than the length between the second conductive portion and the third conductive portion .

Claims (20)

A semiconductor device in which a first chip in which a plurality of pixel circuits are arranged in a matrix of J rows and K columns and a second chip in which a plurality of electric circuits are arranged in a matrix of T rows and U columns are laminated. And,
Each of the plurality of electric circuits processes the signal generated by the plurality of pixel circuits.
The pixel circuits in the ath row and the first column of the plurality of pixel circuits are connected to the electric circuits in the pth row and the vth column of the plurality of electric circuits.
The pixel circuit in the ath row and the f1 column of the plurality of pixel circuits is connected to the electric circuit in the qth row and the vth column of the plurality of electric circuits.
The pixel circuit in the ath row and the g1 column of the plurality of pixel circuits is connected to the electric circuit in the rth row and the vth column of the plurality of electric circuits.
The pixel circuits in the ath row and the h1 column of the plurality of pixel circuits are connected to the electric circuits in the s row and the vth column of the plurality of electric circuits.
A semiconductor device characterized in that T <J and U <K, f1 and g1 are integers between e1 and h1, and q and r are integers between p and s. The pixel circuit in the b-th row and the e1 column of the plurality of pixel circuits is connected to the electric circuit in the p-th row and the v-th column.
The pixel circuit in the b-th row and the f1 column of the plurality of pixel circuits is connected to the electric circuit in the q-th row and the v-th column.
The pixel circuit in the b-th row and the g1 column of the plurality of pixel circuits is connected to the electric circuit in the r-th row and the v-th column.
The pixel circuit in the b-th row and the h1 column of the plurality of pixel circuits is connected to the electric circuit in the s-th row and the v-th column.
The semiconductor device according to claim 1. The pixel circuits in the c-th row and the second column of the plurality of pixel circuits are connected to the electric circuits in the p-th row and the w-th column of the plurality of electric circuits.
The pixel circuit in the cth row and the f2 column of the plurality of pixel circuits is connected to the electric circuit in the qth row and the wth column of the plurality of electric circuits.
The pixel circuit in the c-th row and the g2 column of the plurality of pixel circuits is connected to the electric circuit in the r-th row and the w-th column of the plurality of electric circuits.
The pixel circuit in the c-th row and the h2 column of the plurality of pixel circuits is connected to the electric circuit in the s-th row and the w-th column of the plurality of electric circuits.
The semiconductor device according to claim 1 or 2. The pixel circuits in the ath row and the second column of the plurality of pixel circuits are connected to the electric circuits in the pth row and the wth column.
The pixel circuit in the ath row and the f2 column of the plurality of pixel circuits is connected to the electric circuit in the qth row and the wth column.
The pixel circuit in the ath row and the g2 column of the plurality of pixel circuits is connected to the electric circuit in the rth row and the wth column.
The pixel circuit in the ath row and the h2 column of the plurality of pixel circuits is connected to the electric circuit in the s row and the wth column.
The semiconductor device according to claim 3. The semiconductor device according to claim 3 or 4, wherein f2 and g2 are integers between e2 and h2. The semiconductor device according to any one of claims 1 to 5, wherein e1 <f1 <g1 <h1 and p <q <r <s. The pixel circuits in the ath row and the h1 column of the plurality of pixel circuits are connected to the electric circuits in the s row and the vth column of the plurality of electric circuits.
The pixel circuits in the ath row and the second column of the plurality of pixel circuits are connected to the electric circuits in the s row and the wth column of the plurality of electric circuits.
The pixel circuits in the ath row and the f2 column of the plurality of pixel circuits are connected to the electric circuits in the rth row and the wth column of the plurality of electric circuits.
The semiconductor device according to claim 1 or 2, wherein g1 <h1 <e2 <f2. The pixel circuits in the ath row and the f2 column of the plurality of pixel circuits are connected to the electric circuits in the rth row and the wth column of the plurality of electric circuits.
The pixel circuit in the ath row and the g2 column of the plurality of pixel circuits is connected to the electric circuit in the qth row and the wth column of the plurality of electric circuits.
The pixel circuits in the ath row and the h2 column of the plurality of pixel circuits are connected to the electric circuits in the pth row and the wth column of the plurality of electric circuits.
The semiconductor device according to claim 1 or 2, wherein e1 <f1 <g1 <f2 <g2 <h2. The pixel circuits in the ath row and the h2 column of the plurality of pixel circuits are connected to the electric circuits in the pth row and the wth column of the plurality of electric circuits.
The pixel circuits in the ath row and the third column of the plurality of pixel circuits are connected to the electric circuits in the pth row and the xth column of the plurality of electric circuits.
The pixel circuit in the ath row and the f3 column of the plurality of pixel circuits is connected to the electric circuit in the qth row and the xth column of the plurality of electric circuits.
The semiconductor device according to claim 7 or 8, wherein f2 <h2 <e3 <f3, v <w <x. The pixel circuit in the c-th row and the e1 column of the plurality of pixel circuits is connected to the electric circuit in the p2 row and the v-th column of the plurality of electric circuits.
The pixel circuit in the c-th row and the f1 column of the plurality of pixel circuits is connected to the electric circuit in the q2 row and the v-th column of the plurality of electric circuits.
The pixel circuit of the cth row and the g1 column of the plurality of pixel circuits is connected to the electric circuit of the r2 row and the vth column of the plurality of electric circuits.
The c-th row and h1 column pixel circuits of the plurality of pixel circuits are connected to the s2nd row and v-th column electric circuits of the plurality of electric circuits, according to claim 1 or 2. The semiconductor device described. The semiconductor device according to any one of claims 3 to 5, or claim 7, wherein e2 = h1 + 1. The semiconductor device according to any one of claims 3 to 5, or claim 7, wherein T = e2-e1. The semiconductor device according to any one of claims 1 to 12, wherein J ≦ T × U <J × K / 2. A first output that outputs a signal based on a signal generated by the pixel circuit of the first row and the first column from any of the plurality of electric circuits, and a signal generated by the pixel circuit of the first row and the second column. A second output that outputs a signal based on the above is output from any of the plurality of electric circuits, and a signal based on the signal generated by the pixel circuit of the second row and the first column is output from any of the plurality of electric circuits. The semiconductor device according to any one of claims 1 to 13, wherein the third output and the third output are performed in this order. One of claims 1 to 14, wherein in parallel with the first output, a signal based on the signal generated by the pixel circuit in the first row and the f1 column is output from any of the plurality of electric circuits. The semiconductor device described in. In the direction in which the rows of the plurality of electric circuits are lined up, signals output from two or more of the plurality of electric circuits are generated between the plurality of electric circuits and the first side of the second chip. The first read circuit to be input is arranged, and
In the direction in which the rows of the plurality of electric circuits are lined up, signals output from two or more electric circuits of the plurality of electric circuits are generated between the plurality of electric circuits and the second side of the second chip. The semiconductor device according to any one of claims 1 to 15, wherein a second readout circuit to be input is arranged. The width of the second chip in the direction in which the rows of the plurality of electric circuits are lined up is larger than 33 mm, and the second chip has an interface circuit.
The U is an even number, and the interface circuit is not arranged between the electric circuit in the U / 2 row of the plurality of electric circuits and the outer edge of the first chip, or.
Claims 1 to 1 to claim 1, wherein U is an odd number, and the interface circuit is not arranged between the electric circuit in the (U + 1) / 2 row of the plurality of electric circuits and the outer edge of the second chip. 16. The semiconductor device according to any one of 16. The semiconductor device according to any one of claims 1 to 17, wherein each of the plurality of electric circuits includes an analog-to-digital converter. The semiconductor device according to claim 18, wherein the analog-to-digital converter is a sequential comparison type analog-to-digital converter. The semiconductor device according to any one of claims 1 to 19 is provided.
An optical system that forms an image on the semiconductor device, a control device that controls the semiconductor device, a processing device that processes a signal output from the semiconductor device, and a mechanical device that is controlled based on information obtained by the semiconductor device. A device further comprising at least one of a display device for displaying information obtained by the semiconductor device and a storage device for storing information obtained by the semiconductor device.

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