JP2022029664A - Game machine - Google Patents

Abstract

To provide a game machine in which a performance control operation is further improved.SOLUTION: A display device DS1 includes a display driving circuit MONI which drives a group of display elements constituting a display screen, and an illumination circuit BL which illuminates the display screen. After a lapse of a predetermined stand-by time following a power activation, a power source voltage of the display driving circuit MONI is supplied.SELECTED DRAWING: Figure 6

Description

The present invention relates to a gaming machine that performs a lottery process due to a gaming operation and executes an image effect corresponding to the lottery result, and more particularly to a gaming machine that can stably execute a powerful image effect.

A ball game machine such as a pachinko machine is equipped with a symbol start opening provided on the game board, a symbol display unit that displays a series of symbol variation modes by a plurality of display symbols, and a large winning opening for opening and closing the opening / closing plate. It is composed of. Then, when the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is set, and after the game ball is paid out as the prize ball, the displayed symbol is changed for a predetermined time on the symbol display unit. After that, when the symbol is stopped in a predetermined mode such as 7, 7, 7, a big hit state is reached, and the big winning opening is repeatedly opened to generate a game state advantageous to the player.

Whether or not to generate such a game state is determined by a big hit lottery executed on the condition that the game ball wins at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in the winning state, an effect operation called a reach action or the like is executed for about 20 seconds, and then special symbols are arranged. On the other hand, the same reach action may be executed even in the case of a lost state, and in this case, the player pays close attention to the transition of the production operation while strongly paying attention to the big hit state. Then, if the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

Such a symbol variation operation is usually performed on a liquid crystal display. A liquid crystal display is generally composed of a liquid crystal display unit MONI that realizes color display of the three primary colors RGB, and a backlight unit BL that emits light from an LED on the back side of the liquid crystal display unit. Generally, the liquid crystal display unit MONI is composed of pixels of horizontal H dots × vertical V dots, and each pixel of H × V dots is composed of basic pixels of three colors of RGB, and the backlight unit BL. When is lit, the color of each basic pixel is activated.

The drive of each pixel in the liquid crystal display unit is executed in synchronization with the operation clock CK (= dot clock DCK) of the device, and the pixel drive of the H dots corresponding to one horizontal line is the horizontal synchronization signal HS. It is configured to synchronize with the vertical synchronization signal VS and return to the pixel drive of the first line when the drive for the V line is completed (see FIG. 42). Therefore, it is necessary to supply the liquid crystal display unit from the external device together with the horizontal synchronization signal HS, the vertical synchronization signal VS, and the dot clock DCK together with the image signal corresponding to the resolution H × V dots.

Here, in order to smoothly execute the display update operation (frame update) of the liquid crystal display unit, the pulse width of each synchronization signal HS, Vs or between each synchronization signal HS, Vs and the transmission timing of the image signal , Predetermined conditions are required. For example, FIG. 42 (g) illustrates an example of the drive timing condition required in the case of VGA (Video Graphics Array) of 640 × 408 dots.

Under the driving conditions shown in the figure, first, the pulse width PWh of the horizontal synchronization signal HS is 96 pieces of the operating clock CK, and the front pouch FPh and the backport BPh required before and after the horizontal synchronization signal PWh are each. It is defined as 16 operating clocks and 48 operating clocks.

On the other hand, the pulse width PWv of the vertical synchronization signal VS is defined as 2 lines, and the front pouch FPv and the backport BPv required before and after the vertical synchronization signal VS are defined as 19 lines and 33 lines, respectively. Has been done.

Therefore, in this liquid crystal display unit, the operation cycle of the drive operation of one line is 16 + 96 + 48 + 640 lines (= 800) counted by the operation clock CK, and this is repeated for 10 + 2 + 33 + 480 lines (= 525) in the vertical direction. Then, the display for one frame of the display screen will be updated.

The above operation cycle is 800 × 525 pieces counted by the operation clock CK. For example, when the frequency of the operation clock is 25 MHz, the time required for updating one frame is 800 × 525 / (25). × 10 ⁶ ) = 16.8 mS, and the operation cycle is about 1/60 second.

The external control device that controls the liquid crystal display unit includes a horizontal synchronization signal HS that satisfies the above horizontal conditions (PWh, FPh, BPh) and a horizontal synchronization signal HS that satisfies the above vertical conditions (PWvh, FPvh, BPvh). , The image signal corresponding to the number of pixels of the display screen is repeatedly supplied to the liquid crystal display unit.

JP-A-2017-093633 JP-A-2017-093632 Japanese Unexamined Patent Publication No. 2016-159030 Japanese Unexamined Patent Publication No. 2016-159029

By the way, in this kind of gaming machine, there is a high demand for complicated and abundant various effects, especially for image effects using a liquid crystal display. Therefore, although the applicant has made various proposals (Cited Documents 1 to 4), further sophistication of image production and further improvement of various production control operations centered on image production control have been made. This is where it is desired. Further, it is desired to improve the driving operation of the liquid crystal display so that the control load of the image effect control can be reduced. Further, it is also necessary to ensure the matching operation of the liquid crystal display unit MONI and the backlight unit BL and take measures to prevent inappropriate display in any case.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine in which various effect control operations centered on image effect control are further improved.

In order to achieve the above object, the gaming machine according to the present invention has an image control means for issuing a drawing list that specifies a display screen of a display device, and drawing that generates image data based on the drawing list in a predetermined storage area. A gaming machine comprising a circuit and an image generation means provided with a display circuit for reading and outputting image data in the storage area, wherein the display device is based on image data received from the image generation means. The image control means is configured to include a display drive circuit (MONI) for driving a group of display elements constituting the display screen and a lighting circuit (BL) for illuminating the display screen, and the image control means is after the power is turned on. After a predetermined standby time, the power supply voltage of the display drive circuit (MONI) is controlled to be supplied.

According to the present invention described above, since the power supply voltage is not supplied to the display drive circuit immediately after the CPU is reset, the image control operation is improved, such as not displaying an unnatural image.

It is a perspective view which shows the pachinko machine of this Example. It is a front view which shows the gaming area of the gaming machine of FIG. It is a block diagram which shows the whole circuit composition of the gaming machine of FIG. It is a drawing explaining the specification of a display device. It is a block diagram explaining the internal structure of a display device. It is a drawing explaining the circuit structure and operation of a power supply control circuit. It is a block diagram which shows the circuit structure of the effect control part in a little detail about the gaming machine of FIG. It is a drawing explaining the composite chip which constitutes the effect control part. It is a block diagram which shows the internal structure of the CPU circuit shown in FIG. The memory map of the built-in CPU (effect control CPU) of the CPU circuit is illustrated. It is a drawing explaining various transfer operation modes (a)-(b) and transfer operation procedure (c)-(e) about DMAC. It is a drawing explaining an index space, an index table, a virtual drawing space, and a drawing area. It is a block diagram which described the internal structure of a data transfer circuit together with the related circuit structure. It is a block diagram which described the internal structure of a display circuit together with the related circuit structure. It is a figure explaining the data valid signal ENAB output from the VDP circuit. It is a flowchart explaining the power reset operation after the CPU reset. It is a flowchart explaining the memory section initialization process which is a part of FIG. It is a flowchart explaining the main introduction process and interrupt process which are a part of FIG. It is a flowchart explaining the initialization process of CGROM which is a part of the main introduction process. It is a flowchart explaining the operation of another embodiment which uses interrupt processing. FIG. 5 is a flowchart illustrating a main introduction process following FIG. 18 and a process up to a steady process. It is a flowchart explaining the steady-state processing following FIG. It is a drawing explaining the structure of a display list. It is a flowchart which shows the DL issue process which issues a display list DL. It is a flowchart explaining the operation when DMAC is involved in the operation of FIG. 24. It is a flowchart explaining the operation following the process of FIG. It is a flowchart explaining the routine process in the case of using a preloader. It is a flowchart explaining a part of FIG. 27. It is a flowchart explaining another part of FIG. It is a time chart which shows the operation of each part of VDP about the Example which does not use a preloader. It is a time chart which shows the operation of each part of VDP about the Example which uses the preloader. It is a block diagram which shows the whole circuit composition about another Example. It is a block diagram which shows a part of FIG. 32 in a little detail. It is a time chart explaining the operation content about another embodiment. It is a drawing explaining still another embodiment. It is a figure explaining an embodiment which sets a setting value repeatedly. It is a drawing explaining the circuit structure of the Example which uses the built-in voice circuit. It is a flowchart explaining the initial setting operation of a voice circuit. It is a figure explaining another embodiment about the power reset operation after a CPU reset. It is a time chart which shows an example of a memory READ operation and a memory WRITE operation. It is a drawing explaining another embodiment. It is a drawing explaining the driving method of a general display device. It is a drawing explaining a display list. It is a drawing explaining a zoom notice. It is a drawing explaining the processing of the CPU for realizing the rotation operation. It is a drawing which shows the basis of the calculation formula. It is a time chart which shows the deformation operation of the backlight part and the liquid crystal display part at the time of power-on. It is a time chart which shows the different deformation operation of the backlight part and the liquid crystal display part at the time of power-on.

Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing the pachinko machine GM of this embodiment. This pachinko machine GM consists of a rectangular frame-shaped wooden outer frame 1 that is detachably attached to an island structure and an inner frame 3 that is pivotally attached so as to be openable and closable via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the inner frame 3 not from the back side but from the front side, and a glass door 6 and a front plate 7 are pivotally attached to the front side thereof so as to be openable and closable. In this specification, the glass door 6 and the front plate 7 are collectively referred to as a front door member. The inner frame 3 in which the front door member (glass door 6 or front plate 7) is pivotally attached may be referred to as a game frame.

Illuminations lamps such as LED lamps are arranged in a substantially C shape on the outer periphery of the glass door 6. On the other hand, a total of three speakers are arranged at the upper left and right positions and the lower side of the glass door 6. The two speakers arranged at the upper part are configured to output the sound of the left and right channels R and L, respectively, and the lower speaker is configured to output the bass sound.

An upper plate 8 for storing a game ball for launch is mounted on the front plate 7, and a lower plate 9 for storing a game ball overflowing or extracted from the upper plate 8 and a launch handle are at the lower part of the inner frame 3. 10 is provided. The launch handle 10 is interlocked with the launch motor, and the game ball is launched by a striking mallet that operates according to the rotation angle of the launch handle 10.

A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and the operation is possible. The button chance state is a game state provided as needed.

Further, a rotary switch type volume switch VLSW is arranged below the chance button 11, and the player operates the volume switch VLSW to change the level from silence level (= 0) to the highest level (= 7). The speaker volume can be adjusted in 8 steps. The volume of the speaker is initially set by a setting switch (not shown) that can be operated only by the staff, and the initial set volume is maintained unless the player operates the volume switch VLSW. In addition, the abnormality notification sound for notifying that an abnormal situation has occurred is emitted at the maximum volume regardless of the initial set volume by the staff or the set volume of the player.

On the right side of the upper plate 8, an operation panel 12 for ball lending operation for a card-type ball lending machine is provided, a frequency display unit that displays the remaining amount of the card as a three-digit number, and a game ball for a predetermined amount. A ball lending switch for instructing lending and a return switch for instructing the return of the card at the end of the game are provided.

As shown in FIG. 2, on the surface of the game board 5, a guide rail 13 composed of an outer rail and an inner rail made of metal is provided in an annular shape, and a central opening HO is provided in the substantially center thereof. A movable effect body (not shown) is stored in a concealed state below the central opening HO, and at the time of the movable notice effect, the movable effect body rises and becomes an exposed state, so that the predetermined reliability is achieved. The notice production is realized. Here, the advance notice effect is an effect of uncertainly notifying the player that a jackpot state advantageous to the player will be invited, and the reliability of the advance notice effect means the probability that the big hit state will be invited.

A main display device DS1 composed of a large (for example, horizontal 1280 x vertical 1024 pixels) liquid crystal color display is arranged in the central opening HO, and a small size (for example, horizontal 480 × vertical) is arranged on the right side of the main display device DS1. A movable sub-display device DS2 composed of a liquid crystal color display (800 pixels) is arranged. The main display device DS1 is composed of a main liquid crystal display unit MONI and an LED backlight unit BL, and is a device that displays a specific symbol related to a big hit state in a variable manner and displays a background image, various characters, and the like in an animated manner. .. The display device DS1 has a special symbol display unit Da to Dc in the central portion and a normal symbol display unit 19 in the upper right portion. Then, in the special symbol display units Da to Dc, a reach effect that is expected to invite a big hit state may be executed, and an appropriate advance notice effect or the like is executed in the special symbol display units Da to Dc and its surroundings.

Normally, the sub-display device DS2 displays image information in a stationary state in which the display screen is tilted at an angle that is easy for the player to see. However, at the time of the predetermined advance notice effect, the predetermined advance notice image is displayed while moving to the left side of the figure while changing the inclination angle to an angle that is easy for the player to see.

That is, the sub-display device DS2 of the embodiment is not only a display device but also functions as a movable effect body for executing a notice effect. Here, the notice effect by the sub-display device DS2 is set with high reliability, and the player pays attention to the moving operation of the sub-display device DS2 with great expectation. The sub display device DS2 is also composed of a sub liquid crystal display unit MONI and an LED backlight unit BL.

By the way, in the game area where the game ball falls and moves, the first symbol start opening 15a, the second symbol start opening 15b, the first big winning opening 16a, the second big winning opening 16b, the normal winning opening 17, and the gate 18 Are arranged. Each of these winning openings 15 to 18 has a detection switch inside, so that the passage of a game ball can be detected.

At the upper part of the first symbol start port 15a, an effect stage 14 configured to be able to win a prize in the first symbol start port 15 is arranged after the game ball entering from the introduction port IN moves in a seesaw shape or a roulette shape. There is. Then, when the game ball wins a prize in the first symbol start opening 15, the special symbol display units Da to Dc are configured to start the variable operation.

The second symbol start port 15b is configured to be opened and closed by an electric tulip equipped with a pair of left and right opening / closing claws, and when the stop symbol after the change of the normal symbol display unit 19 displays a hit symbol, it is predetermined. The opening / closing claws are opened only for a period of time or until a predetermined number of game balls are detected.

The normal symbol display unit 19 displays a normal symbol, and when a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted at the time when the game ball passes through the gate 18. The stop symbol determined by the lottery random value is displayed and stopped.

The first big winning opening 16a is configured to have a slide board that moves forward and backward, and the second big winning opening 16b is configured to have an opening / closing plate whose lower end is pivotally supported and opened forward. .. The operation of the first big winning opening 16a and the second big winning opening 16b is not particularly limited, but in this embodiment, the first big winning opening 16a corresponds to the first symbol starting opening 15a and the second big winning opening. 16b is configured to correspond to the first symbol start port 15b.

That is, when the game ball wins a prize in the first symbol start opening 15a, the variable operation of the special symbol display units Da to Dc is started, and then when the predetermined jackpot symbols are aligned with the special symbol display portions Da to Dc, the first jackpot The barrel special game is started, and the slide board of the first large winning opening 16a is opened forward to facilitate the winning of the game ball.

On the other hand, as a result of the variable motion started by winning the game ball to the second symbol start opening 15b, when a predetermined jackpot symbol is aligned with the special symbol display units Da to Dc, the second jackpot special game is started and the second jackpot is started. The opening / closing plate of the two major winning openings 16b is opened to facilitate the winning of the game ball. The game value of the special game (big hit state) varies depending on the big hit symbols to be aligned, but which game value is given is determined in advance based on the lottery result according to the winning timing of the game ball. It is determined.

In a typical big hit state, the opening / closing plate closes when a predetermined time elapses after the opening / closing plate of the big winning opening 16 is opened, or when a predetermined number (for example, 10) of game balls win a prize. Such an operation is continued up to, for example, 15 times, and is controlled in a state advantageous to the player. If the stop symbol after the change of the special symbol display units Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game is in a high probability state (probability change state). Granted.

FIG. 3A is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes each of the above operations. Further, FIG. 3B is a circuit diagram showing a circuit configuration of the power supply monitor unit MNI arranged on the payout control board 25, and FIG. 3C is a specification of the main display device DS1 used in the present embodiment. It is a drawing explaining.

First, the specifications of the main display device DS1 used in the embodiment will be described with reference to FIG. 3 (c). As described above, this display device DS1 is a liquid crystal color display having a width of 1280 and a height of 1024 pixels, but odd pixels (ODD) and even pixels (EVEN) adjacent to each other in the left-right direction are separately LVDS (Low Voltage). Differential Signaling) It is configured to be received by the receiving unit RV (RVa + RVb) through the transmission path. Therefore, in this embodiment, in correspondence with this dual link specification, the ODD signal is transmitted via the first transmission line LVDS1 and the EVEN signal is transmitted via the second transmission line LVDS2 (). Lower right of FIG. 3 (a)).

Further, in the display device DS1, the operation clock CK (see FIG. 42) that defines the internal operation of the display device DS1 is defined so that its frequency is in the range of 40 MHz to 70 MHz (typical value = 54 MHz). This operating clock CK corresponds to the LVDS clock CLK described later, but in the following, for convenience of explanation, the frequency of the operating clock CK is assumed to be a typical value of 54 MHz. Further, a configuration will be described in which the update time FR (Frame Rate) required for updating an image of one frame in the 54 MHz operating clock CK is matched to approximately 1/60 second.

As its specifications, the display device DS1 has two pixels adjacent to each other in the left-right direction of the display screen based on the ODD signal received from the first transmission line LVDS1 and the EVEN signal received from the second transmission line LVDS2. It is configured to process simultaneously with the operation clock CK of. As a result, the pixel data of 1280 pixels in one horizontal line is updated with an operation time of 640/54 MHz = 11.85 μS, and this operation is repeated for 1024 lines, so that an image of 1280 × 1024 pixels for one frame is obtained. The display will be updated. The image is updated in a non-interlaced manner for each line, such as 1st line → 2nd line ... → 1024th line.

However, as shown in FIG. 3C, as the specifications of the display device DS1, a waiting time (blank period) for 204 clocks is provided in the horizontal direction as a typical value, and a typical value is provided in the vertical direction. Is stipulated to provide a waiting time (blank period) for 42 lines. Therefore, the actual screen update cycle FR considering these blank periods is (204 + 640) × (42 + 1024) / 54 MHz ≈ 16.66 mS in the calculation based on the above-mentioned typical value, so that the frame rate FR is about 1 /. It becomes 60 Hz.

The waiting time WTh in the horizontal direction and the waiting time WTv in the vertical direction each specify an allowable range for a typical value, and in reality, a value different from the above-mentioned typical value can be selected. However, since the frame rate FR = 1/60 second, it is necessary to accurately set the standby time WTh / WTv in the horizontal / vertical direction so that (WTh + 640) × (WTv + 1024) / 54 MHz = 1/60 second. ..

On the other hand, in this display device DS1, reception of the horizontal synchronization signal HS and the vertical synchronization signal VS is particularly unnecessary, while the transmission of the H level data valid signal ENAB is required at the time of transmission of the ODD signal and the EVEN signal. That is, at the timing when a significant signal (ODD / EVEN signal) is transmitted to the transmission lines LVDS1 and LVDS2, the data valid signal ENAB needs to be at the active level (H).

Therefore, in this embodiment, based on the specifications of the main display device DS1 described above, the effect control board 23 and the main display device DS1 are subjected to dual link transmission of the LVDS clock CLK having a frequency of 54 MHz (= 1/2 of the dot clock DCK). LVDS connection is made on the road (FIG. 5, FIG. 14 (a)). Further, in the VDP circuit 52 of the present embodiment, a horizontal blank period WTh and a vertical blank period WTv satisfying the specifications of the main display device DS1 are provided, and when the image data (ODD / EVEN signal) is output, a data valid signal is provided. The ENAB is set to the active level (H level).

That is, as shown in FIG. 4B, the data valid signal ENAB is configured so that only the horizontal display period THd of the horizontal synchronization period TH has an H level. Therefore, the data valid signal ENAB is always at the L level in the vertical synchronization period TV except for the vertical display period TVd. The horizontal blank period WTh and the vertical blank period WTv adopt values different from the respective typical values (WTh = 204 / WTv = 42), but the specific design values are based on FIG. Will be described later.

In any case, the data valid signal ENAB is repeatedly transmitted as a discrete DE signal in each operation cycle of the LVDS clock CLK via the differential signal line RA2 / RB2. The data valid signal ENAB shown in FIGS. 4 (b) and 4 (c) is a demodulated DE signal which is discrete data transmitted by LVDS, and is a continuous discrete DE signal on the time axis. Is. In the differential signal line RA2 / RB, the vertical sync signal VS and the horizontal sync signal HS are also repeatedly transmitted following the DE signal (data valid signal ENAB), but the main display used in the embodiment is used. The device DS1 does not utilize the synchronization signals VS and HS.

However, the display device DS1 does not prohibit the transmission of the horizontal synchronization signal HS and the vertical synchronization signal VS. However, the internal operation specified in these synchronization signals is not executed. That is, the horizontal line feed timing of the display line is the operation clock CK (corresponding to the LVDS clock CLK) after the falling timing of the data valid signal ENAB and the rising timing of the data valid signal ENAB, regardless of the received horizontal synchronization signal HS. (640 pieces = 1280/2 in the embodiment) and the like are defined as the optimum timing for the internal circuit of the display device DS1 (downward arrow in FIG. 4B).

This point also applies to the vertical line feed timing after displaying an image for one frame, and the internal circuit of the display device DS1 is based on the continuous number of data valid signals ENAB having a predetermined pulse width (1024 in the embodiment). It is defined by the optimum timing for (down arrow in FIG. 4 (c)) and is not affected by the received vertical sync signal VS. As described above, in this embodiment, since it is not necessary to transmit the horizontal synchronization signal HS and the vertical synchronization signal VS to the display device DS1, the pulse widths PWh / PWv of the synchronization signals HS and VS, the front port FPh / FPv, and the like. It is no longer necessary to optimally set the backport BPh / BPv, and the control load on the effect control unit 23 and the VDP circuit 52 is greatly reduced.

Further, as the internal operation of the display device DS1, the horizontal line feed and the vertical line feed operation are executed at the optimum timing based on the internal configuration of the display device DS1, so that the risk of unnatural display operation is eliminated. Incidentally, in the case of a display device that operates based on the horizontal synchronization signal HS received from the outside or the vertical synchronization signal VS, the pulse width of the synchronization signals HS and VS, the front pouch period before and after the synchronization signals HS and VS, and the front pouch period. If the back pouch period is inappropriate, normal display operation may be impaired.

By the way, in FIG. 4A, the first differential signal LVDS1 using the differential signal lines RA0 to RA3 and RACLK transmits the odd-th pixel (ODD signal on the A side), and is a differential signal. The second differential signal LVDS2 using the lines RB0 to RB3 and RBCLK transmits the even-th pixel (EVEN signal on the B side). As described above, in this embodiment, by transmitting the two types of ODD signals and the EVEN signal through the dual link transmission line, the frequency of the dot clock DCK can be reduced to 1/2, and the noise resistance can be reduced by that amount. It has excellent properties and can increase the transmission distance.

On the other hand, the main display device DS1 has a built-in ODD signal transmitted on the dual link transmission line and an EVEN signal conversion receiving unit RV, and restores an RGB signal from two LVDS signals (ODD signal and EVEN signal). Then, an image for one frame (1280 × 1024 dots) is displayed. As described above, since each of the RGB signals is composed of ⁸ bits, a full ^- color image having a gradation of 28 × ²⁸ × 28 is displayed on the main display device DS1.

FIG. 5 is a block diagram showing a display device DS1 composed of a main liquid crystal display unit MONI and an LED backlight unit BL, in particular, an internal configuration of the liquid crystal display unit MONI together with related parts of the VDP circuit 52. As shown in the figure, the ODD signal is transmitted to the LVDS-parallel conversion unit RVa via the first LVDS line (A side), and the EVEN signal is transmitted to the LVDS- via the second LVDS line (B side). It is transmitted to the parallel conversion unit RVb. Then, among the RGB data of each 8-bit length transmitted on the differential line RA0 / RB0, the image data R0 to R5 and G0 are poured out, and the image data G1 to G5 and B0 are ejected from the differential line RA1 / RB1. ~ B1 is poured out.

Further, image data B2 to B5, DE signal, VS signal, and HS signal are dispensed from the differential line RA2 / RB2, and image data G6 to G7, R6 to R7, and B6 to B6 to the differential lines RA3 / RB3. B7 is poured out. Here, the DE signal is nothing but the data valid signal ENAB. Further, as described above, the injected VS signal and the HS signal are not used.

Next, the LVDS clock CLK of the differential line RACK / RBCK is supplied to the PLL circuit to generate an operating clock CK having the same frequency as the LVDS clock CLK and having a frequency of 54 MHz. This operation clock CK defines the internal operation of the liquid crystal controller LCD_CTL, and the liquid crystal controller LCD_CTL is image data corresponding to two RGB pixels (8 bits × 3 × 2) adjacent to each other in the left-right direction of the liquid crystal panel LCD. Are collectively processed in synchronization with one operating clock CK.

Therefore, the pixels of the 1280 (= 640 × 2) dots in the horizontal direction complete the processing in the processing time of 11.85 μS (= 640/54 MHz) for 640 operation clocks CK. It should be noted that one pixel is composed of basic pixels of three colors of RGB, and the image data of the basic pixels of the three colors of RGB has a length of 1 byte and a gradation of ²⁸ × ²⁸ × ²⁸ . The image data of all the pixels (1280 dots) in one line has a length of 3 × 1280 bytes as a whole.

As shown in FIG. 5, the liquid crystal controller LCD_CNT controls ON / OFF of the source driver SDV, which drives 1280 source signal lines with ²⁸ (= 256) gradation drive signals, and 1024 gate signal lines, respectively. The gate driver GDV is appropriately controlled. Specifically, the liquid crystal controller LCD_CNT performs an image update operation with a frame rate FR = 1/60 Hz by appropriately operating each part based on the DE signal injected from the LVDS transmission line and the operation clock CK. It has been realized. As confirmed earlier, the DE signal corresponds to the data valid signal ENAB output by the VDP circuit 52.

In the case of this embodiment, the source driver SDV is configured by arranging 10 driver elements having 384 output terminals. As explained earlier, all the pixels (1280 dots) in one line of the liquid crystal panel LCD are composed of basic pixels of three colors of RGB and have a total of 3 × 1280, so 10 driver elements are required to drive them. Become. Image data DATs are sequentially supplied from the liquid crystal controller LCD_CNT to these 10 driver elements, and these are appropriately transferred based on the start signal SP and the transfer clock DCLK. Then, in synchronization with the latch signal LT, the analog-converted drive signal is supplied to the 3840 source signal lines. As described above, the time required for updating all the pixels (1280 dots) in one line of the liquid crystal panel LCD is 11.85 μS (= 640/54 MHz).

On the other hand, the liquid crystal controller LCD_CNT updates the gate signal line to be driven by supplying the gate start signal GS and the gate clock signal GCLK to the gate driver GDV. Here, the gate driver GDV is configured by arranging four driver elements having 256 output terminals.

The update timing of the gate signal line is defined based on the falling timing of the DE signal and the operation clock CK, and the horizontal line feed cycle of the gate signal line is counted by the operation clock CK. In the typical value calculation, 640 + 204 It is a clock (see FIG. 3 (c)). Further, based on the number of DE signals (1024), the gate signal line to be driven is reset to the initial state, the gate start signal GS is output at the optimum timing, and the output of the gate clock signal GCLK is restarted. The vertical line feed period of the gate signal line is counted by the operation clock CK, and is 42 + 1024 clocks in the typical value calculation (see FIG. 3C). However, as described above, in this embodiment, the display device DS1 is operated with a design different from the typical value (see FIG. 15).

By the way, the above display operation is conditioned on the condition that the power supply voltage 5V is supplied to the main liquid crystal display unit MONI in the lighting state of the LED backlight unit BL. Therefore, in this embodiment, a power supply control circuit SPY is provided so that the liquid crystal display unit MONI and the backlight unit BL can be operated consistently. The power supply control circuit SPY receives three types of DC voltages (3.3V, 5V, 12V) from the effect interface board 22, and various power supply control signals (STBY, PWM, PS1) are received from the effect control CPU 63 of the composite chip 50. , PS2) (see FIG. 7 (a)).

Then, the power supply control circuit SPY supplies a DC voltage of 5 V as the power supply voltage of the main liquid crystal display unit MONI at the optimum timing (see FIGS. 6 (c) and 6 (g)). Further, the power supply control circuit SPY controls the power supply of a DC voltage of 12V as the power supply voltage of the backlight unit BL, and controls the BL_EN terminal and the PWM terminal of the LED backlight unit BL to an appropriate H / L level. , The optimum lighting operation is realized.

FIG. 6A is a circuit diagram showing the relationship between the circuit configuration of the power supply control circuit SPY and the backlight unit BL and the liquid crystal display unit MONI. As shown in the figure, this power supply control circuit SPY has a first switch circuit having a transistor Tr1 and a MOS transistor Q1, a second switch circuit having a transistor Tr2 and a MOS transistor Q2, and a third switch having a transistor Tr3 and a MOS transistor Q3. It is mainly composed of a circuit, a fourth switch circuit having a transistor Tr4 and a MOS transistor Q4, and a buffer circuit SBUF for receiving various control signals.

The buffer circuit SBUF is a high-speed Schmidt buffer (for example, TC74VHC9125) having a DC voltage of 3.3 V supplied from the effect interface board 22 as a power supply voltage, and operates in a non-inverting input / output relationship. That is, the effect control CPU 63 of the composite chip 50 outputs a power supply control signal (STBY, PWM, PS1, PS2) having a theoretical H / L width of 3.3 V based on the power supply voltage of 3.3 V. In response to this, the buffer circuit SBUF outputs control signals (STBY, PWM, PS1, PS2) having the same logic (see FIG. 7A).

As shown in FIG. 6A, the four input terminals (STBY, PWM, PS1, PS2) of the buffer circuit SBUF are all connected to the ground via the pull-down resistor Rpd, and the connection connector is separated. When each control signal is in the HiZ (high impedance) state, such as when the power is turned on, all the control signals are configured to be at the L level.

Next, in the first to fourth switch circuits, the transistors Tr1 to Tr4 are all NPN type bipolar transistors and are driven to perform switching operations. That is, each transistor Tr1 / Tr2 / Tr3 / Tr4 operates ON based on the voltage division ratio of the bias resistance when the corresponding control signal PS1 / STBY / PWM / PS2 is at H level, while the control signal PS1 / STBY / When the PWM / PS2 is at the L level, the OFF operation is performed because no current flows through the bias resistance.

Here, when the transistors Tr1 / Tr4 are turned off, the collector output of each transistor Tr1 / Tr4 is higher than 3.3V (12V / 5V). Further, when the MOS transistor Q1 is in the ON state and the transistors Tr2 / Tr3 are in the OFF operation, the collector output of each transistor Tr2 / Tr3 is about 12V. In these senses, each of the transitions Tr1 to Tr4 constitutes a level shift circuit that increases the logical H level of the power supply control signal (STBY, PWM, PS1, PS2) together with the bias resistance.

The bias resistances for the transistors Tr1 to Tr4 are R11 + R12, R21 + R22, R31 + R32, and R41 + R42, respectively, and the voltage defined by the voltage division ratio of each bias resistance is supplied to the base terminals of the transistors Tr1 to Tr4.

In this embodiment, since the above-mentioned level shift circuits (Tr1 to Tr4) are provided, it is possible to greatly suppress the power consumption of the effect control unit 23 while increasing the emission brightness of the backlight. That is, while the power supply voltage (12V) of the backlight unit BL is set to the highest possible level, the logical H level of the power supply control signal (STBY, PWM, PS1, PS2) is set to an arbitrary low level (3.3V). Can be set to.

On the other hand, the MOS transistors Q1 to Q4 are all Pch type, and perform a switching operation according to the ON / OFF state of the transistors Tr1 to Tr4, and during the ON operation, the source terminal S and the drain terminal D are in a substantially conductive state. Become.

Specifically, first, the MOS transistor Q1 receives a DC voltage of 12V supplied by the effect interface board 22 to its source terminal S, and when the transistor Tr1 operates ON based on the H level control signal PS1. In response to this, the MOS transistor Q1 also operates ON based on the voltage across the bias resistor Rb1 that shifts to the energized state, and outputs a DC voltage of 12V to the drain terminal D.

This DC voltage of 12V is supplied to the backlight unit BL via the RC filter circuit and the Zener diode. In this embodiment, in particular, as the MOS transistor Q1, an element having an ON resistance between the source S and drain D of 25 mΩ or more and 35 mΩ or less is used. Therefore, for example, even if a drive current (drain current ID) of 2.5 A is constantly applied, the voltage drop in the MOS transistor Q1 is 0.1 V or less, and the lost power is 0.22 W (= 2.5 * 2.5). * 35/1000) is suppressed to about. The ON resistance is a measurement result of pulse drive at VGS = −10V and ID = −4.5A.

Further, the transistor Q2 and the transistor Q3 receive the voltage of the drain terminal D of the transistor Q1 at each source terminal S. Therefore, when the transistor Tr2 / Tr3 is turned ON based on the H level control signal STBY / PWM while the MOS transistor Q1 is ON, it is based on the voltage across the bias resistance Rb2 / Rb3 that shifts to the energized state in response to this. Therefore, the MOS transistors Q2 and Q3 also operate ON. Therefore, a DC voltage of 12V is output to each of the drain terminals D of the MOS transistors Q2 and Q3 via the transistor Q1 in the ON state.

This DC voltage 12V is output as a control signal STBY from the drain terminal D of the MOS transistor Q2, and is output as a control signal PWM from the drain terminal D of the MOS transistor Q3. Then, the control signal STBY is supplied to the BL_EN terminal (back light enable) of the backlight unit BL in the pull-down state by the pull-down resistor Rpd, and the control signal PWM is the PWM of the backlight unit BL in the pull-down state by the pull-down resistor Rpd. It is supplied to the terminal (pulse width modulation).

In this embodiment, by setting the pull-down resistor Rpd to about 33 kΩ, the current flowing through the pull-down resistor Rpd due to the DC voltage 12 V (STBY / PWM) is suppressed to about 0.36 mA. Therefore, it is not necessary to select an expensive element as the MOS transistors Q2 and Q3, and in this embodiment, an element having an ON resistance between the source S drain D of 2.5 Ω or more and 3.8 Ω or less is used. .. The ON resistance is a measurement result of pulse drive at VGS = −4.5V and ID = −100mA.

Next, the backlight unit BL will be described. The backlight unit BL outputs N × M light emitting diodes (LEDs) arranged vertically and horizontally and N × M drive pulses of negative logic. It is configured to have a driver DVL that drives the light emitting diode to light up synchronously. This driver DVL has a BL_EN terminal that specifies whether or not internal operation is enabled, and a PWM terminal that specifies the duty ratio of the drive pulse of negative logic with positive logic in the range of 10% to 100%. It is configured to have output terminals LEDs1 to LEDn that output drive pulses.

As described above, the control signal STBY is supplied to the BL_EN terminal from the power supply control circuit SPY, and the control signal PWM is supplied to the PWM terminal. When the control signal STBY is H level (12V), the internal circuit of the driver DVL operates, and the drive pulse can be output from the output terminals LEDs1 to LEDn. This drive pulse is a negative logic pulse in which the control signal PWM is logically inverted.

As described above, the drive pulse of the embodiment is a negative logic pulse obtained by logically inverting the control signal PWM supplied to the PWM terminal. Therefore, the closer the duty ratio of the control signal PWM is to 100%, the more the output terminals LEDs1 to LEDn. The L level period of the light emitting diode becomes longer, and the average current flowing through the light emitting diode increases, so that the backlight light becomes brighter. On the other hand, as the duty ratio is closer to 10%, the average current of the light emitting diode is lowered, so that the backlight light becomes darker.

Therefore, the emission intensity of the backlight light can be changed by appropriately changing the duty ratio of the control signal (control pulse) PWM. For example, in the demo state where the player is absent, the backlight light can be dimmed. However, in this embodiment, in order to avoid such complexity of light emission control, the duty ratio of the control signal is maintained at 100%, and the control signal PWM does not change in a pulse shape and is in an operating state. The H level (12V) is constantly maintained. Therefore, the output terminals LEDs 1 to LEDn of the driver DVL constantly maintain the L level in the operating state of the backlight unit BL.

By the way, both the BL_EN terminal and the PWM terminal are connected to the ground via the pull-down resistor Rpd. Therefore, when the MOS transistor Q2 is in the OFF state and the control signal STBY is in the HiZ state, the driver DVL is in the non-operating state and the output terminals LEDs 1 to LEDn are in the HiZ state, so that all the light emitting diodes are in the HiZ state. It goes out.

Further, when the MOS transistor Q3 is in the OFF state and the control signal PWM is in the HiZ state, the duty ratio is maintained at 0% even if the control signal STBY is at the H level, so that the output terminal is output. LEDs1 to LEDn maintain the H level (12V) and all the light emitting diodes are turned off. Therefore, when the power is turned on when significant image data is not transferred, or when the operation of the power supply control circuit SPY is abnormal, the backlight is turned off, and as a result, an unnatural image display is avoided. It is based on the same intention to connect a pull-down resistor Rpd between the four input terminals of the buffer circuit SBUF and the ground.

Subsequently, the relationship between the fourth switch circuit having the transistor Tr4 and the MOS transistor Q4 and the main liquid crystal display unit MONI will be described. As described above, the transistor Tr4 of the fourth switch circuit operates ON / OFF based on the H / L level of the control signal PS2.

On the other hand, the MOS transistor Q4 receives a DC voltage of 5V supplied by the effect interface board 22 to its source terminal S, and when the transistor Tr1 is turned on, the bias resistor Rb4 shifts to the energized state in response to the DC voltage 5V. Based on the voltage across both ends, the MOS transistor Q4 also operates ON to output a DC voltage of 5V to the drain terminal D.

This DC voltage of 5V is supplied to the liquid crystal display unit MONI shown in FIG. 5 via the RC filter circuit and the Zener diode, and is utilized as the power supply voltage of the liquid crystal display unit MONI. In this embodiment, in particular, as the MOS transistor Q4, an element having an ON resistance between the source S and drain D of 48 mΩ or more and 65 mΩ or less is used. Therefore, for example, even if the drive current (drain current ID) = 1.5A is constantly applied, the voltage drop in the MOS transistor Q1 is 0.1V or less, and the power loss is 0.15W (= 1.5 *). It is suppressed to about 1.5 * 65/1000). The ON resistance is a measurement result of pulse drive at VGS = −4.5 and ID = −2.5A.

Subsequently, the circuit operation of the power supply control circuit SPY will be described with reference to FIGS. 6 (b) to 6 (j). After the power is turned on, the composite chip 50 starts the control operation after an assert period in which the system reset signal SYS maintains the L level (timing T1 in FIG. 6D). Then, the effect control CPU 63 of the composite chip 50 shifts the control signals PS1 and PS2 to the H level after 1000 mS from the timing T1 (timing T2).

Then, the MOS transistor Q1 is turned on based on the H level control signal PS1, and the power supply of DC 12V to the backlight unit BL is started. Further, the MOS transistor Q4 is turned on based on the H level control signal PS2, and the power supply of DC 5V to the liquid crystal display unit MONI is started. However, at the time of this timing T2, both the control signals STBY and PWM are still at the L level, so that the backlight unit BL does not emit light. Therefore, no matter how the liquid crystal display unit MONI operates, there is no possibility that an unnatural image will be displayed.

Next, the effect control CPU 63 starts the initialization operation of the display clock and the display circuit 74 after about 5 mS has elapsed from the timing T2. This control content will be described in detail later, but these operations are one of the initialization operations until the operation of the VDP circuit 52 is started, and at this stage, a significant image signal is displayed on the display device DS1. It will not be output.

After that, the effect control CPU 63 appropriately initializes the display register, and then starts the operation of the display circuit 74 and the LVDS circuit 80 (timing T4). Therefore, after the timing T4, the LVDS signal as a significant image signal is repeatedly output to the display device DS1 every 1/60 second (see FIG. 6 (f)).

However, at the time of timing T4, since the control signal PWM maintains the L level, the backlight light does not emit light. That is, the effect control CPU 63 shifts the control signal STBY to the H level at the timing T3 and controls the driver DVL into an operable state, but at the time of the timing T4, the control signal PWM = L is still driven. Since the duty ratio of the pulse is 0%, the extinguished state of the backlight unit BL is maintained.

On the other hand, the effect control CPU 63 shifts the control signal PWM to the H level at the timing T5 after 300 mS or more has elapsed after starting the operation of the display circuit 74 and the LVDS circuit 80 (SS4 in FIG. 21). SS6), the backlight unit BL is transitioned to a light emitting state having a duty ratio of 100%. Then, when the operation of the timing T5 is executed, for example, by the timer interrupt process, at the time of the timing T5, the liquid crystal display unit MONI has already repeated the LVDS signal as a significant image signal every 1/60 second. Since it has been received, an image based on the image signal will be displayed. That is, since the steady processing (ST4 to ST14 in FIG. 22) is started immediately after the processing in step SS6 in FIG. 21, the initial screen based on the display list DL is displayed at the time of timing T5.

However, as shown in FIG. 21, when the effect control CPU 63 executes the standby process of 300 mS (step SS5 in FIG. 21), the display list DL has not yet been issued at the timing T5, so that the display contents are displayed. Is a screen based on VRAM (frame buffer FBa) after the power is turned on. Therefore, considering this point, it is preferable to clear the VRAM (particularly the frame buffers FBa and FBb) to zero after turning on the power, but even if the VRAM (particularly the frame buffer FBa, FBb) is not cleared to zero, it is a game that a random image is displayed. There is no problem because it is only a moment when the hall opens. That is, immediately after the process of step SS6 in FIG. 21, the steady process (ST4 to ST14 in FIG. 22) is started, and the initial screen based on the display list DL is displayed.

By the way, in this embodiment, the program is designed so that the program execution time from the timing T2 to the timing T4 is within 20 mS. This recommends that the display device DS1 used in the embodiment should start transmitting an image signal (LVDS signal) within a predetermined time τ (for example, 20 mS) after the power is turned on to the liquid crystal display unit MONI. Because.

In this embodiment, the use of the control signal PS2 to delay the power supply timing to the liquid crystal display unit MONI by about 1 second is also based on the above request, and if the power is turned on, the liquid crystal display unit MONI is sent to the liquid crystal display unit MONI at the same time. It is very impossible to start the transmission of the LVDS signal within the predetermined time τ (for example, 20 mS) after the power supply is started because of the assert period and the program execution time (processing time of SP1 to SP10) (timing T4). reference).

Although the main display device DS1 has been described in detail above, the operation contents of the sub-display device DS2 are substantially the same, and by performing the operation shown in FIG. 6B, the sub-liquid crystal display unit MONI and the sub-display device DS2 are operated. The backlight unit BL is configured to operate consistently so as not to cause inappropriate display.

Further, the sub-display device DS2 operates in the same manner as shown in FIG. 42 based on the horizontal synchronization signal HS and the vertical synchronization signal VS received from the VDP circuit 52. However, it is also preferable that the sub-control device DS2 also operates based on the data valid signal ENAB, not based on the horizontal synchronization signal HS or the vertical synchronization signal VS. The data valid signal ENAB is transmitted to the sub-display device DS2 as a continuous signal ENAB, not in the form of a discrete DE signal (see the lower right of FIG. 14A).

Next, returning to FIG. 3A, the overall circuit configuration of the pachinko machine GM will be described. As shown in FIG. 3A, this pachinko machine GM is mainly responsible for the power supply board 20 that receives AC24V and outputs various DC voltages (35V, 12V, 5V) together with AC24V, and the game control operation. The lamp effect, the sound effect, and the image effect are uniformly executed based on the control board 21, the effect interface board 22 equipped with the circuit element SND for the sound effect, and the control command CMD received from the main control board 21. A game in which the payout motor M is controlled based on the effect control board 23, the liquid crystal interface board 24 located between the effect control board 23 and the display devices DS1 and DS2, and the control command CMD'received from the main control board 21. It is mainly composed of a payout control board 25 for paying out balls and a launch control board 26 for firing a game ball in response to a player's operation.

The effect interface board 22, the effect control board 23, and the liquid crystal interface board 24 are directly connected to the male connector and the female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire substrate can be minimized, and noise resistance can be improved by minimizing the connection line.

As shown in the figure, the control command CMD'output by the main control board 21 is transmitted to the payout control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the effect control board 23 via the effect interface board 22. Here, the control commands CMD and CMD'are both 16-bit length, but are transmitted in parallel in two steps every 8-bit length.

A computer circuit including a one-chip microcomputer is mounted on the main control board 21 and the payout control board 25. Further, the effect control board 23 is equipped with a composite chip 50 having a built-in computer circuit such as a VDP circuit (Video Display Processor) 52 and a built-in CPU circuit 51. Therefore, these control boards 21, 25, 23, the circuits mounted on the effect interface board 22 and the liquid crystal interface board 24, and the operations realized by the circuits are functionally collectively referred to in the present specification. , The main control unit 21, the effect control unit 23, and the payout control unit 25. The effect control unit 23 and the payout control unit 25 serve as sub-control units for the main control unit 21.

Further, the pachinko machine GM is roughly divided into a frame-side member GM1 surrounded by a broken line in FIG. 3A and a board-side member GM2 fixed to the back surface of the game board 5. The frame-side member GM 1 includes an inner frame 3 to which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outer side thereof. It is fixedly installed in. On the other hand, the board-side member GM2 is replaced in response to the model change, and a new board-side member GM2 is attached to the frame-side member GM1 instead of the original board-side member. All except the frame-side member 1 are board-side members GM2.

As shown in the broken line frame of FIG. 3A, the frame side member GM 1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor /. A lamp drive board 37 and a lamp drive board 37 are included, and these circuit boards are fixed in appropriate places in the inner frame 3. On the other hand, on the back surface of the game board 5, a main control board 21 and an effect control board 23 are fixed together with display devices DS1 and DS2 and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by centralized connection connectors C1 to C3 centrally arranged at one location.

The power supply board 20 generates three types of DC voltages (35V, 12V, 5V) based on the AC voltage AC24V distributed from the game hall, and each DC voltage is transmitted via the centralized connector C2. Power is distributed to the face substrate 22. Further, the three types of DC voltages (35V, 12V, 5V) are distributed to the payout control board 25 together with the AC voltage AC24V. The DC voltage (35V, 12V, 5V) distributed to the payout control board 25 is configured to be distributed to the main control board 21 via the centralized connector C1 together with the backup power supply BAK.

The direct current 35V is used as a drive power source for the ball feed solenoid and the launch solenoid, and as a drive power source for the electromagnetic solenoid that opens and closes the electric tulip (variable winning device) and the large winning opening 16 in relation to the launching operation of the game ball. Further, DC 12V is used as a power supply for driving an LED lamp or a motor controlled from each control board, and a power supply voltage for a digital amplifier, while DC 5V is a one-chip microcomputer of a payout control board 25 or a main control board 21. It is used as the power supply voltage of the above and the power supply voltage of the logic element mounted on each control board. Further, in the DC 5V, after the level is lowered by the DC / DC converter of the effect interface board 22, the voltage of various levels lowered is used as the power supply voltage of various computer circuits (composite chip 50, voice processor 27, etc.). used.

The backup power supply BAK is a DC 5V DC power supply for holding data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 after the power supply is cut off, and is realized by, for example, an electric double layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double layer capacitor arranged on the backup power supply board 33 is configured to be charged during the game operation by the DC voltage 5V received from the payout control board 25. Has been done.

On the other hand, after the power is cut off, the backup power supply BAK holds the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25. The game operation can be restarted after the power is turned on. An electric double layer capacitor capable of holding the storage contents of the built-in RAM of each one-chip microcomputer is arranged on the backup power supply board 33 for at least several days.

By the way, in this embodiment, unlike the conventional device configuration, the power supply abnormality signal ABN indicating an abnormal decrease in the AC voltage AC24V is configured to be generated not by the power supply board 20 but by the power supply monitor unit MNT of the payout control board 25. Has been done. As shown in FIG. 3B, the power supply monitor unit MNT includes a full-wave rectifier circuit that rectifies AC24V received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits light, and a power supply board 20. A phototransition TR that operates ON based on the light emission of the photodiode D and an output unit that outputs an H-level detection signal ABN (power supply abnormality signal) based on the ON operation of the phototransition TR, using a DC voltage of 5V received from the power supply. And, it is configured to have. The photodiode D and the phototransition TR form a photocoupler PH.

In the above configuration, the photocoupler PH is immediately turned on after the power is turned on, so that the power supply abnormality signal ABN becomes the normal level (H). However, after that, when the AC power supply abnormally drops for some reason (normally, the power supply is cut off), the photocoupler PH changes to the OFF state, and the power supply abnormality signal ABN changes to the abnormal level (L). The power supply abnormality signal ABN is configured to be transmitted to the one-chip microcomputer of the payout control board 25 and also to the one-chip microcomputer of the main control board 21 via the centralized connector C1. Therefore, each one-chip microcomputer that receives the abnormal level power supply abnormality signal ABN executes a backup process for storing necessary information in each built-in RAM. As described above, since the information in the built-in RAM is maintained by the backup power supply BAK, the game operation before the power is cut off can be restarted after the power is turned on.

As shown in FIG. 3A, a voice circuit SND such as a voice processor 27 is mounted on the effect interface board 22, and a computer circuit such as a VDP circuit 52 and a built-in CPU circuit 51 is built in the effect control board 23. The composite chip 50 is mounted. Hereinafter, the built-in CPU circuit may be abbreviated as a CPU circuit.

The effect interface board 22 is equipped with reset circuits RST3 and RST4 that detect an increase in the power supply voltage and generate various reset signals RT3 and RT4 when the power is turned on. First, the reset circuit RST3 generates a reset signal RT3 based on the DC voltages 12V and 5V distributed from the power supply board 20. Then, the reset signal RT3 resets the power supply of only the voice memory 28 and is transmitted to the effect control board 23 as it is.

As shown in FIG. 7A, the reset signal RT3 transmitted to the effect control board 23 is AND-calculated with the output of the WDT (Watch Dog Timer) circuit 58 at the AND gate G1, and is used as the system reset signal SYS in the CPU circuit. The power supply of 51 and the VDP circuit 52 is reset (see FIGS. 7 (a) and 7 (d)).

The reset signal RT3 generated by the reset circuit RST3 rises to the H level after maintaining the L level as the power reset signal for a predetermined time after the power is turned on. However, after that, when any one or more of the DC voltage 12V or the DC voltage 5V drops (usually when the power is cut off), the system reset signal SYS also drops to the L level in response to the level drop of the reset signal RT3. Therefore, the CPU circuit 51 and the VDP circuit 52 of the effect control board 23 are stopped in operation.

Since this system reset signal SYS also changes based on the output of the WDT circuit 58 (H level at normal times), the output of the WDT circuit 58 is output due to a program runaway or the like when the reset signal RT3 = H. Corresponding to the drop to the L level, the system reset signal SYS also changes to the L level, and the CPU circuit 51 and the VDP circuit 52 are abnormally reset (see FIG. 7D).

On the other hand, the reset circuit RST4 generates a reset signal RT4 based on 3.3V generated by dropping 5V distributed from the power supply board 20. This reset signal RT4 power-resets the voice processor 27 as a power-reset signal when the power is turned on.

As shown in the figure, the reset circuit RST4 is also supplied with the system reset signal SYS returned from the effect control board 23, so that when the CPU circuit 51 or the VDP circuit 52 is abnormally reset, it synchronizes with the abnormal reset of these circuits. Then, the voice processor 27 is also abnormally reset. As a result, the audio effect returns to the initial state together with the image effect and the lamp effect, and there is no possibility that the unnatural audio effect will continue.

Next, the reset circuits RST1 and RST2 are mounted on the frame-side member GM1 payout control board 25 and the board-side member GM2 main control unit 21, respectively, and a power reset signal is generated when the power is turned on. The computer circuit is configured to power reset.

As described above, in this embodiment, the reset circuits RST1 to RST4 are arranged on the main control unit 21, the payout control unit 25, and the effect interface board 22, respectively, and the system reset signal SYS is transmitted between the circuit boards. Not transmitted. That is, since there is no wiring cable for transmitting the system reset signal SYS, the possibility that the computer circuit is abnormally reset due to the noise superimposed on the wiring cable is eliminated.

However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the payout control unit 25 each have a built-in watchdog timer, and do not receive a regular clear pulse from the CPUs of the control units 21 and 25. In that case, each CPU is forcibly reset.

Further, an initialization switch SW that can be operated by a staff member is arranged in the main control unit 21, and a RAM clear signal CLR indicating whether or not the initialization switch SW is turned ON is output when the power is turned on. It is configured. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the payout control unit 25, and determines whether or not to initialize the entire area of the built-in RAM of the one-chip microcomputers of the control units 21 and 25. ing.

Further, as described above, the one-chip microcomputers of the main control unit 21 and the payout control unit 25 receive the power supply abnormality signal ABN from the power supply monitor MNT arranged in the payout control unit 25, thereby prior to a power failure or business termination. Then, the necessary termination processing is started.

As shown in FIG. 3A, the main control unit 21 receives from the payout control unit 25 a prize ball counting signal indicating a payout operation of the game ball, a status signal CON related to an abnormality in the payout operation, and an operation start signal BGN. I'm receiving. The status signal CON includes, for example, a supply shortage signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 25 is completed after the power is turned on.

Further, the main control unit 21 receives the switch signal of the detection switch built in each of the winning openings 16 to 18 on the game board, while driving solenoids such as electric tulips. The solenoids and the detection switch are configured to operate at the power supply voltage VB (12V) distributed from the main control unit 21. Further, each switch signal indicating the winning state of the symbol start port 15 is converted into a TTL level or CMOS level switch signal by an interface IC operating at a power supply voltage VB (12V) and a power supply voltage Vcc (5V). After that, it is transmitted to the main control unit 21.

As described above, the effect interface board 22 receives each level of DC voltage (5V, 12V, 35V) from the power supply board 20 via the centralized connector C2 (FIGS. 3A and 3A). 7 (a)). The DC voltage 12V is a power supply voltage for the digital amplifier 29 and is used as a driving voltage for LED lamps and the like. Further, the DC voltage 35V is used as a driving voltage of a solenoid that is distributed to a suitable place in the game frame to reciprocate a movable object.

On the other hand, the DC voltage of 5V is supplied as the power supply voltage of the circuit elements of the effect interface board 22 and is supplied to the two DC / DC converters DC1 and DC2 to generate 3.3V and 1.0V (). See FIG. 7 (a)). The generated direct current voltages of 3.3 V and 1.0 V are supplied to the voice processor 27 as power supply voltages for I / O (input / output) and for the chip core, respectively. Further, the DC voltage 3.3V is the basic voltage of the power supply reset signal RT4 generated by the reset circuit RST4.

The DC voltage of 5V distributed to the effect interface board 22 is distributed to the effect control board 23 together with 3.3V generated by the DC / DC converter DC1. Then, the DC voltage 3.3V distributed on the effect control board 23 is supplied to the composite chip 50, the PROM 53, and the CGROM 55 as the power supply voltage.

As shown in FIG. 7A, two DC / DC converters DC3 and DC4 are arranged on the effect control board 23, and 1.5V and 1.05V are arranged based on the DC voltage 5V supplied to each. Is being generated. Here, the DC voltage of 1.05V is the power supply voltage for the chip core of the composite chip 50, and the DC voltage of 1.5V is the power supply voltage for I / O (input / output) with the DRAM 54. Therefore, the DC voltage of 1.5V is also supplied to the DRAM 54 as a power supply voltage.

As shown in FIG. 3A, the effect interface board 22 receives the control command CMD and the strobe signal STB from the main control unit 21 and transfers them to the effect control board 23. More specifically, as shown in FIG. 7A, the control command CMD and the strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the effect control board 23 via the input buffer 40. .. Here, the strobe signal STB is a receive interrupt signal IRQ_CMD, and the effect control CPU 63 acquires a control command CMD based on an interrupt processing program (interrupt handler) activated by receiving the receive interrupt signal IRQ_CMD.

As shown in FIG. 7A, the input buffer 44 of the effect interface board 22 receives the chance button 11 and the switch signal of the volume switch VLSW from the frame relay boards 35 and 36, and outputs each switch signal to the CPU of the effect control board 23. It is transmitted to the circuit 51. Specifically, a 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW and a 1-bit length indicating the ON / OFF state of the chance button 11 are transmitted to the CPU circuit 51.

Further, the lamp drive board 30 and the motor lamp drive board 31 are connected to the effect interface board 22, and are also connected to the lamp drive board 37 via the frame relay boards 35 and 36. As shown in the figure, the output buffer 42 is arranged corresponding to the lamp drive board 30, and the input buffer 43a and the output buffer 43b are arranged corresponding to the motor lamp drive board 31. In FIG. 7A, for convenience, the input buffer 43a and the output buffer 43b are collectively referred to as an input / output buffer 43. The input buffer 43a receives the outputs SN0 to SNn of the origin sensor that grasps the current position (rotational position of the effect motors M1 to Mn) of the accessory that is the movable effect body, and transmits the output to the CPU circuit 51 of the effect control board 23. There is.

The same type of driver IC is mounted on the lamp drive board 30, the motor lamp drive board 31, and the lamp drive board 37, and the effect interface board 22 receives the serial signal received from the effect control board 23 for each driver IC. Transferring to. Specifically, the serial signal is a lamp (motor) drive signal SDAT and a clock signal CK, and the drive signal SDAT is transmitted to each driver IC by a clock synchronization method, and a large number of LED lamps and illuminated lamps are used for lamp production. , The effect effect is executed by the effect motors M1 to Mn.

In the case of this embodiment, the lamp effect is executed by the lamp groups CH0 to CH2 of the three systems, and the lamp drive board 37 clocks the lamp drive signal SDAT0 of CH0 via the frame relay boards 35 and 36. Received in synchronization with signal CK0. The series of lamp drive signals SDAT0 transmitted as serial signals are simultaneously updated in the lighting state by being output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level.

The above points are the same for the lamp drive board 30, the driver IC of the lamp drive board 30 receives the lamp drive signal SDAT1 of the lamp group CH1 in synchronization with the clock signal CK1, and the operation control signal ENABLE1 is at the active level. At the timing when it changes to, the lighting state of the lamp group CH1 is updated all at once.

On the other hand, the driver IC mounted on the motor lamp drive board 31 receives the lamp drive signal transmitted in the clock synchronous manner to drive the lamp group CH2, and also receives the motor drive signal transmitted in the clock synchronous manner to drive the lamp group CH2. It drives the effect motor groups M1 to Mn composed of a plurality of stepping motors. The lamp drive signal and the motor drive signal are a series of serial signals SDAT2, which are serially transmitted in synchronization with the clock signal CK1. Then, the drive states of the lamp group CH2 and the motor groups M1 to Mn are updated.

Subsequently, the voice circuit SND will be described. As shown in FIG. 7A, the effect interface board 22 includes a voice processor (voice synthesis circuit) 27 that reproduces a voice signal based on an instruction received from the CPU circuit 51 (effect control CPU 63) of the effect control board 23. , A voice memory 28 for storing compressed voice data which is the original data of the voice signal to be reproduced, and a digital amplifier 29 for receiving the voice signal output from the voice processor 27 are mounted.

The voice processor 27 is configured by incorporating a WDT circuit that automatically resets the set value of the internal circuit to a default value (initial value) when the internal circuit operates abnormally, and a voice control register SRG. Then, the voice processor 27 accesses the voice memory 28 based on the operation parameter (set value by the voice command) received from the effect control CPU 63 to the voice control register SRG, and reproduces and outputs the necessary voice signal. ..

As shown in FIG. 7A, the voice processor 27 and the voice memory 28 are connected by a voice address bus having a length of 26 bits and a voice data bus having a length of 16 bits. Therefore, 1 Gbit (= ²²⁶ × 16) data can be stored in the voice memory 28.

The voice control register SRG is divided into register banks 1 to register banks 6, and each is specified by a register number of 00H to FFH. Therefore, the predetermined setting operation is realized by specifying the register bank and then writing the operation parameter of 1 byte length to the voice control register SRG of the predetermined register number (1 byte length) by the effect control CPU 63. To.

In the case of this embodiment, the register numbers (00H to FFH) of the voice control register SRG correspond to the address space CS3 of the effect control CPU 63. For example, the operation parameter YYH is set in the voice control register SRG of the register number XXH. In this case, the effect control CPU 63 writes XXH at address zero in the address space CS3, and then writes YYH at address 1. That is, the effect control CPU 63 writes XXH and YYH to the data bus in this order. In the present specification, the subscript H and the prefix of 0X / 0x indicate that the numerical value is displayed in hexadecimal.

Further, in the present specification, the address spaces CS0 to CS7 refer to the external memory for the CPU circuit 51 in which the memory type including the presence or absence of volatility and the data bus width (8/16/32 bits) can be specified respectively. Means (excluding internal memory). The address spaces CS0 to CS7 are selected by different chip select signals CS0 to CS7, and are configured to be configurable so that the READ / WRITE control signal functioning at the time of READ / WRITE access can be optimized according to the memory type. This setting operation is executed for the bus state controller 66.

FIG. 7E illustrates the setting operation of the audio register SRG by the effect control CPU 63, and shows the contents of the 2-bit length address bus A1-A0 and the 1-byte length data bus D7-D0. There is. In this embodiment, the chip select signal CS3 is set at power-on so that it is automatically activated when accessing the address space CS3. This point will be described later with reference to FIGS. 9 and 16.

In any case, in the case of this embodiment, the compressed audio data stored in the audio memory 28 is the phrase compressed data specified by the phrase number NUM (000H to 1FFFH) having a length of 13 bits, and is a series of backgrounds. A maximum of 8192 types (= 2 ¹³ ) of music songs (BGM) and a set of directing sounds (notice sounds) are stored corresponding to the phrase number NUM. The phrase number NUM is specified by a set value (operation parameter) of a voice command transmitted from the effect control CPU 63 to the voice control register SRG of the voice processor 27.

As described above, the voice memory 28 having the above configuration is power-reset by the reset signal RT3, and the voice processor 27 is power-reset by the reset signal RT4. As shown in FIG. 7C, the reset signal RT4 rises to the H level after a predetermined assert period ASRT (L level section) after the power is turned on. However, in this embodiment, after that, the internal circuit of the voice processor 27 rises. Is configured to function automatically to perform the initialization sequence process. It should be noted that this initialization sequence processing is an internal operation executed by a predetermined procedure, and the effect control CPU 63 cannot access the voice register SRG during the operation of the initialization sequence processing.

Then, when the initialization sequence processing, which is an internal operation, is completed, the interrupt signal IRQ_SND for the CPU circuit 51 changes to the L level, and the CPU circuit 51 (effect control CPU 63) executes the interrupt processing program based on the interrupt signal IRQ_SND. Then, the interrupt signal IRQ_SND is returned to the H level based on a predetermined instruction, and the details thereof will be described later with reference to FIG. 18 (c).

As shown in FIG. 7A, the data bus and address bus of the CPU circuit 51 of the effect control unit 23 extend to the clock circuit (real time clock) 38 and the effect data memory 39 mounted on the liquid crystal interface board 24. I'm sorry. The clock circuit 38 is connected to the lower 4 bits of the address bus of the CPU circuit 51 and the lower 4 bits of the data bus. When the clock circuit 38 is selected by the chip select signal CS4, the CPU circuit 51 has a (4 bit length). It is configured to allow arbitrary access to internal registers (which have an address value).

Further, the effect data memory 39 is a memory element SRAM (Static Random Access Memory) that can be accessed at high speed, and is connected to 16 bits of the address bus of the CPU circuit 51 and 16 bits of the lower 16 bits of the data bus, and is connected to the chip select signal CS4. In the state where the chip is selected in, the game record information and the like stored in the SRAM (effect data memory) 39 are appropriately R / W accessed from the CPU circuit 51. In the address space CS4 selected by the chip select signal CS4, addresses 0 to 15 are numbered in the clock circuit 38, and are not used in SRAM 39.

The clock circuit 38 and the effect data memory 39 are driven by a secondary battery (not shown), and the secondary battery is appropriately charged by the power supply voltage from the power supply board 20 during the game operation. Therefore, even after the power is cut off, the timekeeping operation of the clock circuit 38 is continued, and the game performance information stored in the effect data memory 39 is permanently stored and retained (non-volatileity is imparted). The clock circuit (RTC) 38 is configured to be able to output an interrupt signal IRQ_RTC to the CPU circuit 51 (RTC interrupt). This RTC interrupt includes an alarm interrupt that can specify the day, day, hour, minute, and second, and a timer interrupt that is activated after a predetermined time has elapsed. It utilizes alarm interrupts that update game performance information.

As shown on the right side of FIG. 7A, the effect control board 23 includes a composite chip 50 incorporating a CPU circuit 51 and a VDP circuit 52, a control memory (PROM) 53 for storing a control program of the CPU circuit 51, and a control memory (PROM) 53. It is equipped with a DRAM (Dynamic Random Access Memory) 54 that can access a large amount of data at high speed, and a CGROM 55 that stores a large amount of CG data required for effect control.

As will be described later with respect to FIG. 10, the control memory (PROM) 53 is positioned in the address space CS0 selected by the chip select signal CS0 in this embodiment. Further, the DRAM (Dynamic Random Access Memory) 54 composed of DDR (Double-Data-Rate 3) is positioned in the address space CS5 selected by the chip select signal CS5.

FIG. 8A is a circuit block diagram showing the composite chip 50 constituting the effect control unit 23, including related circuit elements. As shown in the figure, the composite chip 50 of the embodiment is driven by a CPU circuit 51 that issues a display list DL at predetermined time intervals and display devices DS1 and DS2 that generate image data based on the issued display list DL. It has a built-in VDP circuit 52. The CPU circuit 51 and the VDP circuit 52 are connected to each other through a CPUIF circuit 56 that relays transmission / reception data to each other.

The VDP circuit 52 has a built-in voice circuit SND that exhibits the same function as the voice processor 27, but the voice circuit SND is not used in the first embodiment described below. However, if the voice circuit SND built in the VDP circuit 52 is utilized as in the last embodiment, the voice memory 28 and the voice processor 27 do not need to be arranged.

First, the CPU circuit 51 receives the oscillation output (for example, 100/3 MHz) of the oscillator OSC1 at the HCLKI terminal and multiplies it by frequency (for example, 8 times) to obtain a CPU operating clock of about 266.7 MHz (FIG. 14). See (b)). Here, the oscillator OSC1 is configured to output a spectrum diffused wave to take measures against EMI (Electromagnetic Interference) to prevent radio interference / electromagnetic interference.

By the way, in the case of this embodiment, the CPU operating clock can be generated based on the output of the oscillator OSC2 described later instead of the oscillator OSC1, and the oscillator OSC1 can be eliminated. However, in the configuration where the oscillator is unified, the frequency multiplication ratio of the PLL circuit becomes the same fixed value (for example, 5) as in the case of the system clock described below, so that the frequency of the CPU operating clock is the frequency of the VDP circuit 52. It is 200 MHz (= 40 MHz × 5), which is the same as the system clock.

Adopting such a configuration has an advantage that the operation cycle of the built-in CPU circuit 51 and the VDP circuit 52 is shared, but it goes against the demand for speeding up the operation of the CPU as much as possible. That is, since the VDP operation cannot be speeded up above a certain level, it is not possible to reliably meet the demand for speeding up the CPU operation. Therefore, in this embodiment, two oscillators are provided in order to optimize each operation cycle of the VDP circuit 52 and the CPU circuit 51. Further, by providing a separate oscillator OSC1, it is possible to improve the above-mentioned EMI countermeasures.

The VDP circuit 52 will be described based on the above. The VDP circuit 52 receives the oscillation output (40 MHz) of the oscillator OSC2 different from the oscillator OSC1 at the PLLREF terminal, and the frequency is multiplied by the PLL (Phase Locked Loop) circuit. , The system clock of the VDP circuit 52. The frequency multiplication ratio of the PLL circuit is fixedly defined by the set value for the predetermined setting terminal, and in this embodiment, the set value for the setting terminal (3-bit PLLMD terminal) is the fixed value 5, and thus the VDP. The system clock of the circuit 52 is 200 MHz (= 40 MHz × 5) (see FIG. 14 (b)).

Further, in this embodiment, the dot clocks _DCKA to DCKC that define the operation of the display circuits 74A to _74C and the DDR clock of the external DRAM 54 are also generated based on the oscillation output (40 MHz) of the oscillator OSC2. There is. That is, the output (40 MHz) of the oscillator OSC2 functions as a reference clock for the entire VDP circuit 52.

As will be described later with reference to FIGS. 14 and 15, since the display circuits 74A to 74C usually drive display devices having different specifications, the dot clocks _DCKA to DCK that define the operation of the display circuits 74A to 74C are specified. _C needs to correspond to the specifications of the display device to be driven. Based on this need, in this embodiment, the display circuits 74A to 74C receive any of the output clocks (DCLKAI to DCLKCI) of the dedicated oscillation circuits DCLKA to DCLKC, and use them as dot clocks _DCKA to _DCKC . It is also configured to be able to.

When this configuration is utilized, it is not necessary to design the multiplication ratio and division ratio, which will be described later, and to set the VDP register RGij, and the frequencies of the dot clocks _{DCKA to DCK C can} be easily optimized. .. That is, the dedicated oscillation circuit DCLKA of the oscillation frequency F _DOT1 is provided corresponding to the dot clock frequency F _DOT1 of the main display device DS1, and the dedicated oscillation frequency F _DOT2 is provided corresponding to the dot clock frequency F _DOT2 of the sub display device DS2. It is also possible to provide an oscillation circuit DCLKB.

However, when such a configuration is adopted, a dedicated oscillation circuit is required corresponding to the number of display devices, which complicates the equipment configuration. Therefore, in this embodiment, in order to simplify the device configuration, the dot clock _DCKA / _DCKB of the display circuit 74A / 74B is generated based on the oscillation output (40 MHz) of the oscillator OSC2. Specifically, as shown in FIG. 14B, for the display circuit 74A that drives the main display device DS1, the oscillation output (40 MHz) of the oscillator OSC2 is subjected to predetermined multiplication processing (× 108) and frequency division processing (1). By applying / 40), a dot clock _DCKA with a frequency of 108 MHz is generated.

Similarly, for the display circuit 74B that drives the sub-display device DS2, the oscillation output (40 MHz) of the oscillator OSC2 is subjected to predetermined multiplication processing (× 108) and frequency division processing (1/160) to obtain a frequency F. A dot clock _DCKB with _dot = 27 MHz is generated. Designing these multiplication ratios and division ratios is rather complicated, and it is easier to provide a dedicated oscillation circuit. However, in this embodiment, an emphasis is placed on simplification of the equipment configuration, and a dedicated oscillation circuit is used. Is not provided.

In any case, the dot clocks DCKA to DCK _C are individually set for each of the display circuits 74A to _{74C, but when these dot clocks DCKA to DCK C are generically} referred to in the present specification, the "display clock" is used. It may be called "DCK". Further, in the following description, the dot clock DCK _A and _DCKB may be abbreviated as "dot clock DCK" for convenience.

Since the low-speed LVDS output configuration is not adopted in this embodiment, the LVDS clock CLK of the LVDS signal output via the display circuit 74A also undergoes the same generation process as the dot clock _DCKA and has a frequency of 108 MHz. It is supposed to be. However, in this embodiment, since the dual link transmission line is adopted, the frequency of the actual LVDS clock CLK is 54 MHz as described with respect to FIG. When a single link transmission line is adopted, the frequency of the LVDS clock CLK is 108 MHz.

As described above, in this embodiment, the oscillation output (40 MHz) of the oscillator OSC2 is utilized as a reference clock for the system clock, the dot clock DCK, and the DDR clock. Therefore, in consideration of this importance, the reference clock is operated on the condition that the oscillator OSC2 is operated at the same power supply voltage of 3.3V as the VDP circuit 52 and the output enable terminal OE is H level (= 3.3V). Is configured to oscillate and output. Then, in the unlikely event that the power supply voltage 3.3 V drops to a predetermined level or less, normal production operation cannot be expected thereafter, so that an unmaskable interrupt (NMI) is configured to occur.

Further, the composite chip 50 is provided with an HBTSL terminal, and is the boot program (initial setting program) executed after the power is turned on (CPU reset) stored in the CGROM 55 based on the logic level of the HBTSL terminal (HBTSL)? = H), or whether it is stored in other memory (HBTSL = L) is specified. As shown in the figure, in this embodiment, HBTSL = L level is set, and the zero address of the address space CS0 of the effect control CPU 63 is assigned to other than the CGROM. Specifically, the address space CS0 is the control memory 53. Is assigned to.

On the other hand, when the HBTSL terminal = H level is set (see the broken line), the zero address of the address space CS0 of the effect control CPU 63 is assigned to the CGROM 55. In this case, the memory type of the CGROM 55 and the bus width (64/32/16 bit) are specified based on the input values to the HBTBWD terminal having a 2-bit length and the HBTRMSL terminal having a 4-bit length. These points will be further described later based on FIG. 39.

Subsequently, the CPU IF circuit 56 that relays transmission / reception data between the CPU circuit 51 and the VDP circuit 52 will be described. As shown in FIG. 8A, the CPUIF circuit 56 includes a control memory (PROM) 53 that non-volatileally stores a control program and necessary control data, and a work memory (RAM) 57 having a storage capacity of about 2 Mbytes. Are connected to each other and are configured to be accessible from the CPU circuit 51. As described above, the control memory (PROM) 53 is positioned in the address space CS0 selected by the chip select signal CS0, and the work memory (RAM) 57 is positioned in the address space CS6 selected by the chip select signal CS6. Has been done.

In the work memory (RAM) 57, a DL buffer BUF for temporarily storing a display list DL in which a series of instruction commands for specifying each frame of the display devices DS1 and DS2 are described is secured. In the case of this embodiment, a series of instruction commands include a texture load command such as a TXLOAD command for reading an image material (texture) from the CGROM 55 and decoding (expanding) it, and a VRAM area (index) of the decoding (expanding) destination. Texture setting commands such as the SET INDEX command, which have functions such as specifying the space in advance, and primitive drawing commands such as the SPRITE command for arranging the decoded (expanded) image material at a predetermined position in the virtual drawing space. Of the images drawn in the virtual drawing space by drawing commands, environment setting commands such as the SETDAVR command and SETDAVF command for specifying the drawing area actually drawn on the display device, and the index table IDXTBL that manages the index space. Contains index table control commands (WRIDXTBL) for.

Note that FIG. 12 (c) shows a virtual drawing space (horizontal X direction ± 8192: vertical Y direction ± 8192), a drawing area that can be arbitrarily set in the virtual drawing space, and outputs to the display devices DS1 and DS2. The relationship with the actual drawing area in the frame buffers FBa and FBb for primary storage of the image data to be performed is illustrated.

Next, the CPU circuit 51 is a circuit having the same performance as a general-purpose one-chip microcomputer, and the effect control CPU 63 that comprehensively controls the image effect based on the control program of the control memory 53 and the program go into a runaway state. A watchdog timer (WDT) that forcibly resets the CPU, a built-in RAM 59 that has a storage capacity of about 16 kbytes and is used as a work area of the CPU, and a DMAC (Direct Memory Access) that realizes data transfer without going through the CPU 63. Controller) 60, a serial input / output port (SIO) 61 having a plurality of input ports Si and an output port So, a parallel input / output port (PIO) 62 having a plurality of input ports Pi and an output port Po, and the above-mentioned parts. It is configured to have an operation control register REG or the like in which a set value is set to control the operation. However, in this embodiment provided with the external WDT circuit 58, the watchdog timer (WDT) built in the CPU circuit 51 is not utilized.

In this specification, the term “input / output port” is used for convenience, but in the effect control unit 23, the input / output port includes an input port and an output port that operate independently. This point is the same for the input / output circuit 64p and the input / output circuit 64s described below.

The parallel input / output port 62 is connected to an external device (effect interface board 22) through the input / output circuit 64p, and the production control CPU 63 has a chance with the encoder output 3 bits of the volume switch VLSW via the input circuit 64p. The switch signal of the button 11, the control command CMD, and the interrupt signal STB are received. The encoder output 3 bits and the switch signal 1 bit are supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p.

Similarly, the received control command CMD is supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p. Further, the strobe signal STB is supplied to the interrupt terminal of the effect control CPU 63 via the input / output circuit 64p to activate the reception interrupt processing. Therefore, the effect control CPU 63 that grasps the control command CMD based on the reception interrupt process uniformly controls the audio effect, the lamp effect, the motor effect, and the image effect corresponding to this control command CMD through the effect lottery and the like. Will be done.

Although not particularly limited, in this embodiment, the SMC unit (Serial Management Controller) 78 of the VDP circuit 52 is used for the lamp effect and the motor effect. The SMC unit 78 is a composite controller having a built-in LED controller and Motor controller, and is configured to be able to output a serial signal by a clock synchronization method. Further, the Motor controller is configured to be able to output a latch pulse at an arbitrary timing based on a set value in a predetermined control register 70, and is configured to be able to input a serial signal by a clock synchronization method.

Therefore, in this embodiment, the motor drive signal and the LED drive signal are output from the SMC unit 78 in synchronization with the clock signal, while the latch pulse is output as the operation control signal ENABLE at an appropriate timing. .. Further, the origin sensor signals SN0 to SNn from the effect motor groups M1 to Mn are configured to be serially input by a clock synchronization method.

As described with respect to FIG. 7A, the clock signals CK0 to CK2, the drive signals SDAT0 to SDATA2, and the operation control signals ENABLE0 to ENABLE2 pass through the output buffers 41 to 43, and the predetermined drive boards 30, 31, It is transmitted to 37. Further, the origin sensor signals SN0 to SNn are serially input to the SMC unit 78 from the motor lamp drive board 31 via the input / output buffer 43.

However, it is not essential to use the SMC unit 78 in this embodiment. That is, since the CPU circuit 51 has a built-in general-purpose serial input / output port SIO61, it is also possible to execute a lamp effect and a motor effect by using these.

Specifically, it is as shown by the broken line in FIG. 8A, and in the configuration shown by the broken line, the clock signals CK0 to CK2, via the input / output circuit 64s internally connected to the serial input / output port SIO61. The drive signals SDATA0 to SDATA2 are output, and the operation control signals ENABLE0 to ENABLE2 are output via the input / output circuit 64p. For convenience, it is referred to as an input / output port or an input / output circuit, but what actually functions is an output port or an output circuit.

Here, the serial output port SO is configured to have a built-in 16-stage FIFO register. Then, the DMAC circuit 60 is activated by receiving an operation start instruction (see FIG. 22 (b) ST18) from the effect control CPU 63, and the necessary drive data are ordered from the lamp / motor drive table (see FIG. 22 (b)). It is configured to read to and transfer to the FIFO register of the serial output port SO by DMA. The drive data stored in the FIFO register is serially output from the serial output port SO by a clock synchronization method. Although there are a plurality of (for example, 7) DMA channels in the DMAC circuit, the lamp drive data is DMA-transferred by the third DMA channel, which is inferior in priority, and the motor is driven by the first DMA channel, which has the highest priority. It is configured to transfer data by DMA.

The operation control register REG built in the CPU circuit 51 is an 8-bit, 16-bit, or 32-bit long register whose register number (address value) is numbered after 0xFF400000, and can be appropriately WRITE / READ accessible from the effect control CPU 63. (See FIG. 10). Therefore, due to the influence of noise or the like, the operation control register REG may be set to an unreasonable value.

However, for example, the composite chip 50 can be abnormally reset by intentionally executing an infinite loop process to activate the external WDT circuit 58. In this case, the value of the operation control register REG is returned to the same default value (initial value) as after the power is turned on, and the value of the VDP register RGij is also returned to the default value (initial value) for the VDP circuit 52. This will eliminate the abnormal condition.

FIG. 7B is a circuit configuration related to this reset operation, and is a drawing illustrating a reset mechanism characteristic of the present embodiment. In this specification, the VDP register referred to as RGij is not the operation control register REG built in the CPU circuit 51, but any of the control register group 70 (see FIG. 10) that controls the internal operation of the VDP circuit 52. Means. Further, the system control circuit 520 shown in FIG. 7B means an internal control circuit of the VDP circuit 52 that functions based on a set value in the VDP register RGij (any of the control register group 70 in FIG. 10). (See FIG. 7 (a)). The VDP register RGij is positioned in the address space CS7 selected by the chip select signal CS7 in the address map of the effect control CPU 63.

Explaining the reset mechanism based on the above, as shown in FIG. 7B, the composite chip 50 has an internal circuit via three OR gates G2 to G4 that receive the logically inverted system reset signal SYS bar. Is configured to be resettable. However, in this embodiment, as shown by the broken line, the built-in WDT is not enabled, so that the input terminal and the output terminal of the OR gate G2 are directly connected.

In any case, a pattern check circuit CHK is provided between the CPU circuit 51 and the VDP circuit 52, and the pattern check circuit CHK is a predetermined keyword string (a code string for resetting) from the parallel input / output port (PIO) 62. ) Is received, and the reset signal RST is output.

The internal circuit of the composite chip 50 is divided into (1) a CPU circuit 51, (2) a display circuit 74 of the VDP circuit 52, and (3) a display circuit other than the display circuit of the VDP circuit 52, and each of them is OR. It is configured to receive the reset signals of the first reset path to the third reset path from the gates G2 to G4.

First, the OR gate G2 in which the input / output terminals are directly connected is related to the first reset path, and is configured to system reset the entire CPU circuit 51 based on the system reset signal SYS bar. Further, the OR gate G3 is related to the second reset path, and can reset the entire VDP circuit 52 based on the OR logic by receiving the system reset signal SYS bar and the reset signal RST from the pattern check circuit CHK. It is configured in.

This second reset path is used not only for the power reset operation when the power is turned on, but also for the effect control CPU 63 that has detected a predetermined abnormality to perform an abnormality reset of the entire VDP circuit 52 and return it to the initial state. Specifically, when it is determined that a serious abnormality has occurred based on the predetermined status register RGij indicating the internal operation of the VDP circuit 52, a reset signal RST is generated from the pattern check circuit CHK. , The entire VDP circuit 52 is abnormally reset. The display circuit 74 is abnormally reset in the second reset path → the third reset path via the OR gate G4.

On the other hand, the internal circuit built in the VDP circuit 52 is configured to be individually reset when necessary in the fourth reset path. The internal circuits that can be reset individually include the index table IDXTBL shown in FIG. 8A, the data transfer circuit 72, the preloader 73, the display circuit 74, the drawing circuit 76, the SMC circuit 78, and the audio circuit SND. The ICM circuit shown in 13 is included.

The method for realizing the individual reset operation is as described in the lower part of FIG. 7 (b). For example, the display circuit 74 writes the first reset value to a predetermined VDP register RGij (system command register). As a result, the system is reset via the 4th reset path 4A → the 3rd reset path.

Further, each internal circuit (72, 73, 74, 76, SND, ...) Of the VDP circuit 52 sets (1) a set value for specifying the target circuit in the first VDP register RGij (reset RQ register). After writing, (2) the second reset value is written to the predetermined VDP register RGij (system command register), so that the reset values are individually reset (fourth reset path 4B). Although not used in this embodiment, the voice circuit SND can be reset not only by resetting by the fourth reset path 4B but also by writing a reset value to a predetermined VDP register (circuit setting command register) (No. 1). 4 Reset path 4C).

Since this embodiment has the above configuration, not only the entire VDP circuit 52 automatically returns to the initial state when the power is turned on or the program runs out of control, but also each part is returned to the initial state as necessary to cause an abnormal situation. Can be recovered. For example, when the drawing circuit 76 has no READ / WRITE access to the built-in VRAM 71 for a certain period of time, the drawing circuit 76 is individually initialized via the fourth reset path 4B (FIG. 22D). See ST16a). The same applies to the preloader 73 and the data transfer circuit 72. In the event of a predetermined abnormality, the preloader 73 is initialized via the fourth reset path 4B (see ST27 in FIG. 29) and via the fourth reset path 4B. Then, the data transfer circuit 72 is initialized (see ST27 in FIGS. 24 and 29).

Further, regarding the display circuit 74, when the display timing every 1/60 second is followed by an underrun abnormality in which the display data is not generated in time, the fourth reset path 4A or the fourth reset path 4B is used. Via this, the display circuit 74 is individually initialized (see ST10c in FIG. 22). It should be noted that these individual reset operations will be further described later with respect to the program processing described in FIGS. 22 and later.

The reset mechanism characteristic of this embodiment has been described above. However, when any of the reset paths 1 to 4 functions and the internal circuit of the composite chip 50 is reset, the VDP register RGIj corresponding to the internal circuit is reset. The set value of is returned to the same default value as after the power was turned on.

Subsequently, the process returns to the internal configuration of the CPU circuit 51, and the description of the characteristic circuit configuration is continued. FIG. 9 is a block diagram showing the internal configuration of the CPU circuit 51 in a little more detail. The CPU circuit 51 includes many characteristic circuits other than the built-in RAM 59, the DMAC circuit 60, the SIO61, the PIO62, and the WDT described above.

First, the CPU circuit 51 has a CPU fetch bus for instructions and a CPU memory access bus for data separately to realize a Harvard architecture. Therefore, the fetch operation in which the CPU core (effect control CPU) 63 reads the instruction from the memory does not conflict with the memory access operation, and high-speed processing is realized by making the fetch operation continuous.

Further, the CPU core 63 is configured to have a plurality of (for example, 15) register banks RB0 to RB14, and is configured to be able to select whether or not to use them. Then, in the operating state in which the use of the register bank RBi is permitted, the register values (each 32-bit length) of the CPU's built-in registers (for example, 19) are automatically saved to the free register bank RBi at the start of interrupt processing. Will be done.

Further, when a predetermined return instruction is executed at the end of the interrupt process, for example, 19 save data are automatically returned to the corresponding built-in register. Therefore, unlike a normal configuration, it is not necessary to execute the PUSH instruction 19 times at the start of interrupt processing and the POP instruction 19 times at the end of interrupt processing, and high-speed processing is realized.

Further, the CPU circuit 51 of the embodiment realizes a harbored cache operation by providing an instruction cache memory 67, an operand cache memory 89, and a cache controller 69, and has been cached when the same address is accessed. We are trying to further speed up the program processing by utilizing the data of. By providing the bus bridge 65, a controller for the peripheral bus (1), a controller for the peripheral bus (2), and a controller for the peripheral bus (3), the internal bus and the peripheral bus (1) are provided. ), Peripheral bus (2), and peripheral bus (3) are connected as appropriate.

Next, in the circuit configuration of FIG. 9, the bus state controller 66 operates based on an appropriate set value in the operation control register REG, and performs a memory READ operation or a memory with various memory devices connected to the CPU circuit 51. WRITE This is the part that optimizes the operation. The memory READ operation and the memory WRITE operation are executed, for example, at the operation timing illustrated in FIG. 40, but the address data output from the address bus (28Bit), the READ data read to the READ data bus (32Bit), and the READ data are read. The operation timing of the WRITE data written to the WRITE data bus (32Bit) and the control signals such as the chip select signals CS0 to CS7 corresponds to the characteristics of each memory device based on the set value in the operation control register REG. It is stipulated as appropriate.

Since the READ data bus and the WRITE data bus are provided separately, high-speed operation by the Harvard architecture described above is realized. In this specification, the address bus (28Bit), the READ data bus (32Bit), and the WRITE data bus (32Bit) include the internal bus shown in FIG. 9, the peripheral bus (1) to the peripheral bus (3), and the like. In the sense of distinguishing from, it may be collectively referred to as an external bus.

FIG. 10 illustrates the address spaces CS0 to CS7 selected by the chip select signals CS0 to CS7, and illustrates an address map for the effect control CPU 63 accessed via the bus state controller 66. .. First, each of the address spaces CS0 to CS7 is defined as a maximum of 64 Mbytes (= 0x4000000H = 67108864).

As described above, the address spaces CS0 to CS7 mean an external memory for the CPU circuit 51 in which the memory type including the presence or absence of volatility and the data bus width (8/16/32 bits) can be specified respectively. do. In this embodiment, as shown in FIGS. 9B and 10, the control memory (PROM) 53 is the address space CS0, the voice control register SRG of the voice processor 27 is the address space CS3, and the internal register of the clock circuit 38. The SRAM 39 is located in the address space CS4, the external DRAM (DDR) 54 is located in the address space CS5, the work memory 57 is located in the address space CS6, and the VDP register RGij is located in the address space CS7. The description of the address spaces CS1 and CS2 will be omitted.

By the way, as confirmed from FIG. 10, the address spaces CS0 to CS7 are secured not only in the address values 0x00000000 to 0x1FFFFFFF (cache valid space) but also in the address values 0x20000000 to 0x3FFFFFFF (cache invalid space). When the address bit A29 = 1, the cache is invalidated based on the internal operation of the CPU circuit 51, while when the address bit A29 = 0, the cache is enabled, so that the utilization of the cache function can be arbitrarily selected. It is something like that.

Therefore, in this embodiment, among all 32 bits of address information (bits A31 to A0), regardless of whether the value of bit A29 is 1 or 0, the remaining 31 bits (bits A31 to A30 and bits A28 to A0). If the values are the same, the same address in the same memory is specified. For example, the same data is read from the zero address of the work memory 57 regardless of whether the address 0x18000000 is READ-accessed or the address 0x38000000 is READ-accessed. When the address 0x18000000 is READ-accessed, the read data is saved in the cache, but FIG. 9B illustrates the cache valid / invalid access operation.

However, it is also possible to invalidate the cache operation for the instruction cache and / or the operand cache based on the set value in the predetermined operation control register REG. However, in this embodiment, after the power is turned on, the cache operation is invalidated by enabling the cache operation for the instruction cache and the operand cache and then accessing the cache invalid space as necessary.

Continuing the description of the memory map of FIG. 10, after address 0x40000000, the bus state controller 66 is an internal memory space in which the bus state controller 66 does not function, and addresses 0xF0000000 to 0xFF3FFFFF are allocated to the cache address array space. Further, addresses 0xFF400000 to 0xFFFF7FFFF and addresses 0xFFFC0000 to 0xFFFFFFFF are assigned to the built-in peripheral module, and specifically, are assigned to the operation control register REG of the CPU circuit. The address range of the built-in RAM 59 is 0xFFF80000 to 0xFFFBFFFF.

Continuing to explain the internal configuration of the CPU circuit 51, the compare match timer CMT and the multifunction timer unit MTU count external signals supplied to the CPU circuit 51, or multiply or divide the internal clock. It is a circuit that counts clocks and generates an interrupt signal or the like when the count result reaches a predetermined value. Although not particularly limited, in this embodiment, the multifunction timer unit MTU is utilized to generate a 1 mS interrupt signal and a 20 μS interrupt signal. Further, by utilizing the multifunction timer unit MTU, a timekeeping timer TM that measures the elapsed time after the CPU reset is realized.

Next, the interrupt controller INTC receives internal interrupts from the VDP circuit 52, DMAC circuit 60, multifunction timer unit MTU, etc., and external interrupts such as IRQ_CMD, IRQ_SND, and IRQ_RCT, and is based on a predetermined priority. This is a circuit that activates interrupt processing (interrupt handler). Here, IRQ_CMD is a command reception interrupt signal to receive the control command CMD, IRQ_SND is an end interrupt signal indicating that the voice processor 27 has completed the initialization sequence, and IRQ_RCT is an alarm interrupt signal.

In this embodiment, the command reception interrupt IRQ_CMD is the highest level for the interrupt priority. Hereinafter, 20 μS interrupt → 1 mS interrupt → interrupt from the VDP circuit (IRQ0, IRQ1, IRQ2, IRQ3) → DMAC interrupt → IRQ_SND → The order is IRQ_RCT (see Fig. 18 (d)). All of these are maskable interrupts, and the non-maskable interrupt NMI is output to the effect control CPU 63 when the reference clock is not output from the oscillator OSC2, as described above.

Then, in any interrupt processing, the register values (each 32-bit length) of the plurality of built-in registers of the CPU are automatically saved in any of the free register banks RBi. Then, when a predetermined return instruction is executed at the end of the interrupt process, the saved data is automatically returned to the corresponding built-in register.

Subsequently, the DMAC circuit 60 will be described. The DMAC circuit 60 of the embodiment is based on a set value in a predetermined operation control register REG, from a transfer source (Source) to a transfer destination (Destination) in a predetermined DMA transfer mode for each predetermined data transfer unit. In addition, it is a circuit that repeats data transfer a predetermined number of times. It should be noted that DMAC0 to DMACn of a plurality of channels having the same internal configuration are prepared and can be operated in parallel. However, the priority is fixed (channel 0 >> ...> channel n), and during parallel operation in the channel arbitration operation mode, the operation of DMACi, which has a higher priority, is prioritized by channel arbitration at a predetermined timing.

As for the utilization of the DMAC circuit 60, for example, in the embodiment in which the serial output port SO functions (see the broken line portion in FIG. 10A), the operation control register REG of the CPU circuit 51 has the start address of the lamp / motor drive table. (The start value of the transfer source address), the address of the input register of the serial output port SO (fixed value of the transfer destination address), the data transfer unit (8 bits), and the number of transfers are specified. Then, the DMAC circuit 60, which has received the operation start instruction in the predetermined operation control register REG, transfers the drive data to the predetermined transfer destination address by DMA while updating the transfer source address. Then, when all the DMA transfers are completed, a DMAC interrupt (operation end interrupt) is configured to occur.

This point is almost the same in the case of the embodiment (FIGS. 25 and 29 (c)) in which the display list DL is issued by the DMAC circuit 60. That is, the effect control CPU 63 sets the start address of the transfer source (DL buffer BUF), the address of the transfer destination (transfer port TR_PORT), the DMA transfer mode, and the data transfer unit in the predetermined operation control register REG of the CPU circuit 51. , The number of transfers and other conditions will be set. These points will be described later with reference to FIG. 25.

By the way, in general, the DMA transfer mode includes a cycle steel transfer mode in which the DMA operation does not occupy the memory bus, such as releasing the bus control right in the middle of the unit operation (R operation / W operation) of the DMA transfer, and a plurality of Rs. Between the burst transfer (pipeline transfer) mode in which the bus control right is not released until the specified number of transfers is completed, such as continuous operation and W operation, and the DMA transfer request (demand) received from another device is active. A demand transfer mode that continues the DMA operation can be considered. However, the DMAC circuit 60 of this embodiment functions in the cycle stealing transfer mode in which a memory release period of at least one cycle is provided between the read access activation (R operation) and the write access activation (W operation) at the time of DMA transfer. By doing so, the operation of the effect control CPU 63 is not hindered.

FIG. 11 is a drawing illustrating a cycle steal transfer operation (a1) and a pipeline transfer (a2). As shown in FIG. 11 (a1), the DMAC circuit 60 functioning in the cycle stealing transfer mode operates at least one cycle between the read access activation (R) and the write access activation (W) of one data transfer. In this vacant cycle, the bus of the effect control CPU 63 can be used. As is clear from the contrasting relationship between FIGS. 11 (a1) and 11 (a2), in pipeline transfer, the bus is not released to the CPU until one cycle (one operand transfer) is completed, whereas cycle stealing is performed. In the transfer mode, the bus is opened to the CPU for each read access, so that the operation of the CPU is not significantly delayed.

Then, for example, in the embodiment in which the DMAC circuit 60 is used when the display list DL is issued to the VDP circuit 52, the data transfer unit (1 operand) for one cycle is set to 32 × 2 bits, and the display list DL is stored. While increasing the source address of the built-in RAM 59 as appropriate (+8 for each operand transfer), the DMA transfer operation is performed for the transfer port register TR_PORT (see FIG. 13) of the data transfer circuit 72 specified by the fixed address. Is running.

As will be described later, in the embodiment, by adding the required number of NOP (no operation) commands to the display list DL, the entire data size is set to a fixed value (for example, 4 × 64 = 256 bytes or an integer thereof). It is adjusted to double), and the issuance of the display list DL is completed by repeating one operand transfer of 32 bits × 2 times 32 times (or an integral multiple thereof). Even if the drawing circuit 76 executes the NOP command, it is in the no operation state and virtually no change occurs.

Further, when the operation modes are classified with respect to the DMA transfer conditions, generally, single operand transfer (see FIG. 11 (b1)), continuous operand transfer (see FIG. 11 (b2)), and non-stop transfer (see FIG. 11 (b3)). See).

Here, the single operand transfer means, as shown in FIG. 11 (b1), when the byte count for counting the number of transferred bytes becomes zero by repeating the transfer of one operand each time a DMA transfer request is given. This means an operation mode in which a DMA interrupt request is generated. Next, the continuous operand transfer means an operation mode in which the DMA transfer is repeated until the byte count becomes zero with one DMA request, as shown in FIG. 11 (b2).

In these continuous operand transfers (b2) and single operand transfers (b1), channel arbitration is performed every time one operand transfer is completed, and the current channel is provided on the condition that there is no DMA request for the channel with high priority. Transfer continues (channel arbitration operation mode). Therefore, in this embodiment, a single operand transfer method is adopted for issuing the display list DL to the VDP circuit and for DMA transfer of lamp drive data and motor drive data. Then, at the time of parallel operation, for example, DMACi of the optimum channel is used so that the channel arbitration of the priority of motor data> display list DL> lamp data.

On the other hand, non-stop transfer is an operation mode in which channel arbitration is not executed, and as shown in FIG. 11 (b3), DMA transfer is continuously repeated until the byte count becomes zero with one DMA request. Is done. In this embodiment, in the memory section initialization process (SP8 in FIG. 16) when the power is turned on, the program or data is DMA-transferred by non-stop transfer.

Since the CPU circuit 51 has been described above, the VDP circuit 52 will be described next. The VDP circuit 52 includes a CGROM 55 for storing compressed data which is a component of still images and moving images constituting an image effect, and about 4 Gbit. An external DRAM (Dynamic Random Access Memory) 54 having a storage capacity of the above, a main display device DS1 and a sub display device DS2 are connected to each other. The DRAM 54 is preferably composed of DDR3 (Double-Data-Rate3 SDRAM).

Here, the DDR 54 receives the DDR clock generated based on the oscillation output (40 MHz) of the oscillator OSC2, as shown in FIG. 14 (b). Further, the DRAM 54 of the embodiment has a built-in refresh counter, and the self-refresh function (Self-Refresh Operation) is enabled at the time of initial setting (SP4 in FIG. 16), so that the effect control CPU 63 The refresh control operation by is not necessary.

Although not particularly limited, in this embodiment, the CGROM 55 is composed of a flash SSD (solid state drive) composed of a NAND flash memory having a storage capacity of about 62 Gbit, and is compressed data required for serial transmission. Is configured to get. Therefore, the problem of skew (difference in transmission speed for each bit data) that inevitably occurs in parallel transmission is solved, and extremely high-speed transmission operation becomes possible. Although not particularly limited, in this embodiment, the CGROM 55 is accessed at high speed by the HSS (High Speed Serial) method compliant with Serial ATA.

Regardless of whether or not the HSS method compliant with SerialATA is adopted, the NAND type flash memory is mechanically more stable than the hard disk and can be accessed at high speed, but is a sequential access memory. Compared to DRAM and SRAM (Static Random Access Memory), there is a problem with random accessibility. Therefore, in this embodiment, by executing a preload operation in which a group of compressed data (CG data) is read out to the DRAM 54 prior to the drawing operation, smooth random access of the CG data during the drawing operation is realized. ing. By the way, the access speed becomes slower in the order of built-in VRAM> external DRAM> CGROM.

In detail, the VDP circuit 52 includes a control register group 70 in which various operation parameters defining the operation of the VDP (Video Display Processor) can be set by the effect control CPU 63, and image data to be displayed on the display devices DS1 and DS2. Regarding the built-in VRAM (video RAM) 71 of about 48 Mbytes used at the time of generation, the data transfer circuit 72 that executes data transmission / reception between each part inside the chip and data transmission / reception with the outside of the chip, and the built-in VRAM 71, the Source and Destination An index table IDXTBL that can specify address information, a preloader 73 that can execute a preload operation that READ-accesses the CGROM 55 prior to the drawing operation, and a graphics decoder that decodes (decodes / decompresses / expands) the compressed data read from the CGROM 55. (GDEC) 75, the drawing circuit 76 that generates image data for each frame of the display devices DS1 and DS2 by appropriately combining the still image data and the moving image data after decoding (decompression), and the operation of the drawing circuit 76. As a part, three systems that can read the image data of the frame buffers FBa and FBb generated by the geometry engine 77 that generates a stereoscopic image by appropriate coordinate conversion and the drawing circuit 76 and execute appropriate image processing in parallel. (A / B / C) display circuits 74A to 74C, an output selection unit 79 that appropriately selects and outputs the outputs of the three systems (A / B / C) display circuits 74, and an image output by the output selection unit 79. The LVDS unit 80 that converts data into an LVDS signal, the SMC unit 78 that can transmit and receive serial data, the CPUIF unit 81 that relays data transmission and reception between the CPUIF circuit 56, and the CG bus IF unit 82 that relays data reception from the CGROM 55. A DRAMIF unit 83 that relays data transmission / reception with the external DRAM 54 and a VRAMIF unit 84 that relays data transmission / reception with the built-in VRAM 71 are provided (see FIG. 8A). The audio circuit SND is also built-in.

FIG. 8B illustrates the relationship between the CPU IF unit 81, the CG bus IF unit 82, the DRAM IF unit 83, and the VRAM IF unit 84, and the control register group 70, the CGROM 55, the DRAM 54, and the built-in VRAM 71. As shown in the figure, the CG data acquired from the CGROM 55 is transferred as preload data to the preload area of the external DRAM 54 via the data transfer circuit 72 and the DRAM IF unit 83, for example.

However, the above-mentioned preload operation is not an essential operation, and the data transfer destination is not limited to the external DRAM 54 and may be the built-in VRAM 71. Therefore, for example, in the embodiment in which the preload operation is not executed, the CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and the VRAM IF unit 84 (FIG. 8 (b)).

By the way, in this embodiment, the built-in VRAM 71 stores image data for specifying the expansion area of the compressed data read from the CGROM 55 and each ARGB information (32 bits = 8 × 4) of W × H display pixels of the display device. A frame buffer area to be used, a Z buffer area for storing depth information of each display pixel, and the like are required. In the ARGB information, A means 8-bit α-plane data, and RGB means 8-bit data of the three primary colors.

Here, each of the above-mentioned areas of the built-in VRAM 71 is indirectly accessed by the effect control CPU 63 based on various instruction commands (such as the above-mentioned texture and SPRITE) described in the display list DL, and the READ / WRITE access thereof. In, it is complicated to specify the Destination address and the Source address of the built-in VRAM 71 one by one. Therefore, in this embodiment, in the initial processing after the CPU reset, a one-dimensional or two-dimensional logical address space (hereinafter referred to as an index space) required for drawing operation is secured, and an index number is assigned to each index space. By doing so, access based on the index number is possible.

Specifically, after the CPU is reset, the built-in VRAM 71 is roughly divided into three types of memory areas, and a required number of index spaces are secured in each memory area. Then, by constructing the index table IDXTBL (see FIG. 12A) that stores the index space and the index number in association with each other, the operation based on the subsequent index number is realized.

It is also necessary to (1) add this index space after the initial processing, and conversely, (2) open it. Therefore, a flag capable of determining whether or not the addition / release processing is possible and whether or not the addition / release processing is actually completed during the operation of the addition / release effect control CPU 63 is possible. The area FG is provided in the index table IDXTBL. The built-in VRAM 71 is roughly divided into three types of memory areas, two AAC areas (a1 and a2), a page area (b), and an arbitrary area (c), which will be described below, and these three types of memory areas. Corresponding to (a1, a2) (b) (c), the index table IDXTBL is divided into three categories (FIG. 12 (a)). As shown in the figure, in this embodiment, the first AAC region (a1) and the second AAC region (a2) are secured as the AAC region (a), but the region is not particularly limited, and only one of them is used. But it's okay. In the following description, when the first and second AAC regions (a1, a2) are collectively referred to, they may be referred to as an AAC region (a).

In the case of this embodiment, the built-in VRAM 71 has (a) an index space and an AAC area in which the index number is automatically assigned by internal processing and has a memory cache function, and (b) a two-dimensional space of, for example, 4096 bits × 128 lines. The unit space can be divided into a page area where an index space can be secured within a range of integral multiples thereof, and (c) an arbitrary area where the start address (space start address) STx and the horizontal size Hx can be arbitrarily set. (See FIG. 12 (b)). However, in order to facilitate the internal operation of the VDP circuit 52, the space head address STx of the index space arbitrarily set in the arbitrary area (c) has a lower 11 bits of 0 and a predetermined bit (2048 bits = 256 bytes). Must be a unit.

Then, after the CPU reset, the maximum value of the address space required for each and the area start address (lower 11 bits = 0) are defined, and the AAC area (a1), the second AAC area (a2), and the page area (a2) are specified. b) is secured, and the remaining memory area becomes an arbitrary area (c). In order to facilitate the internal operation of the VDP circuit 52, the maximum value of the address space in the AAC area is defined in units of 2048 bits, and the maximum value of the address space in the page area is an integral multiple of the unit space of the above-mentioned 4096 bits × 128 lines. It is said that.

Next, the required number of index spaces are set in each of the areas (a1, a2) (b) (c) secured in this way. When the arbitrary area (c) is used, the horizontal size Hx of the index space that handles two-dimensional data can be arbitrarily set as a multiple of 256 bits in order to facilitate the internal operation of the VDP circuit 52. Its vertical size is a fixed value (eg, 2048 lines).

In any case, the index space and the index number are automatically assigned to the first and second AAC regions (a1, a2) by the VDP circuit 52. Therefore, for example, by the SETINDEX command of the texture setting command, the index space and the index number are automatically assigned. If the decoding destination is specified in the AAC area (a), the TXLOAD (texture load) command that reads CG data from the CGROM55 only needs to specify the Source address of the CGROM55 and the horizontal / vertical size after expansion (decoding). It will be. Therefore, in this embodiment, the decoding destination of a still image (texture) such as a character that temporarily appears at the time of a preview effect or an I-stream moving image is set to the AAC area (a).

Since the memory cache function is added to each of the AAC areas (a), for example, when the same texture of the CGROM 55 is read into the AAC area (a) multiple times, the second and subsequent times may be performed. The decoded data cached in the AAC area (a) can be utilized, and extra READ access and decoding processing can be suppressed. However, when the AAC area (a) is used up, old data is automatically destroyed. Therefore, in this embodiment, when the AAC area (a) is used, the first AAC area (a1) is used in principle. It is decided to use it, and only a specific texture to be used repeatedly is acquired in the second AAC region (a2).

As the texture to be used repeatedly, for example, a character that repeatedly appears at the time of a predetermined advance notice effect, a background image when the background screen is constructed from a still image, and the like can be exemplified. In such a case, the SETINDEX command, which is a texture setting command, sets the decoding destination to the second AAC area (a2), and the TXLOAD command decodes the texture such as characters and background images to the second AAC area (a2). After that, the decoding result is protected by not using the second AAC region (a2).

After that, if you specify the decoding destination in the second AAC area (a2) with the SETINDEX command and then execute the same TXLOAD command to reacquire the acquired texture, the acquired texture will be cache hit. , READ access to the CGROM 55 and the time required for the decoding process can be deleted. As will be described later, such a cache hit function is also exhibited in the preload data pre-read in the preload area, but the cache hit preload data in the preload area is compressed data before decoding, whereas AAC. It is significant that the cache hit in the area is the expanded data after decoding.

By the way, texture is a concept that generally refers to the texture and texture of the surface of an object, but in the present specification, sprite image data constituting a still image, image data constituting one frame of a moving image, and the like are used. , It is used as a concept that includes not only image data to be pasted on drawing primitives such as triangles and squares, but also image data after decoding. When copying image data inside the built-in VRAM71 (hereinafter referred to as "move" for convenience), use the SETINDEX command of the texture setting command to set the image data of the move source as a texture and then use the SPRITE command. Will be executed.

By executing the SPRITE command, the source image data of the movement source is formally drawn in the virtual drawing space shown in FIG. 12 (c), but the drawing in the virtual drawing space actually drawn on the display device is performed. If the correspondence between the area and the index space that serves as the frame buffer is set in advance using environment setting commands (SETDAVR, SETDAVF) or texture setting commands (SETINDEX), for example, the SPRITE command can be used to create a virtual drawing space. By drawing, the source image data of the movement source is drawn in the predetermined index space (frame buffer) (see FIG. 12 (c)).

In any case, in this embodiment, the built-in VRAM 71 is roughly divided into an AAC area (a1, a2), a page area (b), and an arbitrary area (c), and an appropriate number of index spaces are secured for each. And each index space is specified by an independent index number for each region (a) (b) (c). The index number is, for example, 1 byte long, and the page area (b) and the arbitrary area (c) (excluding the AAC area (a) automatically assigned by the internal circuit) are produced in the range of 0 to 255. The control CPU 63 can freely assign an index number.

Therefore, in this embodiment, as shown in FIG. 12A, a pair of frame buffers FBa are secured in the arbitrary area (c) for the display device DS1, and the index numbers 255 and 25 are used in both of the double buffer structures. 254 is given. That is, as the frame buffer FBa for the main display device DS1, the index space 255 and the index space 254 used by switching in a toggle manner are secured. Although not particularly limited, the index spaces 255 and 254 have a horizontal size of 1280 corresponding to the number of horizontal pixels of the display device DS1. Since each pixel is specified by ARGB information 32 bits, the horizontal size 1280 means 32 × 1280 = 40960 bits (a multiple of 256 bits).

Further, for the display device DS2, another pair of frame buffers FBb is secured in the arbitrary area (c), and index numbers 252 and 251 are assigned to both of the double buffer structures. That is, the index space 252 and the index space 251 are secured as the frame buffer FBb for the sub display device DS2. The index spaces 252 and 251 have a horizontal size of 480 corresponding to the number of horizontal pixels of the display device DS2. Also in this case, since each pixel is specified by the ARGB information 32 bits, the horizontal size 480 means 32 × 480 = 15360 bits (multiple of 256 bits).

The frame buffers FBa and FBb are secured in the arbitrary area (c) by setting the arbitrary area (c) to an arbitrary horizontal size as a multiple of 32 bytes (= 256 bits = 8 pixels). This is because, as described above, if the number of horizontal pixels of the display devices DS1 and DS2 is matched, the reserved area is not wasted. On the other hand, in the page area (b), only the horizontal / vertical size that is an integral multiple of the unit space of 128 pixels × 128 lines can be set.

However, the vertical size of the two-dimensional index space secured in the arbitrary region (c) is a fixed value (for example, 2048 lines). Therefore, in the frame buffer FBa, only the area of horizontal size 1280 × vertical size 1024 is an effective data area for the main display device DS1. This point is the same for the sub-display device DS2, and in the frame buffer FBb, only the area of the horizontal size 480 × the vertical size 800 is an effective data area for the sub-display device DS2 (FIGS. 12 (c) and 22). See (e)).

The above points will be further described later, but in any case, in the frame buffers FBa and FBb, each double buffer (255/254, 252/251) is alternately used as a drawing area for the drawing circuit 76, and the frame buffers FBa and FBb are used alternately. The double buffers (255/254, 252/251) are alternately used as the display area for the display circuits 74A and 74B. In this embodiment, since the Z buffer that stores the depth information of the display pixel is not used, a missing number (253) occurs. However, when the Z buffer is used, the index number 253, 250 in the arbitrary area (c) is used. The index space 253,250 serves as a Z buffer for the display device DS1 and the display device DS2.

Further, in this embodiment, when an additional index space (memory area) is secured in the arbitrary area (c) in which the frame buffers FBa and FBb are secured, an index number starting from 0 is assigned. .. Although not limited in any way, in the present embodiment, as a work area for a preview effect in which an effect image composed of a character or other still images appears on a part of a display screen in an appropriate rotation posture as needed. The index space (0) is secured in the arbitrary area (c).

However, it is not essential to use the work area, and instead of the arbitrary area (c), an index space as a work area may be secured in the page area (b). If the page area (b) is used, an index space having an index space that is a multiple of a square unit space having a horizontal size of ¹²⁸ (= 4096 bits) × a vertical size of 128 can be secured, which is suitable for handling a small production image. ..

By the way, in this embodiment, the image is composed of a moving image including a background image, and the image production is realized only by the moving image. In particular, a large number (usually 10 or more) of moving images are drawn at the same time during the variable effect. All of these videos are stored in the CGROM 55 in a compressed state as a series of video frames, but an I-stream video composed of only I-frames and an IP stream video composed of I-frames and P-frames. It is divided into. Here, the I frame (Intra coded frame) means a frame that compresses the input image as it is, independently of other screens. On the other hand, the P frame (Predictive coded frame) means a frame for performing forward predictive coding, and an I frame or a P frame located in the past in time is required.

Therefore, in this embodiment, the IP stream moving image is developed not in the AAC area (a) where there is a concern about the destruction of old data, but in the page area (b). That is, a large number of index spaces (IDX ₀ to IDX _N ) are secured in the page area (b) where an index space having a multiple dimension of horizontal size 128 × vertical size 128 can be secured, and a series of video frames are each video. The same index space IDXi corresponding to MVi is always used for decoding. That is, the moving image MV1 is expanded in the index space IDX1, the moving image MV2 is expanded in the index space IDX2, and similarly, the moving image MVi is configured to be expanded in the index space IDXi.

To explain the moving image MVi more specifically, the SETINDEX command specifies in advance that the decoding destination of the IP stream moving image MVi is the index space (i) of the index number i in the page area (b). The TXLOAD command to acquire one frame of the IP stream video MVi video is executed.

Then, one video frame (any of a series of video frames) on the CGROM 55 specified by the TXLOAD command is first acquired in the AAC area (a), and then automatically activated by the GDEC (graphics decoder) 75. , One frame of the acquired video is decoded and expanded in the index space (i) of the page area (b).

On the other hand, in this embodiment, the I-stream moving image is treated the same as the still image, and the SETINDEX command is used to specify that "the decoding destination of the I-stream moving image MVj is the first AAC area (a1)". Execute the TXLOAD command. As a result, the moving image frame is acquired in the first AAC area (a1), and then the automatically activated GDEC75 expands the decoded data in the first ACC area (a1). As described above, the index space of the AAC area (a) is automatically generated, so it is not necessary to specify the index number. The expansion volume required for the index space, that is, the horizontal size and vertical size of the decoded texture (video frame), is TXLOAD regardless of whether the expansion destination is the AAC area (a) or the page area (b). Specified by the command.

By the way, the IP stream moving image MVi and the I stream moving image MVj are generally composed of N moving image frames (I frame and P frame). Therefore, in the TXLOAD command, for example, the Source address of the CGROM 55 in which the kth (1 ≦ k ≦ N) moving image frame is stored, the horizontal / vertical size after expansion, and the like are specified. Although not limited in any way, in the embodiment in which the still image is scarcely used, most of the address space 48 Mbytes (about 30 Mbytes) of the built-in VRAM 71 is allocated to the page area (b). In the embodiment in which the still image is hardly used, only the first AAC region (a1) is secured as the AAC region, the second AAC region (a2) is not secured, and the cache hit function of the above-mentioned AAC region is secured. Do not utilize.

In addition, in order to speed up the decoding process of the compressed moving image data, it is conceivable to provide a dedicated GDEC (graphics decoder) circuit. Then, if a dedicated GDEC circuit is built in the VDP circuit 52, it is sufficient to indicate the start address of the video compressed data to the GDEC circuit in the decoding process of the compressed video data composed of N compressed video frames. It is no longer necessary to specify the start address for each of the N compressed video frames.

However, if a plurality of such dedicated GDEC circuits are built in for each compression algorithm, the internal configuration of the VDP circuit 52 is further complicated. Therefore, in this embodiment, software GDEC is used, and decoding processing is realized for data such as IP stream moving image, I stream moving image, still image, and other α values by software processing corresponding to each compression algorithm. The processing time difference between the hardware processing and the software processing does not matter so much, and the processing time becomes a problem mainly in the access (READ) time from the CGROM 55.

Subsequently, returning to FIG. 8A and continuing the description, the data transfer circuit 72 uses a resource (storage medium) inside the VDP circuit and an external storage medium as a transfer source port or a transfer destination port between them. It is a circuit that executes a data transfer operation like DMA (Direct Memory Access). FIG. 13 is a block diagram showing the internal configuration of the data transfer circuit 72 together with the related circuit configurations.

As shown in FIG. 13, the data transfer circuit 72 is configured to transmit / receive data to / from the CGROM 55, the DRAM 54, and the built-in VRAM 71 via the integrated connection bus ICM having a router function. The CGROM 55 and the DRAM 54 are accessed via the CG bus IF unit 82 and the DMAMIF unit 83.

On the other hand, the CPU circuit 51 issues a display list DL to the drawing circuit 76 and the preloader 73 via the transfer port register TR_PORT built in the data transfer circuit 72. The CPU circuit 51 and the data transfer circuit 72 are connected in both directions, but when the display list DL is issued, the transfer port register TR_PORT is used as a data write port for receiving one unit of data constituting the display list DL. Function. The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits corresponding to the FIFO structure of the CPU bus control unit 72d.

As shown in the figure, the effect control CPU 63 can access the transfer port register TR_PORT by WRITE via the CPUIF unit 81, while when the DMAC circuit 60 is utilized, the DMAC circuit 60 directly accesses the transfer port register TR_PORT. WRITE access will be made. The series of instruction commands written in the transfer port register TR_PORT (that is, the instruction command sequence constituting the display list DL) is a CPU bus having a built-in FIFO buffer having a FIFO structure (32 bits x 130 stages) in units of 32 bits. It is configured to be automatically stored in the control unit 72d.

Further, the data transfer circuit 72 executes a data transmission / reception operation on a transmission path of 3 channels ChA to ChC, and has a FIFO structure (64 bits × N stages) of a ChA control circuit 72a (N = 130). Stage), a ChB control circuit 72b (N = 1026 stages), and a ChC control circuit 72c (N = 130 stages).

The instruction command sequence (display list DL) stored in the CPU bus control unit 72d is the drawing circuit 76 or the drawing circuit 76 based on the set value in the data transfer register RGij (a type of various control registers 70) by the effect control CPU 63. It is transferred to the preloader 73. As shown by the arrow, the display list DL is transferred from the CPU bus control unit 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b, and transferred to the preloader 73 via the FIFO buffer of the ChC control circuit 72c. It is configured to be.

In this embodiment, the ChB control circuit 72b and the ChC control circuit 72b are specialized for the transfer operation of the display list DL, and the data stored in the FIFO buffer of the CPU bus control unit 72d is the ChB control circuit. It is transferred to the drawing circuit 76 or the display list analyzer of the preloader 73 as a part of the display list DL, respectively, via the 72b or the FIFO buffer of the ChC control circuit 72c.

Then, the drawing circuit 76 starts a drawing operation based on the transferred display list DL. On the other hand, the preloader 73 executes a necessary preload operation based on the transferred display list DL. By the preload operation, the CG data of the CGROM 55 is read ahead to the preload area secured in the DRAM 54, and the display list DL (hereinafter referred to as the rewrite list DL') in which the source address of the texture is changed is secured in the DRAM 54 with respect to the TXLOAD command or the like. It is saved in the DL buffer area BUF'.

On the other hand, the ChA control circuit 72a and the connection bus access arbiter circuit 72e function for data transfer between storage media such as the CGROM 55, the DRAM 54, and the built-in VRAM 71. Further, the IDXTBL access arbiter circuit 72f functions when the built-in VRAM 71, which requires the address information of the index table IDXTBL, is accessed. Specifically, the ChA control circuit 72a may, for example, (a) transfer the compressed data of the CGROM 55 to the built-in VRAM 71, or (b) preload (pre-read) the compressed data of the CGROM 55 and transfer the compressed data to the external DRAM 54. In some cases, or (c) it functions when transferring the look-ahead data in the preload area to the built-in VRAM 71.

Here, the ChA control circuit 72a is configured to be operable in parallel with the ChB control circuit 72b and the ChC control circuit 72c, and the above-mentioned operations (a) to (c) are the display list DL issuance operations ( It can be executed in parallel with ST8 in FIG. 22 and PT11 in FIG. 27) and the transfer operation of the rewrite list DL'(PT10 in FIG. 27). Further, the ChB control circuit 72b and the ChC control circuit 72c can also be executed at the same time. For example, the processing of step PT10 in FIG. 27 in which the ChB control circuit 72b functions and the processing in step PT11 in which the ChC control circuit 72c functions are performed in parallel. It is feasible. However, since the forwarding port register TR_PORT is single, when one (72b / 72c) is using the forwarding port register TR_PORT, the other (72c / 72b) should access the forwarding port register TR_PORT. Can't.

When the ChA control circuit 72a is operating, the connection bus access arbitration circuit 72e arbitrates data transmission with each storage element (CGROM55, DRAM54) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 72f arbitrates data communication with the built-in VRAM 71 by controlling the ChA control circuit 72a based on the index table IDXTBL. In the case of the embodiment in which the preloader 73 functions, the rewrite list DL'stored in the DL buffer area BUF' of the DRAM 54 is transferred to the drawing circuit 76 via the connection bus access arbiter circuit 72e and the ChB control circuit 72b. (See FIG. 28 (b)).

As described above, the data transfer circuit 72 of the present embodiment has a data transfer source arbitrarily selected from various storage resources (Resource) and a data transfer destination arbitrarily selected from various storage resources (Resource). High-speed data transfer is realized between them. As confirmed from FIG. 13, the storage resource in which the data transfer circuit 72 functions includes not only the built-in VRAM 71 but also an external device via the CPU IF unit 56, the CG bus IF unit 82, and the DRAM IF unit 83.

Then, the amount of data transferred to an external device on which the ChA control circuit 72a functions, such as the amount of data to be acquired from the CGROM 55 at one time (memory sequential READ), is the display on which the ChB control circuit 72b and the ChC control circuit 72c function. It is enormous as compared with the case of the list DL, and the amount of data transfer differs greatly from each other.

Here, for these various types of data transfer, it is conceivable to configure the unit data amount and total transfer data amount to be finely set, but this complicates the control operation inside the VDP and facilitates smooth transfer operation. Be hindered. Therefore, in this embodiment, the minimum data amount Dmin for data transfer is uniquely defined, and the total transfer data amount is limited to an integral multiple of the minimum data amount DTmin, so that high-speed and smooth data transfer operation can be performed. It has been realized. Although not particularly limited, in the data transfer circuit 72 of the embodiment, the minimum data amount Dmin (unit data amount) is 256 bytes, and the total transfer data amount is limited to an integral multiple of this.

Therefore, the instruction command sequence of the display list DL stored in the FIFO buffer of the CPU bus control unit 72d every 32 bits is transferred to the ChB control circuit 72b or the ChC control circuit 72b at the timing when the total amount reaches the minimum data amount Dmin. Will be stored in each FIFO buffer.

The display list DL is composed of a series of instruction commands, but in this embodiment, the command length of the display list DL is an integer N times of 32 bits corresponding to the write unit (32 bits) of the transfer port register TR_PORT. It consists only of the instruction command (N> 0). Therefore, the drawing circuit 76 and the preloader 73 that receive the instruction command of the display list DL via the data transfer circuit 72 can start the command analysis process (DL analyze) quickly and smoothly. It should be noted that the command length of a 32-bit integer N times does not mean that all of them are significant bits, but also includes an involuntary bit (Don't care bit), which means a 32-bit integer N times.

Next, the preloader 73 will be described. As outlined above, the preloader 73 interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72b) and preliminarily converts the CG data on the CGROM 55 referenced by the TXLOAD command into the DRAM 54. It is a circuit to transfer to the preload area of. Further, the preloader 73 stores the rewrite list DL'in which the reference destination of the CG data is rewritten to the address after the transfer in the DL buffer BUF' of the DRAM 54 with respect to this TXLOAD command. The DL buffer BUF'and the preload area are secured in advance at the time of initial processing after the CPU reset (SS3 in FIG. 21).

Then, the rewrite list DL'is a display list analyzer (DL Analyzer) of the drawing circuit 76 via the connection bus access arbiter circuit 72e of the data transfer circuit 72 and the ChB control circuit 72b at the start of the drawing operation of the drawing circuit 76. ). Then, the drawing circuit 76 executes the drawing operation based on the rewrite list DL'. Therefore, based on the TXLOAD command or the like, the CG data that should be originally acquired from the CGROM 55 is acquired from the preload area of the DRAM 54 as the preload data that is pre-read in the preload area. In this case, the preload data can be used repeatedly unless it is overwritten and erased, and the preload data cache-hit in the preload area is repeatedly reused.

In this embodiment, since the preload area is set in the external DRAM 54 having a sufficient storage capacity, the above cache hit function functions effectively. Further, since the storage capacity of the external DRAM 54 is large, for example, multiple preloads that preload CG data for a plurality of frames at once are possible. That is, regarding the operation period of the preloader 73, the operation period of a series of preload operations including the look-ahead operation of CG data is appropriately set within a range of an integral multiple of the operation cycle δ at the time of intermittent operation of the VDP circuit 52. Multiple preloads are realized with.

However, in the following description, for convenience, an embodiment without multiple preloads will be described. Therefore, the preloader 73 of the embodiments will complete the preload operation for one frame during one operation cycle (δ). As will be described later with reference to FIG. 22, in this embodiment, the operation cycle δ during the intermittent operation of the VDP circuit 52 is 1/30 second, which is twice the period of the vertical synchronization signal of the display device DS1.

Next, the drawing circuit 76 sequentially analyzes the instruction command sequence of the display list DL and the rewriting list DL'transferred via the data transfer circuit 72, and cooperates with the graphics decoder 75, the geometry engine 77, and the like. Then, it is a circuit that draws an image for one frame of each display device DS1 and DS2 in the frame buffer formed in the VRAM 71.

As described above, in the embodiment in which the preloader 73 is made to function, the reference destination of the CG data in the rewrite list DL'is not the CGROM 55 but the preload area set in the DRAM 54. Therefore, the sequential access to the CG data generated during the execution of drawing by the drawing circuit 76 can be quickly executed, and even a high-resolution moving image with intense movement can be drawn without any problem. That is, according to this embodiment, as the CGROM 55, it is possible to perform complicated and advanced image production while utilizing an inexpensive SATA module.

By the way, regardless of whether or not the preloader 73 is made to function, even if data garbled occurs during transfer of the display list DL or the rewrite list DL', the drawing circuit 76 cannot detect this. In addition, the drawing circuit 76 may freeze due to the influence of noise or the like, and the READ / WRITE access of the built-in VRAM 71 may stop abnormally. Therefore, in this embodiment, if the drawing circuit 76 detects an irrational instruction command (bit sequence that cannot be analyzed), or if there is no READ / WRITE access to the built-in VRAM 71 for a certain period of time, a drawing error interrupt is interrupted. Is configured to generate (drawing error interrupt is enabled). This point will be described later with respect to FIG. 22 (d).

Next, as described with respect to FIG. 12, the frame buffer FB secured in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a reading area, and the two areas are alternately used. To use. Further, in the present embodiment, since the two display devices DS1 and DS2 are connected, the frame buffers FBa / FBb of two sections are secured as shown in FIG. Therefore, the drawing circuit 76 draws image data for one frame in the drawing area (writing area) of the frame buffer FBa for the display device DS1 and draws the image data for one frame and draws the image data of the frame buffer FBa for the display device DS2 (writing area). In addition, one frame of image data will be drawn. When the image data is written in the drawing area, the display circuit 74 reads the image data in the other read area (display area) and outputs the image data to the display devices DS1 and DS2.

The display circuit 74 is a circuit that reads out the image data of the frame buffers FBa and FBb, performs final image processing, and outputs the data (see FIG. 14A). The final image processing includes, for example, a scaler scaling process for enlarging / reducing the image, a subtle color correction process, and a dithering process for minimizing the quantization error of the entire image. Then, the digital RGB signal (24 bits in total) that has undergone these image processing is usually output together with the horizontal sync signal HS, the vertical sync signal VS, and the like.

As shown in FIG. 14A, in this embodiment, three display circuits A / B / C for executing the above operations in parallel are provided, and the display circuits 74A to 74C correspond to each of them. The image data of the frame buffer FBa / FBb / FBc is read out, and the above final image processing is executed. However, in this embodiment, since there are two display devices, the frame buffer FBc is not secured and the display circuit 74C does not function.

Here, when the specifications of the main display device DS1 are confirmed, the main display device DS1 passes odd pixels (ODD) and even pixels (EVEN) adjacent to each other in the left-right direction through separate LVDS (Low Voltage Differential Signaling) transmission lines. It needs to be received by the receiving unit RV (RVa + RVb). Further, the frequency of the operation clock CK of the main display device DS1 needs to be about 40 to 70 MHz (typical value 54 MHz), and is horizontal / vertical so that (WTh + 640) × (WTv + 1024) / 54 MHz ≈ 1/60 second. It is necessary to set the waiting time WTh / WTv in the direction. Further, at the timing of outputting the image data (ODD / EVEN signal) to the main display device DS1, it is necessary to output the active level data valid signal ENAB.

Therefore, the display circuit 74A needs to output a signal satisfying all the above specifications. 15 (a) to 15 (e) show various signals output from the display circuit 74A. First, it is necessary to determine the frequency of the dot clock (LVDS clock) DCK. In this embodiment, the main display device DS1 is operated with an operating clock CK having a typical value of 54 MHz. The design dot clock DCK (in the circuit 52) is set to 108 MHz (= 54 × 2).

This is because in the display panel LCD (see FIG. 15F) having 1280 dots horizontally and 1024 lines vertically, two pixels adjacent to the left and right are processed at once in synchronization with the 54 MHz operating clock CK, so that it is substantially processed. Is equivalent to operating with a 108 MHz dot clock DCK.

The various operating parameters that define the operation of the display circuit 74A are defined based on the dot clock DCK having a frequency of 108 MHz. First, it is necessary to set the standby time WTh / WTv in the horizontal / vertical direction so that (WTh + 640) × (WTv + 1024) / 54 MHz ≈ 1/60 seconds. , (WTh + 1280) × (WTv + 1024) / 108 MHz ≈ 1/60 second must be satisfied.

Further, it is necessary to consider the allowable range in the specifications of the display device DS1 for the standby time WTh / WTv in the horizontal / vertical direction. Therefore, in this embodiment, the horizontal standby time WT is counted by the dot clock DCK of 108 MHz to be 382 clocks, and the vertical standby time WTv is 59 lines. Therefore, the time required to update the image of one frame is (382 + 1280) × (59 + 1024) / 108 MHz = 16.666 mS, and the frame rate FR (Frame Rate) is 1/60 second.

This relationship defines the update cycle FR [seconds] of the display device DS1, and when the frequency F _dot of the dot clock DCK described later, the number of cycles of horizontal synchronization THc, and the number of lines of vertical synchronization TVl are used, FR = THc × TVl / F _dot . If the update cycle FR is too long, an abnormality such as flicker may occur. On the other hand, if the update cycle FR is too short, the display device cannot execute normal update processing. Therefore, 0.95 / 60 <FR [ Seconds] <1.05 / 60 should be specified.

Corresponding to this setting, the data valid signal ENAB has a waiting time WTh (= 382/108 MHz) corresponding to the 382 clock in the image update operation of each line, which is the L level, and then is active corresponding to the 1280 clock. The section (= 1280/108 MHz) becomes the active level (H) (FIG. 15 (c)). As shown in FIGS. 15 (d) and 15 (e), in the active section of the data valid signal ENAB, an image is updated for a pixel of 1280 dots per line in a predetermined time (11.85 μS = 1280/108 MHz). Image data is output so that the operation is completed. That is, 1280 pixel data (Pixel Data) are output in synchronization with the 1280 dot clock DCK. Since a full ^- color image having a gradation of 28 × ²⁸ × 28 is displayed on the display device DS1, the pixel data of one pixel has a length of 3 × ⁸ bits.

By the way, in this embodiment, although not required by the main display device DS1, the vertical synchronization signal VS and the horizontal synchronization signal HS are output. The vertical synchronization signal VS is output within the time of the vertical standby time WTv, and the horizontal synchronization signal HS is output within the time of the horizontal standby time WT. Note that FIGS. 15 (a) and 15 (b) show each operation cycle for convenience of understanding. Further, in FIG. 15 (f), circles are shown at the upper left and lower right vertices of the rectangular frame specified by TH × TV (= 1083 × 1662 clock) to indicate “start of display operation” and “display operation”. Although it is described as "end", this ◯ mark means "V blank start" which defines the operation cycle of the display circuit 74A which is started every 1/60 second. Since the 1083 × 1662 clock that defines the display operation matches 1/60 seconds, the elapsed time from “start of display operation” to “end of display operation” (operation cycle of display circuit 74A) is 1/60 seconds. Is. The "V-blank start" will be described later with reference to FIG. 22.

Returning to FIG. 14, the output selection unit 79 of the embodiment divides the output signal of the display circuit 74A into dual links that divide the 108 MHz dot clock DCK by two, and the LVDS unit 80a and the output signal unit 80a, respectively. , Is transmitted to the LVDS unit 80b (see FIGS. 14 (a) and 5). Then, the LVDS units 80a and 80b convert the image data (a total of 24 bits of digital RGB signals) into the first and second LVDS signals, and transmit a pair of clock signals (54 MHz = 108/2) to the first and second LVDS signals. In addition, all five pairs of differential signals LVDS1 and LVDS2 are output to the main display device DS1 via two paths (see FIG. 14A and FIG. 4).

As described above, in the main display device DS1, the ODD signal for one pixel and the EVEN signal for one adjacent pixel are processed at the same timing, so that the actual operating clock CK frequency is displayed. It matches the 108 MHz dot clock DCK output by the circuit 74A.

Although the display circuit 74A for generating the image to be transmitted to the main display device DS1 has been described above, the display circuit 74B generates the image data to be transmitted to the sub display device DS2. The digital RGB signal output by the display circuit 74B is supplied to the digital RGB unit 80c via the output selection unit 79, and is transmitted to the sub display device DS2 together with the vertical synchronization signal VS and the horizontal synchronization signal HS.

Along with the synchronization signals VS and HS, the data valid signal ENAB is also transmitted via the digital RGB unit 80c, but each of these signals is transmitted as a continuous signal rather than a discrete value as in the case of the LVDS transmission line. Of course, (see FIG. 14 (a)).

By the way, in the case of this embodiment, the display circuits 74A to 74B are provided with underrun counters URCNTa to URCNTc for counting the Underrun abnormality in which the display data is not generated in time for the display timing (FIG. 15). reference). The counter values of the underrun counters URCNTa to URCNTc are configured to be automatically added for each VBLANK when an underrun abnormality occurs.

Next, the SMC unit 78 (Serial Management Controller) is a composite controller having a built-in LED controller and Motor controller. Then, while outputting the LED drive signal and the motor drive signal in synchronization with the clock signal to the LED / Motor driver (driver IC with a built-in shift register) mounted on the external board, the latch pulse is output at an appropriate timing. It is configured to be outputable.

Regarding the internal circuit of the VDP circuit 52 and its operation described above, the operation content to be executed by the internal circuit is defined by the operation parameters (set values) set by the effect control CPU 63 in the control register group 70, and the execution of the VDP circuit 52. The state can be specified by READing the operation status value of the control register group 70. The control register group 70 means a large number of VDP registers RGij mapped in an address space (0 to FFFFFF) of about 1 Mbyte on the memory map of the effect control CPU 63, and the effect control CPU 63 passes through the CPU IF unit 81. The WRITE (setting) operation of the operation parameter and the READ operation of the operation status value are executed (see FIG. 8 (b)).

In the control register group 70 (VDP register RGij), the "system control register" in which the initial setting values related to the system operation such as the interrupt operation are written, and the AAC area (a) and the page area (b) are determined in the built-in VRAM. , "Index table register" related to building or changing index table IDXTBL, and "data transfer" in which setting values related to data transfer processing by the data transfer circuit 72 between the effect control CPU 63 and the internal circuit of the VDP circuit 52 are written. The "register", the "GDEC register" that specifies the execution status of the graphics decoder 75, the "drawing register" in which the setting values related to the instruction command and the drawing circuit 76 are written, and the setting values related to the operation of the preloader 73 are written. A "preloader register", a "display register" in which setting values related to the operation of the display circuit 74 are written, an "LED control register" in which setting values related to the LED controller (SMC unit 78) are written, and a motor controller (SMC). A "motor control register" in which the setting value relating to the voice circuit SND is written and a "voice control register SRG" in which the setting value relating to the voice circuit SND is written are included. However, in this embodiment, the voice circuit SND is not utilized.

In any case, in the following description, one or more registers RGij included in the control register group 70 may be referred to by the above-mentioned individual names or collectively referred to as VDP register RGij. The effect control CPU 63 controls the internal operation of the VDP circuit 52 by writing an appropriate set value to the predetermined VDP register RGij. Specifically, the effect control CPU 63 realizes a predetermined image effect based on the display list DL updated at an appropriate time interval and the set value in the predetermined VDP register RGij. In this embodiment, since the effect control CPU 63 is in charge of the effect control CPU 63 including the lamp effect and the motor effect, the VDP register RGij also includes the LED control register and the motor control register.

Subsequently, a unified effect control operation of image effect, sound effect, motor effect, and lamp effect realized by the composite chip 50 incorporating the CPU circuit 51 and the VDP circuit 52 described above will be described.

In the case of this embodiment, the operation of the composite chip 50 is started by a power-on reset operation (see FIG. 16A) by turning on the power or performing an abnormal reset, and the initial setting process (SP1 to SP1) by the initial setting program (boot program) Pinit. It is configured to shift to the main control process (SP10) by the effect control program Main and the interrupt process program (vector handler) Reset via SP9). Regarding the main control process, the processing content of the introduction unit is described in FIG. 18A, and the processing content of the main body unit is described in FIG. 22A. The process of step SP27 in FIG. 18 does not include the process of steps SS1 to SS3 in FIG. 21 (a).

Based on the above, the power-on reset operation will be described with reference to FIG. 16A. When the system reset signal SYS maintains the L level for a predetermined period (assert period), such as when the power is turned on, all the operation control registers REG and all VDP registers RGij are automatically set to predetermined default values.

After that, when the system reset signal SYS changes to the H level (negate level) (see the timing T1 in FIG. 6D), in this embodiment, in order to measure the elapsed time after the CPU reset, the timekeeping timer TM (see the timing T1). The operation of FIG. 9A) is started (SP1). Further, the 32-bit data from the head address of the address space CS0 is set in the program counter PC of the effect control CPU 63, and the 32-bit data following the 32-bit data is set in the stack pointer SP (SP1). In FIGS. 10 and 17 (c), the head area of the memory for storing the initial values of the program counter PC and the stack pointer SP is referred to as a vector table VECT.

As shown in FIG. 16B, the vector table VECT stores the vector number for specifying the priority, the interrupt factor, and the like, and the address information in correspondence with each other. The smaller the vector number, the higher the priority. For example, the vector number 11 is an non-maskable interrupt (NMI), and the start address of the interrupt processing program executed at the time of NMI interrupt is stored as address information. Has been done. Further, the vector number 64 is an internal interrupt (VDP_IRQ0) from VDP, and the start address of the interrupt processing program executed at the time of VDP_IRQ0 interrupt is stored as address information.

Since the interrupt priority is as shown in FIG. 18 (d), in the column of the vector number smaller than the vector number 64, the control command reception interrupt IRQ_CMD, the 20 μS timer interrupt, and the 1 mS timer interrupt of the interrupt processing program. Each start address is stored. On the other hand, in the column of the vector number larger than the vector number 64, the start address of the interrupt processing program (IRQ_SND, IRQ_RTC, etc.) having a lower priority than VDP_IRQ 1 is stored.

Further, in the vector table VECT, vector number 0 and vector number 1 are defined as set values that should be automatically set in the program counter of the CPU and the stack pointer at the time of power-on reset. As shown in FIG. 16B, in this embodiment, 4-byte data "*****" is set in the program counter PC as an internal operation at the time of power-on reset (reset assert period), and the 4-byte data ". ++++ "is set in the stack pointer SP. Note that "*****" is the start address value of the initial setting program Pinit (SP1 to SP9 in FIG. 16) that is non-volatilely stored in the address space CS0, and "++++" is secured in the built-in RAM 59. It is also the address value of the tip or end of the stack area that functions in the LIFO (Last-In First-Out) method.

In this embodiment, since the register bank RBi is effectively used, the stack area is not consumed at the time of interrupt processing, and a large amount of memory capacity is not required. That is, in this embodiment, the stack area is exclusively used in function processing and subroutine processing.

As a result of the above operation, after that, the effect control CPU 63 executes the initial setting program Pinit described after the address value "*****". However, the memory READ operation of the address space CS0 is executed based on the default value (initial value) of the operation control register REG that defines the operation of the bus state controller 66 (FIG. 9). The initial value of this operation control register REG is a value automatically set during the reset assert period (the period shown in FIG. 7D in which the system reset signal SYS maintains the L level), and any address space CS0 can be set. It is set to the slowest READ access operation (default access operation) so that READ access can be performed without problems even if it is configured with a memory device.

Therefore, in order to change this default access operation to the optimum access operation, first, an optimum value is set in a predetermined operation control register REG that defines the operation of the bus state controller 66 (FIG. 9) with respect to the address space CS0 (. SP1). That is, in order to optimize the memory READ operation when accessing the initial setting program Pinit (SP1 to SP9), the effect control program MainB (SP10 or less), the PROM 53 storing constant data, etc., the bus width And page access is set, and the chip selection signal CS0, READ control signal, WRITE control signal, and other operation timings are optimally set (see FIG. 40).

As a result of the above settings, the processes after step SP2 are executed by optimally READing the memory stored in the address space CS0. Therefore, next, in order to optimize the READ / WRITE access operation when the effect control CPU 63 accesses the VDP register RGij, a predetermined operation control that defines the operation of the bus state controller 66 (FIG. 9) with respect to the VDP register RGij is specified. The optimum value is set in the register REG (SP2).

As described above, in the present embodiment, since the VDP register RGij is positioned in the address space CS7 of the effect control CPU 63, it is predetermined to optimally set the operation timing of the chip selection signal CS7 and other control signals. A predetermined value is written in the operation control register REG.

Subsequently, the register value of the specific VDP register RGij is read out, and it is determined whether or not the value is a predetermined value (device code) (SP3). This is a confirmation determination that the system clock of the VDP circuit 52 has stabilized. That is, the VDP circuit 52 operates based on the oscillation output of the oscillator OSC2 supplied to the PLLREF terminal, and the VDP circuit 52 normally corrects a command from the CPU circuit 51 (that is, setting to the VDP register RGij, etc.). It is a judgment as to whether or not it can be accepted.

Then, if it is confirmed that the system clock is stabilized by the device code reading process (SP3), then the normal operation of the VDP circuit 52 can be expected, so that the setting process for the predetermined VDP register RGij is executed (SP4). ~ SP6). In the process of step SP4, first, the ender setting (big / little) when accessing the VDP register RGij from the effect control CPU 63, the data bus width is set (SP40), and the internal interrupt from the VDP circuit to the CPU circuit. For (VDP_IRQ0, VDP_IRQ1, VDP_IRQ2, VDP_IRQ3), set the interrupt significance level (H / L) (SP41).

In this embodiment, the most significant bit of the set value is set to the big endian stored in the most significant bit of the VDP register RGij, and the data 32 bus width is set to 32 bits. If the value is the same as the default value, these setting processes can be omitted (the same applies to the following processes).

Further, in the process of step SP4, the frequency of the display clock is set based on the set value in the predetermined system control register RGij (SP42 to SP44). Specifically, for the display circuit 74A and the display circuit 74B, it is set in the predetermined system control register RGij to generate the dot clock DCKA and DCKB based on the reference clock (output of the oscillator OSC2) of 40 MHz. (SP42), the multiplication ratio and division ratio with respect to this reference clock are appropriately specified for each display circuit (SP43). Further, the operation start of the display circuit 74B is set in the predetermined system control register RGij in order to synchronize the operation start of the display circuit 74A with the operation start of the display circuit 74A (SP44). Furthermore, the sampling clock of the LVDS is set to be the same as the dot clock DCKA of the display circuit A (SP43).

In these processes, the dot clock DCK is set separately for the display circuit 74A and the display circuit 74B, and the frequency of the dot clock DCKA for the main display device DS1 applied to the display circuit 74A is 108 MHz as described above. Is set to. On the other hand, the frequency of the dot clock DCKB for the sub-display device DS2 applied to the display circuit 74B is set to 27 MHz corresponding to 480 horizontal × 800 vertical pixels.

Further, in the process of step SP4, the LVDS unit 80 is set to be used as a dual link (a pair of LVDS transmission lines) (SP45), and the LVDS unit 80 is set based on the set value in the predetermined system control register RGij. The operating state is switched from the mask state (Defult state) that outputs zero to the unmask state according to the output of the display circuit 74 (SP45). When the LVDS unit 80 is used as a single link (single LVDS transmission line), a setting to that effect is made in the process of step SP45.

As shown in FIG. 6 (f), as a result of the processing of step SP45, the operation of the LVDS unit 80 is switched from the defult state to the non-masked state, and after the timing T4 when the display circuit 74 starts the operation, ( The ODD signal and the EVEN signal are supplied to the LVDS units 80a and 80b via the output selection unit 79, and the LVDS signal (LVDS1 / LVDS2) is supplied to the display device DS1 via the dual link. ) Will be transmitted (see FIG. 14 (a)). The LVDS sampling clock is set to 108 MHz, which is the same as the dot clock DCKA of the display circuit A. However, in this embodiment, since the dual link configuration is adopted, the LVDS sampling clock in each dual link is 54 MHz. Yes (see Figure 4).

Further, in the process of step SP4, it is set that the DDR (DRAM54) functions based on the clock signal (reference clock) to the PLLREF terminal (see FIG. 8A) (SP46). It should be noted that the reference clock of the oscillator OSC2 is supplied to the PLLREF terminal as described with respect to FIG. 8A. Further, by setting an appropriate value in the register built in the DDR (DRAM54), the self-refresh operation (Self-Refresh Operation) of the DRAM 54 is enabled, and other settings for the DRAM 54 to operate normally are made (). SP47). By the above processing, the DRAM 54 is in a state where it can operate normally, and the subsequent data transfer operation from the PROM 53 to the DRAM 54 (SP8) and the execution of the control program transferred to the DRAM 54 (SP10) are realized without any problem. Will be done.

Subsequently, the address spaces CS1 to CS6 are defined (SP5) in order to realize the memory map shown in FIG. As described above, the address space CS3 is assigned to the internal register of the voice processor 27, the address space CS4 is assigned to the internal register of the RTC 38 and the address space of the SRAM 39, and the address space CS5 is assigned to the external DRAM (DDR). The address space CS6 is assigned to 54, and the address space CS6 is assigned to the work memory 57 of the built-in CPU.

Since it is fixedly specified that the VDP register RGij is assigned to the address space CS7, the definition process of the address space CS7 is unnecessary. Further, it is fixedly defined in advance that the address space CS0 is after the memory map address 0x000000000000 of the CPU circuit 51, and on the premise of this specification, the address space CS0 is secured in the CGROM 55 or other memory. Whether it is given to the device is specified by the H / L level of the HBTSL terminal.

As described above, in this embodiment, the HBTSL terminal = L, and it is shown that the address space CS0 is defined in addition to the CGROM55. Since the specific bus width of the control memory 53 other than the CGROM 55 and the optimum access operation have already been set in step SP1, the processing of step SP5 is not necessary for the address space CS0.

Subsequently, for the address spaces CS1 to CS6 defined in the process of step SP5, a predetermined value is written in a predetermined operation control register REG regarding the bus width and the presence / absence of page access when accessing each address space CSi (SP6). ). Further, in order to optimally set the chip selection signal CSi and others, a predetermined value is written in a predetermined operation control register REG (SP6). These processes have the same contents as the processes of steps SP1 and SP2, and are the chip select signal CSi, the READ control signal, and the WRITE by the write process to the operation control register that defines the operation of the bus state controller 66 (FIG. 9). The control signal and other operation timings are optimally set.

Subsequently, regarding the WDT circuit 58 that has already started operation, an abnormal reset is avoided by outputting a clear signal to the WDT circuit 58 (SP7). This is in consideration of the fact that the WDT circuit 58 automatically starts operation after the power is turned on, and the same process is repeatedly executed after that. The process of step SP9 is stored in the control memory 53 as the subroutine SP7, but the subroutine SP7 of the control memory 53 is called until the end of step SP9, and after the end of step SP9, the external DRAM 54 stores the process. Another transferred subroutine SP7'is called and executed.

Next, among the programs and data stored in the address space CS0, the vector handler Vopt (interrupt processing program) shown in FIGS. 16B and 17C, the error recovery processing program Piram, the effect control program MainB, and the like. The variable D with an initial value and the constant data C are transferred to the external DRAM 54 or the built-in RAM 59 (SP8). The variable D with an initial value means the initial value data stored in a predetermined variable area. The memory section initialization process (SP8) is a process for transferring programs and data in order to speed up the effect control process, and is a process for avoiding access to the ROM, which is inferior in access speed.

Then, next, the setting to use the register bank RBi is made (SP9). Therefore, after that, the register banks RB0 to RB14 function at the time of interrupt processing, the interrupt processing is speeded up, and the consumption of the stack area is alleviated.

The above processing is realized by executing the "initial setting program Pinit" stored in the control memory 53 which is the address space CS0 (see FIG. 17C). Then, when the execution of the initial setting program Pinit is completed, the main control process by the effect control program Main is subsequently executed (SP10). Here, the execution of the main control process means the execution of the “effect control program Main” transferred from the control memory 53 to the external DRAM 54 by the transfer process of step SP8 (see FIG. 16 (b)).

The processing of the "effect control program Main" is divided into a main introduction process shown in FIGS. 18A and 21 and a main main body processing shown in the lower part of FIG. 21 and FIG. 22A. The specific contents will be described with reference to FIGS. 18 (a) and 21 to 22, but prior to that, the memory section initialization process (SP8) will be described. As shown in FIG. 17A, in the memory section initialization process (SP8), the DMACs of a plurality of channels are first initially set to the operation stop state. Note that this process is just a formal process just in case.

When the above processing is completed, DMACi of a predetermined channel is activated, and the vector handler Vopt (interrupt processing program) stored in the control memory 53 is transferred to the built-in RAM 59 by a non-stop transfer method (see FIG. 11 (b3)). DMA transfer with. In this embodiment, since the interrupt processing program Vopt is transferred to the built-in RAM 59, appropriate abnormality handling processing can be performed even when an abnormality occurs in the external DRAM 54.

Subsequent processing is also the same, and is executed by the non-stop transfer method using DMACi of a predetermined channel, and the error recovery processing program Pilam is DMA-transferred to the built-in RAM 59 (SP62). In this embodiment, since the error recovery processing program Pilam is transferred to the built-in RAM 59, the peripheral circuit can be reliably reset in the error recovery processing. For example, if the error recovery processing program Pilam is transferred to, for example, an external DRAM 54 other than the built-in RAM 59, the external DRAM 54 cannot be reset during the error recovery processing.

Next, the effect control program Main is DMA-transferred to the external DRAM 54 (SP63), and the constant data C is DMA-transferred to the external DRAM 54 (SP64). The constant data includes lottery data used for the effect lottery, lamp drive data, and motor drive data in various drive data tables shown in FIG. 22B. Further, the variable D having an initial value is DMA-transferred to the external DRAM 54 (SP65), and all of these are executed by a non-stop transfer method using DMACi of a predetermined channel.

Finally, the clear data is written at the beginning of the variable area B of the external DRAM (SP66). Assuming that this start address is ADb, in the subsequent DMA transfer processing, the transfer source address is set to ADb, the transfer destination address is initially set to ADb + 1, and then the clear data is incremented while each address value ADb, ADb + 1 is incremented. By spreading the above, the clearing process of the variable area B is executed (SP67).

The processes of steps SP61 to SP66 and steps SP67 described above are all similar operations and are as shown in FIG. 17 (b). That is, first, regarding DMACi of a predetermined channel, as DMA transfer conditions, (1) cycle steal transfer mode, (2) non-stop transfer method is adopted, and (3) the address values of Source and Destination are updated by increment (setting). SP68).

Next, set the initial values of the transfer source source address and the transfer destination destination address (SP69), set the transfer size, set the interrupt disabled, etc. (SP70), and then start the DMA transfer operation (SP71). ). The settings of steps SP68 to SP71 are all realized by the setting operation in the predetermined operation control register REG.

In the initialization process of this memory section, the interrupt for the end of DMA transfer is prohibited (SP70). Therefore, after starting the operation of DMA transfer, the status flag of the predetermined operation control register REG is repeatedly READ-accessed. Then, it waits for the end of DMA transfer (SP72). However, in consideration of the processing time until the end of the operation, the clear signal is repeatedly output to the WDT circuit 58 (SP73). Then, at the end of the DMA transfer, the DMACi is stopped and set based on the setting operation in the predetermined operation control register REG.

Subsequently, the operation contents (main introduction process + main main body process) of the main control process will be described with reference to FIGS. 18 (a) to 22. Regarding the main control process (main introduction process + main main body process), the main introduction process (SP20 to SP27) is described in the upper part of FIGS. 18A and 21 and is an initial part of the main main body process. The setting process (SS1 to SS6) is described in the lower part of FIG. 21. Further, the contents of the steady processing (ST4 to ST14), which is the rest of the main body processing, are shown in FIG. 22.

As shown in FIG. 18A, in the main introduction process, first, the bus width and the type of the ROM device of the CGROM 55 are specified (SP20). Specifically, as shown in FIG. 19A, READ access is made to a predetermined VDP register RGij (for example, CG bus Status register) that specifies the operating state of the CG bus that controls the interface with the CGROM 55 (SP80). ), It is determined whether or not the operation can be set for the CG bus (SP81).

Here, if the value of the CG bus Status register is 1, it means that the internal circuit of the CG bus is in the reset operation, and it means that the set value in the VDP register RGij cannot be accepted. Therefore, after confirming that the value of the CG bus Status register has changed from 1 to 0 (SP81), each device section (SPA0 to SPAn) that can be specified corresponding to the memory device constituting the CGROM (SP81) ( 1) Enable / disable each device section SPAi, (2) ROM device type, (3) Data bus width and other operating parameters are set in the predetermined VDP register RGij (SP82).

As shown in FIG. 18A, in this embodiment, the CGROM 55 can be divided into a plurality of areas (device sections), for example, a memory device and a data bus width for each device section (SPA0 to SPAn). Is configured to be selectable. As the memory device, for example, (1) a SATA module (AHSI / F) adopted in this embodiment, (2) a memory element adopting a parallel I / F (Interface) format, and (3) a sequential I / F format are adopted. It is roughly classified into memory elements and the like, but the memory device can be specifically selected for each of the roughly classified memory devices, and the data bus width and the like can be arbitrarily specified.

Next, in order to optimize the memory READ operation with the memory device selected for each device section (SPA0 to SPAn), a predetermined operation parameter is set in a predetermined VDP register RGij (SP83). The operation parameters include setting values that define the operation timing of the chip select signal and other control signals (READ control signal, etc.). Further, when a memory element adopting the sequential I / F format is selected, the output timing of the address latch, the number of read clocks, and the like are specified in order to realize the operation shown in FIG. 19B.

Therefore, the CGROM 55 can be configured by combining different types of memory devices. However, in this embodiment, the CGROM 55 is configured by using only the SATA module, only the device section (SPA0) is enabled, and the other device sections (SPA1 to SPAn) are disabled.

In any case, when the setting process of steps SP82 to SP83 is completed, a predetermined value is written in the predetermined VDP register RGij in order to make the setting process effective (SP84). This is in consideration of the fact that it takes a predetermined time for the internal circuit of the CG bus to operate in response to the setting process of steps SP82 to SP83, and during the operation of the internal circuit, the CG bus Status register described above is used. The value of (see SP80) becomes 0.

Therefore, after that, the CG bus Status register is repeatedly READ-accessed (SP85), and the process is completed after confirming that the value of the Status register returns from 1 to 0 (SP86). In addition, regardless of the determination of a predetermined number of times, if the value of the Status register does not return from 1 to 0, the processing of step SP66 may be completed. However, in that case, since the game process starts in a state where the CGROM cannot be normally accessed, the WDT circuit 58 is activated at any timing thereafter, and the composite chip 50 is in an abnormal reset state. Then, in this case, the power-on reset operation is executed again.

On the other hand, after the processing of step SP20 in FIG. 18 is normally executed, the built-in circuits of the CPU circuit 51 such as the interrupt controller INTC, the DMAC circuit 60, and the multifunction timer unit MTU are individually initialized by software processing. (SP21).

Next, for the multifunction timer unit MTU, after starting the predetermined timer measurement operation (SP22), for the internal interrupt and the internal interrupt, the permission setting value is written in the predetermined operation control register REG and the interrupt enabled state is set. (SP23).

As a result, after that, various interrupts shown in FIG. 18D can occur. Normally, at this timing, the voice processor 27 has completed its initialization sequence, so that the end interrupt signal IRQ_SND should have dropped to the L level, as shown in FIG. 7 (c). Therefore, the interrupt process shown in FIG. 18C is activated, the effect control CPU 63 initially sets the error flag ERR to 1, and READ-accesses the address space CS3 (SP30) to obtain a predetermined voice of the voice processor 27. The value of the register SRG is acquired, and it is determined whether or not the initialization sequence is normally completed (SP31).

If the initialization sequence is not normally completed, the effect control CPU 63 writes a reset command to a predetermined voice register SRG of the voice processor 27 (SP32) and is initially set to 1. Set the existing error flag ERR to 2 (SP33). This error flag ERR defines whether or not to execute the voice processor initialization process (SP26), and the error flag ERR = 1 is an execution condition of step SP26.

On the other hand, the voice processor 27 starts the initialization sequence again in the state of the end interrupt signal IRQ_SND = H level in response to receiving the reset command, and when the initialization sequence is completed, the end interrupt signal IRQ_SND becomes. Lower to L level. As a result, the process of FIG. 18C will be re-executed.

Although the exceptional case where the initialization sequence is not normally completed has been described above, normally, the process of step SP32 is executed following step SP31, and the effect control CPU 63 is set to the predetermined voice register SRG. By writing a predetermined value, the end interrupt signal IRQ_SND is returned from the L level to the H level (SP34).

Finally, by writing a predetermined value to the predetermined voice register SRG, READ / WRITE access to all the voice registers SRG is permitted (SP35). As a result of this processing, in the subsequent voice processor initialization processing (SP26), necessary setting processing can be executed.

Although an example of the Maskable Interrupt corresponding to the interrupt enable setting in step SP23 has been described above, the non-maskable interrupt based on the oscillation stop of the oscillator OSC2 can be started at an arbitrary timing. As described above, the operating clock (CPU system clock) of the circuit other than the built-in CPU (effect control CPU 63) is generated by frequency-multiplying the output clock of the oscillator OSC2 with a PLL (Phase Locked Loop), and is generated by the oscillator OSC2. If the oscillation of the VDP circuit 52 is stopped, the subsequent normal operation of the VDP circuit 52 is impossible.

On the other hand, the operation clock of the effect control CPU 63 is generated by multiplying the output clock of the oscillator OSC1 by the PLL, and the program processing can be continued. Moreover, the interrupt processing program is stored in the built-in RAM 59. Therefore, the effect control CPU 63 notifies the occurrence of an abnormal situation by voice or a lamp (SP28), and continues to output a clear signal to the WDT circuit 58 (SP29). The abnormality notification is, for example, a voice notification such as "An abnormal situation has occurred. Please contact the staff immediately." The reason why the clear signal is continuously output to the WDT circuit 58 is to avoid an abnormal reset operation. That is, in the case of a serious abnormality in which the oscillator OSC1 stops operating, it is considered that normal recovery of the device cannot be expected even if the abnormality reset process is repeated.

Since FIGS. 18 (b) and 18 (c) have been described above, the description will be continued by returning to FIG. 18 (a). In step SP24, the required area is set to write-protected in order to protect the program area of the external DRAM 54. Next, regarding the clock circuit 38 driven by the battery when the power is cut off, the normal operation when the power is turned off is confirmed, and the alarm interrupt is reset just in case (SP25).

Then, on condition that the error flag ERR = 1, a necessary setting value is written in the built-in register (voice register SRG) of the voice processor 27, and the initialization process is executed (SP26). When the error flag ERR = 0, the process waits for a predetermined time until the error flag ERR = 1, but when the time limit is exceeded, the process shifts to the infinite loop process in order to activate the WDT circuit 58.

Next, the power supply control circuit SPY is controlled to prepare the display device DS1 to start, and the necessary setting values are written to the VDP register RGij to initialize the display clock DCK and the display circuit 74 (SP27). .. The process of step SP27 is shown in detail as the process of steps SP50 to SP57 in FIG.

Although the embodiment of receiving the end interrupt signal IRQ_SND from the voice processor has been described above, it is also preferable to omit the interrupt processing of FIG. 18 (c). FIG. 20 shows a modified embodiment, in which the 1 ms timer interrupt signal generated by the multifunction timer unit MTU is used instead of the end interrupt signal IRQ_SND.

FIG. 20 illustrates a part of the 1 ms timer interrupt process, and realizes four-step operation based on the value (0/1/2/3) of the operation management flag FLG whose initial state is zero. is doing. The IRQ_SND output terminal of the audio processor 27 is in an open state, and the IRQ_SND input terminal of the CPU circuit 51 is fixed to the H level.

In the 1 mS timer interrupt process, first, when the operation management flag FLG = 0 is determined in the process of step SP42, it is confirmed that the initialization sequence of the voice processor 27 is normally completed (SP43). Then, when the process ends normally, the interrupt signal (IRQ_SND) is cleared (SP46) by writing a predetermined value to the predetermined voice register SRG, and the operation management flag FLG is set to 1 (SP47). The processing of steps SP43 and SP46 is the same as the processing of steps SP31 and SP34 in FIG. 18C.

On the other hand, if the initialization sequence is not completed normally, the reset command is written in the predetermined voice register SRG to activate the initialization sequence in the voice processor 27 (SP44), and the operation management flag FLG is set to zero. Return (SP45). The process of step SP44 corresponds to the process of step SP32 of FIG. 18 (c).

Normally, the operation management flag FLG = 1 is set after the processing of step SP47. Therefore, in the next 1 ms timer interrupt, access to all voice registers is permitted by writing a predetermined value to a predetermined voice register (SP48). ), Set the operation management flag FLG = 2 (SP49). The process of step SP48 corresponds to the process of step SP35 of FIG. 18 (c).

Next, in the 1 ms timer interrupt with the operation management flag FLG = 2, the necessary setting values are written in the built-in register (voice register SRG) of the voice processor 27 as in the case of step SP26 in FIG. 18 (a). The initialization process is executed (SP50), and the operation management flag FLG = 3 is set.

The operation management flag FLG = 3 means a normal voice control state, and voice control is advanced by setting necessary operation parameters in the necessary voice register SRG (SP52).

As described above, the method of confirming the normal termination of the initialization sequence of the voice processor 27 by the interrupt processing caused by the interrupt signal (IRQ_SND) (SP31 in FIG. 18C) and the method of confirming by the 1mS timer interrupt processing (FIG. 20). Although SP43) of the above has been described, the present invention is not limited to these methods. For example, it is also preferable to determine whether or not the initialization sequence of the voice processor 27 has been normally completed as part of the process of step SP26 in FIG.

Since the outline of the main introduction process (SP20 to SP26 in FIG. 18) has been described above, the details of the process of step SP27 (startup preparation process + initialization process) and the main body process are described below based on FIGS. 21 to 22. The operation of the processing (SS1 to SS6 and ST4 to ST14) will be described.

As shown in FIG. 21, the effect control CPU 63 first determines the timekeeping timer TM as the process of step SP27, and one second has elapsed from the start of operation of the effect control CPU 63 (timing T1 in FIG. 6D). , Check while outputting a clear signal to the WDT circuit 58 (SP50). This is to maintain the display device DS1 in a non-operating state until the VDP circuit 52 starts substantially operating. Further, since the clear signal is output to the WDT circuit 58, there is no possibility that the initialization process up to this point is wasted, such as the activation of the WDT circuit 58 is surely prevented and the composite chip 50 is abnormally reset. Is the same in the following standby processing).

Next, the effect control CPU 63 shifts the control signals PS1 and PS2 to the power supply control circuit SPY from the L level to the H level (SP51). This process is the operation of the timing T2 shown in FIGS. 6 (g) and 6 (h), and the control signals PS1 and PS2 are maintained at the H level thereafter.

When the control signal PS1 reaches the H level, the MOS transistor Q1 is turned on, and the power supply voltage 12V is supplied to the backlight unit BL. However, at this timing T2, since both the BL_EN terminal and the PWM terminal of the driver DVL of the backlight unit BL are at the L level, the backlight unit BL does not emit light.

Further, when the control signal PS2 reaches the H level, the MOS transistor Q4 is turned on, and the power supply voltage 5 is supplied to the liquid crystal display unit MONI. However, at this timing T2, since the backlight unit BL is in the extinguished state, there is no possibility that an unnatural image will be displayed.

After the processing of step SP51 is completed, the effect control CPU 63 next defines the refresh mode based on the set value in the predetermined VDP register RGij, and also defines the refresh cycle of the built-in VRAM 71 and the row address (refresh address). The initial value is set and the initialization process of the built-in VRAM 71 is executed (SP52).

The VRAM 71 of the embodiment is composed of a DRAM (Dynamic Random Access Memory), and the electric charge stored in the memory cell is gradually lost due to the leakage current inside the element. Therefore, in this embodiment, for example, a distributed refresh method of refreshing one row at a time is adopted, and all the rows (ROW) in the element are refreshed in the refresh cycle specified in the process of step SP52 to lose the charge of the memory cell. Is prevented. Therefore, even if there is a memory cell that is not accessed for a long time in the VRAM 71, there is no possibility that the data will be lost. The refresh mode is not limited to the distributed refresh method, and a centralized refresh method can also be adopted.

Next, a necessary setting value is written in the VDP register RGij to initialize the display clock DCK and initialize the display circuit 74 (SP54). It should be noted that this process is nothing but an operation of hardware resetting the corresponding internal circuit.

Subsequently, the control signal STBY to the power supply control circuit SPY is changed from the L level to the H level (SP56). This process is the operation of the timing T3 shown in FIG. 6 (i), and the H level of the control signal STBY is maintained thereafter. At this timing T3, since the power supply voltage 12V has already been supplied to the driver DVL of the backlight unit BL (timing T2), the driver DVL is in an operable state. However, since the control control signal PWM still maintains the L level, the backlight unit BL does not emit light.

Next, the effectiveness of the process of step SP4 of FIG. 16 and the effectiveness of the process of step SP54 of FIG. 21 are confirmed by reading access to a predetermined VDP register (status register STS) RGij (SP57). Specifically, first, it is confirmed by the status register STS (1) that the display clock set in the process of step SP4 in FIG. 16 is stabilized.

Next, the status register STS (2) confirms that the initialization of the display circuit is normally completed in response to the processing of step SP54. Subsequently, it is confirmed by the status register STS (3) that the initialization of each part LVDS1 / LVDS2 is normally completed for the LVDS circuit 80 in which the dual link is set in the process of step SP45. Then, when it is confirmed that all the initializations are completed normally, the main introduction process ends (SP57).

Subsequently, the subsequent processing will be described with respect to an embodiment in which the preloader does not work. As shown in FIGS. 21 to 22 (a), the main main body processing is a VDP initial setting processing (SS1 to SS6) executed after the CPU reset, and then a steady processing (ST4) repeatedly executed every 1/30 second. ~ ST14).

Since the steady processing (ST4 to ST14) is started at the timing when the interrupt counter VCNT becomes VCNT ≧ 2 (ST4), the operation cycle δ of the steady processing is 1/30 second. This operation cycle δ is nothing but a substantial operation cycle δ of the VDP circuit 52 that operates intermittently based on the control of the effect control CPU 63. The determination condition is VCNT ≧ 2, considering the possibility that the steady processing (ST4 to ST14) is abnormally prolonged and the timing of VCNT = 2 is overlooked, but the situation is that VCNT = 3. Is designed not to occur.

Based on the above, the VDP initial setting process will be described. As shown in FIG. 21, in the present embodiment, in the VDP initial setting process, the built-in VRAM 71 having a storage capacity of 48 Mbytes has an ACC area (a) having an appropriate storage capacity, a page area (b), and an arbitrary area (c). ) And, as appropriate (SS1). Specifically, for the ACC area (a1, a2) and the page area (b), the area start address and the required total data size are set in the predetermined index table register RGij (SS1). Then, the reserved ACC area (a1, a2) and the residual area not included in the page area (b) become an arbitrary area (c).

Here, the lower 11 bits of the first and second ACC areas (a1, a2) and the page area (b) must be 0 for the lower 11 bits, but they can be arbitrarily selected in units of 2048 bits. There is (1 address = 1 byte, selection for each 256 addresses). The total data size is also arbitrarily selected in the range of an integral multiple of the unit size. Although not particularly limited, the unit size of the ACC area (a) is 2048 bits, and the unit size of the page area (b) is 512 kbit.

As described above, in this embodiment, certain conditions are set for the area settings of the ACC area (a1, a2) and the page area (b), but this is as wasteful as possible for the built-in VRAM 71 having a limited memory capacity. This is to facilitate the internal operation of the VDP circuit 52 while eliminating the region. That is, if the storage capacity of the built-in VRAM 71 is increased unnecessarily, there is a concern that the manufacturing cost will rise and the chip area will increase, but if a free area setting that completely eliminates the wasted area is allowed, the internal processing will be performed. This is because it becomes complicated and the processing time for VRAM access cannot be shortened. For the same reason, certain restrictions are placed on securing the index space described below.

Continuing the explanation based on the above, following the process of step SS1, the necessary index space IDXi is secured for the page area (b) and the arbitrary area (c) (SS2). Specifically, the index space IDXi of each area (b) (c) is secured by setting necessary information in the predetermined index table register RGij.

For example, when the index space IDXi is provided in the page area (b), multiple information of an arbitrary horizontal size Hx and an arbitrary vertical size Wx corresponding to an arbitrary index number i (vertical and horizontal multiple information with respect to a unit space). ) Is set in the predetermined index table register RGij (SS2).

As described above, the index space IDXi in the page area (b) has a horizontal size of 128 × a vertical size of 128 lines as a unit space, and one pixel is specified by 32 bits of information, so that it is perpendicular to the horizontal size Hx. Based on the setting of the size Wx, the index space IDXi of the data size (bit length) = 32 × 128 × Hx × 128 × Wx is secured. The start address (space start address) of the index space IDXi in the page area (b) is automatically assigned internally.

Further, when the index space IDXi is provided in the arbitrary area (c), the arbitrary start address (space start address) STx and the multiple information of the arbitrary horizontal size Hx are predetermined corresponding to the arbitrary index number i. It is set in the index table register RGij of (SS2). Here, "arbitrary" is premised on a predetermined condition, and the horizontal size Hx is arbitrarily determined in units of 256 bits, the lower 11 bits of the head address STx is 0, and is arbitrarily determined in units of 2048 bits. As explained above, the vertical size of the arbitrary area is fixed to the 2048 line, so based on the setting of the horizontal size Hx, after the start address STx, the data size (bit length) = 2048 x Hx index. Space has been secured.

Specifically, as the frame buffer FBa of the main display device DS1, a pair of index spaces of horizontal size 1280 × vertical line 2048 are set in one or a plurality of predetermined index table registers RGij by specifying each index number. As the frame buffer FBb of the sub-display device DS2, a pair of index spaces of horizontal size 480 × vertical line 2048 are set in one or a plurality of predetermined index table registers RGij, each specifying an index number. If the number of horizontal pixels of the display device does not match an integral multiple of 256 bits / 32 bits, the horizontal size of each index space is larger than the number of horizontal pixels of the display device, and 256/32 = 8. Set to a value that is an integral multiple of, to minimize the occurrence of wasted memory area.

As described above, the required number of index space IDXi is generated by setting the required size information and address information for the page area (b) and the arbitrary area (c) in the predetermined index table register RGij. (SS2). Then, in response to this setting process (SS2), an index table IDXTBL that specifies the address information and size information of each index space IDXi is automatically constructed. As shown in FIG. 12A, the start address of each index space IDXi is stored in the index table IDXTBL together with other necessary information, and is stored at the time of data transfer inside the VDP circuit 52 or as an external storage resource (Resource). ) (See FIG. 13). Since the index space IDXi in the AAC area (a) is automatically generated and automatically disappears when necessary, the setting process of step SS2 is unnecessary.

As shown in FIGS. 12 (a) and 12 (b), each pair of frame buffers FBa and FBb are secured in the arbitrary area (c), and each is assigned an index number. In the embodiment in which the Z buffer is not used, a pair of index spaces 255 and 254 with index numbers 255 and 254 are secured as the frame buffer FBa. Further, as the frame buffer FBb, a pair of index spaces 252 and 251 to which the index numbers 252 and 251 are assigned are secured. In this embodiment, a work area (index space 0) having an index number of 0 is also secured in the arbitrary area (c).

Further, in this embodiment, the required number of index space IDXi, which is the decoding area of the IP stream moving image, is secured in the page area (a), and the index number i is assigned. However, initially, only the index space IDX ₀ for the background moving image (IP stream moving image) is secured. Then, the index space IDXj in the page area (a) is increased based on the setting process in the index table register RGij and the instruction command of the display list DL according to the necessity in the image effect (variation effect or notice effect). After that, when it becomes unnecessary, the index space IDXj is released. That is, FIG. 12A shows the index table IDXTBL during steady operation.

The index space of the ACC area (a) is automatically generated when necessary based on the instruction command described in the display list DL, and the index table IDXTBL contains the start address of the automatically generated index space IDXj. And other necessary information is set automatically. In this embodiment, this AAC region (a) is used as a decoding region for still images and other textures.

The above operation of securing the index space is realized exclusively by the setting operation to the index table register RGij included in the control register group 70, but following the processing of steps SS1 to SS2, the other VDP registers RGij By executing the necessary setting operation (SS3), the steady operation (intermittent operation) of the VDP circuit 52 shown in FIGS. 30 to 31 is enabled.

In this embodiment, the required setting process (SS3) includes at least SS30 to SS39. The steps SS30 to SS37 are not limited in the order of processing, and can be executed in any order regardless of the following description order.

In this embodiment, first, by writing a predetermined operation parameter (number of lines and number of pixels) to a predetermined display register RGij that defines the operation of the display circuit 74, the number of display lines and the number of display lines are calculated for each display device DS1 and SD2. Set the number of horizontal pixels (SS30). In the case of this embodiment, the number of horizontal pixels of the main display device DS1 is 1280 dots, and the number of display lines is 1024 lines. The number of horizontal pixels of the sub-display device DS2 is 480 dots, and the number of display lines is 80 lines. As a result of the setting process of step SS34, the vertical and horizontal dimensions of the effective data area (broken line portion in FIG. 22E) to be READ-accessed by the display circuits 74A and 74B are specified in each frame buffer FBa and FBb. ..

Next, by writing predetermined operation parameters (THc, WTh) to the predetermined display register RGij that defines the operation of the display circuit 74, the number of cycles THc of the horizontal cycle TH and the number of cycles THc of the horizontal cycle TH are obtained for each display device DS1 and SD2. The horizontal standby time WTh is set (SS31). Further, by writing predetermined operation parameters (TVl, WTv) to the predetermined display register RGij, the number of lines TVl of the vertical period TV and the vertical standby time WTv are set for each display device DS1 and SD2 (SS32). ).

As described with respect to FIG. 15, for the main display device DS1, the number of cycles of the horizontal cycle TH is set to THc = 1662, and the number of lines of the vertical cycle TV is set to TVl = 1083. Further, the horizontal standby time WTh = 382 and the vertical standby time WTv = 59 lines are set. On the other hand, for the sub-display device DS2, for example, the number of cycles of the horizontal cycle TH is set to THc = 519, the number of lines of the vertical cycle TV is set to TVl = 867, the horizontal standby time is set to WTh = 39, and the vertical standby time is set to WTv = 67 lines. Will be done. It should be noted that THc-WTh = 519-39 = 480 and TVl-WTv = 867-67 = 800, which matches the number of pixels of the sub-display device (horizontal 480 x vertical 800).

In any case, the frequency F _dot (= 108 MHz) of the dot clock DCK is determined by the processing of step SP4 in FIG. 16, and the number of cycles of the horizontal cycle TH for the main display device DS1 by the processing of steps SS30 to SS32. As a result of defining THc (= 1662) and the number of lines TVl (= 1083) of the vertical period TV, the display period of one frame is determined as THc × TVl / F _dot . Specifically, the display period of one frame is 1083 × 1662/108 MHz = 16.667 mS, and the frame rate FR is determined to be 1/60 second.

Regarding the sub-display device DS2, for example, based on the frequency F _dot = 27 MHz of the dot clock DCK, the number of cycles THc = 519 of the horizontal cycle TH, and the number of lines TVl = 867 of the vertical cycle TV, 519 × 867 / It is confirmed that 27 MHz = 16.66 mS.

Next, in this embodiment, for the sub-display device DS2, the pulse width of the horizontal cycle signal HS and the number of cycles from the V-blank start timing of the pulse rising edge are set in the predetermined display register RGij (SS33). Further, regarding the sub-display device DS2, the pulse width of the vertical period signal VS and the number of cycles from the V blank start timing of the pulse rising edge are set (SS34).

As described above, since the main display device DS1 does not require the horizontal synchronization signal HS and the vertical synchronization signal VS, the above processing (SS33 to SS34) for the main display device DS1 is unnecessary. However, if the setting process of steps SS33 to SS34 is omitted, the default value set at the time of power reset functions, so that the display device 74A also outputs the horizontal synchronization signal HS and the vertical synchronization signal VS. It will be.

According to the default value, for example, the horizontal synchronization signal HS for a pulse width of 40 clocks, which becomes the active level 16 clocks after the V blank start timing, is output, and the pulse width becomes the active level in synchronization with the V blank start timing. The vertical synchronization signal VS for three lines is output.

In this operation, the horizontal synchronization signal HS of the horizontal front pouch HPv = 16, the pulse width PWh = 40, and the horizontal back pouch BPv = 326 is output to the main display device DS1 during the horizontal standby time WTh = 382 clocks. Further, it means that a vertical synchronization signal VS having a vertical front pouch HPv = 0, a pulse width PWv = 3, and a vertical back pouch BPv = 56 is output during the vertical standby time WTv = 59 lines. However, as described above, these synchronization signals are ignored in the main display device.

In order to prevent the synchronization signals HS and VS based on the default values from being output, a configuration may be adopted in which the predetermined system control register RGij is set so as not to output the horizontal synchronization signal HS and the vertical synchronization signal VS. When such a mask setting is provided, the output terminal of the horizontal synchronization signal HS of the VDP circuit 52 and the output terminal of the vertical synchronization signal VS can maintain a fixed value of H level or L level.

Subsequently, the predetermined system control register RGij is set to allow a V blank interrupt (SS35). As a result, in this embodiment, the VBLANK start interrupt shown in FIG. 22C is generated corresponding to the V blank start timing that occurs every 16.667 mS = 1/60 second. This V blank interrupt timing defines the start timing of steady processing (ST5 to ST14) of the effect control CPU 63, and also means the start timing of the display period (end timing of the immediately preceding display period) for the display circuits 74A and 74B. ..

Next, a predetermined operation parameter (address value) is written in the predetermined display register RGij to specify the vertical display start position and the horizontal display start position for each frame buffer FBa and FBb (SS36). As a result, the effective data area whose vertical and horizontal dimensions are specified in the process of step SS34 is determined on the frame buffers FBa and FBb. Here, the vertical display start position and the horizontal display start position are relative address values in each index space, and in the embodiment shown in FIG. 22 (e), the display start position is (0,0).

Here, the "display area" means an index space (frame buffers FBa, FBb) in which image data should be read in order for the display circuits 74A and 74B to drive the display devices DS1 and DS2, and each has a double buffer structure. It means either one of the double buffers in the frame buffers FBa and FBb. However, the display circuits 74A and 74B actually read the image data only in the "effective data area" specified in step SS30 and step SS36 in the display area (0) or the display area (1).

Next, the display register RGij (DSPAINDEX) relating to the display circuit 74A driving the main display device DS1 and the display register RGij (DSPBINDEX) relating to the display circuit 74B driving the sub-display device DS2 are respectively "display area (0)". And "display area (1)" are set to define each display area (SS37).

Although not limited in any way, in this embodiment, for the frame buffer FBa, the index space 254 of the index number 254 in the VRAM arbitrary area (c) is defined as the “display area (0)”, and the index number in the VRAM arbitrary area (c) is defined. The index space 255 of 255 is defined as a "display area (1)" (SS37).

Further, regarding the frame buffer FBb, the index space 251 of the index number 251 in the VRAM arbitrary area (c) is set as the “display area (0)”, and the index space 252 of the index number 252 in the VRAM arbitrary area (c) is set as the “display area (display area (c)). 1) ”(SS37). The definition of the "display area" in the initial processing (SS3) is not particularly limited, and the index space (display area) in which the display circuit 74 should READ access the image data is toggled for each operation cycle δ. It may be switched. It is also preferable to clear the display area (0) and the display area (1) of the frame buffer FBa and the frame buffer FBb to zero at this timing. In this case, the image is unnatural for the display device. Is not displayed.

In this embodiment, once the initial settings including the above processes (SS30 to SS37) are completed, the first setting value to the predetermined system control register RGij is not changed due to the influence of noise or the like. A predetermined prohibition value is set in the kind prohibition setting register RGij (first prohibition setting SS38).

Here, the setting values for which future writing is prohibited include (1) the setting value related to the display clock DCK of the display devices DS1 and DS2, (2) the setting value related to the sampling clock of the LVDS, and (3) the setting value of the output selection circuit 79. It includes setting values related to the selection operation, (4) synchronization relations of a plurality of display devices DS1 and DS2 (the display circuit 74B is dependent on the operation cycle of the display circuit 74A), and the like. Although there is a software process for canceling the first prohibition setting, it is not used in this embodiment. However, it is also preferable to use it as needed.

Next, by setting a predetermined prohibition value in the second type prohibition setting register RGij, the write prohibition setting is set for the VDP register RGij of the initial setting system (second prohibition setting SS39). Here, the prohibited register includes step SP4 and the VDP register RGij related to steps SS30 to SS37.

On the other hand, by setting a predetermined prohibition value in the third type prohibition setting register RGij, it is possible to set prohibition to a large number of VDP registers including the VDP register related to the setting process of steps SS1 to SS3 (the first). 3 prohibition setting). However, in principle, it is not used in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be arbitrarily canceled by writing the release value in the predetermined release register RGij, and the set value is changed during steady operation. Is also possible.

After the above processing is completed, next, in the processing of step SP52 in FIG. 21, the operation is stable with reference to the status register (4) regarding the completion of the initialization of the built-in VRAM 71 in which the refresh cycle is defined. Confirm the normal completion of initialization) (SS40).

By the above processing, it is confirmed based on the values of the status registers (1) to (4) that all of the built-in VRAM 71, the display circuit 74, and the LVDS circuit 30 have normally completed the initialization processing. Next, by writing a specified value to the predetermined display register RGij (DSPACTL / DSPBCTL), the operation of the display circuits 74A and 74B is started (SS4a), and the predetermined system control register RGij (SYSDSPLVDS1MD / SYSDSPLVDS2MD) is started. By writing the specified value to, the output data from the display circuit 74A is output from the LVDS circuit 80 (LVDS1 / LVDS2) (SS4b).

This operation is nothing but the processing of the timing T4 of FIG. 6E, and in this embodiment, the program is designed so that the processing of steps SS4a to SS4b is executed within a predetermined time τ (for example, 20mS) from the timing T2. Has been done. Then, in response to the start of operation (timing T4) of the display circuits 74A and 74B and the LVDS circuit 80, the timekeeping timer TM is restarted from zero (SS4c). The processing procedure of steps SS4a to SS4b is not necessarily limited. Even if the processes of steps SS4a to SS4b are executed in the reverse order, the LVDS circuit 80 outputs useless image data for a moment at most, and the backlight unit BL is turned off. There is no problem.

In any case, in this embodiment, the display circuit 74 is in the V blank start state every 1/60 second, and the LVDS circuit (LVDS1 / LVDS2) 80 is set in accordance with the processing of the above steps SS4a to SS4b. By operating, the display operation shown in FIG. 15 is repeated. In FIG. 15, the start timing of the display operation and the end timing of the display operation indicated by the circles indicate the V blank start timing.

Then, based on this V blank start timing, the horizontal reference point TH0 (= horizontal reference time) and the vertical reference point (= vertical reference time) TV0 in the operation of the display circuit 74 are defined, and the display circuit 74 Stands by without outputting the image data corresponding to each pixel of the display device until the horizontal standby time WTh elapses from the horizontal reference point TH0. Similarly, the display circuit 74 is configured to wait from the vertical reference point TV0 until the vertical standby time WTv elapses without outputting the image data corresponding to each pixel of the display device.

Further, since the display circuit 74B operates in synchronization with the display device 74A (SP4 in FIG. 16), the start and end timings of the display operation of the sub display device DS2 are the same as the timing of the main display device DS1. Therefore, the frame period (519 × 867/27) for the sub-display device DS2 is set shorter than the frame period (1083 × 1662/108) for the sub-display device DS2, so that the sub-display device DS2 starts. The update process is set to be completed.

After the processing of step SS4 having the above meaning is completed, next, it waits for 300 mS to elapse based on the timekeeping timer TM (SS5), and then the control signal PWM to the power supply control circuit SPY is changed from L level to H level. Make a transition (SS6). As a result, the backlight unit BL is in the light emitting state, and the liquid crystal display unit MONI, which has started the operation before this, starts the display operation based on the image data received from the display circuit 74A. Since the display list has not been issued at this timing, the contents of the VRAM are displayed as they are, as described above. Therefore, it is also preferable to entrust the processing of steps SS5 to SS6 to the timer interrupt processing (see the broken line). If such a configuration is adopted, the display list DL has already been issued at the time of timing T5, so that the display list DL is displayed. A predetermined initial screen will be displayed on the device DS1.

Subsequently, the rest of the main body processing, which is a steady processing that is repeatedly executed at predetermined time intervals, will be described with reference to FIG. 22. As shown in FIG. 22, the operation of the effect control CPU 63 includes a main control process (a), a timer interrupt process (b) that is activated every 1 mS, and a reception interrupt process (not shown) that is activated by receiving the control command CMD. , VBLANK interrupt processing (c) that is activated by receiving the VBLANK signal that occurs at the start timing of the V blank (vertical blanking interval) of the display device DS1, and drawing abnormality interrupt processing (c) that occurs when an operation freezes or an irrational instruction command is detected. d) and is configured to include. The description of 20 μS interrupt processing will be omitted.

In the receive interrupt process, the control command CMD received from the main control unit 21 is stored in a predetermined receive buffer so that it can be referred to in the main control process (ST13), and the process ends. Further, in the VBLANK interrupt processing (FIG. 22 (b)), the interrupt counter VCNT is incremented for each VBLANK interrupt (ST15), and at the start timing of the main control processing, 1/30 second based on the value of the interrupt counter VCNT. After grasping the operation start timing of, the interrupt counter VCNT is cleared to zero (ST4).

On the other hand, as shown in FIG. 22B, the timer interrupt processing includes the progress processing (ST18) of the lamp effect and the motor effect, and the sensor signal acquisition process for acquiring the origin sensor signals SN0 to SNn signals, chance button signals, and the like. (ST19) and is included. The lamp effect and the motor effect are controlled based on the effect scenario that centrally manages all the effect operations, and when the effect time reached at the start of the effect managed by the effect counter EN, the motor drive table or The lamp drive table is designed to be specified.

After that, the motor effect proceeds based on the specified motor drive table, and the lamp effect proceeds based on the specified motor drive table. As described above, there is also an embodiment in which the DMAC circuit (first and second DMA channels) 60 functions during the operation of step ST18. The motor effect progresses every 1 mS, but the lamp effect progresses at an appropriate timing longer than 1 mS.

On the other hand, as shown in FIG. 22D, in the drawing abnormality interrupt processing, the status register RGij indicating the operating state of the drawing circuit 76 is READ-accessed to identify the interrupt cause. Specifically, it is specified whether it is (1) a drawing abnormality interrupt due to detection (garbled bit) of an abnormal instruction command or (2) a drawing abnormality interrupt due to an operation abnormality (freeze) of the drawing circuit 76 (ST16a). Then, in the case of a drawing abnormality interrupt based on the detection of an abnormal instruction command, the drawing circuit 76 is initialized by writing a predetermined value to the predetermined system control register RGij (ST16b). This operation is nothing but the individual reset operation of the reset path 4B shown in FIG. 7B.

Next, after confirming the normal termination of the individual reset operation with the predetermined status register RGij, a group of operation parameters defining the operation of the drawing circuit 76 is reset to the predetermined drawing register RGij to end the process (ST16c). .. Then, after adjusting the stack area for storing the return destination address (opening process for erasing the return destination address after the interrupt process), the process proceeds to the process of step ST13 (ST16c).

On the other hand, in the case of a drawing abnormality interrupt based on an operation abnormality of the drawing circuit 76, the WDT circuit 58 is activated by shifting to the infinite loop processing (ST16d), and the entire composite chip 50 is reset. If the CPU circuit 51 is not desired to be reset, a predetermined keyword string may be output to the pattern check circuit CHK and only the VDP circuit 52 may be reset by the reset signal RST (see FIG. 7B). .. In this case, after confirming the normal end of the reset operation of the VDP circuit 52, the process proceeds to steps ST4 and ST13. In addition, in order to avoid over-reading of the control command CMD as much as possible, it is better to shift to step ST13 rather than step ST4, including other cases.

When the entire composite chip 50 is reset, the effect up to that point disappears and the effect control completely returns to the initial state (power-on state). However, when resetting only the VDP circuit 52, the reset operation of the VDP circuit 52 is performed. A series of effect control can be continued, although a predetermined waiting time is generated until the above is completed. Since the effect control CPU 63 controls the image effect, the lamp effect, and the sound effect in a unified manner, there is no unnatural deviation in each effect.

The initial setting process of steps SS1 to SS3 described above is executed based on the initial value setting table SETTABLE (see FIG. 36) in which the register address value of the VDP register RGij and the set value of the register RGij are associated with each other. Will be done. Since the initial setting process has been described above, next, before the steady process (ST4 to ST14) is described, the steady operation (intermittent operation) of the VDP circuit 52 controlled by the effect control CPU 63 is shown in FIGS. 30 (a) and 30 (a). A schematic description will be given based on FIG. 31 (b).

The intermittent operation of the VDP circuit 52 is as shown in FIGS. 30 and 31, and in the embodiment in which the preloader 73 is not used, as shown in FIG. 30A, the display list DLi completed by the effect control CPU 63 is It is issued to the drawing circuit 76 in the operation cycle (T1), and the drawing circuit 76 completes the image data in the frame buffers FBa and FBb by the drawing operation based on the display list DLi. Then, the image data completed in the frame buffers FBa and FBb is output to the display devices DS1 and DS2 by the display circuit 74 in the next operation cycle T1 + δ, and based on the subsequent drawing operation of the display devices DS1 and DS2. , The display screen is detected by the player.

On the other hand, in the embodiment using the preloader 73, as shown in FIG. 31A, the display list DLi completed by the effect control CPU 63 is issued to the preloader 73 in the operation cycle (T1), and the preloader 73 is , Interpret the display list DLi, perform the necessary look-ahead operation, and rewrite a part of the display list DLi to complete the rewrite list DL'. The pre-read CG data and the rewrite list DL'are stored in appropriate places in the DRAM 54.

Next, the drawing circuit 76 acquires the rewrite list DL'from the DRAM 54 in the next operation cycle (T1 + δ), and completes the image data in the frame buffers FBa and FBb by the drawing operation based on the rewrite list DL'. .. Then, the image data completed in the frame buffers FBa and FBb is further output to the display devices DS1 and DS2 by the display circuit 74 in the next operation cycle (T1 + 2δ), so that the subsequent display devices DS1 and DS2 are drawn. The display screen is detected by the player based on the movement.

Although the intermittent operation of the VDP circuit 52 has been schematically described above, in order to realize the above-mentioned operations of FIGS. 30 to 31, the effect control CPU 63 has the value of the interrupt counter VCNT after the initial processing (SS1 to SS3). Is repeatedly referred to, the operation start timing is waited to be reached, and when the operation start timing (one-step V blank start timing) is reached, the interrupt counter VCNT is cleared to zero (ST4).

After that, steady operation is started, but in this embodiment, it is first determined whether or not the operation start condition for starting steady operation is satisfied (ST5). The determination timing is the timing of T1, T1 + δ, T1 + 2δ, ..., That is, the start timing of the vertical blanking interval (VBLANK) of the display device DS1 shown in FIGS. 30 to 31. The display timing of the display device DS2 is set at the time of initial setting (ST3) so as to depend on the display timing of the display device DS1.

Since the operation start condition determined at the start timing of the vertical blanking interval (VBLANK) differs depending on whether or not the preloader 73 is used, an embodiment (FIG. 22) in which the preloader 73 is not used will be described first. In this case, the circuit configuration and the program are originally designed so that the internal operation of the VDP proceeds as shown in the time chart of FIG. 30 (a). That is, based on the display list DL1 completed in the operation cycle (T1), the drawing circuit 76 should finish the drawing operation during the operation cycle (T1 to T1 + δ). However, for example, as in the display list DL3 completed in the operation cycle (T1 + 2δ) of FIG. 30A, it cannot be said that the drawing operation may not be completed during the operation cycle (T1 + 2δ to T1 + 3δ). Further, with respect to the display circuit 74, there is a possibility that an Underrun abnormality has occurred in which the display data is not generated in time for the display timing.

The determination process in step ST5 takes such a situation into consideration, and the effect control CPU 63 accesses the status register RGij (a type of control register group 70) indicating the operating state of the drawing circuit 76, and at the timing of step ST5, The drawing circuit 76 determines whether or not the required operation has been completed and whether or not there is an Underrun abnormality. The presence or absence of the Underrun abnormality is determined based on the underrun counters URCNTa to URCNTc. Further, in the embodiment in which the preloader 73 is not utilized, for example, at the timing T1 + δ in FIG. 30A, the status information of the drawing register related to the drawing circuit 76 is READ-accessed, and the drawing operation based on the display list DL1 is completed. To confirm.

Then, when the operation start condition is not satisfied (abnormality / nonconformity), the abnormality flag ER for counting the number of abnormalities is incremented, and the steps ST6 to ST8 processing are skipped. The abnormality flag ER is determined in the processing of steps ST9 and ST10 together with the other serious abnormality flag ABN, and if the number of continuous abnormalities is not large (ER ≦ 2) on the assumption that the serious abnormality flag ABN is in the reset state, the abnormality flag ER is determined. The effect command analysis process is executed in the same manner as in the normal state (ST13).

Similarly, in the case of an Underrun abnormality, the processes of steps ST6 to ST8 are skipped. Then, the display clock DCK (frequency) and the display circuit 74 are initialized by writing a predetermined clear value to the predetermined system control register RGij (ST10c). After confirming the normal completion of this initialization process, the frequency of the display clock DCK and the value of the group of system control registers RGij that regulate the operation of the display circuit 74 are reset to the specified values (ST10c). , The effect command analysis process is executed (ST13).

In the effect command analysis process (ST13), it is determined whether or not the control command CMD is received from the main control board 21, and if the control command CMD is received, the control command CMD is analyzed and necessary processing is executed. (ST13). Here, the necessary processing includes a process for preparing to start a new variation effect based on the control command CMD instructing the start of the variation effect, and a process for starting error notification based on the control command CMD indicating the occurrence of an error. Subsequently, a clear pulse is output to the WDT circuit (ST14), and the process returns to the process of step ST4.

The case where the error flag ER is ER ≦ 2 has been described above when there is a slight Underrun abnormality or when the operation start condition is incompatible, but in such a case, the display circuit 74 is used in the operation cycle. The process of switching the toggle of the display area read by the user (ST6) and the process of creating the display list (ST7) are skipped, and the effect scenario does not proceed (see ST8 to ST12). This is because the image data of the frame buffers FBa and FBb in an incomplete state is not output. Therefore, for example, in the operation cycle (T1 + 3δ) of FIG. 30A, the image effect does not proceed, and the original screen (screen based on DL2) is redisplayed with a frame drop.

Here, in order to avoid dropping frames, a configuration that waits until the operation start condition is satisfied is also conceivable. However, since there are many control processes (ST6 to ST12) to be executed by the effect control CPU 63 and it is necessary to secure each processing time, in this embodiment, a frame drop occurs when the operation start condition is not satisfied. There is.

However, even if a frame is dropped, the progress of the image effect is only delayed by about 1/30 to 2/30 seconds as compared with the lamp effect and the motor effect that are progressed by the interrupt processing (FIG. 22 (b)). Yes, this is not noticed by the player. Moreover, when the frame is dropped, the effect scenario processing (ST11) including the update process of the effect counter EN and the voice progress process (ST12) are also skipped, so that the reach effect, the advance notice effect, and the accessory to be started after that are also skipped. In the production, there is no possibility that the start timings of the image production, the audio production, the lamp production, the motor production, and the like are shifted.

That is, in the production scenario, the start timings of the image production, the voice production, the lamp production, and the motor production, and the production content to be executed after that are centrally managed, and the production counter EN, which is updated only during normal times, starts the production. Since the timing is controlled, the synchronization of various productions will not be out of sync. For example, if there is an effect operation that combines an explosion sound, an explosion image, an accessory movement, and a lamp flash operation, each of the above effect operations is started correctly in synchronization even after a frame drop occurs. To.

The above is a description of a relatively minor abnormality. However, when the serious abnormality flag ABN is set, the number of continuous abnormalities is large (ER> 2), or when an underrun abnormality occurs repeatedly, step ST10 is performed. After the determination, an infinite loop state is set (ST10b). As a result, the timekeeping operation of the WDT circuit 58 progresses, the composite chip 50 including the effect control CPU 63 is abnormally reset, and then the initial processing (SS1 to SS3) is re-executed, so that an abnormal situation occurs. It is expected that the root cause will be eliminated.

Since this reset operation is executed by starting the WDT circuit 58, the entire composite chip 50 including the CPU circuit 51 is in the reset state (FIG. 7 (b)). Therefore, in order to avoid resetting the CPU circuit 51, the effect control CPU 63 outputs a predetermined keyword string (for example, three 1-byte data) to the pattern check circuit CHK and outputs the reset signal RST to the VDP circuit 52. Is also suitable (see ST100 in FIG. 36). Also in this case, after confirming the normal termination of the reset operation of the VDP circuit 52 (ST101), the process proceeds to the processes of steps ST4 and ST13.

In any case, at the time of this abnormality, the audio circuit SND is also reset abnormally, so that the image effect, the sound effect, the lamp effect, and the motor effect all return to the initial state. However, since these reset operations have no effect on the main control unit 21 and the payout control unit 25, there is no possibility that a situation such as the disappearance of the jackpot state or the disappearance of the prize ball will occur.

Although the abnormal situation has been described above, in reality, the above-mentioned abnormality rarely occurs even in a minor case, and after the processing of step ST5, the setting to the predetermined display register RGIj (DSPACTL / DSPBCTL) is performed. Based on this, the "display area" of the frame buffers FBa and FBb for storing the image data to be read by the display circuit 74A and the display circuit 74B is toggled (ST6). As described above, since the "display area (0)" and the "display area (1)" are defined in advance in the initial processing (ST3), in the processing of step ST6, the frame buffers FBa and FBb are used this time. It is specified whether the "display area" of the above is the display area (0) or the display area (1).

By executing this step ST6, the display circuit 74A alternately outputs image data from the index space 254 (display area (0)) and the index space 255 (display area (1)) for each operation cycle δ. It will be read out and the display device DS1 will be driven. Similarly, the display circuit 74B alternately reads image data from the index space 251 (display area (0)) and the index space 252 (display area (1)) at each operation cycle δ to display the sub-display device DS2. It will be driven. As described above, the display circuit 74 actually performs READ access only to the effective data area in the display area (0) / display area (1).

In any case, in this embodiment, since the "display area" is switched for each operation cycle, the display circuits 74A and 74B use the display devices DS1 and DS2 for the image data completed by the drawing circuit 76 in the immediately preceding operation cycle. The output process to is started. However, since the processing in step ST5 is started from the start of the vertical blanking interval (V blank) of the main display device DS1, the image data output processing is actually started after the vertical blanking interval is completed. Will be done. In FIG. 30A, the arrow shown in the column of the display circuit indicates the operation cycle of this output processing.

After the processing of step ST6 having the above meaning is completed, the effect control CPU 63 subsequently completes the display list DL that specifies the image data to be output to the display device by the display circuit 74 in the next operation cycle. (ST7). Although not particularly limited, in this embodiment, the list buffer area (DL buffer BUF) of the RAM 59 is secured, and the display list DL is completed there (see FIG. 13).

The display list DL is configured by listing a series of instruction commands in an appropriate order, and is configured to end with an EODL (End Of DL) command. Then, in this embodiment, in order to realize smooth operation of the data transfer circuit 72, the drawing circuit 76, and the preloader 73, all the instruction commands including the EODL command are executed by an integer N times (N> 0) having a command length of 32 bits. It is limited to the instruction command of. As described above, the instruction command composed of a 32-bit integer N times may include a don't care bit.

As described above, since the display list DL of the embodiment is composed of only instruction commands having a command length of 32 bits and an integer N times (N> 0), the data volume value (total amount of data) of the entire display list DL is determined. It is always an integral multiple of the minimum unit of command length (32 bits = 4 bytes). Further, in this embodiment, the data volume value of the display list DL is set to an integral multiple (1 or more) of the minimum data amount Dmin in consideration of the minimum data amount Dmin of the data transfer circuit 72, and the instruction command is used. It is adjusted to be an integral multiple of the minimum unit (4 bytes). For example, if Dmin = 256 bytes, the data volume value of the display list DL is adjusted to any value of 256 bytes, 512 bytes, and so on.

Here, it is also preferable to appropriately adjust to 256 bytes or 512 bytes according to the complexity of the effect content, but in this embodiment, there are two display devices, and the sub display device DS2 is The data volume value of the display list DL is always adjusted to 256 bytes in consideration of not performing such a complicated image effect.

However, this method is not limited in any way, and is adjusted to 512 bytes or 768 bytes in the case of three or more display devices or in the case of a gaming machine that executes complicated image production including the sub display device DS2. Will be done. Further, during a normal effect, the data volume value of the display list DL is adjusted to 256 bytes, and the data volume value of the display list DL is adjusted to 512 bytes or 768 bytes only when a special effect is executed. Is also suitable.

However, in the case of this embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) specified in advance in each operation cycle δ. The adjustment method is a simple method (A) that fills the 32-bit length NOP (No Operation) command after the 32-bit length EODL command, or after filling the shortage area with the 32-bit length NOP command. Finally, a standard method (B) in which a 32-bit length EODL command is described can be considered. It should be noted that the data volume value (total amount of data) of the display list DL is terminated by the EODL command without any adjustment, and dummy data is additionally transferred during the operation of the data transfer circuit 72, which is an integral multiple of the minimum data amount Dmin. An unadjusted method (C) for securing the transfer amount of the data can be considered.

Here, when the standard method (B) is adopted, first, the command counter CNT is initially set to a specified value (64-1 corresponding to 256 bytes), and every time a significant instruction command is written to the DL buffer area BUF. A method is conceivable in which the command counter CNT is appropriately subtracted, and when the writing of a series of significant instruction commands is completed, the NOP command is described until the command counter CNT becomes zero, and finally the EODL command is described. In the case of this embodiment, since the command length is limited to an integer N times (N> 0) of 32 bits, the above processing is easy, and the subtraction processing of the command counter CNT is an integer. It is a subtraction process corresponding to N.

On the other hand, when the simple method (A) is adopted, it is sufficient to first fill the entire list buffer area (DL buffer BUF) with the NOP command when creating the display list DL, so at first glance, it is better than the standard method (B). Seems to be excellent. Further, from the viewpoint of simplicity, the non-adjustment method (C) seems to be excellent. However, in this embodiment, the standard method (B) is basically adopted, and the actual data amount from the beginning of the display list DL to the EODL command, that is, the data amount up to the EODL command is always the data transfer circuit 72. The minimum data amount of Dmin is adjusted to be an integral multiple of Dmin.

This is in consideration of an embodiment using the preloader 73, and if the simple method (A) or the non-adjustment method (C) is adopted, the actual data amount of the display list DL up to the EODL command is random. This is because the value becomes a value, and problems occur when transferring the rewrite list DL'rewritten by the preloader 73 to the DRAM 54 or when transferring the rewrite list DL'from the DRAM 54 to the drawing circuit 76. The ChA control circuit 72a of the data transfer circuit 72 functions when the rewrite list DL'is transferred to the DRAM 54, and the ChB control circuit 72b functions when the rewrite list DL'is transferred to the drawing circuit 76 (FIG. 28). (See), in either case, only the rewrite list DL'up to the EODL command will be transferred.

The advantages of the standard method (B) for adjusting the data volume value of the display list DL have been described above, but in the embodiment in which the preloader 73 is not used, the issued display list DL is only processed by the drawing circuit 76. Therefore, the use of the simple method (A) and the non-adjustment method (C) is not prohibited at all.

However, in the following description, the details of the display list DL will be described with reference to FIG. 23 on the premise that the standard method (B) is adopted in principle regardless of whether or not the preloader 73 is used.

Although not particularly limited, in the present embodiment, the instruction command sequence (L11 to L16) relating to the main display device DS1 is first described in the display list DL, and then the instruction command sequence (L17 to L20) relating to the sub display device DS2 is described. I am trying to describe it. Further, the standard method (B) is adopted to adjust the data volume value of the display list DL to a fixed length (256 bytes). Note that FIG. 23 also shows, in effect, the procedure in which the effect control CPU 63 writes an instruction command to the list buffer area of the RAM 59, and the operation of the drawing circuit 76 based on the display list DL.

As shown in FIG. 23, at the beginning of the display list DL, an instruction command (SETDAVR) of the environment setting system is described, and the upper left base point address (X, Y) on the index space IDX is set for the frame buffer FBa of the display device DS1. Specify (L11). As described with respect to FIG. 12A, in this embodiment, a pair of frame buffers FBa are secured in the arbitrary area (c) for the display device DS1. Then, normally, by setting the base point address (X, Y) = (0,0) corresponding to the effective data area for the display circuit 74, the drawing circuit 76 is utilized from the head position of the frame buffer FBa. ..

In FIG. 12 (c), L11 is attached to the actual drawing area on the lower left side thereof, which means that the actual drawing area on the frame buffer FBa is set to the base point address (0,) of the frame buffer FBa by the instruction command L11. 0) It means that it was specified to start from the position. However, the vertical and horizontal dimensions of the actual drawing area and the index number that specifically specifies the actual drawing area are still undecided, and are determined by the instruction command (SETINDEX) L13 described later. The instruction command L11 also specifies whether or not to use the Z buffer.

Next, the upper left base point coordinates (Xs, Ys) and the lower right diagonal point coordinates (Xe, Ye) are set on the virtual drawing space by the instruction command (SETDAVF) of the environment setting system, and the W × H dimension is set. The drawing area of is defined (L12). Here, the virtual drawing space is a virtual two-dimensional space in the X direction ± 8192 and the Y direction ± 8192 that can be drawn by an instruction command for drawing (SPRITE command or the like) (see FIG. 12 (c)). ..

By this instruction command L12 (SETDAVF), the virtual drawing space is divided into a drawing area in which the drawing contents are actually reflected on the display device DS1 and other non-drawing areas. Further, the instruction command L12 (SETDAVF) associates the actual drawing area whose start position (base point address) is defined by the instruction command L11 with the drawing area on the virtual drawing space.

In other words, the instruction command L12 defines a W × H actual drawing area starting from the base point address, which corresponds to the drawing area on the virtual drawing space, in the frame buffer FBa (index space is undecided). It will be. Therefore, the drawing area specified by the instruction command L12 needs to be the same as or smaller than the horizontal size of the frame buffer FBa. Normally, the drawing area and the actual drawing area are defined so as to have the same dimensions as the effective data area (FIG. 22 (e)) for the display circuit 74.

Then, after the drawing circuit 76 executes the instruction commands L11 and L12, only the drawing contents drawn in the virtual drawing space, which are included in the drawing area, are reflected in the actual drawing area of the frame buffer FBa. become. Therefore, the drawing contents of the portion protruding from the drawing area and the portion described as the work area in FIG. 12C are not reflected in the frame buffer as they are. When securing a work area in the virtual drawing space, the non-drawing area of the virtual drawing space is used.

Next, in this operation cycle, the drawing circuit 76 defines where to draw the drawing content to be drawn based on the display list DL to be completed (L13). Specifically, for the frame buffer FBa of the display device DS1 having a double buffer configuration, the index space IDX which is the "write area" of the drawing contents based on the display list DL this time is specified (L13). Specifically, by the SETINDEX command, which is a texture setting command, (1) the frame buffer FBa is secured in an arbitrary area, and (2) the index space IDX _N that becomes the "write area" is arbitrary. The index number N on the area is specified.

When, for example, N = 255 is specified by this instruction command L13, the actual drawing area corresponding to the drawing area defined on the virtual drawing space is specifically in the frame buffer FBa having a double buffer structure. It is defined as the index space IDX ₂₅₅ .

In the case of this embodiment, the index number of the frame buffer FBa is 255 or 254 (FIG. 12 (a)), and either toggled switch is specified (L13). Note that this index number is an index number that is not the display area (0) / (1) specified in step ST6 of the main control process. For example, in the process of step ST6, when the display area (0) is designated for the display circuit 74, the display area (1) becomes the “write area” for the drawing circuit 76.

As described above, after the correspondence between the actual drawing area (W × H logical space) and the drawing area (W × H virtual space) is generally defined by the instruction command L11 and the instruction command L12, By the instruction command L13 (SETINDEX) that specifically specifies the index space IDX, the virtual space of W × H is associated with the logical space of W × H in the specific index space IDX.

In other words, in the future, the content virtually drawn in the W × H virtual space based on a series of instruction commands will be inside the VDP that defines the correspondence between the virtual space and the real address of the built-in VRAM 71. Based on the conversion table, it becomes the image data of the built-in VRAM 71 (frame buffer).

Subsequently, as a "write area", an instruction command for executing a frame buffer clear process for filling the specified index space IDX with black, for example, is described (L14, L15). This is nothing but the erasing process of the image data written in the frame buffer FBa before the two operation periods.

Specifically, the SETFCOLOR command, which is a type of environment setting command, selects black, for example, and the RECTANGLE command, which is a primitive drawing command, specifies that the rectangular area should be filled. In the RECTANGLE command, the XY coordinates of the upper left end point and the lower right end point of the drawing area (virtual space corresponding to the frame buffer FBa) set in the virtual drawing space are specified (see FIG. 12 (c)). ..

Since the drawing preparation process is completed by the above processing, next, instruction commands for drawing an appropriate texture such as a still image or a moving image frame in the virtual drawing space are listed. Typically, first, the index space IDX to which the texture is expanded is specified by the SETINDEX command of the texture setting system, and then the TXLOAD command, which is the instruction command of the texture load system, is described and read from the CGROM 55. The texture is described in the display list DL so as to expand into a predetermined index space IDX.

As described above, in this embodiment, the background moving image is composed of the IP stream moving image. Therefore, for example, for the background video, the index space IDX to be expanded is specified as the index space IDX ₀ in the page area (b) by the SETINDEX command of the texture setting system, and then the TXLOAD command of the texture load system is described. do. In the TXLOAD command, it is necessary to specify the start address (texture source address) of the CGROM 55 and the expanded data size (horizontal x vertical) for the moving image frame to be loaded this time.

When the above TXLOAD command is executed in the VDP circuit 52, one moving image frame (texture) of the background moving image is first acquired in the AAC area (a), and then the page area (page area (texture) is automatically activated by the GDEC75. b) Expands to index space IDX ₀ in. Next, this one moving image frame will be drawn in the virtual drawing space. In this case, the SETINDEX command (texture setting system) may be used to set "index space IDX ₀ in the page area (b) is the texture to be processed thereafter", but the TXLOAD command is continuously processed. If so, the description of this SET INDEX command can be omitted.

In any case, in the state where "the index space IDX ₀ in the page area (b) is the texture to be processed after that" is specified, then the parameters for the α blend processing are set, and so on. Describe the instruction command of the appropriate inter-drawing operation system. The α-blending process relates to a transparent / semi-transparent process between an image already described in the drawing area (frame buffer FBa) and an image to be overwritten. Therefore, it is not necessary to use the instruction command of the inter-drawing calculation system in the drawing operation of the first sheet as in the moving image frame of the background moving image.

Then, by using the SPRITE command, which is an instruction command for primitive drawing, "texture of index space IDX ₀ in page area (b) (one video frame of background video)" is set in place in the virtual drawing space (rectangular destination area). Describe the SPRITE command to draw in. For the SPRITE command, it is necessary to specify the upper left end point and the right lower end point of the Destination area of the virtual drawing space.

This Destination area is the whole or a part of the drawing area (virtual space defined on the virtual drawing space) associated with the actual drawing area (FBa) in advance by the instruction commands L11 and L12. However, since the background moving image is usually drawn on the entire display screen, the Destination area in such a case is the entire drawing area or more. The case where the Destination area is larger than the entire drawing area is, for example, the case where the background moving image is zoomed up.

Since the drawing of the video frame of the background video is completed by the above processing, the instruction commands such as the texture load system, the texture setting system, the inter-drawing calculation system, and the primitive drawing system commands are listed in an appropriate order. The display list DL is configured to draw various textures on the background moving image. As described above, a large number of moving images are required during the variable effect. In that case, the index table control system is instructed to increase the index space IDX for the page area (b) of the built-in VRAM 71. The command (NEWPIX) will be described.

For example, for the second IP stream video, the NEWPIX command allocates an additional index space IDX ₁ in the page area (b), then specifies this index space IDX ₁ (SETINDEX), and then the second Instructs the expansion of one frame of the video (TXLOAD), and places the expanded texture in the appropriate place in the drawing area (SPRITE). Normally, the Destination area in this case becomes a part of the drawing area.

The same applies to the following. If the index space IDX _k is secured one after another by the NEWPIX command and then a plurality of IP streams are drawn in the drawing area while performing appropriate α-blending processing, the drawing contents in the drawing area will be the same. , It will be sequentially accumulated as image data in the frame buffer FBa which is the actual drawing area. When a plurality of N IP stream moving images are drawn, a plurality of N index spaces are functioning in the page area (b).

Then, when a series of fluctuation effects are completed, the DELPIX command is used to release the index space IDX that is considered unnecessary among the large number of index spaces IDX ₁ to IDX _k secured in the page area (b). The unnecessary index space IDX may be deleted.

When drawing a still image or I-stream movie, use the SETINDEX command to specify that the decoding destination of these textures is the AAC area (a), and then execute the TXLOAD command to execute the AAC area. The texture acquired in (a) is then expanded into the ACC area (a) by the automatically activated GDEC75. Then, the expanded texture may be drawn in a suitable place in the drawing area by the SPRITE command. The first AAC region (a1) or the second AAC region (a2) is used depending on whether or not the cache hit function is utilized.

In the description so far, each texture is directly drawn in the drawing area of the DS1 for the main display device, but is not necessarily limited to such an operation. For example, if an appropriate drawing area is provided (FIG. 12 (c)) in a state where it does not overlap with the drawing area already reserved for the display device DS1, and this drawing area is associated with the work area of the built-in VRAM 71, it is intermediate. It is possible to construct an appropriate drawing area and complete an appropriate effect image. Here, the reason why the drawing area does not overlap with the drawing area for the display device DS1 is that the later association setting is prioritized for the overlapping area and the drawing contents in the area are not reflected in the frame buffer FBa.

As shown in FIG. 12 (c), the work area of this embodiment is the index space IDX ₀ in the arbitrary area (c). Then, in the effect timing using this work area, an instruction command for associating the drawing area for the effect image (see FIG. 12C) with the work area (actual drawing area of index space IDX ₀ ) is preceded. Describe the columns (SETDAVR, SETDAVF, SETINDEX). As shown in FIG. 12 (c), the drawing area for the effect image is secured in the area not included in the drawing area for the main display device DS1.

Then, after that, the same instruction command as the instruction command sequence L16 regarding the frame buffer FBa may be listed, and an appropriate effect image may be completed in the index space IDX ₀ . In the case of this embodiment, since the effect image is composed of a still image, an instruction command (SETINDEX) is described so that the decoded data is expanded in the first AAC region (a1), and then the index space IDX ₀ A primitive drawing-type instruction command (SPRITE) with the destination in the drawing area will be used. It should be noted that such an operation is repeated once or a plurality of times depending on the content of the effect.

Then, after positioning the index space IDX ₀ that has completed the effect image as a texture (SETINDEX), the effect image (texture) of the index space IDX ₀ is drawn at an appropriate position in the drawing area of the DS1 for the main display device by the SPRITE command. Just do it. In such a case, it is conceivable to decompose the effect image of the index space IDX ₀ into triangular drawing primitives, rotate them at an appropriate angle, and then draw them in the drawing area. The rotation angle of the texture is associated with, for example, the reliability of the advance notice effect.

The instruction command sequence (L11 to L16) for completing one frame of the main display device DS1 has been described above, but the instruction command sequence (L17 to L12) for completing one frame of the sub display device DS2 has also been described. The same is true. That is, the start XY coordinates of the frame buffer FBb are specified (L17), defined (usually X = 0, Y = 0), and on the virtual drawing space shown in FIG. 12 (c), for the sub-display device DS2. A drawing area is defined (L18).

By the way, in this embodiment, after the generation of the image data for the main display device DS1 is completed, the process shifts to the generation process for the sub display device DS2, so that the drawing area for the sub display device DS2 is for the main display device DS1. There is no problem even if it overlaps with the drawing area of, and the drawing area can be set freely. Therefore, when developing a display list DL generation program, for example, when pasting an appropriate texture to a newly set drawing area with the SPRITE command, set the operation parameters (Destination area) of the SPRITE command and so on. It can be stylized to some extent.

After the definition of such an arbitrary drawing area is completed (L18), next, for the frame buffer FBb of the display device DS2 having a double buffer configuration, the index space becomes the "write area" of the drawing contents based on the display list DL this time. Identify the IDX (L19). The index number of the index space IDX is the index number of the frame buffer FBb that does not correspond to the display area (0) / (1) specified in step ST6 of the main control process.

After that, the instruction command sequences L20 to L22 for the sub display device DS2 are listed in the same manner as the instruction command sequences L14 to L16 for the main display device DS1. It is also possible to use the effect image completed in the index space IDX ₀ .

As described above, all the instruction commands of L11 to L22 constituting the display list DL are limited to those having a command length that is an integral multiple of 32 bits in this embodiment. Then, as described above, the data volume value (total amount of data) of the display list DL of this embodiment is adjusted to a fixed length (256 bytes), and the required number of NOP commands (L23) as dummy commands are added. After that, it is terminated by the EODL command (L24). That is, in the embodiment of FIG. 23, the above-mentioned standard method (B) is adopted.

However, even when the standard method (B) is adopted, it is not always essential to fix the total amount of data in the display list DL to 256 bytes in all operation cycles. That is, in another embodiment, when the total amount of data in the display list DL excluding the NOP command exceeds 256 bytes (for example, during a special effect period), the total amount of data in the display list DL is added with the NOP command. Is adjusted to 512 bytes or more, N × 256 bytes. As described above, when the standard method (B) is adopted, the end of N × 256 bytes is terminated by the EODL command.

Although the configuration of the display list DL has been described in detail above, the effect control CPU 63 will issue the completed display list DL having a fixed byte length to the VDP circuit (ST7 to ST8). FIG. 24 is a flowchart illustrating a DL issuance process (ST8 in FIG. 22) in which the effect control CPU 63 directly accesses the transfer port register TR_PORT of the transfer circuit 72 to issue a display list DL to the drawing circuit 76. The transfer port register TR_PORT is a type of data transfer register RGij that defines the operation content of the data transfer circuit 72.

In order to realize the DL issuance process, it is first necessary to set necessary setting values in a plurality of data transfer registers RGij that define the operation contents of the data transfer circuit 72. Specifically, the transfer operation mode of the data transfer circuit 72 and the transmission via the inside of the data transfer circuit 72 are specified in the predetermined data transfer register RGij. The setting contents are not particularly limited, but here, when the data transfer operation is executed while checking the remaining amount of the FIFO buffer with respect to the CPU IF unit 56 via the ChB control circuit 72b and the CPU bus control unit 72d. Set (ST20). In the following description, the ChB control circuit 72b may be abbreviated as "transfer circuit ChB" for convenience.

Next, the total transfer size is set in the predetermined data transfer register RGij. As described above, in this embodiment, the total amount of data in the display list DL is adjusted to an integral multiple of 256 bytes, so that value is set. The total amount of data = 256 × N is also an integer N times the minimum amount of data Dmin of the data transfer circuit 72. Normally, the multiple N is 1 or 2, but in the following description, it will be described as N = 1.

Here, since the transfer port register TR_PORT (hereinafter, may be abbreviated as a transfer port) is a 32-bit length register, the effect control CPU 63 executes a register WRITE operation for the transfer port TR_PORT every 32 bits. It will be. Therefore, the value of the management counter CN that manages the number of register WRITEs is initially set to 64 (ST21). When the non-adjustment method (C) is adopted, the data transfer amount that is an integral multiple of the minimum data amount Dmin is determined at this timing, and the management counter CN is set.

Since the initial setting is completed by the above processing, next, the data transfer operation via the transfer circuit ChB is set to the start state (ST22), and the setting to the predetermined drawing register RGij that regulates the operation of the drawing circuit 76 is set. The drawing operation is started based on the value (ST23). As a result, after that, the effect control CPU 63 guarantees a quick and smooth Analyze process by the drawing circuit 76 (display list analyzer) for the instruction command sequence in which the register WRITE operation is performed on the transfer port TR_PORT.

It should be noted that the fact that the instruction commands listed in the display list DL are limited to the instruction commands having a command length of 32 bits, which is an integral multiple of the command length, also contributes effectively to the quick and smooth Analyze processing. The timings t1, t2, t3, and t4 in FIG. 30A indicate the operation timing of step ST23. Since the display list DL issuance process (ST8) is completed quickly, the time width required for the issuance process is not shown in FIGS. 30 to 31.

Then, it is confirmed whether or not the setting of step ST22 has worked (ST24). This is because the initial setting of each part of the data transfer circuit 72 takes more processing time than the register WRITE operation (setting operation) by the effect control CPU 63, so a subsequent instruction is given to the data transfer circuit 72 in an incomplete state. Because there is no such thing. Then, if the operation start state is not reached even after waiting for a predetermined time, the critical abnormality flag ABN is set and the DL issuance process is completed (ST25). As a result, after that, the WDT circuit 58 functions and the composite chip 50 is abnormally reset (ST10).

The effect control CPU 63 may output a predetermined keyword string to the pattern check circuit CHK and abnormally reset only the VDP circuit 52 based on the reset signal RST in order to avoid resetting the CPU circuit 51. As mentioned above.

However, since the setting of step ST22 is normally completed quickly, it is subsequently confirmed that the FIFO buffer (32 bits x 130 stages) of the CPU bus control unit 72d is not full (ST26). , Write the instruction command to the transfer port TR_PORT line by line in order from the first line constituting the display list DL (ST28).

Then, while decrementing the management counter CN (ST29), the processes of steps ST26 to ST29 are repeated until the management counter CN becomes zero (ST30). In the case of this embodiment, since the minimum data amount Dmin is specified in the data transfer circuit 72, the data transfer operation is executed at the timing when the minimum data amount Dmin is accumulated in the FIFO buffer, which is intermittent. Transfer operation.

In any case, in this embodiment, the DL issuance process (ST28) is completed quickly, but if the settings to the VDP register RGIj are inconsistent due to the influence of noise or the like, step ST26 is performed. In the determination, the state of the FIFO buffer Full may not be resolved even after waiting for a predetermined time. Then, in such a case, the initialization data is set in the predetermined VDP register RGij, the drawing circuit 76 and the data transfer circuit 72 are initialized, and then the serious abnormality flag ABN is set and the DL issuance process is performed. Finish (ST27).

By the way, at this timing, the data transfer circuit 72 and the drawing circuit 76 have already started operation and have completed some processing. Therefore, in the initialization processing of the drawing circuit 76, the contents of the drawing register RGij are used. While maintained, (1) set all internal parameters that may be set by the display list DL to the initial values, (2) set all internal control circuits to the initial state, (3). It includes initializing the GDEC75 and (4) initializing the cache state of the AAC area. Similarly, the initialization process of the data transfer circuit 72 includes the initialization process of the entire data transfer up to that point, such as clearing the FIFO buffer. As a result, the status information indicating the operating state of the data transfer circuit 72 changes to a predetermined value (a value indicating that the entire data transfer is being initialized).

In the initialization process of step ST27 described above, the contents of the drawing register RGij are maintained, but the contents of the predetermined drawing register may be initialized. The predetermined drawing registers that are cleared to the initial values include (a) an execution control register that sets the start of drawing execution (see ST23 in FIG. 24), (b) a status register that indicates the execution status of the drawing circuit 76, and ( c) Contains a status register that identifies the location of the display list currently being processed.

In any case, as a result of setting the serious abnormality flag ABN, the WDT circuit 58 and the effect control CPU 63 function thereafter, and the composite chip 50 or the VDP circuit 52 is abnormally reset (ST10a), so that the drawing circuit 76 And the process of initializing the data transfer circuit 72 is not always essential. On the other hand, when the drawing circuit 76 and the data transfer circuit 72 are initialized, as a result, abnormal recovery can be expected. Therefore, the DL issuance process is repeated by returning to the process of step ST20 without setting the serious error flag ABN. It is also suitable to carry out.

This point is the same in the process of step ST25, and it is preferable to initialize the data transfer circuit 72 and the drawing circuit 76 and then return to the process of step ST20 without setting the serious abnormality flag ABN. However, in such a case, the number of re-executions of the DL issuance process is counted, and if the number of re-executions exceeds the limit value, the serious abnormality flag ABN is set and the DL issuance process is completed.

FIG. 24B is a confirmatory illustration of a normal operating state. As shown in the figure, the issued display list DL is analyzed by the drawing circuit 76 (display list analyzer) in the order of the listed instruction commands, and the operation based on each instruction command is executed. This operation is executed in parallel with the display list DL issuance process and the data transfer operation (ST26 to ST30) of the data transfer circuit 72.

For example, when the instruction command (TXLOAD) is executed, the necessary texture is read from the CGROM 55 and acquired in the AAC area (a), and then the GDEC75 is automatically started to execute the decoding operation and decode. Later data is expanded into a given index space. Further, depending on the instruction command, the geometry engine 77 and others function, but in any case, the image data corresponding to the display list DL is completed in the frame buffers FBa and FBb by the cooperation of each part of the drawing circuit 76. Will be.

Subsequently, a case where the display list DL is issued via the DMAC circuit 60 will be described with reference to FIG. 25. Although not limited in any way, the third DMA channel among the first to fourth DMA channels built in the DMAC circuit 60 will be used.

In the embodiment of FIG. 25, first, the data transfer circuit 72 and the drawing circuit 76 are initialized by setting clear values in the predetermined data transfer register RGij and the predetermined drawing register RGij, respectively (ST20). This processing is the same as the error processing in step ST27 of FIG. 24, the internal circuit of the data transfer circuit 72 including the FIFA buffer is initialized, and the status bit of the data transfer register indicating the progress status of the data transfer is the initial value. And the bit indicating that the entire data transfer is being initialized becomes a predetermined value.

The same applies to the drawing circuit 76, and the above-mentioned (1) setting the internal parameters to the initial values, (2) setting the internal control circuit to the initial state, (3) initializing the GDEC75, and (4) ) A process to initialize the cache state of the AAC area is included. Further, in the initialization process of the drawing circuit (ST20 in FIG. 25), the predetermined drawing register RGij may be initialized. In the process of FIG. 24, such an initialization process may be executed first.

In the process of FIG. 25, next, it is confirmed by READing the predetermined status register RGij that specifies the operating state of the data transfer circuit 72 and the drawing circuit 76 that the initialization process is completed normally (ST21). If the initialization cannot be performed, the serious abnormality flag ABN is set and the process is completed (ST22). However, such a situation rarely occurs in reality.

Next, the transfer operation mode of the data transfer circuit 72 and the transmission via the inside of the data transfer circuit 72 are set in the predetermined data transfer register RGij. The content of the setting is not particularly limited, but here, it is set to follow the setting to the DMAC circuit 60 regarding the transfer protocol from the CPU IF unit 56 to the CPU bus control unit 72d via the ChB control circuit 72b (ST23). ).

Next, the total transfer size is set in the predetermined data transfer register RGij. As in the case of FIG. 24, the total amount of data = 256. When the non-adjustment method (C) is adopted, the total transfer size that is an integral multiple of the minimum data amount Dmin is determined and set at this timing. Next, the drawing operation of the drawing circuit 76 is started based on the set value in the predetermined drawing register RGij (ST25). The timings t1, t2, t3, and t4 in FIG. 30A are also the operation timings of step ST25. Then, after starting the operation of the DMAC circuit 60 (ST26), the data transfer operation of the data transfer circuit 72 is started (ST27).

The process of starting the operation of the DMAC circuit 60 is as shown in FIG. 25 (b). First, with the DMAC transfer prohibited, the transfer of one cycle of the data transfer unit (1 operand) is waited for to be completed (1). ST40). The detailed operation content is the same as the process shown in FIG. 26, and is divided into a process for prohibiting DMAC transfer (ST53) and a subsequent standby process (ST54).

Such processing is provided (1) In another embodiment, the DMAC circuit 60 (third DMA channel) may be used in the main control processing and the timer interrupt processing (FIG. 22). (2) In another embodiment in which the process of step ST5 of FIG. 22 is not provided, the DMAC circuit 60 that has started issuing the display list DL may not be able to end the DL issuing operation within the operation cycle (δ). It takes into consideration the possibility.

In the above exceptional situation, if a new setting value (inconsistent setting value, etc.) is additionally set for the DMAC circuit 60 in operation, normal DMA operation is not guaranteed at all, and serious trouble occurs. Although there is concern, by providing the process of step ST40, normal operation based on the subsequent set value is guaranteed. That is, even in the modified embodiment in which the present embodiment is partially modified, the subsequent normal DMA operation can be realized regardless of the preceding trouble.

After executing the process of step ST40 having the above meaning, the operating conditions of the DMAC circuit 60 are next set (ST41). Specifically, as shown in FIG. 9, the cycle steal transfer mode is selected, and one operand transfer is set to 32 bit transfer × 2 times. Further, since the Source address is the address of the list buffer area (DL buffer BUF) of the RAM 59, it should be recognized as increasing sequentially, while the Destination address should be a fixed value because it is the transfer port TR_PORT. ..

Next, the start address of the DL buffer BUF of the RAM 59 is set in the predetermined operation control register REG that defines the operation of the DMAC circuit 60 (ST42), and the address of the transfer port TR_PORT, which is the transfer destination address, is set (ST43). ). Further, after setting the total transfer size, that is, the total amount of data in the display list DL to 256 bytes (ST44), the DMA operation of the DMAC circuit 60 is started (ST45).

By the way, the description so far is based on the premise that the actual bit lengths of the instruction commands are all integral multiples of 32 bits. However, since the configuration of the display list DL and the instruction command is not necessarily limited, such a case will be described below.

For example, when the total data amount X of the display list DL is an arbitrary value X that is not an integral multiple of 32 bits, including the case where the above-mentioned non-adjustment method (C) is adopted, in the processing of step ST44, this arbitrary value X Is adjusted to an appropriate transfer amount MOD, and then the transfer total size setting process is executed. Here, the appropriate transfer amount MOD is defined based on the setting contents for one operand transfer and the minimum data amount Dmin (bytes) of the data transfer circuit 72.

Specifically, if one operand transfer setting is N bytes × M times, the transfer amount MOD is adjusted to an integer multiple of N × M (bytes) and an integral multiple of Dmin (bytes). Will be done. For example, if N × M = 8 × 4 and Dmin = 256, the arbitrary value X (= 300) bytes are adjusted to the transfer amount MOD (= 512) bytes.

As described above, the DMA operation of the DMAC circuit 60 has started the cycle steal transfer operation as shown in FIG. 9, and the display list DL is the embodiment without particularly disturbing the operation of the CPU. In this case, it is transferred to the transfer port TR_PORT every 32 bits. Then, the transferred data is transferred to the drawing circuit 76 via the transfer circuit ChB.

In order to realize such an operation, in this embodiment, following the process of step ST45, the transfer operation of the data transfer circuit 72 is started and the process is completed (ST27). After that, the data transfer circuit 72 receives the instruction command sequence of the display list DL from the DMAC circuit 60 with the minimum data amount Dmin as one unit, and transfers this to the drawing circuit 76. Then, the drawing circuit 76 executes the drawing operation based on the instruction command of the display list DL. Therefore, after the process of step ST27, the effect control CPU 63 can start the process of step ST11 of FIG. 22, and the sound effect is produced in parallel with the drawing operation by the VDP circuit 52 (DL issuance process by the DMAC circuit 60). It is possible to control the lamp effect and the motor effect.

FIG. 25 (c) illustrates this operation content. Prior to the DMA transfer, the operation of the drawing circuit is started (ST25), the display list analyzer of the drawing circuit 76 executes the Analyze process quickly and smoothly, and other operations such as the GDEC75 and the geometry engine 77 are performed. Based on this, in the frame buffers FBa and FBb, image data for each frame is generated for each display device DS1 and DS2.

By the way, the configuration of FIG. 25 in which the DL issuance process is completed by the process of step ST27 is not necessarily limited. For example, as shown in FIGS. 32 to 33, when another CPU controls the audio effect, the lamp effect, and the motor effect, the DMAC circuit 60 and the data transfer circuit 72 normally operate after the processing of step ST27. It is preferable to confirm. FIG. 26 is an operation following step ST27 in FIG. 25, and is a flowchart illustrating a confirmation process of normal operation.

First, it is confirmed that the transfer operation of the DMAC circuit 60 is normally completed by referring to a predetermined status register (ST50). Further, it is confirmed that the data transfer circuit 72 has finished the transfer operation (ST51). Normally, the DL issuance process of FIG. 25 is completed by such a route.

On the other hand, even if you wait for a predetermined time. If the operation of the DMAC circuit 60 is not completed, or if the data transfer circuit 72 has not completed the transfer operation, a clear value is set in the predetermined VDP register RGij for the drawing circuit 76 and the data transfer circuit 72. Then, the DL issuance process is initialized (ST52). This is an operation based on the fact that the display list DL issuance process has not been completed normally, and specifically, it has the same contents as the error process in step ST27 in FIG. 24 and the initial process in step ST20 in FIG. 25. be.

That is, also in this case, since the drawing circuit 76 has already started the operation and has completed some processing, the initialization processing of the drawing circuit 76 may be set by (1) the display list DL. Set all internal parameters to the initial values, (2) set all internal control circuits to the initial state, (3) initialize the GDEC75, (4) initialize the cache state of the AAC area. Is included.

Next, after prohibiting a new DMA transfer operation (ST53), it waits for the transfer operation of one operand being executed to end (ST54). As described above, in this embodiment, 32 bit transfer × 2 times is set as one operand, and this is to avoid sudden initialization of the DMAC circuit 60 in operation.

Then, when this preparatory work is completed, a clear value is set in a predetermined operation control register REG that defines the operation of the DMAC circuit 60, and the DMAC circuit 60 is initialized (ST52). Then, the serious abnormality flag ABN is set and the DL issuance process is completed. In this case, since abnormal recovery can be expected by the processing of steps ST52 and ST55, it is also preferable to return to step ST20 of FIG. 25 and re-execute the DL issuance processing without setting the serious abnormality flag ABN. be. However, it is necessary to count the number of re-executions of the DL issuance process (ST23 to ST27), and if the number of re-executions exceeds the limit value, set the serious abnormality flag ABN and finish the DL issuance process.

Subsequently, the main control process when the preloader 73 is used will be described with reference to FIG. 27. The process of FIG. 27 is similar to the process of FIG. 22, but first, the content of the start condition determination (ST5') is different. That is, in the embodiment using the preloader, the status information of the drawing circuit 76 and the preloader 73 is READ-accessed at the start of each operation cycle to complete the drawing operation based on the display list DL1 and the display list DL2. Confirm that the preload operation based on is completed (ST5').

As shown in the time chart of FIG. 31A, for example, the preloader 76 has a look-ahead operation (preload operation) during the operation cycle (T1 to T1 + δ) based on the display list DL1 issued in the operation cycle (T1). Should have finished. Further, the drawing circuit 76 should have completed the drawing operation based on the display list DL1 during the operation cycle (T1 + δ to T1 + 2δ) based on the operation start command instructed in the operation cycle (T1 + δ), for example.

Therefore, in (ST5'), the status information of the VDP register RGij regarding the drawing circuit 76 and the preloader 73 is READ-accessed to confirm the above-mentioned normal operation. FIG. 31A shows a state in which normal operation is confirmed at the determination timing of the operation cycle T1, T1 + δ, T1 + 2δ, T1 + 4δ, but the preload operation is not completed at the determination timing of the operation cycle T1 + 3δ. ..

Then, at the time of such an abnormality, the abnormality flag ER is incremented (ER = ER + 1), and then the process is shifted to the process of step ST9. Therefore, as in the case of the embodiment of FIG. 22, frame dropping occurs. That is, since the display area switching process (ST6) is skipped, the same screen is redisplayed. The operation period (T1 + 3δ to T1 + 4δ) shown in FIG. 30A indicates the operation state.

Further, in the determination of step ST5', if the start condition is not satisfied, the drawing operation start instruction (PT10) based on the rewrite list DL'is not executed for the drawing circuit 76, so that the drawing circuit 76 does not operate. It is in a state and no new display list is generated. In FIG. 31A, the timings t0, t2, and t4 indicate the operation timing of the drawing operation start instruction (PT10), or more accurately, the timing of step ST26 in FIG. 28.

The case where the determination in step ST5'is incompatible has been described above, but in a normal case, after switching the display areas of the frame buffers FBa and FBb in a toggle manner (ST6), the rewrite list DL is applied to the drawing circuit 76. 'The drawing operation based on'is started (PT10). The specific contents are as shown in FIG. 28, and the drawing circuit 76 is based on the control of the effect control CPU 63, via the data transfer circuit 72 (transfer circuit ChB), from the DL buffer BUF'of the external DRAM 54. The rewrite list DL'is acquired and the drawing operation is executed.

Prior to explaining the flowchart of FIG. 28 that realizes this operation, when the operation of the preloader 73 is confirmed, the preloader 73 preloads the CGROM 55 based on the display list DL acquired one operation cycle before. The pre-read data has already been stored in the preload area secured in the external DRAM 54. Further, for the texture load type command (TXLOAD) described in the display list DL, the source address is rewritten to the address of the preload area, and the rewrite list DL'is stored in the DL buffer BUF' of the external DRAM 54. ing.

In this rewriting process, the total amount of data in the display list DL does not change, and the total amount of data in the rewriting list DL'is the same as that in the display list DL. Further, the display list DL is created by the standard method (B), and the end of the rewrite list DL'is an EODL command as in the case of the display list DL.

Based on the above, FIG. 28 will be described. First, the effect control CPU 63 sets clear values in the predetermined data transfer register RGij and the predetermined drawing register RGij, respectively, and sets the data transfer circuit 72 and the drawing circuit 76. Initialize (ST20). This process has the same contents as the process of ST20 in FIG. Next, it is confirmed that this initialization process is completed normally (ST21), and if the initialization is not completed even after a predetermined time has elapsed, the serious abnormality flag ABN is set and the process is completed (ST21). ST22).

Normally, the initialization of the data transfer circuit 72 and the drawing circuit 76 ends normally, so that the transmission via the inside of the data transfer circuit 72 is subsequently set in the predetermined data transfer register RGij (ST23). Specifically, it is set to transfer data from the external DRAM 54 to the drawing circuit 76 via the ChB control circuit 72b (ST23). Next, the start address of the DL buffer BUF'of the external DRAM 54 in which the rewrite list DL'is stored is set in the predetermined data transfer register RGij (ST24).

Further, for this rewrite list DL', the total transfer size is set in the predetermined data transfer register RGij (ST25). As described above, the total amount of data in the rewrite list DL'is the same as the total amount of data in the display list DL, and specifically, for example, 256 bytes.

Next, the drawing operation of the drawing circuit 76 is started based on the set value in the predetermined drawing register RGij (ST26). The timings t1, t2, t3, and t4 in FIG. 30A are also the operation timings of step ST26. Then, the operation of the data transfer circuit 60 is started and the process is completed based on the set value in the predetermined data transfer register RGij (ST27). After that, the effect control CPU 63 shifts to the display list generation process (ST7) that is effective in the next operation cycle without being particularly involved in the operation of the data transfer circuit 72 or the drawing circuit.

On the other hand, the drawing circuit 76, which starts the operation at the timing of step ST26, executes the drawing operation based on the rewrite list DL', and generates image data based on the rewrite list DL'in the frame buffers FBa and FBb. In this operation, the drawing circuit 76 exclusively READ-accesses the preload area without READ-accessing the CGROM 55, so that a series of drawing operations can be completed quickly.

Since the processing contents of step PT10 have been described above, returning to FIG. 27 and continuing the explanation, in the embodiment in which the preloader 73 is utilized after the processing of step PT11, the display list DL to be activated in the next cycle is displayed. Created based on the standard method (B) (ST7). For example, in the operation cycle (T1) shown in FIG. 31 (a), the display list DL referred to by the drawing circuit 76 is created in the operation cycle (T1 + δ) which is the next cycle.

Next, the effect control CPU 63 issues the created display list DL to the preloader 73 instead of the drawing circuit 76 (PT11). The specific operation content is as shown in FIG. 29. First, regarding the embodiment (FIG. 22) in which the preloader 73 is not used, when the effect control CPU 63 directly issues the display list DL to the drawing circuit 76 (FIG. 24), the display list DL is directly issued to the drawing circuit 76 (FIG. 24) and via the DMAC circuit 60. Although the case of issuing (FIG. 25) is shown, in FIG. 29, substantially the same operation is shown in FIGS. 29 (b) and 29 (c) except that the issuing destination is the preloader 73. ..

29 (a) is a flowchart illustrating the operation of FIG. 29 (b), which is almost the same as the flowchart of FIG. 24. However, it is set that the data transfer operation is executed from the CPU IF unit 56 via the ChC control circuit 72c and the CPU bus control unit 72d while checking the remaining amount of the FIFO buffer (ST20). In the following description, the ChC control circuit 72c may be abbreviated as "transfer circuit ChC" for convenience.

Next, the total transfer size (for example, 256 bytes adjusted by the standard method (B)) is set to the predetermined data transfer register RGij, and the management counter CN is initially set to 64 (ST21). Next, the data transfer operation via the transfer circuit ChC is set to the start state (ST22), and the preload operation is started based on the set value in the preload register RGij that defines the operation of the preloader 73 (ST23).

As a result, after that, the preloader 73 executes necessary analysis (Analyze) processing for each instruction command written to the transfer port TR_PORT by the effect control CPU 63, and detects an instruction command (TXLOAD) that should be READ-accessed to the CGROM 55. , The texture is preloaded and stored in the preloaded area of the DRAM 54. Further, the rewrite list DL'with the source address of the texture changed is saved in the DL buffer area BUF' of the DRAM 54.

The timings t1, t3, and t5 in FIG. 31A substantially indicate the operation timing of step ST23 in FIG. 29. However, also in this embodiment, if any abnormality occurs in the process of issuing the display list DL, the processes of step ST25 and step ST27 are executed. Specifically, the operations of the data transfer circuit 72 and the preloader 73 are initialized, and the display list DL issuance process (ST20 to ST30) is re-executed to the extent possible. The initialization process of the preloader 73 includes a process of erasing the rewrite list DL'in an unfinished state and a process of clearing a preload area in which preload data is newly stored.

Although the case where the preloader 73 is used and the case where the preloader 73 is not used have been described in detail above, the specific operation content is not particularly limited. FIG. 30B shows an embodiment in which the display list generated by the effect control CPU 63 is issued to the drawing circuit 76 with a delay of one operation cycle δ instead of the generated operation cycle. In the case of such an embodiment, since the drawing circuit 76 can use almost the entire time of one operation cycle (δ), the possibility of frame dropping is reduced.

Further, FIG. 31B shows an embodiment in which the display list generated by the effect control CPU 63 is issued to the preloader 73 with a delay of one operation cycle instead of the generated operation cycle. In this case, since the preloader 73 can execute the pre-doed operation using almost the entire time of one operation cycle (δ), the possibility of frame dropping is reduced in this case as well.

In the description so far, the composite chip 50 is used, but it is not always necessary to integrate the effect control CPU 63 and the VDP circuit 52 into one element. Furthermore, in the above embodiment, the entire effect control is controlled by a single CPU (effect control CPU 63), but the upstream CPU and the downstream effect control CPU 63 cooperate with each other to produce the effect. Control operations may be performed.

32 to 33 are block diagrams showing such an embodiment. As shown in the figure, in this embodiment, the effect control CPU on the upstream side controls the sound effect, the lamp effect, and the motor effect. On the other hand, the CPU circuit 51 on the downstream side controls only the image effect based on the control command CMD'received from the effect control CPU.

When such a configuration is adopted, the CPU circuit 51 does not need to execute the process of step ST12 in FIG. 22 (a) and the process of FIG. 22 (b), and takes a sufficient time to perform a complicated display. A list DL can be generated, and more complicated and advanced image effects such as 3D (Dimension) can be realized. In such a case, the display list becomes large, but in that case, the total amount of data in the display list DL is adjusted to 512 bytes or more by adding a dummy command to N × 256 bytes. ..

Further, since the operation of the CPU circuit 51 on the downstream side is specialized in image effect control, it is possible to confirm that the drawing operation is completed after the display list DL is issued. The lower part of FIG. 24 shows an operation control example in this case. If the drawing operation is not completed even after the time limit is exceeded, the serious abnormality flag ABN is set and the process is completed (ST32). Since the processing of the CPU circuit 51 on the downstream side is only the image effect control, the completion of the drawing operation may be simply waited in an infinite loop.

When such a configuration is adopted, the start condition determination (ST5) in FIG. 22A can be repeated for a predetermined time. Even with this configuration, if the delay in completing the drawing operation is not so long, there is only a problem that the switching between the display area (0) and the display area (1) is delayed. That is, as shown in the operation cycle T1 + 3δ shown in FIG. 34 (a), in one operation cycle in which the display operation is repeated twice, the frame is dropped only in the first half, and the normal frame is displayed in the second half.

This point is the same when using the preloader, and the start condition determination (ST5') in FIG. 27 (a) can be repeated for a predetermined time. Then, if there is a slight delay, as shown in the operation cycle T1 + 3δ shown in FIG. 34 (b), the frame is dropped only in the first half, and a normal frame is displayed in the second half. However, if the completion of the drawing operation is significantly delayed, a complete frame drop will occur as in the operation cycle T1 + 3δ in FIG. 30 (a), and if such a situation continues, the WDT circuit 58 will be used. It will start. This point is the same even when the preloader is not used.

Further, when the control operation of the CPU circuit 51 is specialized for image effect control, in the embodiment in which DMA transfer is adopted, as shown in the lower part of FIG. 26, the drawing operation of the drawing circuit 76 is completed and the data transfer circuit 72 is completed. It is determined that the operation of the DMAC circuit 60 is completed and the operation of the DMAC circuit 60 is completed (ST50'to ST52'). If any of the operations is not completed normally, the operations of the data transfer circuit 72 and the drawing circuit 76 are initialized, and the same processing (ST55'to ST57') as the processing of steps ST53 to ST55 is executed. To. Also in this case, it is preferable to re-execute the DL issuance process a predetermined number of times.

As described above, an example of constructing a horizontally sized index space that completely matches the number of horizontal pixels of each display device as the frame buffers FBa and FBb of the main display device DS1 and the sub display device DS2 has been described. FIG. 35A is a confirmatory illustration of this relationship, in which a drawing area (W × H) on the virtual drawing space and an effective data area (actual drawing area W × H) on the index space are shown. , Both show cases that match the number of horizontal / vertical pixels of the display device.

In such a correspondence, the drawing operation in the virtual drawing space by the display list DL is not necessarily limited to the drawing area (W × H), and therefore, for example, as shown by the left inclined line in the upper part of FIG. 35 (a). By moving the drawing position of the drawn image (W'xH') that exceeds the drawing area (WxH) in time, the actual drawing area WxH shown by the right inclined line at the lower part of FIG. 35 (a). It is possible to appropriately move the contents drawn on the screen vertically / horizontally / diagonally.

Further, in order to execute such an effect, for example, as shown in FIG. 35B, an index space having a horizontal size W larger than the number of horizontal pixels of the display device may be provided. In this case, the drawing area W × H on the virtual drawing space defined by the instruction command L12 (SETDAVF) of the display list DL is larger than the actual drawing area w × h corresponding to the number of horizontal / vertical pixels of the display device. Set. In the lower part of FIG. 35 (b), the actual drawing area w × h is shown by a right inclined line.

The vertical and horizontal dimensions of the actual drawing area w × h are specified as the number of display lines and the number of horizontal pixels of the display device in the process of step SS30 in FIG. 21, and the upper left end point of the actual drawing area w × h is shown in the figure. In the process of step SS36 of 21, the vertical / horizontal display start position is set in a predetermined display register.

On the other hand, the base point address (X, Y) in the index space is set in a predetermined drawing register by the instruction command L11 of the display list. As described above, specifically, the upper left base point address on the index space IDX is defined as (0,0) by the instruction command L11 (SETDAVR) of the environment setting system. Then, if the upper left end point of the actual drawing area w × h is appropriately moved in the steady processing, the drawing content of the actual drawing area W × H shown by the right inclined line at the lower part of FIG. Will move appropriately.

As described with respect to FIG. 21, the VDP registers RGij related to steps SS30 to SS37 are write-protected after the initial setting (second prohibition setting SS39), but are predetermined at the timing of executing the above effect. By writing the release value to the VDP register RGij of, this prohibition setting is released.

By the way, in the above embodiment, the predetermined system control register RGij and the predetermined VDP register RGIj of the initial setting system are uniformly put into a write-protected state by utilizing the type 1 and type 2 prohibition setting registers. It was set (see SS38 and SS39 in FIG. 21) so that the set values for these registers would not be changed due to the influence of noise or the like thereafter. However, it is also preferable to repeat the setting process at predetermined time intervals for the important setting value of the system control register RGij without making such a write-protection setting.

FIG. 36 is a drawing for explaining the processing in such a case, and the setting values to be set in the initial setting processing (SS1 to SS3) are collected in the setting value table SET TABLE stored in the control memory 53 (PROGMROM). ing. Although the description is omitted in steps SS1 to SS3 in FIG. 21, (a) the initial setting process is executed based on the initial value setting table SETTABLE, and (b) the contents of the initial value setting table SETTABLE. The embodiment of FIG. 21 is also substantially the same as the content described below.

In any of the embodiments, the set value table SETTABLE is composed of a plurality of sets (N sets) in which the register address value of the VDP register RGij and the set value for the register RGij are set as one set. Although not particularly limited, the register address value is fixed to 16-bit length and the set value is fixed to 32-bit length, and each has a fixed length, so that the data capacity of the initial value setting table SETTABLE is 6 × N bytes (= 48t). × Nbit) length, VDP register RGij is N pieces.

However, in the embodiment of FIG. 21, the initial value setting table SETTABLE is READ-accessed only once, and all N VDP registers RGij are initialized only once, whereas in the embodiment of FIG. 36, all of them are initialized. The N VDP registers RGij are divided into the N1 VDP register RGij that is initially set only once and the N2 VDP register RGij that is repeatedly initialized every 1/30 second after the first initial setting. It is classified. However, also in the embodiment of FIG. 36, the processes of steps SS5 to SS6 are executed only once after the power is turned on.

Then, in the embodiment of FIG. 36, the set values that are repeatedly initially set include (1) a set value for the DMA transfer operation, (2) a set value for the VRAM, (3) a set value for an interrupt, and (4) a display. The set value related to the circuit 74 and (5) the set value related to the drawing circuit 76 are included.

(1) The set value related to the DMA transfer operation is, for example, a set value that is a precondition for the operating condition specified in step ST41, and is fixed regardless of the difference in the operating condition in FIGS. 25 (c) and 29 (c). It is a basic setting value that is applied to the target. Specifically, (a) a threshold value (for example, 1/2 stage of the whole) of how much the FIFO buffer (N stage) built in the DAMC circuit 60 is released to make a transfer request to the transfer source, ( b) Includes settings such as whether or not to perform a handshake operation with the transfer destination or transfer source (for example, No).

Further, (2) the set value of VRAM includes the refresh cycle of the refresh operation. The built-in VRAM 71 operates in this refresh cycle to prevent spontaneous discharge of stored data. Next, (3) the setting value related to the interrupt is a value that specifies an error type that causes an interrupt request and an output terminal (internal terminal of the built-in CPU) of the interrupt signal. For example, (a) the drawing circuit 76 If it freezes, an abnormal drawing interrupt occurs in the CPU circuit 51 (interrupt enabled state, see FIG. 22 (d)). (B) When the VBLANK of the display device DS1 starts, a VBLANK start interrupt occurs in the CPU circuit 51. It includes set values such as what happens (see FIG. 22 (c)).

In this embodiment, the composite chip 50 in which the CPU circuit 51 and the VDP circuit 52 are integrated is used, but when a separate chip is used, the output terminal from which the VDP circuit 52 outputs an interrupt signal is a CPU circuit. It is connected to the external interrupt input terminal of 51.

In addition, (4) the set values related to the display circuit include (a) the horizontal / vertical start position of each frame buffer (see SS36), (b) the set values related to the horizontal synchronization signal of each display device, and (c) each display device. The set value for the vertical synchronization signal, (d) the set value for the scaler, (e) the set value for the number of horizontal pixels and the number of display lines of each display device (SS30), and the like are included.

(5) The setting value related to the drawing circuit 76 includes the setting value of the freeze time until the drawing abnormality interrupt occurs. This set value is set, for example, as an integral multiple of the period of the vertical synchronization signal. As described in FIG. 22D, if the drawing circuit 76 does not access the VRAM during the freeze period specified here, the drawing circuit 76 is individually reset (ST16b) and the operating parameters for the drawing circuit 76 are set. It is reset (ST16c).

As described above, in this embodiment, the important set values are repeatedly reset at predetermined time intervals, so even if the set values are garbled due to the influence of noise or the like, the abnormality is immediately detected. Will be recovered. Further, in this embodiment, unlike the case of the embodiment of FIG. 21, the type 1 and type 2 prohibition setting registers RGIj are not set to the write-protected state, so that a slightly complicated prohibition release process is not performed. , You can freely execute the rewriting process.

As described above, in the examples so far, when (1a) the operation freeze state of the drawing circuit 76 after a predetermined freeze time has elapsed, or (1b) the drawing circuit 76 detects an irrational instruction command in the display list DL, , A configuration in which a drawing abnormality interrupt occurs from the drawing circuit 76 of the VDP circuit 52 to the CPU circuit 51 has been described (see FIG. 22 (d)). Then, at the time of a drawing abnormality interrupt, a configuration (ST16c to ST16d) is adopted in which the cause of the interruption is determined (ST16a in FIG. 22D) and the processing is executed according to the determination result.

However, according to the experiment of the present inventor, an abnormal drawing interrupt hardly occurs even under harsh operating conditions with a lot of noise. Therefore, in order to reduce the control load, the interrupt cause determination process (ST16a) is not provided, and the process is uniformly shifted to the infinite loop process (see FIG. 27 (b)), or the pattern check circuit CHK (FIG. It is also preferable to make 7 (b) function (see ST17a in FIG. 27 (c)).

In this case, after that, the WDT circuit 58 is activated after a predetermined time, and the entire composite chip 50 is reset, or only the VDP circuit 52 is reset immediately after that (FIG. 7 (b)). reference). When the VDP circuit 52 is reset based on the reset keyword output process (ST17a), after confirming the normal end of the reset operation and rearranging the stack area for storing the return address (ST17b). For example, the process is shifted to step ST4 or ST13.

Further, in this embodiment, since the abnormality determination process (ST5 in FIGS. 22 and 27) is provided to determine the completion of the operation of the drawing circuit 76 every 1/30 second, the control load is substantially reduced. A drawing abnormality interrupt process (FIG. 27 (d)) that does not execute anything may be provided. As shown in FIG. 27 (d), in this configuration, the IRET (Interrupt Return) instruction is immediately executed and the process returns to the main control process at the time of a drawing abnormality interrupt, so that the freeze state of the drawing circuit 76 is continued as it is. become. However, in this embodiment, the number of frame drops is counted by the abnormality flag ER in the process of step ST5 in FIGS. 22 and 27, and the WDT circuit 58 or the pattern check circuit CHK will be activated eventually, so that FIG. 27 The configuration of (d) is substantially the same as the configuration of FIGS. 27 (b) and 27 (c).

Further, in order to further reduce the control load, it is also preferable to set the VDP circuit 52 to the drawing abnormality interrupt prohibition state at the time of initial setting (see step SS3 in FIG. 21). If the default state when the power is turned on is the drawing abnormal interrupt prohibition state, (a) write the predetermined system control register RGij for which the permission / rejection value that defines the permission / prohibition of the abnormal interrupt should be set. The prohibition state is set, or (b) the prohibition value is repeatedly written to the system control register RGij at predetermined time intervals.

At first glance, this configuration seems to be superior to the configurations of FIGS. 27 (b) and 27 (b). However, for all models of this type of gaming machine, (a) drawing error interrupts are uniformly set to the disabled state, and (b) the drawing error interrupt is uniformly set to the permitted state for each model. It is better to select whether to adopt the configuration of FIG. 22 (d) or the configuration of FIGS. 27 (b) to 27 (d) from the viewpoint of generalization of the control program. In the former configuration (a), it is necessary (complexity) to change the initial setting routine (see step SS3 in FIG. 21) for each model.

As a further modification example, it is also preferable to utilize the voice circuit SND built in the composite chip 50. FIG. 37 is a block diagram showing such an embodiment. As is clear when FIG. 37 is compared with FIG. 7, in this embodiment, the voice processor 27 and the voice memory 28 are unnecessary, and the data bus (8 bits) and the address bus (2 bits) of the CPU circuit 51 are unnecessary. No need for external wiring to the audio circuit. Further, since the transmission line of the underflow signal UF does not exist, it is possible to avoid the possibility that the composite chip is erroneously reset abnormally due to the noise superimposed on the UF transmission line.

Further, in this embodiment, the voice data to be stored in the voice memory 28 is stored in the CGROM 53 in response to the elimination of the voice memory 28. FIG. 38D illustrates the stored contents of the CGROM 53, and the CGROM 53 includes sound ROM header information, phrase header information HD, a large number of phrase data PH compressed with a group of voice data, and a voice circuit. A large number of sound commands SCMD, which define the operation of the SND, are fixedly stored.

As shown in the figure, the sound ROM header information is stored from the head address SNDst, and subsequently, the phrase header information HD having a data size HDvl is stored from the head address HDst. Further, the phrase data PH having a data size PHvl is stored from the head address PHst, and the sound command SCMD having a data size SCMDvl is stored from the head address SCMDst.

Here, the sound ROM header information is specifically the start address HDst of the phrase header HD area, the data size HDvl of the phrase header HD area, the start address PHst of the phrase data area PH, and the phrase data area PH. It means the data size PHvl, the head address SCMDst of the sound command area SCM, and the data size SCMDvl of the sound command area SCMD. Then, these information are acquired in the internal circuit of the voice circuit SND when the power is turned on (see step SD4).

Further, the phrase header information HD and the phrase data PH are transferred to the external DRAM 54 at the time of turning on the power to speed up the subsequent READ access (step SD6). As described above, in this embodiment, the voice processor 27 and the voice memory 28 are eliminated to reduce the size and manufacturing cost, and the CGROM 53 is inexpensive and easy to increase in capacity, but has a slow access speed. Overcoming weaknesses.

Based on the above, the initial setting process at the time of turning on the power will be described with reference to FIG. 38 (a). It should be noted that these processes are executed as a part of the process of step SS3 in FIG.

As described with respect to FIG. 7B, when the power is turned on or when the WDT 58 is activated abnormally, the voice circuit SND is hardware reset along the reset path 2 (step SD1). When the effect control CPU 63 detects an abnormality in the voice circuit SND, the voice circuit SND is hardware reset along the reset path 4B or 4C (step SD1). When the effect control CPU 63 functions the pattern check circuit CHK, the audio circuit SND may be hardware reset together with other circuits (72, 73, 74 ...) (Step SD1).

In any of these cases, the effect control CPU 63 next confirms that the reset operation has been completed normally (step SD2), and then first controls the head address SNDst of the sound data area to the system control of the voice circuit SND. It is set in the register RGij (step SD3). Next, by setting a predetermined value in a predetermined system control register, the sound ROM header information HD is stored in the internal circuit. The sound ROM header information HD is the above-mentioned 6 elements (HDst, HDvl, PHst, PHvl, SCMDst, SCMDvl), and is as shown in FIG. 38 (c).

Then, it is confirmed that the processing up to this point has operated normally, and if it cannot be completed normally, the voice circuit is individually reset by the reset path 4B or 4C. However, since normal termination can be confirmed normally, the phrase header information HD and the phrase data PH are subsequently transferred to the external DRAM 54 using the data transfer circuit 72 (step SD6). In the data transfer circuit 72, the head address BGN of the transfer destination, the head address HDst of the transfer source, the total amount of transfer data HDvl + FDvl, and the like are appropriately designated.

Next, the phrase header information HD and the phrase data PH exist in the external DRAM 54 instead of the CGROM 55, which is set in the predetermined system control register RGij (step SD7), and then transferred to the external DRAM 54. The data start address BGN (sound RAM start address) is set in a predetermined system control register (step SD8). After that, by completing the other initial setting processing (step SD9), the voice control operation becomes possible.

As described above, the sound ROM header information, that is, the six pieces of information (HDst, HDvl, PHst, PHvl, SCMDst, SCMDv) are stored in the internal circuit of the audio circuit SND (step SD4), and then thereafter. , The effect control CPU 63 can instruct necessary information such as phrase data as a relative value with the sound RAM start address BGN, and the voice circuit SND receiving this instruction converts the relative address value into an absolute address value. Then, the necessary voice processing will be executed. Since audio data such as phrase data is READ-accessed not from the CGROM 55 but from the external DRAM 54, even complicated and advanced audio effects can be smoothly realized.

Although various examples have been described in detail above, the present invention is not limited to the ball game machine, the spinning machine, and the like, and the specific description content is not limited to the present invention. In particular, regarding the backlight unit BL and the liquid crystal display unit MONI, the circuit configuration and operation timing of the power supply control circuit (FIG. 6) and the corresponding control processing in FIG. 21 are merely examples. The invention is not limited and can be changed as appropriate.

For example, in the embodiment, the control signals PS1 and PS2 are used, but when the driver DVL having the BL_EN terminal and the PWM terminal is used as the backlight unit BL, the control signal PS1 is not particularly required. Further, since the control signals STBY and PWM are used, the control signal PS2 can also be omitted. When the control signals PS1 and PS2 are omitted, the power supply voltages 12V and 5V are supplied to the backlight unit BL and the liquid crystal display unit MONI from the time the power is turned on.

However, in order to respond to the liquid crystal display MONI of the specification that requires the transmission of a significant image signal quickly (for example, within 20 mS) after the power is turned on, the control signal PS2 is used to delay the power supply start timing of the power supply voltage 5V. Is preferable. FIG. 47 is a time chart illustrating such an embodiment, and while omitting the control signal PS1, the liquid crystal display unit synchronizes the output from the display circuit 74 with the timing T4 at which the LVDS circuit 80 starts to output. An embodiment of starting power supply of a power supply voltage of 5 V to MONI is shown. Also in this case, for example, if the backlight unit BL is turned on with a further delay of 300 mS from the timing T4 by using a timer interrupt, an unnatural image is displayed without clearing the frame buffers FBa and FBb to zero. There is no risk of it.

Further, in the examples up to this point, a considerable standby time (> 1000 + 300 mS) is provided until the backlight is turned on, but the standby time of 1000 mS is eliminated and the output from the display circuit 74 is output by the LVDS circuit 80. It is also preferable to make the output start timing as early as possible. For example, as shown in FIG. 48, the operation of the display circuit 74 and the LVDS circuit 80 (LVDS1 / LVDS2) is started in the step SS4 (following the operation of the step SP45 for making the Dual Link setting of the LVDS circuit and other settings). It is also preferable to execute the process of SS4a + SS4b). As described above, the execution order of steps SS4a and SS4b is arbitrary.

In this case, since the process of step SS4 is executed without executing the process of step SS3, a meaningless image signal is transmitted, but as long as the backlight unit BL is turned off, it is particularly difficult. The problem does not occur. That is, in the state where the backlight unit BL is turned off, as long as the processes of steps SP41 to SP44 are preceded, the processes related to the display operations executed in steps SP4 to SP10 can be replaced in an appropriate order.

In particular, the dual link setting and other setting processing (SP41) for the LVDS circuit 80 (LVDS1 / LVDS2) may be collectively performed at the timing of step SP54 of FIG. 21 instead of the timing of step SP4 of FIG. .. The setting process performed collectively includes the setting that the data to be output from the LVDS1 circuit / LVDS2 circuit is the output (ODD / EVEN) of the display circuit 74 for the LVDS circuit 80 having the dual link configuration. Further, it is set in the predetermined display register RGij (DSPACTRL) and the predetermined system control register RGij (SYSDSPLVDS1MD, SYSDSPLVDS2MD) that the operation of the display circuit 74 and the LVDS circuit 80 should be started from the execution timing of this step SP54. May be.

Further, at the register setting timing of step SP54, the fact that the data of the display circuit 74 is output to LVDS is set in the predetermined system control register RGIj (SYSDSPLVDSLNK, SYSDSPLVDS1CFG1, SYSDSPLVDS2CFG1) (see SP4), and then at the timing of step SS4. It is also preferable to configure the display circuit 74 and the LVDS circuit 80 to start operation. Immediately before the timing T4 in FIG. 47, the output operation (SS4) of the LVDS circuit 80 may be started after executing the processes of steps SP42 to SP44 and step SP46.

However, as described above, the processing of steps SP46 to SP47 relating to the external DRAM (DDR) 54 must always precede the processing of step SP8.

Regarding the power-on reset operation, the power-on reset operation shown in FIG. 16 was started based on the information of the vector table VECT secured after the address 0x00000000 of the control memory 53, but is set to the HBTSL terminal = H level. At the same time, it is also preferable to arrange the vector table VECT in the head area of the CGROM 55. 39 (a) and 39 (b) show an address map in such a case, and the address space CS0 of the effect control CPU 63 is secured in a part (head area) of the CGROM 55.

Since the main body of the CGROM 55 is not accessed from the effect control CPU 63 (inaccessible) and is accessed exclusively from the VDP circuit 52, it is not positioned in the address space CSi. As described above, the main body of the CGROM 55 can be configured by a plurality of memory devices. In such a case, the device section of SPA0 to SPA1 is divided by the process of step SP20 in FIG. 18A. By doing so, the optimum READ access suitable for the characteristics of the memory device becomes possible.

In any case, when the HBTSL terminal = H level is set, the memory type of the CGROM55 and the bus width (64/32/16 bit) correspond to the HBTBWD terminal having a length of 2 bits. It needs to be specified in advance based on a fixed input value to the 4-bit length HBTRMSL terminal.

Then, in this embodiment, following the vector table VECT, it is necessary to store the bus parameters for optimizing the READ access from the CGROM 55 in the head area of the CGROM 55. Although it is not essential, it is also preferable to store the obfuscation parameter for decoding the obfuscation when the obfuscation is obfuscated in order to make the illegal analysis of the effect control program difficult.

When such a configuration is adopted, the following operations 1 to 4 are automatically executed without going through the program processing during the reset assert period after the power supply is reset. First, the bus width of the address space CS0 is specified based on the input value to the HBTRMSL terminal, and the memory type is automatically specified based on the input value to the BTBWD terminal, and each is set in the predetermined VDP register RGIj. (Operation 1). The memory type in this case is roughly classified into a memory element that adopts the parallel I / F (Interface) format and a memory element that adopts the sequential I / F format.

Next, the obfuscation parameter stored in the CGROM 55 is loaded, and the information necessary for canceling the obfuscation is automatically set in the internal circuit (operation 2). Further, the bus parameters stored in the CGROM 55 are automatically acquired in the VDP register RGij (operation 3). Note that this operation 3 is an operation corresponding to the program processing of step SP63 in FIG. 19, and is automatically executed by the internal circuit.

Finally, in order to implement the bus parameters set in the operations 1 to 3, the operation corresponding to the program processing of step SP64 in FIG. 19 is automatically executed by the internal circuit (operation 4). Then, when the bus parameter settings are activated, the values of the program counter PC and the stack pointer SP are automatically set based on the information in the vector table, and the execution of the boot program (initial setting program) is started. To.

According to the configuration shown in FIG. 39 (a), the program processing of step SP1 of FIG. 16 (a) becomes unnecessary, and the operations 1 to 4 are automatically executed, so that the program processing load is greatly reduced. .. Then, also in this case, the programs and data after the vector handler Vopt are transferred to an appropriate RAM area based on the operation of the initial setting program Pinit.

The programs and data after the vector handler Vopt do not necessarily have to be stored in the head area of the CGROM 55, and may be stored in the control memory 53, for example (FIG. 39 (b)). Further, the programs and data after the vector handler Vopt do not necessarily have to be transferred to the RAM area, and if they are not transferred, the memory section initialization process (SP8 in FIG. 16) in the initialization setting program becomes unnecessary.

Further, it is not always necessary to match the V blank timing with the transmission end timing of significant image data. That is, it is not necessary to end the transmission of the image data at the timing of the left lower end point (marked with ◯) in the display area shown in FIG. 15 (f). In short, it is sufficient if the specifications of the standby time WTh / WRv and the specifications of the horizontal / vertical synchronization signal HS / Vs required from the display device side are satisfied.

FIG. 41A is a drawing illustrating such an embodiment, and shows, for example, the operation of the display circuit 74A. Also in this embodiment, the frequency F _dot of the dot clock DCK is defined as 108 MHz corresponding to the specifications of the main display device DS1. Further, in order to match the frame rate FR to 1/60 second, it is necessary to set THc × TVl / F _dot = 1/60, and again, as in the case of FIG. 15 (f), the horizontal synchronization cycle. The number THc is 1662 clocks, and the number of lines of vertical synchronization TVl is 1083 lines.

Further, in the illustrated embodiment, the horizontal synchronization signal HS and the vertical synchronization signal VS are output according to the specifications of the display device so that the display device can also be used. In the illustrated example, the pulse width of the horizontal synchronization signal HS is 100 clocks, the horizontal front pouch FPh is designed to be 110 (= 10 + 100) clocks, and the horizontal back pouch BPh is designed to be 172 clocks. The pulse width of the vertical synchronization signal VS is 10 lines, the vertical front pouch FPv is designed to be 20 (= 10 + 10) lines, and the vertical back pouch BPv is designed to be 291 lines.

However, in the embodiment shown in FIGS. 41 (a) and 41 (b), since the output operation is completed before the V blank start timing indicated by ◯, the vertical standby time WTv is set to 49 lines and the horizontal standby time WT is set to 372 clocks. .. Therefore, according to this embodiment, the V blank start timing arrives after 10 lines of time (154 μS) have elapsed after the image update process of one frame is completed, and the image update process is reliable under any operating conditions. (See FIG. 41 (b)).

Such an operation is particularly suitable for a display circuit that operates incidentally in synchronization with another display circuit, for example, a display circuit 74B or a display circuit 74C that accompanies the operation of the display circuit 74A. 41 (c) to 41 (e) are drawings for explaining this point, and show a case where the V blank period T2 in the display circuit 74B is longer than the V blank period T1 in the display circuit 74A (T1). <T2).

In such a case, if the V blank period T1 in the display circuit 74A is attached to the display circuit 74A and operated, the V blank is started before the output of the image data in the display circuit 74B is completed, and the image is displayed. There is a possibility that defects or unnatural display operations may occur (FIG. 41 (d)). On the other hand, if the display circuit 74B is operated independently, the operation timing of the drawing circuit synchronized with the operation of the display circuit 74A cannot be matched.

Therefore, when the V blank period T2 of the display circuit 74B accompanying the operation of the display circuit 74A is longer than the V blank period T1 of the display circuit 74A, the display device is similar to the case of FIGS. 41 (a) and 41 (b). In B, the waiting time (vertical blank period) may be set short so that a sufficient margin time is generated after the image data is output. In this case, unless the standby time is set extremely short, the display operation can be realized without any problem in a normal liquid crystal display device.

For example, even when the V blank cycle T3 of the display circuit 74B accompanying the operation of the display circuit 74A is shorter than the V blank cycle T1 of the display circuit 74A, an extra waiting period occurs after the V blank cycle T3. As long as the waiting time as a whole is not extremely long, the display operation can be realized without any problem.

Although the embodiments of the present invention have been described in detail above, the specific description content does not limit the present invention. For example, in the embodiment, the dual link transmission line (a pair of LVDS transmission lines) has been described exclusively, but in order to simplify the equipment configuration, it is also preferable to adopt a single link transmission line (single LVDS transmission line). Is.

In the case of a single link transmission line, if the frequency of the dot clock DCK is 108 MHz, the frequency of the LVDS clock CLK is also 108 MHz. Also in this case, it is preferable that the dot clock DCK and the LVDS clock CLK are generated by using the oscillator OSC2 as a common supply source and in the same generation process.

Further, unlike the above embodiment, the supply source of the system clock of the VDP circuit 52 and the CPU operating clock of the CPU circuit 51 is shared by a single oscillator OSC2 in order to simplify the circuit configuration. Is suitable. Then, if a configuration is adopted in which the multiplication ratio of the PLL circuit is commonly set based on the set value of the common setting terminal (3-bit PLLMD terminal), the frequency setting process becomes unnecessary and it is more effective.

In this case, although it is somewhat contrary to the demand for speeding up the CPU operating clock, it is preferable to adopt the system clock having the highest frequency allowed by the internal circuit of the VDP circuit 52 and to use the CPU operating clock having the same frequency. ..

For example, when the oscillation frequency of the oscillator OSC2 is 40 MHz, the system clock and the CPU operating clock are commonly set to 200 MHz (= 40 MHz × 5) by setting the set value to the setting terminal (3 bit PLLMD terminal) to 5. can. According to this configuration, the oscillator OSC1 is not required, the circuit configuration can be simplified, and the setting process for the VDP register, which is rather complicated, is not required. There is also an advantage that the operation cycles of the VDP circuit 52 and the CPU circuit 51 match.

Finally, I will summarize the video production. As described above, in this embodiment, most of the variable effects are realized by using moving images instead of still images. In addition, during the variable effect, a plurality of moving images are operating in parallel except for special cases such as a blackout notice.
<Initial processing>

In this embodiment, in order to execute the moving image effect, an AAC area and a page area are secured in the initial process after the power is turned on (SS1 in FIG. 21), and one or more specified by the index number in the page area. Index space is secured.

Specifically, one or a plurality of page areas having an integer N times the basic size of a unit space of 4096 bits × 128 lines are secured, and a unique index number is assigned to each page area (SS2 in FIG. 21). In this embodiment, since one pixel is represented by 32 bits (ARGB8888), the unit space of the page area is 128 pixels × 128 lines.

As explained earlier, the index space in the page area can be opened or added as needed, so a new index space can be created in the page area when variable production is required. Is also good.

By the way, in this embodiment, the AAC area secured by the initial processing is used as a decoding area for still images and I-stream moving images. In this case, if you specify the size of the texture (one frame of video or still image) after expansion with the load command TXLOAD that specifies the memory read of the image material (texture), the start address of the decode area and the horizontal size are automatically set. It is secured in the AAC area.
<Playback of IP stream video during steady operation>

After the above initial processing, one or more moving image effects are executed at appropriate timings. Here, the following commands CM1 to CM5 are required as instruction commands to the drawing circuit in the display list DL instructing the reproduction of the IP stream moving image.

FIG. 43A is a diagram showing a main part of the display list DL, and is a reprint of the instruction command sequence L16 of FIG. 23. Hereinafter, an embodiment in which a page area is used as the decoding area will be described, but an arbitrary area can also be used. In this case, the page area may be read as an arbitrary area. However, in the index space of the page area, any horizontal size × vertical size is 2048 lines, which causes waste in the vertical direction.
(1) Texture command SETINDEX (CM1)

First, the texture command SETINDEX (CM1) specifies whether to use an arbitrary area or a page area as the decoding area. However, in the case of an IP stream video, the index space i of the page area is used in the embodiment. do. More specifically, the texture command SETINDEX with necessary operation parameters is described in the display list DL, "page area" and "texture" are selected, and the index number i that specifies the index space to be used is specified. Is specified.

When using an arbitrary area, use the texture command SETINDEX to select "arbitrary area" and "texture", and specify the index number i that specifies the index space of the arbitrary area.
(2) Load command TXLOAD (CM2)

Next, the load command TXLOAD (CM2), which specifies the memory read of the material, specifies that the required texture (unit frame constituting the moving image) is loaded from the CGROM. Specifically, the load command TXLOAD to which the necessary operation parameters are added is described in the display list DL. Then, in the VDP circuit 52, the designated texture is loaded from the predetermined area of the CGROM, and the decoded data obtained by decoding this is expanded in the index space i of the page area.

The operation parameters added to the load command TXLOAD include (1) distinction between decoding the texture (unit frame that composes the moving image) as the first frame or as the continuous frame, and (2) after expanding the texture. It includes the horizontal size, (3) the vertical size after the texture is expanded, and (4) the source address of the texture (the start address of the CGROM in which the texture is stored).
(3) Basic information set command SETTXATR (CM3)

Next, the basic information set command SETTXATR (CM3) to which the necessary operation parameters are added is described in the display list DL, and the color mode of the texture is ARGB8888 mode (1 pixel is 32 bits long). Set the basic information of.

Also, set the necessary information about the blending process between pixels. The blending process means a mixing operation of an RGB value that defines the color of each pixel and an α value that defines transparency and the like with pixels that have already been drawn in a frame buffer or the like. In this embodiment, since a plurality of moving images are always operating in parallel during the variable effect, an α-blending operation related to transparency and the like is required.
(4) Pixel-to-pixel blend calculation system command (CM4)

Therefore, the command (CM4) of the inter-pixel blend calculation system to which the necessary operation parameters are added is described in the display list DL, and the α blend calculation formula and others are specified by the necessary operation parameters.
(5) Sprite command PRITE (CM5)

Next, in order to paste the texture expanded in the index space i to the appropriate place in the virtual drawing space (see FIG. 12 (c)), the sprite command SPRITE (CM5) with the necessary operation parameters added to the display list DL. Describe. In this sprite command SPRITE, the upper left vertex (X0, Y0) and the lower right vertex (X1, Y1) of the virtual drawing space that specifies the paste destination of the texture are specified.

Further, regarding the texture to be pasted in the rectangular area specified by the upper left vertex (X0, Y0) and the lower right vertex (X1, Y1), the UV value in the texture UV coordinate space, that is, (U0, V0) and ( U1, V1) are specified. The texture to be pasted has already been specified by the texture command SETINDEX, so there is no need to specify the texture itself again.

Also, instead of the sprite command SPRITE, the triangular polygon command TRIANGLE can be used to tilt the texture and draw it. However, the triangular polygon command TRIANGLE will be described later with respect to the tilt / rotation notice effect.
<Playback of I-stream video during steady operation>

In the case of an I-stream moving image, it is sufficient to load the texture to be decoded (unit frame constituting the I-stream moving image) in the AAC area as in the case of reproducing a still image. That is, the texture command SETINDEX (CM1) is unnecessary, and the configuration of the display list DL is as follows. Normally, command CM3 and command CM4 are also required, but the description is omitted in order to avoid redundancy in the description.
(1) Load command TXLOAD (CM2)

The load command TXLOAD with the operation parameters added is described in the display list DL, and it is specified that the texture (unit frame constituting the I-stream moving image) is loaded from the predetermined area of the CGROM to the AAC area. Then, the VDP circuit 52 automatically decodes the loaded texture and expands the decoded data into the automatically secured space in the AAC region.
(2) Sprite command SPRITE (CM5)

Subsequently, a sprite command SPRITE to which necessary operation parameters are added in order to paste the texture expanded in the automatically secured space of the AAC area to a suitable place in the virtual drawing space is described in the display list DL. As explained earlier, the sprite command SPRITE specifies the upper left vertex and the lower right vertex of the virtual drawing space that specifies the paste destination of the texture.

Instead of the sprite command SPRITE, the triangular polygon command TRIANGLE can be used to draw the texture in an inclined posture.

If you want to enlarge or reduce the texture, you can write the completion command SETTXSMPLNG before the sprite command SPRITE. If the completion command SETTXSMPLNG specifies the texture sampling method (point sampling / bilinear filtering), the completion process when expanding / reducing the texture is specified.

The enlargement processing and reduction processing are automatically executed based on the upper left vertex and the lower right vertex of the virtual drawing space specified by the sprite command SPRITE. That is, it is automatically enlarged or reduced based on the size of the rectangular space defined by the upper left vertex and the lower right vertex. When point sampling is selected, the enlargement process is simply executed in a mosaic pattern, and the reduction process is performed by thinning out the pixels. On the other hand, when bilinear filtering is selected, the information of the unspecified pixel becomes the weighted average value of the information of the identified surrounding pixels.
<Slight fluctuation effect of reserved image and enlargement / reduction effect>

By the way, in the gaming machine of this embodiment, when the number of winning balls to the symbol start port exceeds four, the variable effect is put on hold, and a hold image (still image sprite, I stream or IP stream moving image) showing the number of holds is displayed. It is displayed on the display device.

In this case, it is preferable in terms of production that the reserved image is slightly changed up, down, left, and right, rotated, and enlarged / reduced so as to suggest the lottery result of whether or not it is a big hit. If such a configuration is adopted, various effects can be produced by simply preparing one still image or moving image, and the amount of CG data can be suppressed.

Rotation of the pending image (still image sprite or stream movie) is executed by the triangular polygon command TRIANGLE. On the other hand, minute fluctuations and enlargement / reduction effects are realized by specifying the pasting position or the pasting area of the reserved image (still image sprite or stream moving image) by the sprite command SPRITE. Then, in the display list at the time of enlargement / reduction, it is necessary to describe the completion command SETTXSMPLNG prior to the sprite command SPRITE.
<Serif notice>

The serif notice effect means a notice effect in which the voice effect of the serif sound is started with a predetermined time delay after the display of the serif character is started. By deliberately delaying the audio production, the impact of the character display displayed in advance can be enhanced.

In this serif moving image effect, a group of serif characters are displayed in order, one character at a time or one unit at a time. In some cases, a character image may be displayed prior to the start of displaying a group of serif characters. Further, it is also preferable to start the output of the serif sound after providing a silent period of a predetermined time after the display of the serif character is started.

Further, the character image may be displayed after the serif characters are displayed. In that case, after the serif characters are displayed, the serif sound is started to be produced with a delay of a predetermined time, and then the character image is displayed. It becomes a flow. In this case, it is preferable that the voice effect corresponding to the serif character performed in advance corresponds to the character image displayed after that. Further, after the execution of the voice effect, the character image may be displayed after a silent period of a predetermined time is provided.

When the dialogue preview effect is executed in the IP stream moving image, at least the following commands are described in the display list DL issued prior to the audio effect.

First, the texture command SETINDEX (CM1) is used to set the load destination of the texture (for example, the constituent frame of the IP stream video) to, for example, the page area.

Next, use the TXLOAD command (CM2) to load the texture (unit frame that composes the moving image) from the CGROM into the page area, set the necessary information related to the α blend calculation (CM3, CM4), and finally in the page area. The loaded texture is pasted into a predetermined rectangular area of the virtual drawing space by the sprite command SPRITE (CM5). Here, it is suitable to change the moving image reproduction position by appropriately moving the rectangular area of the pasting destination.

When the dialogue preview effect is executed in the IP stream video, the load command TXLOAD, the completion command SETTXSMPLNG, and the sprite command SPRITE are used. If there is no enlargement / reduction processing, the completion command SETTXSMPLNG is omitted.
<Notice of darkening>

The darkening notice means an effect in which the entire display screen suddenly changes from the previous display mode during a series of variable effects, and a darkened image appears in which the entire screen or almost the entire screen becomes pitch black. In this advance notice production, after the preceding video effect is finished, a display list DL that displays a darkened image is issued for a predetermined time, and then the subsequent development video effect is started as a development notice of the preceding video. One aspect includes a second aspect in which a darkened image appears as a part of the moving image at the start of the developed moving image effect without using the display list DL for displaying the darkened image.

Further, it may be configured to execute a predetermined effect suggesting the degree of expectation of winning while displaying the blackout image. Furthermore, the darkened image is not limited to an image in which almost the entire display screen is completely dark, and may be an image with reduced visibility that reduces the visibility of the display screen up to that point. Specifically, it is a transparent black image.

FIG. 43B illustrates the configuration of the display list DL that realizes the blackout image of the first aspect. First, the endpoint address on the index space is specified for the frame buffer FBa secured in the arbitrary area (L11). The drawing area of the display device DS1 is defined in the virtual drawing space (L12). Specifically, the coordinates of the upper left base point and the lower right base point of the virtual drawing space are set in the predetermined registers.

Next, the index number of the frame buffer FBa used in the current cycle is toggled and specified (L13). In addition, black is set by the SETFCOLOR command (L14), and the entire drawing area of the display device DS1 is specified to be filled with black by using the rectangular drawing command (RECTANGLE) (L15).

This is exactly the same as the instruction commands L11 to L15 shown in FIG. 23. Normally, the commands of FIG. 43A are listed after that, but in the case of a blackout image, the required number is thereafter. After writing the NOP command, write the EODL command to adjust the total amount of data including the EODL command to an integral multiple of 4 × 64 bytes.

It is also preferable to superimpose one or a plurality of moving images on the blackout image, and in this case, the instruction commands CM1 to CM5 shown in FIG. 43A are additionally described.

In the case of the darkening notice of the second aspect, the video frames that realize each of the preceding video production and the subsequent development video production are the instruction commands CM1 to CM5 shown in FIG. 43 (a). Specified by.
<Zoom UP / DOWN notice>

The zoom notice means an effect in which an appropriate character moves appropriately on the display screen while being zoomed up or down (see FIG. 44 (a)). Such a zoom notice can be realized even with a still image depicting a character, but in this embodiment, since a character that changes facial expressions and has movement throughout the body is used, a moving image is used.

In FIG. 44 (a), the character appearing in the zoom notice is represented by "A" like a still image for convenience, but in reality, the "A" part has facial expressions and movements in the limbs. A person / animal character is drawn.

Continuing the explanation based on the above, for example, in a 30 fps (frames per second) 3-second video, the zoom notice character is zoomed up and then zoomed down. 30 × 3 = 90 video frames FR1 to FR2n It is composed of -1.

Since the display list DL for drawing each of the 90 video frames FRi is configured as shown in FIGS. 23 and 43 (a), the loaded texture (video frame depicting the zoom notice character) is a sprite. It is pasted in place in the virtual drawing space by the command SPRITE. Therefore, the zoom notice character can be moved on the display screen only by appropriately moving the designation of the pasting position. Since the zoom-up / down operation is realized as a moving image, the enlargement / reduction control is unnecessary in the display list.

On the other hand, when the zoom notice character is realized by a single still image, the rectangular space defined by the upper left vertex and the lower right vertex of the virtual drawing space may be appropriately enlarged or reduced by the sprite command SPRITE.
<Inclination / rotation notice>

The tilt / rotation notice means, for example, an effect of appropriately tilting or rotating the original images FR1 to FR2n-1 in an upright state as shown in FIG. 44 (a). In FIG. 44 (b), for example, the N moving image frames FR1 to FRn to be zoomed in are sequentially rotated in the clockwise direction.

In order to realize such tilt / rotation notice, a rectangular image (texture constituting a still image or moving image frame FRi) is divided into triangular polygons, and each triangular polygon is divided into triangular polygons by using the triangular polygon command TRIANGLE (CM5). It is necessary to paste it in the appropriate place in the virtual drawing space in an upright state or in an inclined state.

In the following description, a case where enlargement / reduction is not performed for a rectangular image (still image or moving image frame FRi) will be described for convenience, but enlargement / reduction is also possible by appropriately setting the coordinate position. .. In this case, more diverse effects can be produced without increasing the amount of CG data.

FIG. 45 (c) shows a state in which a rectangular image (still image or moving image frame FRi) composed of horizontal W × vertical H pixels having four vertices is divided into a first polygon and a second polygon. Has been done. Then, in this embodiment, the four vertices are drawn together in an upright state or an inclined state by executing the single triangular polygon command TRIANGLE.

However, in order to realize such an operation, the operation parameters to be added to the triangular polygon command TRIANGLE include the number of vertices (information 1) of the polygon to be drawn by one triangular polygon command, and whether only the shape or the texture is included. Setting (information 2), polygon drawing method of triangular polygon (information 3), XY coordinates of each vertex in the virtual drawing space (information 4), UV value of the texture corresponding to information 4 in the UV coordinate space (information). 5), is included.

In this embodiment, four rectangular vertices are drawn with one triangular polygon command, and a texture (video frame) is pasted on the four vertices. Therefore, it is specified that the information 1 that specifies the number of vertices = 4 and the texture are included. Information 2 to be used, information 4 which is an XY coordinate value for four vertices, and information 5 which is a UV value are defined.

The drawing methods include (1) triangle fan drawing that sets common vertices for all triangular polygons, and (2) drawing a triangle surrounded by the final drawing side and the specified vertices. You can select between drawing a triangle strip and drawing a triangle list (3) drawing a triangle polygon independently.

As shown in FIG. 45 (c), in the triangle strip drawing method, vertices 0 → vertices 1 → vertices 3 are drawn in this order, followed by vertices 3 → vertices 1 → vertices 2. On the other hand, in the triangle fan drawing method, the vertex 1 of the common vertex is selected and drawn in the order of vertex 1 → vertex 3 → vertex 0, and then drawn in the order of vertex 1 → vertex 2 → vertex 3. ..

However, since the rectangular image in question here is not a three-dimensional 3D image but a two-dimensional 2D image, the culling process for erasing unnecessary parts does not matter, and no matter which one is selected. Although there is no big difference, in this embodiment, the triangle strip drawing is selected. Although the term "rectangular image" is used in the present specification, it is needless to say that the image is rectangular including a transparent portion and the outline of the image is not always rectangular.

Based on the above, the operation of the effect control CPU 63 for calculating the operation parameters of the triangular polygon command TRIANGLE will be described with reference to FIG. 45 (a). First, the four vertices when the center of the rectangular image composed of horizontal W × vertical H pixels is arranged at the origin of the virtual drawing space are specified (ST61).

As shown in FIG. 12 (c), in the virtual drawing space, the X coordinate is positive in the right direction from the origin, and the Y coordinate is positive in the downward direction from the origin. Therefore, the coordinates (x, y) of the four vertices are positive. , Coordinate 0 (-W / 2, -H / 2), Coordinate 1 (W / 2, -H / 2), Coordinate 2 (W / 2, H / 2), and Coordinate 3 (-W / 2). , H / 2).

Next, the four vertices after rotating the rectangular image at the origin position by the rotation angle θ in the clockwise direction are calculated by the matrix calculation using the rotation matrix of FIG. 45 (b) (ST62). Since the clockwise direction in the rotation matrix is the counterclockwise direction in the virtual drawing space, the rotation angle is actually −θ. This rotation angle is always the rotation angle from the texture in the upright state regardless of the progress of the moving image. That is, even when the texture is rotated at a constant speed at a rotation angle θ1, the rotation angle is not a constant value θ1, but is, for example, θ1 → 2 * θ1 → 3 * θ1 → 4 * θ1 → 5 * θ1 ... It is necessary to increase it sequentially.

Next, the four vertices (X, Y) calculated in the process of step ST62 are moved to an arbitrary destination (ST63). Specifically, if the coordinate value of the destination of the movement of the center point of the rectangular image is (X0, Y0), the operations of X = X + X0 and Y = Y + Y0 are executed for each of the four vertices, and the four after rotation are executed. Determine the coordinates of the vertices.

Finally, the operation parameter (4) of the triangular polygon command TRIANGLE is added, and correspondingly, the operation parameter (5) which is the coordinate value of the UV coordinate system of four vertices for the rectangular image (texture) in the upright state. ) Is added. The same applies to the information (1) to (4).

The operation parameter (4), which is the XY coordinates of each vertex on the virtual drawing space, changes appropriately according to the progress of the moving image, and the display content of the rectangular image (texture) also changes. Since the vertical and horizontal dimensions of the texture in the upright state do not change, the operation parameter (4) is always the same.

In this embodiment, the above calculation is executed every time the display of the tilt / rotation notice effect is issued. This point is a little complicated for the effect control CPU 63, and it is conceivable to specify only the rotation angle and the arrangement position of the texture in the VDP circuit 52.

However, if such a configuration is adopted, it becomes necessary to perform a rotation matrix calculation in the VDP circuit 52, and the calculation load increases. Therefore, in order to reduce the calculation load of the VDP circuit 52, which requires other complicated arithmetic calculations, in this embodiment, the effect control CPU 63 calculates the coordinate position.

However, in order for the effect control CPU 63 to execute the matrix calculation, it is necessary not only to arrange the trigonometric function calculation routine (trigonometric function library) in the memory 53, but also to require a certain amount of processing time. It is preferable to provide a device for speeding up the processing.

FIG. 45D is an example in which the calculation load is reduced, and the distance (radius r) from the center point of the rectangular image to each vertex and the reference angle α of the texture 4 vertices when placed at the origin position (FIG. 45). 45 (e)) and an embodiment of performing the necessary calculation based on.

First, the radius r of the four texture vertices and the reference angle α when the center of the rectangular image composed of horizontal W × vertical H pixels is placed at the origin of the virtual drawing space are specified (ST71).

Next, the coordinate values of the four vertices when rotated in the counterclockwise direction by the rotation angle θ are calculated based on the conversion formula of FIG. 45 (f) (ST72). The calculation process of the conversion formula in FIG. 45 (f) is shown in FIG. 46.

Next, if the coordinate values of the destinations of the four vertices (X, Y) calculated in the process of step ST72 are (X0, Y0), the operations of X = X + X0 and Y = Y + Y0 are executed for each of the four vertices. Then, the coordinates of the four vertices after rotation are fixed (ST73).

Finally, the operation parameters (1) to (5) are added to complete the triangular polygon command TRIANGLE, which is additionally described in the display list DL (ST74).

By the way, in FIGS. 45 to 46, a vertically long rectangular image (texture) is illustrated in an upright state, but if the texture is formed into a square, the root symbol SQR is used and H = W = r * SQR ( 2), and the conversion formula of FIG. 45 (f) is simplified. Further, since there is a relationship of Cos (θ) = Sin (90 + θ), the conversion formula of FIG. 45 (f) can be expressed only by the radius r, the angle of rotation θ, and the Sin function value.

Therefore, it is preferable to prepare a SIN table Angle Table (see FIG. 46 (c)) for storing each Sin function value for the rotation angle −180 degrees to 0 degrees to 180 degrees. In this case, it is preferable. , It is not necessary to arrange the trigonometric function calculation routine in the memory 53, and the processing speed of the trigonometric function calculation can be increased.

GM gaming machine DS1, DS2 display device 52 image generation means 51 image control means DL drawing list (display list)
76 Drawing circuit 74 Display circuit MONI display drive circuit (liquid crystal display)
LCD display screen (display panel)
BL lighting circuit (backlight part)

Claims (10)

An image control means that issues a drawing list that specifies the display screen of the display device, a drawing circuit that generates image data based on the drawing list in a predetermined storage area, and a display that reads out and outputs image data in the storage area. A gaming machine having an image generation means provided with a circuit.
The display device includes a display drive circuit (MONI) that drives a group of display elements constituting the display screen, and a lighting circuit (BL) that illuminates the display screen, based on image data received from the image generation means. , Consists of,
The image control means is a gaming machine characterized in that it controls to supply a power supply voltage of the display drive circuit (MONI) after a predetermined standby time after the power is turned on. During the waiting time, the image control means relates to an internal register that defines the operation of the image generation means.
The gaming machine according to claim 1, wherein the endian setting when accessing the internal register and the setting process (SP40) for setting the data bus width are executed. The first aspect of the present invention, wherein the image control means executes a predetermined division process (SP5) in order to divide the address space when the built-in CPU accesses the memory space into a plurality of areas during the standby time. Game machine. The gaming machine according to claim 3, wherein the built-in CPU is configured to output different chip select signals when accessing any of a plurality of divided address spaces. During the waiting time, the image control means
The gaming machine according to claim 4, wherein a signal matching process (SP5) for matching the operation timing of the chip select signal is executed according to the characteristics of the memory elements constituting each of the plurality of divided address spaces. During the waiting time, the image control means
The gaming machine according to any one of claims 1 to 5, wherein the frequency processing (SP42 to SP43) that defines the frequency of the display clock that defines the operation of the display circuit is executed. The gaming machine according to any one of claims 1 to 6, wherein the image data output by the display circuit is configured to be transmitted to the display device via one or two LVDS circuits. During the waiting time, the image control means
The gaming machine according to claim 7, wherein the image data is set to be transmitted to the display device via one or two LVDS circuits. The gaming machine according to claim 8, wherein the image control means is configured to start transmission of a significant LVDS signal after the standby time. The gaming machine according to claim 9, wherein the image control means starts the lighting operation of the lighting circuit after a lapse of a predetermined time or more after starting transmission of a significant LVDS signal.

Images