JP2022029179A - Detector - Google Patents

Abstract

To provide a detector capable of improving detection sensitivity.SOLUTION: A detector includes a substrate, a plurality of photodiodes including a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer stacked on the substrate and being arranged on the substrate, and a plurality of transistors provided for each of the plurality of photodiodes, and the i-type semiconductor layer and the n-type semiconductor layer are stacked on a top of the p-type semiconductor layer, extend into a region non-overlapping the p-type semiconductor layer and cover at least one transistor.SELECTED DRAWING: Figure 7

Description

The present invention relates to a detection device.

Patent Document 1 describes an optical image pickup apparatus having a light-shielding layer provided with an opening between a microlens and an optical sensor. As such an optical sensor, a PIN type photodiode is known.

U.S. Patent Application Publication No. 2020/0008928

In a detection device using a PIN type photodiode, it is required to improve the detection sensitivity. For example, a PIN-type photodiode can increase the photocurrent by increasing the sensor area. On the other hand, if the sensor area is increased, the parasitic capacitance may increase and the detection sensitivity may decrease. Further, each of the plurality of photodiodes is provided with a circuit including a plurality of transistors and capacitive elements. Therefore, in the case of a configuration in which a plurality of photodiodes are provided on the same plane as the plurality of transistors, it may not be possible to secure an effective light receiving area of the photodiode.

An object of the present invention is to provide a detection device capable of improving the detection sensitivity.

The detection device according to one aspect of the present invention includes a substrate, a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer laminated on the substrate, and a plurality of photodiodes arranged on the substrate, and a plurality of transistors. It has a plurality of transistors provided corresponding to each of the photodiodes, and the i-type semiconductor layer and the n-type semiconductor layer are laminated on the p-type semiconductor layer and the p-type It extends to a region not superimposed on the semiconductor layer and is provided so as to cover at least one of the transistors.

FIG. 1A is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with a lighting device having the detection device according to the embodiment. FIG. 1B is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with a lighting device having the detection device according to the first modification. FIG. 1C is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with a lighting device having the detection device according to the second modification. FIG. 1D is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with a lighting device having the detection device according to the third modification. FIG. 2 is a plan view showing the detection device according to the embodiment. FIG. 3 is a block diagram showing a configuration example of the detection device according to the embodiment. FIG. 4 is a circuit diagram showing a detection element. FIG. 5 is a timing waveform diagram showing an operation example of the detection element. FIG. 6 is a plan view showing a plurality of detection elements. FIG. 7 is a plan view schematically showing one detection element in an enlarged manner. FIG. 8 is a cross-sectional view taken along the line VIII-VIII'of FIG. FIG. 9 is a cross-sectional view showing a configuration example of the optical filter. FIG. 10 is a cross-sectional view showing the detection element according to the modified example 4. FIG. 11 is a cross-sectional view showing the detection element according to the modified example 5. FIG. 12 is a cross-sectional view showing the detection element according to the modified example 6.

An embodiment (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The disclosure is not limited by the content described in the following embodiments. In addition, the components described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the present disclosure are naturally included in the scope of the present disclosure. In addition, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example, and the interpretation of the present disclosure is used. It is not limited. Further, in the present disclosure and each figure, the same elements as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

In the present specification and the scope of patent claims, when expressing an aspect of arranging another structure on one structure, when the term "above" is simply used, the structure shall be used unless otherwise specified. It includes both the case where another structure is placed directly above the structure so as to be in contact with each other and the case where another structure is placed above one structure via another structure.

FIG. 1A is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with a lighting device having the detection device according to the embodiment. FIG. 1B is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with a lighting device having the detection device according to the first modification. FIG. 1C is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with a lighting device having the detection device according to the second modification. FIG. 1D is a cross-sectional view showing a schematic cross-sectional configuration of a detection device with a lighting device having the detection device according to the third modification.

As shown in FIG. 1A, the detection device 120 with a lighting device includes a detection device 1 and a lighting device 121. The detection device 1 includes a sensor substrate 5, an optical filter 7, an adhesive layer 125, and a cover member 122. That is, the sensor substrate 5, the optical filter 7, the adhesive layer 125, and the cover member 122 are laminated in this order in the direction perpendicular to the surface of the sensor substrate 5. As will be described later, the cover member 122 of the detection device 1 can be replaced with the lighting device 121. The adhesive layer 125 may have a structure in which the optical filter 7 and the cover member 122 are adhered to each other, and the adhesive layer 125 may not be present in the region corresponding to the detection region AA. When there is no adhesive layer 125 in the detection region AA, the adhesive layer 125 has a structure in which the cover member 122 and the optical filter 7 are adhered to each other in the region corresponding to the peripheral region GA outside the detection region AA. Further, the adhesive layer 125 provided in the detection region AA may be simply paraphrased as a protective layer of the optical filter 7.

As shown in FIG. 1A, the lighting device 121 uses, for example, a cover member 122 as a light source plate provided at a position corresponding to the detection region AA of the detection device 1, and a plurality of cover members 122 arranged at one end or both ends of the cover member 122. It may be a so-called side light type front light having a light source 123. That is, the cover member 122 has a light irradiation surface 121a that irradiates light, and is a component of the lighting device 121. According to this lighting device 121, the light L1 is irradiated from the light irradiation surface 121a of the cover member 122 toward the finger Fg to be detected. As a light source, for example, a light emitting diode (LED: Light Emitting Diode) that emits light of a predetermined color is used.

Further, as shown in FIG. 1B, the lighting device 121 may have a light source (for example, an LED) provided directly under the detection area AA of the detection device 1, and the lighting device 121 provided with the light source may be used. It also functions as a cover member 122.

Further, the lighting device 121 is not limited to the example of FIG. 1B, and as shown in FIG. 1C, the lighting device 121 may be provided on the side or the upper side of the cover member 122, and the light is applied to the finger Fg from the side or the upper side of the finger Fg. You may irradiate L1.

Further, as shown in FIG. 1D, the lighting device 121 may be a so-called direct type backlight having a light source (for example, an LED) provided in the detection area of the detection device 1.

The light L1 emitted from the illuminating device 121 is reflected as the light L2 by the finger Fg to be detected. The detection device 1 detects unevenness (for example, a fingerprint) on the surface of the finger Fg by detecting the light L2 reflected by the finger Fg. Further, the detection device 1 may detect information about the living body by detecting the light L2 reflected inside the finger Fg in addition to detecting the fingerprint. Information about a living body is, for example, a blood vessel image such as a vein, a pulse, a pulse wave, or the like. The color of the light L1 from the illuminating device 121 may be different depending on the detection target.

The cover member 122 is a member for protecting the sensor substrate 5 and the optical filter 7, and covers the sensor substrate 5 and the optical filter 7. As described above, the lighting device 121 may also have a structure that also serves as the cover member 122. In the structure in which the cover member 122 shown in FIGS. 1C and 1D is separated from the lighting device 121, the cover member 122 is, for example, a glass substrate. The cover member 122 is not limited to the glass substrate, but may be a resin substrate or the like. Further, the cover member 122 may not be provided. In this case, a protective layer such as an insulating film is provided on the surfaces of the sensor substrate 5 and the optical filter 7, and the finger Fg is in contact with the protective layer of the detection device 1.

As shown in FIG. 1B, the detection device 120 with a lighting device may be provided with a display panel in place of the lighting device 121. The display panel may be, for example, an organic EL display panel (OLED: Organic Light Emitting Diode) or an inorganic EL display (micro LED, mini LED). Alternatively, the display panel may be a liquid crystal display panel (LCD: Liquid Crystal Display) using a liquid crystal element as a display element or an electrophoretic display panel (EPD: Electrophoretic Display) using an electrophoretic element as a display element. good. Even in this case, the fingerprint of the finger Fg and information about the living body can be detected based on the light L2 reflected by the display light (light L1) emitted from the display panel.

FIG. 2 is a plan view showing the detection device according to the embodiment. The first direction Dx shown in FIGS. 2 and 2 is one direction in a plane parallel to the substrate 21. The second direction Dy is one direction in a plane parallel to the substrate 21 and is a direction orthogonal to the first direction Dx. The second direction Dy may intersect with the first direction Dx without being orthogonal to each other. The third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy, and is a normal direction of the substrate 21. Further, the "planar view" indicates an arrangement relationship when viewed from the third direction Dz.

As shown in FIG. 2, the detection device 1 includes an array board 2 (board 21), a sensor unit 10, a scanning line drive circuit 15, a signal line selection circuit 16, a detection circuit 48, and a control circuit 102. It has a power supply circuit 103 and.

The control board 101 is electrically connected to the board 21 via the wiring board 110. The wiring board 110 is, for example, a flexible printed circuit board or a rigid board. The wiring board 110 is provided with a detection circuit 48. The control board 101 is provided with a control circuit 102 and a power supply circuit 103. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 102 supplies a control signal to the sensor unit 10, the scanning line drive circuit 15, and the signal line selection circuit 16 to control the operation of the sensor unit 10. The power supply circuit 103 supplies voltage signals such as the power supply potential VDD and the reference potential VCOM (see FIG. 4) to the sensor unit 10, the scanning line drive circuit 15, and the signal line selection circuit 16. In this embodiment, the case where the detection circuit 48 is arranged on the wiring board 110 is illustrated, but the present invention is not limited to this. The detection circuit 48 may be arranged on the substrate 21.

The substrate 21 has a detection region AA and a peripheral region GA. The detection region AA and the peripheral region GA extend in the plane direction parallel to the substrate 21. Each element (detection element 3) of the sensor unit 10 is provided in the detection area AA. The peripheral region GA is a region outside the detection region AA, and is a region in which each element (detection element 3) is not provided. That is, the peripheral region GA is a region between the outer periphery of the detection region AA and the outer edge portion of the substrate 21. A scanning line drive circuit 15 and a signal line selection circuit 16 are provided in the peripheral region GA. The scanning line drive circuit 15 is provided in a region extending along the second direction Dy in the peripheral region GA. The signal line selection circuit 16 is provided in a region extending along the first direction Dx in the peripheral region GA, and is provided between the sensor unit 10 and the detection circuit 48.

The plurality of detection elements 3 of the sensor unit 10 are optical sensors each having a photodiode 30 as a sensor element. The photodiode 30 is a photoelectric conversion element, and outputs an electric signal corresponding to the light emitted to each of them. More specifically, the photodiode 30 is a PIN (Positive Intrinsic Negative) photodiode. Further, the photodiode 30 may be paraphrased as an OPD (Organic Photo Diode). The detection elements 3 are arranged in a matrix in the detection region AA. The photodiode 30 included in the plurality of detection elements 3 performs detection according to a gate drive signal (for example, reset control signal RST, read control signal RD) supplied from the scanning line drive circuit 15. The plurality of photodiodes 30 output an electric signal corresponding to the light emitted to each of them to the signal line selection circuit 16 as a detection signal Vdet. The detection device 1 detects information about the living body based on the detection signals Vdet from the plurality of photodiodes 30.

FIG. 3 is a block diagram showing a configuration example of the detection device according to the embodiment. As shown in FIG. 3, the detection device 1 further includes a detection control circuit 11 and a detection unit 40. A part or all of the functions of the detection control circuit 11 are included in the control circuit 102. Further, in the detection unit 40, a part or all of the functions other than the detection circuit 48 are included in the control circuit 102.

The detection control circuit 11 is a circuit that supplies control signals to the scanning line drive circuit 15, the signal line selection circuit 16, and the detection unit 40, respectively, and controls their operations. The detection control circuit 11 supplies various control signals such as a start signal STV and a clock signal CK to the scanning line drive circuit 15. Further, the detection control circuit 11 supplies various control signals such as the selection signal ASW to the signal line selection circuit 16.

The scanning line drive circuit 15 is a circuit that drives a plurality of scanning lines (read control scanning line GLrd, reset control scanning line GLrst (see FIG. 4)) based on various control signals. The scan line drive circuit 15 selects a plurality of scan lines sequentially or simultaneously, and supplies a gate drive signal (for example, a reset control signal RST, a read control signal RD) to the selected scan lines. As a result, the scanning line drive circuit 15 selects a plurality of photodiodes 30 connected to the scanning line.

The signal line selection circuit 16 is a switch circuit that sequentially or simultaneously selects a plurality of output signal lines SL (see FIG. 4). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected output signal line SL and the detection circuit 48 based on the selection signal ASW supplied from the detection control circuit 11. As a result, the signal line selection circuit 16 outputs the detection signal Vdet of the photodiode 30 to the detection unit 40.

The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a storage circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 to operate in synchronization with each other based on the control signal supplied from the detection control circuit 11.

The detection circuit 48 is, for example, an analog front-end circuit (AFE: Analog Front End). The detection circuit 48 is a signal processing circuit having at least the functions of the detection signal amplification circuit 42 and the A / D conversion circuit 43. The detection signal amplification circuit 42 is a circuit that amplifies the detection signal Vdet, and is, for example, an integrator circuit. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplification circuit 42 into a digital signal.

The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. When the finger Fg comes into contact with or is close to the detection surface, the signal processing circuit 44 can detect the unevenness of the finger Fg or the surface of the palm based on the signal from the detection circuit 48. Further, the signal processing circuit 44 may detect information about the living body based on the signal from the detection circuit 48. Information about the living body is, for example, a blood vessel image of a finger Fg or a palm, a pulse wave, a pulse, a blood oxygen saturation, and the like.

The storage circuit 46 temporarily stores the signal calculated by the signal processing circuit 44. The storage circuit 46 may be, for example, a RAM (Random Access Memory), a register circuit, or the like.

The coordinate extraction circuit 45 is a logic circuit that obtains the detection coordinates of the unevenness of the surface of the finger Fg or the like when the contact or proximity of the finger Fg is detected in the signal processing circuit 44. Further, the coordinate extraction circuit 45 is a logic circuit for obtaining the detection coordinates of the finger Fg and the blood vessel of the palm. The coordinate extraction circuit 45 combines the detection signals Vdet output from each detection element 3 of the sensor unit 10 to generate two-dimensional information indicating the shape of surface irregularities such as a finger Fg. The coordinate extraction circuit 45 may output the detection signal Vdet as the sensor output Vo without calculating the detection coordinates.

Next, a circuit configuration example of the detection device 1 will be described. FIG. 4 is a circuit diagram showing a detection element. As shown in FIG. 4, the detection element 3 includes a photodiode 30, a reset transistor Mrst, a read transistor Mrd, and a source follower transistor Msf. The reset transistor Mrst, the read transistor Mrd, and the source follower transistor Msf are provided corresponding to one photodiode 30. The reset transistor Mrst, the read transistor Mrd, and the source follower transistor Msf are each composed of an n-type TFT (Thin Film Transistor). However, the present invention is not limited to this, and each transistor may be composed of a p-type TFT.

A reference potential VCOM is applied to the anode of the photodiode 30. The cathode of the photodiode 30 is connected to the node N1. The node N1 is connected to the capacitance Cs, one of the source or drain of the reset transistor Mrst, and the gate of the source follower transistor Msf. Further, the node N1 has a parasitic capacitance Cp, an input capacitance Crst, and a Csf. When light is incident on the photodiode 30, the signal (charge) output from the photodiode 30 is stored in the capacitance Cs.

Here, the capacitance Cs is, for example, a capacitance formed between the p-type semiconductor layer 33 and the n-type semiconductor layer 32 (see FIG. 7) of the photodiode 30. The parasitic capacitance Cp is a capacitance added to the capacitance Cs, and is a capacitance formed between various wirings and electrodes provided on the array substrate 2. The input capacitances Crst and Csf are the capacitances of the reset transistor Mrst and the source follower transistor Msf as viewed from the input side, respectively, and more specifically, the capacitances of the gate-source capacitance and the gate-drain capacitance are combined. ..

The gate of the reset transistor Mrst is connected to the reset control scanning line GLrst. A reset potential Vrst is supplied to the other of the source or drain of the reset transistor Mrst. When the reset transistor Mrst is turned on (conducting state) in response to the reset control signal RST, the potential of the node N1 is reset to the reset potential Vrst. The reference potential VCOM has a potential lower than the reset potential Vrst, and the photodiode 30 is reverse-biased.

The source follower transistor Msf is connected between the terminal to which the power supply potential VDD is supplied and the read transistor Mrd (node N2). The gate of the source follower transistor Msf is connected to the node N1. A signal (charge) generated by the photodiode 30 is supplied to the gate of the source follower transistor Msf. As a result, the source follower transistor Msf outputs a voltage signal corresponding to the signal (charge) generated by the photodiode 30 to the read transistor Mrd.

The read transistor Mrd is connected between the source (node N2) of the source follower transistor Msf and the output signal line SL (node N3). The gate of the read transistor Mrd is connected to the read control scanning line GLrd. When the read transistor Mrd is turned on in response to the read control signal RD, a signal output from the source follower transistor Msf, that is, a voltage signal corresponding to the signal (charge) generated by the photodiode 30 is output as a detection signal Vdet. It is output to the signal line SL.

In the example shown in FIG. 4, the reset transistor Mrst and the read transistor Mrd each have a so-called double gate structure in which two transistors are connected in series. However, the present invention is not limited to this, and the reset transistor Mrst and the read transistor Mrd may have a single gate structure or a multi-gate structure in which three or more transistors are connected in series. Further, the circuit of one detection element 3 is not limited to the configuration having three transistors of the reset transistor Mrst, the source follower transistor Msf, and the read transistor Mrd. The detection element 3 may have two or four or more transistors.

FIG. 5 is a timing waveform diagram showing an operation example of the detection element. As shown in FIG. 5, the detection element 3 executes detection in the order of reset period Prst, exposure period Pch, and read period Pdet. The power supply circuit 103 supplies the reference potential VCOM to the anode of the photodiode 30 over the reset period Prst, the exposure period Pch, and the read period Pdet.

At time t0, the control circuit 102 sets the reset control signal RST supplied to the reset control scanning line GLrst to high (high level voltage), and the reset period Prst starts. In the reset period Prst, the reset transistor Mrst is turned on (conducting state), and the potential of the node N1 rises to the potential of the reset potential Vrst.

The control circuit 102 sets the read control signal RD supplied to the read control scanning line GLrd to high (high level voltage) at time t1. As a result, the read transistor Mrd is turned on (conducting state).

The control circuit 102 sets the reset control signal RST to low (low level voltage) at time t2, and the reset period Prst ends. At time t2, the reset transistor Mrst is turned off (non-conducting state). The potential of the node N1 drops to (Vrst-ΔVn1) by accumulating a signal corresponding to the light applied to the photodiode 30. Note that ΔVn1 is a signal (voltage fluctuation) corresponding to the light applied to the photodiode 30.

The potential of the detection signal Vdet output from the output signal line SL at time t3 is (Vrst-Vthsf-Vrdon). Note that Vthsf is the threshold voltage Vthsf of the source follower transistor Msf. Vrdon is a voltage drop due to the on-resistance of the read transistor Mrd.

The control circuit 102 sets the read control signal RD to low (low level voltage) at time t3. As a result, the read transistor Mrd is turned off (non-conducting state), the potential of the node N2 becomes constant, and the potential of the detection signal Vdet output from the output signal line SL also becomes low (low level voltage).

The control circuit 102 sets the read control signal RD to high (high level voltage) at time t4. As a result, the read transistor Mrd is turned on (conducting state), the exposure period Pch ends, and the read period Pdet starts. The potential of the detection signal Vdet2 output to the read period Pdet is reduced by the signal ΔVn1 from the potential of the detection signal Vdet1 acquired at time t3, and becomes (Vrst-Vthsf-Vrdon-ΔVn1).

The detection unit 40 can detect the light emitted to the photodiode 30 based on the signal (ΔVn1) of the difference between the detection signal Vdet1 at the time t3 and the detection signal Vdet2 at the time t5. For example, the signal ΔVn1a shown in FIG. 5 is a signal (voltage fluctuation component) generated when the illuminance is low, and the signal ΔVn1b is a signal (voltage fluctuation component) generated when the illuminance is high. The detection device 1 can detect, for example, unevenness of a fingerprint, a blood vessel image (vein pattern), or the like based on the difference between the signal ΔVn1a and the signal ΔVn1b.

Although FIG. 5 shows an operation example of one detection element 3, the scanning line drive circuit 15 sequentially scans the reset control scanning line GLrst and the read control scanning line GLrd in a time-division manner. It can be detected by the detection element 3 in the entire detection area AA.

Here, assuming that the total capacitance added to the photodiode 30 is the capacitance Cn1, the capacitance Cn1 is expressed by the following equation (1). The capacitance Cs, the parasitic capacitance Cp, the input capacitance Crst, and Csf are various capacitances equivalently connected to the cathode (node N1) of the photodiode 30 described above in FIG.
Cn1 = Cs + Crst + Csf + Cp ... (1)

The signal ΔVn1 is represented by the following equation (2). In addition, ΔQ represents the electric charge accumulated in the exposure period Pch, Ip represents the photocurrent flowing according to the light irradiated to the photodiode 30, and T represents the exposure time (the period from time t3 to time t4). ).
ΔVn1 = ΔQ / Cn1 = (Ip × T) / Cn1 ... (2)

As shown in the equation (2), the signal ΔVn1 can be increased by reducing the capacitance Cn1. That is, it was shown that the detection sensitivity of the detection device 1 can be improved by reducing the capacitance Cn1 even when the same object to be detected is detected under the same detection conditions.

Next, the planar configuration and the cross-sectional configuration of the detection element 3 will be described. FIG. 6 is a plan view showing a plurality of detection elements. In FIG. 6, in order to make the drawing easier to see, the region overlapping the i-type semiconductor layer 31 and the n-type semiconductor layer 32 of the photodiode 30 is shown with diagonal lines. Further, FIG. 6 schematically shows the configuration of each transistor.

As shown in FIG. 6, the photodiode 30 includes an i-type semiconductor layer 31, an n-type semiconductor layer 32, and a p-type semiconductor layer 33, respectively. The reset transistor Mrst, the read transistor Mrd, and the source follower transistor Msf are provided adjacent to the p-type semiconductor layer 33 of the photodiode 30 and the first direction Dx.

The i-type semiconductor layer 31 and the n-type semiconductor layer 32 have a substantially rectangular shape in a plan view and are arranged in a matrix shape. In the adjacent photodiode 30, the i-type semiconductor layer 31 and the n-type semiconductor layer 32 are separated by slits SPa and SPb. The i-type semiconductor layer 31 and the n-type semiconductor layer 32 are laminated on the p-type semiconductor layer 33 and extend to a region not overlapped with the p-type semiconductor layer 33, and at least one transistor (for example, a read transistor Mr. And the source follower transistor Msf) are covered. Further, the i-type semiconductor layer 31 and the n-type semiconductor layer 32 are provided with a cutout portion NT in a region overlapping with a part of the reset transistor Mrst.

The i-type semiconductor layer 31 and the n-type semiconductor layer 32 further include two scanning lines (read control scanning line GLrd, reset control scanning line GLrst) and four signal lines (output signal line SL, power supply signal line SLsf, reset). It is provided so as to cover the signal line SLrst and the reference signal line SLcom).

The read control scanning line GLrd and the reset control scanning line GLrst extend in the first direction Dx and are arranged side by side in the second direction Dy. The output signal line SL, the power supply signal line SLsf, the reset signal line SLrst, and the reference signal line SLcom extend in the second direction Dy and are arranged side by side in the first direction Dx.

The outer edges of the i-type semiconductor layer 31 and the n-type semiconductor layer 32 have two scanning lines (read control scanning line GLrd and reset control scanning line GLrst) and two signal lines (for example, power supply signal line SLsf and reference signal line SLcom). ) And. One detection element 3 is defined by a region that overlaps with the i-type semiconductor layer 31 and the n-type semiconductor layer 32.

FIG. 7 is a plan view schematically showing one detection element in an enlarged manner. In FIG. 7, in order to make the drawings easier to see, the i-type semiconductor layer 31 and the n-type semiconductor layer 32 of the photodiode 30 are shown by a two-dot chain line, and the p-type semiconductor layer 33 is shown by a dotted line.

As shown in FIG. 7, the p-type semiconductor layer 33 of the photodiode 30 is provided in a region surrounded by the read control scanning line GLrd, the reset control scanning line GLrst, the reset signal line SLrst, and the reference signal line SLcom. The i-type semiconductor layer 31 and the n-type semiconductor layer 32 have a larger area than the p-type semiconductor layer 33, and are provided so as to cover the p-type semiconductor layer 33, the read transistor Mrd, and the source follower transistor Msf.

The i-type semiconductor layer 31 and the n-type semiconductor layer 32 are, for example, amorphous silicon (a-Si). The p-type semiconductor layer 33 is, for example, polysilicon (p—Si). The material of the semiconductor layer is not limited to this, and may be polysilicon, microcrystalline silicon, or the like.

In the n-type semiconductor layer 32, impurities are doped in a—Si to form an n + region. In the p-type semiconductor layer 33, impurities are doped in p—Si to form a p + region. The i-type semiconductor layer 31 is, for example, a non-doped intrinsic semiconductor and has lower conductivity than the n-type semiconductor layer 32 and the p-type semiconductor layer 33.

The p-type semiconductor layer 33 is connected to the reference signal line SLcom via the contact hole H11. As a result, the reference potential VCOM is supplied to the p-type semiconductor layer 33 of the photodiode 30 via the reference signal line SLcom.

The detection element 3 further has an upper conductive layer 34 and a lower conductive layer 35. The lower conductive layer 35 is provided in a region overlapping the p-type semiconductor layer 33 of the photodiode 30. The lower conductive layer 35 is connected to the reference signal line SLcom via the contact hole H12. As a result, the lower conductive layer 35 is supplied with the same reference potential VCOM as the p-type semiconductor layer 33, and the parasitic capacitance between the lower conductive layer 35 and the p-type semiconductor layer 33 can be suppressed.

The upper conductive layer 34 is provided on the photodiode 30 and is electrically connected to the n-type semiconductor layer 32 via the contact hole H1. The upper conductive layer 34 is connected to the connection wiring 34a. The connection wiring 34a is drawn out to a region not overlapped with the p-type semiconductor layer 33 and is connected to the connection wiring SLcn1 via the contact hole H2. The cutout portion NT provided in the i-type semiconductor layer 31 and the n-type semiconductor layer 32 is formed in at least a region overlapping with the contact hole H2. In other words, the i-type semiconductor layer 31 and the n-type semiconductor layer 32 are provided in a non-superimposed manner with a part of the reset transistor Mrst. The upper conductive layer 34 is electrically connected to the reset transistor Mrst via the connection wiring 34a and the notch NT. As a result, the cathode (n-type semiconductor layer 32) of the photodiode 30 is electrically connected to the reset transistor Mrst and the source follower transistor Msf via the connection wiring SLcn1.

The reset transistor Mrst, the source follower transistor Msf, and the read transistor Mrd are provided between the power supply signal line SLsf and the output signal line SL, and are arranged in the second direction Dy. Further, in the first direction Dx, two signal lines (output signal line SL and reset signal line SLrst) are provided between the three transistors and the p-type semiconductor layer 33.

The reset transistor Mrst has a semiconductor layer 61, a source electrode 62, a drain electrode 63, and a gate electrode 64. One end of the semiconductor layer 61 is connected to the reset signal line SLrst. The other end of the semiconductor layer 61 is connected to the connection wiring SLcn1 via the contact hole H3. The portion of the reset signal line SLrst connected to the semiconductor layer 61 functions as the source electrode 62, and the portion of the connection wiring SLcn1 connected to the semiconductor layer 61 functions as the drain electrode 63. The semiconductor layer 61 intersects the reset control scanning line GLrst. A channel region is formed in a portion of the semiconductor layer 61 that overlaps with the reset control scanning line GLrst, and a portion of the semiconductor layer 61 that overlaps with the semiconductor layer 61 of the reset control scanning line GLrst functions as a gate electrode 64.

The source follower transistor Msf has a semiconductor layer 65, a source electrode 66, a drain electrode 67, and a gate electrode 68. One end of the semiconductor layer 65 is connected to the power supply signal line SLsf via the contact hole H4. The other end of the semiconductor layer 65 is connected to the connection wiring SLcn2. The connection wiring SLcn2 corresponds to the node N2 in the equivalent circuit diagram of FIG. The portion of the power signal line SLsf connected to the semiconductor layer 65 functions as the drain electrode 67, and the portion of the connection wiring SLcn2 connected to the semiconductor layer 65 functions as the source electrode 66.

One end of the gate connection wiring GLsf is connected to the connection wiring SLcn1 via the contact hole. The other end side of the gate connection wiring GLsf is branched into two and provided side by side in the second direction Dy. The semiconductor layer 65 intersects the gate connection wiring GLsf branched into two. The portion of the gate connection wiring GLsf that overlaps with the semiconductor layer 65 functions as the gate electrode 68. As a result, the reset transistor Mrst is electrically connected to the gate of the source follower transistor Msf via the connection wiring SLcn1 and the gate connection wiring GLsf.

The read transistor Mrd has a semiconductor layer 81, a source electrode 82, a drain electrode 83, and a gate electrode 84. One end of the semiconductor layer 81 is connected to the connection wiring SLcn2. The other end of the semiconductor layer 81 is connected to the output signal line SL. In other words, the portion of the connection wiring SLcn2 connected to the semiconductor layer 81 functions as the drain electrode 83, and the portion of the output signal line SL connected to the semiconductor layer 81 functions as the source electrode 82. The two gate electrodes 84 are provided side by side in the second direction Dy and overlap with the semiconductor layer 81. The two gate electrodes 84 are electrically connected to the read control scanning line GLrd via a branch portion extending in the second direction Dy and superimposing on the power supply signal line SLsf. With such a configuration, the source follower transistor Msf and the read transistor Mrd are connected to the output signal line SL.

The planar configuration of the photodiode 30 and each transistor shown in FIG. 7 is merely an example and can be changed as appropriate. For example, the configuration is not limited to a configuration in which a plurality of transistors are arranged side by side in the second direction Dy, and some transistors are provided at different positions such as being arranged next to another transistor in the first direction Dx. You may. Further, the i-type semiconductor layer 31 and the n-type semiconductor layer 32 may not be provided with the cutout portion NT and may be provided so as to be superimposed on a part of the reset transistor Mrst. In this case, the i-type semiconductor layer 31 and the n-type semiconductor layer 32 may have contact holes formed at least in a region overlapping with the contact holes H2.

Next, the cross-sectional configuration of the detection element 3 will be described. FIG. 8 is a cross-sectional view taken along the line VIII-VIII'of FIG. Note that FIG. 8 shows the cross-sectional configuration of the reset transistor Mrst among the three transistors included in the detection element 3, but the cross-sectional configuration of the source follower transistor Msf and the read transistor Mrd is also the same as that of the reset transistor Mrst.

As shown in FIG. 8, the substrate 21 is an insulating substrate, and for example, a glass substrate such as quartz or non-alkali glass, or a resin substrate such as polyimide is used. The gate electrode 64 is provided on the substrate 21. The insulating films 22 and 23 are provided on the substrate 21 so as to cover the gate electrode 64. The insulating films 22, 23 and the insulating films 24, 25, 26 are inorganic insulating films, such as silicon oxide (SiO ₂ ) and silicon nitride (SiN).

The semiconductor layer 61 is provided on the insulating film 23. For the semiconductor layer 61, for example, polysilicon is used. However, the semiconductor layer 61 is not limited to this, and may be a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, low temperature polysilicon (LTPS), or the like. The reset transistor Mrst has a bottom gate structure in which the gate electrode 64 is provided on the lower side of the semiconductor layer 61, but a top gate structure in which the gate electrode 64 is provided on the upper side of the semiconductor layer 61 may be used, and the gate electrode 64 is a semiconductor. A dual gate structure provided on the upper side and the lower side of the layer 61 may be used.

The semiconductor layer 61 includes a channel region 61a, high-concentration impurity regions 61b and 61c, and low-concentration impurity regions 61d and 61e. The channel region 61a is, for example, a non-doped intrinsic semiconductor or a low-impurity region, and has lower conductivity than the high-concentration impurity regions 61b and 61c and the low-concentration impurity regions 61d and 61e. The channel region 61a is provided in a region overlapping the gate electrode 64.

The insulating films 24 and 25 are provided on the insulating film 23 so as to cover the semiconductor layer 61. The source electrode 62 and the drain electrode 63 are provided on the insulating film 25. The source electrode 62 is connected to the high-concentration impurity region 61b of the semiconductor layer 61 via the contact hole H5. Further, the drain electrode 63 is connected to the high-concentration impurity region 61c of the semiconductor layer 61 via the contact hole H3. The source electrode 62 and the drain electrode 63 are composed of, for example, a laminated film of TiAlTi or TiAl, which is a laminated structure of titanium and aluminum.

The gate connection wiring GLsf connected to the gate of the source follower transistor Msf is provided in the same layer as the gate electrode 64. The drain electrode 63 (connection wiring SLcn1) is connected to the gate connection wiring GLsf from the insulating film 22 via a contact hole penetrating the insulating film 25.

Next, the cross-sectional configuration of the photodiode 30 will be described. The lower conductive layer 35 is provided on the substrate 21 in the same layer as the gate electrode 64 and the gate connection wiring GLsf. The insulating film 22 and the insulating film 23 are provided on the lower conductive layer 35. The photodiode 30 is provided on the insulating film 23. In other words, the lower conductive layer 35 is provided between the substrate 21 and the p-type semiconductor layer 33. Since the lower conductive layer 35 is formed of the same material as the gate electrode 64, it functions as a light-shielding layer, and the lower conductive layer 35 can suppress the intrusion of light from the substrate 21 side into the photodiode 30.

The i-type semiconductor layer 31 is provided between the p-type semiconductor layer 33 and the n-type semiconductor layer 32 in the direction perpendicular to the surface of the substrate 21 (third direction Dz). In the present embodiment, the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32 are laminated in this order on the insulating film 23.

Specifically, the p-type semiconductor layer 33 is provided on the insulating film 23 in the same layer as the semiconductor layer 61. The insulating films 24, 25, and 26 are provided so as to cover the p-type semiconductor layer 33. The insulating film 24 and the insulating film 25 are provided with a contact hole H13 at a position where they overlap with the p-type semiconductor layer 33. The insulating film 26 is provided on the insulating film 25 so as to cover a plurality of transistors including the reset transistor Mrst. The insulating film 26 covers the side surfaces of the insulating film 24 and the insulating film 25 constituting the inner wall of the contact hole H13. Further, the insulating film 26 is provided with a contact hole H14 at a position overlapping the p-type semiconductor layer 33.

The i-type semiconductor layer 31 is provided on the insulating film 26 and is connected to the p-type semiconductor layer 33 from the insulating film 24 via a contact hole H14 penetrating the insulating film 26. The n-type semiconductor layer 32 is provided on the i-type semiconductor layer 31.

The i-type semiconductor layer 31 and the n-type semiconductor layer 32 extend on the insulating film 26 to a region not superimposed on the p-type semiconductor layer 33. Further, the reference signal line SLcom is provided on the insulating film 25 and is connected to the p-type semiconductor layer 33 via the contact hole H11. The i-type semiconductor layer 31 and the n-type semiconductor layer 32 are provided so as to cover the reference signal line SLcom. In other words, the p-type semiconductor layer 33, the insulating films 24 and 25, the reference signal line SLcom, the insulating film 26, the i-type semiconductor layer 31 and the n-type semiconductor layer 32 are laminated in this order at the portion where the reference signal line SLcom is provided. To.

A notch NT is provided in a region of the i-type semiconductor layer 31 and the n-type semiconductor layer 32 that overlaps with the reset transistor Mrst. The i-type semiconductor layer 31 and the n-type semiconductor layer 32 that overlap with a part of the reset transistor Mrst (source electrode 62) are a part of the photodiode 30 adjacent to the second direction Dy shown in FIG. The insulating film 26 is provided so as to cover the source follower transistor Msf and the read transistor Mrd (not shown in FIG. 12), and the i-type semiconductor layer 31 and the n-type semiconductor layer 32 cover the source follower transistor Msf and the read transistor Mrd. It is provided on the insulating film 26.

The insulating film 27 is provided on the insulating film 26 so as to cover the photodiode 30. The insulating film 27 is provided in direct contact with the photodiode 30 and the insulating film 26. The insulating film 27 is made of an organic material such as photosensitive acrylic. The insulating film 27 is thicker than the insulating film 26. The insulating film 27 has better step coverage than the inorganic insulating material, and is provided so as to cover the side surfaces of the i-type semiconductor layer 31 and the n-type semiconductor layer 32.

The upper conductive layer 34 is provided on the insulating film 27. The upper conductive layer 34 is a translucent conductive material such as ITO (Indium Tin Oxide). The upper conductive layer 34 is provided following the surface of the insulating film 27, and is connected to the n-type semiconductor layer 32 via the contact hole H1 provided in the insulating film 27. Further, the upper conductive layer 34 is electrically connected to the drain electrode 63 of the reset transistor Mrst and the gate connection wiring GLsf via the contact hole H2 provided in the insulating film 27.

The insulating film 28 is provided on the insulating film 27 so as to cover the upper conductive layer 34. The insulating film 28 is an inorganic insulating film. The insulating film 28 is provided as a protective layer that suppresses the intrusion of moisture into the photodiode 30.

The protective film 29 is provided on the insulating film 28. The protective film 29 is an organic protective film. The protective film 29 is formed so as to flatten the surface of the detection device 1.

In the present embodiment, the p-type semiconductor layer 33 and the lower conductive layer 35 of the photodiode 30 are provided in the same layer as each transistor, so that the manufacturing process can be performed as compared with the case where the photodiode 30 is formed in a layer different from each transistor. Can be simplified.

The cross-sectional configuration of the photodiode 30 shown in FIG. 8 is merely an example. Not limited to this, for example, the photodiode 30 may be provided in a layer different from that of each transistor. Further, the stacking order of the p-type semiconductor layer 33, the i-type semiconductor layer 31 and the n-type semiconductor layer 32 is not limited to FIG. 8, and the n-type semiconductor layer 32, the i-type semiconductor layer 31 and the p-type semiconductor layer 33 are in this order. It may be laminated. In this case, the i-type semiconductor layer 31 and the p-type semiconductor layer 33 extend on the insulating film 26 to a region not superimposed on the n-type semiconductor layer 32, and are provided so as to cover at least one or more transistors.

Next, a configuration example of the optical filter 7 will be described. FIG. 9 is a cross-sectional view showing a configuration example of the optical filter. Note that FIG. 9 schematically shows the photodiode 30 and the protective film 29 that covers the photodiode 30.

The optical filter 7 is an optical element that transmits the component of the light L2 reflected by the object to be detected such as the finger Fg that travels in the third direction Dz toward the photodiode 30 and shields the component that travels in the diagonal direction. Is. The optical filter 7 is also called a collimator aperture or a collimator.

As shown in FIG. 9, the optical filter 7 includes a first light-shielding layer 71, a second light-shielding layer 72, a first translucent resin layer 74, a second translucent resin layer 75, and a lens 78. Has. The optical filter 7 is an external member and is adhered onto the protective film 29 via an adhesive layer 76. In the present embodiment, the adhesive layer 76, the first light-shielding layer 71, the first light-transmitting resin layer 74, the second light-shielding layer 72, the second light-transmitting resin layer 75, and the lens 78 are placed in this order on the protective film 29. It is laminated.

The lens 78 is provided in a region superimposed on the photodiode 30. The lens 78 is a convex lens. The optical axis CL of the lens 78 is provided in a direction parallel to the third direction Dz and intersects with the photodiode 30. The lens 78 is provided in direct contact with the second translucent resin layer 75. Further, in the present embodiment, a light-shielding layer or the like is not provided on the second translucent resin layer 75 between the adjacent lenses 78.

The first light-shielding layer 71 and the second light-shielding layer 72 are provided between the photodiode 30 and the lens 78 in the third direction Dz. Further, the first light-shielding layer 71 is provided with a first opening OP1 in a region superimposed on the photodiode 30. The second light-shielding layer 72 is provided with a second opening OP2 in a region superimposed on the photodiode 30. The first opening OP1 and the second opening OP2 are formed in a region overlapping the optical axis CL.

The first light-shielding layer 71 is made of a metal material such as molybdenum (Mo). As a result, the first light-shielding layer 71 can reflect the components of the light L2 traveling in the oblique direction other than the light L2 transmitted through the first opening OP1.

The second light-shielding layer 72 is formed of, for example, a black-colored resin material. As a result, the second light-shielding layer 72 functions as a light absorption layer that absorbs the components of the light L2 traveling in the oblique direction other than the light L2 transmitted through the second opening OP2. For example, the second light-shielding layer 72 can absorb the light reflected by the first light-shielding layer 71 and the external light incident from between the adjacent lenses 78.

In the present embodiment, the width W3 in the first direction Dx of the lens 78, the width W2 in the first direction Dx of the second opening OP2, and the width W1 in the first direction Dx of the first opening OP1 become smaller in this order. .. Further, the width W1 of the first opening OP1 in the first direction Dx is smaller than the width of the photodiode 30 in the first direction Dx.

Further, the thickness TH2 of the second translucent resin layer 75 shown in FIG. 9 is formed to be thicker than the thickness TH1 of the first translucent resin layer 74. Further, the thickness TH1 of the first translucent resin layer 74 and the thickness TH2 of the second translucent resin layer 75 are thicker than the thickness TH3 of the protective film 29 of the sensor substrate 5.

With such a configuration, among the light L2 reflected by the object to be detected such as the finger Fg, the light L2-1 traveling in the third direction Dz is focused by the lens 78, and the second opening OP2 and the first opening It passes through OP1 and is incident on the photodiode 30. Further, the light L2-2 inclined by the angle θ1 with respect to the third direction Dz also passes through the second aperture OP2 and the first aperture OP1 and is incident on the photodiode 30.

The configuration of the optical filter 7 shown in FIG. 9 is merely an example and can be changed as appropriate. For example, the relationship between the widths W1, W2, W3 and the thicknesses TH1, TH2, TH3 may be appropriately changed according to the required optical characteristics. Further, the optical filter 7 is not limited to the configuration in which the first light-shielding layer 71 and the second light-shielding layer 72 are provided, and may be provided with one layer of the first light-shielding layer 71.

The optical filter 7 may not be provided with the adhesive layer 76 and may be provided in direct contact with the protective film 29.

As described above, the detection device 1 of the present embodiment includes the substrate 21, the p-type semiconductor layer 33, the i-type semiconductor layer 31 and the n-type semiconductor layer 32 laminated on the substrate 21, and is arranged on the substrate 21. It has a plurality of photodiodes 30 and a plurality of transistors (for example, a reset transistor Mrst, a read transistor Mrd, and a source follower transistor Msf) provided corresponding to each of the plurality of photodiodes 30. The i-type semiconductor layer 31 and the n-type semiconductor layer 32 are laminated on the p-type semiconductor layer 33 and extend to a region not superimposed on the p-type semiconductor layer 33, and at least one transistor (for example, a read transistor) is provided. It is provided so as to cover Mrd and the source follower transistor Msf).

According to this, even when the p-type semiconductor layer 33 is formed in the same layer as each transistor, the i-type semiconductor layer 31 and the n-type semiconductor layer 32 are less restricted by each transistor and are arranged. The degree of freedom can be increased. Therefore, the area of the i-type semiconductor layer 31 and the n-type semiconductor layer 32 in a plan view can be made larger than that of the p-type semiconductor layer 33. Therefore, the light receiving area of the photodiode 30 becomes large, and the detection sensitivity can be improved. Further, even when an external optical filter 7 is provided on the photodiode 30, the allowable range of misalignment between the first aperture OP1, the second aperture OP2 and the lens 78 and the photodiode 30 is increased. can do.

Further, in the region of the i-type semiconductor layer 31 and the n-type semiconductor layer 32 that is not superimposed on the p-type semiconductor layer 33, the capacitance Cs formed between the n-type semiconductor layer 32 and the p-type semiconductor layer 33 can be suppressed. .. Therefore, it is possible to suppress an increase in the capacitance Cs as compared with the case where the p-type semiconductor layer 33 is formed in a large area together with the i-type semiconductor layer 31 and the n-type semiconductor layer 32. As a result, since the capacitance Cn1 represented by the above equations (1) and (2) can be suppressed and the signal ΔVn1 can be increased, the detection device 1 can improve the detection sensitivity.

FIG. 10 is a cross-sectional view showing the detection element according to the modified example 4. In the following description, the same components as those described in the above-described embodiment are designated by the same reference numerals, and duplicate description will be omitted.

As shown in FIG. 10, the detection element 3A according to the modified example 4 has a different configuration in which the insulating film 26 has the first inorganic insulating film 26a and the second inorganic insulating film 26b as compared with the above-described embodiment. The first inorganic insulating film 26a is provided on a plurality of transistors including the reset transistor Mrst, the p-type semiconductor layer 33, and the reference signal line SLcom. The second inorganic insulating film 26b is provided on the first inorganic insulating film 26a. The i-type semiconductor layer 31 and the n-type semiconductor layer 32 are provided on the second inorganic insulating film 26b.

With such a configuration, a plurality of insulating films (first inorganic insulating film 26a and second inorganic insulating film 26b) are provided between the i-type semiconductor layer 31 and the n-type semiconductor layer 32 and the reference signal line SLcom. Therefore, in this modification, it is possible to secure the insulation between the i-type semiconductor layer 31 and the n-type semiconductor layer 32 and the reference signal line SLcom. Similarly, a plurality of insulating films (first inorganic insulating film 26a and second inorganic insulating film 26b) are provided between the i-type semiconductor layer 31 and the n-type semiconductor layer 32 and the plurality of transistors. Therefore, in this modification, it is possible to secure the insulation between the i-type semiconductor layer 31 and the n-type semiconductor layer 32 and the plurality of transistors.

FIG. 11 is a cross-sectional view showing the detection element according to the modified example 5. As shown in FIG. 11, the detection element 3B according to the modified example 5 has a different configuration in which the insulating film 26 has the first inorganic insulating film 26a and the organic insulating film 26c as compared with the above-described embodiment and the modified example 4. .. The first inorganic insulating film 26a is provided on a plurality of transistors including the reset transistor Mrst, the p-type semiconductor layer 33, and the reference signal line SLcom. The organic insulating film 26c is provided on the first inorganic insulating film 26a. The i-type semiconductor layer 31 and the n-type semiconductor layer 32 are provided on the organic insulating film 26c.

With such a configuration, an organic insulating film is formed between the i-type semiconductor layer 31 and the n-type semiconductor layer 32 and the reference signal line SLcom, and between the i-type semiconductor layer 31 and the n-type semiconductor layer 32 and the plurality of transistors. 26c is provided. The organic insulating film 26c flattens the irregularities formed by the reference signal line SLcom and a plurality of transistors, and improves the flatness of the i-type semiconductor layer 31 and the n-type semiconductor layer 32 formed on the organic insulating film 26c. Can be made to.

FIG. 12 is a cross-sectional view showing the detection element according to the modified example 6. As shown in FIG. 12, the detection element 3C according to the modified example 6 has a different configuration having the superimposed conductive layer 36 as compared with the above-described embodiment and the modified examples 4 and 5. The superimposed conductive layer 36 is provided on the insulating film 28 and covers the i-type semiconductor layer 31 and the n-type semiconductor layer 32 of the photodiode 30. The protective film 29 is provided on the insulating film 28 so as to cover the superposed conductive layer 36. The superimposed conductive layer 36 is a conductive material having translucency such as ITO. The superimposed conductive layer 36 is electrically connected to the reference signal line SLcom at an arbitrary position, and the same reference potential VCOM as the p-type semiconductor layer 33 is supplied.

In this modification, the capacitance formed between the superposed conductive layer 36 and the n-type semiconductor layer 32 is added to the capacitance Cs formed between the n-type semiconductor layer 32 and the p-type semiconductor layer 33. It may be necessary to adjust the capacitance Cs in relation to the illuminance received by the photodiode 30, and the capacitance for adjustment can be formed by providing the superimposed conductive layer 36. Further, the superimposed conductive layer 36 may be applied to the detection elements 3 and 3A shown in the above-described embodiment and modification 4.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various changes can be made without departing from the spirit of the present invention. Appropriate changes made without departing from the spirit of the present invention naturally belong to the technical scope of the present invention. At least one of the various omissions, substitutions and modifications of the components may be made without departing from the gist of each of the embodiments and modifications described above.

1 Detection device 3, 3A, 3B, 3C Detection element 2 Array board 5 Sensor board 7 Optical filter 10 Sensor part 21 Board 30 Photodiode 31 i-type semiconductor layer 32 n-type semiconductor layer 33 p-type semiconductor layer 34 Upper conductive layer 35 Lower Conductive layer Mrst reset transistor Mrd read transistor Msf source follower transistor GLrd read control scanning line GLrst reset control scanning line SL output signal line SLsf power supply signal line SLrst reset signal line SLcom reference signal line NT notch

Claims (7)

With the board
A plurality of photodiodes including a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer laminated on the substrate, and a plurality of photodiodes arranged on the substrate.
A plurality of transistors provided corresponding to each of the plurality of photodiodes, and
Have,
The i-type semiconductor layer and the n-type semiconductor layer are laminated on the p-type semiconductor layer, extend to a region not overlapped with the p-type semiconductor layer, and are provided so as to cover at least one of the transistors. Detection device to be. It has a signal line electrically connected to the photodiode and has
The detection device according to claim 1, wherein the i-type semiconductor layer and the n-type semiconductor layer are provided so as to cover the signal line. The p-type semiconductor layer is provided in the same layer as the semiconductor layer of the transistor.
The detection device according to claim 2, wherein the p-type semiconductor layer, the signal line, the i-type semiconductor layer, and the n-type semiconductor layer are laminated in this order in the direction perpendicular to the substrate. It has an insulating film that covers the plurality of transistors and the p-type semiconductor layer, and has an insulating film.
Claims 1 to 3 are the i-type semiconductor layer and the n-type semiconductor layer provided on the insulating film and connected to the p-type semiconductor layer via a contact hole provided in the insulating film. The detection device according to any one of the above items. The insulating film includes a first inorganic insulating film provided on the plurality of transistors and the p-type semiconductor layer, and a second inorganic insulating film provided on the first inorganic insulating film.
The detection device according to claim 4, wherein the i-type semiconductor layer and the n-type semiconductor layer are provided on the second inorganic insulating film. The insulating film includes the plurality of transistors, an inorganic insulating film provided on the p-type semiconductor layer, and an organic insulating film provided on the inorganic insulating film.
The detection device according to claim 4, wherein the i-type semiconductor layer and the n-type semiconductor layer are provided on the organic insulating film. It has an upper conductive layer that is electrically connected to the n-type semiconductor layer.
The i-type semiconductor layer and the n-type semiconductor layer have a notch portion formed in a region overlapping with at least a part of the transistor.
The detection device according to any one of claims 1 to 6, wherein the upper conductive layer is electrically connected to the transistor via the notch.

Images