JP2022020089A - Memory drive device, information processing device, and control method - Google Patents

Abstract

To provide a memory drive device, an information processing device, and a control method that reduce data corruption due to retention characteristics and improve reliability.SOLUTION: A memory drive device having a rewritable non-volatile memory includes: a data storage area that is composed of the non-volatile memory and can store data used for information processing; a test storage area that is composed of the non-volatile memory and stores predetermined test data; and a control unit that determines that a predetermined test data retention period is reached based on an index value indicating a ratio of memory failure to the test storage area in which the predetermined test data is stored in advance, and executes rewriting of data already stored in the data storage area when the predetermined data retention period is reached.SELECTED DRAWING: Figure 2

Description

The present invention relates to a memory drive device, an information processing device, and a control method.

In recent years, memory drive devices such as SSDs (Solid State Drives) have been known (see, for example, Patent Document 1). In such a memory drive device, for example, a non-volatile memory such as a NAND type (negative AND type) flash memory is used.

Japanese Unexamined Patent Publication No. 2020-17262

By the way, in a rewritable non-volatile memory such as a NAND flash memory, the written data may be garbled due to the passage of time, and the characteristic that the data is garbled due to the passage of time is a retention characteristic. This data retention period is called the retention period. In the conventional memory drive device described above, it is difficult to grasp how much time has passed since the data was written. Therefore, for example, when the retention period is exceeded, the data may be garbled.

The present invention has been made to solve the above problems, and an object thereof is to provide a memory drive device, an information processing device, and a control method capable of reducing data garbled due to retention characteristics and improving reliability. To do.

In order to solve the above problem, one aspect of the present invention is a memory drive device having a rewritable non-volatile memory, which is composed of the non-volatile memory and can store data used for information processing. Based on a test storage area composed of the non-volatile memory and storing predetermined test data, and an index value indicating the ratio of storage failure to the test storage area in which the predetermined test data is stored in advance. A memory provided with a control unit for determining that the data retention period has been reached and rewriting the already stored data to the data storage area when the predetermined data retention period is reached. It is a drive device.

Further, in one aspect of the present invention, in the memory drive device, the control unit stores the data when the index value reaches a predetermined threshold indicating that the predetermined data retention period has been reached. The data that has already been stored may be rewritten to the area.

Further, in one aspect of the present invention, in the memory drive device, the control unit is already stored in the data storage area and the test storage area when the predetermined data retention period is reached. You may want to rewrite the existing data.

Further, one aspect of the present invention is that in the memory drive device, the control unit has a change amount of the index value equal to or more than a predetermined threshold indicating that the predetermined data retention period has been reached. , The data already stored may be rewritten to the data storage area.

Further, in one aspect of the present invention, in the memory drive device, the index value includes a bit error rate when reading the test data in the test storage area, and the control unit controls the bit error rate. It may be determined that the predetermined data retention period has been reached based on the above.

Further, in one aspect of the present invention, in the memory drive device, the index value includes an applied voltage value capable of normally reading the test data in the test storage area, and the control unit controls the device. It may be determined that the predetermined data retention period has been reached based on the applied voltage value.

Further, one aspect of the present invention has an error correction code for correcting an error in the data stored in the non-volatile memory in the above memory drive device, and an error in the read data is corrected based on the error correction code. A correction processing unit for correction may be provided.

Further, one aspect of the present invention is an information processing device provided with the above-mentioned memory drive device and performing information processing using the data stored in the memory drive device.

Further, one aspect of the present invention has a rewritable non-volatile memory, is composed of the non-volatile memory, is composed of a data storage area capable of storing data used for information processing, and is composed of the non-volatile memory, and is predetermined. A control method for a memory drive device including a test storage area for storing test data of the above, wherein the control unit sets an index value indicating the ratio of storage failure to the test storage area in which the predetermined test data is stored in advance. Based on this, it is determined that the predetermined data retention period has been reached, and when the predetermined data retention period is reached, a control method for rewriting the already stored data to the data storage area is executed. Is.

According to the above aspect of the present invention, data garbled due to retention characteristics can be reduced and reliability can be improved.

It is a figure which shows an example of the main hardware composition of the information processing apparatus and SSD by 1st Embodiment. It is a block diagram which shows an example of the functional structure of SSD by 1st Embodiment. It is a flowchart which shows an example of the operation of SSD by 1st Embodiment. It is a block diagram which shows an example of the functional structure of SSD by 2nd Embodiment. It is a flowchart which shows an example of the operation of SSD by 2nd Embodiment. It is a block diagram which shows an example of the functional structure of SSD by 3rd Embodiment. It is a flowchart which shows an example of the operation of SSD by 3rd Embodiment.

Hereinafter, a memory drive device, an information processing device, and a control method according to an embodiment of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a diagram showing an example of a main hardware configuration of the information processing apparatus 100 and SSD 40 according to the first embodiment.
As shown in FIG. 1, the information processing apparatus 100 is, for example, a notebook type personal computer, and is a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a chipset 21, and a BIOS memory 22. , An embedded controller 31, an input unit 32, a power supply circuit 33, and an SSD 40.

The CPU (Central Processing Unit) 11 executes various arithmetic processes by program control and controls the entire information processing apparatus 100.

The main memory 12 is a writable memory used as a read area for the execution program of the CPU 11 or as a work area for writing the processing data of the execution program. The main memory 12 is composed of, for example, a plurality of DRAM (Dynamic Random Access Memory) chips. This execution program includes an OS (operating system), various drivers for operating peripheral devices by hardware, various services / utilities, application programs, and the like.

The video subsystem 13 is a subsystem for realizing a function related to image display, and includes a video controller. The video controller processes a drawing command from the CPU 11, writes the processed drawing information to the video memory, reads the drawing information from the video memory, and outputs the drawn drawing data (display data) to the display unit 14.

The display unit 14 is, for example, a liquid crystal display, and displays a display screen based on drawing data (display data) output from the video subsystem 13.

The chip set 21 includes USB (Universal Serial Bus), serial ATA (AT Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus, LPC (Low Pin Count) bus, and the like. It has a controller and multiple devices are connected. In FIG. 1, as an example of the device, the BIOS memory 22 and the SSD 40 are connected to the chipset 21.

The BIOS (Basic Input Output System) memory 22 is composed of, for example, an electrically rewritable non-volatile memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash ROM (flash memory). The BIOS memory 22 stores the BIOS, the system firmware for controlling the embedded controller 31, and the like.

The SSD (Solid State Drive) 40 (an example of a memory drive device) is a memory drive device having a rewritable non-volatile memory, and stores an OS, various drivers, various services / utilities, application programs, and various data. The information processing apparatus 100 executes various information processing by using the data stored in the SSD 40. The SSD 40 is connected to the chipset 21 by, for example, a serial ATA or a PCI-Express bus.
Further, the SSD 40 includes a plurality of flash memories 41 and a memory controller 42.

The flash memory 41 is, for example, a NAND flash memory, which is an example of a rewritable non-volatile memory. The flash memory 41 writes data (“0”) or erases data (“1”) to the memory cell by injecting or extracting electrons into the floating gate of the memory cell. In the flash memory 41, the data stored in the memory cell may be garbled because the electrons of the floating gate move with the passage of time. In the flash memory 41, the characteristic that data garbled occurs due to the passage of time is called a retention characteristic, and this data retention period is called a retention period. Also, this retention period tends to be shorter as the temperature rises.

The memory controller 42 is, for example, a processor including a CPU, ROM, RAM, etc. (not shown), and controls the SSD 40 in an integrated manner. The memory controller 42 has, for example, control processing of the host interface (host I / F) with the chipset 21, control processing of the memory interface (memory I / F) with the flash memory 41, and data of the flash memory 41. Execute processing such as management processing.

The embedded controller 31 is a one-chip microcomputer that monitors and controls various devices (peripheral devices, sensors, etc.) regardless of the system state of the information processing device 100. Further, the embedded controller 31 has a power supply management function for controlling the power supply circuit 33. The embedded controller 31 is composed of a CPU, ROM, RAM, etc. (not shown), and includes a plurality of channels of A / D input terminals, D / A output terminals, timers, and digital input / output terminals. For example, an input unit 32, a power supply circuit 33, and the like are connected to the embedded controller 31 via their input / output terminals, and the embedded controller 31 controls these operations.

The input unit 32 is, for example, an input device such as a keyboard, a pointing device, or a touch pad.

The power supply circuit 33 includes, for example, a DC / DC converter, a charge / discharge unit, an AC / DC adapter, and the like, and requires a DC voltage supplied from an external power source or a battery to operate the information processing apparatus 100. Convert to multiple voltages. Further, the power supply circuit 33 supplies electric power to each part of the information processing apparatus 100 based on the control from the embedded controller 31.

Next, with reference to FIG. 2, the functional configuration of the SSD 40 according to the present embodiment will be described.
FIG. 2 is a block diagram showing an example of the functional configuration of the SSD 40 according to the present embodiment.

As shown in FIG. 2, the SSD 40 includes a data storage unit 50 and a control unit 60.
The data storage unit 50 is, for example, a storage unit composed of the plurality of flash memories 41 described above, and includes, for example, a data storage area 51, an ECC (Error Correction Code) storage area 52, and a test storage area 53. ..

The data storage area 51 is composed of a flash memory 41 and is a storage area capable of storing data used for information processing. The data storage area 51 stores, for example, an OS, various drivers, various services / utilities, application programs, various data, and the like.

The ECC storage area 52 is composed of a flash memory 41, and is a storage area for storing an error correction code (ECC) for correcting an error in the data stored in the data storage area 51 and the test storage area 53. In the ECC storage area 52, for example, when data is stored (written) in the data storage area 51 or the test storage area 53, an error correction code (ECC) corresponding to the data is stored.

The test storage area 53 is composed of a flash memory 41 and stores predetermined test data. The test storage area 53 stores test data for determining whether or not a predetermined data retention period indicating a predetermined period has been reached since the data was written. In the test storage area 53, for example, test data is stored when the information processing apparatus 100 ships. Further, in the test storage area 53, for example, the test data may be re-stored (re-written) when the OS is reinstalled after the information processing apparatus 100 is shipped.

The control unit 60 is a functional unit realized by the memory controller 42 described above, and executes various processes of the SSD 40. The control unit 60 includes a host I / F processing unit 61, a memory I / F processing unit 62, a data management unit 63, an ECC processing unit 64, and a test processing unit 65.

The host I / F processing unit 61 controls the interface between the chipset 21 and the SSD 40. The host I / F processing unit 61 controls an interface such as a serial ATA or a PCI-Express bus, and receives commands such as data writing and reading from the chipset 21. Further, the host I / F processing unit 61 outputs output information such as data read from the data storage unit 50 to the chipset 21 by an interface such as a serial ATA or a PCI-Express bus.

The memory I / F processing unit 62 controls the interface between the control unit 60 (memory controller 42) and the data storage unit 50 (plurality of flash memories 41). The memory I / F processing unit 62 outputs, for example, erase, write, and read commands to the flash memory 41 to control the flash memory 41.

The data management unit 63 manages the correspondence between the logical address of the SSD used for control from the information processing device 100 and the physical address of the data storage unit 50 (flash memory 41), and manages the data stored in the data storage unit 50. do. The data management unit 63 executes various processes based on various commands from the chipset 21 received by the host I / F processing unit 61.

For example, the data management unit 63 converts the logical address of the data access (write or read) command received by the host I / F processing unit 61 into the physical address of the data storage unit 50 (flash memory 41), and the memory I / A command is output to the data storage unit 50 (flash memory 41) via the F processing unit 62. Further, the data management unit 63 uses the data (for example, read data, etc.) of the data storage unit 50 (flash memory 41) acquired by the memory I / F processing unit 62 as data on the logical address of the host I / F. It is output to the chip set 21 via the processing unit 61.

When the ECC function is effective, the data management unit 63 acquires the data read from the data storage unit 50 and the ECC of the ECC storage area 52 corresponding to the read data, and performs error correction processing. Then, the read data is output to the chip set 21 via the host I / F processing unit 61.

The ECC processing unit 64 (an example of the correction processing unit) corrects an error in the data read from the data storage unit 50 based on the ECC (error correction code). The ECC processing unit 64 determines, for example, whether or not data garbled (bit garbled) has occurred based on the read data and the ECC corresponding to the read data, and the data garbled (bit garbled) is generated. If it occurs, ECC is used to execute error correction processing to correct garbled data.

The test processing unit 65 determines that a predetermined data retention period has been reached based on an index value indicating the ratio of storage defects to the test storage area 53, and when the predetermined data retention period is reached, the data storage area 65. The data already stored is rewritten to the 51. Here, the index value is, for example, a bit error rate (hereinafter referred to as BER (Bit Error Rate)) when reading the test data in the test storage area 53, and the test processing unit 65 sets the BER in the test storage area 53. It is calculated, and based on the calculated BER, it is determined that the predetermined data retention period has been reached.

For example, the test processing unit 65 determines whether or not the BER has reached a predetermined threshold value R1 (whether or not the BER has reached a predetermined threshold value R1 or more). The predetermined threshold R1 is a value indicating that the predetermined data retention period has been reached. For example, the ECC processing unit is based on the retention characteristic (relationship characteristic between the passage of time and garbled data) in the flash memory 41. In the error correction process according to 64, the data in the test storage area 53 is set within a range in which the error can be corrected.

Further, the test processing unit 65 determines whether or not the BER has reached the predetermined threshold value R1 or whether or not the BER has reached the predetermined threshold value R1 or more at the timing when the information processing apparatus 100 is started or shut down, for example. ) Is determined. When the BER reaches a predetermined threshold value R1 (when the BER reaches a predetermined threshold value R1 or more), the test processing unit 65 passes through the memory I / F processing unit 62 to a buffer composed of a RAM (not shown). The data already stored in the data storage area 51 is saved in the storage unit, and the data is rewritten (re-stored).

The test processing unit 65 may rewrite the data to the test storage area 53 when rewriting the already stored data. That is, when the predetermined data retention period is reached, the test processing unit 65 may rewrite the already stored data to the data storage area 51 and the test storage area 53.

Next, the operation of the SSD 40 according to the present embodiment will be described with reference to the drawings.
FIG. 3 is a flowchart showing an example of the operation of the SSD 40 according to the present embodiment. Here, the process in which the SSD 40 prevents data garbled due to retention will be described.

As shown in FIG. 3, the control unit 60 of the SSD 40 first calculates the BER of the test storage area 53 (step S101). The test processing unit 65 of the control unit 60 reads the test data of the test storage area 53 via the memory I / F processing unit 62, and calculates the BER.

Next, the test processing unit 65 determines whether or not the BER is equal to or higher than the predetermined threshold value R1 (step S102). Here, the predetermined threshold value R1 is a value indicating that the predetermined data retention period has been reached. That is, the test processing unit 65 determines whether or not the predetermined data retention period has been reached based on the BER. When the BER is equal to or higher than the predetermined threshold value R1 (step S102: YES), the test processing unit 65 advances the processing to step S103. Further, the test processing unit 65 ends the processing when the BER is less than the predetermined threshold value R1 (step S102: NO).

In step S103, the test processing unit 65 rewrites the data in the data storage area 51. The test processing unit 65 reads and saves the data already stored in the data storage area 51 via the memory I / F processing unit 62, and rewrites (re-stores) the data. The test processing unit 65 may rewrite the data already stored in the data storage area 51 and the test storage area 53. After the processing of step S103, the test processing unit 65 ends the processing.

The test processing unit 65 executes the processing shown in FIG. 3, for example, at the timing when the information processing apparatus 100 is started or at the timing when the information processing apparatus 100 is shut down. Further, the test processing unit 65 may execute the processing shown in FIG. 3 as background processing during a period in which access (writing or reading) from the information processing apparatus 100 to the SSD 40 is not executed.

As described above, the SSD 40 (memory drive device) according to the present embodiment is a memory drive device having a rewritable flash memory 41 (nonvolatile memory), and includes a data storage area 51, a test storage area 53, and the like. A control unit 60 is provided. The data storage area 51 is composed of a flash memory 41 and is an area capable of storing data used for information processing. The test storage area 53 is composed of a flash memory 41 and stores predetermined test data. The control unit 60 determines that the predetermined data retention period has been reached based on the index value indicating the ratio of the storage failure to the test storage area 53 in which the predetermined test data is stored in advance, and sets the predetermined data retention period. When it reaches the data storage area 51, the data already stored is rewritten.

As a result, the SSD 40 according to the present embodiment rewrites the data storage area 51 when the predetermined test data in the test storage area 53 reaches the predetermined data retention period, so that the retention characteristic of the flash memory 41 Data garbled due to data can be reduced and reliability can be improved.

Further, in the present embodiment, the control unit 60 is already stored in the data storage area 51 when the index value reaches a predetermined threshold value R1 indicating that the predetermined data retention period has been reached. Perform data rewrite. For example, the index value includes a bit error rate (for example, BER: Bit Error Rate) when reading the test data in the test storage area 53. The control unit 60 determines that a predetermined data retention period has been reached based on the bit error rate (BER). That is, when the bit error rate (BER) reaches a predetermined threshold value R1 (when the predetermined threshold value R1 or more is reached), the control unit 60 stores data already stored in the data storage area 51. Perform a rewrite.

As a result, the SSD 40 according to the present embodiment can use the bit error rate (BER) even when it is not possible to grasp, for example, the period during which the information processing apparatus 100 is not activated or the temperature change has occurred. It is possible to accurately determine the possibility of data garbled due to retention. Therefore, the SSD 40 according to the present embodiment can more appropriately reduce data garbled due to the retention characteristic of the flash memory 41.

Further, in the present embodiment, when the predetermined data retention period is reached, the control unit 60 rewrites the already stored data to the data storage area 51 and the test storage area 53. You may.

As a result, the SSD 40 according to the present embodiment can reset the influence of the retention of not only the data storage area 51 but also the test storage area 53. The data retention period can be determined more accurately.

Further, in the present embodiment, the control unit 60 determines that the predetermined data retention period has been reached during the period in which the information processing apparatus 100 does not access (write or read) the SSD 40 as background processing. You may try to do it. Further, as a background process, the control unit 60 may rewrite the already stored data to the data storage area 51 when the predetermined data retention period is reached. ..

Thereby, the SSD 40 according to the present embodiment can reduce the influence of the information processing apparatus 100 on the information processing, reduce the garbled data due to the retention characteristic of the flash memory 41, and improve the reliability.

Further, the information processing apparatus 100 according to the present embodiment includes the SSD 40 described above, and executes information processing using the data stored in the SSD 40.
As a result, the information processing apparatus 100 according to the present embodiment has the same effect as the SSD 40 described above, can reduce data garbled due to the retention characteristic of the flash memory 41, and can improve reliability.

Further, the control method according to the present embodiment has a rewritable flash memory 41, is composed of a flash memory 41, is composed of a data storage area 51 capable of storing data used for information processing, and is composed of a flash memory 41, and is predetermined. It is a control method of SSD 40 including a test storage area 53 for storing the test data of the above. In the control method, the control unit 60 determines that the predetermined data retention period has been reached based on the index value indicating the ratio of the storage failure to the test storage area 53 in which the predetermined test data is stored in advance, and determines that the predetermined data retention period has been reached. When the data retention period is reached, the data already stored is rewritten to the data storage area 51.

As a result, the control method according to the present embodiment has the same effect as the SSD 40 and the information processing apparatus 100 described above, reduces data garbled due to the retention characteristics of the flash memory 41, and can improve reliability.

[Second Embodiment]
Next, the SSD 40a according to the second embodiment will be described with reference to the drawings.
In the second embodiment, a modification will be described in which it is determined by the amount of change in the index value (BER) that the predetermined data retention period has been reached.

FIG. 4 is a block diagram showing an example of the functional configuration of the SSD 40a according to the present embodiment.
As shown in FIG. 4, the SSD 40a (child proportional to the memory drive device) includes a data storage unit 50a and a control unit 60a.

In this figure, the same reference numerals are given to the same configurations as those in FIG. 2, and the description thereof will be omitted. Further, since the hardware configuration of the SSD 40a and the information processing apparatus 100 according to the present embodiment is the same as that of the first embodiment shown in FIG. 1, the description thereof will be omitted here.

The data storage unit 50a is a storage unit composed of the plurality of flash memories 41 described above, and includes, for example, a data storage area 51, an ECC storage area 52, a test storage area 53, and a BER storage area 54.

The BER storage area 54 is composed of a flash memory 41 and stores the test storage area 53 and the initial values of the BER. The initial value of BER is updated when the test processing unit 65a rewrites the data to the data storage area 51.

The control unit 60a is a functional unit realized by the memory controller 42 described above, and executes various processes of the SSD 40a. The control unit 60a includes a host I / F processing unit 61, a memory I / F processing unit 62, a data management unit 63, an ECC processing unit 64, and a test processing unit 65a.

The test processing unit 65a has already been stored in the data storage area 51 when the amount of change in the index value (BER) becomes equal to or higher than the predetermined threshold value ΔR1 indicating that the predetermined data retention period has been reached. Rewrite the existing data.

For example, the test processing unit 65a calculates the BER of the test storage area 53 and acquires the initial value of the BER of the BER storage area 54. The test processing unit 65a determines that the predetermined data retention period has been reached when the amount of change in the calculated BER from the initial value of the BER becomes equal to or greater than the predetermined threshold value ΔR1. Here, the predetermined threshold value ΔR1 is, for example, an error correction process by the ECC processing unit 64 based on the retention characteristic (relationship characteristic between the passage of time and garbled data) in the flash memory 41, and the data in the test storage area 53 is stored. It is set as the amount of change in BER corresponding to the period in which the error can be corrected.

Further, when the change amount of the index value (BER) becomes equal to or higher than the predetermined threshold value ΔR1, the test processing unit 65a rewrites the already stored data to the data storage area 51 and rewrites the data. , The initial value of BER stored in the BER storage area 54 is updated to the calculated current BER value.

It should be noted that the processing of the test processing unit 65a in the present embodiment is different from the processing of determining that the predetermined data retention period has been reached due to the amount of change in the index value (BER) described above. Other processing is the same as that of the test processing unit 65 of the first embodiment.

Next, the operation of the SSD 40a according to the present embodiment will be described with reference to FIG.
FIG. 5 is a flowchart showing an example of the operation of the SSD 40a according to the present embodiment. Here, the process in which the SSD 40a prevents data garbled due to retention will be described.

As shown in FIG. 5, the control unit 60a of the SSD 40a first calculates the BER of the test storage area 53 (step S201). The test processing unit 65a of the control unit 60a reads out the test data of the test storage area 53 via the memory I / F processing unit 62, and calculates the BER.

Next, the test processing unit 65a acquires the initial value of the BER (the value of the past BER) from the BER storage area 54 (step S202). The test processing unit 65a acquires the initial value of the BER stored in the BER storage area 54 via the memory I / F processing unit 62.

Next, the test processing unit 65a determines whether or not the amount of change in BER is equal to or greater than a predetermined threshold value ΔR1 (step S203). Here, the predetermined threshold value ΔR1 is a value indicating that the predetermined data retention period has been reached. The test processing unit 65a calculates the amount of change in BER from the difference between the calculated BER and the initial value of BER, and determines whether or not the amount of change in BER is equal to or greater than a predetermined threshold value ΔR1. When the amount of change in BER is equal to or greater than the predetermined threshold value ΔR1 (step S203: YES), the test processing unit 65a advances the processing to step S204. Further, the test processing unit 65a ends the processing when the amount of change in BER is less than the predetermined threshold value ΔR1 (step S203: NO).

In step S204, the test processing unit 65a rewrites the data in the data storage area 51. The test processing unit 65a executes the same processing as in step S103 of FIG. 3 described above.

Next, the test processing unit 65a stores the BER in the BER storage area 54 (step S205). That is, the test processing unit 65a updates the initial value of the BER stored in the BER storage area 54 to the calculated current BER value. After the processing of step S205, the test processing unit 65a ends the processing.

The test processing unit 65a executes the processing shown in FIG. 5, for example, at the timing when the information processing apparatus 100 is started or at the timing when the information processing apparatus 100 is shut down. Further, the test processing unit 65a may execute the processing shown in FIG. 5 as a background processing during a period in which the information processing apparatus 100 does not access (write or read) the SSD 40a.

Further, as in the first embodiment, the test processing unit 65a rewrites the data already stored in the data storage area 51 and the test storage area 53 when the predetermined data retention period is reached. May be executed.

As described above, in the present embodiment, the control unit 60a (test processing unit 65a) has a predetermined change amount of an index value (for example, a change amount of BER) indicating the ratio of memory failure to the test storage area 53. When the predetermined threshold value ΔR1 or more indicating that the data retention period has been reached is reached, the data already stored is rewritten to the data storage area 51.

As a result, the SSD 40a (memory drive device) and the information processing device 100 according to the present embodiment have the same effects as those of the first embodiment described above, reduce garbled data due to the retention characteristics of the flash memory 41, and are reliable. Can be improved.

[Third Embodiment]
Next, the SSD 40b according to the third embodiment will be described with reference to the drawings.
In the third embodiment, there is a modification for determining that the predetermined data retention period has been reached based on the applied voltage value of the flash memory 41 instead of the index value. explain.

FIG. 6 is a block diagram showing an example of the functional configuration of the SSD 40b according to the present embodiment.
As shown in FIG. 6, the SSD 40b (child proportional to the memory drive device) includes a data storage unit 50 and a control unit 60b.

In this figure, the same reference numerals are given to the same configurations as those in FIG. 2, and the description thereof will be omitted. Further, since the hardware configuration of the SSD 40b and the information processing apparatus 100 according to the present embodiment is the same as that of the first embodiment shown in FIG. 1, the description thereof will be omitted here.

The control unit 60b is a functional unit realized by the memory controller 42 described above, and executes various processes of the SSD 40b. The control unit 60b includes a host I / F processing unit 61, a memory I / F processing unit 62, a data management unit 63, an ECC processing unit 64, and a test processing unit 65b.

The test processing unit 65b determines that the predetermined data retention period has been reached based on the applied voltage value (an example of the index value) capable of normally reading the test data in the test storage area 53. Here, the applied voltage value is a voltage applied to the memory cell when reading the data of the flash memory 41, and includes, for example, a source-drain voltage, a gate applied voltage, and the like.

By the way, the cell threshold voltage (hereinafter referred to as cell VT voltage) indicating the write depth of the memory cell changes with the passage of time. Even when the cell VT voltage changes, it may be read normally by changing the source-drain voltage and the gate applied voltage at the time of data reading according to the cell VT voltage. In the present embodiment, the test processing unit 65b determines that a predetermined data retention period has been reached based on the applied voltage value (cell applied voltage value) corresponding to the change in the cell VT voltage.

The test processing unit 65b detects a readable cell applied voltage (applied voltage value) in the test storage area 53 in response to a change in the cell VT voltage, and the cell applied voltage reaches a predetermined data retention period. It is determined whether or not a predetermined threshold value V1 indicating the above value has been reached. Here, the predetermined threshold value V1 is, for example, an error correction process by the ECC processing unit 64 based on the retention characteristic (relationship characteristic between the passage of time and garbled data) in the flash memory 41, and the data in the test storage area 53 is stored. The cell applied voltage value corresponding to the error-correctable range period is set.
When it is determined that the predetermined data retention period has been reached, the test processing unit 65b rewrites the already stored data to the data storage area 51.

As in the first embodiment, the test processing unit 65b is configured to rewrite the data to the test storage area 53 when rewriting the already stored data. May be good.

Next, the operation of the SSD 40b according to the present embodiment will be described with reference to FIG. 7.
FIG. 7 is a flowchart showing an example of the operation of the SSD 40b according to the present embodiment. Here, the process in which the SSD 40b prevents data garbled due to retention will be described.

As shown in FIG. 7, the control unit 60b of the SSD 40b first detects the readable cell applied voltage of the test storage area 53 (step S301). The test processing unit 65b of the control unit 60b changes the cell applied voltage via the memory I / F processing unit 62, reads out the test data of the test storage area 53, and calculates the limit value of the readable cell applied voltage. do.

Next, the test processing unit 65b determines whether or not the cell applied voltage has reached a predetermined threshold value V1 (step S302). Here, the predetermined threshold value V1 is a value indicating that the predetermined data retention period has been reached. That is, the test processing unit 65b determines whether or not a predetermined data retention period has been reached based on the cell applied voltage. When the cell applied voltage reaches a predetermined threshold value V1 (step S302: YES), the test processing unit 65b advances the processing to step S303. Further, the test processing unit 65b ends the processing when the cell applied voltage does not reach a predetermined value (step S302: NO).

In step S303, the test processing unit 65b rewrites the data in the data storage area 51. The test processing unit 65b executes the same processing as in step S103 of FIG. 3 described above.

The test processing unit 65b executes the processing shown in FIG. 7, for example, at the timing when the information processing apparatus 100 is started or at the timing when the information processing apparatus 100 is shut down. Further, the test processing unit 65 may execute the processing shown in FIG. 7 as a background processing during a period in which the information processing apparatus 100 does not access (write or read) the SSD 40b.

As described above, in the present embodiment, the index value indicating the ratio of storage failure to the test storage area 53 is an applied voltage value (cell applied voltage) capable of normally reading the test data of the test storage area 53. Is included. The control unit 60b (test processing unit 65b) determines that a predetermined data retention period has been reached based on the applied voltage value cell applied voltage).

As a result, the SSD 40b (memory drive device) and the information processing device 100 according to the present embodiment have the same effects as those of the first embodiment described above, reduce garbled data due to the retention characteristics of the flash memory 41, and are reliable. Can be improved.

The present invention is not limited to each of the above embodiments, and can be modified without departing from the spirit of the present invention.
For example, in each of the above embodiments, the information processing apparatus 100 has been described as an example of a notebook type personal computer, but the present invention is not limited to this, and the information processing apparatus 100 is not limited to this, for example, other than a desktop personal computer, a tablet terminal apparatus, and the like. It may be an information processing device of.

Further, in the above embodiment, an example in which BER or a cell applied voltage is used as an index value indicating the ratio of memory failure to the test storage area 53 has been described, but the present invention is not limited to this, and other index values may be used. You may use it. Further, in the above embodiment, for example, a BER and a cell applied voltage may be used in combination as an index value.

Further, in each of the above embodiments, an example in which the processing by the control unit 60 (60a, 60b) (test processing unit 65 (65a, 65b)) is executed as the internal processing of the SSD 40 (40a, 40b) has been described. The information processing device 100 may execute a part of the processing of the test processing unit 65 (65a, 65b) without being limited to this.

Further, in each of the above embodiments, the test processing unit 65 (65a, 65b) performs a determination process of reaching a predetermined data retention period and a rewrite process of rewriting the data storage area 51. , The example of continuous execution has been described, but the present invention is not limited to this, and the determination process and the rewrite process may be executed separately. The test processing unit 65 (65a, 65b) may execute the rewrite process, for example, by using the background media scan of the SSD 40 (40a, 40b) as a trigger.

Further, the test processing unit 65 (65a, 65b) may execute the rewriting process on the block (or page) of the flash memory 41 in which the data in the data storage area 51 is written. Further, the test processing unit 65 (65a, 65b) detects, for example, a block (or page) having a high BER rescued by the ECC function in the data storage area 51 in the rewrite process, and the detected BER or the like. The rewrite process may be executed for the block (or page) having a high value.

Further, in each of the above embodiments, the SSD 40 (40a, 40b) has described an example in which the ECC processing unit 64 is provided as a functional unit realized by the memory controller 42, but the present invention is not limited to this, and for example. The flash memory 41 may include an ECC processing unit 64.

Further, in the third embodiment described above, an example in which the cell applied voltage is used instead of the BER has been described for the first embodiment, but similarly for the second embodiment, the cell applied voltage has been described. May be used. In this case, the test processing unit 65b is already stored in the data storage area 51 when the amount of change in the cell applied voltage becomes a predetermined threshold value ΔV1 or more indicating that the predetermined data retention period has been reached. Rewrite the existing data.

Each configuration of the SSD 40 (40a, 40b) and the information processing apparatus 100 described above has a computer system inside. Then, the program for realizing the functions of the respective configurations included in the SSD 40 (40a, 40b) and the information processing apparatus 100 described above is recorded on a computer-readable recording medium, and the program recorded on the recording medium is recorded on the computer. The processing in each configuration provided in the SSD 40 (40a, 40b) and the information processing apparatus 100 described above may be performed by loading and executing the system in the system. Here, "loading and executing a program recorded on a recording medium into a computer system" includes installing the program in the computer system. The term "computer system" as used herein includes hardware such as an OS and peripheral devices.
Further, the "computer system" may include a plurality of computer devices connected via a network including a communication line such as the Internet, WAN, LAN, and a dedicated line. Further, the "computer-readable recording medium" refers to a portable medium such as a flexible disk, a magneto-optical disk, a ROM, or a CD-ROM, and a storage device such as a hard disk built in a computer system. As described above, the recording medium in which the program is stored may be a non-transient recording medium such as a CD-ROM.

The recording medium also includes an internal or external recording medium accessible from the distribution server for distributing the program. It should be noted that the program is divided into a plurality of units, and after downloading at different timings, the SSD 40 (40a, 40b) and the information processing apparatus 100 are combined with each configuration, or a distribution server that distributes each of the divided programs. May be different. Furthermore, a "computer-readable recording medium" is a volatile memory (RAM) inside a computer system that serves as a server or client when a program is transmitted via a network, and holds the program for a certain period of time. It shall include things. Further, the above program may be for realizing a part of the above-mentioned functions. Further, a so-called difference file (difference program) may be used, which can realize the above-mentioned function in combination with a program already recorded in the computer system.

Further, a part or all of the above-mentioned functions may be realized as an integrated circuit such as an LSI (Large Scale Integration). Each of the above-mentioned functions may be made into a processor individually, or a part or all of them may be integrated into a processor. Further, the method of making an integrated circuit is not limited to the LSI, and may be realized by a dedicated circuit or a general-purpose processor. Further, when an integrated circuit technology that replaces an LSI appears due to advances in semiconductor technology, an integrated circuit based on this technology may be used.

11 CPU
12 Main memory 13 Video subsystem 14 Display 21 Chipset 22 BIOS memory 31 Embedded controller (EC)
32 Input section 33 Power supply circuit 40, 40a, 40b SSD
41 Flash memory 42 Memory controller 50, 50a Data storage 51 Data storage area 52 ECC storage area 53 Test storage area 54 BER storage area 60, 60a, 60b Control unit 61 Host I / F processing unit 62 Memory I / F processing unit 63 Data management unit 64 ECC processing unit 65, 65a, 65b Test processing unit 100 Information processing device

In order to solve the above problem, one aspect of the present invention is a memory drive device having a rewritable non-volatile memory, which is composed of the non-volatile memory and can store data used for information processing. Based on a test storage area composed of the non-volatile memory and storing predetermined test data, and an index value indicating the ratio of storage failure to the test storage area in which the predetermined test data is stored in advance. The data retention period is determined to be reached, and when the predetermined data retention period is reached, the data storage area is provided with a control unit for rewriting the already stored data. The control unit receives data already stored in the data storage area when the amount of change in the index value becomes equal to or greater than a predetermined threshold indicating that the predetermined data retention period has been reached. A memory drive device that performs rewrites .

Further, one aspect of the present invention has a rewritable non-volatile memory, is composed of the non-volatile memory, is composed of a data storage area capable of storing data used for information processing, and is composed of the non-volatile memory, and is predetermined. A control method for a memory drive device including a test storage area for storing test data of the above, wherein the control unit sets an index value indicating the ratio of storage failure to the test storage area in which the predetermined test data is stored in advance. Based on this, it is determined that the predetermined data retention period has been reached, and it is shown that the change amount of the index value has reached the predetermined data retention period even when the predetermined data retention period has been reached. This is a control method for rewriting data that has already been stored in the data storage area when the value exceeds a predetermined threshold .

Claims (9)

A memory drive device with rewritable non-volatile memory.
A data storage area composed of the non-volatile memory and capable of storing data used for information processing, and
A test storage area composed of the non-volatile memory and storing predetermined test data, and
When it is determined that the predetermined data retention period has been reached based on the index value indicating the ratio of the storage failure to the test storage area in which the predetermined test data has been stored in advance, and the predetermined data retention period has been reached. A memory drive device including a control unit that rewrites data that has already been stored in the data storage area. When the index value reaches a predetermined threshold value indicating that the predetermined data retention period has been reached, the control unit rewrites the data already stored in the data storage area. The memory drive device according to claim 1. According to claim 1 or 2, the control unit executes rewriting of data already stored in the data storage area and the test storage area when the predetermined data retention period is reached. The memory drive device described. The control unit receives data already stored in the data storage area when the amount of change in the index value becomes equal to or greater than a predetermined threshold value indicating that the predetermined data retention period has been reached. The memory drive device according to claim 1, wherein the rewrite is performed. The index value includes a bit error rate when reading the test data in the test storage area.
The memory drive device according to any one of claims 1 to 4, wherein the control unit determines that the predetermined data retention period has been reached based on the bit error rate. The index value includes an applied voltage value capable of normally reading the test data in the test storage area.
The memory drive device according to any one of claims 1 to 4, wherein the control unit determines that the predetermined data retention period has been reached based on the applied voltage value. Any of claims 1 to 6, which has an error correction code for correcting an error in data stored in the non-volatile memory, and includes a correction processing unit for correcting an error in read data based on the error correction code. The memory drive device according to item 1. The memory drive device according to any one of claims 1 to 7 is provided.
An information processing device that executes information processing using the data stored in the memory drive device. A data storage area having a rewritable non-volatile memory, which is composed of the non-volatile memory and can store data used for information processing, and a test storage area which is composed of the non-volatile memory and stores predetermined test data. It is a control method of a memory drive device including
The control unit
It is determined that the predetermined data retention period has been reached based on the index value indicating the ratio of the storage failure to the test storage area in which the predetermined test data is stored in advance.
A control method for rewriting data that has already been stored in the data storage area when the predetermined data retention period is reached.

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