JP2022012503A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device that reduces both internal gate resistance and an on-resistance ratio.SOLUTION: In a semiconductor device, an active cell 23 formed of a drift region 27, a first impurity region 28, and a second impurity region 29 includes a first unit structure 30 and a second unit structure 31. The first unit structure is formed in a region of a first main surface opposite to a source electrode layer 5 in a Z axial direction. The second unit structure is formed in a region of the first main surface opposite to a gate electrode layer 6. The first unit structure and the second unit structure have planar patterns different from each other. Each first unit structure is formed in quadrangular shape in planar view. A quadrangular-shaped first source region 32 in planar view, a square-ring-shaped first body region that surrounds the first source region, and a square-ring-shaped first drift region 34 that surrounds the first body region are formed in each first unit structure.SELECTED DRAWING: Figure 4

Description

The present invention relates to a semiconductor device.

Patent Document 1 describes a semiconductor layer having a first surface and a second surface, an emitter electrode, a collector electrode, a trench gate electrode extending in a first direction substantially parallel to the first surface, and a first. Dummy trench gate electrode extending in the direction of, p-base region, emitter region, n-base region, collector region, trench gate electrode, trench gate insulating film, dummy trench gate electrode, dummy trench gate insulation. The membrane, the first gate pad electrode connected to the trench gate electrode and the dummy trench gate electrode, the first electrical resistance connected between the first gate pad electrode and the trench gate electrode, and the first Disclosed is a semiconductor device comprising a second electrical resistor connected between a gate pad electrode and a dummy trench gate electrode, wherein the CR time constant of the trench gate electrode is smaller than the CR time constant of the dummy trench gate electrode. ing.

Japanese Unexamined Patent Publication No. 2019-57702

The semiconductor device according to the embodiment of the present invention includes a semiconductor chip having a first main surface, a first electrode formed on the first main surface, and the first main surface formed on the first main surface. A second electrode separated from the electrode, a first unit structure formed in a region facing the first electrode in a plan view, and a second unit structure formed in a region facing the second electrode in a plan view. Each of the first unit structure and the second unit structure is formed in a first conductive type drift region formed on the surface layer portion of the first main surface and a surface layer portion of the drift region. The first impurity region of the second conductive type, the second impurity region of the first conductive type formed on the surface layer of the first impurity region, and the first between the drift region and the second impurity region. The second impurity region of the first unit structure includes a third electrode facing a channel region formed in a portion of the impurity region, and the second impurity region is electrically connected to the first electrode and is the first unit. The second impurity region of the structure and the second impurity region of the second unit structure are electrically connected to each other in a state of being electrically separated from the drift region by the first impurity region.

FIG. 1 is a schematic perspective view of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a schematic plan view of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a diagram for explaining an arrangement pattern of active cells in the semiconductor device. FIG. 4 is an enlarged view of a main part of the portion surrounded by the alternate long and short dash line IV of FIG. FIG. 5 is a diagram for explaining the connection relationship of the first impurity region (p-type region) of FIG. FIG. 6 is an enlarged view of a main part of the portion surrounded by the alternate long and short dash line VI of FIG. FIG. 7 is a diagram for explaining the connection relationship of the first impurity region (p-type region) of FIG. FIG. 8 is an enlarged view of a main part of the portion surrounded by the alternate long and short dash line VIII of FIG. FIG. 9 is a diagram for explaining the connection relationship of the first impurity region (p-type region) of FIG. FIG. 10A is a cross-sectional view showing a cross section of XA-XA of FIG. FIG. 10B is a cross-sectional view showing a cross section of XB-XB of FIG. 11A is a cross-sectional view showing a cross section of XIA-XIA of FIG. 11B is a cross-sectional view showing the XIB-XIB cross section of FIG. FIG. 12A is a cross-sectional view showing a cross section of XIIA-XIIA of FIG. FIG. 12B is a cross-sectional view showing a cross section of XIIB-XIIB of FIG. FIG. 13A is a diagram showing a part of a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 13B is a diagram showing the next step of FIG. 13A. FIG. 13C is a diagram showing the next step of FIG. 13B. FIG. 13D is a diagram showing the next step of FIG. 13C. FIG. 13E is a diagram showing the next step of FIG. 13D. FIG. 13F is a diagram showing the next step of FIG. 13E. FIG. 13G is a diagram showing the next step of FIG. 13F. FIG. 13H is a diagram showing the next step of FIG. 13G. FIG. 14 is a diagram showing the internal gate resistance and the on-resistance ratio of the simulation example. FIG. 15 is a schematic plan view of the semiconductor device according to the second embodiment of the present invention, and is an enlarged view of a main part corresponding to FIG. FIG. 16 is a diagram showing a first modification of the first unit structure and the second unit structure. FIG. 17 is a diagram showing a first unit structure and a second modification of the second unit structure. FIG. 18 is a diagram showing a third modification of the first unit structure and the second unit structure.

<Embodiment of the present invention>
First, embodiments of the present invention will be listed and described.
The semiconductor device according to the embodiment of the present invention includes a semiconductor chip having a first main surface, a first electrode formed on the first main surface, and the first main surface formed on the first main surface. A second electrode separated from the electrode, a first unit structure formed in a region facing the first electrode in a plan view, and a second unit structure formed in a region facing the second electrode in a plan view. Each of the first unit structure and the second unit structure is formed in a first conductive type drift region formed on the surface layer portion of the first main surface and a surface layer portion of the drift region. The first impurity region of the second conductive type, the second impurity region of the first conductive type formed on the surface layer of the first impurity region, and the first between the drift region and the second impurity region. The second impurity region of the first unit structure includes a third electrode facing a channel region formed in a portion of the impurity region, and the second impurity region is electrically connected to the first electrode and is the first unit. The second impurity region of the structure and the second impurity region of the second unit structure are electrically connected to each other in a state of being electrically separated from the drift region by the first impurity region.

According to this configuration, since the second impurity regions of the first unit structure and the second unit structure are connected to each other, the current flowing through the second unit structure can be taken out from the first unit structure. As a result, an active cell capable of conducting a current can be formed in a region facing the second electrode. As a result, the region facing the second electrode on the first main surface of the semiconductor chip can be effectively utilized.

The "region facing the first electrode in a plan view" may be a "region covered with the first electrode in a plan view", or a "region facing the second electrode in a plan view". May be "a region covered by the second electrode in a plan view".
In the semiconductor device according to the embodiment of the present invention, the second impurity region of the second unit structure is formed on the outer peripheral portion of the second unit structure, and the second impurity region of the first unit structure is formed. In the first unit structure, it is formed in the inner part inside the first impurity region, is formed around the second unit structure, and has the second impurity region and the first unit structure of the second unit structure. A second conductive type separation region that electrically separates the drift region of the above, and the second impurity region of the first unit structure that is drawn from the second impurity region of the second unit structure and passes through the separation region. It may include a first conductive type connection region connected to the impurity region.

In the semiconductor device according to the embodiment of the present invention, the first unit structure is formed in the first region formed in the second impurity region, around the first region, and formed in the first impurity region. A second region and a third region formed around the second region and formed in the drift region are included, and the second unit structure is a fourth region formed in the drift region, the fourth region. The first unit includes a fifth region formed around the region and formed by the first impurity region, and a sixth region formed around the fifth region and formed by the second impurity region. The boundary region formed in the first impurity region between the structure and the second unit structure and connected to the second region and the fifth region is electrically separated from the drift region. The surface layer portion of the boundary region may include a connection region formed by the second impurity region and connecting the first region and the sixth region.

In the semiconductor device according to the embodiment of the present invention, the first region of the first unit structure includes a source region, the second region of the first unit structure includes a body region, and the first electrode. May include a source electrode connected to the source region, the third electrode may include a gate electrode facing the channel region formed in the body region.
In the semiconductor device according to the embodiment of the present invention, the second electrode may include a gate pad electrically connected to the gate electrode.

According to this configuration, an active cell including a second unit structure is formed in a region facing the gate pad. In other words, it is not necessary to omit the active cell from the area facing the gate pad. Therefore, the gate pad can prevent the chip area (cell area) from being sacrificed. As a result, the internal gate resistance of the transistor in the semiconductor device can be reduced.

In the semiconductor device according to the embodiment of the present invention, the second electrode may include a gate finger electrically connected to the gate electrode.
According to this configuration, an active cell containing the second unit structure is formed in the region facing the gate finger. In other words, it is not necessary to omit the active cell from the area facing the gate finger. Therefore, it is possible to suppress the sacrifice of the chip area (cell area) due to the increase in the number of gate fingers. As a result, the internal gate resistance of the transistor in the semiconductor device can be reduced.

In the semiconductor device according to the embodiment of the present invention, the drift region has an impurity concentration of 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 , and the first impurity region has an impurity concentration of 1 × 10 ¹⁵ . The second impurity region may have an impurity concentration of cm ^-3 to 1 × 10 ²⁰ cm ^-3 , and the second impurity region may have an impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²¹ cm ^-3 . ..
In the semiconductor device according to the embodiment of the present invention, the second impurity region of the second unit structure has a higher concentration of impurities of the first conductive type than the second impurity region of the first unit structure. You may.

The semiconductor device according to the embodiment of the present invention is on the first main surface so as to cover the first insulating layer formed between the third electrode and the first main surface and the third electrode. The third electrode includes the formed second insulating layer, the third electrode includes a polysilicon electrode formed on the first insulating layer, and the first electrode and the second electrode are on the second insulating layer. It may contain a metal electrode formed in.

In the semiconductor device according to the embodiment of the present invention, the polysilicon electrode may contain polysilicon containing impurities at an impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²¹ cm ^-3 .
The semiconductor device according to the embodiment of the present invention is formed in the first impurity region of the first unit structure and has a second conductive type impurity concentration higher than that of the first impurity region. It may further include a contact area connected to the first electrode.

In the semiconductor device according to the embodiment of the present invention, the contact region may have an impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²¹ cm ^-3 .
In the semiconductor device according to the embodiment of the present invention, at least one of the first unit structure and the second unit structure is a polygonal unit structure formed in a polygonal shape in a plan view or a line shape formed in a line shape. It may include a unit structure.

In the semiconductor device according to the embodiment of the present invention, at least one side of the polygonal unit structure and the line-shaped unit structure may be formed along the a-plane or the m-plane.
In the semiconductor device according to the embodiment of the present invention, at least one of the first unit structure and the second unit structure may be periodically arranged.
In the semiconductor device according to the embodiment of the present invention, the first unit structure and the second unit structure are arranged in a matrix in a plan view, and the first unit structure and the second unit structure are arranged with each other. The row direction and the column direction may be the same.

In the semiconductor device according to the embodiment of the present invention, the first unit structure and the second unit structure are arranged in a matrix in a plan view, and the first unit structure and the second unit structure are arranged with each other. , At least one of the row direction and the column direction may be deviated.
In the semiconductor device according to the embodiment of the present invention, the first conductive type may be n-type and the second conductive type may be p-type.
<Detailed Description of Embodiments of the Present Invention>
Next, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
[Overall structure of semiconductor device 1]
FIG. 1 is a schematic perspective view of the semiconductor device 1 according to the first embodiment of the present invention. FIG. 2 is a schematic plan view of the semiconductor device 1 according to the first embodiment of the present invention. Note that FIG. 2 shows the semiconductor device 1 in a state where the protective film 13 is omitted for the sake of clarity.

The semiconductor device 1 is, for example, a discrete transistor (for example, a discrete Si transistor, a discrete SiC transistor, or the like). In this embodiment, it is a semiconductor switching device including a SiC-MISFET (Metal Insulator Semiconductor Field Effect Transistor). The semiconductor device 1 has a first main surface 2 and a second main surface 3 on the opposite side of the first main surface 2, and is formed in a rectangular parallelepiped shape. The first main surface 2 and the second main surface 3 of the semiconductor device 1 are formed in a square shape (in this embodiment, a square shape) in a plan view. The first main surface 2 and the second main surface 3 of the semiconductor device 1 may be referred to as the front surface and the back surface of the semiconductor device 1, or the upper surface and the lower surface of the semiconductor device 1, respectively.

An electrode layer 4 is formed on the first main surface 2 of the semiconductor device 1. The electrode layer 4 may be formed of, for example, a metal layer such as Al (aluminum), AlCu (aluminum-copper alloy), or Cu (copper). In this embodiment, the electrode layer 4 may include a source electrode layer 5 as an example of the first electrode of the present invention and a gate electrode layer 6 as an example of the second electrode of the present invention.

The source electrode layer 5 may be formed, for example, in almost the entire area of the first main surface 2 of the semiconductor device 1. Specifically, the source electrode layer 5 is formed in a rectangular shape smaller than the first main surface 2 of the semiconductor device 1 in a plan view. An outer peripheral portion 7 having a predetermined width corresponding to the size difference between the two is formed between the peripheral edge of the source electrode layer 5 and the peripheral edge of the first main surface 2 of the semiconductor device 1.
The source electrode layer 5 is formed with a gap 8 from which a part of the source electrode layer 5 is removed. In this embodiment, the gap portion 8 is formed so as to extend from the peripheral edge of the source electrode layer 5 toward the inner region of the source electrode layer 5. Further, the gap portion 8 may include a first region 9 (pad region) in which the gate pad 11 described later is arranged and a second region 10 (finger region) in which the gate finger 12 is arranged. For example, the first region 9 may be formed in an island shape, and the second region 10 may be formed in a line shape having a width narrower than that of the first region 9. Further, the gap portion 8 may be formed, for example, by cutting out a part of the peripheral edge of the source electrode layer 5, and in that case, it may be referred to as a cutout portion.

The gate electrode layer 6 is formed on the first main surface 2 of the semiconductor device 1 in a region where the source electrode layer 5 is not formed. In this embodiment, the gate electrode layer 6 is formed on the outer peripheral portion 7 and the gap portion 8 of the first main surface 2 of the semiconductor device 1. The gate electrode layer 6 may include a gate pad 11 and a gate finger 12. The gate pad 11 is formed in a rectangular shape in a plan view, and is arranged in the first region 9 of the gap portion 8. The gate finger 12 is integrally formed with the gate pad 11, and is formed on a straight line extending from the gate pad 11 toward the second region 10 and the outer peripheral portion 7 of the gap portion 8. The gate finger 12 of the outer peripheral portion 7 extends along three of the four peripheral edges of the first main surface 2 of the semiconductor device 1 and surrounds the source electrode layer 5 from three sides.

A protective film 13 is formed on the first main surface 2 of the semiconductor device 1 so as to cover the electrode layer 4. The protective film 13 may be formed of, for example, an insulating film such as SiN (silicon nitride) or SiO ₂ (silicon oxide). The protective film 13 is formed with a first opening 15 that exposes a part of the source electrode layer 5 as a first pad 14, and a second opening 17 that exposes a part of the gate pad 11 as a second pad 16. There is. In this embodiment, a plurality of (a pair in this embodiment) first openings 15 are formed independently of each other with the second opening 17 interposed therebetween. As a result, the first pad 14 is formed at a plurality of locations on the source electrode layer 5, and the second pad 16 is formed at one location on the gate pad 11.

FIG. 3 is a diagram for explaining the arrangement pattern of the active cells 23 in the semiconductor device 1, and shows a plan view of the semiconductor device 1 in a state where the protective film 13 is omitted from FIGS. 1 and 2. However, the electrode layer 4 is shown by a broken line in order to clarify the positional relationship with the active cell 23.
As shown in FIG. 3, the semiconductor device 1 includes a semiconductor chip 18. The semiconductor chip 18 forms the outer shape of the semiconductor device 1, and is, for example, a structure in which a single crystal semiconductor material is formed in a chip shape (rectangular parallelepiped shape). The semiconductor chip 18 is made of SiC in this embodiment. The semiconductor chip 18 made of SiC is made of, for example, a hexagonal SiC single crystal. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal) -SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal and the like. In this embodiment, an example in which the semiconductor chip 18 is made of a 4H-SiC single crystal is shown, but other polytypes are not excluded.

The semiconductor chip 18 is continuous with the first main surface 19, the second main surface 20 on the opposite side of the first main surface 19 (see FIG. 10A, etc.), the first main surface 19, and the second main surface 20, and is a plane. It has first to fourth end faces 21A to 21D surrounding the first main surface 19 and the second main surface 20 in view.
The first main surface 19 is a device surface on which a functional device is formed. The second main surface 20 is a non-device surface on which a functional device is not formed. The first main surface 19 and the second main surface 20 are formed in a rectangular shape in a plan view (hereinafter, simply referred to as "plan view") viewed from their normal direction Z (third direction Z).

The first main surface 19 and the second main surface 20 face the c-plane of the SiC single crystal. The c-plane includes a silicon plane ((0001) plane) and a carbon plane ((000-1) plane) of the SiC single crystal. It is preferable that the first main surface 19 faces the silicon surface and the second main surface 20 faces the carbon surface. The first main surface 19 and the second main surface 20 may have an off angle inclined at a predetermined angle in the off direction with respect to the c surface. The off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may be greater than 0 ° and less than or equal to 10 °. The off angle is preferably 5 ° or less. The off angle is particularly preferably 2 ° to 4.5 °.

The first end surface 21A and the second end surface 21B extend in the first direction X along the first main surface 19 and face the second direction Y intersecting (specifically, orthogonal to) the first direction X. The third end surface 21C and the fourth end surface 21D extend in the second direction Y and face the first direction X.
In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction of the SiC single crystal. That is, the first end face 21A and the second end face 21B are formed by the a-plane of the SiC single crystal, and the third end face 21C and the fourth end face 21D are formed by the m-plane of the SiC single crystal.

A guard ring 22 is formed on the surface layer portion of the first main surface 19 of the semiconductor chip 18. The guard ring 22 is formed on the peripheral edge of the first main surface 19 of the semiconductor chip 18. The guard ring 22 is formed in an annular shape along the end faces 21A to 21D of the semiconductor chip 18. In this embodiment, the guard ring 22 is formed in a square ring along the four end faces 21A to 21D of the semiconductor chip 18 in a plan view. In the first main surface 19 of the semiconductor chip 18, the region surrounded by the guard ring 22 may be referred to as an active region 24 in which the active cells 23 are arranged, and the region in which the guard ring 22 is formed is the outer peripheral region 25. It may be called. The guard ring 22 may be referred to as a termination structure or a JTE (Junction Termination Extension) structure from the viewpoint of relaxing the voltage in the vicinity of the end faces 21A to 21D of the semiconductor chip 18.

Further, a plurality of active cells 23 are formed on the surface layer portion of the first main surface 19 of the semiconductor chip 18. The active cell 23 is a unit cell capable of conducting an electric current. The active cell 23 has, for example, a transistor gate structure, is electrically connected to at least a pair of first and second electrodes, and is controlled by the gate electrode to turn on the current between the first electrode and the second electrode. Control / off. In this embodiment, the active cell 23 is electrically connected to the source electrode layer 5 and the drain electrode layer 58 (described later), and the gate electrode 54 (described later) is controlled to turn on / off the current between the source and drain. Control.

The plurality of active cells 23 are arranged periodically (in this embodiment, in a matrix) in the active region 24 inside the guard ring 22, and are arranged in the source electrode layer 5 and the gate electrode layer 6 in the third direction Z, respectively. It is formed in the opposite region. In other words, the plurality of active cells 23 are formed in the region covered by the source electrode layer 5 and the gate electrode layer 6 in the third direction Z. The source electrode layer 5 and the gate electrode layer 6 are formed so as to straddle the plurality of active cells 23 and cover the plurality of active cells 23.
[Detailed structure of active cell 23]
FIG. 4 is an enlarged view of a main part of the portion surrounded by the alternate long and short dash line IV of FIG. FIG. 5 is a diagram for explaining the connection relationship of the first impurity region 28 (p-type region) of FIG. FIG. 6 is an enlarged view of a main part of the portion surrounded by the alternate long and short dash line VI of FIG. FIG. 7 is a diagram for explaining the connection relationship of the first impurity region 28 (p-type region) of FIG. FIG. 8 is an enlarged view of a main part of the portion surrounded by the alternate long and short dash line VIII of FIG. FIG. 9 is a diagram for explaining the connection relationship of the first impurity region 28 (p-type region) of FIG. FIG. 10A is a cross-sectional view showing a cross section of XA-XA of FIG. FIG. 10B is a cross-sectional view showing a cross section of XB-XB of FIG. 11A is a cross-sectional view showing a cross section of XIA-XIA of FIG. 11B is a cross-sectional view showing the XIB-XIB cross section of FIG. FIG. 12A is a cross-sectional view showing a cross section of XIIA-XIIA of FIG. FIG. 12B is a cross-sectional view showing a cross section of XIIB-XIIB of FIG.

More simply, FIGS. 4, 5, 10A and 10B are enlarged views of the main part near the boundary portion 43 between the gate pad 11 and the source electrode layer 5, and FIGS. 6, 7, 11A and 10B. 11B is an enlarged view of a main part near the end surface 21C of the semiconductor chip 18 including the gate finger 12, and FIGS. 8, 9, 12A and 12B show the boundary between the end of the gate finger 12 and the source electrode layer 5. It is an enlarged view of the main part in the vicinity of part 43. For clarity, the second impurity region 29 and the separation region 47 are hatched in FIGS. 4, 6 and 8, and the first impurity region 28 is hatched in FIGS. 5, 7 and 9. ing.

Next, the detailed structure of the active cell 23 will be described with reference to FIGS. 4 to 12B.
With reference to FIGS. 10A, 10B to 12A, 12B, the semiconductor chip 18 has a first main surface 19 and a second main surface 20 as described above. The semiconductor chip 18 includes an n-type drain region 26 formed on the surface layer portion of the second main surface 20. The drain region 26 is formed over the entire surface layer portion of the second main surface 20, and is exposed from the second main surface 20 and the first to fourth end surfaces 21A to 21D. The concentration of n-type impurities in the drain region 26 may be 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²¹ cm ^-3 . The thickness of the drain region 26 may be 1 μm to 500 μm. In this embodiment, the drain region 26 is formed of an n-type semiconductor substrate (SiC substrate). Further, the drain region 26 may be a first conductive type third impurity region using an ordinal number in the same manner as the first impurity region 28 and the second impurity region 29, which will be described later.

The semiconductor chip 18 includes an n-type drift region 27 formed on the surface layer portion of the first main surface 19 so as to be electrically connected to the drain region 26. The drift region 27 is directly connected to the drain region 26 in this embodiment. The drift region 27 has an n-type impurity concentration lower than that of the drain region 26. For example, the concentration of n-type impurities in the drift region 27 may be 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 . The drift region 27 is formed over the entire surface layer portion of the first main surface 19, and is exposed from the first main surface 19 and the first to fourth end faces 21A to 21D. The thickness of the drift region 27 is, for example, smaller than the thickness of the drain region 26. The thickness of the drift region 27 may be 5 μm to 50 μm. In this embodiment, the drift region 27 is formed by an n-type epitaxial layer (SiC epitaxial layer).

The semiconductor chip 18 includes a p-type first impurity region 28 formed on the surface layer portion of the first main surface 19. The first impurity region 28 is formed on the surface layer portion of the drift region 27 at a distance from the bottom portion of the drift region 27 (in this embodiment, the boundary portion with the drain region 26) toward the first main surface 19 side. That is, the first impurity region 28 faces the drain region 26 with a part of the drift region 27 interposed therebetween. The p-type impurity concentration in the first impurity region 28 may be 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ²⁰ cm ^-3 .

The semiconductor chip 18 includes an n-type second impurity region 29 formed on the surface layer portion of the first main surface 19. The second impurity region 29 is formed on the surface layer portion of the first impurity region 28 at a distance from the bottom portion of the first impurity region 28 (in this embodiment, the boundary portion with the drift region 27) to the first main surface 19 side. Has been done. That is, the second impurity region 29 faces the drift region 27 with a part of the first impurity region 28 interposed therebetween. The second impurity region 29 has an n-type impurity concentration higher than the n-type impurity concentration in the drift region 27. For example, the concentration of the n-type impurity in the second impurity region 29 may be 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²¹ cm ^-3 .

In this embodiment, the active cell 23 is formed by the drift region 27, the first impurity region 28, and the second impurity region 29.
The active cell 23 includes a first unit structure 30 and a second unit structure 31, as shown in FIGS. 4, 6 and 8. The first unit structure 30 is formed in the region of the first main surface 19 facing the source electrode layer 5 (the region of the first main surface 19 covered with the source electrode layer 5) in the third direction Z. On the other hand, the second unit structure 31 is formed in the region of the first main surface 19 facing the gate electrode layer 6 (the region of the first main surface 19 covered with the gate electrode layer 6). The first unit structure 30 and the second unit structure 31 have different planar patterns from each other.

More specifically, the first unit structure 30 is formed around the first source region 32 and the first source region 32 as an example of the first region of the present invention formed by the second impurity region 29, and the first unit structure 30 is formed. An example of a first body region 33 as an example of a second region of the present invention formed by an impurity region 28, and an example of a third region of the present invention formed around a first body region 33 and formed by a drift region 27. The first drift region 34 is included.

In this embodiment, each first unit structure 30 is formed in a rectangular shape in a plan view. In each first unit structure 30, the first source region 32 having a rectangular shape in a plan view, the first body region 33 having a square ring surrounding the first source region 32, and the first drift having a square ring surrounding the first body region 33. A region 34 is formed.
The first source region 32 is formed on the surface layer portion of the first body region 33 at a distance from the bottom portion of the first body region 33 (in this embodiment, the boundary portion with the drift region 27) toward the first main surface 19 side. Has been done. As a result, the first source region 32 is covered by the first body region 33 from below and from the side, and is electrically separated from the drift region 27.

The first body region 33 is formed on the surface layer portion of the first drift region 34 at a distance from the bottom portion of the first drift region 34 (in this embodiment, the boundary portion with the drain region 26) toward the first main surface 19 side. Has been done. As a result, the first body region 33 is covered by the first drift region 34 from below and from the side. In the first body region 33, the annular region surrounding the first source region 32 is the first channel region 35 in which the channel through which the carrier passes is formed.

Further, each first unit structure 30 may include a p-type contact region 36. As shown in FIGS. 10A, 11A and 12A, the contact region 36 passes from the first main surface 19 of the semiconductor chip 18 to the first source region 32 and is in contact with the first body region 33. The contact region 36 has a p-type impurity concentration higher than the p-type impurity concentration of the first body region 33. For example, the concentration of p-type impurities in the contact region 36 may be 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²¹ cm ^-3 .

Focusing on the first impurity region 28 with respect to the first unit structure 30, the first body regions 33 included in each first unit structure 30 are formed independently of each other, as shown in FIGS. 5, 7 and 9. Has been done. As a result, the plurality of first body regions 33 are arranged in a matrix with intervals from each other as a whole. The plurality of first body regions 33 are arranged side by side along the first direction X and the second direction Y, respectively. The grid-like region between the matrix-like first body regions 33 is the first drift region 34.

As shown in FIGS. 4, 6 and 8, the first unit structures 30 are arranged in a matrix in contact with each other in the region facing the source electrode layer 5. The first drift region 34 of the adjacent first unit structure 30 is integrated. That is, since the first drift region 34 is integrated on all four sides of the first unit structure 30 having a rectangular shape in a plan view, the first drift region 34 is formed in a grid pattern as a whole.

The second unit structure 31 was formed around the second drift region 37 and the second drift region 37 as an example of the fourth region of the present invention formed by the drift region 27, and was formed in the first impurity region 28. A second source as an example of a sixth region of the present invention formed around a second body region 38 as an example of a fifth region of the present invention and a second impurity region 29 formed around the second body region 38. Includes region 39.

In this embodiment, each second unit structure 31 is formed in a rectangular shape in a plan view. In each second unit structure 31, the second drift region 37 having a rectangular shape in a plan view, the second body region 38 having a square ring shape surrounding the second drift region 37, and the second source having a square ring shape surrounding the second body area 38. A region 39 is formed.
The second source region 39 is formed on the surface layer portion of the second body region 38 at a distance from the bottom portion of the second body region 38 (in this embodiment, the boundary portion with the drift region 27) toward the first main surface 19 side. Has been done. As a result, the second source region 39 is covered by the second body region 38 from below and from the sides and is electrically separated from the drift region 27.

The second body region 38 is formed on the surface layer portion of the second drift region 37 at a distance from the bottom portion of the second drift region 37 (in this embodiment, the boundary portion with the drain region 26) toward the first main surface 19 side. Has been done. As a result, the second body region 38 is covered by the second drift region 37 from below and from the side. In the second body region 38, the annular region surrounding the second drift region 37 is the second channel region 40 in which the channel through which the carrier passes is formed.

Focusing on the first impurity region 28 with respect to the second unit structure 31, the second body region 38 included in the second unit structure 31 is integrated as a whole, as shown in FIGS. 5, 7 and 9. It is formed in a grid pattern. The window portion of the grid-shaped second body region 38 (white portion in FIGS. 5, 7, and 9) is a second drift region 37 that is independent of each other in a plan view.
As shown in FIGS. 4, 6 and 8, the second unit structure 31 is arranged in a matrix in contact with each other in the region facing the gate electrode layer 6. The plurality of second unit structures 31 are arranged side by side along the first direction X and the second direction Y, respectively. The second source region 39 of the adjacent second unit structure 31 is integrated. That is, since the second source region 39 is integrated on the four sides of the second unit structure 31 having a rectangular shape in a plan view, the second source region 39 is formed in a grid pattern as a whole.

Further, in this embodiment, the matrix-shaped first unit structure 30 and the matrix-shaped second unit structure 31 have the same row direction and column direction. The coincidence in the row direction and the column direction is, for example, the linear portion in the first direction X and the second direction Y of the grid-like first drift region 34 (first unit structure 30) and the grid-like second source region 39 (the first unit structure 30). The straight line portion in the first direction X and the second direction Y of the second unit structure 31) may be defined by forming a continuous straight line portion, respectively.

The first body region 33 and the second body region 38 are both composed of the first impurity region 28, but may have the same p-type impurity concentration or have different p-type impurity concentrations. May be. Further, although the first source region 32 and the second source region 39 are both composed of the second impurity region 29, they may have the same n-type impurity concentration or have different n-type impurity concentrations. May be. Regarding the second impurity region 29, it is preferable that the second source region 39 has an n-type impurity concentration higher than that of the first source region 32.

The second source region 39 does not face the source electrode layer 5 in the third direction Z, and is formed at a position farther from the source electrode layer 5 than the first source region 32. Therefore, by making the concentration of n-type impurities in the second source region 39 higher than that in the first source region 32, the resistance of the current path to the source electrode layer 5 can be reduced.
As described above, in the first unit structure 30 and the second unit structure 31, the inner and outer regions of the annular first impurity region 28 (first body region 33 and second body region 38) are inverted from each other. ing. More specifically, as shown in FIGS. 4, 6 and 8, in the first unit structure 30, the second impurity region 29 is formed in the inner portion surrounded by the annular first impurity region 28. On the other hand, in the second unit structure 31, the second impurity region 29 is formed on the outer peripheral portion around the annular first impurity region 28. That is, the patterns of the second impurity region 29 are inverted between the first unit structure 30 and the second unit structure 31.

Further, in this embodiment, each first unit structure 30 formed in a rectangular shape in a plan view has at least one side 41 formed along the a-plane or the m-plane. Further, each second unit structure 31 formed in a rectangular shape in a plan view has at least one side 42 formed along the a-plane or the m-plane. In this embodiment, as shown in FIGS. 4, 6 and 8, each first unit structure 30 and each second unit structure 31 have a pair of sides 41, 42 parallel to the a-plane and parallel to the m-plane. It has a pair of sides 41 and 42. As a result, the current paths of the first unit structure 30 and the second unit structure 31 are formed along the a-plane or the m-plane, so that the resistance of the current paths can be reduced.

As shown in FIGS. 4, 6 and 8, the first unit structure 30 and the second unit structure 31 are located in a region facing the boundary portion 43 between the source electrode layer 5 and the gate electrode layer 6 in the third direction Z. It has a boundary portion 44. In this embodiment, the outer peripheral portion of the first unit structure 30 is the first drift region 34, and the outer peripheral portion of the second unit structure 31 is the second source region 39. Therefore, the first drift region 34 of the first unit structure 30 and the second source region 39 of the second unit structure 31 adjacent to each other can come into contact with each other at the boundary portion 44.

Therefore, in this embodiment, at the boundary portion 44 as the periphery of the second unit group 46 (for example, the group consisting of a plurality of periodically arranged second unit structures 31) composed of the plurality of second unit structures 31. A separation region 47 (also an example of the boundary region of the present invention) formed in the first impurity region 28 is formed. The separation region 47 is a boundary between the first unit group 45 consisting of a plurality of first unit structures 30 (for example, a group consisting of a plurality of periodically arranged first unit structures 30) and the second unit group 46. In the unit 44, the first drift region 34 and the second source region 39 are separated.

As shown in FIGS. 5, 7 and 9, the separation region 47 is integrated with the first body region 33 of the first unit structure 30 and the second body region 38 of the second unit structure 31. As a result, of the first body regions 33 included in the first unit group 45, the first body region 33 adjacent to the second unit group 46 is the second body of the second unit group 46 via the separation region 47. It is electrically connected to the region 38. Therefore, the potential of the second body region 38 of the second unit structure 31 is fixed at the same potential as the first body region 33 via the separation region 47. On the other hand, of the first body regions 33 included in the first unit group 45, the first body regions 33 separated from the second unit group 46 may be formed independently of each other.

Since the separation region 47 is formed, among the first body region 33 and the first drift region 34 included in the first unit group 45, the first body region 33 and the first drift region adjacent to the second unit group 46 are formed. 34 is partially missing. As a result, the first body region 33 and the first drift region 34 are formed in an open ring shape in which the first body region 33 and the first drift region 34 are opened toward the adjacent second unit structure 31 and the opposite side thereof is closed.

The semiconductor chip 18 further includes a connection region 48 formed by the second impurity region 29. The connection region 48 is formed on the surface layer portion of the separation region 47 at a distance from the bottom portion of the separation region 47 (in this embodiment, the boundary portion with the drift region 27) toward the first main surface 19 side. As a result, the connection region 48 is covered by the separation region 47 from below and from the sides and is electrically separated from the drift region 27. The connection area 48 is drawn from the second source area 39 of the second unit structure 31 toward the adjacent first unit structure 30, and is connected to the first source area 32 of the first unit structure 30.

For example, as shown in FIGS. 4 and 8, when the gate electrode layer 6 has a corner portion 51 where a first side 49 extending in the first direction X and a second side 50 extending in the second direction Y intersect. The connection region 48 may extend from the second source region 39 of the second unit structure 31 on the region facing the corner portion 51 along the two directions of the first direction X and the second direction Y. The concentration of n-type impurities in the connection region 48 may be the same as or different from the concentrations of the first source region 32 and the second source region 39.

Further, as shown in FIG. 4, the second unit structure 31 may not be formed in a part of the region facing the gate electrode layer 6. The region may be a solid region 52 formed by exposing the first impurity region 28 connected to the second body region 38 of the second unit structure 31 to one surface. For example, the second unit structure 31 is selectively formed in the region facing the peripheral edge portion of the gate electrode layer 6 forming the boundary portion 43 with the source electrode layer 5, and the region facing the inner portion of the gate electrode layer 6 is formed. The solid region 52 may be formed in the area. In this embodiment, the solid region 52 is formed in a region facing the gate pad 11 having a width wider than that of the gate finger 12.

Further, a p-type guard ring 22 is formed on the surface layer portion of the first main surface 19 of the semiconductor chip 18. The guard ring 22 is spaced from the bottom of the drift region 27 (the boundary with the drain region 26 in this embodiment) to the first main surface 19 side, and is spaced from the first impurity region 28 to the end faces 21A to 21D. It is formed on the surface layer portion of the drift region 27 with a gap. That is, the guard ring 22 faces the drain region 26 with a part of the drift region 27 interposed therebetween. The p-type impurity concentration of the guard ring 22 may be the same as the p-type impurity concentration of the first impurity region 28. That is, the p-type impurity concentration of the guard ring 22 may be 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ²⁰ cm ^-3 .

With reference to FIGS. 10A and 10B to 12A and 12B, a gate insulating film 53 as an example of the first insulating layer of the present invention is formed on the first main surface 19 of the semiconductor chip 18. The gate insulating film 53 may be referred to as a first insulating film based on the forming order of the insulating films formed on the first main surface 19. The gate insulating film 53 is made of silicon oxide (SiO ₂ ) in this embodiment, but may be silicon nitride (SiN), a high dielectric constant film (for example, hafnium oxide (HfO ₂ )) or the like.

The gate insulating film 53 is formed so as to cover at least the first channel region 35 in the first unit structure 30. The gate insulating film 53 is formed so as to cover at least the second channel region 40 in the second unit structure 31. In this embodiment, the gate insulating film 53 covers the entire second unit structure 31 so as not to expose the second source region 39 and the connection region 48. This makes it possible to prevent the second source region 39 and the connection region 48 covered with the gate electrode layer 6 from being electrically connected to the gate electrode layer 6. Further, the gate insulating film 53 may cover the solid region 52 as shown in FIG. 10A.

A gate electrode 54 as an example of the third electrode of the present invention is formed on the gate insulating film 53. The gate electrode 54 may be, for example, a polysilicon electrode. More specifically, the gate electrode 54 may be a polysilicon electrode containing impurities at an impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²¹ cm ^-3 .
In the first unit group 45, the gate electrode 54 is formed so as to face the first channel region 35 and the first drift region 34, and has a grid-like pattern as a whole. On the other hand, the second unit group 46 is formed so as to cover the entire second unit structure 31, and is a solid pattern (a pattern in which an opening or the like is not formed) that covers the second unit group 46 as a whole. It has a pattern that covers the entire 2 unit group 46). The gate structure of this solid pattern may cover the entire solid region 52.

An interlayer insulating film 55 as an example of the second insulating layer of the present invention is further formed on the first main surface 19 of the semiconductor chip 18 so as to cover the gate electrode 54. The interlayer insulating film 55 may be referred to as a second insulating film based on the forming order of the insulating film formed on the first main surface 19. The interlayer insulating film 55 is made of silicon oxide (SiO ₂ ) in this embodiment, but may be silicon nitride (SiN) or the like. In the interlayer insulating film 55 and the gate insulating film 53, the first contact hole 56 for exposing the first source region 32 and the contact region 36 of the first unit structure 30 and the gate electrode 54 on the second unit structure 31 are exposed. A second contact hole 57 is formed.

The source electrode layer 5 and the gate electrode layer 6 described above are formed on the interlayer insulating film 55. The source electrode layer 5 is connected to the first source region 32 and the contact region 36 of the first unit structure 30 via the first contact hole 56. The second source region 39 of the second unit structure 31 is connected to the source electrode layer 5 via the connection region 48 and the first source region 32. On the other hand, the gate electrode layer 6 is connected to the gate electrode 54 via the second contact hole 57.

The source electrode layer 5 and the gate electrode layer 6 are formed on the same layer as each other, that is, on the upper surface of the interlayer insulating film 55. As a result, the electrode layer connected to the second source region 39 is not interposed in the region facing the gate electrode layer 6 in the third direction Z. The potential of the second source region 39 is secured by the source electrode layer 5 via the first source region 32 and the connection region 48. As described above, since it is not necessary to form the source wiring for the active cell 23 (second unit structure 31) facing the gate electrode layer 6, it is possible to prevent the wiring structure in the third direction Z from becoming complicated. can.

A drain electrode layer 58 is formed on the second main surface 20 of the semiconductor chip 18. The drain electrode layer 58 is formed on the entire second main surface 20, and is a common electrode of the first unit structure 30 and the second unit structure 31. The drain electrode layer 58 may be formed of, for example, a metal layer such as Al (aluminum), AlCu (aluminum-copper alloy), or Cu (copper).
[Manufacturing method of semiconductor device 1]
13A to 13H are diagrams showing the manufacturing process of the semiconductor device 1 according to the first embodiment of the present invention in order of process. 13A to 13H are views corresponding to the above-mentioned FIG. 11A.

In manufacturing the semiconductor device 1 with reference to FIG. 13A, first, a semiconductor wafer 59 having a first wafer main surface 60 and a second wafer main surface 61 on the opposite side of the first wafer main surface 60 is prepared. Next, an n-type epitaxial layer 62 is formed on the first wafer main surface 60 of the semiconductor wafer 59. In the step of forming the epitaxial layer 62, SiC is epitaxially grown from the first wafer main surface 60 of the semiconductor wafer 59. The thickness of the epitaxial layer 62 may be 1 μm to 50 μm. As a result, the semiconductor wafer structure 63 including the semiconductor wafer 59 and the epitaxial layer 62 is formed. The semiconductor wafer structure 63 includes a first main surface and a second main surface.

The first main surface and the second main surface of the semiconductor wafer structure 63 correspond to the first main surface 19 and the second main surface 20 of the semiconductor chip 18, respectively. The thickness of the semiconductor wafer structure 63 may be 150 μm to 800 μm.
Next, with reference to FIG. 13B, a p-type first impurity region 28, a separation region 47, and a guard ring 22 are formed on the first main surface 19 of the semiconductor wafer structure 63. In the step of forming the first impurity region 28, the separation region 47, and the guard ring 22, p-type impurities are selectively selected on the surface layer portion of the first main surface 19 of the semiconductor wafer structure 63 via an ion implantation mask (not shown). Including the process of introduction. The first impurity region 28, the separation region 47 and the guard ring 22 are more specifically formed on the surface layer portion of the epitaxial layer 62. For example, when the p-type impurity concentrations of the first body region 33, the second body region 38, the separation region 47, and the guard ring 22 are different from each other, the steps of forming the first impurity region 28 and the guard ring 22 are performed. It may be performed multiple times with different dose amounts.

Next, with reference to FIG. 13C, an n-type second impurity region 29 and a connection region 48 are formed on the first main surface 19 of the semiconductor wafer structure 63. The step of forming the second impurity region 29 and the connection region 48 is a step of selectively introducing n-type impurities into the surface layer portion of the first main surface 19 of the semiconductor wafer structure 63 via an ion implantation mask (not shown). include. The second impurity region 29 and the connection region 48 are more specifically formed on the surface layer portion of the epitaxial layer 62. For example, when the n-type impurity concentrations of the first source region 32, the second source region 39, and the connection region 48 are made different from each other, the step of forming the second impurity region 29 is performed a plurality of times with different dose amounts. May be good.

Next, with reference to FIG. 13D, a p-type contact region 36 is formed on the first main surface 19 of the semiconductor wafer structure 63. The step of forming the contact region 36 includes a step of selectively introducing p-type impurities into the surface layer portion of the first main surface 19 of the semiconductor wafer structure 63 via an ion implantation mask (not shown). More specifically, the contact region 36 is formed on the surface layer portion of the epitaxial layer 62.

Next, with reference to FIG. 13E, the gate insulating film 53 is formed on the first main surface 19 of the semiconductor wafer structure 63. The gate insulating film 53 contains silicon oxide (SiO ₂ ). The gate insulating film 53 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (for example, a thermal oxidation treatment method).
Next, with reference to FIG. 13F, the gate electrode 54 is formed on the gate insulating film 53. The gate electrode 54 contains polysilicon containing impurities. The gate electrode 54 may be formed by depositing an electrode layer (polysilicon layer) by a CVD method and then patterning the electrode layer.

Next, with reference to FIG. 13G, an interlayer insulating film 55 is formed on the first main surface 19 of the semiconductor wafer structure 63 so as to cover the gate electrode 54. The interlayer insulating film 55 contains silicon oxide (SiO ₂ ). The interlayer insulating film 55 may be formed by a CVD method.
Next, with reference to FIG. 13H, a mask (not shown) having a predetermined pattern is formed on the interlayer insulating film 55. Next, an unnecessary portion of the interlayer insulating film 55 is removed by an etching method via the mask. As a result, the first contact hole 56 and the second contact hole 57 are formed in the interlayer insulating film 55. After the formation of the first contact hole 56 and the second contact hole 57, the mask is removed. Next, the electrode layer 4 (in this embodiment, the gate electrode layer 6 and the source electrode layer 5) is formed on the interlayer insulating film 55. The electrode layer 4 may be formed by a vapor deposition method, a sputtering method or a plating method.

Next, a protective film 13 (not shown in FIG. 13H) is formed on the first main surface 19 of the semiconductor wafer structure 63. The protective film 13 contains silicon nitride (SiN). The protective film 13 may be formed by a CVD method. Next, the protective film 13 is selectively removed to form the first opening 15 and the second opening 17 (both see FIG. 1). Next, the second main surface 20 of the semiconductor wafer structure 63 (second wafer main surface 61 of the semiconductor wafer 59) is ground. As a result, the semiconductor wafer structure 63 (semiconductor wafer 59) is thinned. Next, the drain electrode layer 58 is formed on the second main surface 20 of the semiconductor wafer structure 63. The drain electrode layer 58 may be formed by a vapor deposition method, a sputtering method or a plating method.

Next, a plurality of semiconductor devices 1 are cut out from the semiconductor wafer structure 63. The semiconductor device 1 is manufactured through the steps including the above.
[Action / effect of semiconductor device 1]
As described above, according to the semiconductor device 1, in addition to the region facing the source electrode layer 5 on the first main surface 19 of the semiconductor chip 18, the active cell 23 (second unit structure 31) also covers the region facing the gate electrode layer 6. Is formed. That is, it is not necessary to omit the active cell 23 from the region facing the gate electrode layer 6. Therefore, the gate electrode layer 6 can suppress the sacrifice of the chip area (cell area).

For example, in order to reduce the internal gate resistance, it is preferable to route the gate finger 12 made of a metal layer over the entire first main surface 19 of the semiconductor chip 18. However, if the active cell 23 is not formed in the region facing the gate finger 12, the active cell 23 may be sacrificed in the occupied region of the gate finger 12, and as a result, it may be difficult to reduce the internal gate resistance.

On the other hand, in this embodiment, since the active cell 23 can be formed in the region facing the gate electrode layer 6, the active cell can be formed on the entire first main surface 19 of the semiconductor chip 18 regardless of the pattern of the gate electrode layer 6. 23 can be effectively arranged. As a result, the internal gate resistance can be reduced in synergy with the change of the pattern of the gate electrode layer 6, such as increasing the number of gate fingers 12.

Moreover, in this embodiment, since the first source region 32 of the first unit structure 30 and the second source region 39 of the second unit structure 31 are connected, the current flowing through the second unit structure 31 is first. It can be easily taken out from the unit structure 30. As a result, the active cell 23 can be formed in the region facing the gate electrode layer 6.
FIG. 14 is a diagram showing the internal gate resistance and the on-resistance ratio of the simulation example. In this simulation, the internal gate resistance and on-resistance ratios were compared for structures A to D. In FIG. 14, the on-resistance ratio is shown as a relative value when the on-resistance ratio of the structure A is 1.

The structure A is a pattern in which the gate pad 11 is omitted in FIG. 3 and the active cell 23 is omitted from the region facing the gate electrode layer 6. That is, the structure A is a structure in which the gate voltage cannot be supplied from the gate pad 11 to the active cell 23.
The structure B is a structure in which the gate pad 11 is formed in the structure A. The structure C is a structure in which the active cell 23 is added to the entire region facing the gate electrode layer 6 in the structure B. The structure D is a structure in which the active cell 23 is omitted from a region other than the region facing the peripheral edge portion of the gate pad 11 in the region facing the gate pad 11 of the structure C to form a solid region 52.

Further, from FIG. 14, in the structure C and the structure D in which the active cell 23 is formed in the region facing the gate electrode layer 6, both the internal gate resistance and the on-resistance ratio can be reduced as compared with the structure A and the structure B. I understood.
[Second Embodiment]
FIG. 15 is a schematic plan view of the semiconductor device 1 according to the second embodiment of the present invention, and is an enlarged view of a main part corresponding to FIG.

In the first embodiment described above, the matrix-like first unit structure 30 and the matrix-like second unit structure 31 have the same row and column directions, but as shown in FIG. 15, at least each other. Either the row direction or the column direction may be offset. For example, a linear portion of the grid-like first drift region 34 (first unit structure 30) in the first direction X and a linear portion of the grid-like second source region 39 (second unit structure 31) in the first direction X. A step may be formed between the two and the like, and the two may be displaced by being discontinuous with each other.
[Transformation example of cell pattern]
16 to 18 are diagrams showing first to third modified examples of the first unit structure 30 and the second unit structure 31, respectively.

In the above-mentioned first embodiment, the first unit structure 30 and the second unit structure 31 are formed in a rectangular shape in a plan view, but may be formed in another polygonal shape or a line shape. The first unit structure 30 and the second unit structure 31 may have, for example, a triangular shape in a plan view as shown in FIG. 16, a hexagonal shape in a plan view as shown in FIG. 17, and the figure. As shown in 18, it may be in the shape of a plan view line.

Although one embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments.
For example, a configuration in which the conductive type of each semiconductor portion of the semiconductor device 1 is inverted may be adopted. For example, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.

Further, in the above-described embodiment, the MISFET is taken up as an example of the element structure of the semiconductor device 1, but the element structure of the semiconductor device 1 may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like. In the case of the IGBT, the n-type drain region 26 is the p-type collector region, the n-type first and second source regions 39 are the n-type first and second emitter regions, and the p-type first and second emitter regions. The second body region 38 may be a p-shaped first and second base region.

Further, in the above-described embodiment, the planar gate structure is taken up as an example of the gate structure of the transistor, but the gate structure may be, for example, a trench gate structure.
In addition, various design changes can be made within the scope of the matters described in the claims.

1: Semiconductor device 4: Electrode layer 5: Source electrode layer 6: Gate electrode layer 11: Gate pad 12: Gate finger 18: Semiconductor chip 19: First main surface 20: Second main surface 23: Active cell 26: Drain region 27: Drift region 28: 1st impurity region 29: 2nd impurity region 30: 1st unit structure 31: 2nd unit structure 32: 1st source region 33: 1st body region 34: 1st drift region 35: 1st Channel area 36: Contact area 37: Second drift area 38: Second body area 39: Second source area 40: Second channel area 41: One side 42: One side 47: Separation area 48: Connection area 53: Gate insulating film 54 : Gate electrode 55: Interlayer insulating film X: First direction Y: Second direction Z: Third direction

Claims (18)

A semiconductor chip having a first main surface and
The first electrode formed on the first main surface and
A second electrode formed on the first main surface and separated from the first electrode, and
The first unit structure formed in the region facing the first electrode in a plan view,
Including a second unit structure formed in a region facing the second electrode in a plan view.
Each of the first unit structure and the second unit structure
The first conductive type drift region formed on the surface layer of the first main surface and
The second conductive type first impurity region formed on the surface layer of the drift region and
The first conductive type second impurity region formed on the surface layer of the first impurity region and
A third electrode facing the channel region formed in the portion of the first impurity region between the drift region and the second impurity region is included.
The second impurity region of the first unit structure is electrically connected to the first electrode.
The second impurity region of the first unit structure and the second impurity region of the second unit structure are electrically connected to each other in a state of being electrically separated from the drift region by the first impurity region. It is a semiconductor device. The second impurity region of the second unit structure is formed on the outer peripheral portion of the second unit structure.
The second impurity region of the first unit structure is formed in the inner portion inside the first impurity region in the first unit structure.
A second conductive type separation region formed around the second unit structure and electrically separating the second impurity region of the second unit structure and the drift region of the first unit structure.
Claim 1 includes a first conductive type connection region drawn from the second impurity region of the second unit structure and connected to the second impurity region of the first unit structure via the separation region. The semiconductor device described in. The first unit structure is formed around a first region formed by the second impurity region, a second region formed around the first impurity region and formed by the first impurity region, and around the second region. Including a third region formed in the drift region.
The second unit structure is formed around a fourth region formed in the drift region, a fifth region formed around the fourth region, and formed around the first impurity region, and around the fifth region. And includes a sixth region formed by the second impurity region.
A boundary region formed in the first impurity region between the first unit structure and the second unit structure and connected to the second region and the fifth region.
Claim 1 includes a connection region formed by the second impurity region on the surface layer portion of the boundary region so as to be electrically separated from the drift region, and connecting the first region and the sixth region. The semiconductor device described in. The first region of the first unit structure includes a source region.
The second region of the first unit structure includes a body region.
The first electrode includes a source electrode connected to the source region.
The semiconductor device according to claim 3, wherein the third electrode includes a gate electrode formed in the body region and facing the channel region. The semiconductor device according to claim 4, wherein the second electrode includes a gate pad electrically connected to the gate electrode. The semiconductor device according to claim 4 or 5, wherein the second electrode includes a gate finger electrically connected to the gate electrode. The drift region has an impurity concentration of 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 .
The first impurity region has an impurity concentration of 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ²⁰ cm ^-3 .
The semiconductor device according to any one of claims 1 to 6, wherein the second impurity region has an impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²¹ cm ^-3 . One of claims 1 to 7, wherein the second impurity region of the second unit structure has a higher concentration of impurities of the first conductive type than the second impurity region of the first unit structure. The semiconductor device described in. A first insulating layer formed between the third electrode and the first main surface,
A second insulating layer formed on the first main surface so as to cover the third electrode is included.
The third electrode includes a polysilicon electrode formed on the first insulating layer.
The semiconductor device according to any one of claims 1 to 8, wherein the first electrode and the second electrode include a metal electrode formed on the second insulating layer. The semiconductor device according to claim 9, wherein the polysilicon electrode contains polysilicon containing impurities at an impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²¹ cm ^-3 . It is formed in the first impurity region of the first unit structure, has a second conductive type impurity concentration higher than that of the first impurity region, and further includes a contact region connected to the first electrode. , The semiconductor device according to any one of claims 1 to 10. The semiconductor device according to claim 11, wherein the contact region has an impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ²¹ cm ^-3 . Any one of claims 1 to 12, wherein at least one of the first unit structure and the second unit structure includes a polygonal unit structure formed in a polygonal shape or a line-shaped unit structure formed in a line shape in a plan view. The semiconductor device according to one item. The semiconductor device according to claim 13, wherein at least one side of the polygonal unit structure and the line-shaped unit structure is formed along the a-plane or the m-plane. The semiconductor device according to any one of claims 1 to 14, wherein at least one of the first unit structure and the second unit structure is periodically arranged. The first unit structure and the second unit structure are arranged in a matrix in a plan view.
The semiconductor device according to any one of claims 1 to 15, wherein the first unit structure and the second unit structure have the same row direction and column direction. The first unit structure and the second unit structure are arranged in a matrix in a plan view.
The semiconductor device according to any one of claims 1 to 15, wherein the first unit structure and the second unit structure are offset from each other by at least one of the row direction and the column direction. The semiconductor device according to any one of claims 1 to 17, wherein the first conductive type is n type and the second conductive type is p type.

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