JP2022011993A - Circuit reconfiguration device, control method, and program - Google Patents

Abstract

To provide a circuit reconfiguration device, a control method, and a program capable of efficiently utilizing a memory.SOLUTION: A circuit reconfiguration device includes: a selection section that selects a plurality of target areas, which are set to a frame on the basis of the preset number of pixels in row and column directions, in a preset order; and a control section that performs control for writing image data included in the selected target area into a buffer that is not used in image processing among a plurality of buffers set in a memory provided in the circuit reconfiguration device.SELECTED DRAWING: Figure 1

Description

The present invention relates to a circuit reconstructor having a memory, a control method, and a program.

In image processing, it is known that a device (circuit reconstructing device) capable of programmablely configuring a circuit is used when processing a frame at high speed. As a programmable device, for example, FPGA (Field Programmable Gate Array) and the like are known. However, such devices do not have enough memory to store all the image data corresponding to the frame.

Therefore, a technique using a line memory as disclosed in Patent Documents 1 and 2 has been proposed. In the technology using the line memory, instead of storing all the image data corresponding to the frame in the memory of the device and then performing the image processing as in the conventional case, the image data for the lines required for the image processing is sequentially stored in the device. Image processing is performed while storing in the memory of. Therefore, even if the memory of the device is small, the image processing can be smoothly executed.

Japanese Unexamined Patent Publication No. 2008-11395 Japanese Unexamined Patent Publication No. 2007-140643

However, when the resolution of the frame is high or when a plurality of image data are processed hierarchically, the number of pixels of the line increases, so that the capacity of the line memory must be increased accordingly. Then, the image data for the line cannot be stored in the memory of the small capacity of the device.

As one aspect, it is an object of the present invention to provide a circuit reconstructing device, a control method, and a program that efficiently utilize the memory provided in the circuit reconstructing device.

In order to achieve the above objectives, the circuit reconstructor in one aspect is
A selection unit that selects a plurality of target areas set in the frame based on the number of pixels in the preset row direction and column direction in a preset order.
A control unit that controls to write the image data included in the selected target area to a buffer that is not used in image processing among a plurality of buffers set in the memory provided in the circuit reconstruction device.
It is characterized by having.

Further, in order to achieve the above object, the control method for writing the image data to the memory provided in the circuit reconstructing device on one aspect is as follows.
A selection step that selects multiple target areas set in the frame based on the number of pixels in the preset row direction and column direction in a preset order.
A control step that controls to write the image data included in the selected target area to a buffer that is not used in image processing among a plurality of buffers set in the memory.
It is characterized by having.

Further, in order to achieve the above object, the program for writing the image data to the memory provided in the circuit reconstructing device on one aspect is
In the circuit reconstructor
A selection step that selects multiple target areas set in the frame based on the number of pixels in the preset row direction and column direction in a preset order.
A control step that controls to write the data included in the selected target area to a buffer that is not used in image processing among a plurality of buffers set in the memory.
Is characterized by executing.

As one aspect, the memory of the circuit reconstructor can be efficiently used.

FIG. 1 is a diagram for explaining the relationship between a frame and a local region. FIG. 2 is a diagram showing an example of a circuit reconstructing device. FIG. 3 is a diagram showing an example of a system having a circuit reconstructing device. FIG. 4 is a diagram for explaining the relationship between the local region and the target region. FIG. 5 is a diagram for explaining the timing of storage in the buffer. FIG. 6 is a diagram for explaining image processing when a local region straddles two buffers. FIG. 7 is a diagram for explaining an example of the operation of the circuit reconstructing device. FIG. 8 is a diagram for explaining an example of the operation of the circuit reconstructing device. FIG. 9 is a diagram showing an example of hardware having a circuit reconstructing device.

First, an outline will be given to facilitate understanding of the embodiments described below.
FIG. 1 is a diagram for explaining the relationship between a frame and a local region. The example of FIG. 1 is an example in which a plurality of local regions are set in the frame F and predetermined image processing is executed for the pixels included in the local region for each local region. The image processing is, for example, a filter processing.

The frame F is data corresponding to one screen imaged by the image pickup apparatus. The frame F shown in FIG. 1 has M × N pixels. M indicates the number of pixels in the row direction, and N indicates the number of pixels in the column direction.

The data corresponding to the frame F is stored in a memory provided outside the circuit reconstructing device. Hereinafter, this memory will be referred to as an external memory.

The local regions T are selected in the frame F in a predetermined order. In addition, predetermined image processing is executed on the selected local area.

The local area contains pixels necessary for image processing. In the example of FIG. 1, the local region T has m1 × n pixels required for image processing. m1 indicates the number of pixels in the row direction, and n indicates the number of pixels in the column direction. The number of pixels m1 and n are set to different values depending on the type of image processing.

In the selection of the local area, when the image processing for the target local area is completed, the target local area is selected next. For example, a region deviated from the target local region by a preset number of pixels is selected as the next target local region.

In the example of FIG. 1, the local region T1 is first selected as the target. Next, when the image processing for the local region T1 is completed, the local region T1'(the number of pixels of m1 × n) deviated from the local region T1 by the preset number of pixels step1 in the row direction (horizontal direction). Dashed line range) is selected. In this way, when the local region is selected by shifting the number of pixels by step 1 in the row direction and image processing is performed for each selected local region, the local region T2 on the opposite side of the local region T1 is reached.

When the local region T2 is selected, that is, when the final column (M column) of the frame F is reached, when the image processing for the local region T2 is completed, the next target is the column direction (vertical direction) from the local region T1. A preset local area T3 (dashed line / diagonal line range) at a position shifted by the number of pixels step2 is selected.

Next, when the image processing for the local region T3 is completed, the local region is selected by shifting the local region T3 by the number of pixels step1 in the row direction, and the image processing is performed for each selected local region. Then, when the local region T4 in the final column is reached, image processing is performed on the local region T4, and when the image processing on the local region T4 is completed, the pixels in the column direction from the local region T3 as the next target region. A local region that is off by a few steps 2 is selected.

In this way, the selection of the local region shown in FIG. 1 and the image processing are repeated. Finally, when the target local region T6 is selected and image processing is executed for the selected local region T6, the processing for the frame F in FIG. 1 is terminated.

However, when the local areas are sequentially selected as described above and the image processing is executed for the selected local areas, if the capacity of the image data corresponding to the frame F stored in the external memory is large, the circuit is re-used. It may not be possible to store all the image data corresponding to the frame F in the memory of the configuration device.

As a case where the capacity of the image data is large, for example, when handling a high-resolution image or a pyramid image, the capacity of the image data corresponding to the frame F becomes large.

Therefore, as described above, a method using a line memory has been proposed, but even in this method, when the number of pixels in the row direction of the frame F is large, the image data required for the memory of the circuit reconstructing device is stored. Sometimes you can't.

Further, as another method, a method has been proposed in which image data is sequentially acquired from the frame F by the amount corresponding to the local region, and image processing is executed on the acquired local region. However, since the image data corresponding to the local area must be frequently transferred from the external memory to the memory of the circuit reconstructing device, it causes a decrease in the image processing speed due to waiting for data transfer.

Through such a process, in the above-mentioned method, when the data capacity of the frame F is large, the inventor can efficiently execute the image processing even if a small memory provided in the circuit reconstructing device is used. We found the problem that we couldn't do it, and came to derive the means to solve the problem.

That is, the inventor has come to derive a means capable of efficiently executing image processing by using a small memory provided in the circuit reconstructing device even when the data capacity of the frame is large.

Hereinafter, embodiments will be described with reference to the drawings. In the drawings described below, elements having the same function or corresponding functions are designated by the same reference numerals, and the repeated description thereof may be omitted.

(Embodiment)
The configuration of the circuit reconstructing device 10 in the present embodiment will be described with reference to FIG. 2. FIG. 2 is a diagram showing an example of a circuit reconstructing device. The circuit reconstructor 10 is a programmable device such as an FPGA.

[Device configuration]
The circuit reconstruction device 10 shown in FIG. 2 can efficiently use the memory provided in the circuit reconstruction device 10. Further, as shown in FIG. 1, the circuit reconstructing device 10 includes a selection unit 11, a control unit 12, and a memory 13 (buffers 14-1 and 14-2).

The selection unit 11 selects the target area set in the frame based on the number of pixels in the row direction and the column direction set in advance in the preset order. The size of the target area is preset based on the type of image processing (the size of the local area used in the image processing). Further, when the type of image processing is changed, the size of the target area is automatically changed based on the changed type of image processing. Further, the selection unit 11 selects the next target area based on the position of the local area currently selected.

The control unit 12 uses the image data included in the selected target area for image processing among the plurality of buffers 14-1 and 14-2 set in the memory 13 provided in the circuit reconstruction device 10. Controls writing to no buffer.

As described above, in the present embodiment, the target area is sequentially selected and the image data of the selected target area is stored in the buffer 14-1 or 14-2 that is not used in the image processing. Even when the data capacity of the frame is large and the number of pixels for the line is large, the image processing can be efficiently executed by using the memory provided in the circuit reconstructing device 10.

Further, since the number of times of image data transfer from the external memory to the memory 13 of the circuit reconstructing device 10 can be suppressed, it is possible to prevent a decrease in the image processing speed due to waiting for data transfer.

[System configuration]
Subsequently, the configuration of the circuit reconstructing device 10 in the present embodiment will be described more specifically with reference to FIG. FIG. 3 is a diagram showing an example of a system having a circuit reconstructing device. The system shown in FIG. 3 has a circuit reconstructing device 10, an external memory 20, and an image pickup device 30.

The circuit reconstructing device 10 includes a selection unit 11, a control unit 12, memories 13 (buffers 14-1, 14-2), and a processing unit 15. The circuit reconstructor 10 is a programmable device such as an FPGA.

The external memory 20 is, for example, various RAMs (Random Access Memory) provided outside the circuit reconstructing device 10.

The image pickup device 30 is a camera or the like that captures a high-quality image. In addition to the image pickup device 30, an image processing device such as a recording device or a video device may be connected to the external memory 20. The high image quality is an image having a resolution such as HD (High Definition), Full-HD, 4K UHD (Ultra High Definition), 8K UHD, or the like.

The circuit reconstructing device will be described.
The circuit reconstructing device 10 has a circuit component. The circuit configuration unit is, for example, hardware having a part for implementing a circuit function, a wiring part between logic blocks, a switch matrix, an input / output block, a wiring part between an input / output block and a logic block, and the like.

The circuit configuration unit of the circuit reconstruction device 10 includes the selection unit 11, the control unit 12, and the processing unit 15 described above.

The selection unit 11 selects the target area to be selected next based on the position of the local area currently selected as described above.

The control unit 12 processes the image data included in the target area selected as described above into image processing among the plurality of buffers 14-1 and 14-2 set in the memory 13 provided in the circuit reconstructing device 10. Controls writing to a buffer that is not used in. Further, the control unit 12 acquires image data stored in the external memory 20 so that the addresses of the target areas are continuous from the external memory 20.

The processing unit 15 performs image processing on the currently selected local region using buffer 14-1, buffer 14-2, or both.

Note that the processing unit 15 executes image processing using the image data of the buffer used in the image processing even while writing to the buffer not used in the image processing.

Further, when the local region including the pixel to be processed for image processing extends (divided) over the two buffers, the processing unit 15 uses the image data corresponding to the local regions of the two buffers to image. Do the processing.

The selection of the target area will be specifically described with reference to FIG.
FIG. 4 is a diagram for explaining the relationship between the local region and the target region. The example of FIG. 4 describes a method of effectively selecting the target region R when performing image processing on the local region T described with reference to FIG. 1.

The target area R is an area set in the frame F based on the preset number of pixels in the row direction and the column direction. In the example of FIG. 4, the target area R has m2 × n pixels. m2 indicates the number of pixels in the row direction (grid width), and n indicates the number of pixels in the column direction (line width).

Further, the values of the number of pixels m2 and n are changed according to, for example, the type of image processing, the specifications of the memory interface, and the like. For example, since the size of the local region changes depending on the type of image processing, the values of the number of pixels m2 and n are changed according to the size of the local region. Further, since the bit width, burst length, data transfer speed, etc. change depending on the specifications of the memory interface between the external memory 20 and the memory 13, the values of the number of pixels m2 and n are changed according to the specifications of the memory interface. .. However, the number of pixels m2 is a value larger than the number of pixels m1 and is set in consideration of the size (capacity) that can be allocated to the memory 13.

The following methods (1) and (2) will be specifically described for setting the target area.
In the method (1), the control unit 12 has the number of bits of the data width of the memory interface, the maximum burst transfer length, the clock frequency of the bus, which are stored in advance in the storage unit provided in the circuit reconstruction device 10. The number of pixels m2 and n in the target area are calculated by using the resolution information related to the local image.

In the method (1), when the number of pixels m2 and n of the target area are calculated, (1-A) the number of vertical pixels n of the target area and the number h of the vertical pixels of the local image are the same (n = h). ) And (1-B) the case where the number of vertical pixels n in the target area and the number h in the vertical pixels of the local image are different (n ≠ h) is assumed.

(1-A) A case where the number of vertical pixels n of the target area and the number of vertical pixels h of the local image are the same (n = h) will be described. The processing unit 15 has a minimum value N0_min of an integer of the number N0 in the horizontal direction of the local image in the target area satisfying the equation 1, and a minimum value N1_min of an integer of the number of burst transfers N1 for transferring the image data for the target area. Is calculated.

(Number 1)
(W + step_w × N0) × bpp = bw × len × N1
w: Number of pixels next to the local image step_w: Number of pixels next to the step of image processing N0: Number of pixels in the horizontal direction of the local image in the target area bpp: Data amount of one pixel (bits)
bw: Number of bits in the data width of the memory interface len: Maximum burst transfer length (times)
N1: Number of burst transfers required to transfer image data for the target area

Next, using the number 2, the number of pixels m2 beside the target area is calculated.

(Number 2)
m2 = w + step_w × N0_min
m2: Number of pixels horizontal to the target area n: Number of vertical pixels in the target area N0_min: Minimum value of the integer of N0 N1_min: Minimum value of the integer of N1 h: Number of vertical pixels of the local image step_h: Step of image processing Number of vertical pixels

(1-B) When the relationship between the number of vertical pixels n in the target area and the number h in the vertical pixels of the local image is the number 3 (n ≠ h), the processing unit 15 uses the numbers 3 and 4. Then, the number of pixels m2 in the horizontal direction of the target area and the number of pixels n in the vertical direction of the target area are calculated.

(Number 3)
n = h + step_h × N2
step_h: Number of vertical pixels of the step of image processing N2: Number of pixels in the vertical direction of the local image in the target area

(Number 4)
(W + step_w × N0) × (h + step_h × N2) × bpp
= Bw x len x N1

However, when the setting is made so that the relationship shown in the numbers 3 and 4 is established, N0, N1 and N2 cannot be uniquely determined. Therefore, for example, the ratio of N0 and N2 (N0 / N2) is used as a constraint condition. .. Alternatively, N2 is determined first, and then N0 and N1 are calculated.

In the method (2), the number of pixels m2 horizontal to the target area and the number n vertical pixels n of the target area so that data transfer from the external memory 20 to the memory 13 can be efficiently executed are calculated.

Specifically, the control unit 12 has the number of bits of the data width of the memory interface, the maximum burst transfer length, the clock frequency of the bus, which are stored in advance in the storage unit provided in the circuit reconstruction device 10. With reference to the constraint condition between N0, N1 and N2 included in 4), the number of pixels m2 and n in the target area is calculated.

Further, the control unit 12 has a function of counting the number of clocks required for processing the entire frame F and a function of temporarily storing the counted value, and is engaged in the processing of the frame. It has a function to compare the count value with the count value applied to the processing in the previous frame. Further, the control unit 12 applies the change to N0, N1 and N2 with reference to the function of making changes to N0, N1 and N2 while satisfying (Equation 4) and the comparison result of the count values described above. It has a function to judge whether or not.

That is, the control unit 12 sets N0, N1 and N2 set in a certain frame number F0 to N0_0, N1_0 and N2_0, and sets the count value at this time to COUNT_0. Further, before starting the processing of the next frame number F1, N0, N1 and N2 are changed to N0_1, N1_1 and N2_1.

Further, when the count value of the number of clocks applied to the processing of the frame number F1 is COUNT_1, the control unit 12 refers to N0_1, N1-1, and N2_1 when the count value COUNT_1 is smaller than the count value COUNT_1 (COUNT_1 <COUNT_1). As a result, the difference Δ (= N0_1-N0_0) between N0_1 and N0_1 is added to N0_1 (N0_1 + Δ), and N0_1 + Δ is set to N0_2.

After that, N1_2 and N2_2 are calculated based on NO_2 and the above-mentioned constraints, and used as new parameters. Subsequently, the processing of the next frame F2 is executed using the new parameters N1_2 and N2_2, and the number of clocks is counted again.

On the other hand, when the count value COUNT_1 is greater than or equal to the count value COUNT_1 (COUNT_1 ≧ COUNT_1), N0_0, N1_0, and N2_0 are used as a reference, and the value obtained by subtracting the difference Δ from N0_0 (= N0_0-Δ) is defined as N0_2. Then, N1_2 and N2_2 are calculated based on N0_2 and the constraint conditions, and the number of pixels m2 horizontal to the target area and the number n vertical pixels n of the target area are calculated by (Equation 2) and (Equation 3).

Here, to efficiently execute data transfer means, for example, (2-A) shortening the processing time required for data transfer (increasing the processing speed), or (2-B) data transfer from image input to image. For example, the image processing time until the processing result is obtained is shortened (the delay is reduced).

(2-A) The processing time required for data transfer can be shortened, or (2-B) the image processing time can be shortened by changing the above-mentioned clock number counting method. The method (2) described above is a counting method for the purpose of increasing the processing speed (2-A).

Further, when the purpose is to reduce the delay (2-B), the condition for counting the number of clocks is from the start of data transfer in the first target area of the frame to the completion of processing for the first local image.

In the example of FIG. 8 described later, in (2-A), the processing time (= number of clocks) from “Start” to “End” is measured, whereas in (2-B), steps B1 to B2 are measured. Measure the processing time up to.

The above-mentioned processing time or image processing time may be set in advance in the storage unit so that the processing time or image processing time can be changed in the wake of an external event during operation.

Next, the selection of the target area will be described.
First, since the processing unit 15 executes image processing on the local region T1, the selection unit 11 selects the target region R11 shown in FIG. Then, the control unit 12 stores the image data of the target area R11 in the buffer 14-1 which has not been used in the image processing yet.

FIG. 5 is a diagram for explaining the timing of storage in the buffer. Specifically, when image processing is started for the frame F, the selection unit 11 selects the target area R11 at the data acquisition timing t1 as shown in FIG. 5, and the control unit 12 selects the image data of the target area R11. Store in buffer 14-1.

Next, while the processing unit 15 is performing image processing on the local area T included in the target area R11, the selection unit 11 selects the target area R21, and the control unit 12 selects the image data of the target area R21. Is stored in buffer 14-2, which is not used in image processing. That is, at the data acquisition timing t2 of FIG. 5, the image data of the target area R21 is stored in the buffer 14-2.

In this way, when image processing is sequentially executed in the row direction for the local area T, the selection unit 11 selects the target area R51 at the data acquisition timing t5 in FIG. 5, and the control unit 12 selects the target area R51. Image data is stored in the buffer 14-1.

Next, during the period in which the processing unit 15 is performing image processing on the local area T included in the target area R51, at the data acquisition timing t6 of FIG. 5, the selection unit 11 pixels in the column direction from the target area R11. The target area R12 deviated by several steps 2 is selected, and the image data of the target area R12 selected by the control unit 12 is stored in the buffer 14-2 not used in the image processing.

As described above, by repeating the process of storing the selected target area R in the buffers 14-1 and 14-2 not used in the image processing, the processing unit 15 smoothly continues the image processing for the local area T. be able to.

A case where the local region T to be image-processed straddles the two buffers 14-1 and 14-2 will be described with reference to FIG. FIG. 6 is a diagram for explaining processing when a local area straddles two buffers.

In the example of FIG. 6, when the image data of the target area R31 is stored in the buffer 14-1 and the image data of the target area R21 is stored in the buffer 14-2, the image data of the local area T7 is two. The case where the buffers 14-1 and 14-2 are straddled is shown.

In such a case, the processing unit 15 acquires the divided region T7-1 of the local region T7 of the buffer 14-2 and the divided region T7-2 of the buffer 14-1, and executes image processing on the local region T7. do.

[Device operation]
Next, the operation of the circuit reconstructing device according to the embodiment of the present invention will be described with reference to FIG. 7. 7 and 8 are diagrams for explaining an example of the operation of the circuit reconstructing device. In the following description, the drawings will be referred to as appropriate. Further, in the present embodiment, the method of writing image data is implemented by operating the circuit reconstructing device. Therefore, the description of the method of writing the image data in the present embodiment is replaced with the following description of the operation of the circuit reconstructing device.

First, the operations of the selection unit 11 and the control unit 12 will be described with reference to FIG. 7. The selection unit 11 selects the target area based on the position of the local area in which the image processing is currently executed (step A1). As described in the examples of FIGS. 4 and 5, the selection unit 11 selects the target area so that the image processing for the local area T is not interrupted.

Next, the control unit 12 selects a buffer for which image processing has been completed for the local area stored in the buffers 14-1 and 14-2 (step A2). After that, the control unit 12 stores the image data of the selected target area in the selected buffer 14-1 or buffer 14-2 (step A3).

Specifically, in step A2, after the image processing using the image data of the buffer 14-2 is completed, the processing unit 15 uses only the image data of the target area stored in the buffer 14-1 to be used. When image processing is performed on the local area, in step A3, the control unit 12 stores the image data of the selected target area in the buffer 14-2.

Further, in step A2, after the image processing using the image data of the buffer 14-1 is completed, the processing unit 15 uses only the image data of the target area stored in the buffer 14-2 for the local area. When image processing is performed, in step A3, the control unit 12 stores the image data of the selected target area in the buffer 14-1.

Further, in step A2, when the target local area is stored straddling the buffer 14-1 and the buffer 14-2, in the step A3, the control unit 12 sends the control unit 12 to both the buffer 14-1 and the buffer 14-2. The processing unit 15 determines from the position (coordinates) of the local area being processed that the data being processed still exists, and controls so that the image data is not stored in the buffer 14.

Next, when all the target areas set in the target frame are selected by the control unit 12 (step A4: Yes), the processing for the target frame is terminated. Next, if there is a target frame, the processes of steps A1 to A4 are executed again for that frame. If the control unit 12 has not selected all the target areas set in the frame (step A4: No), the process proceeds to step A1 and the next target area is selected.

Next, the operation of the processing unit 15 will be described with reference to FIG. The processing unit 15 acquires image data corresponding to the local region from the buffer 14-1 or 14-2 (step B1). Next, the processing unit 15 executes image processing on the acquired local area (step B2).

Next, when the image processing is executed for all the local regions in the target frame (step B3: Yes), the processing unit 15 ends the processing for the target frame. Next, if there is a target frame, the processes of steps B1 to B3 are executed again for that frame. If the processing unit 15 has not selected all the local areas set in the frame (step B3: No), the process proceeds to the processing of step B1 and the next local area is selected.

The processes of steps A1 to A4 shown in FIG. 7 and the processes of steps B1 to B3 shown in FIG. 8 operate in conjunction with each other.

[Effect of this embodiment]
As described above, according to the present embodiment, the target area is sequentially selected and the image data of the selected target area is stored in the buffer 14-1 or 14-2 that is not used in the image processing. Even when the data capacity of the frame is large and the number of pixels for the line is large, the image processing can be efficiently executed by using the memory provided in the circuit reconstructing device 10.

Further, since the number of times of image data transfer from the external memory to the memory 13 of the circuit reconstructing device 10 can be suppressed, it is possible to prevent a decrease in the image processing speed due to waiting for data transfer.

When image data corresponding to a frame is continuously stored in the external memory 20 for a line, when reading with a specified address, address jumps frequently occur and a large overhead occurs, resulting in image processing performance. Decreases.

Therefore, when the image data is stored in the external memory 20, the control unit 12 stores the images so that the addresses of the target areas are continuous. By doing so, it is possible to prevent a large overhead from occurring, so that the processing performance of image processing can be improved.

[program]
The program according to the embodiment of the present invention may be any program that causes the circuit reconstructor to execute steps A1 to A4 shown in FIG. 7 and steps B1 to B3 shown in FIG. By installing and executing this program in the circuit reconstructing device, the circuit reconstructing device and the image data writing method in the present embodiment can be realized. In this case, a programmable device such as an FPGA of the circuit reconstructing device functions as a selection unit 11, a control unit 12, and a processing unit 15 to perform processing.

Further, the program in the present embodiment may be constructed and executed by a plurality of circuit reconstructing devices. In this case, for example, each circuit reconstructing device may function as any of the selection unit 11, the control unit 12, and the processing unit 15, respectively.

[Physical configuration]
FIG. 9 is a diagram showing an example of hardware having a circuit reconstructing device. As shown in FIG. 9, it has a circuit reconstructing device 10, a peripheral circuit 120, and a storage unit 130. The peripheral circuit 120 is a circuit having, for example, a GPU (Graphics Processing Unit), an FPGA, a communication device, or the like in addition to or in place of the CPU (Central Processing Unit).

The storage unit 130 is typically a non-volatile storage device such as a ROM (Read Only Memory). Further, the program in the present embodiment may be provided in a state of being stored in a computer-readable recording medium 140. The program in the present embodiment may be distributed on the Internet connected via a communication interface. Specific examples of the recording medium 140 include a general-purpose semiconductor storage device such as CF (Compact Flash (registered trademark)) and SD (Secure Digital), a magnetic recording medium such as a flexible disk, or a CD-. Examples include optical recording media such as ROM (Compact Disk Read Only Memory).

The circuit reconstructing device 10 in the present embodiment can also be realized by using the hardware corresponding to each part instead of the computer in which the program is installed. Further, the circuit reconstructing device 10 may be partially realized by a program and the rest may be realized by hardware.

[Additional Notes]
Further, the following additional notes will be disclosed with respect to the above embodiments. A part or all of the above-described embodiments can be expressed by the following descriptions (Appendix 1) to (Appendix 15), but the description is not limited to the following.

(Appendix 1)
A selection unit that selects multiple target areas set in the frame based on the number of pixels in the preset row direction and column direction in the preset order.
A control unit that controls to write the image data included in the selected target area to a buffer that is not used in image processing among a plurality of buffers set in the memory provided in the circuit reconstruction device.
Circuit reconstructor with.

(Appendix 2)
The circuit reconstructing device according to Appendix 1.
A processing unit that performs image processing using the image data of the buffer used in image processing even while writing to the buffer that is not used in image processing.
Circuit reconstructor with.

(Appendix 3)
The circuit reconstructing device according to Appendix 2.
When the local area including the pixel to be processed for image processing is divided into the two buffers, the processing unit is a circuit reconstructing device that performs image processing using the two buffers.

(Appendix 4)
The circuit reconstructing device according to Appendix 3.
A circuit reconstructing device that changes the size of the target area according to the size of the local area.

(Appendix 5)
The circuit reconstructing device according to Appendix 1.
The control unit is a circuit reconstructing device that acquires the image data stored in an external memory provided outside the circuit reconstructing device so that the addresses of the target areas are continuous from the external memory.

(Appendix 6)
It is a control method for writing image data to a memory provided in a circuit reconstruction device.
A selection step that selects multiple target areas set in the frame based on the number of pixels in the preset row and column directions in a preset order.
A control step that controls to write the data included in the selected target area to a buffer that is not used in image processing among a plurality of buffers set in the memory.
Control method having.

(Appendix 7)
The control method described in Appendix 6
A control method having a processing step that performs image processing using the image data of the buffer used in image processing even while writing to the buffer that is not used in image processing.

(Appendix 8)
The control method described in Appendix 7.
A control method for performing image processing using the two buffers when the local region including the pixel to be processed in the image processing is divided into the two buffers in the processing step.

(Appendix 9)
The control method according to Appendix 8.
A control method in which the size of the target area is changed according to the size of the local area.

(Appendix 10)
The control method described in Appendix 6
A control method for acquiring image data stored in an external memory provided outside the circuit reconstruction apparatus so that the addresses of the target areas are continuous in the control step.

(Appendix 11)
It is a program for writing image data to the memory provided in the circuit reconstructor.
In the circuit reconstructor
A selection step that selects multiple target areas set in the frame based on the number of pixels in the preset row direction and column direction in a preset order.
A control step that controls to write the data included in the selected target area to a buffer that is not used in image processing among a plurality of buffers set in the memory.
A program that contains instructions to execute.

(Appendix 12)
The program described in Appendix 11
The program is applied to the circuit reconstructor.
A program including an instruction to execute a processing step that performs image processing using the image data of the buffer used in image processing even while writing to the buffer that is not used in image processing.

(Appendix 13)
The program described in Appendix 12
In the processing step, when the local area including the pixel to be processed in the image processing is divided into the two buffers, a program for executing the image processing using the two buffers.

(Appendix 14)
The program described in Appendix 13
A program that changes the size of the target area according to the size of the local area.

(Appendix 15)
The program described in Appendix 11
In the control step, a program for acquiring image data stored in an external memory provided outside the circuit reconstructing device so that the addresses of the target areas are continuous from the external memory.

Although the invention of the present application has been described above with reference to the embodiments, the invention of the present application is not limited to the above-described embodiment. Various changes that can be understood by those skilled in the art can be made within the scope of the present invention in terms of the configuration and details of the present invention.

As described above, according to the present invention, the memory of the circuit reconstructing device can be efficiently used. The present invention is useful in the field of using a circuit reconstructor.

10 Circuit reconfiguration device 11 Selection unit 12 Control unit 13 Memory 14-1, 14-2 Buffer 15 Processing unit 20 External memory 30 Imaging device 110 Circuit configuration unit 120 Peripheral circuit 130 Storage unit 140 Recording medium

Claims (10)

A selection means that selects a plurality of target areas set in a frame based on the number of pixels in the preset row direction and column direction in a preset order.
A control means for controlling the image data included in the selected target area to be written to a buffer not used in image processing among a plurality of buffers set in a memory provided in the circuit reconstruction apparatus.
Circuit reconstructor with. The circuit reconstructing device according to claim 1.
A processing means that performs image processing using the image data of the buffer used in image processing even while writing to the buffer that is not used in image processing.
Circuit reconstructor with. The circuit reconstructing device according to claim 2.
When the local area including the pixel to be processed for image processing is divided into the two buffers, the processing means is a circuit reconstructing device that performs image processing using the two buffers. The circuit reconstructing device according to claim 1.
The control means is a circuit reconstructing device that acquires image data stored in an external memory provided outside the circuit reconstructing device so that the addresses of the target areas are continuous from the external memory. It is a control method for writing image data to a memory provided in a circuit reconstruction device.
Select multiple target areas set in the frame based on the number of pixels in the preset row direction and column direction in the preset order.
A control method for controlling to write data included in the selected target area to a buffer not used in image processing among a plurality of buffers set in the memory. The control method according to claim 5.
A control method that performs image processing using the image data of the buffer used in image processing even while writing to the buffer that is not used in image processing. The control method according to claim 6.
A control method for performing image processing using the data in the two buffers when the local area including the pixel to be processed is divided into the two buffers in the image processing. It is a program for writing image data to the memory provided in the circuit reconstructor.
In the circuit reconstructor
Select multiple target areas set in the frame based on the number of pixels in the preset row direction and column direction in the preset order.
A program including an instruction for executing a process of controlling to write data contained in the selected target area to a buffer not used in image processing among a plurality of buffers set in the memory. The program according to claim 8.
The program is applied to the circuit reconstructor.
A program that includes an instruction to execute image processing by referring to the image data in the buffer used in image processing even while writing to the buffer that is not used in image processing. The program according to claim 9.
The program is applied to the circuit reconstructor.
A program including an instruction to execute image processing using the two buffers when the local area including the pixel to be processed is divided into the two buffers in the image processing.

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