JP2022003680A - Method, apparatus and electronic device for testing memory of chip, computer-readable storage medium and computer program - Google Patents

Abstract

To provide: a method, an apparatus and an electronic device for efficiently and flexibly testing a memory of a chip; a computer readable storage medium; and computer program.SOLUTION: A memory test process of a chip that includes a plurality of operation modules each of which includes at least one operation unit that includes at least one memory. The memory test process includes: a step 210 of generating a first test vector for a first operation module of the at least one operation module; and a step 220 of performing a memory test on the first operation module by using the generated first test vector independent of other operation modules of the at least one operation modules, the other operation modules being different from the first operation module.SELECTED DRAWING: Figure 2

Description

The present disclosure relates primarily to the field of chips, and more specifically to memory testing methods and devices for chips, electronic devices, computer-readable storage media and computer programs.

With the rapid development of artificial intelligence, the capabilities and computing power of artificial intelligence (AI) chips (eg, system-on-chip SoCs) have become more and more powerful, resulting in a rapid increase in the scale and complexity of AI chip design. ing. A large number of memories such as static random memory (SRAM), dynamic random memory (DRAM), cache (CACHE), registers and flash memory (FLASH (registered trademark)) are embedded in the existing AI chip. .. These memories are located at various positions on the chip and support various logical operations.

In the chip manufacturing process, some memory on the chip cannot operate correctly due to many causes such as process flow and design. Therefore, before shipping from the factory, the validity of the memory of the chip is usually tested by testing the memory of the chip by the memory built-in scan test MBIST (Memory Built-In-Scan-Test), and the bad memory is detected. Replace or repair.

The present disclosure provides memory testing means for chips.

The first aspect of the present disclosure is a memory test method for a chip, wherein the chip comprises a plurality of arithmetic modules including at least one arithmetic unit including at least one memory.
A step of generating a first test vector for the first arithmetic module of at least one arithmetic module,
A step of executing a memory test on the first arithmetic module using the generated first test vector independently of other arithmetic modules different from the first arithmetic module among at least one arithmetic module. Provides a memory testing method for the chip, including.

A second aspect of the present disclosure provides a memory test apparatus for a chip comprising a plurality of arithmetic modules including at least one arithmetic unit including at least one memory. The device is
A first test vector generation module configured to generate a first test vector for the first calculation module of at least one calculation module.
To execute a memory test on the first arithmetic module using the generated first test vector independently of other arithmetic modules different from the first arithmetic module among at least one arithmetic module. Includes a first memory test module to be configured.

In the third aspect of the present disclosure, it is an electronic device.
With one or more processors
Provided is an electronic device comprising a memory for storing one or more programs that causes the electronic device to perform the method according to the first aspect of the present disclosure when executed by one or more processors.

A fourth aspect of the present disclosure provides a computer-readable storage medium in which a computer program that realizes the method according to the first aspect of the present disclosure is stored when executed by a processor.
A fifth aspect of the present disclosure provides a computer program and realizes the method according to the first aspect of the present disclosure when the computer program is executed by a processor.

The technique according to the present application solves the problem of a conventional memory testing means (eg, MBIST) for a chip that is inflexible and time consuming to meet the requirements of designing and manufacturing AI chips. According to the present disclosure, the flexibility of the memory test of the AI chip is improved, the pressure on the memory test cycle and time of the chip is reduced, the time required to perform the memory test is shortened, and the chip is manufactured. And provide memory testing means for improved chips that can reduce production costs.

It should be noted that the content described in this section is not intended to identify key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the disclosure are facilitated by the following specification.

Shown is a schematic diagram of an exemplary environment in which a memory test means for a chip according to a plurality of embodiments of the present disclosure is realized. A flowchart of a memory test process for a chip according to a plurality of embodiments of the present disclosure is shown. FIG. 3 shows a schematic diagram of another exemplary environment in which the memory testing means for the chip according to the plurality of embodiments of the present disclosure is realized. A schematic diagram of an exemplary environment in which the memory test means of the arithmetic unit for a chip according to a plurality of embodiments of the present disclosure is realized is shown. A schematic block diagram of a memory test device for a chip according to a plurality of embodiments of the present disclosure is shown. A block diagram of a memory test device for a chip according to a plurality of embodiments of the present disclosure is shown.

In the following, exemplary embodiments of the present application will be described with reference to the drawings, which include various details of the embodiments of the present application for ease of understanding, but these are merely exemplary. Should be understood. Accordingly, what one of ordinary skill in the art should understand is that various changes and modifications can be made to the embodiments described herein without departing from the scope and gist of the present application. Similarly, in the following description, well-known functions and configurations will be omitted for the sake of clarity and simplification.

In the description of the embodiments of the present disclosure, the term "contains" and similar terms should be understood as open inclusion, i.e., "contains, but is not limited to". The term "based on" should be understood as "at least partially based". The term "one embodiment" or "the embodiment" should be construed as "at least one embodiment". The terms "first", "second" and the like can refer to different objects or the same object. Other explicit and implicit definitions can be included below.

As used herein, the term "chip" refers to existing or future developed software or hardware, and the physical carriers realized by combinations thereof. In certain application scenarios, this includes "SoC", "crystal block", "wafer", "die", "integrated circuit", "monolithic device", "semiconductor device", "microelectronic device", etc. However, it is not limited to these.

As used herein, the term "arithmetic unit" refers to a unit that implements a basic arithmetic algorithm or function, which may be by any existing or future developed software or hardware, or a combination thereof. It can be realized. The arithmetic unit can realize various basic operations in the chip including, but not limited to, convolution, numerical operation, vector operation, matrix operation, character operation, and the like.

As used herein, the term "arithmetic module" refers to a module that implements a function or operation, which may be accomplished by any existing or future developed software or hardware, or a combination thereof. Can be done. The arithmetic module can include a plurality of arithmetic units, for example, an arithmetic module can include a plurality of arithmetic units in the form of an array. Arithmetic modules can quickly perform complex and iterative computations to meet the AI algorithm's requirements for computational power.

As described above, a large amount of memory (for example, SRAM, DRAM, CACHE, FLASH®, etc.) is embedded in the AI chip. In order to test the validity of the embedded memory and replace or repair the bad memory, MBIST is usually performed on the memory of the chip before shipping the chip.

The conventional MBIST means is executed after the design of the entire chip is completed, and when the MBIST test is performed, a flat test method is used in which all the memory of the chip is tested as a whole without dividing the memory of the chip. It has been adopted.

With the improvement of the function and the computing power of the AI chip, the number of memories embedded in the AI chip is also increasing rapidly. This makes it time consuming to run a single test for all memory on the chip. Especially when it is necessary to perform an iterative MBIST test, the MBIST test requires a lot of time and increases the manufacturing cost of the chip. Furthermore, with the rapid increase in the number of chip memories, the test vector used for the MBIST test is becoming more and more complicated. More importantly, if any math module / functional unit on the chip needs to be tuned, all memory across the chip will have to be retested, which will result in more unnecessary testing and operation. Is inflexible.

As described above, the conventional MBIST means cannot meet the needs of the memory execution test corresponding to the AI chip under the premise that the cycle of chip design and manufacturing is not increased or extended. Therefore, an efficient and flexible memory testing means is needed to meet the needs of testing the memory of AI chips.

The inventor first concludes that as the functionality of AI chips becomes more complex, a single AI chip typically contains multiple arithmetic modules, and these arithmetic modules are usually designed and implemented independently of each other. Noticed. As an example, an image processing AI chip can include at least one vector calculation module and at least one displacement calculation submodule. The arithmetic modules can be completed independently of each other by different design teams.

Next, the inventor noticed that the structure of the existing AI chip is regular and has the structural feature of being distributed layer by layer. Specifically, one AI chip includes a plurality of arithmetic modules, each arithmetic module includes a plurality of arithmetic units, and each arithmetic unit includes a plurality of memories.

Furthermore, the inventor has also noticed that the structure of the AI chip is highly reproducible. Specifically, arithmetic modules having the same function may have the same structure. As an example, one image processing AI chip can include a plurality (for example, 6) convolution calculation modules having the same structure and function. Further, each arithmetic module can include a plurality of arithmetic units having the same structure and function, and as an example, the convolution arithmetic module may be an array of convolution arithmetic units having a size of 1024 * 512.

Further, the inventor has described that in a conventional AI chip, each arithmetic unit can include one circuit that executes a corresponding arithmetic logic and a plurality of corresponding memories, and the plurality of memories are usually included. I also noticed that it is located near the circuit that executes the corresponding arithmetic logic and can realize high-speed data interaction. Multiple memories belonging to the same arithmetic unit can be divided into multiple groups according to specific criteria (eg, memory location, type, size, test requirements, etc.), and for multiple groups the MBIST tests are parallel to each other. Can be carried out in.

Based on the above findings, the present disclosure proposes improved means of memory testing (eg, MBIST) for chips. According to the embodiments of the present disclosure, the memory tests for the chip do not have to be performed together after the design of all submodules (ie, arithmetic modules) of the chip has been completed, and the design and manufacture of each arithmetic module. Performed independently before. Specifically, in the process of designing and manufacturing the arithmetic module of the chip, a test vector is designed and generated for the current arithmetic module, and the memory test is completed. In this way, it is not necessary to perform the memory test of the chip after the design of all arithmetic modules is completed, and the pressure on the cycle and time limit of the MBIST test is relieved. In addition, memory tests are performed on a single arithmetic module rather than the entire chip, reducing the complexity of test vector design. Furthermore, since the memory test of each arithmetic module of the chip can be executed independently, it is not necessary to test all the storage units of the entire chip when adjusting one arithmetic module, and thus it is unnecessary. Avoid bad tests. Therefore, the present disclosure provides an efficient and flexible memory testing means.

Hereinafter, examples of the present disclosure will be specifically described with reference to the drawings. FIG. 1 shows a schematic diagram of an exemplary environment 100 in which a plurality of embodiments of the present disclosure can be realized. This exemplary environment 100 includes a computing device 110 and a chip 150. The chip 150 includes a first arithmetic module 120-1, a second arithmetic module 120-2, and an L arithmetic module 120-L. The first arithmetic module 120-1, the second arithmetic module 120-2, and the Lth arithmetic module 120-L are arithmetic modules to be executed in the memory test in the chip, and are, for example, a convolution arithmetic module and a displacement arithmetic module. The above arithmetic modules may be designed independently of each other. For convenience of explanation, the plurality of arithmetic modules 120-1, 120-2 to 120-L can be collectively referred to as arithmetic modules 120.

The computing device 110 is a test device that executes a memory test, such as an MBIST control device. As shown in FIG. 1, the computing device 110 inputs the first test vector 130-1 to the first arithmetic module 120-1, and receives the first test result 140-1 by the first arithmetic module 120-1. , The second test vector 130-2 is input to the second calculation module 120-2, and the second test result 140-2 by the second calculation module 120-2 is received. The computing device 110 can obtain a test result regarding the validity of the memory of the first arithmetic module 120-1 based on the first test result 140-1, and the second test result 140-2 is used as the second test result. The test result about the validity of the memory of the arithmetic module 120-2 can be obtained. Further, the computing device 110 can replace or repair the defective memory when it is determined that the defective memory exists.

For convenience of explanation, the plurality of test vectors, for example, the first test vector 130-1 and the second test vector 130-2, can be collectively referred to as the test vector 130, and the plurality of test results, for example, the first test result 140. -1 and the second test result 140-2 can be collectively referred to as a test result 140. The test for the first arithmetic module 120-1 and the test for the second arithmetic module 120-2 are independent of each other and can be executed in different periods depending on the design and manufacturing needs.

In some embodiments, the test vector 130 and the test result 140 can interact between the computing device 110 and the arithmetic module 120 in the form of wired or wireless communication. In some exemplary embodiments, the computing device 110 can generate the test vector 130. Alternatively, in another exemplary embodiment, the computing device 110 includes, but is not limited to, an input device coupled to the computing device 110 (eg, including, but not limited to, a mouse, keyboard, touch pen, touch screen, etc.). It is also possible to receive the test vector 130 input by the user via.

It should be noted that the numbers of the computing device 110 and the arithmetic module 120 shown in FIG. 1 are not limited but merely exemplary, and in other embodiments, the numbers of the computing device 110 and the arithmetic module 120 are other arbitrary. Data, and this disclosure does not limit this.

Further, the test vector 130 and the test result 140 may be transmitted by one or a plurality of interactions between the computing device 110 and the arithmetic module 120 according to a specific application scenario, and the present disclosure. There are no restrictions on this either.

Hereinafter, the memory test process for the chip according to the present disclosure will be described in more detail with reference to FIG. FIG. 2 shows a flowchart of a memory test process 200 for a chip according to a plurality of exemplary embodiments of the present disclosure. Process 200 may be implemented by the computing device 110 of FIG. For ease of consideration, process 200 is described with reference to FIG.

At block 210, the computing device 110 generates a first test vector 130-1 for the first arithmetic module 120-1 of the chip 150.

In the block 220, the computing device 110 receives the generated first test vector 130-1 independently of other arithmetic modules of the chip 150 (for example, the second arithmetic module 120-1 to the L arithmetic module). It is used to perform a memory test on the first arithmetic module 120-1. Specifically, the first test vector 130-1 is output to the first arithmetic module 120-1, and the first test result 140-1 returned from the first arithmetic module 120-1 is received.

As described above, the memory test of the first arithmetic module 120-1 is compared with the conventional memory test means, and the design of the first arithmetic module 120-1 is performed without waiting for the design of the entire chip 150 to be completed. And can be done during manufacturing. Further, it is not necessary to design the test vector for all the memories of the entire chip 150, which reduces the complexity of the test vector. Finally, when the memory test is executed again after the adjustment of the first arithmetic module 120-1, it is not necessary to perform an unnecessary test on the memory of another arithmetic module.

In some embodiments, the first test vector 130-1 may be reused by other arithmetic modules. For example, the computing device 110 determines whether another arithmetic module (for example, the second arithmetic module 120-2) and the first arithmetic module 120-1 satisfy the first criterion. If the first criterion is met, the computing device 110 reuses the first test vector 130-1 when performing a memory test on the second arithmetic module 120-2. If the computing device 110 determines that the second calculation module 120-2 and the first calculation module 120-1 do not meet the first criterion, the computing device 110 refers to the second calculation module 120-2. When executing the memory test, a second test vector 130-2 different from the first test vector 130-1 is generated for the second arithmetic module 120-2, and the generated second test vector 130-2 is used. Then, a memory test is executed for the second arithmetic module 120-2.

In some embodiments, the first criterion is that the second math module 120-2 has the same structure or math function as the first math module 120-1.

As an example, an AI chip for performing an image processing function can include a plurality of convolution operation arrays and a plurality of displacement operation arrays, and the plurality of convolution operation arrays have the same or at least similar structures to each other. However, the plurality of displacement operation arrays have the same or at least similar structures to each other. Based on the similarities between the structures, the test vector can be reused between multiple convolutional or displacement arithmetic arrays.

In this way, the design complexity of the test vector 130 is further reduced.

It should be noted that the fact that the first arithmetic module 120-1 executes the memory test independently of the second arithmetic module 120-2 means that the test operation processes between the two are independent of each other, and is not necessarily the first. It does not mean that the tests for the arithmetic module 120-1 and the second arithmetic module 120-2 must not overlap in time. In some embodiments, the memory tests for the first math module 120-1 and the second math module 120-2 are specific application scenarios (eg, the number of pins for MBIST contained in the chip 150, math module 120). It may be executed in parallel or in series depending on the test requirements, test cost, etc.).

As described above, the first arithmetic module 120-1 can include a plurality of arithmetic units. Further, with reference to FIG. 2, the memory test means for the chips of the present disclosure will be further described as follows. In block 210, the computing device 110 generates a subtest vector for one arithmetic unit of the first arithmetic module 120-1, and the generated subtest vector is transferred among all the arithmetic units of the first arithmetic module 120-1. The first test vector 130-1 may be generated by reuse. In block 220, the computing device 110 executes a memory test on the first arithmetic module 120-1 by executing a corresponding memory subtest for each arithmetic unit of the first arithmetic module 120-1. In some embodiments, the different memory subtests are run in parallel, and in some other embodiments, the different memory subtests are run in series.

Next, with reference to FIG. 3, the means by which the computing device 110 performs a memory test on the first arithmetic module 120-1 will be further described. FIG. 3 shows a schematic diagram of another exemplary environment 300 in which the memory testing means for the chip according to the plurality of embodiments of the present disclosure is realized. As shown in FIG. 3, the first arithmetic module 120-1 includes a plurality of arithmetic units 310-11, 310-12, 310-1M, ..., ...,; 310-N1, 310-N2, ..., Includes 310-NM, where N and M are positive integers. That is, the first arithmetic module 120-1 is an array of arithmetic units of M * N. For convenience of explanation, the plurality of arithmetic units 310-11, 310-12, 310-1M, ..., ...,; 310-N1, 310-N2, ..., 310-NM are collectively referred to as arithmetic units 310. be able to.

In some embodiments, the computing device 110 generates a subtest vector for one arithmetic unit 310 of the first arithmetic module 120-1, for example, arithmetic unit 310-11, and the generated subtest vector is the first. The first test vector 130-1 can be generated by reusing among all the arithmetic units 310 of the arithmetic module 120-1. In the exemplary embodiment shown in FIG. 3, the generated subtest vector may be reused M * N times.

In some embodiments, different arithmetic units 310 (eg, arithmetic units 310-11, 310-12, ..., 310-1M; ...,; 310-N1, 310-N2, ..., 310 in FIG. 3). Multiple memory subtests performed for −NM) may be performed in parallel. In some other embodiments, different memory subtests may be performed serially.

As described above, the characteristics that the structures and functions are the same / similar in the different arithmetic units 310 belonging to the same arithmetic module 120 are fully utilized, and the design of the test vector is further simplified. In addition, different memory subtests are performed in parallel or in series, depending on the particular application scenario (eg, the number of pins for MBIST contained in the chip 150, the test requirements of the arithmetic module 120, the test cost, etc.). It is also good, thereby further improving the efficiency of memory testing.

As mentioned above, each arithmetic unit 310 is generally located close to one circuit that executes the corresponding arithmetic logic and a circuit that executes the corresponding arithmetic logic in order to enable high-speed data exchange. Includes multiple memories. On the other hand, a plurality of memories belonging to the same arithmetic unit may be divided into a plurality of groups according to specific criteria (for example, memory location, type, size, test requirements, etc.). Depending on the above characteristics of the arithmetic unit 310, the memory test for the chip can be further improved.

With reference to FIG. 4, the means by which the computing device 110 performs a memory test on the arithmetic unit 310 will be further described. FIG. 4 shows a schematic diagram of an exemplary environment 400 in which the memory test means for the chip arithmetic unit 310 according to the plurality of embodiments of the present disclosure is realized. As shown in FIG. 4, the arithmetic unit 310-11 has a plurality of memories 410-11, 410-12, ..., 410-1P; ..., 410-R1, 410-R2, ..., 410-RQ. Including, where R and Q are positive integers. For convenience of explanation, a plurality of memories 410-11, 410-12, ..., 410-1P; ..., 410-R1, 410-R2, ..., 410-RQ can be collectively referred to as memory 410. ..

Alternatively or additionally, in some embodiments, the arithmetic unit 310-11 may be configured to include a test controller 440. The test controller 440 may be implemented as part of the computing device 110 or may be designed as a module or entity independent of the computing device 110. The test controller 440 receives the subtest vector 420 and returns the test result 430 of the arithmetic unit 310 to the corresponding device. In some embodiments, the test controller 440 may be implemented as an MBIST controller.

In some embodiments, the memory 410 of the compute unit 310 is divided into a plurality of memory groups according to a second criterion.

In some embodiments, the computing device 110 can divide the memory 410 into a plurality of groups according to the location of the memory 410. For example, the computing device 110 can divide memory 410s located close to each other into one group.

Alternatively or additionally, the computing device 110 can divide the memory 410 into a plurality of groups according to the type of the memory 410 (eg, SRAM, DRAM, CACHE, FLASH®, etc.). For example, the computing device 110 divides all SRAM type memories into one group and all registers into another group.

As shown in FIG. 4, the memory 410 of the calculation unit 310-11 is divided into the memories of the R group, of which 410-11, 410-12, ..., 410-1P are divided into one group and the memory. 410-R1, 410-R2, ..., 410-RQ are divided into different groups.

The grounds for grouping the memory 410 by the computing device 110 are not limited to the example examined above, and in other embodiments, the memory size, the MBIST test cost, and the like may be used. This disclosure does not limit this.

In some embodiments, each memory group comprises 10-12 memories.

In some embodiments, the computing device 110 produces each group test vector 450 for each of at least one group that is divided.

In some embodiments, the test controller 440 performs a corresponding memory group test for each group based on the separated groups, and different memory group tests are performed in parallel. As shown in FIG. 4, the test controller 440 receives the subtest vector 420, and based on the subtest vector 420, for the group test vector 450-1 for the memory of the first group and for the memory of the third group. Generate a group test vector 450-R. The test controller 440 executes the memory group test in parallel between the memory of the first group and the memory of the Rth group.

In some embodiments, the test controller 440 receives the memory group test results 460-1 and 460-R and returns them as arithmetic unit test results 430 to the corresponding instrument.

In this way, the memory belonging to the same calculation unit 310 is divided into different memory groups, and the memory group test is executed in parallel between the different memory groups, thereby improving the performance of the memory test.

In addition, the AI chip also contains some common memory (eg, some slow memory) that is not included in any of the arithmetic modules 120. Further, each arithmetic module 120 includes some common memories (for example, low-speed memory) for the arithmetic module 120 in addition to the memory arranged in each arithmetic unit 310. In some embodiments, the computing device 110 divides these common memories into a plurality of arithmetic modules according to predetermined criteria (including, but not limited to, location, type, test requirements, etc.) and the memory of the present disclosure. A memory test may be executed on the above common memory according to the test method.

In some embodiments, when performing a memory test, the corresponding clock control module assists the execution so as to control the read / write rate of the memory test.

When designing the numerical value of the concrete test vector, the test vector can be designed by using an existing or future method, and when the wiring for the memory test is executed, the existing or future method can be used. Any future wiring method can be used and the present disclosure is not limited to this.

Furthermore, the method of the present disclosure can be applied not only to the process of designing and manufacturing the AI chip, but also to the process of emulation, research and development, simulation, and the like of the chip.

According to the embodiments of the present disclosure, unlike the conventional MBIST method based on flattening, the present invention uses a layered memory test technique to accelerate the MBIST test to the design and manufacturing stage of the arithmetic module 120 of the chip. It alleviates the pressure on the MBIST test cycle and test time period, while reducing the complexity of the test vector design. Further, since the memory 410 of each arithmetic module 120 can be tested independently, the memory of another arithmetic module should be re-executed when adjustment occurs in one arithmetic module and the memory test needs to be re-executed. There is no need to perform unnecessary tests on the 410.

Further, the complexity of designing the test vector is further reduced by reusing the test vector between the arithmetic modules 120 having the same function and between the plurality of arithmetic units 310 of the same arithmetic module 120.

Further, the present disclosure further shortens the memory test time by grouping the memory 410 of the same arithmetic unit 310 and executing the memory group test in parallel using different test vectors among different memory groups. Reduce chip manufacturing and manufacturing costs.

FIG. 5 shows a schematic block diagram of a memory test device 500 for a chip according to an embodiment of the present disclosure. The device 500 may be included in the computing device 110 shown in FIG. 1 or may be realized as the computing device 110. As shown in FIG. 5, the apparatus 500 includes a first test vector generation module 510 configured to generate a first test vector 130-1 for the first arithmetic module 120-1 of at least one arithmetic module. include. The apparatus 500 uses the generated first test vector 130-1 independently of other arithmetic modules different from the first arithmetic module 120-1 among at least one arithmetic module 120 to perform the first arithmetic. It may further include a first memory test module 520 configured to perform a memory test on module 120-1.

In some embodiments, if the second arithmetic module 120-2 and the first arithmetic module 120-1 among the other arithmetic modules satisfy the first criterion, the apparatus 500 uses the first test vector 130-1. Further, a second memory test module configured to execute a memory test on the second arithmetic module 120-2 is included, and the second arithmetic module 120-2 and the first arithmetic module among other arithmetic modules are included. If 120 does not meet the first criterion, the apparatus 500 comprises a second test vector generation module configured to generate a second test vector for the second arithmetic module 120-2, and at least one arithmetic module. Memory for the 1st and 2nd arithmetic modules 120-2 using the 2nd test vector 130-2, which is different from the 1st test vector 130-1, which was generated independently of our other arithmetic modules. It further includes a third memory test module configured to perform the test.

In some embodiments, the first criterion is that the second math module 120-2 has the same structure or math function as the first math module 120-1.

In some embodiments, the first test vector generation module 510 is a subtest vector 420 generation module configured to generate a subtest vector 420 for one arithmetic unit 310 of the arithmetic module, and a subtest. It includes a subtest vector reuse module configured to generate the first test vector 130-1 by reusing the vector 420 among all the arithmetic units 310 of the first arithmetic module 120-1.

In some embodiments, the apparatus 500 further comprises a first memory partitioning module configured to divide at least one memory 410 of the arithmetic unit into at least one group according to a second criterion. The subtest vector generation module is based on a group test vector generation module configured to generate each group test vector 450 for each of at least one partitioned group and a generated group test vector 450. It further includes a group test vector synthesis module configured to generate the subtest vector 420.

In some embodiments, the first memory partition block is configured to divide at least one memory 420 of the arithmetic unit into at least one group, depending on the location and type of at least one memory. Includes compartmentalized modules.

In some embodiments, the first memory test module corresponds to each of at least one arithmetic unit 310 of the first arithmetic module 120-1 in which different memory subtests are executed in parallel or serially. Includes a memory subtest module configured to perform a memory test on the first arithmetic module 120-1 by performing a memory subtest.

In some embodiments, the apparatus 500 further comprises a second memory partitioning module configured to divide at least one memory 420 of the arithmetic unit 310 into at least one group according to a third criterion, a memory subtest. The module further comprises performing a memory subtest by performing a corresponding memory group test in which different memory group tests are performed in parallel for each of the separated groups.

In some embodiments, the second memory partitioning module is configured to divide at least one memory 420 of the arithmetic unit 310 into at least one group, depending on the location and type of at least one memory 420. Includes memory group partition module.

FIG. 6 shows a schematic block diagram of an exemplary device 600 that can be used to carry out the embodiments of the present disclosure. The device 600 can be used to realize the image processing device 130 shown in FIG. As shown in the figure, the device 600 is variously suitable according to the computer program instructions stored in the read-only memory (ROM) 602 or the computer program instructions loaded from the storage unit 608 into the random access memory (RAM) 603. Includes a central processing unit (CPU) 601 capable of performing various operations and processes. Various programs and data necessary for the operation of the device 600 may be stored in the RAM 603. The CPU 601 and the ROM 602 and the RAM 603 are connected to each other via the bus 604. The input / output (I / O) interface 605 is also connected to the bus 604.

A plurality of components of the device 600 are connected to the I / O interface 605, and these components are input units 606 such as a keyboard and a mouse; output units 607 such as various displays and speakers; magnetic disks, optical disks and the like. Storage unit 608; includes a communication unit 609 such as a network card, a modem, and a wireless communication transmitter / receiver. The communication unit 609 allows the device 600 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunications networks.

The processing unit 601 performs the various methods and processes described above, such as process 400. For example, in some embodiments, process 200 may be implemented as a computer software program tangibly contained in a machine readable medium such as storage unit 608. In some embodiments, some or all of the computer programs can be loaded and / or installed on the device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded into the RAM 603 and executed by the CPU 601 it is possible to perform one or more steps of the process 400 described above. Alternatively, in other embodiments, the CPU 601 may be configured to perform any other suitable method (eg, by firmware) to perform the process 400.

The functions described herein may be performed at least partially by one or more hardware logic components. For example, but not limited to, exemplary types of hardware logic components that can be used include field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), and system-on-a-chips. Includes chips (SOCs), compound programmable logic devices (CPLDs), and the like.

The program code for implementing the methods of the present disclosure can be programmed in any combination of one or more programming languages. These program codes are provided to the processor or controller of a general purpose computer, dedicated computer, or other programmable data processing device and are specified in the flow chart and / or block diagram when the program code is executed by the processor or controller. Functions / actions can be performed. The program code may be run entirely on the machine, partly on the machine, or as a separate software package, partly on the machine and partly on the remote machine, completely. It may be run on a remote machine or server.

In the context of the present disclosure, machine readable media may include or store programs to be used by or with an instruction execution system, device, or device. It can be a tangible medium. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can include, but are limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination thereof. It is not something that will be done. More specific examples of machine-readable storage media are electrical connections based on one or more lines, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable reads. Includes dedicated memory (EPROM or flash memory), optical fiber, compact disc read-only memory (CD-ROM), optical storage equipment, magnetic storage equipment, or any suitable combination thereof.

The systems and technologies described herein are computing systems that include background components (eg, as data servers), or computing systems that include middleware components (eg, application servers), or computing systems that include front-end components. (For example, a user computer having a graphical user interface or web browser that allows the user to interact with embodiments of the systems and techniques described herein), or such background components, middleware components, or. Implemented in computing systems that include any combination of front-end components. The components of the system can be interconnected via digital data communication of any form or medium (eg, a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

Computer systems can include clients and servers. Clients and servers are generally separated from each other and generally interact over a communication network. The client-server relationship runs on the corresponding computer and is generated by a computer program that has a client-server relationship with each other.

Further, each action is illustrated in a particular order, which means that such actions are performed in the particular order or order shown, or all actions shown are all. It should be understood to mean that it needs to be done to get the desired result. In some environments, multitasking and parallel processing may be advantageous. Similarly, the above discussion contains some specific implementation details, which should not be construed as limiting the scope of this disclosure. Some features described in the context of separate embodiments may be realized in combination in a single embodiment. Conversely, the various features described in the context of a single form may be realized in multiple forms alone or in any suitable subcombination.

This subject matter is described in a language specific to the logical behavior of structural features and / or methods, but the subject matter limited to the appended claims is limited to the particular feature or behavior described above. Please understand that it is not always done. Conversely, the particular features and behaviors described above are merely exemplary forms that fulfill the claims.

Claims (21)

A memory test method for a chip, wherein the chip comprises a plurality of arithmetic modules including at least one arithmetic unit including at least one said memory.
A step of generating a first test vector for the first arithmetic module of the at least one arithmetic module,
A step of executing a memory test on the first arithmetic module using the generated first test vector independently of other arithmetic modules different from the first arithmetic module among at least one arithmetic module. A memory test method for chips, including. When the second calculation module and the first calculation module among the other calculation modules satisfy the first criterion, the step of executing a memory test on the second calculation module using the first test vector. ,
When the second arithmetic module and the first arithmetic module among the other arithmetic modules do not satisfy the first criterion, a second test vector is generated for the second arithmetic module, and at least one arithmetic module is generated. A step of performing a memory test on the second arithmetic module using the generated second test vector, which is different from the first test vector, is further performed independently of the other arithmetic modules of The method according to claim 1, including. The method according to claim 2, wherein the first criterion is that the second arithmetic module has the same structure or arithmetic function as the first arithmetic module. The step of generating the first test vector is
A step of generating a subtest vector for one of the arithmetic modules,
The method of claim 1, comprising the step of generating a first test vector by reusing the subtest vector among all the arithmetic units of the first arithmetic module. Further comprising dividing the at least one memory of the arithmetic unit into at least one group according to a second criterion.
The step of generating the subtest vector is
For each of the divided at least one group, a step of generating each group test vector, and
The method of claim 4, comprising the step of generating the subtest vector based on the generated group test vector. The step of dividing the at least one memory of the arithmetic unit into the at least one group according to the second criterion is
5. The method of claim 5, comprising dividing the at least one memory of the arithmetic unit into the at least one group, depending on the location and type of the at least one memory. The step of executing the memory test for the first arithmetic module is
By executing the corresponding memory subtests such that different memory subtests are executed in parallel or serially for each of the at least one arithmetic unit of the first arithmetic module. 1 The method of claim 1, comprising the step of performing the memory test on the arithmetic module. A step further comprising dividing the at least one memory of the arithmetic unit into at least one group according to a third criterion and performing the corresponding memory subtest for each arithmetic unit is a step.
A claim comprising performing the memory subtest by performing a corresponding memory group test such that different memory group tests are performed in parallel for each of at least one group divided. Item 7. The method according to Item 7. The step of dividing the at least one memory of the arithmetic unit into the at least one group according to the third criterion is
8. The method of claim 8, comprising the step of dividing the at least one memory of the arithmetic unit into the at least one group, depending on the location and type of the at least one memory. A memory test device for chips
The chip comprises a plurality of arithmetic modules including at least one arithmetic unit including at least one said memory.
The device is
A first test vector generation module configured to generate a first test vector for the first calculation module of the at least one calculation module.
A memory test is executed on the first arithmetic module using the generated first test vector independently of the other arithmetic modules different from the first arithmetic module among at least one arithmetic module. A memory test device for a chip, including a first memory test module configured in. When the second arithmetic module and the first arithmetic module among the other arithmetic modules satisfy the first criterion
A second memory test module configured to perform a memory test on the second arithmetic module using the first test vector is further included.
When the second arithmetic module and the first arithmetic module among the other arithmetic modules do not satisfy the first criterion.
A second test vector generation module configured to generate a second test vector for the second arithmetic module, and a second test vector generation module.
A memory test is executed on the second arithmetic module using the generated second test vector, which is different from the first test vector, independently of the other arithmetic modules of the at least one arithmetic module. 10. The apparatus of claim 10, further comprising a third memory test module configured to do so. The apparatus according to claim 12, wherein the first criterion is that the second arithmetic module has the same structure or arithmetic function as the first arithmetic module. The first test vector generation module is
A subtest vector generation module configured to generate a subtest vector for one of the arithmetic modules.
The tenth aspect of the present invention includes a subtest vector reuse module configured to generate a first test vector by reusing the subtest vector among all the arithmetic units of the first arithmetic module. Equipment. A first memory partition block configured to divide the at least one memory of the arithmetic unit into at least one group according to a second criterion is further included.
The subtest vector generation module is
A group test vector generation module configured to generate each group test vector for each of the at least one group divided.
13. The apparatus of claim 13, comprising a group test vector synthesis module configured to generate the subtest vector based on the generated group test vector. The first memory division block is
14. The 14. Device. The first memory test module is
The first operation by executing the corresponding memory subtest so that different memory subtests are executed in parallel or serially for each of the at least one operation unit of the first operation module. 9. The apparatus of claim 9, comprising a memory subtest module configured to perform the memory test on the module. A second memory partitioning module configured to divide the at least one memory of the arithmetic unit into at least one group according to a third criterion is further included.
The memory subtest module is
Further comprising running the memory subtest by running the corresponding memory group test such that different memory group tests are run in parallel for each of at least one group divided. The device according to claim 16. The second memory division module is
17. The 17. Device. It ’s an electronic device,
With one or more processors
An electronic device comprising a memory for storing one or more programs that causes the electronic device to perform the method according to any one of claims 1-9 when executed by one or more processors. .. A computer-readable storage medium in which a computer program that realizes the method according to any one of claims 1 to 9 when executed by a processor is stored. A computer program that realizes the method according to any one of claims 1 to 9 when the computer program is executed by a processor.

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