JP2021190599A - Thin film transistor and manufacturing method for the same - Google Patents

Abstract

To provide a thin film transistor having high carrier mobility, suppressing the negative shift of threshold voltage, and including an oxide semiconductor layer, and a manufacturing method for the same.SOLUTION: In a manufacturing method for a thin film transistor in which at least an oxide semiconductor layer, a gate insulating film, and a gate electrode are formed in this order on a substrate, metal elements in the oxide semiconductor layer include In, Ga, Zn, and Sn, and the oxide semiconductor layer is irradiated with predetermined light from the gate electrode side, so that a region in the oxide semiconductor layer not overlapping with the gate electrode has lower resistance and source and drain regions are formed. Regarding the ratio of the metal elements, preferably, In is contained by 45 atom% or more and 65 atom% or less, Ga is contained by 5 atom% or more and 16 atom% or less, Zn is contained by 10 atom% or more and 40 atom% or less, and Sn is contained by 3 atom% or more and 10 atom% or less.SELECTED DRAWING: Figure 1

Description

The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly to a thin film transistor using an oxide semiconductor and a method for manufacturing the thin film transistor.

Metal oxide semiconductors (hereinafter, simply referred to as “oxide semiconductors”) have higher carrier mobility than general-purpose amorphous silicon. Oxide semiconductors have a large optical bandgap and can be formed at low temperatures, so they are expected to be applied to next-generation displays that require large size, high resolution, and high-speed drive, and resin substrates with low heat resistance. ..

When an oxide semiconductor is used as a semiconductor layer of a thin film transistor (TFT), it is required to have excellent switching characteristics of the thin film transistor. Specifically, (1) the on current (the maximum drain current when a positive voltage is applied to the gate electrode and the drain electrode) is large, and (2) the off current (a negative voltage is applied to the gate electrode and a positive voltage is applied to the drain voltage). (Drain current when applied respectively) is small, (3) S value (Subthreshold Swing: gate voltage required to raise the drain current by one digit) is small, and (4) threshold voltage (positive voltage is applied to the drain electrode). It is required that the voltage at which the drain current starts to flow when a positive or negative voltage is applied to the gate voltage) does not change with time and is stable.

Here, in order to increase the on-current, it is required that the carrier mobility (hereinafter, may be simply referred to as mobility) is high, the channel length is short, and the like.

As the oxide semiconductor, an In-Ga-Zn-based oxide semiconductor (IGZO) composed of indium, gallium, zinc, and oxygen and an In-Ga-Sn-based oxide semiconductor composed of indium, gallium, tin, and oxygen are preferable. It is known (Patent Documents 1 and 2). For example, it is known that an In-Ga-Zn-based oxide semiconductor can obtain a mobility of about ^{10 cm 2 / Vs.}

On the other hand, self-aligned thin film transistors, in which a low-resistance source / drain region is formed in the semiconductor layer of the thin film transistor in alignment with the gate electrode to reduce parasitic capacitance and improve manufacturing efficiency, are attracting attention. There is a need to establish a manufacturing technology for self-aligned thin film transistors that use various oxide semiconductors as channels. As a self-alignment manufacturing technique, for example, a manufacturing method using an excimer laser (Patent Document 3) and a manufacturing method using Ar plasma (Non-Patent Document 1) have been proposed.

Patent No. 5357342 Japanese Unexamined Patent Publication No. 2011-174134 Japanese Unexamined Patent Publication No. 2014-135474

J. Park, et al., "Self-aligned top-gate amorphous gallium indium zinc oxide thin film transistors", Applied Physics Letters 93, 053501 (2008). S. Hong, et al., "Study on the Lateral Carrier Diffusion and Source-Drain Series Resistance in Self-Aligned Top Gate Coplanar InGaZnO Thin-Film Transistors", Scientific Reports 9, 6588 (2019).

However, a thin film transistor manufactured by using a conventional oxide semiconductor such as IGZO does not have sufficient characteristics such as not being able to obtain a sufficient on-current.

Further, as a problem of the self-aligned thin film transistor for improving the efficiency of the manufacturing process, as shown in Non-Patent Document 2, a source / drain region having a low resistance is diffused in the channel. In this case, problems such as an increase in parasitic capacitance, in-plane variation in parasitic capacitance, and a shift of the threshold voltage to the negative side due to an increase in carrier density in the channel region are caused.

Therefore, an object of the present invention made in view of the above-mentioned problems is to have high carrier mobility, prevent diffusion of the source / drain region, and suppress the shift of the threshold voltage to the negative side. It is an object of the present invention to provide a thin film transistor provided with an oxide semiconductor layer and a method for manufacturing the thin film transistor.

In order to solve the above problems, the method for manufacturing a thin film according to the present invention is a method for manufacturing a thin film in which at least an oxide semiconductor layer, a gate insulating film, and a gate electrode are formed in this order on a substrate. The metal element constituting the layer contains In, Ga, Zn, and Sn, and the oxide semiconductor layer is irradiated with predetermined light from the side of the gate electrode so that the oxide semiconductor layer does not overlap with the gate electrode. It is characterized by lowering the resistance of the layer region and forming a source / drain region.

Further, in the method for manufacturing the thin film, the ratio of each metal element to the total of all metal elements (In + Ga + Zn + Sn) in the oxide semiconductor layer is In: 45 atomic% or more and 65 atomic% or less, Ga: 5 atomic% or more and 16 atoms. % Or less, Zn: 10 atomic% or more and 40 atomic% or less, and Sn: 3 atomic% or more and 10 atomic% or less are desirable.

Further, in the method for manufacturing the thin film transistor, it is desirable that the ratio of In to the total of all metal elements (In + Ga + Zn + Sn) is 50 atomic% or more and 60 atomic% or less.

Further, in the method for manufacturing the thin film transistor, it is desirable that ^{the irradiation intensity of the light is 120 mJ / cm 2 or more.}

Further, in the method for manufacturing the thin film transistor, it is desirable that the irradiation intensity of the light is 150 to 240 mJ / cm ^2.

Further, in the method for manufacturing the thin film transistor, it is desirable that the oxide semiconductor layer is irradiated with the predetermined light through the gate insulating film to form the source / drain region.

In order to solve the above problems, the thin film according to the present invention is a thin film in which at least an oxide semiconductor layer, a gate insulating film, and a gate electrode are laminated in this order on a substrate, and constitutes the oxide semiconductor layer. The metal element contains In, Ga, Zn, and Sn, and the positions of the end of the gate electrode and the end of the source / drain region provided in the oxide semiconductor layer are the same, and the source / drain region is the same. Is characterized by having the same composition of metal elements as the oxide semiconductor layer and having a sheet resistance lower than that of the channel region due to oxygen deficiency.

Further, in the thin film, the ratio of each metal element to the total of all metal elements (In + Ga + Zn + Sn) in the oxide semiconductor layer is In: 45 atomic% or more and 65 atomic% or less, Ga: 5 atomic% or more and 16 atomic% or less. It is desirable that Zn: 10 atomic% or more and 40 atomic% or less, and Sn: 3 atomic% or more and 10 atomic% or less.

Further, it is desirable that the thin film transistor has ^{an oxygen deficiency of 1.5 × 10 18} cm ^{-3 or more in the source / drain region.}

According to the thin film transistor and the manufacturing method thereof in the present invention, it is possible to have high carrier mobility, prevent diffusion of the source / drain region, and suppress the shift of the threshold voltage to the negative side.

It is a figure explaining the thin film transistor of this invention and the manufacturing method thereof. It is a figure explaining the thin film transistor of the comparative example and the manufacturing method thereof. It is a figure which shows the irradiation intensity dependence of the sheet resistance of an oxide semiconductor (IGZTO). It is a figure which shows the transmission characteristic of the thin film transistor which has different laser irradiation intensities. It is a figure which shows the channel length dependence of the threshold voltage of the thin film transistor by laser irradiation and Ar plasma processing. It is a figure which shows the transmission characteristic of the thin film transistor by laser irradiation and Ar plasma processing.

The present inventors have a region in which an oxide semiconductor containing In, Ga, Zn and Sn has a high carrier mobility, and the oxide semiconductor is irradiated with a predetermined light to have a high carrier concentration. We have found that it can be formed. Further, by controlling the composition of the oxide semiconductor so that the ratio of the contents of In, Ga, Zn and Sn to the total content of In, Ga, Zn and Sn is within a predetermined range, the oxidation is performed. It was discovered that a thin film transistor using a physical semiconductor exhibits good characteristics. In the present specification, an oxide composed of In, Ga, Zn, Sn and O (oxygen) may be referred to as "IGZTO".

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating a thin film transistor of the present invention and a method for manufacturing the same.

First, as shown in FIG. 1A, the base film 2 is formed on a substrate 1 such as glass. The undercoat film 2 is, for example, SiO _x (silicon oxide), and is formed by a CVD (Chemical Vapor Deposition) method, PECVD (Plasma Enhanced Chemical Vapor Deposition), or the like. The thickness of the base film 2 is preferably about 50 to 200 nm, which improves the adhesion between the substrate 1 and the oxide semiconductor layer 3 and prevents the diffusion of impurities from the substrate 1 to the oxide semiconductor layer 3. There is a function. However, it is not essential for the operation of the thin film transistor, and the undercoat film 2 may be omitted.

Next, an oxide semiconductor layer (oxide semiconductor thin film) 3 containing In, Ga, Zn, and Sn as metal elements is formed on the base film 2 by using sputtering or the like. In this oxide semiconductor (IGZTO), the ratio of each metal element to the total number of all metal elements (In + Ga + Zn + Sn) in the oxide semiconductor layer 3 (hereinafter, may be referred to as “atomic number ratio”) is determined.
In: 45 atomic% or more and 65 atomic% or less,
Ga: 5 atomic% or more and 16 atomic% or less,
It is desirable that Zn: 10 atomic% or more and 40 atomic% or less, and Sn: 3 atomic% or more and 10 atomic% or less.

In is an element that contributes to the improvement of conductivity (electrical conductivity). As the In atomic number ratio increases, that is, as the amount of In in all metal elements increases, the conductivity of the oxide semiconductor layer 3 improves, so that the carrier concentration and carrier mobility increase. In order to effectively exert this effect, the In atom number ratio needs to be 45 atomic% or more, preferably 50 atomic% or more. However, if the In atom number ratio is too large, there is a problem that the resistance of the oxide semiconductor layer 3 decreases, the carrier concentration becomes too high, and the threshold voltage decreases. Therefore, the In atom number ratio needs to be 65 atomic% or less, preferably 60 atomic% or less, and more preferably 55 atomic% or less.

Ga is an element that contributes to the reduction of oxygen deficiency and the control of carrier density. The larger the Ga atomic number ratio, that is, the larger the amount of Ga in the total metal elements, the better the electrical stability of the oxide semiconductor layer 3 and the more the effect of suppressing the excessive generation of carriers is exhibited. Ga is also an element that suppresses etching by a hydrogen peroxide-based Cu etching solution. Therefore, the larger the Ga atom number ratio, the larger the selection ratio with respect to the hydrogen peroxide-based etching solution used for etching the Cu electrode as the source / drain electrode, and the less likely it is to be damaged. When the Ga atomic number ratio is less than 5 atomic%, the etching resistance is lowered, and the light stress resistance (change in the characteristics of the transistor caused by voltage application (light stress) in the light irradiation state or remaining after stress is removed). Since resistance to changes in characteristics) deteriorates, Ga must be 5 atomic% or more in order to effectively exert the above action. The Ga atomic number ratio is preferably 8 atomic% or more, more preferably 10 atomic% or more. However, if the Ga atomic number ratio is too large, the carrier density of the oxide semiconductor layer 3 becomes low, and the mobility decreases. In addition, the conductivity of the sputtering target material for forming the oxide semiconductor layer decreases, and it becomes difficult for the DC discharge to be stably maintained during film formation. Therefore, the Ga atomic number ratio needs to be 16 atomic% or less, preferably 15 atomic% or less, and more preferably 12 atomic% or less.

Zn is not as sensitive to thin film transistor characteristics as other metal elements, but it affects the processing characteristics of oxide semiconductors. When the Zn atom number ratio is less than 10 atomic%, the etching rate for a superwater system, oxalic acid, or the like is low. Therefore, the Zn atom number ratio needs to be 10 atomic% or more, preferably 20 atomic% or more, and more preferably 30 atomic% or more. However, if the Zn atom number ratio is too large, the oxide semiconductor layer 3 tends to crystallize. In particular, in fields such as displays where film formation over a large area is required, partial formation of crystals causes a decrease in the uniformity of the oxide semiconductor layer 3. Further, as a result of increasing the solubility of the oxide semiconductor layer 3 in the etching solution for the source / drain electrode, the wet etching resistance tends to deteriorate. Further, since the amount of In is relatively reduced, the mobility of the electric field effect is lowered, or Ga is relatively reduced, so that the electrical stability of the oxide semiconductor layer 3 is likely to be lowered. Therefore, the Zn atom number ratio needs to be 40 atomic% or less, preferably 35 atomic% or less.

In the oxide semiconductor to which Sn is added, the carrier density is increased due to hydrogen diffusion and the sheet resistance is lowered, and if the Sn addition amount is appropriate, the reliability of the thin film transistor against light stress is improved. In order to effectively exert this effect, the Sn atom number ratio needs to be 3 atomic% or more, preferably 5 atomic% or more, and more preferably 6 atomic% or more. On the other hand, Sn is an element that inhibits etching by an acid-based chemical solution. Therefore, if the Sn atom number ratio is too large, the resistance of the oxide semiconductor layer 3 to the etching solution of the organic acid and / or the inorganic acid becomes higher than necessary, and the etching process of the oxide semiconductor layer 3 becomes difficult. Further, if the Sn atomic number ratio is too large, the linearity of the change in the drain current with respect to the change in the channel size may be lowered due to the strong influence of hydrogen diffusion. Therefore, the Sn atomic number ratio needs to be 10 atomic% or less, preferably 8 atomic% or less, and more preferably 7 atomic% or less.

In one embodiment of the invention, the oxide semiconductor comprises In, Ga, Zn, Sn, O and unavoidable impurities. Inevitable impurities can be introduced depending on the situation of raw materials, materials, manufacturing equipment, and the like. Examples of unavoidable impurities include Al, Pb, Si, Fe, Ni, Ti, Mg, Cr and Zr. The content of unavoidable impurities is preferably 1% by mass or less, more preferably 500% by mass or less, based on the mass of the oxide semiconductor layer 3.

The ratio of the Zn content to the Sn content (ratio of the Zn atom number ratio to the Sn atom number ratio) is preferably more than 2.4. This makes it easy to improve the linearity of the drain current Id with respect to the channel size W / L. Further, by setting the ratio of the Zn content to the Sn content to be more than 2.4, it becomes easier to suppress the effective fluctuation of the channel size. The ratio of the Zn content to the Sn content is more preferably 3.0 or more, further preferably 4.0 or more, still more preferably 7.0 or less, still more preferably 5.5 or less.

When forming a film of an oxide semiconductor having a desired composition by a sputtering method, the composition of the sputtering target is set to be substantially close to the composition of the target oxide semiconductor while considering the sputtering characteristics of each metal. Is preferable.

The thickness of the oxide semiconductor layer 3 is not particularly limited, but is preferably 10 nm or more because it is excellent in selectivity during etching processing of the source / drain electrode, and more preferably 15 nm or more. Further, from the viewpoint of maintaining high mobility, it is preferably 50 nm or less, for example.

In order to realize a thin film transistor with high mobility, the film structure of the oxide semiconductor layer 3 is also an important factor, and the oxide semiconductor layer 3 has an amorphous structure or at least a partially crystallized amorphous structure. It is preferable to have. That is, it is preferable that the oxide forming the oxide semiconductor layer 3 is amorphous or at least partially crystallized amorphous.

Since the oxide semiconductor layer 3 is formed by a sputtering method having a high throughput, it is usually considered that the film structure is amorphous. However, in reality, submicron level (nano level) crystals are dispersed in the amorphous structure in the film structure. The structure of the oxide semiconductor can be obtained by controlling the gas pressure in the range of 1 to 5 mTorr at the time of forming the oxide semiconductor layer, forming a protective film, and then heat-treating at a temperature of 200 ° C. or higher. ..

In addition, since the process for manufacturing a thin film transistor using an oxide semiconductor includes several heat treatment processes (during film formation, heat treatment, etc.), the amorphization rate is determined by the total result of these heat treatment processes. become. Since the structure of the oxide semiconductor layer 3 affects the carrier mobility, it is desirable to search for the optimum process conditions in order to realize a thin film transistor having high mobility.

Further, before forming the protective layer, i.e., the oxide semiconductor layer 3 by sputtering film formation, further the sheet resistance of the oxide semiconductor layer 3 after the addition of the heat treatment is preferably from 1.0 × 10 ⁵ Ω / □ or less , 5.0 × 10 ⁴ Ω / □ or less is more preferable. An oxide semiconductor layer having such a sheet resistance is preferable for increasing the mobility of the thin film transistor. The sheet resistance of common oxide semiconductor is 10 ⁷ Ω / □ extent, relatively low resistance IGZO oxide sheet resistance be a semiconductor layer is 1.0 × 10 ⁵ Ω / □ super value Often indicates. In the case of a thin film transistor having an oxide semiconductor layer 3, the sheet resistance of the oxide semiconductor layer 3 after forming the protective film tends to increase in the manufacturing process thereof. This is because oxide semiconductors generally have a band gap, but band bending occurs by forming a protective film.

Further, when the OH group of the oxide semiconductor layer 3 is increased, the photostress resistance is improved while the high mobility is maintained. That is, when the oxide semiconductor layer 3 having such an increased OH group is used for the display panel, the characteristics of the thin film transistor are less likely to change even if it is irradiated with light such as a backlight for a long time. The reason for this is that when hydrogen invades the oxide semiconductor layer to form OH groups, oxygen-related defects and unstable hydrogen-related defects in the channel layer are effectively suppressed, and stable metal-oxygen bonds are suppressed. Is believed to be due to the formation of. The density of OH groups in the oxide semiconductor layer can be effectively controlled by post-annealing.

After forming the oxide semiconductor layer 3, patterning is performed using photolithography. Wet etching with organic and / or inorganic acids can be used for patterning. Immediately after patterning, it is preferable to perform a heat treatment to improve the film quality of the oxide semiconductor, whereby the on-current and mobility of the thin film transistor characteristics are increased, and the performance is improved. The heat treatment is preferably performed at 300 ° C. or higher for 30 minutes or longer.

Next, the gate insulating film 4 is formed on the oxide semiconductor layer 3. For the gate insulating film 4, for example, SiO _x is formed by a CVD or PECVD method. The gate insulating film 4 may be formed of another insulating material having a desired dielectric constant, and SiN, SiON, or another high dielectric constant insulating film may be used. The thickness of the gate insulating film 4 is determined in consideration of the threshold voltage of the thin film transistor, the gate withstand voltage, and the like, but it is desirable to form the gate insulating film 4 with a thickness of 100 to 500 nm depending on the desired switching characteristics.

Then, after forming a metal such as Mo as the gate electrode material, patterning is performed using photolithography to form the gate electrode 5. As the gate electrode material, a material having a lower absorption rate (higher reflectance) than the laser used for the laser treatment to be performed later is preferable. When the laser absorption rate is high, the temperature of the gate electrode rises significantly due to the irradiation laser absorption, which may lead to deformation or ablation of the shape. The gate electrode material may be a metal that can be used as a general semiconductor electrode, such as Mo, Cr, Al, Ti, Cu, or an alloy mainly composed of these metals. The thickness of the gate electrode is set in consideration of workability of the gate electrode, resistance of the gate electrode, laser absorption rate, etc., but a thickness of about 50 to 500 nm is desirable.

After that, a predetermined light is irradiated to the oxide semiconductor layer 3 from the upper surface (the side of the gate electrode 5). Here, light is irradiated through the translucent gate insulating film 4. A laser having high directivity and a constant wavelength is desirable as the irradiation light. By this laser irradiation, the oxide semiconductor (IGZTO) irradiated with the laser has a low resistance, and a source region 3a and a drain region 3b are formed. The laser needs to be a laser in a wavelength range that can be absorbed by the oxide semiconductor, and ultraviolet light is desirable. For example, a YAG laser can be used. The light to be irradiated is not limited to the solid-state laser, and any laser such as an excimer laser such as an XeCl excimer laser and a CW laser can be used. Further, a flash lamp may be used. It is desirable that the light irradiation be in the form of a pulse. Further, as will be described later, it is desirable that the irradiation intensity of the laser beam is 120 mJ / cm ^{2 or more.}

The laser is reflected in the region where the gate electrode 5 is formed, and only the region of the oxide semiconductor layer 3 that is not covered by the gate electrode 5 (does not overlap with the gate electrode 5) is irradiated with the laser, and the source region 3a and the drain Since the region 3b is formed, the gate electrode 5, the source region 3a, and the drain region 3b are formed by self-alignment (automatic alignment). Since the laser beam has high directivity (straightness), the low resistance source / drain regions 3a and 3b do not enter the lower part of the gate electrode 5.

After that, as shown in FIG. 1 (b), the insulating film 6 covering the thin film transistor is formed. The insulating film 6 functions as a protective film or an interlayer film. As the insulating film 6, for example, PECVD is used to form SiO _x at about 100 to 800 nm. Since there is a problem that the resistance in the region where the resistance is lowered increases depending on the film forming temperature of the insulating film 6, it is possible to appropriately adjust the film forming temperature (for example, 250 ° C. or less) at which the resistance does not increase. preferable. Since _{the insulating film such as SiO x} has high transmission of laser light, laser irradiation may be performed after the insulating film 6 is formed to form the source / drain regions 3a and 3b. In this case, it is not necessary to adjust the film forming temperature in order to suppress the increase in resistance, which has the effect of widening the process margin.

Next, in order to connect the source / drain electrodes 7 (7a, 7b) and the source / drain regions 3a, 3b, holes to be contact holes are formed in the insulating film 6 and the gate insulating film 4 by using photolithography and dry etching. do. Then, the source / drain electrode material is formed by using sputtering. As the source / drain electrode material, any metal used as a wiring / electrode of a semiconductor device such as Mo, Cr, Al, Ti, Cu, or an alloy mainly composed of these metals can be used. The thickness of the electrode material can be appropriately set in consideration of the resistance and workability of the electrodes and wiring, but it is preferably about 50 to 500 nm. The formed metal layer is patterned by photolithography and wet etching to form a source electrode 7a and a drain electrode 7b. This completes the production of the self-aligned thin film transistor in the present invention.

In the thin film transistor according to the above manufacturing method, the oxide semiconductor layer 3, the gate insulating film 4, and the gate electrode 5 are laminated in this order, the oxide semiconductor layer 3 is irradiated with laser using the gate electrode 5 as a mask, and the source / drain region is formed. Since 3a and 3b are formed, the positions of the ends of the gate electrode 5 and the ends of the source / drain regions 3a and 3b provided in the oxide semiconductor layer coincide with each other. Further, since no doping is performed, the source / drain regions 3a and 3b are hardly diffused and the regions are hardly changed. Therefore, by the above manufacturing method, it is possible to form a thin film transistor having a channel length as designed.

(Verification of Examples and their characteristics)
Examples of the present invention are shown below. Here, a self-aligned thin film transistor using the laser-based laser resistance reduction process of the present invention was produced, and its characteristics were verified. Further, as a comparative example, a self-aligned thin film transistor using a conventional Ar plasma low resistance process was produced, and the characteristics were compared with the examples.

In both the examples and the comparative examples, the same process was used until the formation of the gate electrode 5. The manufacturing process of both will be described up to the formation of the gate electrode 5 with reference to FIG. 1 (a).

_{A SiO x} of 100 nm was formed on the glass substrate 1 by using PECVD as the base film 2. Next, the IGZTO film having the composition described in the above-described embodiment was formed under the following film-forming conditions.
Film formation method: DC sputtering method Film formation temperature: Room temperature Gas pressure: 0.2Pa
Carrier gas: Ar
Oxygen partial pressure: 100 × O ₂ / (Ar + O ₂ ) = 30%

An oxide semiconductor (IGZTO) film 3 was formed at 15 nm under the above film forming conditions, and the IGZTO film 3 was patterned using photolithography and wet etching. Next, annealing at 300 ° C. in air using a hot plate was carried out for 1 hour. Annealing improves the mobility and reliability of the thin film transistor.

Next, using PECVD, SiO _x was formed into a film of 140 nm as the gate insulating film 4, and Mo alloy was formed into a film of 70 nm as the gate electrode 5 on the SiO x. The gate electrode 5 was patterned using photolithography and wet etching.

The following steps are different between the laser process of the example and the Ar plasma process of the comparative example.

[Example: Laser process]
A thin film transistor using a laser-based low resistance process and a method for manufacturing the thin film transistor will be described with reference to FIG. 1 (a). In this example, a solid-state YAG laser having a wavelength of 266 nm and a pulse width of 7 ns was used as the laser. Since the laser used _{passes through the SiO x} of the gate insulating film 4, it is not necessary to pattern the gate insulating film 4. This simplifies the process and has the effect of improving throughput. Further, since the processing variation of the gate insulating film, which will be described later, does not occur, it is possible to suppress an increase in parasitic resistance and parasitic capacitance due to processing accuracy.

By irradiating the oxide semiconductor layer 3 with a laser from the upper surface side (the side of the gate electrode 5) of the thin film transistor using the gate electrode 5 as a mask, a source region 3a and a drain region 3b aligned with the gate electrode 5 are formed. did. The laser irradiation intensity will be described later.

Next, as shown in FIG. 1 (b), SiO _x was formed at a film forming temperature of 250 ° C. at 300 nm using PECVD, and this was used as an insulating film (interlayer film) 6.

Next, contact holes were formed in the insulating film (interlayer film) 6 and the gate insulating film 4 by using photolithography and dry etching. Then, the Mo alloy was formed into a film having a thickness of 70 nm by sputtering, and patterned by photolithography and wet etching to form the source / drain electrodes 7 (7a, 7b). This completes the production of a self-aligned thin film transistor using a laser-based low resistance process.

FIG. 3 shows the irradiation intensity dependence of the sheet resistance of the oxide semiconductor (IGZTO). In the experiment, a plurality of samples in which an IGZTO film was formed at 15 nm on glass were prepared, and the irradiation intensity was changed to irradiate the laser. Sheet resistance before laser irradiation was 10 ⁸ Ω / □ or more. The sheet resistance decreased as the irradiation intensity increased, and the sheet resistance became the minimum at 1.9 × 10 ^{3 Ω / □ at the irradiation intensity of 200 mJ / cm 2.} This is a good value equal to or higher than the ^{minimum value of 2 × 10 3} Ω / □ of the sheet resistance when Ar plasma treatment is performed for a long time, which will be described later.

The data for the irradiation intensity of the sheet resistance in FIG. 3 are shown in Table 1 (the unit of the irradiation intensity is mJ / cm ² , and the unit of the sheet resistance is Ω / □).

It is considered that the temperature of the film rises as the irradiation intensity increases. As the temperature rises, the bond between the metal ion and the oxygen ion is broken, oxygen deficiency is formed in the IGZTO, and at the same time, free electrons are generated and the carrier density rises. As a result, the resistance of the laser irradiation region of the oxide semiconductor is reduced while the composition of the metal element remains constant. However, if the irradiation intensity is too strong, the sheet resistance tends to increase again.

The sheet resistance that can be used as the source / drain region of the field effect transistor is shown as 1.0 × 10 ⁵ Ω / □ or less at an irradiation intensity of 120 mJ / cm ^{2 or more.} Further, when the irradiation intensity is 150 to 240 mJ / cm ² , the value is 1.9 × 10 ^{3 to} 3.7 × 10 ³ Ω / □, which is almost the same as the minimum value, and it can be said that the process margin is wide.

Estimating based on the measured sheet resistance, oxygen deficiency of 1.5 × 10 ¹⁸ cm ^-3 or more is formed in the IGZTO at an irradiation intensity of 120 mJ / cm ² or more, and an irradiation intensity of 150 to 240 mJ / cm. ^{In 2} , an oxygen deficiency of 3.8 × 10 ¹⁹ cm ^-3 or more is formed.

FIG. 4 shows the transmission characteristics of thin film transistors having different laser irradiation intensities. The voltage-current characteristics of a self-aligned thin film transistor manufactured by performing a low resistance process under the conditions of laser irradiation intensity of 100, 120, and ^{200 mJ / cm 2 are shown.} The channel length (L) is 10 μm, and the channel width (W) is 50 μm (channel length and channel width are design values). Each sheet resistance of IGZTO the irradiation intensity 100,120,200mJ / cm ^2, 10 ⁸ or more, 7.3 × 10 ^4, was 1.9 × 10 ³ Ω / □. As the irradiation intensity increased, the on-current increased. Since the resistance in the source / drain region acts as a parasitic resistance, a decrease in the on-current is caused when ^{the sheet resistance is high and the irradiation intensity is 100 mJ / cm 2.} When the irradiation intensity was 120 mJ / cm ^{2 , 10-6} (A) could be secured as the on-current. When the irradiation intensity is 200 mJ / cm ² , the sheet resistance of the source / drain current is negligibly small as compared with the channel resistance. The on-current was 10 ^-5 (A) at an irradiation intensity of 200 mJ / cm ² , and a mobility of 31 cm ² / Vs was obtained. This mobility was about 3 times that of IGZO, which is a typical oxide semiconductor material in the past.

[Comparative example: Ar plasma process]
As a comparative example, a thin film transistor using a process for reducing resistance by Ar plasma treatment and a method for manufacturing the thin film transistor will be described.

The same manufacturing conditions and steps as in the examples shown in FIG. 1A were used up to the formation of the substrate 1, the base film 2, the oxide semiconductor (IGZTO) film 3, the gate insulating film 4, and the gate electrode 5. The following steps will be described with reference to FIG. 2 (a).

In the case of the Ar plasma process, since it is necessary to expose the Ar plasma to the IGZTO film 3, the gate insulating film 4 above the IGZTO film 3 which is the source / drain region is removed by etching. _{In this treatment, the SiO x} of the gate insulating film 4 was patterned by dry etching using the gate electrode 5 as a mask, so that the gate electrode 5 and the removed portion of the insulating film 4 were self-aligned.

Next, Ar plasma treatment was carried out for 3 minutes to form a source region 3a and a drain region 3b. For IGZTO of thickness 15 nm, in the practice of the Ar plasma for 3 minutes, 10 ⁸ Ω / □ sheet resistance is lowered to 2 × 10 ³ Ω / □. It was confirmed that when the treatment time of Ar plasma is 3 minutes or less, the resistance tends to decrease as the irradiation time is longer, and the resistance becomes almost the same when the treatment time is 3 minutes or more.

When the gate insulating film 4 is etched using the gate electrode 5 as a mask, processing variations always occur with respect to the size of the gate electrode 5. In FIG. 2A, when the width of the gate insulating film 4 is larger than that of the gate electrode 5 (when the insulating film is tapered on the outside of the gate electrode), the channel region and the source / drain regions 3a and 3b under the gate electrode 5 are formed. An offset region that is not reduced in resistance is formed between the two. At this time, the offset region becomes a parasitic resistance and becomes a factor of reducing the on-current of the thin film transistor. Further, when the width of the gate insulating film 4 is smaller than that of the gate electrode 5 (when overetching occurs), the source / drain regions 3a and 3b invade the channel region. In this case, the gate electrode 5 and the source / drain regions 3a and 3b overlap each other, which causes an increase in parasitic capacitance.

Further, as described later, even if the side surfaces of the gate electrode 5 and the gate insulating film 4 are aligned with each other, the Ar plasma collides in a random direction, so that the exposed region of the IGZTO film 3 also moves downward from the gate insulating film 4. enter in. Therefore, the source / drain regions 3a and 3b tend to diffuse to the lower part of the gate electrode 5.

Next, as shown in FIG. 2B, a SiO _x of 300 nm was formed at a film forming temperature of 250 ° C. using PECVD to form an insulating film (interlayer film) 6, and further, photolithography and dry etching were used. Contact holes reaching the source / drain regions 3a and 3b were formed in the insulating film (interlayer film) 6. A Mo alloy to be a source / drain electrode 7 was formed into a 70 nm film by sputtering, and this was patterned by photolithography and wet etching to form a source electrode 7a and a drain electrode 7b. This completes the production of a self-aligned thin film transistor using a process of reducing resistance with Ar plasma.

(Comparison between laser process and plasma process)
The characteristics of the field-effect transistor using the laser-based low resistance process and the field-effect transistor using the Ar plasma low-resistance process were compared.

First, in order to investigate the effect of suppressing the shift of the threshold voltage in a short channel, the channel length dependence of the transfer characteristics in the self-aligned thin film transistor produced by the laser process and the Ar plasma process was evaluated. FIG. 5 shows the channel length dependence of the threshold voltage Vt of the thin film transistor by laser irradiation and Ar plasma processing. The threshold voltage Vt is the gate voltage at which the current value Id × (L / W) obtained by normalizing the drain current (Id) with the gate width (W) and the channel length (L) is 10 ^-9 A. It was derived by defining it as the value voltage Vt.

As is clear from FIG. 5, in both processes, when the channel length (L) was 5 μm or more, the Vt was almost the same. However, in the case of Ar plasma treatment, when the channel length (L) becomes 4 μm or less, the threshold voltage Vt rapidly shifts to the negative side. On the other hand, in the case of laser irradiation, when the channel length (L) becomes 3 μm or less, the threshold voltage Vt shifts to the negative side, but the tendency is gradual.

When a thin film transistor having a large Vt shift is used in a pixel circuit or a drive circuit, a larger drive voltage is required, which causes a problem of increased power consumption. When the channel length L (design value) was 2 μm or less in the Ar plasma treatment, the OFF current was very high and switching characteristics could not be obtained. This is because in the Ar plasma process, Ar ions collide with IGZTO in random directions, and Ar ions traveling diagonally also penetrate under the gate electrode 5, and due to the long processing time of 3 minutes, the source. -It is considered that this is because the low resistance regions, which are the drain regions 3a and 3b, are diffused in the channel region. When the low resistance region diffuses into the channel region, the carrier density in the channel region increases, and the negative gate voltage required to obtain the OFF characteristic increases.

In the case of Ar plasma treatment, even if plasma irradiation is performed using the gate electrode 5 as a mask, the source / drain regions 3a and 3b are diffused under the gate electrode, and the gate electrode 5 ends and the source / drain regions 3a and 3b are diffused. It was confirmed that accurate alignment of the edges could not be achieved.

FIG. 6 shows the transmission characteristics of the thin film transistor by laser irradiation and Ar plasma processing. The gate voltage-drain current characteristics of the top gate thin film transistors with channel lengths L = 3 μm and 1 μm by each process are shown. The gate width W was fixed at 10 μm, and the measurement was performed at a drain voltage of 0.1 V.

As is clear from FIGS. 5 and 6 (a), no large negative Vt shift was observed at L = 3 μm in the laser process. Further, as shown in FIG. 6 (b), although a shift of Vt to the negative side was observed at L = 1 μm, in the laser process, switching performance was obtained even at L = 1 μm. These results show that the processing time is very short with a pulse width of 7 ns, and that the diffusion of the source / drain regions 3a and 3b into the channel region is suppressed by the irradiation process of the laser having high directivity. Is due to.

On the other hand, in the thin film transistor by the Ar plasma process, at L = 3 μm, a large shift to the negative side of Vt occurs as compared with the thin film transistor by laser irradiation. Further, when L = 1 μm, the drain current could not be controlled by the gate voltage, and the switching characteristic could not be obtained.

As described above, by applying IGZTO to the semiconductor layer of the thin film transistor and manufacturing the thin film transistor by using a laser-based low resistance process, self-mobility and the shift of the threshold voltage Vt to the negative side are suppressed. It is possible to realize a matched thin film transistor.

Although the present invention has been described based on the drawings, embodiments and examples, it should be noted that those skilled in the art can easily make various modifications and modifications based on the present disclosure. Therefore, the present invention should not be construed as being limited by the above-described embodiments, and various modifications and modifications can be made without departing from the scope of claims.

1 Substrate 2 Base film 3 Oxide semiconductor layer 4 Gate insulating film 5 Gate electrode 6 Insulation film 7 Source / drain electrode

Claims (9)

A method for manufacturing a thin film transistor in which at least an oxide semiconductor layer, a gate insulating film, and a gate electrode are formed on a substrate in this order.
The metal element constituting the oxide semiconductor layer contains In, Ga, Zn, and Sn, and contains In, Ga, Zn, and Sn.
The oxide semiconductor layer is irradiated with a predetermined light from the side of the gate electrode to reduce the resistance of the region of the oxide semiconductor layer that does not overlap with the gate electrode, thereby forming a source / drain region. A method for manufacturing a thin film transistor. In the method for manufacturing a thin film transistor according to claim 1,
The ratio of each metal element to the total of all metal elements (In + Ga + Zn + Sn) in the oxide semiconductor layer is
In: 45 atomic% or more and 65 atomic% or less,
Ga: 5 atomic% or more and 16 atomic% or less,
A method for manufacturing a thin film transistor, characterized in that Zn: 10 atomic% or more and 40 atomic% or less, and Sn: 3 atomic% or more and 10 atomic% or less. In the method for manufacturing a thin film transistor according to claim 2.
A method for manufacturing a thin film transistor, wherein the ratio of In to the total of all metal elements (In + Ga + Zn + Sn) is 50 atomic% or more and 60 atomic% or less. In the method for manufacturing a thin film transistor according to any one of claims 1 to 3.
A method for manufacturing a thin film transistor, characterized in that the irradiation intensity of light is 120 mJ / cm ^{2 or more.} In the method for manufacturing a thin film transistor according to any one of claims 1 to 4.
A method for manufacturing a thin film transistor, wherein the irradiation intensity of the light is 150 to 240 mJ / cm ^2. The method for manufacturing a thin film transistor according to any one of claims 1 to 5.
A method for manufacturing a thin film transistor, which comprises irradiating the oxide semiconductor layer with the predetermined light through the gate insulating film to form the source / drain region. A thin film transistor in which at least an oxide semiconductor layer, a gate insulating film, and a gate electrode are laminated in this order on a substrate.
The metal element constituting the oxide semiconductor layer contains In, Ga, Zn, and Sn, and contains In, Ga, Zn, and Sn.
The positions of the end of the gate electrode and the end of the source / drain region provided in the oxide semiconductor layer are the same.
A thin film transistor having the same metal element composition as the oxide semiconductor layer in the source / drain region and having a sheet resistance lower than that of the channel region. In the thin film transistor according to claim 7,
The ratio of each metal element to the total of all metal elements (In + Ga + Zn + Sn) in the oxide semiconductor layer is
In: 45 atomic% or more and 65 atomic% or less,
Ga: 5 atomic% or more and 16 atomic% or less,
A thin film transistor having Zn: 10 atomic% or more and 40 atomic% or less, and Sn: 3 atomic% or more and 10 atomic% or less. In the thin film transistor according to claim 7 or 8.
The source / drain region is a thin film transistor characterized by having an oxygen deficiency of ^{1.5 × 10 18} cm ^{-3 or more.}

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