JP2021182687A - Front-end module - Google Patents

Abstract

To provide a front-end module capable of suppressing deterioration in performance.SOLUTION: A front-end module 1 comprises: a PA1 that amplifies a first transmission signal; a PA2 that amplifies a second transmission signal; an LNA1 that amplifies a first reception signal; an LNA2 that amplifies a second reception signal; an FIL1 that filters the first transmission signal or the first reception signal; an FIL2 that filters the second transmission signal or the second reception signal; a TX/RXSW1 that switches the first transmission signal and the first reception signal to be passed through the FIL1; and a TX/RXSW2 that switches the second transmission signal and the second reception signal to be passed through the FIL 2. A substrate 2 has: a first region 100 where the PA1 and the FIL1 are mounted; a second region 200 where the PA2 and the FIL2 are mounted; and a third region 300 where the LNA1, the LNA2, the TX/RXSW1 and the TX/RXSW2 are mounted.SELECTED DRAWING: Figure 2

Description

The present invention relates to a front-end module.

In recent years, the development of front-end modules compatible with the 5th generation mobile communication system (hereinafter, also simply referred to as "5G"), which is a new communication standard for mobile terminals, has been promoted. The front-end module is an ultra-compact integrated module that integrates various functional components used in wireless front-end circuits such as PA (Power Amp) and LNA (Low Noise Amp). In the front-end module, for example, a plurality of functional devices are mounted on an LTCC (Low Temperature Co-fired Ceramics) or a dielectric substrate.

When a plurality of functional devices are mounted on one board to form a front-end module, performance deterioration may occur depending on the arrangement of the functional devices. For example, if the transmission path of the transmission / reception signal becomes long, the propagation loss of the transmission / reception signal may increase. Further, in a configuration having a plurality of PAs, the heat generated by each PA may affect each other, resulting in deterioration of the amplification characteristics. Further, in a configuration having a plurality of filter circuits, isolation between the circuits may deteriorate.

The present disclosure has been made in view of the above, and an object of the present disclosure is to realize a front-end module capable of suppressing performance deterioration.

The front-end module on one aspect of the present disclosure is a front-end module in which a plurality of circuit blocks are mounted on a substrate, and the circuit blocks are a first power amplifier circuit for amplifying a first transmission signal and a second transmission. The second power amplifier circuit that amplifies the signal, the first low noise amplifier circuit that amplifies the first received signal, the second low noise amplifier circuit that amplifies the second received signal, and the first transmission signal or the first reception signal are filtered. First transmission / reception that switches between the first filter circuit, the second filter circuit that filters the second transmission signal or the second reception signal, and the first transmission signal and the first reception signal that pass through the first filter circuit. The substrate includes a switching circuit and a second transmission / reception switching circuit for switching between the second transmission signal and the second reception signal passing through the second filter circuit, and the substrate includes the first power amplifier circuit and the first. The first region in which the filter circuit is mounted, the second region in which the second power amplifier circuit and the second filter circuit are mounted, the first low noise amplifier circuit, the second low noise amplifier circuit, and the first transmission / reception It has a switching circuit and a third region on which the second transmission / reception switching circuit is mounted, and the first region and the second region are arranged so as to sandwich the third region. And.

In this configuration, the transmission path of the first received signal and the second received signal and the transmission path of the first transmitted signal and the second transmitted signal can be shortened, and the propagation loss of each transmitted / received signal can be reduced. .. Further, it is possible to suppress deterioration of the amplification characteristics due to heat generation of the first power amplifier circuit and the second power amplifier circuit. In addition, deterioration of isolation between the first filter circuit and the second filter circuit can be suppressed.

Further, by sandwiching the third region between the first region and the second region, it is possible to prevent the signal amplified by the first power amplifier circuit in the first region from leaking into the second region. Further, it is possible to prevent the signal amplified by the second power amplifier in the second region from leaking into the first region.

The front-end module includes a decoupling capacitor of a power supply voltage applied to the first power amplifier circuit and the second power amplifier circuit, and a decoupling capacitor switching circuit for switching the capacitance value of the decoupling capacitor. The decoupling capacitor and the decoupling capacitor switching circuit are mounted in the third region.

In this configuration, the wiring between the decoupling capacitor switching circuit and the decoupling capacitor can be shortened. Further, the wiring between the decoupling capacitor and the first region and the wiring between the decoupling capacitor and the second region can be shortened. As a result, deterioration of the smoothing function can be suppressed.

The front-end module according to one aspect of the present disclosure is a front-end module in which a plurality of devices are mounted on a substrate, wherein the device is a first chip device including a first power amplifier circuit for amplifying a first transmission signal. , A second chip device including a second power amplifier circuit that amplifies the second transmission signal, a first low noise amplifier circuit that amplifies the first received signal, a second low noise amplifier circuit that amplifies the second received signal, the first. A first transmission / reception switching circuit that switches between the first transmission signal and the first reception signal that passes through the filter circuit, and a second transmission signal that switches between the second transmission signal and the second reception signal that passes through the second filter circuit. 2 A third chip device including a transmission / reception switching circuit, a component of a first filter circuit for filtering a first transmission signal or a first reception signal, and a second filter circuit for filtering a second transmission signal or a second reception signal. The third chip device includes the components, the first chip device and the components of the first filter circuit, and the second chip device and the components of the second filter circuit on the substrate. It is characterized in that it is mounted at a position that sandwiches.

In this configuration, the transmission path of the first received signal and the second received signal and the transmission path of the first transmitted signal and the second transmitted signal can be shortened, and the propagation loss of each transmitted / received signal can be reduced. .. In addition, deterioration of amplification characteristics due to heat generation of the first chip device and the second chip device can be suppressed. In addition, deterioration of isolation between the components of the first filter circuit and the components of the second filter circuit can be suppressed.

Further, by mounting the components of the first chip device and the first filter circuit and the components of the second chip device and the second filter circuit at positions sandwiching the third chip device, the first chip device can be first. It is possible to prevent the signal amplified by the 1 power amplifier circuit from leaking to the second chip device. Further, it is possible to prevent the signal amplified by the second power amplifier of the second chip device from leaking to the first chip device.

The front-end module includes a decoupling capacitor of a power supply voltage applied to the first power amplifier circuit and the second power amplifier circuit, and a decoupling capacitor switching circuit for switching the capacitance value of the decoupling capacitor. The decoupling capacitor switching circuit is provided in the third chip device, and the decoupling capacitor is mounted adjacent to the third chip device.

In this configuration, the wiring between the decoupling capacitor switching circuit and the decoupling capacitor can be shortened. Further, the wiring between the decoupling capacitor and the first chip device and the wiring between the decoupling capacitor and the second chip device can be shortened. As a result, deterioration of the smoothing function can be suppressed.

The front-end module is characterized by including a shield case that covers the substrate.

According to the present disclosure, it is possible to realize a front-end module capable of suppressing performance deterioration.

It is a schematic diagram which shows the circuit block composition of the front-end module which concerns on embodiment. It is a schematic diagram which shows the modification of the circuit block composition of the front-end module which concerns on embodiment. It is a schematic diagram which shows the modification of the circuit block composition of the front-end module which concerns on embodiment. It is a schematic diagram which shows the modification of the circuit block composition of the front-end module which concerns on embodiment. It is a schematic diagram which shows the modification of the circuit block composition of the front-end module which concerns on embodiment. It is a schematic diagram which shows the modification of the circuit block composition of the front-end module which concerns on embodiment. It is a schematic diagram which shows the modification of the circuit block composition of the front-end module which concerns on embodiment. It is a schematic diagram which shows the modification of the circuit block composition of the front-end module which concerns on embodiment. It is a schematic diagram which shows the modification of the circuit block composition of the front-end module which concerns on embodiment. It is a figure which shows an example of the circuit arrangement of the front-end module which concerns on embodiment. It is a figure which shows the circuit arrangement of the front-end module which concerns on 1st comparative example. It is a figure which shows the circuit arrangement of the front-end module which concerns on 2nd comparative example. It is a schematic diagram which shows the transmission path of the 1st receive signal and the 2nd receive signal in the front-end module which concerns on embodiment. It is a schematic diagram which shows the transmission path of the 1st transmission signal and the 2nd transmission signal in the front-end module which concerns on embodiment. It is a schematic diagram which shows the rationality of the arrangement of the 1st chip device and the 2nd chip device in the front-end module which concerns on embodiment. It is a schematic diagram which shows the rationality of the arrangement of the 1st filter circuit and the 2nd filter circuit in the front-end module which concerns on embodiment. FIG. 7 is a vertical sectional view taken along the line AA shown in FIG. It is a schematic diagram which shows the rationality of the arrangement of the decoupling capacitor in the front-end module which concerns on embodiment. It is a modification of the schematic diagram which shows the rationality of the arrangement of the decoupling capacitor in the front-end module which concerns on embodiment. It is a modification of the schematic diagram which shows the rationality of the arrangement of the decoupling capacitor in the front-end module which concerns on embodiment.

Hereinafter, the front-end module according to the embodiment will be described in detail with reference to the drawings. The present disclosure is not limited to this embodiment.

FIG. 1A is a schematic diagram showing a circuit block configuration of a front-end module according to an embodiment. 1B to 1I are schematic views showing a modified example of the circuit block configuration of the front-end module according to the embodiment. FIG. 2 is a diagram showing an example of a circuit arrangement of a front-end module according to an embodiment. The front-end module 1 according to the present embodiment is an ultra-compact integrated module in which a plurality of integrated circuits mounted on a substrate 2 and various functional components are integrated. The substrate 2 is exemplified by a ceramic laminated substrate such as an LTCC (Low Temperature Co-fired Ceramics) substrate. Hereinafter, first, the circuit block configuration shown in FIG. 1A will be described.

As shown in FIG. 1A, the front-end module 1 according to the first embodiment has a first power amplifier circuit (hereinafter, also referred to as “PA1”) and a second power amplifier circuit (hereinafter, “PA2”) as main functional blocks. ”), A first low noise amplifier (hereinafter, also referred to as“ LNA1 ”), a second low noise amplifier (hereinafter, also referred to as“ LNA2 ”), and a first filter circuit (hereinafter, also referred to as“ FIL1 ”). , The second filter circuit (hereinafter, also referred to as "FIL2"), the first power amplifier transmission power switching circuit (hereinafter, also referred to as "PASW1"), and the second power amplifier transmission power switching circuit (hereinafter, also referred to as "PASW2"). (Hereinafter referred to as), a decoupling amplifier switching circuit (hereinafter, also referred to as “PACAPSW”), a first transmission / reception switching circuit (hereinafter, also referred to as “TX / RXSW1”), and a second transmission / reception switching circuit (hereinafter, “TX / RXSW2”). ”), An antenna switching circuit (hereinafter, also referred to as“ ANTSW ”), a power amplifier control circuit (hereinafter, also referred to as“ PAC ”), and a low noise amplifier control circuit (hereinafter, also referred to as“ LNAC ”). To prepare for.

PA1 amplifies the first transmission signal input from the transmission signal input terminal TX1. PA2 amplifies the second transmission signal input from the transmission signal input terminal TX2. For example, in the circuit block configuration shown in FIG. 1A, PA1 and PA2 are configured by connecting three stages of amplifier circuits, a first stage, a power stage, and a drive stage, in series. Each of the amplifier circuits of the first stage, the power stage, and the drive stage performs an amplification operation by applying a power supply voltage from each of the power supply voltage terminals VCS1, VCC2, and VCS3, respectively.

PA1 and PA2 are an envelope tracking (ET: Envelope Tracking) method that improves power efficiency by controlling the power supply voltage of the power amplifier according to the amplitude level of the input signal, and the power amplifier according to the average output power. Power amplification is performed by switching between the average power tracking (APT) method, which improves power efficiency by controlling the power supply voltage.

The PA1 and PA2 may be composed of, for example, a bipolar transistor, or may be composed of, for example, a field effect transistor (FET). When PA1 and PA2 are composed of bipolar transistors, for example, a heterojunction bipolar transistor (HBT) is exemplified. The present disclosure is not limited by the configurations of PA1 and PA2.

The PACAPSW switches the impedance of the power supply line connected to the power supply voltage terminal VCS3 (in the circuit block configuration shown in FIG. 1A, the power supply wiring of the drive stage amplifier circuit of PA1 and PA2). Specifically, when the power supply line connected to the power supply voltage terminal VCC3 has a low impedance, for example, when performing APT method power amplification in PA1 and PA2, PACAPSW is turned on and connected to the power supply voltage terminal VCS3. When the power supply line has a high impedance, for example, the PACAPSW is off-controlled when the power amplification of the ET method is performed in PA1 and PA2. The impedance of the power supply line connected to the power supply voltage terminal VCS3 when the PACAPSW is turned on is determined by the capacitance value of the decoupling capacitor connected between the power supply voltage terminal VCS3 and the PACAPSW.

PASW1 switches the gain of PA1. Specifically, PASW1 switches the amplifier circuit for inputting the first transmission signal. In the circuit block configuration shown in FIG. 1A, it is switched whether the first transmission signal is input to the first stage amplifier circuit of PA1 or the power stage amplifier circuit. The PA1 operates in the so-called high power mode when the first transmission signal is input to the first stage amplifier circuit, and operates in the so-called low power mode when the first transmission signal is input to the power stage amplifier circuit. The present disclosure is not limited by the configuration of the connection points of PASW1 and PA1.

PASW2 switches the gain of PA2. Specifically, PASW2 switches the amplifier circuit for inputting the second transmission signal. In the circuit block configuration shown in FIG. 1A, it is switched whether the second transmission signal is input to the first stage amplifier circuit of PA2 or the power stage amplifier circuit. The PA2 operates in the so-called high power mode when the second transmission signal is input to the first stage amplifier circuit, and operates in the so-called low power mode when the second transmission signal is input to the power stage amplifier circuit. The present disclosure is not limited by the configuration of the connection points of PASW2 and PA2.

The LNA1 amplifies the first received signal input from the antenna terminals ANT1, ANT2, ANT3, and ANT4. For example, in the circuit block configuration shown in FIG. 1A, the first received signal amplified by LNA1 is output from the received signal output terminal RX1.

The LNA2 amplifies the second received signal input from the antenna terminals ANT1, ANT2, ANT3, and ANT4. For example, in the circuit block configuration shown in FIG. 1A, the second received signal amplified by LNA2 is output from the received signal output terminal RX2.

In the circuit block configuration shown in FIG. 1A, the TX / RXSW1 switches between a first transmission signal output from PA1 and a first reception signal to LNA1. Specifically, when the TX / RXSW1 transmits the first transmission signal, the TX / RXSW1 outputs the first transmission signal output from the PA1 to the FIL1. Further, when the TX / RXSW1 receives the first reception signal, the TX / RXSW1 outputs the first reception signal output from the FIL1 to the LNA1.

In the circuit block configuration shown in FIG. 1A, the TX / RXSW2 switches between a second transmission signal output from PA2 and a second reception signal to LNA2. Specifically, when the TX / RXSW2 transmits the second transmission signal, the TX / RXSW2 outputs the second transmission signal output from the PA2 to the FIL2. Further, when the TX / RXSW2 receives the second reception signal, the TX / RXSW2 outputs the second reception signal output from the FIL2 to the LNA2.

FIL1 filters the first transmission signal or the first reception signal. Specifically, when transmitting the first transmission signal, the FIL1 filters the first transmission signal and outputs it to the ANTSW. Further, when the FIL1 receives the first received signal, the FIL1 filters the first received signal and outputs it to the TX / RXSW1.

FIL2 filters the second transmitted signal or the second received signal. Specifically, when the FIL2 transmits the second transmission signal, the FIL2 filters the second transmission signal and outputs it to the ANTSW. Further, when the FIL2 receives the second received signal, the FIL2 filters the second received signal and outputs it to the TX / RXSW2.

The ANTSW switches the transmission / reception path of the first transmission signal, the first reception signal, the second transmission signal, and the second reception signal. Specifically, the ANTSW switches the output destination (antenna terminals ANT1, ANT2, ANT3, ANT4) of the first transmission signal input from the FIL1. Further, the ANTSW switches the output destination (antenna terminals ANT1, ANT2, ANT3, ANT4) of the second transmission signal input from the FIL2. Further, the ANTSW switches the output destination (FIL1, FIL2) of the received signal input from the antenna terminals ANT1, ANT2, ANT3, and ANT4. Although FIG. 1 illustrates a configuration having four antenna terminals ANT1, ANT2, ANT3, and ANT4, the number of antenna terminals is not limited to this.

The PAC mainly controls PA1 and PA2. Further, in the configuration of the present disclosure, the PAC controls switching between PASW1, PASW2, PACAPSW, TX / RXSW1, TX / RXSW2, and ANTSW.

LNAC mainly controls LNA1 and LNA2.

The circuit block configuration shown in FIG. 1A has been described above. Hereinafter, a modified example of the circuit block configuration shown in FIGS. 1B to 1I will be described. In the following modified examples of the circuit block configuration shown in FIGS. 1B to 1I, the same components as the circuit block configuration shown in FIG. 1A are the same as those in FIG. 1A, and thus the description thereof will be omitted.

In the circuit block configuration shown in FIG. 1B, PASW1 switches whether the first transmission signal is input to the first stage amplifier circuit of PA1 or the drive stage amplifier circuit. Further, in the circuit block configuration shown in FIG. 1B, the PASW2 switches whether the second transmission signal is input to the first stage amplifier circuit of the PA2 or the drive stage amplifier circuit.

In the circuit block configuration shown in FIG. 1C, in each of PA1 and PA2, two first-stage amplifier circuits are connected in parallel to the power stage amplifier circuit. PASW1 switches the first-stage amplifier circuit for inputting the first transmission signal. PASW2 switches the first-stage amplifier circuit for inputting the second transmission signal.

In the circuit block configuration shown in FIG. 1D, in each of PA1 and PA2, two first-stage amplifier circuits are connected in parallel to the drive stage amplifier circuit. PASW1 switches the first-stage amplifier circuit for inputting the first transmission signal. PASW2 switches the first-stage amplifier circuit for inputting the second transmission signal.

In the circuit block configuration shown in FIG. 1E, PA1 and PA2 are configured by connecting two-stage amplifier circuits in series, unlike the configuration shown in FIG. 1A. In PA1 and PA2, two first-stage amplifier circuits are connected in parallel to the second-stage amplifier circuit, respectively. PASW1 switches the first stage amplifier circuit for inputting the first transmission signal.

In the circuit block configuration shown in FIG. 1F, PA1 and PA2 each include an amplifier circuit having a three-stage configuration and an amplifier circuit having a one-stage configuration. The PASW1 switches between inputting the first transmission signal to the amplifier circuit having a three-stage configuration and inputting the first transmission signal to the amplifier circuit having a one-stage configuration. The PASW2 switches whether the second transmission signal is input to the amplifier circuit having a three-stage configuration or the amplifier circuit having a one-stage configuration. When the TX / RXSW1 transmits the first transmission signal, the TX / RXSW1 switches between the output of the amplifier circuit having a three-stage configuration and the output of the amplifier circuit having a one-stage configuration of PA1. When the TX / RXSW2 transmits the second transmission signal, the TX / RXSW2 switches between the output of the amplifier circuit having a three-stage configuration and the output of the amplifier circuit having a one-stage configuration of PA2.

In the circuit block configuration shown in FIG. 1G, PA1 and PA2 each include a two-stage amplifier circuit and a one-stage amplifier circuit. The PASW1 switches between inputting the first transmission signal to the amplifier circuit having a two-stage configuration and inputting it to the amplifier circuit having a one-stage configuration. The PASW2 switches between inputting the second transmission signal to the amplifier circuit having a two-stage configuration and inputting it to the amplifier circuit having a one-stage configuration. When the TX / RXSW1 transmits the first transmission signal, the TX / RXSW1 switches between the output of the amplifier circuit having a two-stage configuration and the output of the amplifier circuit having a one-stage configuration of PA1. When the TX / RXSW2 transmits the second transmission signal, the TX / RXSW2 switches between the output of the amplifier circuit having a two-stage configuration and the output of the amplifier circuit having a one-stage configuration of PA2.

In the circuit block configuration shown in FIG. 1H, PA1 and PA2 include an amplifier circuit having a three-stage configuration and an amplifier circuit having a two-stage configuration, respectively. The PASW1 switches between inputting the first transmission signal to the amplifier circuit having a three-stage configuration and inputting it to the amplifier circuit having a two-stage configuration. The PASW2 switches whether the second transmission signal is input to the amplifier circuit having a three-stage configuration or the amplifier circuit having a two-stage configuration. When the TX / RXSW1 transmits the first transmission signal, the TX / RXSW1 switches between the output of the amplifier circuit having a three-stage configuration and the output of the amplifier circuit having a two-stage configuration of PA1. When the TX / RXSW2 transmits the second transmission signal, the TX / RXSW2 switches between the output of the amplifier circuit having a three-stage configuration and the output of the amplifier circuit having a two-stage configuration of PA2.

In the circuit block configuration shown in FIG. 1I, LNA1 and LNA2 each include two amplifier circuits. The TX / RXSW1 switches and outputs the first received signal to one of the two amplifier circuits constituting the LNA1. The TX / RXSW2 switches and outputs the second received signal to one of the two amplifier circuits constituting the LNA2.

Each circuit block configuration shown in FIGS. 1A to 1I described above is an example, and each circuit configuration of PA1 and PA2, each circuit configuration of LNA1 and LNA2, a switching mode of PASW1 and PASW2, and switching of TX / RXSW1 and TX / RXSW2. The present disclosure is not limited by aspects.

When a plurality of functional devices constituting each circuit block illustrated in FIGS. 1A to 1I described above are mounted on one board 2 to form a front-end module 1, performance deterioration may occur depending on the arrangement of the functional devices. Can be considered. For example, if the transmission path of the transmission / reception signal becomes long, the propagation loss of the transmission / reception signal may increase. In addition, the heat generated by PA1 and PA2 may affect each other, resulting in deterioration of amplification characteristics. In addition, the isolation between FIL1 and FIL2 may deteriorate.

Hereinafter, the arrangement of each circuit block shown in FIG. 1 of the front-end module 1 according to the present embodiment on the substrate 2 will be described with reference to FIG. In the front-end module 1 according to the present embodiment, one surface of the substrate 2 is a component mounting surface. FIG. 2 illustrates a circuit arrangement in which the component mounting surface of the board 2 is viewed.

In the present embodiment, as shown in FIG. 2, the component mounting surface of the substrate 2 is divided into three regions, a first region 100, a second region 200, and a third region 300.

PA1 is included in the first chip device 11 mounted on the substrate 2. The first chip device 11 is composed of, for example, an HBT. Peripheral circuit components of PA1 are mounted around the first chip device 11 in the first region 100 on which the first chip device 11 is mounted. The peripheral circuit component of the PA 1 may be an SMD mounted on the surface of the substrate 2, or may be composed of a conductor provided in the inner layer of the substrate 2.

The FIL 1 is mounted on the first region 100 of the substrate 2. The component 12 of the FIL 1 may be an SMD mounted on the surface of the substrate 2 or may be composed of a conductor provided in the inner layer of the substrate 2. Peripheral circuit components of FIL1 are mounted around FIL1 in the first region 100 on which FIL1 is mounted. The peripheral circuit component of the FIL 1 may be an SMD mounted on the surface of the substrate 2, or may be composed of a conductor provided in the inner layer of the substrate 2.

PA2 is included in the second chip device 21 mounted on the substrate 2. The second chip device 21 is composed of, for example, an HBT. Peripheral circuit components of PA2 are mounted around the second chip device 21 in the second region 200 on which the second chip device 21 is mounted. The peripheral circuit component of the PA 2 may be an SMD mounted on the surface of the substrate 2, or may be composed of a conductor provided in the inner layer of the substrate 2.

The FIL 2 is mounted on the second region 200 of the substrate 2. The component 22 of the FIL 2 may be an SMD mounted on the surface of the substrate 2 or may be composed of a conductor provided in the inner layer of the substrate 2. Peripheral circuit components of FIL2 are mounted around FIL2 in the second region 200 on which FIL2 is mounted. The peripheral circuit component of the FIL 2 may be an SMD mounted on the surface of the substrate 2, or may be composed of a conductor provided in the inner layer of the substrate 2.

LNA1, LNA2, and LNAC are included in the chip device 31 mounted on the substrate 2. The chip device 31 is composed of, for example, CMOS or silicon germanium (SiGe). Peripheral circuit components of LNA1, LNA2, and LNAC are mounted around the chip device 31 in the third region 300 on which the chip device 31 is mounted. Peripheral circuit components of LNA1, LNA2, and LNAC may be surface mount components (Surface Mount Device, hereinafter also referred to as "SMD") mounted on the surface of the substrate 2, or conductors provided in the inner layer of the substrate 2. It may be composed of.

The PAC, PASW1, PASW2, and PACAPSW are included in the chip device 32 mounted on the substrate 2. The chip device 32 is composed of, for example, CMOS or silicon germanium (SiGe). Peripheral circuit components of PAC, PASW1, PASW2, and PACAPSW are mounted around the chip device 32 in the third region 300 on which the chip device 32 is mounted. Peripheral circuit components of PAC, PASW1, PASW2, and PACAPSW may be SMDs mounted on the surface of the substrate 2, or may be composed of conductors provided in the inner layer of the substrate 2.

Further, a decoupling capacitor 34 for lowering the impedance of the power supply line connected to the power supply voltage terminal VCC3 is mounted around the chip device 32 in the third region 300 on which the chip device 32 is mounted. As the decoupling capacitor 34, for example, an SMD mounted on the surface of the substrate 2 is exemplified.

The TX / RXSW1, TX / RXSW2, and ANTSW are included in the chip device 33 mounted on the substrate 2. The chip device 33 is composed of, for example, CMOS or silicon germanium (SiGe). Peripheral circuit components of TX / RXSW1, TX / RXSW2, and ANTSW are mounted around the chip device 33 in the third region 300 on which the chip device 33 is mounted. The peripheral circuit components of the TX / RXSW1, TX / RXSW2, and ANTSW may be an SMD mounted on the surface of the substrate 2, or may be composed of a conductor provided in the inner layer of the substrate 2.

The chip device 31, the chip device 32, and the chip device 33 may be configured by one chip device or may be configured by two chip devices. Hereinafter, when it is not necessary to distinguish the chip device 31, the chip device 32, and the chip device 33, the chip device 31, the chip device 32, and the chip device 33 will be collectively referred to as a third chip device 30.

The front-end module 1 according to the present embodiment has a first region 100 in which the first chip device 11 and the component 12 of the FIL 1 are mounted, and a second region in which the second chip device 21 and the component 22 of the FIL 2 are mounted. The 200 is mounted at a position sandwiching the third region 300 on which the third chip device 30 is mounted.

That is, the front-end module 1 according to the present embodiment has a first region 100 in which PA1 (first power amplifier circuit) and FIL1 (first filter circuit) are mounted, and PA2 (second power amplifier circuit) and FIL2 ( The second area 200 on which the second filter circuit) is mounted, LNA1 (first low noise amplifier), LNA2 (second low noise amplifier), LNAC (low noise amplifier control circuit), PAC (power amplifier control circuit), PASW1 (first). 1 power amplifier transmission power switching circuit), PASW2 (second power amplifier transmission power switching circuit), PACAPSW (decoupling capacitor switching circuit), TX / RXSW1 (first transmission / reception switching circuit), TX / RXSW2 (second transmission / reception switching circuit) ), And a third region 300 on which an ANTSW (amplifier switching circuit) is mounted. The first region 100 and the second region 200 are arranged so as to sandwich the third region 300.

In other words, in the front-end module 1 according to the present embodiment, the position where the component 12 of the first chip device 11 and the FIL1 and the component 22 of the second chip device 21 and the FIL2 sandwich the third chip device 30. It is implemented in. It is preferable that the component 12 of the first chip device 11 and the FIL1 and the component 22 of the second chip device 21 and the FIL2 are symmetrically arranged with the third chip device 30 interposed therebetween.

FIG. 3A is a diagram showing a circuit arrangement of the front-end module according to the first comparative example. FIG. 3B is a diagram showing a circuit arrangement of the front-end module according to the second comparative example. Hereinafter, while comparing with the first example shown in FIG. 3A and the second example shown in FIG. 3B, the rationality of the circuit arrangement of the front-end module 1 according to the present embodiment shown in FIG. 2 is described in FIGS. 4 to 9C. This will be described with reference to the figure.

FIG. 4 is a schematic diagram showing a transmission path of a first received signal and a second received signal in the front-end module according to the embodiment. In FIG. 4, the transmission paths of the first received signal and the second received signal are shown by solid arrows.

FIG. 5 is a schematic diagram showing a transmission path of a first transmission signal and a second transmission signal in the front-end module according to the embodiment. In FIG. 5, the transmission paths of the first transmission signal and the second transmission signal are shown by solid arrows.

In order to reduce the propagation loss of the first received signal and the second received signal, it is necessary to shorten the transmission path of the first received signal and the second received signal. Further, in order to reduce the propagation loss of the first transmission signal and the second transmission signal, it is necessary to shorten the transmission path of the first transmission signal and the second transmission signal.

As shown in FIG. 4, in the circuit arrangement of the front-end module 1 according to the present embodiment, the first received signal and the second received signal from the antenna terminals ANT1, ANT2, ANT3, and ANT4 to the received signal output terminals RX1 and RX2 are The transmission path can be shortened. Specifically, the first received signal is transmitted from the antenna terminals ANT1, ANT2, ANT3, and ANT4 via the paths of the ANTSW, FIL1, TX / RXSW1, LNA1, and the received signal output terminal RX1. Further, the second received signal is transmitted from the antenna terminals ANT1, ANT2, ANT3, and ANT4 via the paths of the ANTSW, FIL2, TX / RXSW2, LNA2, and the received signal output terminal RX2.

Further, as shown in FIG. 5, in the circuit arrangement of the front-end module 1 according to the present embodiment, the first transmission signal and the second transmission from the transmission signal input terminals TX1 and TX2 to the antenna terminals ANT1, ANT2, ANT3, and ANT4. The signal transmission path can be shortened. Specifically, the first transmission signal is transmitted from the reception signal output terminal RX1 via the paths of PASW1, PA1, TX / RXSW1, FIL1, and antenna terminals ANT1, ANT2, ANT3, and ANT4. Further, the second transmission signal is transmitted from the reception signal output terminal RX2 via the paths of PASW2, PA2, TX / RXSW2, FIL2, antenna terminals ANT1, ANT2, ANT3, and ANT4.

In the first comparative example shown in FIG. 3A and the second comparative example shown in FIG. 3B, the transmission path of each transmitted / received signal becomes longer with respect to the circuit arrangement of the front-end module 1 according to the present embodiment, and each transmitted / received signal propagates. The loss may be large.

FIG. 6 is a schematic diagram showing the rationality of the arrangement of the first chip device and the second chip device in the front-end module according to the embodiment.

The first chip device 11 and the second chip device 21 are heat generating components. In order to prevent the heat radiation by the first chip device 11 and the heat radiation by the second chip device 21 from affecting each other, it is necessary to arrange the first chip device 11 and the second chip device 21 apart from each other.

In the first comparative example shown in FIG. 3A and the second comparative example shown in FIG. 3B, since the first chip device 11 and the second chip device 21 are arranged close to each other, the first chip device 11 and the second chip device 21 are arranged in close proximity to each other. There is a possibility that the amplification characteristics will deteriorate due to the influence of heat dissipation from each other.

In the circuit arrangement of the front-end module 1 according to the present embodiment, as shown by the solid line arrow in FIG. 6, the third chip device 30 is mounted between the first chip device 11 and the second chip device 21. Therefore, deterioration of the amplification characteristics due to heat generation of the first chip device 11 and the second chip device 21 can be suppressed.

FIG. 7 is a schematic diagram showing the rationality of the arrangement of the first filter circuit and the second filter circuit in the front-end module according to the embodiment. FIG. 8 is a vertical sectional view taken along the line AA shown in FIG.

The component 12 of FIL1 and the component 22 of FIL2 include a plurality of transmission lines. In a configuration in which the component 12 of FIL1 and the component 22 of FIL2 are arranged close to each other as in the first comparative example shown in FIG. 3A and the second comparative example shown in FIG. 3B, the transmission line of FIL1 and FIL2 serves as an antenna and is isolated. The ration may worsen.

In the circuit arrangement of the front-end module 1 according to the present embodiment, as shown by the solid line arrow in FIG. 7, the third chip device 30 is mounted between the component 12 of the FIL1 and the component 22 of the FIL2. Therefore, deterioration of isolation between FIL1 and FIL2 can be suppressed.

Further, assuming that a plurality of front-end modules 1 are provided, as shown in FIG. 8, a configuration is conceivable in which the component mounting surface of the substrate 2 is covered with the shield case 3. Although the transmission / reception signal may propagate between the FIL1 and the FIL2 through the shield case 3, the third chip device 30 is provided between the component 12 of the FIL1 and the component 22 of the FIL2. As a result, deterioration of isolation can be suppressed as compared with the first comparative example shown in FIG. 3A and the second comparative example shown in FIG. 3B.

FIG. 9A is a schematic diagram showing the rationality of the arrangement of the decoupling capacitor in the front-end module according to the embodiment. 9B and 9C are modified examples of the schematic diagram showing the rationality of the arrangement of the decoupling capacitor in the front-end module according to the embodiment. Hereinafter, FIG. 9A will be described first. In FIG. 9A, the supply path of the power supply voltage VCS3 to PA1 and PA2 and the wiring path of the decoupling capacitor 34 are schematically shown by a solid line.

If the wiring between the PADAPSW and the decoupling capacitor 34 becomes long, the resistance component of the wiring becomes large and the impedance of the power supply voltage VCS3 may become high. Therefore, it is desirable that the wiring between the PACAPSW and the decoupling capacitor 34 is short.

In the circuit arrangement of the front-end module 1 according to the present embodiment, the decoupling capacitor 34 is provided in the third region 300 on which the third chip device 30 is mounted. In the example shown in FIG. 9, the decoupling capacitor C is mounted adjacent to the third chip device 30. Specifically, the decoupling capacitor 34 is located in close proximity to the chip device 32 containing the PACAPSW (see FIG. 2). As a result, the wiring between the PACAPSW and the decoupling capacitor 34 can be shortened.

The FIG. 9A has been described above. Hereinafter, the modified examples shown in FIGS. 9B and 9C will be described. In the following FIGS. 9B and 9C, the same components as those in FIG. 9A are the same as those in FIG. 9A, and thus the description thereof will be omitted.

FIG. 9A shows an example in which the decoupling capacitor 34 is connected between the power supply voltage terminal VCS3 and one end of the PACAPSW, but as shown in FIG. 9B, it is connected between the power supply voltage terminal VCS3 and the PACAPSW. In addition to the decoupling capacitor 34, a decoupling capacitor 34a may be provided between the other end of the PACAPSW and GND. Further, as shown in FIG. 9C, the decoupling capacitor 34 is not provided between the power supply voltage terminal VCC3 and one end of PACAPSW, and the decoupling capacitor 34a is provided between the other end of PACAPSW and GND. May be. The connection points and the number of decoupling capacitors to PACAPSW are not limited to the configuration shown in FIG. 9A and FIG. 9C.

The configurations of PA1 and PA2 and the number of stages of the amplifier circuit are not limited to the configurations disclosed in the above-described embodiment. For example, PA1 and PA2 may be configured by four or more stages of amplifier circuits, or may be configured by one amplifier circuit.

Further, the above-described embodiment is for facilitating the understanding of the present disclosure, and is not for limiting the interpretation of the present invention. The present disclosure may be modified / improved without departing from its spirit, and the present disclosure also includes its equivalents.

The present disclosure may have the following configurations as described above or in place of the above.

(1) The front-end module on one aspect of the present disclosure is a front-end module in which a plurality of circuit blocks are mounted on a substrate, and the circuit blocks include a first power amplifier circuit for amplifying a first transmission signal and a first power amplifier circuit. A second power amplifier circuit that amplifies the second transmission signal, a first low noise amplifier circuit that amplifies the first reception signal, a second low noise amplifier circuit that amplifies the second reception signal, and a first transmission signal or a first reception. The first filter circuit for filtering the signal, the second filter circuit for filtering the second transmission signal or the second reception signal, and the first transmission signal and the first reception signal passing through the first filter circuit are switched. A first transmission / reception switching circuit and a second transmission / reception switching circuit for switching between the second transmission signal and the second reception signal passing through the second filter circuit are included, and the substrate includes the first power amplifier circuit and the first power amplifier circuit. The first region in which the first filter circuit is mounted, the second region in which the second power amplifier circuit and the second filter circuit are mounted, the first low noise amplifier circuit, the second low noise amplifier circuit, and the above. It has a first transmission / reception switching circuit and a third region in which the second transmission / reception switching circuit is mounted, and the first region and the second region are arranged so as to sandwich the third region. It is characterized by that.

In this configuration, the transmission path of the first received signal and the second received signal and the transmission path of the first transmitted signal and the second transmitted signal can be shortened, and the propagation loss of each transmitted / received signal can be reduced. .. Further, it is possible to suppress deterioration of the amplification characteristics due to heat generation of the first power amplifier circuit and the second power amplifier circuit. In addition, deterioration of isolation between the first filter circuit and the second filter circuit can be suppressed.

Further, by sandwiching the third region between the first region and the second region, it is possible to prevent the signal amplified by the first power amplifier circuit in the first region from leaking into the second region. Further, it is possible to prevent the signal amplified by the second power amplifier in the second region from leaking into the first region.

(2) In the front-end module of (1) above, the decoupling capacitor switching between the decoupling capacitor of the power supply voltage applied to the first power amplifier circuit and the second power amplifier circuit and the capacitance value of the decoupling capacitor. A circuit is provided, and the decoupling capacitor and the decoupling capacitor switching circuit are mounted in the third region.

In this configuration, the wiring between the decoupling capacitor switching circuit and the decoupling capacitor can be shortened. Further, the wiring between the decoupling capacitor and the first region and the wiring between the decoupling capacitor and the second region can be shortened. As a result, deterioration of the smoothing function can be suppressed.

(3) The front-end module on one aspect of the present disclosure is a front-end module in which a plurality of devices are mounted on a substrate, and the device includes a first power amplifier circuit for amplifying a first transmission signal. A second chip device including a chip device and a second power amplifier circuit for amplifying a second transmission signal, a first low noise amplifier circuit for amplifying a first received signal, and a second low noise amplifier circuit for amplifying a second received signal. A first transmission / reception switching circuit that switches between the first transmission signal and the first reception signal that passes through the first filter circuit, and the second transmission signal and the second reception signal that pass through the second filter circuit. A third chip device including a second transmission / reception switching circuit for switching, a component of a first filter circuit for filtering a first transmission signal or a first reception signal, and a second for filtering a second transmission signal or a second reception signal. The components of the first chip device and the first filter circuit, and the components of the second chip device and the second filter circuit include the components of the filter circuit, and the components of the first chip device and the first filter circuit are included in the substrate. The feature is that it is mounted at a position sandwiching the 3-chip device.

In this configuration, the transmission path of the first received signal and the second received signal and the transmission path of the first transmitted signal and the second transmitted signal can be shortened, and the propagation loss of each transmitted / received signal can be reduced. .. In addition, deterioration of amplification characteristics due to heat generation of the first chip device and the second chip device can be suppressed. In addition, deterioration of isolation between the components of the first filter circuit and the components of the second filter circuit can be suppressed.

Further, by mounting the components of the first chip device and the first filter circuit and the components of the second chip device and the second filter circuit at positions sandwiching the third chip device, the first chip device can be first. It is possible to prevent the signal amplified by the 1 power amplifier circuit from leaking to the second chip device. Further, it is possible to prevent the signal amplified by the second power amplifier of the second chip device from leaking to the first chip device.

(4) In the front-end module of (3) above, the decoupling capacitor switching between the decoupling capacitor of the power supply voltage applied to the first power amplifier circuit and the second power amplifier circuit and the capacitance value of the decoupling capacitor. The decoupling capacitor switching circuit is provided in the third chip device, and the decoupling capacitor is mounted adjacent to the third chip device.

In this configuration, the wiring between the decoupling capacitor switching circuit and the decoupling capacitor can be shortened. Further, the wiring between the decoupling capacitor and the first chip device and the wiring between the decoupling capacitor and the second chip device can be shortened. As a result, deterioration of the smoothing function can be suppressed.

(5) The front-end module according to any one of (1) to (4) is provided with a shield case for covering the substrate.

According to the present disclosure, it is possible to realize a front-end module capable of suppressing performance deterioration.

1 Front-end module 2 Board 3 Shield case 11 1st chip device 12 Components (1st filter circuit)
21 2nd chip device 22 Components (2nd filter circuit)
30 3rd chip device 31 Chip device 32 Chip device 33 Chip device 34 Decoupling capacitor 100 1st region 200 2nd region 300 3rd region

Claims (5)

A front-end module in which multiple circuit blocks are mounted on a board.
The circuit block is
The first power amplifier circuit that amplifies the first transmission signal and
A second power amplifier circuit that amplifies the second transmission signal,
The first low noise amplifier circuit that amplifies the first received signal, and
The second low noise amplifier circuit that amplifies the second received signal, and
A first filter circuit that filters the first transmission signal or the first reception signal,
A second filter circuit that filters the second transmission signal or the second reception signal,
A first transmission / reception switching circuit that switches between the first transmission signal and the first reception signal that passes through the first filter circuit.
A second transmission / reception switching circuit that switches between the second transmission signal and the second reception signal that passes through the second filter circuit.
Including
The substrate is
The first region in which the first power amplifier circuit and the first filter circuit are mounted, and
A second region in which the second power amplifier circuit and the second filter circuit are mounted, and
A third region in which the first low noise amplifier circuit, the second low noise amplifier circuit, the first transmission / reception switching circuit, and the second transmission / reception switching circuit are mounted.
Have,
A front-end module characterized in that the first region and the second region are arranged so as to sandwich the third region. The front-end module according to claim 1.
A decoupling capacitor of the power supply voltage applied to the first power amplifier circuit and the second power amplifier circuit,
The decoupling capacitor switching circuit that switches the capacitance value of the decoupling capacitor,
Equipped with
The front-end module, wherein the decoupling capacitor and the decoupling capacitor switching circuit are mounted in the third region. A front-end module in which multiple devices are mounted on the board.
The device is
A first chip device including a first power amplifier circuit that amplifies the first transmission signal, and
A second chip device including a second power amplifier circuit that amplifies the second transmission signal, and
The components of the first filter circuit that filters the first transmission signal or the first reception signal, and
A component of the second filter circuit that filters the second transmission signal or the second reception signal, and
A first low noise amplifier circuit that amplifies the first received signal, a second low noise amplifier circuit that amplifies the second received signal, and a first switch between the first transmitted signal passing through the first filter circuit and the first received signal. A third chip device including a transmission / reception switching circuit and a second transmission / reception switching circuit for switching between the second transmission signal and the second reception signal passing through the second filter circuit.
Including
On the substrate, the components of the first chip device and the first filter circuit, and the components of the second chip device and the second filter circuit are mounted at positions sandwiching the third chip device. Front-end module characterized by being present. The front-end module according to claim 3.
A decoupling capacitor of the power supply voltage applied to the first power amplifier circuit and the second power amplifier circuit,
The decoupling capacitor switching circuit that switches the capacitance value of the decoupling capacitor,
Equipped with
The decoupling capacitor switching circuit is provided in the third chip device.
The decoupling capacitor is a front-end module characterized in that it is mounted adjacent to the third chip device. The front-end module according to any one of claims 1 to 4.
A front-end module comprising a shield case that covers the substrate.

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