JP2021180553A - Dc-dc conversion device - Google Patents

Abstract

To realize a DC-DC conversion device with high performance at a low cost.SOLUTION: A first flying capacitor circuit 31 and a second flying capacitor circuit 32 are serially connected in parallel with a high-voltage side DC part. A reactor L1 is provided between a low-voltage side DC part, and the first flying capacitor circuit 31 and the second flying capacitor circuit 32. The first flying capacitor circuit 31 and the second flying capacitor circuit 32 include a plurality of switching elements S1 to S8 in or to which first diodes D1 to D8 are formed or connected in a reverse parallel manner, respectively. At least one second diodes De3 to De6 for bypassing current flowing to at least one first diodes D3 to D6 is connected in a reverse parallel manner to at least one of the plurality of switching elements S1 to S8.SELECTED DRAWING: Figure 15

Description

The present disclosure relates to a DC / DC converter that converts DC power into DC power of another voltage.

A DC / DC converter and an inverter are used in a power conditioner connected to a storage battery, a solar cell, a fuel cell, or the like. Highly efficient power conversion and compact design are desired for DC / DC converters and inverters. As a DC / DC converter to realize this, a flying capacitor circuit (four switching elements connected in series and a flying capacitor connected in parallel to the second switching element and the third switching element is configured after the reactor. A multi-level power conversion device has been proposed in which the voltage at the connection point between the reactor and the flying capacitor circuit is divided into three levels (see, for example, Patent Document 1).

The multi-level power conversion device can reduce the voltage applied to each switching element, thereby reducing the switching loss and realizing highly efficient power conversion. In the multi-level power conversion device using the flying capacitor circuit, the voltage applied to each switching element constituting the flying capacitor circuit can be reduced to 1/2 times the DC bus voltage by increasing the level to three. ..

As a result, it is possible to configure a switching element with a relatively low withstand voltage (for example, 300V) without using a switching element with a relatively high withstand voltage (for example, 600V) used in the full bridge portion of the inverter. Become. A switching element with a low withstand voltage is cheaper than a switching element with a high withstand voltage, and has less conduction loss and switching loss during power conversion, which contributes to further improvement in efficiency.

Japanese Unexamined Patent Publication No. 2013-192383

In MOSFETs commonly used as inexpensive switching devices, parasitic diodes are used as freewheeling diodes. Parasitic diodes have a large recovery loss and are a factor in increasing switching loss.

The present disclosure has been made in view of these circumstances, and an object thereof is to provide a low-cost and highly efficient DC / DC converter.

In order to solve the above problems, the DC / DC converter of one aspect of the present disclosure includes at least one reactor connected to the low voltage side DC section and a first flying capacitor connected in series with the high voltage side DC section. A circuit and a second flying capacitor circuit are provided. The positive terminal of the low-voltage side DC section and the midpoint of the first flying capacitor circuit are electrically connected, and the negative terminal of the low-voltage side DC section and the midpoint of the second flying capacitor circuit are electrically connected. The reactor is connected to a path connecting the positive terminal of the low-voltage side DC portion and the midpoint of the first flying capacitor circuit, and the negative terminal of the low-voltage side DC portion and the second flying capacitor circuit. Inserted in at least one of the paths connecting the midpoints, the first flying capacitor circuit and the second flying capacitor circuit include a plurality of switching elements in which the first diode is formed or connected in antiparallel, respectively. The DC / DC converter has at least one second diode connected in antiparallel to at least one of the plurality of switching elements to bypass the current flowing through the at least one first diode. Further prepare.

According to the present disclosure, a low-cost and highly efficient DC / DC converter can be realized.

It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on embodiment. It is a figure which summarized the switching pattern of the 1st switching element-8th switching element of the DC / DC conversion apparatus which concerns on embodiment. 3 (a)-(d) is a circuit diagram showing a current path of each switching pattern at the time of boosting operation. 4 (a)-(d) is a circuit diagram showing a current path of each switching pattern at the time of step-down operation. It is a timing chart which shows an example of the switching pattern of the 1st switching element-8th switching element when the step-up ratio is 2 times or more. It is a timing chart which shows an example of the switching pattern of the 1st switching element-8th switching element when the step-up ratio is less than 2 times. 7 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is twice or more (No. 1). 8 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is twice or more (No. 2). 9 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is twice or more (No. 1). 10 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is twice or more (No. 2). 11 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is less than 2 times (No. 1). 12 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is less than 2 times (No. 2). 13 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is less than 2 times (No. 1). 14 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is less than 2 times (No. 2). It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 1. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 2. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 3. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 4. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 5. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 6. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 7. FIG. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on Example 8. FIG. 23 (a)-(c) are diagrams showing a configuration example of a flying capacitor circuit. It is a figure which shows the flying capacitor circuit of N (N is a natural number) stage. It is a figure for demonstrating the structure of the DC / DC conversion apparatus which concerns on a modification.

FIG. 1 is a diagram for explaining the configuration of the DC / DC converter 3 according to the embodiment. The DC / DC converter 3 according to the embodiment is a bidirectional buck-boost DC / DC converter. The DC / DC converter 3 can boost the DC power supplied from the second DC power supply 2 and supply it to the first DC power supply 1. Further, the DC / DC converter 3 can step down the DC power supplied from the first DC power supply 1 and supply it to the second DC power supply 2. In the present specification, it is assumed that the second DC power supply 2 is a power supply having a lower voltage than the first DC power supply 1.

The second DC power supply 2 corresponds to, for example, a storage battery, an electric double layer capacitor, or the like. The first DC power supply 1 corresponds to, for example, a DC bus to which a bidirectional DC / AC inverter is connected. The AC side of the bidirectional DC / AC inverter is connected to the commercial power system and the AC load in the application of the power storage system. For electric vehicle applications, it is connected to a motor (with regenerative function). In the application of the power storage system, a DC / DC converter for a solar cell or a DC / DC converter for another storage battery may be further connected to the DC bus.

The DC / DC converter 3 includes a DC / DC converter 30 and a control unit 40. The DC / DC converter 30 includes an input capacitor C5, a reactor L1, a first flying capacitor circuit 31, a second flying capacitor circuit 32, a first dividing capacitor C3, a second dividing capacitor C4, and an output capacitor C6.

The input capacitor C5 is connected in parallel with the second DC power supply 2. The output capacitor C6 is connected in parallel with the first DC power supply 1. The first dividing capacitor C3 and the second dividing capacitor C4 are connected in series between the positive side bus and the negative side bus of the first DC power supply 1. The first dividing capacitor C3 and the second dividing capacitor C4 act as a snubber capacitor for dividing the voltage E of the first DC power supply 1 into 1/2 and suppressing the surge voltage generated in the DC / DC converter 30. Has the effect of. In the present specification, the configuration before the input capacitor C5 is referred to as a low-voltage DC unit, and the configuration after the first division capacitor C3 and the second division capacitor C4 is referred to as a high-voltage DC unit.

The first flying capacitor circuit 31 and the second flying capacitor circuit 32 are connected in series with the high voltage side DC unit in parallel. The reactor L1 is connected between the positive terminal of the low voltage side DC portion and the midpoint of the first flying capacitor circuit 31. The negative terminal of the low voltage side DC portion and the midpoint of the second flying capacitor circuit 32 are connected. The connection point between the first flying capacitor circuit 31 and the second flying capacitor circuit 32 is connected to the intermediate potential point M (the voltage dividing point of the first divided capacitor C3 and the second divided capacitor C4) of the DC portion on the high voltage side. NS.

The first division capacitor C3 and the second division capacitor C4 can be omitted. In that case, the connection point between the first flying capacitor circuit 31 and the second flying capacitor circuit 32 is not necessarily in the middle of the high-voltage side DC portion. It does not need to be connected to the potential point M.

The first flying capacitor circuit 31 includes a first switching element S1, a second switching element S2, a third switching element S3, a fourth switching element S4, and a first flying capacitor C1. The first switching element S1, the second switching element S2, the third switching element S3, and the fourth switching element S4 are connected in series and are connected between the positive bus of the high voltage direct current section and the intermediate potential point M. The first flying capacitor C1 is connected between the connection point between the first switching element S1 and the second switching element S2 and the connection point between the third switching element S3 and the fourth switching element S4, and is connected to the first switching element. S1-Charged and discharged by the fourth switching element S4.

At the midpoint of the first flying capacitor circuit 31, the voltage E [V] of the first DC power supply 1 applied to the upper terminal of the first switching element S1 and the voltage E [V] applied to the lower terminal of the fourth switching element S4. Potentials in the range between 1 / 2E [V] are generated. The first flying capacitor C1 is initially charged (precharged) so as to have a voltage of 1 / 4E [V], and charging / discharging is repeated centering on the voltage of 1 / 4E [V]. Therefore, at the midpoint of the first flying capacitor circuit 31, three levels of potentials of E [V], 3/4 E [V], and 1 / 2E [V] are generally generated.

The second flying capacitor circuit 32 includes a fifth switching element S5, a sixth switching element S6, a seventh switching element S7, an eighth switching element S8, and a second flying capacitor C2. The fifth switching element S5, the sixth switching element S6, the seventh switching element S7, and the eighth switching element S8 are connected in series and are connected between the intermediate potential point M of the high voltage direct current section and the negative bus. The second flying capacitor C2 is connected between the connection point between the fifth switching element S5 and the sixth switching element S6 and the connection point between the seventh switching element S7 and the eighth switching element S8, and is connected to the fifth switching element. S5-charged and discharged by the eighth switching element S8.

At the midpoint of the second flying capacitor circuit 32, 1 / 2E [V] applied to the upper terminal of the fifth switching element S5 and 0 [V] applied to the lower terminal of the eighth switching element S8. Potentials in the range between are generated. The second flying capacitor C2 is initially charged (precharged) so as to have a voltage of 1 / 4E [V], and charging / discharging is repeated centering on the voltage of 1 / 4E [V]. Therefore, at the midpoint of the second flying capacitor circuit 32, three levels of potentials of 1 / 2E [V], 1 / 4E [V], and 0 [V] are generally generated.

A first diode D1 to an eighth diode D8 are formed / connected in antiparallel to each of the first switching element S1 and the eighth switching element S8.

For the first switching element S1 to the eighth switching element S8, it is preferable to use a switching element having a withstand voltage lower than the voltage of the first DC power supply 1 and the second DC power supply 2. Hereinafter, in the present embodiment, an example in which an N-channel MOSFET with a withstand voltage of 150 V is used for the first switching element S1 to the eighth switching element S8 is assumed. In the N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a parasitic diode is formed from the source to the drain.

Although not shown in FIG. 1, a voltage sensor that detects the voltage of the low voltage DC portion, a current sensor that detects the current flowing through the reactor L1, a voltage sensor that detects the voltage of the first flying capacitor C1, and the second flying capacitor C2. A voltage sensor for detecting the voltage and a voltage sensor for detecting the voltage of the high-voltage DC unit are provided, and the measured values of each are output to the control unit 40.

The control unit 40 can control the first flying capacitor circuit 31 and the second flying capacitor circuit 32 to transmit DC power from the low-voltage side DC unit to the high-voltage side DC unit by boosting operation. Further, DC power can be transmitted from the high-voltage side DC section to the low-voltage side DC section by step-down operation. More specifically, the control unit 40 supplies a drive signal (PWM (Pulse Width Modulation) signal) to the gate terminal of the first switching element S1-eighth switching element S8, thereby supplying the first switching element S1-eighth. By controlling the switching element S8 on / off, power can be transmitted in both directions by a step-up operation or a step-down operation.

The configuration of the control unit 40 can be realized by the collaboration of hardware resources and software resources, or only by hardware resources. Analog devices, microcomputers, DSPs, ROMs, RAMs, FPGAs, ASICs, and other LSIs can be used as hardware resources. Programs such as firmware can be used as software resources.

FIG. 2 is a diagram summarizing the switching patterns of the first switching element S1 to the eighth switching element S8 of the DC / DC converter 3 according to the embodiment. In the switching pattern shown in FIG. 2, the set of the first switching element S1 and the eighth switching element S8 and the set of the fourth switching element S4 and the fifth switching element S5 have a complementary relationship. Further, the set of the second switching element S2 and the seventh switching element S7 and the set of the third switching element S3 and the sixth switching element S6 have a complementary relationship.

The control unit 40 executes a step-up operation or a step-down operation using four modes.
In the mode a, the control unit 40 turns on the second switching element S2, the fourth switching element S4, the fifth switching element S5, and the seventh switching element S7, and the first switching element S1, the third switching element S3, and the sixth. The switching element S6 and the eighth switching element S8 are controlled to be in the off state. In the mode a, the voltage between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32 (that is, the input / output voltage _VL on the low voltage side of the flying capacitor portion) is 1 / 2E.

In the mode b, the control unit 40 turns on the first switching element S1, the third switching element S3, the sixth switching element S6, and the eighth switching element S8, and the second switching element S2, the fourth switching element S4, and the fifth. The switching element S5 and the seventh switching element S7 are controlled to be in the off state. _{In mode b, the input / output voltage VL} on the low voltage side of the flying capacitor section is 1 / 2E.

In the mode c, the control unit 40 turns on the first switching element S1, the second switching element S2, the seventh switching element S7, and the eighth switching element S8, and the third switching element S3, the fourth switching element S4, and the fifth. The switching element S5 and the sixth switching element S6 are controlled to be in the off state. _{In mode c, the input / output voltage VL} on the low voltage side of the flying capacitor section is E.

In the mode d, the control unit 40 turns on the third switching element S3, the fourth switching element S4, the fifth switching element S5, and the sixth switching element S6, and the first switching element S1, the second switching element S2, and the seventh. The switching element S7 and the eighth switching element S8 are controlled to be in the off state. _{In mode d, the input / output voltage VL} on the low voltage side of the flying capacitor section becomes 0.

3 (a)-(d) is a circuit diagram showing a current path of each switching pattern at the time of boosting operation. 4 (a)-(d) is a circuit diagram showing a current path of each switching pattern at the time of step-down operation. The MOSFET is drawn with a simple switch symbol to simplify the drawing.

FIG. 3A shows the current path of mode a during boosting operation, FIG. 3B shows the current path of mode b during boosting operation, and FIG. 3C shows the current of mode c during boosting operation. The path is shown, and FIG. 3D shows the current path of the mode d at the time of boosting operation. Similarly, FIG. 4A shows the current path of the mode a during the step-down operation, FIG. 4B shows the current path of the mode b during the step-down operation, and FIG. 4C shows the mode during the step-down operation. The current path of c is shown, and FIG. 4 (d) shows the current path of the mode d at the time of step-down operation.

The direction of the current is opposite between the step-up operation and the step-down operation. In the mode a, the first flying capacitor C1 and the second flying capacitor C2 are charged during the boosting operation as shown in FIG. 3A, but the first flying capacitor C1 is charged during the stepping down operation as shown in FIG. 4A. The flying capacitor C1 and the second flying capacitor C2 are discharged. In the mode b, as shown in FIG. 3 (b), the first flying capacitor C1 and the second flying capacitor C2 are in the discharge operation during the step-up operation, but as shown in FIG. 4 (b), the first flying capacitor C1 is in the step-down operation. The flying capacitor C1 and the second flying capacitor C2 are in the charging operation.

When the control unit 40 transmits power from the low voltage DC unit to the high voltage DC unit by boosting operation, the control unit 40 sets a current command value in the positive direction, and the measured value of the current flowing through the reactor L1 maintains the current command value in the positive direction. The duty ratio (on time) of the first switching element S1 to the eighth switching element S8 is controlled so as to be performed. On the contrary, when the control unit 40 transmits power from the high voltage DC unit to the low voltage DC unit by step-down operation, the control unit 40 sets a current command value in the negative direction, and the measured value of the current flowing through the reactor L1 is the current command value in the negative direction. The duty ratio (on time) of the first switching element S1 to the eighth switching element S8 is controlled so as to maintain the value.

Further, when the ratio of the voltage of the low voltage side DC unit to the voltage of the high voltage side DC unit is smaller than the set value, the control unit 40 transmits power using modes a, mode b, and mode c. Further, when the ratio is larger than the set value, the control unit 40 transmits electric power using modes a, b, and d. Further, when the ratio matches the set value, the control unit 40 uses modes a and b to transmit electric power.

The voltage of the low-voltage side DC section and the voltage of the high-voltage side DC section are measured by voltage sensors, respectively. The above set value is set according to the ratio of the total voltage 1 / 2E of the voltage of the first flying capacitor C1 and the voltage of the second flying capacitor C2 to the voltage E of the first DC power supply 1. In this embodiment, the above setting value is set to 2.

The control unit 40 generates a duty ratio so that the current command value and the measured value of the current flowing through the reactor L1 match, and the voltages of the first flying capacitor C1 and the second flying capacitor C2 are 1 / 4E, respectively. .. Specifically, the control unit 40 increases the duty ratio as the measured value of the current flowing through the reactor L1 is smaller than the current command value, and decreases the duty ratio as the measured value is larger.

FIG. 5 is a timing chart showing an example of a switching pattern of the first switching element S1 to the eighth switching element S8 when the step-up ratio is twice or more. FIG. 6 is a timing chart showing an example of the switching pattern of the first switching element S1 to the eighth switching element S8 when the boost ratio is less than twice. The control examples shown in FIGS. 5 and 6 show a control example using the double carrier drive system. In the double carrier drive system, two carrier signals (triangular wave in FIGS. 5 and 6) that are 180 ° out of phase are used. The duty ratio duty is a threshold value to be compared with the two carrier signals. When the boost ratio is 2 times or more, the duty ratio duty takes a value in the range of 0.5 to 1.0, and when the boost ratio is less than 2 times, the duty ratio duty is in the range of 0.0 to 0.5. Take a value.

Based on the comparison result of the carrier signal of the thick wire and the duty ratio duty, the first gate signal supplied to the first switching element S1 and the eighth switching element S8 and the fourth gate supplied to the fourth switching element S4 and the fifth switching element S5. Generate a signal. Specifically, in the region where the carrier signal of the thick line is higher than the duty ratio duty, the first gate signal is turned on and the fourth gate signal is turned off. In the region where the carrier signal of the thick line is lower than the duty ratio duty, the first gate signal is turned off and the fourth gate signal is turned on. The first gate signal and the fourth gate signal are in a complementary relationship. A dead time period is set in which the first gate signal and the fourth gate signal are turned off at the same time when the first gate signal and the fourth gate signal are switched on / off.

Based on the comparison result of the carrier signal of the thin wire and the duty ratio duty, the second gate signal supplied to the second switching element S2 and the seventh switching element S7 and the third gate supplied to the third switching element S3 and the sixth switching element S6. Generate a signal. Specifically, in the region where the carrier signal of the thin wire is higher than the duty ratio duty, the second gate signal is turned on and the third gate signal is turned off. In the region where the carrier signal of the thin wire is lower than the duty ratio duty, the second gate signal is turned off and the third gate signal is turned on. The second gate signal and the third gate signal are in a complementary relationship. A dead time period is set in which the second gate signal and the third gate signal are turned off at the same time when the second gate signal and the third gate signal are switched on / off.

When the boost ratio is twice or more, the control unit 40 alternately switches between the mode a and the mode b, and inserts the mode d while switching between the two. That is, the control unit 40 switches modes in the order of mode a → mode d → mode b → mode d → mode a → mode d → mode b → mode d .... While the duty ratio duty does not change, the periods of mode a and mode b become equal, and the voltages of the first flying capacitor C1 and the second flying capacitor C2 are maintained at 1 / 4E, respectively. When the boost ratio is twice or more, as the duty ratio duty increases, the period of mode d with respect to the period of mode a and mode b becomes longer, and the amount of energy transmitted increases.

When the boost ratio is less than twice, the control unit 40 alternately switches between the mode a and the mode b, and inserts the mode c while switching between the two. That is, the control unit 40 switches modes in the order of mode a → mode c → mode b → mode c → mode a → mode c → mode b → mode c .... While the duty ratio duty does not change, the periods of mode a and mode b become equal, and the voltages of the first flying capacitor C1 and the second flying capacitor C2 are maintained at 1 / 4E, respectively. When the boost ratio is less than twice, as the duty ratio duty increases, the period of mode c with respect to the period of mode a and mode b becomes shorter, and the amount of energy transmitted increases.

If the boost ratio ideally maintains 2 times and the voltages of the first flying capacitor C1 and the second flying capacitor C2 ideally maintain 1 / 4E, the duty ratio duty maintains 0.5.

When the total voltage of the voltage of the first flying capacitor C1 and the voltage of the second flying capacitor C2 is less than 1 / 2E, the control unit 40 increases the time of the charging mode among the modes a and b. Bring the total voltage closer to 1 / 2E. On the contrary, when the total voltage of the voltage of the first flying capacitor C1 and the voltage of the second flying capacitor C2 exceeds 1 / 2E, the control unit 40 increases the time of the discharging mode among the modes a and b. The total voltage is brought closer to 1 / 2E.

The control unit 40 alternately switches between the mode c and the mode d without using the first flying capacitor C1 and the second flying capacitor C2, so that the DC / DC conversion unit 30 can operate the normal boost chopper. It is also possible to make it. In this case, the operation mode is not switched depending on the boost ratio.

Hereinafter, detailed switching patterns including the dead time will be described for each of the step-up ratio of 2 times or more, the step-down ratio of 2 times or more, the step-up ratio of less than 2 times, and the step-down ratio of less than 2 times.

7 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is twice or more (No. 1). 8 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is twice or more (No. 2). When the boost ratio is twice or more, the control unit 40 has mode d (FIG. 7 (a)) → dead time 1 (FIG. 7 (b)) → mode a (FIG. 7 (c)) → dead time 1 (FIG. 7 (c)). 7 (d)) → mode d (FIG. 8 (a)) → dead time 2 (FIG. 8 (b)) → mode b (FIG. 8 (c)) → dead time 2 (FIG. 8 (d)) in one cycle As, the switching pattern is switched.

In the dead time 1 when the boost ratio is twice or more, the control unit 40 turns off the second switching element S2, the third switching element S3, the sixth switching element S6, and the seventh switching element S7 at the same time. Since the second switching element S2 and the seventh switching element S7 are in the off state in the dead time 1, the second switching element S2 and the seventh switching element S7 are not synchronous rectification, but the parasitic diode of the second switching element S2 and the seventh. The current returns through the parasitic diode of the switching element S7.

When the dead time 1 (FIG. 7 (d)) is switched to the mode d (FIG. 8 (a)), the third switching element S3 and the sixth switching element S6 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the second switching element S2 and the parasitic diode of the seventh switching element S7 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the third switching element S3 and the sixth switching element S6, so that the current flowing at the time of turn-on of the third switching element S3 and the sixth switching element S6 increases, and the third switching element S3 and the sixth switching element S6 The switching loss of the switching element S6 increases.

In the dead time 2 when the boost ratio is twice or more, the control unit 40 turns off the first switching element S1, the fourth switching element S4, the fifth switching element S5, and the eighth switching element S8 at the same time. Since the first switching element S1 and the eighth switching element S8 are in the off state in the dead time 2, the first switching element S1 and the eighth switching element S8 are not synchronous rectification, but the parasitic diode of the first switching element S1 and the eighth. The current returns through the parasitic diode of the switching element S8.

When switching from the dead time 2 (FIG. 8 (d)) to the mode d (FIG. 7 (a)), the fourth switching element S4 and the fifth switching element S5 turn on. As a result, a reverse bias voltage is applied to the parasitic diode of the first switching element S1 and the parasitic diode of the eighth switching element S8 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the fourth switching element S4 and the fifth switching element S5, so that the current flowing at the time of turn-on of the fourth switching element S4 and the fifth switching element S5 increases, and the fourth switching element S4 and the fifth switching element S5 and the fifth switching element S5. The switching loss of the switching element S5 increases.

9 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is twice or more (No. 1). 10 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is twice or more (No. 2). When the step-down ratio is twice or more, the control unit 40 has mode d (FIG. 9 (a)) → dead time 1 (FIG. 9 (b)) → mode a (FIG. 9 (c)) → dead time 1 (FIG. 9 (c)). 9 (d)) → mode d (FIG. 10 (a)) → dead time 2 (FIG. 10 (b)) → mode b (FIG. 10 (c)) → dead time 2 (FIG. 10 (d)) in one cycle. As the switching pattern is switched.

In the dead time 1 when the step-down ratio is twice or more, the control unit 40 simultaneously turns off the second switching element S2, the third switching element S3, the sixth switching element S6, and the seventh switching element S7. Since the third switching element S3 and the sixth switching element S6 are in the off state in the dead time 1, the third switching element S3 and the sixth switching element S6 are not synchronous rectification, but the parasitic diode of the third switching element S3 and the sixth. The current returns through the parasitic diode of the switching element S6.

When the dead time 1 (FIG. 9 (b)) is switched to the mode a (FIG. 9 (c)), the second switching element S2 and the seventh switching element S7 turn on. As a result, a reverse bias voltage is applied to the parasitic diode of the third switching element S3 and the parasitic diode of the sixth switching element S6 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the second switching element S2 and the seventh switching element S7, so that the current flowing at the time of turn-on of the second switching element S2 and the seventh switching element S7 increases, and the second switching element S2 and the seventh switching element S7. The switching loss of the switching element S7 increases.

In the dead time 2 when the step-down ratio is twice or more, the control unit 40 turns off the first switching element S1, the fourth switching element S4, the fifth switching element S5, and the eighth switching element S8 at the same time. Since the 4th switching element S4 and the 5th switching element S5 are in the off state in the dead time 2, the 4th switching element S4 and the 5th switching element S5 are not synchronous rectification, but the parasitic diode of the 4th switching element S4 and the 5th. The current returns through the parasitic diode of the switching element S5.

When the dead time 2 (FIG. 10 (b)) is switched to the mode b (FIG. 10 (c)), the first switching element S1 and the eighth switching element S8 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the fourth switching element S4 and the parasitic diode of the fifth switching element S5 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the first switching element S1 and the eighth switching element S8, so that the current flowing at the time of turn-on of the first switching element S1 and the eighth switching element S8 increases, and the first switching element S1 and the eighth The switching loss of the switching element S8 increases.

11 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is less than 2 times (No. 1). 12 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the boost ratio is less than 2 times (No. 2). When the boost ratio is less than twice, the control unit 40 has mode c (FIG. 11 (a)) → dead time 1 (FIG. 11 (b)) → mode a (FIG. 11 (c)) → dead time 1 (FIG. 11 (c)). 11 (d)) → mode c (FIG. 12 (a)) → dead time 2 (FIG. 12 (b)) → mode b (FIG. 12 (c)) → dead time 2 (FIG. 12 (d)) in one cycle. As, the switching pattern is switched.

In the dead time 1 when the boost ratio is less than twice, the control unit 40 turns off the first switching element S1, the fourth switching element S4, the fifth switching element S5, and the eighth switching element S8 at the same time. Since the first switching element S1 and the eighth switching element S8 are in the off state in the dead time 1, the first switching element S1 and the eighth switching element S8 are not synchronous rectification, but the parasitic diode of the first switching element S1 and the eighth. The current returns through the parasitic diode of the switching element S8.

When the dead time 1 (FIG. 11 (b)) is switched to the mode a (FIG. 11 (c)), the fourth switching element S4 and the fifth switching element S5 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the first switching element S1 and the parasitic diode of the eighth switching element S8 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the fourth switching element S4 and the fifth switching element S5, so that the current flowing at the time of turn-on of the fourth switching element S4 and the fifth switching element S5 increases, and the fourth switching element S4 and the fifth switching element S5 and the fifth switching element S5. The switching loss of the switching element S5 increases.

In the dead time 2 when the boost ratio is less than twice, the control unit 40 turns off the second switching element S2, the third switching element S3, the sixth switching element S6, and the seventh switching element S7 at the same time. Since the second switching element S2 and the seventh switching element S7 are in the off state in the dead time 2, the second switching element S2 and the seventh switching element S7 are not synchronous rectification, but the parasitic diode of the second switching element S2 and the seventh. The current returns through the parasitic diode of the switching element S7.

When switching from the dead time 2 (FIG. 12 (b)) to the mode b (FIG. 12 (c)), the third switching element S3 and the sixth switching element S6 turn on. As a result, a reverse bias voltage is applied to the parasitic diode of the second switching element S2 and the parasitic diode of the seventh switching element S7 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the third switching element S3 and the sixth switching element S6, so that the current flowing at the time of turn-on of the third switching element S3 and the sixth switching element S6 increases, and the third switching element S3 and the sixth switching element S6 The switching loss of the switching element S6 increases.

13 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is less than 2 times (No. 1). 14 (a)-(d) is a circuit diagram showing a transition of a switching pattern when the step-down ratio is less than 2 times (No. 2). When the step-down ratio is less than twice, the control unit 40 has mode c (FIG. 13 (a)) → dead time 1 (FIG. 13 (b)) → mode a (FIG. 13 (c)) → dead time 1 (FIG. 13 (c)). 13 (d)) → mode c (FIG. 14 (a)) → dead time 2 (FIG. 14 (b)) → mode b (FIG. 14 (c)) → dead time 2 (FIG. 14 (d)) in one cycle. As the switching pattern is switched.

In the dead time 1 when the step-down ratio is less than twice, the control unit 40 simultaneously turns off the first switching element S1, the fourth switching element S4, the fifth switching element S5, and the eighth switching element S8. Since the 4th switching element S4 and the 5th switching element S5 are in the off state in the dead time 1, the 4th switching element S4 and the 5th switching element S5 are not synchronous rectification, but the parasitic diode of the 4th switching element S4 and the 5th. The current returns through the parasitic diode of the switching element S5.

When the dead time 1 (FIG. 13 (d)) is switched to the mode c (FIG. 14 (a)), the first switching element S1 and the eighth switching element S8 are turned on. As a result, a reverse bias voltage is applied to the parasitic diode of the fourth switching element S4 and the parasitic diode of the fifth switching element S5 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the first switching element S1 and the eighth switching element S8, so that the current flowing at the time of turn-on of the first switching element S1 and the eighth switching element S8 increases, and the first switching element S1 and the eighth The switching loss of the switching element S8 increases.

In the dead time 2 when the step-down ratio is less than twice, the control unit 40 turns off the second switching element S2, the third switching element S3, the sixth switching element S6, and the seventh switching element S7 at the same time. Since the third switching element S3 and the sixth switching element S6 are in the off state in the dead time 2, the third switching element S3 and the sixth switching element S6 are not synchronous rectification, but the parasitic diode of the third switching element S3 and the sixth. The current returns through the parasitic diode of the switching element S6.

When switching from the dead time 2 (FIG. 14 (d)) to the mode c (FIG. 13 (a)), the second switching element S2 and the seventh switching element S7 turn on. As a result, a reverse bias voltage is applied to the parasitic diode of the third switching element S3 and the parasitic diode of the sixth switching element S6 in which the current is flowing in the forward direction, and the recovery current flows in the reverse direction (see R). As a result, the recovery current flows into the second switching element S2 and the seventh switching element S7, so that the current flowing at the time of turn-on of the second switching element S2 and the seventh switching element S7 increases, and the second switching element S2 and the seventh switching element S7. The switching loss of the switching element S7 increases.

The recovery loss due to the parasitic diode of the MOSFET used as the switching element is not negligible, and reducing the recovery loss due to the parasitic diode greatly contributes to improving the efficiency of the DC / DC converter 3 as a whole. In the embodiment described below, an external diode is connected in antiparallel to at least one of the first switching element S1 to the eighth switching element S8. The external diode is a diode for bypassing the return current flowing through the parasitic diode in the dead time.

(Example 1)
FIG. 15 is a diagram for explaining the configuration of the DC / DC converter 3 according to the first embodiment. The DC / DC converter 3 according to the first embodiment has a configuration in which four external diodes are added to the configuration of the DC / DC converter 3 shown in FIG. Specifically, the third external diode De3, the fourth external diode De4, and the fifth are arranged in antiparallel to the third switching element S3, the fourth switching element S4, the fifth switching element S5, and the sixth switching element S6, respectively. The configuration is such that the external diode De5 and the sixth external diode De6 are connected.

The forward voltage Vf'of the third external diode De3, the fourth external diode De4, the fifth external diode De5, and the sixth external diode De6 is the third parasitic diode D3 and the fourth parasitic diode, respectively, which are in parallel with each other. It is necessary that the relationship is lower than the forward voltage Vf of D4, the fifth parasitic diode D5 and the sixth parasitic diode D6. If this condition is not met, the return current will not be bypassed by the external diode.

The recovery losses Prr'of the third external diode De3, the fourth external diode De4, the fifth external diode De5, and the sixth external diode De6 are parallel to each other in the third parasitic diode D3 and the fourth parasitic diode D4, respectively. , It is necessary that the relationship is lower than the recovery loss Pr of the fifth parasitic diode D5 and the sixth parasitic diode D6. If this condition is not satisfied, the recovery loss reduction effect cannot be obtained even if an external diode is connected.

A Schottky barrier diode (SBD) can be used as a diode that satisfies the above two conditions. The Schottky barrier diode utilizes a Schottky barrier generated by a junction between a metal and a semiconductor (for example, silicon) instead of a PN junction. Compared with the PN junction parasitic diode, the forward voltage Vf is low and the reverse recovery time Trr is short, so the recovery loss is also low.

Further, a fast recovery diode (FRD) may be used as the diode that satisfies the above two conditions. The fast recovery diode is a PN junction diode, but the recovery loss is low because the reverse recovery time Trr is short. In recent years, a type having a low forward voltage Vf has also been put into practical use.

Further, a SiC (silicon carbide) diode may be used as the diode that satisfies the above two conditions. For example, SiC-SBD has a shorter reverse recovery time Trr than Si-SBD, and recovery loss can be further reduced. SiC-FRD is superior to Si-FRD in the temperature characteristics of the reverse recovery time Trr, and can suppress an increase in the reverse recovery time Trr even during high-temperature operation.

(Example 2)
FIG. 16 is a diagram for explaining the configuration of the DC / DC converter 3 according to the second embodiment. The DC / DC converter 3 according to the second embodiment has a configuration in which four external diodes are added to the configuration of the DC / DC converter 3 shown in FIG. Specifically, the first external diode De1, the second external diode De2, and the seventh are arranged in antiparallel to the first switching element S1, the second switching element S2, the seventh switching element S7, and the eighth switching element S8, respectively. The configuration is such that the external diode De7 and the eighth external diode De8 are connected.

The forward voltage Vf'of the first external diode De1, the second external diode De3, the seventh external diode De7, and the eighth external diode De8 are the first parasitic diode D1 and the second parasitic diode, respectively, which are in parallel with each other. It is necessary that the relationship is lower than the forward voltage Vf of D2, the seventh parasitic diode D7, and the eighth parasitic diode D8. If this condition is not met, the return current will not be bypassed by the external diode.

The recovery losses Prr'of the first external diode De1, the second external diode De2, the seventh external diode De7, and the eighth external diode De8 are parallel to each other in the first parasitic diode D1 and the second parasitic diode D2, respectively. , It is necessary that the relationship is lower than the recovery loss Pr of the 7th parasitic diode D7 and the 8th parasitic diode D8. If this condition is not satisfied, the recovery loss reduction effect cannot be obtained even if an external diode is connected.

As a diode that satisfies the above two conditions, a Schottky barrier diode (SBD) or the like can be used.

(Example 3)
FIG. 17 is a diagram for explaining the configuration of the DC / DC converter 3 according to the third embodiment. The DC / DC converter 3 according to the third embodiment has a configuration in which eight external diodes are added to the configuration of the DC / DC converter 3 shown in FIG. Specifically, the configuration according to the first embodiment shown in FIG. 15 and the configuration according to the second embodiment shown in FIG. 16 are combined.

Control examples when the step-up ratio shown in FIGS. 7 (a)-(d) and 8 (a)-(d) is twice or more, and FIGS. 11 (a)-(d) and 12 (a). In the control example in the case where the boost ratio shown in − (d) is less than twice, the mode in which the return current flows through the first parasitic diode D1 and the eighth parasitic diode D8, or the second parasitic diode D2 and the seventh parasitic diode D7. There has occurred.

Control examples when the step-down ratio shown in FIGS. 9 (a)-(d) and 10 (a)-(d) is twice or more, and FIGS. 13 (a)-(d) and 14 (a). In the control example when the step-down ratio shown in − (d) is less than 2 times, a mode in which a return current flows through the third parasitic diode D3 and the sixth parasitic diode D6, or the fourth parasitic diode D4 and the fifth parasitic diode D5. There has occurred.

In the first embodiment, the third parasitic diode D3 and the sixth parasitic diode D6 are added by adding the third external diode De3, the fourth external diode De4, the fifth external diode De5, and the sixth external diode De6. Alternatively, the recovery loss can be reduced in a mode in which a return current flows through the fourth parasitic diode D4 and the fifth parasitic diode D5. As described above, according to the first embodiment, the recovery loss during the step-down operation can be reduced, and the conversion efficiency during the step-down operation of the DC / DC converter 3 can be improved.

In the second embodiment, the first parasitic diode D1 and the eighth parasitic diode D8 are added by adding the first external diode De1, the second external diode De2, the seventh external diode De7, and the eighth external diode De8. Alternatively, the recovery loss can be reduced in a mode in which a return current flows through the second parasitic diode D2 and the seventh parasitic diode D7. As described above, according to the second embodiment, the recovery loss during the boosting operation can be reduced, and the conversion efficiency during the boosting operation of the DC / DC converter 3 can be improved.

In the third embodiment, by adding the first external diode De1 to the eighth external diode De8, the recovery loss during both the step-up operation and the step-down operation can be reduced, and the conversion efficiency of the DC / DC converter 3 can be improved. Can be improved.

In the case of an application that requires only boosting operation (for example, a boosting chopper of a solar cell), the number of external diodes to be added can be reduced by adopting the configuration according to the second embodiment, and the configuration according to the third embodiment can be reduced. The cost can be further reduced. Further, in the case of an application that requires only step-down operation (for example, a charger for a storage battery), the number of external diodes to be added can be reduced by adopting the configuration according to the first embodiment, and the third embodiment can be reduced. The cost can be reduced compared to the configuration.

(Example 4)
FIG. 18 is a diagram for explaining the configuration of the DC / DC converter 3 according to the fourth embodiment. The DC / DC converter 3 according to the fourth embodiment has a configuration in which two external diodes are added to the configuration of the DC / DC converter 3 shown in FIG. Specifically, the ninth external diode De9 is connected in antiparallel to both ends of the first switching element S1 and the second switching element S2, and the ninth external diode De9 is connected in antiparallel to both ends of the seventh switching element S7 and the eighth switching element S8. 10 An external diode De10 is connected to the configuration.

The forward voltage Vf'of the ninth external diode De9 is the sum of the forward voltage Vf of the first parasitic diode D1 and the voltage drop during conduction of the second switching element S2, or the forward direction of the second parasitic diode D2. It is necessary that the relationship is lower than the sum of the voltage Vf and the voltage drop at the time of conduction of the first switching element S1. If this condition is not satisfied, the return current is not bypassed by the 9th external diode De9. The recovery loss Prr'of the ninth external diode De9 needs to be lower than the recovery loss Prr of the first parasitic diode D1 or the second parasitic diode D2. If this condition is not satisfied, the effect of reducing the recovery loss cannot be obtained even if the ninth external diode De9 is connected.

When all of the first switching element S1 to the eighth switching element S8 are turned off during the dead time, the forward voltage Vf'of the ninth external diode De9 is the first parasitic diode D1 or the second parasitic diode D2. The relationship may be lower than twice the forward voltage Vf. In this case, the recovery loss Prr'of the 9th external diode De9 may be lower than the sum of the recovery loss Prr of the first parasitic diode D1 and the recovery loss Prr of the second parasitic diode D2.

Similarly, the forward voltage Vf'of the 10th external diode De10 is the sum of the forward voltage Vf of the 8th parasitic diode D8 and the voltage drop during conduction of the 7th switching element S7, or the 7th parasitic diode D7. It is necessary that the relationship is lower than the sum of the forward voltage Vf of No. 1 and the voltage drop at the time of conduction of the eighth switching element S8. If this condition is not satisfied, the return current is not bypassed by the 10th external diode De10. The recovery loss Prr'of the 10th external diode De10 needs to be lower than the recovery loss Prr of the 8th parasitic diode D8 or the 7th parasitic diode D7. If this condition is not satisfied, the effect of reducing the recovery loss cannot be obtained even if the tenth external diode De10 is connected.

When all of the first switching element S1 to the eighth switching element S8 are turned off during the dead time, the forward voltage Vf'of the tenth external diode De10 is the seventh parasitic diode D7 or the eighth parasitic diode D8. The relationship may be lower than twice the forward voltage Vf. In this case, the recovery loss Prr'of the 10th external diode De10 may be lower than the sum of the recovery loss Prr of the 7th parasitic diode D7 and the recovery loss Prr of the 8th parasitic diode D8.

The voltage drop during conduction of the first switching element S1, the second switching element S2, the seventh switching element S7, or the eighth switching element S8 described above is the first switching element S1, the second switching element S2, and the seventh switching element. It is determined by the on-resistance of S7 or the eighth switching element S8 and the current flowing through the first switching element S1, the second switching element S2, the seventh switching element S7, or the eighth switching element S8.

In the fourth embodiment, in the dead time 1 (see FIG. 11 (b)) and the dead time 2 (see FIG. 12 (b)) when the boost ratio is less than twice, the ninth external diode De9 and the tenth outside. The attached diode De10 has the effect of reducing the recovery loss. In the dead time when the boost ratio is 2 times or more, the reflux current cannot be bypassed by the 9th external diode De9 and the 10th external diode De10.

As described above, in the fourth embodiment, by adding the ninth external diode De9 and the tenth external diode De10, the recovery loss during the boosting operation when the boosting ratio is less than twice can be reduced, and the DC / DC conversion can be performed. The conversion efficiency of the device 3 can be improved.

(Example 5)
FIG. 19 is a diagram for explaining the configuration of the DC / DC converter 3 according to the fifth embodiment. The DC / DC converter 3 according to the fifth embodiment has a configuration in which two external diodes are added to the configuration of the DC / DC converter 3 shown in FIG. Specifically, the eleventh external diode De11 is connected in antiparallel to both ends of the third switching element S3 and the fourth switching element S4, and the eleventh external diode De11 is connected in antiparallel to both ends of the fifth switching element S5 and the sixth switching element S6. The configuration is such that the 12 external diode De12 is connected.

The forward voltage Vf'of the eleventh external diode De11 is the sum of the forward voltage Vf of the third parasitic diode D3 and the voltage drop during conduction of the fourth switching element S4, or the forward direction of the fourth parasitic diode D4. It is necessary that the relationship is lower than the total voltage of the voltage Vf and the voltage drop at the time of conduction of the third switching element S3. If this condition is not satisfied, the return current is not bypassed by the 11th external diode De11. The recovery loss Prr'of the 11th external diode De11 needs to be lower than the recovery loss Prr of the third parasitic diode D3 or the fourth parasitic diode D4. If this condition is not satisfied, the recovery loss reduction effect cannot be obtained even if the eleventh external diode De11 is connected.

When all of the first switching element S1 to the eighth switching element S8 are turned off during the dead time, the forward voltage Vf'of the eleventh external diode De11 is the third parasitic diode D3 or the fourth parasitic diode D4. The relationship may be lower than twice the forward voltage Vf. In this case, the recovery loss Prr'of the 11th external diode De11 may be lower than the sum of the recovery loss Prr of the third parasitic diode D3 and the recovery loss Prr of the fourth parasitic diode D4.

Similarly, the forward voltage Vf'of the 12th external diode De12 is the sum of the forward voltage Vf of the 6th parasitic diode D6 and the voltage drop during conduction of the 5th switching element S5, or the 5th parasitic diode D5. It is necessary that the relationship is lower than the sum of the forward voltage Vf of No. 1 and the voltage drop at the time of conduction of the sixth switching element S6. If this condition is not satisfied, the return current is not bypassed by the 12th external diode De12. The recovery loss Prr'of the 12th external diode De12 needs to be lower than the recovery loss Prr of the 6th parasitic diode D6 or the 5th parasitic diode D5. If this condition is not satisfied, the effect of reducing the recovery loss cannot be obtained even if the 12th external diode De12 is connected.

When all of the first switching element S1 to the eighth switching element S8 are turned off during the dead time, the forward voltage Vf'of the twelfth external diode De12 is the fifth parasitic diode D5 or the sixth parasitic diode D6. The relationship may be lower than twice the forward voltage Vf. In this case, the recovery loss Prr'of the 12th external diode De12 may be lower than the sum of the recovery loss Prr of the 5th parasitic diode D5 and the recovery loss Prr of the 6th parasitic diode D6.

In the fifth embodiment, in the dead time 1 (see FIG. 9 (b)) and the dead time 2 (see FIG. 10 (b)) when the step-down ratio is twice or more, the eleventh external diode De11 and the twelfth outside diode are used. The attached diode De12 has the effect of reducing the recovery loss. In the dead time when the step-down ratio is less than twice, the reflux current cannot be bypassed by the 11th external diode De11 and the 12th external diode De12.

As described above, in the fifth embodiment, by adding the eleventh external diode De11 and the twelfth external diode De12, the recovery loss during the step-down operation when the step-down ratio is twice or more can be reduced, and the DC / DC conversion can be performed. The conversion efficiency of the device 3 can be improved.

(Example 6)
FIG. 20 is a diagram for explaining the configuration of the DC / DC converter 3 according to the sixth embodiment. The DC / DC converter 3 according to the sixth embodiment has a configuration in which four external diodes are added to the configuration of the DC / DC converter 3 shown in FIG. Specifically, the configuration according to the fourth embodiment shown in FIG. 18 and the configuration according to the fifth embodiment shown in FIG. 19 are combined.

In Example 6, by adding the 9th external diode De9-12th external diode De12, the step-up operation when the step-up ratio is less than 2 times and the step-down operation when the step-down ratio is 2 times or more are performed. The recovery loss can be reduced, and the conversion efficiency of the DC / DC converter 3 can be improved.

(Example 7)
FIG. 21 is a diagram for explaining the configuration of the DC / DC converter 3 according to the seventh embodiment. The DC / DC converter 3 according to the seventh embodiment has a configuration in which one external diode is added to the configuration of the DC / DC converter 3 shown in FIG. Specifically, the thirteenth external diode De13 is connected in antiparallel to both ends of the fourth switching element S4 and the fifth switching element S5.

The forward voltage Vf'of the thirteenth external diode De13 needs to be lower than twice the forward voltage Vf of the fourth parasitic diode D4 or the fifth parasitic diode D5. If this condition is not satisfied, the return current is not bypassed by the 13th external diode De13. The recovery loss Prr'of the 13th external diode De13 needs to be lower than the sum of the recovery loss Prr of the 4th parasitic diode D4 and the recovery loss Prr of the 5th parasitic diode D5. If this condition is not satisfied, the effect of reducing the recovery loss cannot be obtained even if the 13th external diode De13 is connected.

In Example 7, the dead time 2 (see FIG. 10 (b)) when the step-down ratio is 2 times or more and the dead time 1 (see FIG. 13 (d)) when the step-down ratio is less than 2 times are the same. 13 The external diode De13 exerts an effect of reducing the recovery loss. In the dead time 1 when the step-down ratio is 2 times or more and the dead time 2 when the step-down ratio is less than 2 times, the return current cannot be bypassed by the 13th external diode De13.

As described above, in the seventh embodiment, by adding the thirteenth external diode De13, the recovery loss in a part of the dead time during the step-down operation can be reduced, and the conversion efficiency of the DC / DC converter 3 can be improved. can.

(Example 8)
FIG. 22 is a diagram for explaining the configuration of the DC / DC converter 3 according to the eighth embodiment. The DC / DC converter 3 according to the eighth embodiment has a configuration in which one external diode is added to the configuration of the DC / DC converter 3 shown in FIG. Specifically, the 14th external diode De14 is connected in antiparallel to both ends of the third switching element S3, the fourth switching element S4, the fifth switching element S5, and the sixth switching element S6.

The forward voltage Vf'of the 14th external diode De14 is the forward voltage Vf of the third parasitic diode D3, the voltage drop when the fourth switching element S4 is conducting, the voltage drop when the fifth switching element S5 is conducting, and the first. 6 The total voltage of the forward voltage Vf of the parasitic diode D6, or the voltage drop when the third switching element S3 is conducting, the forward voltage Vf of the fourth parasitic diode D4, and the forward voltage Vf and the third of the fifth parasitic diode D5. 6 It is necessary that the relationship is lower than the total voltage of the voltage drops during conduction of the switching element S6. If this condition is not satisfied, the return current is not bypassed by the 14th external diode De14. The recovery loss Prr of the 14th external diode De14 is the sum of the recovery loss Prr of the third parasitic diode D3 and the recovery loss Prr of the sixth parasitic diode D6, or the recovery loss Prr of the fourth parasitic diode D4 and the fifth parasitic diode. The relationship must be lower than the total recovery loss Prr of D5. If this condition is not satisfied, the effect of reducing the recovery loss cannot be obtained even if the 14th external diode De14 is connected.

When all of the first switching element S1 to the eighth switching element S8 are turned off during the dead time, the forward voltage Vf'of the 14th external diode De14 is the forward voltage Vf of the third parasitic diode D3. The relationship may be lower than the sum of the forward voltage Vf of the 4 parasitic diode D4, the forward voltage Vf of the 5th parasitic diode D5, and the forward voltage Vf of the 6th parasitic diode D6. In this case, the recovery loss Prr'of the 14th external diode De14 is the recovery loss Prr of the third parasitic diode D3, the recovery loss Prr of the fourth parasitic diode D4, the recovery loss Prr of the fifth parasitic diode D5, and the sixth parasitic diode. The relationship may be lower than the total voltage of the recovery loss Prr of D6.

In Example 8, the 14th external diode De14 causes a recovery loss in the dead time 1 (see FIG. 9B) and the dead time 2 (see FIG. 10B) when the step-down ratio is twice or more. Demonstrate the effect of reduction. In the dead time when the step-down ratio is less than twice, the 14th external diode De14 cannot bypass the reflux current.

As described above, in the eighth embodiment, by adding the 14th external diode De14, the recovery loss during the step-down operation when the step-down ratio is twice or more can be reduced, and the conversion efficiency of the DC / DC converter 3 is improved. Can be made to.

The circuit configurations according to the first to eighth embodiments described above can be combined in various ways other than those described above. For example, the circuit configuration shown in the first embodiment and the circuit configuration shown in the fourth embodiment can be combined. Further, it is possible to combine the circuit configuration shown in the second embodiment and the circuit configuration shown in the fifth embodiment. Further, it is possible to combine the circuit configuration shown in the second embodiment and the circuit configuration shown in the seventh embodiment. Further, it is possible to combine the circuit configuration shown in the second embodiment and the circuit configuration shown in the eighth embodiment.

The present disclosure has been described above based on the embodiments. It is understood by those skilled in the art that the embodiments are exemplary and that various modifications are possible for each of these components and combinations of processing processes, and that such modifications are also within the scope of the present disclosure. ..

In the above embodiment, as a configuration example of the flying capacitor circuit, four switching elements connected in series and a one-stage flying capacitor circuit using one flying capacitor are given as an example. In this respect, a flying capacitor circuit with an increased number of stages can also be used.

23 (a)-(c) are diagrams showing a configuration example of a flying capacitor circuit. FIG. 23A shows a one-stage flying capacitor circuit. The flying capacitor circuit shown in FIG. 23 (a) has the same circuit configuration as described in the above embodiment.

FIG. 23B shows a two-stage flying capacitor circuit. The two-stage flying capacitor circuit includes six switching elements S12, S1, S2, S3, S4, and S42 connected in series, and two flying capacitors C11 and C12. The innermost flying capacitor C11 is connected in parallel to the two switching elements S2 and S3, and is controlled to maintain a voltage of 1 / 6E. The second flying capacitor C12 from the inside is connected in parallel to the four switching elements S1, S2, S3, and S4, and is controlled to maintain a voltage of 1 / 6E.

FIG. 23 (c) shows a three-stage flying capacitor circuit. The three-stage flying capacitor circuit includes six switching elements S13, S12, S1, S2, S3, S4, S42, and S43 connected in series, and three flying capacitors C11, C12, and C13. The innermost flying capacitor C11 is connected in parallel to the two switching elements S2 and S3, and is controlled to maintain a voltage of 1 / 8E. The second flying capacitor C12 from the inside is connected in parallel to the four switching elements S1, S2, S3, and S4, and is controlled to maintain a voltage of 2 / 8E. The third flying capacitor C13 from the inside is connected in parallel to the six switching elements S12, S1, S2, S3, S4, and S42, and is controlled to maintain a voltage of 3 / 8E.

FIG. 24 shows an N (N is a natural number) stage flying capacitor circuit. In the N-stage flying capacitor circuit, N (2N + 2) switching elements S1n, ..., S13, S12, S1, S2, S3, S4, S42, S43, ..., S4n connected in series. The flying capacitors C11, C12, C13, ..., C1n of the above are provided. The innermost flying capacitor C11 is connected in parallel to the two switching elements S2 and S3, and is controlled to maintain a voltage of 1 / (2N + 2) E. The second flying capacitor C12 from the inside is connected in parallel to the four switching elements S1, S2, S3, and S4, and is controlled to maintain a voltage of 2 / (2N + 2) E. The third flying capacitor C13 from the inside is connected in parallel to the six switching elements S12, S1, S2, S3, S4, and S42, and is controlled to maintain a voltage of 3 / (2N + 2) E. The outermost flying capacitor C1n has 2N S1 (n-1), ..., S13, S12, S1, S2, S3, S4, S42, S43, ..., S4 (n-1). They are connected in parallel and controlled to maintain a voltage of N / (2N + 2) E.

In the first flying capacitor circuit 31 and the second flying capacitor circuit 32 shown in FIG. 1, the one-stage flying capacitor circuit shown in FIG. 23A is used. When a one-stage flying capacitor circuit is used, a voltage of three levels (E, 1 / 2E, 0) is generated between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32. Is possible. Using the two-stage flying capacitor circuit shown in FIG. 23 (b), there are five levels (E, 2 / 3E,) between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32. It is possible to generate a voltage of 1 / 2E, 1 / 3E, 0). Using the three-stage flying capacitor circuit shown in FIG. 23 (c), there are seven levels (E, 3/4E,) between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32. It is possible to generate a voltage of 5 / 8E, 1 / 2E, 3 / 8E, 1 / 4E, 0). By using the N-stage flying capacitor circuit shown in FIG. 24, it is possible to generate a (2N + 1) level voltage between the midpoint of the first flying capacitor circuit 31 and the midpoint of the second flying capacitor circuit 32. Will be.

As the number of stages of the flying capacitor circuit is increased, switching elements that are inexpensive and have a low breakdown voltage can be used, but the number of switching elements used increases. Therefore, the designer may determine the optimum number of stages of the flying capacitor circuit in consideration of the total cost and the total conversion efficiency. Further, in an application in which the voltage of the DC portion on the high voltage side exceeds 1000 V or in an application in which the voltage exceeds 10,000 V, it is effective to increase the number of stages of the flying capacitor circuit in order to reduce the withstand voltage of each switching element.

In the present disclosure, regardless of the number of stages of the flying capacitor circuit, by connecting an external diode in antiparallel to at least one of a plurality of switching elements, a return current is transmitted to the parasitic diode of the switching element. It is possible to reduce the recovery loss caused by the flow.

FIG. 25 is a diagram for explaining the configuration of the DC / DC converter 3 according to the modified example. In the DC / DC converter 3 shown in FIG. 1, the reactor L1 is connected between the positive terminal of the low-voltage side DC portion and the midpoint of the first flying capacitor circuit 31. In this regard, in the modified example shown in FIG. 25, the first reactor L1 is connected between the positive terminal of the low voltage side DC portion and the midpoint of the first flying capacitor circuit 31, and the negative terminal of the low voltage side DC portion and the second terminal. The second reactor L2 is connected between the midpoints of the flying capacitor circuit 32. The first reactor L1 and the second reactor L2 may be configured by a magnetically coupled reactor having a common core. In this case, the magnetic fluxes of the first reactor L1 and the second reactor L2 can be mutually strengthened when energized.

The reactor L1 may be connected between the negative terminal of the low voltage side DC portion and the midpoint of the second flying capacitor circuit 32. As described above, the reactor L1 has a path connecting the positive terminal of the low-voltage side DC portion and the midpoint of the first flying capacitor circuit 31, and the negative terminal of the low-voltage side DC portion and the inside of the second flying capacitor circuit 32. It suffices if it is inserted in at least one of the paths connecting the points.

Each of the first switching element S1 to the eighth switching element S8 described above may be composed of a plurality of switching elements connected in parallel. In that case, the current flowing through one switching element can be reduced, and one switching element can be miniaturized.

In the above-described embodiment, an example in which a MOSFET is used for the first switching element S1 to the eighth switching element S8 has been described. In this regard, when a switching element such as an IGBT (Insulated Gate Bipolar Transistor) in which a parasitic diode is not formed is used, it is sufficient to connect an external diode having a small recovery loss in antiparallel to each switching element. It is not necessary to adopt the circuit configuration shown in. In the circuit configuration shown in Example 4-8, the recovery loss can be reduced by additionally connecting a bypass diode.

The present disclosure can also be applied to the case of using a switching element composed of a wide bandgap semiconductor using silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), or the like. Is.

The embodiment may be specified by the following items.

[Item 1]
At least one reactor (L1) connected to the low voltage side DC section,
A first flying capacitor circuit (31) and a second flying capacitor circuit (32) connected in parallel with the high-voltage side DC unit are provided.
The positive terminal of the low voltage side DC portion and the midpoint of the first flying capacitor circuit (31) are electrically connected, and the negative terminal of the low voltage side DC portion and the second flying capacitor circuit (32) are connected. The midpoints are electrically connected,
The reactor (L1) has a path connecting the positive terminal of the low voltage side DC portion and the midpoint of the first flying capacitor circuit (31), a negative terminal of the low voltage side DC portion, and the second flying. Inserted into at least one of the paths connecting the midpoints of the capacitor circuit (32),
The first flying capacitor circuit (31) and the second flying capacitor circuit (32) each include a plurality of switching elements (S1-S8) in which a first diode (D) is formed or connected in antiparallel.
This DC / DC converter (3) is
At least one second diode (for bypassing the current flowing through the at least one first diode (D), which is connected in antiparallel to at least one of the plurality of switching elements (S1-S8)). Further equipped with De),
DC / DC converter (3).
According to this, the recovery loss due to the first diode (D) can be reduced.
[Item 2]
The first flying capacitor circuit (31) is
The first switching element (S1), the second switching element (S2), the third switching element (S3), and the fourth switching element (S4) connected in series,
The first connected between the connection point between the first switching element (S1) and the second switching element (S2) and the connection point between the third switching element (S3) and the fourth switching element (S4). Including the flying capacitor (C1),
The second flying capacitor circuit (32) is
The fifth switching element (S5), the sixth switching element (S6), the seventh switching element (S7), and the eighth switching element (S8) connected in series,
A second connected between the connection point between the fifth switching element (S5) and the sixth switching element (S6) and the connection point between the seventh switching element (S7) and the eighth switching element (S8). Including a flying capacitor (C2),
The first diode (D1-D8) is formed or connected in antiparallel to each of the first switching element (S1) and the eighth switching element (S8).
The DC / DC converter (3) according to item 1.
According to this, a three-level multi-level DC / DC converter (3) can be realized. By connecting eight switching elements (S1-S8) in series in parallel with the high-voltage DC unit, it is possible to use a switching element having a lower withstand voltage than before.
[Item 3]
The four second diodes (De3-) are inversely parallel to the third switching element (S3), the fourth switching element (S4), the fifth switching element (S5), and the sixth switching element (S6), respectively. De6) is connected,
The DC / DC converter (3) according to item 2.
According to this, the recovery loss due to the first diode (D3-D6) at the time of step-down operation can be reduced.
[Item 4]
The four second diodes (De1-) are inversely parallel to the first switching element (S1), the second switching element (S2), the seventh switching element (S7), and the eighth switching element (S8), respectively. De2, De7-De8) are connected,
The DC / DC converter (3) according to item 2 or 3.
According to this, the recovery loss due to the first diode (D1-2, D7-D8) at the time of boosting operation can be reduced.
[Item 5]
The forward voltage of the second diode (De1-De8) is lower than the forward voltage of the first diode (D1-D8).
The recovery loss of the second diode (De1-De8) is lower than the recovery loss of the first diode (D1-D8).
The DC / DC converter (3) according to item 3 or 4.
According to this, the return current can be bypassed to the second diode (De1-De8), and the loss can be reduced as compared with the case where the return current flows through the first diode (D1-D8).
[Item 6]
One second diode (De9) is connected in antiparallel to both ends of the first switching element (S1) and the second switching element (S2) connected in series.
One second diode (De10) is connected in antiparallel to both ends of the seventh switching element (S7) and the eighth switching element (S8) connected in series.
The DC / DC converter (3) according to item 2.
According to this, it is possible to reduce the recovery loss due to the first diode (D1-D2, D7-D8) at the time of boosting operation in which the boosting ratio is less than twice.
[Item 7]
One second diode (De11) is connected in antiparallel to both ends of the third switching element (S3) and the fourth switching element (S4) connected in series.
One second diode (De12) is connected in antiparallel to both ends of the fifth switching element (S5) and the sixth switching element (S6) connected in series.
The DC / DC converter (3) according to item 2 or 6.
According to this, it is possible to reduce the recovery loss due to the first diode (D3-D6) at the time of the step-down operation in which the step-down ratio is twice or more.
[Item 8]
One second diode (De13) is connected in antiparallel to both ends of the fourth switching element (S4) and the fifth switching element (S5) connected in series.
The DC / DC converter (3) according to any one of items 2, 4 and 6.
According to this, the recovery loss due to the first diode (D4-D5) at the time of step-down operation can be reduced.
[Item 9]
One of the first elements connected in series to both ends of the third switching element (S3), the fourth switching element (S4), the fifth switching element (S5), and the sixth switching element (S6). 2 diodes (De14) are connected,
The DC / DC converter (3) according to any one of items 2, 4 and 6.
According to this, it is possible to reduce the recovery loss due to the first diode (D3-D6) at the time of the step-down operation in which the step-down ratio is twice or more.
[Item 10]
By controlling the first flying capacitor circuit (31) and the second flying capacitor circuit (32), power is transmitted from the low voltage side DC section to the high voltage side DC section by a boosting operation, and from the high voltage side DC section to the high voltage side DC section. Further equipped with a control unit (40) capable of executing at least one of power transmission by step-down operation to the low-voltage side DC unit.
The control unit (40)
The second switching element (S2), the fourth switching element (S4), the fifth switching element (S5) and the seventh switching element (S7) are turned on, and the first switching element (S1), the said. A first mode for controlling the third switching element (S3), the sixth switching element (S6), and the eighth switching element (S8) to an off state.
The first switching element (S1), the third switching element (S3), the sixth switching element (S6) and the eighth switching element (S8) are turned on, and the second switching element (S2), the said. A second mode for controlling the fourth switching element (S4), the fifth switching element (S5), and the seventh switching element (S7) to an off state.
The first switching element (S1), the second switching element (S2), the seventh switching element (S7) and the eighth switching element (S8) are turned on, and the third switching element (S3), the said. A third mode for controlling the fourth switching element (S4), the fifth switching element (S5), and the sixth switching element (S6) in an off state.
The third switching element (S3), the fourth switching element (S4), the fifth switching element (S5) and the sixth switching element (S6) are turned on, and the first switching element (S1), the said. A fourth mode for controlling the second switching element (S2), the seventh switching element (S7), and the eighth switching element (S8) in an off state.
Performing the step-up operation or the step-down operation using the four modes of
The DC / DC converter (3) according to any one of items 2 to 9.
According to this, various controls are possible by combining the four modes.
[Item 11]
One second diode (De) is connected in antiparallel to two or more switching elements connected in series.
The DC / DC converter (3) according to item 1.
According to this, the recovery loss can be efficiently reduced with a small number of second diodes (De).
[Item 12]
The switching element (S1-S8) is an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
The first diode (D1-D8) is a parasitic diode of the N-channel MOSFET.
The DC / DC converter (3) according to any one of items 1 to 11.
According to this, it is possible to reduce the recovery loss due to the reflux current flowing through the parasitic diode.

1 1st DC power supply, 2 2nd DC power supply, 3 DC / DC converter, 30 DC / DC converter, 31, 32 flying capacitor circuit, 40 control unit, C1, C2 flying capacitor, C3, C4 split capacitor, C5 Input capacitor, C6 output capacitor, L1, L2 reactor, S1-S8 8th switching element, D1-D8 parasitic diode, De1-De14 14th external diode.

Claims (12)

At least one reactor connected to the low voltage side DC section,
A first flying capacitor circuit and a second flying capacitor circuit connected in parallel with the high-voltage side DC unit are provided.
The positive terminal of the low-voltage side DC section and the midpoint of the first flying capacitor circuit are electrically connected, and the negative terminal of the low-voltage side DC section and the midpoint of the second flying capacitor circuit are electrically connected. Connected to
The reactor has a path connecting the positive terminal of the low-voltage side DC portion and the midpoint of the first flying capacitor circuit, and between the negative terminal of the low-voltage side DC portion and the midpoint of the second flying capacitor circuit. Is inserted in at least one of the routes connecting the
The first flying capacitor circuit and the second flying capacitor circuit include a plurality of switching elements in which a first diode is formed or connected in antiparallel, respectively.
This DC / DC converter is
Further comprising at least one second diode for bypassing the current flowing through the at least one first diode connected in antiparallel to at least one of the plurality of switching elements.
DC / DC converter. The first flying capacitor circuit is
The first switching element, the second switching element, the third switching element and the fourth switching element connected in series,
A first flying capacitor connected between the connection point between the first switching element and the second switching element and the connection point between the third switching element and the fourth switching element is included.
The second flying capacitor circuit is
The fifth switching element, the sixth switching element, the seventh switching element and the eighth switching element connected in series,
A second flying capacitor connected between the connection point between the fifth switching element and the sixth switching element and the connection point between the seventh switching element and the eighth switching element is included.
The first diode is formed or connected in antiparallel to each of the first switching element and the eighth switching element.
The DC / DC converter according to claim 1. Four of the second diodes are connected in antiparallel to each of the third switching element, the fourth switching element, the fifth switching element, and the sixth switching element.
The DC / DC converter according to claim 2. Four of the second diodes are connected in antiparallel to each of the first switching element, the second switching element, the seventh switching element, and the eighth switching element.
The DC / DC converter according to claim 2 or 3. The forward voltage of the second diode is lower than the forward voltage of the first diode.
The recovery loss of the second diode is lower than the recovery loss of the first diode.
The DC / DC converter according to claim 3 or 4. One second diode is connected in antiparallel to both ends of the first switching element and the second switching element connected in series.
One second diode is connected in antiparallel to both ends of the seventh switching element and the eighth switching element connected in series.
The DC / DC converter according to claim 2. One second diode is connected in antiparallel to both ends of the third switching element and the fourth switching element connected in series.
One second diode is connected in antiparallel to both ends of the fifth switching element and the sixth switching element connected in series.
The DC / DC converter according to claim 2 or 6. One second diode is connected in antiparallel to both ends of the fourth switching element and the fifth switching element connected in series.
The DC / DC converter according to any one of claims 2, 4 and 6. One second diode is connected in antiparallel to both ends of the third switching element, the fourth switching element, the fifth switching element, and the sixth switching element connected in series.
The DC / DC converter according to any one of claims 2, 4 and 6. By controlling the first flying capacitor circuit and the second flying capacitor circuit, power is transmitted from the low voltage side DC section to the high voltage side DC section by a boosting operation, and the voltage is stepped down from the high voltage side DC section to the low voltage side DC section. It also has a control unit that can execute at least one of the power transmissions in operation.
The control unit
The second switching element, the fourth switching element, the fifth switching element and the seventh switching element are turned on, and the first switching element, the third switching element, the sixth switching element and the eighth switching. First mode, which controls the element to the off state,
The first switching element, the third switching element, the sixth switching element and the eighth switching element are turned on, and the second switching element, the fourth switching element, the fifth switching element and the seventh switching. The second mode, which controls the element to the off state,
The first switching element, the second switching element, the seventh switching element and the eighth switching element are turned on, and the third switching element, the fourth switching element, the fifth switching element and the sixth switching. Third mode, which controls the element to the off state,
The third switching element, the fourth switching element, the fifth switching element and the sixth switching element are turned on, and the first switching element, the second switching element, the seventh switching element and the eighth switching. Fourth mode, which controls the element to the off state,
Performing the step-up operation or the step-down operation using the four modes of
The DC / DC converter according to any one of claims 2 to 9. One second diode is connected in antiparallel to two or more switching elements connected in series.
The DC / DC converter according to claim 1. The switching element is an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
The first diode is a parasitic diode of the N-channel MOSFET.
The DC / DC converter according to any one of claims 1 to 11.

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