JP2021159139A - Game machine - Google Patents

Abstract

To provide a game machine that can arrange wiring patterns on a substrate more efficiently.SOLUTION: A game machine includes a first arrangement area in which a chip having a CPU circuit built in is arranged and a second arrangement area in which a ROM is arranged on a first wiring layer L1 out of a plurality of wiring layers L1 to L6. Specific interlayer conductive parts v61 to v102 are arranged in the second arrangement area, a plurality of wiring paths P2- connecting the chip and the ROM includes a plurality of specific wiring paths to be wired via the specific interlayer conductive parts v61 to v102. The plurality of specific wiring paths includes a first wiring path for transmitting address information or data information and a second wiring path for transmitting chip select information. The first wiring path and the second wiring path are connected to the specific interlayer conductive parts from the chip side in the wiring layers different from each other.SELECTED DRAWING: Figure 40

Description

The present invention relates to gaming machines such as pachinko machines and slot machines.

In a game machine such as a pachinko machine, various control means such as an effect control means, a payout control means, a launch control means, and a main control means for controlling them are mounted on a plurality of substrates in a distributed manner. Electronic components such as composite chips (LSIs) with built-in CPU circuits, various ICs, ROMs, capacitors, resistors, and connectors are mounted on each control board, and wiring patterns for connecting these electronic components are For example, it is formed so as to straddle a plurality of wiring layers (Patent Document 1).

Japanese Unexamined Patent Publication No. 2019-187989

In recent years, gaming machines are equipped with a large number of various production means such as movable bodies and image display means, and they tend to be large in size. Therefore, it is necessary to efficiently arrange a large number of parts in a limited space. Various boards arranged on the rear side of the game machine main body are no exception, and it is required to efficiently arrange complicated wiring patterns in order to minimize the size of the boards.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a gaming machine capable of arranging wiring patterns on a substrate more efficiently.

The present invention includes a substrate having a plurality of wiring layers and an interlayer conduction portion in the plate thickness direction for conducting the plurality of wiring layers with each other, and a CPU is used as the first wiring layer among the plurality of wiring layers. In a gaming machine provided with a first arrangement area in which a chip having a circuit is arranged and a second arrangement area in which a ROM connected to the chip is arranged, the interlayer conduction portion is contained in the second arrangement area. The plurality of wiring paths for arranging the specific interlayer conductive portion and connecting the chip and the ROM include a plurality of specific wiring paths routed through the specific interlayer conductive portion, and the plurality of specific wirings. The path includes a first wiring path for transmitting address information or data information and a second wiring path for transmitting chip select information, and the first wiring path and the second wiring path are different from each other. It is connected to the specific interlayer conductive portion from the chip side.

According to the present invention, it is possible to arrange the wiring pattern on the substrate more efficiently.

It is an overall front view of the pachinko machine which concerns on one Embodiment of this invention. It is an exploded perspective view of the pachinko machine. It is an exploded perspective view of the glass door of the pachinko machine. It is a top view which shows the operation effect means of the pachinko machine, a cross operation button, a volume adjustment button, a light amount adjustment button, and the like. It is a front view of the game board of the pachinko machine. It is a front view of the game information display means of the pachinko machine. It is a rear view of the pachinko machine. It is an exploded perspective view of the production board case and the production control unit of the pachinko machine. It is a plan sectional view of the production board case and the production control unit of the pachinko machine. It is a block diagram which shows the whole circuit composition of the pachinko machine. It is a circuit block diagram which illustrated about the composite chip mounted on the liquid crystal control board of the pachinko machine, including the related circuit elements. It is a figure which shows the wiring pattern of the 1st wiring layer in the liquid crystal control board of the pachinko machine. It is a figure which shows the wiring pattern of the 2nd wiring layer in the liquid crystal control board of the pachinko machine. It is a figure which shows the wiring pattern of the 3rd wiring layer in the liquid crystal control board of the pachinko machine. It is a figure which shows the wiring pattern of the 4th wiring layer in the liquid crystal control board of the pachinko machine. It is a figure which shows the wiring pattern of the 5th wiring layer in the liquid crystal control board of the pachinko machine. It is a figure which shows the wiring pattern of the 6th wiring layer in the liquid crystal control board of the pachinko machine. It is a figure which shows the terminal information of the composite chip arranged on the liquid crystal control board of the pachinko machine. It is a figure which shows the terminal information of the control ROM arranged on the liquid crystal control board of the pachinko machine. It is a figure which extracted only the wiring lines P1 to P47 from the 1st wiring layer in the liquid crystal control board of the pachinko machine. It is a figure which extracted only the wiring lines P1 to P47 from the 2nd wiring layer in the liquid crystal control board of the pachinko machine. It is a figure which extracted only the wiring lines P1 to P47 from the 3rd wiring layer in the liquid crystal control board of the pachinko machine. It is a figure which extracted only the wiring lines P1 to P47 from the 4th wiring layer in the liquid crystal control board of the pachinko machine. It is a figure which extracted only the wiring lines P1 to P47 from the 5th wiring layer in the liquid crystal control board of the pachinko machine. It is a figure which extracted only the wiring lines P1 to P47 from the 6th wiring layer in the liquid crystal control board of the pachinko machine. It is an enlarged view of the region E1a in FIG. It is an enlarged view of the region E1b in FIG. It is an enlarged view of the region E3a in FIG. 22. It is an enlarged view of the region E3b in FIG. 22. It is an enlarged view of the region E3c in FIG. 22. It is an enlarged view of the region E4 in FIG. 23. It is an enlarged view of the region E6a in FIG. 25. It is an enlarged view of the region E6b in FIG. 25. It is an enlarged view of the region E6c in FIG. It is a figure which shows typically the wiring path of the wiring path P1 to P8 in the liquid crystal control board of the pachinko machine which concerns on one Embodiment of this invention. It is a figure which shows typically the wiring path of the wiring path P9 to P17 in the liquid crystal control board of the pachinko machine. It is a figure which shows typically the wiring path of the wiring path P18-P26 in the liquid crystal control board of the pachinko machine. It is a figure which shows typically the wiring path of the wiring path P27-P34 in the liquid crystal control board of the pachinko machine. It is a figure which shows typically the wiring path of the wiring path P35-P42 in the liquid crystal control board of the pachinko machine. It is a figure which shows typically the wiring path of the wiring path P43-P47 in the liquid crystal control board of the pachinko machine. It is a circuit diagram of the decoding circuit in the liquid crystal control board of the pachinko machine. It is a circuit diagram of the reset circuit in the liquid crystal control board of the pachinko machine. It is a figure which shows the silk printing pattern on the 1st wiring layer side in the liquid crystal control board of the pachinko machine.

Hereinafter, embodiments of the invention will be described in detail with reference to the drawings. 1 to 43 illustrate an embodiment in which the present invention is applied to a pachinko machine. In FIGS. 1 and 2, the gaming machine main body 1 includes an outer frame 2 and a front frame 3 arranged on the front side of the outer frame 2. The front frame 3 is pivotally attached to the outer frame 2 via a first hinge 4 in the vertical direction arranged on one end side in the left-right direction, for example, the left end side, and is pivotally attached to the outer frame 2 so as to be openable and detachable. The outer frame 2 can be locked in a closed state by the locking means 5 provided on the opposite side, for example, the right end side.

The front frame 3 includes an inner frame 6 and a front door 7 arranged on the front side of the inner frame 6. The front door 7 is pivotally attached to the inner frame 6 via a second hinge 8 in the vertical direction arranged on one end side in the left-right direction, for example, the left end side, and is pivotally attached to the inner frame 6 by the locking means 5. It can be locked in the closed state.

As shown in FIG. 2, the outer frame 2 is formed in a rectangular shape by a pair of left and right vertical frame members 2a and 2b and a pair of upper and lower horizontal frame members 2c and 2d. For example, a front cover member 9 made of synthetic resin is attached to the lower front side of the outer frame 2 so as to connect the lower front side of the left and right vertical frame members 2a and 2b along the front edge of the lower horizontal frame member 2d. There is. The front cover member 9 projects forward from the left and right vertical frame members 2a and 2b, and the inner frame 6 is arranged on the upper side thereof. Further, in the outer frame 2, the outer frame upper hinge metal fittings 11 constituting the first hinge 4 are arranged, for example, in the upper left portion, and the outer frame lower hinge metal fittings 12 are arranged in the upper left portion of the front cover member 9 in the lower left portion, respectively.

The inner frame 6 is made of synthetic resin, and has a rectangular frame portion 13 that can substantially contact the front edge side of the outer frame 2 on the upper side of the front cover member 9, and a game board provided on the upper side of the frame portion 13. For example, the mounting portion 14 and the lower mounting portion 15 provided on the lower side in the frame portion 13 are integrally provided. A game board 16 is detachably mounted on the game board mounting portion 14, for example, from the front side, and a launching means 17, a lower speaker 18, and the like are arranged on the lower mounting portion 15 on the front side thereof. Further, in the inner frame 6, the main body frame upper hinge metal fittings 19 constituting the first hinge 4 and the main body frame upper hinge metal fittings 20 forming the second hinge 8 are, for example, in the upper left portion, and the first, second hinges 4, 8 are provided. The hinge metal fittings 21 under the main body frame constituting the above are arranged, for example, in the lower left portion.

The front door 7 includes a resin door base 22 formed in a rectangular shape corresponding to the front side of the inner frame 6. The door base 22 is formed with window holes 24a of the glass window 24 corresponding to the front side of the game area 23 formed on the game board 16, and a plurality of window holes 24a (here, four) are formed around the window holes 24a, for example. Various effect means such as the upper speaker 25, the frame first movable body 26, the frame second movable body 27, and the blowing means 28 are arranged.

On the upper front side of the door base 22, a side unit 30 is attached to at least a part of the outer circumference of the window hole 24a, for example, a front view inverted L-shaped portion corresponding to the upper side and the right side of the window hole 24a, and the other one. An upper decorative cover 31 is attached to a portion, for example, the left side of the window hole 24a. Inside the side unit 30 and the upper decorative cover 31, a large number of LEDs constituting the illumination for directing are arranged. As shown in FIGS. 2 and 3, the side unit 30 operates the fixing screw 30a, the fixing lever 30b, etc. on the back side of the front frame 3 with the front frame 3 open without using a special tool. By doing so, it can be easily attached and detached. Normally, the front frame 3 is commonly used by a plurality of models, and by mounting a game board 16 different for each model on the front frame 3, the playability and design peculiar to the model are realized. In the machine, a part of the front side of the front frame 3 is a side unit 30 that can be easily attached and detached as compared with other parts, and this side unit 30 has a design and unique functions that are integrated with the game board 16. By making it possible, it is possible to increase the degree of freedom in design and function for each model while making most of the front frame 3 common.

In addition to the LED for illumination, the side unit 30 of the present embodiment is equipped with a frame first movable body 26, a frame second movable body 27, a blowing means 28, and the like. The frame first movable body 26 can slide and move in the substantially front-rear direction by driving a driving means (not shown). The frame second movable body 27 can be slid and moved substantially in the front-rear direction by driving a driving means (not shown), and can be pushed by the player. The blowing means 28 can blow wind toward the player's hand, for example, at the timing when the player operates the frame second movable body 27.

On the lower front side of the door base 22, the upper plate 33 that stores the game balls paid out from the payout means 32 arranged on the rear side of the inner frame 6 and supplies them to the launching means 17, and the upper plate 33 is full. A lower plate 34 for storing surplus balls and the like, a launch handle 35 for operating the launching means 17, and the like are arranged, and a lower decorative cover 36 for substantially covering the upper plate 33, the lower plate 34, etc. from the front side is attached. Has been done. The lower decorative cover 36 is formed in a forward-facing bulge shape, for example, and various operation means such as an operation effect means 37, a cross operation button 38, a volume adjustment button 39, and a light amount adjustment button 40 are provided on the upper side thereof, for example. (Fig. 4).

The operation effect means 37 is used for a notice effect during a symbol change and other effects, and is a vertical movement type effect button 41 that can be pressed and operated by the player, and a frame third arranged inside the effect button 41. It includes a movable body 42 and the like. The frame third movable body 42 is composed of, for example, a substantially spherical rotating body that can rotate around a horizontal axis, and can be rotated in both forward and reverse directions by a rotary drive motor 43.

As shown in FIG. 4, the cross operation button 38 includes four operation buttons 38a to 38d up, down, left, and right, and is used in situations where operations such as moving the cursor up, down, left, and right are required, such as when a player selects a menu item. used. The volume adjustment button 39 is used by the player to adjust the volume. As shown in FIG. 4, the volume adjustment button 39 is operated when the player wants to raise the volume from the speaker, and the plus button 39a is operated when the player wants to lower the volume. It is equipped with a minus button 39b to operate. The light amount adjustment button 40 is used for adjusting the light amount by the player, and is the same as the plus button 40a that the player operates when he / she wants to increase the light amount of the LED illumination as shown in FIG. 4, and when he / she wants to decrease the light amount. It is equipped with a minus button 40b to operate. In the present embodiment, the volume adjustment button 39 dedicated to volume adjustment and the light amount adjustment button 40 dedicated to light amount adjustment are provided, but without providing them, general-purpose operation means such as the cross operation button 38 can be used for volume adjustment and light amount. It may also be used for adjustment.

As shown in FIG. 2, a glass unit 50 that substantially closes the window hole 24a from the rear side is detachably mounted on the back side of the door base 22, and is attached to the edges on the first, second hinges, and 8 sides. The vertical hinge end side reinforcing sheet metal 51a arranged along the vertical direction, the vertical opening / closing end side reinforcing sheet metal 51b arranged along the opening / closing end side edge, and the left and right arranged below the window hole 24a. The lower reinforcing sheet metal 51c in the direction is detachably fixed by screwing or the like. Further, on the door base 22, the hinge metal fittings 52a on the glass door constituting the second hinge 8 are arranged, for example, in the upper left portion, and the hinge metal fittings 52b below the glass door are arranged in the lower left portion, for example.

Further, for example, a ball feed unit 53a, a lower plate guide unit 53b, and the like are mounted on the back side of the lower reinforcing sheet metal 51c. The ball feeding unit 53a is for supplying the game ball in the upper plate 33 to the launching means 17, and is arranged corresponding to the front side of the launching means 17 arranged on the inner frame 6 side, and the launching means 17 By operating the ball feed solenoid 53c in synchronization with the firing operation of the above plate 33, the game balls in the upper plate 33 are supplied one by one onto the firing rail 17a of the launching means 17.

The launching means 17 includes a launch rail 17a arranged in an inclined shape that rises to the left when viewed from the front, and a launch ball stopper 17b that supports a game ball supplied on the launch rail 17a by the ball feed unit 53a at a launch standby position. A striking mallet 17c that is arranged corresponding to a launch standby position on the launch rail 17a and is swingable around a drive shaft in the front-rear direction, and a launch drive means 17d such as a rotary solenoid that swings and drives the striking mallet 17c. When the firing handle 35 is rotationally operated, the firing driving means 17d continuously drives the striking mallet 17c in the striking direction (clockwise) with a firing intensity corresponding to the amount of operation.

The lower plate guide unit 53b guides the surplus ball when the upper plate 33 is full and the foul ball that has returned without reaching the game area 23 even though it was launched by the launching means 17 to the lower plate 34. For example, the ball feed unit 53a is adjacent to the ball feed unit 53a and is arranged on the first, second hinges, 4 and 8 sides thereof.

As shown in FIG. 5, the game board 16 includes a base plate 55 made of a veneer plate, a polycarbonate plate, or the like, and a guide rail 56 for guiding a game ball launched from the launching means 17 is annularly formed on the front side of the base plate 55. In addition to being arranged, a large number of game nails (not shown) are arranged in the game area 23 inside the guide rail 56, in addition to unit parts such as the central display frame unit 57, the starting winning unit 58, and the normal winning unit 59. Further, the game information display means 60 is arranged on the outer side of the game area 23, for example, on the lower side. Of course, the game information display means 60 may be arranged in the game area 23.

As shown in FIG. 6, the game information display means 60 includes four LED groups composed of, for example, eight LEDs 70, and a total of 32 LEDs 70 are the normal symbol display means 61 and the normal hold number display means. 62, 1st special symbol display means 63, 2nd special symbol display means 64, 1st special hold quantity display means 65, 2nd special hold quantity display means 66, fluctuation shortening notification means 67, right-handed notification means 68 and number of rounds. A predetermined number is assigned to the notification means 69. That is, each of the eight LEDs 70 belonging to the first and second LED groups 60a and 60b constitutes the first and second special symbol display means 63 and 64, respectively, and the eight LEDs 70 belonging to the third LED group 60c are two. Eight LEDs 70 belonging to the fourth LED group 60d, respectively, constitute the first special reserved quantity display means 65, the second special reserved quantity display means 66, the normal hold quantity display means 62, and the fluctuation shortening notification means 67, respectively. Two of them form the normal symbol display means 61, the other two form the right-handed notification means 68, and the remaining four form the round number notification means 69, respectively.

On the plurality of unit parts 57 to 59 of the game board 16, a normal symbol starting means 71, a first special symbol starting means 72, a second special symbol starting means 73, a large winning means 74, a plurality of ordinary winning means 75, and the like are placed. It is provided. Further, on the rear side of the base plate 55, in addition to the liquid crystal display unit (image display means) 76, movable bodies such as the first movable body 77 of the board, the second movable body 78 of the board, and the third movable body 79 of the board are arranged. There is.

The central display frame unit 57 constitutes the display frame of the liquid crystal display unit 76 and the movable bodies 77 to 79, and the opening window 80 corresponding to the liquid crystal display unit 76 on the rear side is formed substantially in the center of the base plate. It is detachably mounted from the front side with respect to the mounting hole (not shown) formed in 55 in the front-rear direction. As shown in FIG. 5, the central display frame unit 57 is arranged outside the mounting hole along the front surface of the base plate 55, and the front mounting plate 81 through which the game ball can pass, and the liquid crystal display unit 76. The decorative frame 82 is arranged in the shape of a front view gate extending from both the left and right sides to the upper side on the front side, and is arranged forward on the inner peripheral side of the front mounting plate 81, and between the left and right lower ends of the decorative frame 82. It has a stage 83 to be played. The game ball launched by the launching means 17 and entering the upper side of the game area 23 is distributed to the left and right at the top of the decorative frame 82, and the left flow path 84a on the left side and the right flow path 84b on the right side of the central display frame unit 57. Flow down either.

The central display frame unit 57 is provided with a warp inlet 85 through which a game ball can flow, on at least one side of the left flow path 84a side and the right flow path 84b side, for example, the left flow path 84a side. The game ball that has flowed into the warp inlet 85 while flowing down the left flow path 84a freely rolls in the left-right direction on the stage 83, and then is provided at the center of the game area 23 in the left-right direction. It falls to the front side from any of the other parts.

Both the first movable body 77 and the third movable board 79 are arranged in a horizontally long shape on the front side of the liquid crystal display unit 76, and both left and right ends thereof are supported outside the opening window 80 so as to be movable in the vertical direction. It can be individually moved up and down by a lifting drive means (not shown). The board second movable body 78 is a three-dimensional model formed in a predetermined shape such as a character, is arranged on the front side of the board first movable body 77, and can move up and down integrally with the board first movable body 77. At the same time, by driving the rotation driving means (not shown), it is possible to rotate the first movable body 77 of the board around the central axis in the front-rear direction.

As shown in FIG. 5, the start winning unit 58 is arranged on the lower side of the central display frame unit 57 along the guide rail 56, and is detachably attached to the base plate 55 from the front side. As shown in FIG. 5, the ordinary winning unit 59 is arranged along the guide rail 56 on the left side of the starting winning unit 58 under the central display frame unit 57, and is detachably attached to the base plate 55 from the front side. ing.

The normal symbol starting means 71 is for starting the variable display of the normal symbol by the normal symbol display means 61, and is composed of a passing gate or the like through which the game ball can pass, and is a game ball detection switch for detecting the passage of the game ball. (Not shown). As shown in FIG. 5, the ordinary symbol starting means 71 is provided, for example, on the front side of the front mounting plate 81 on the right side of the central display frame unit 57, and allows a game ball flowing down the right flow path 84b to pass through. ing.

The normal symbol display means 61 is for displaying the normal symbol in a variable manner, and is composed of a predetermined number (here, two) of LEDs 70 in the game information display means 60 as shown in FIG. Based on the fact that 71 detects a game ball, after those two LEDs 70 constituting the normal symbol emit light in a light emitting pattern during normal fluctuation, the normal random number information acquired at the time of detection of the game ball by the normal symbol starting means 71 is used. If the included hit determination random number value matches a predetermined hit determination value, the fluctuation is stopped in the hit mode, and in other cases, the fluctuation is stopped in the off mode. It should be noted that the two LEDs 70 constituting the normal symbol can display one or more hit modes and one or more missed modes depending on the combination of their light emitting modes (for example, lighting / extinguishing), and are in normal fluctuation. As for the light emission pattern, for example, a plurality of specific types (here, two types) of light emission modes are switched at predetermined time (for example, 128 ms).

Further, when the ordinary symbol starting means 71 detects a game ball during the ordinary holding period including the symbol fluctuation of the ordinary symbol display means 61 and the ordinary profit state, the ordinary random number information acquired by the detection is predetermined. The maximum number of reserved symbols, for example, 4 is reserved and stored, and each time the normal holding period ends, one is consumed and the normal symbol is changed. The stored number of ordinary random number information (ordinary hold number) is notified to the player by the ordinary hold number display means 62 or the like. As shown in FIG. 6, the normally held number display means 62 is composed of a predetermined number (two in this case) of LEDs 70 in the game information display means 60, and each of the two LED 70s emits light (for example, lighting / lighting /). By combining blinking / extinguishing), it is possible to display 5 types of normal hold numbers of 0 to 4.

The first special symbol starting means 72 is for starting the symbol variation by the first special symbol display means 63, and is composed of non-opening / closing winning means having no opening / closing means, and is a game ball that detects a winning game ball. It is equipped with a detection switch (not shown). As shown in FIG. 5, the first special symbol starting means 72 is provided in, for example, the starting winning unit 58, and is arranged in an upward opening shape on the lower side corresponding to the central falling portion 86 of the stage 83, and is left. Due to the existence of a winning route from the warp inlet 85 on the flow path 84a side via the stage 83, the probability that the game ball that has flowed down the left flow path 84a is higher than that of the game ball that has flowed down the right flow path 84b. It is possible to win a prize at. When a game ball wins the first special symbol starting means 72, a predetermined number of game balls per winning is paid out as a prize ball.

The second special symbol starting means 73 is for starting the symbol variation by the second special symbol displaying means 64, and the game ball can be won in the open state and cannot be won (or from the open state) by the operation of the opening / closing unit 88. A game ball detection switch (not shown) that detects a winning game ball and an opening / closing driving means such as an electromagnetic solenoid that opens / closes the opening / closing unit 88. When the stop symbol after the change of the normal symbol display means 61 becomes a hit mode and a normal profit state occurs, the opening / closing unit 88 changes from the closed state to the open state for a predetermined time. There is.

As shown in FIG. 5, the second special symbol starting means 73 is arranged, for example, on the front mounting plate 81 on the right side of the central display frame unit 57 and on the downstream side of the normal symbol starting means 71, and is a right flow path. The game ball that has flowed down 84b can win a prize. The opening / closing portion 88 can swing around a rotation axis in the left-right direction provided on the lower side, for example, and in the closed state, the opening / closing portion 88 is substantially flush with the front mounting plate 81 so that the game ball can pass through the front side and is opened. In the state, the front side of the front mounting plate 81 has an inclined shape that descends backward so that the game ball can win a prize backward. When a game ball wins the second special symbol starting means 73, a predetermined number of game balls per winning is paid out as a prize ball.

As shown in FIG. 6, the first special symbol display means 63 is composed of a predetermined number (8 in this case) of LEDs 70 in the game information display means 60, and the first special symbol starting means 72 detects a game ball. On the condition that the eight LEDs 70 constituting the first special symbol emit light in the light emission pattern during the special fluctuation, the information is included in the first special random number information acquired when the game ball is detected by the first special symbol starting means 72. When the jackpot determination random number value to be determined matches a predetermined jackpot determination value, the fluctuation is stopped in the first jackpot mode, and in other cases, the fluctuation is stopped in the first missed mode. When the stop symbol after the change of the first special symbol display means 63 becomes the first jackpot mode, the first extraordinary profit state occurs.

As shown in FIG. 6, the second special symbol display means 64 is composed of a predetermined number (8 in this case) of LEDs 70 in the game information display means 60, and the second special symbol starting means 73 detects the game ball. On condition that, after those eight LEDs 70 constituting the second special symbol emit light in the light emission pattern during the special fluctuation, they are included in the second special random number information acquired when the game ball is detected by the second special symbol starting means 73. When the jackpot determination random number value to be determined matches a predetermined jackpot determination value, the fluctuation is stopped in the second jackpot mode, and in other cases, the fluctuation is stopped in the second missed mode. When the stop symbol after the change of the second special symbol display means 64 becomes the second big hit mode, the second extraordinary profit state occurs.

The first and second special symbol display means 63 and 64 have one or a plurality of first and second jackpot modes and one or a plurality of first, depending on the combination of the light emitting modes (for example, lighting / extinguishing) of each of the eight LEDs 70. The second out-of-range mode can be displayed, and the light emission pattern during the special fluctuation is adapted to switch the light emission mode of a specific plurality of types (here, two types) at predetermined time (for example, 128 ms).

In addition, the first and second special symbols are started during the special holding period including the symbol change of the first special symbol display means 63, the symbol change of the second special symbol display means 64, and the first and second extraordinary profit states. When the means 72 and 73 detect the game ball, the first and second special random number information acquired by the means 72 and 73 are stored in a predetermined maximum number of pending numbers, for example, four each. Then, when the hold memory on the second special symbol side is 1 or more at the end of the special hold period, one hold memory of the second special symbol is digested to change the second special symbol, and the first When only the reserved memory on the special symbol side is 1 or more, one reserved memory of the 1st special symbol is digested and the 1st special symbol is changed. As described above, in the present embodiment, when both the first special symbol and the second special symbol are not changing, and there is a hold memory on both the first special symbol side and the second special symbol side. Is designed to give priority to the change of the second special symbol.

The number of stored first and second special random number information (first and second special reserved number) is notified to the player by the first and second special reserved number display means 65, 66, the liquid crystal display unit 76, and the like. NS. Here, as shown in FIG. 6, the first and second special reserved number display means 65 and 66 are composed of a predetermined number (here, two each) of LEDs 70 in the game information display means 60, and their light emitting modes ( For example, by combining lighting / blinking / extinguishing), it is possible to display 5 types of 1st and 2nd special hold numbers of 0 to 4.

The large winning means 74 is an opening / closing type winning means provided with an opening / closing plate 89 that can switch between an open state in which the game ball can win and a closed state in which the game ball cannot win. A game ball detection switch (not shown) for detecting a winning game ball and an opening / closing driving means such as an electromagnetic solenoid for opening / closing the opening / closing plate 89 are provided on the downstream side of the second special symbol starting means 73. Moreover, because it is arranged on the upstream side of the first special symbol starting means 72, the game ball that has flowed down the right flow path 84b can win a prize with a higher probability than the game ball that has flowed down the left flow path 84a. It has become. The first prize-winning means 74 is generated when the first and second special symbols of the first and second special symbol display means 63 and 64 stop in the first and second big hit modes (specific modes) after the change. , In the second extraordinary profit state, the opening / closing plate 89 opens to the front side according to any one or a plurality of types of opening patterns, and the game ball that has fallen on the opening / closing plate 89 is made to win a prize inside. When a game ball wins the large prize-winning means 74, a predetermined number of game balls are paid out as prize balls per prize.

Further, the liquid crystal display unit 76 can variablely display the effect symbol 90 in parallel with the variable display of the first and second special symbols by the first and second special symbol display means 63 and 64, and the first and first special symbols. 2. Various images such as the first and second reserved images X1 to X4, Y1 to Y4, and the changing pending image Z indicating the number of special reserved images can be displayed.

Here, the effect symbol 90 includes a plurality of symbol sequences (here, three in the left-right direction) composed of a plurality of symbol symbols and other symbols, and each symbol constituting each of these symbol sequences is shown in FIG. As shown in the above, it is composed of a combination of a symbol main body 90a composed of numbers such as 1 to 8 and others, and a character or other decorative portion 90b attached to the symbol main body 90a. The display mode of the effect symbol 90 can be arbitrarily changed, such as enlargement or reduction, change of the display position, and erasure of the decorative portion 90b.

For example, the effect symbol 90 starts the fluctuation by vertical scrolling for each symbol row according to a predetermined fluctuation pattern substantially at the same time as the fluctuation start of the first and second special symbols, and the stop symbol on the predetermined effective line is the predetermined mode. For example, the final stop is performed substantially at the same time as the fluctuation stop of the first and second special symbols. In the effect symbol 90, for example, the case where all the stop symbols on the effective line are the same is the jackpot effect mode, and the other cases are the off effect mode, and the first and second special symbols are the first and second jackpot modes. If this is the case, the effect symbol 90 is in the jackpot effect mode, and if the first and second special symbols are in the first and second off modes, the effect symbol 90 is in the off effect mode.

Regarding the first and second reserved images X1 to X4, Y1 to Y4, and the changing pending image Z, the first and first first and second special symbol starting means 72 and 73 detect the game ball. 2 When the number of special reserved images increases, one additional first and second reserved images X1 to Y1 to be displayed on the liquid crystal display unit 76, and the first and second special symbol display means 63 and 64 are used. When the number of first and second special reservations decreases based on the start of new fluctuations of the first and second special symbols, for example, the changing hold image Z is deleted and the first and second reserved images X1 to , Y1 to the front side of the queue (for example, the right side of the screen) by one, and the extruded first and second reserved images X1 and Y1 are moved to a predetermined position, for example, to make a new fluctuation. It is designed to be changed to the middle hold image Z.

Further, as shown in FIG. 7, a back case 91 for supporting the liquid crystal display unit 76 on the rear side of the game board 16 is mounted on the back side of the game board 16, and a main control is provided on the back side of the back case 91. A main board case 94 in which the main control board 93 constituting the unit 92 is stored, an effect interface board 96 in which the effect control unit 95 is formed, a liquid crystal interface board 97, a liquid crystal control board 98, and a production board case in which the ROM board 99 is stored. 100 etc. are detachably attached.

Here, the effect interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98, and the ROM board 99 will be described in detail with reference to FIGS. 8 and 9 in detail of the state of being stored in the effect board case 100.

The effect interface board 96 and the liquid crystal interface board 97 are arranged so that the surfaces 96a and 97a are on the rear side and are close to each other on the left and right sides. The effect interface board 96 and the liquid crystal interface board 97 are the effect IF first and second connectors CN11 and CN12 arranged along the edge of the effect interface board 96 on the liquid crystal interface board 97 side, and the liquid crystal interface board 97. The liquid crystal IF first and second connectors CN21 and CN22 arranged along the edge of the production interface board 96 side are directly connected to each other in the left-right direction to be integrated with each other. In the production interface board 96, various electronic components are arranged on both the front and back surfaces, but various ICs such as an audio processor 101 and a digital amplifier 102, and various connectors such as liquid crystal IF first to third connectors CN21 to CN23, The audio ROM 103 and the like are arranged on the surface 96a side. Further, with respect to the liquid crystal interface substrate 97, various electronic components are arranged on both the front and back surfaces, but various connectors such as the liquid crystal IF first to third connectors CN21 to CN23 are arranged on the surface 97a side.

Further, the liquid crystal control board 98 is placed behind the effect interface board 96 and the liquid crystal interface board 97 so that the front surface 98a faces the rear side and the back surface 98b faces the surface 96a and 97a of the effect interface board 96 and the liquid crystal interface board 97. It is arranged. Then, in the liquid crystal control board 98, the liquid crystal control first connector CN31 provided on the back surface 98b side thereof is attached to the production IF third connector CN13 on the production interface board 96 side, and the liquid crystal control second connector CN32 also provided on the back surface 98b side. Is directly connected to the liquid crystal IF third connector CN23 on the liquid crystal interface board 97 side, respectively, so that the effect interface board 96 and the liquid crystal interface board 97 are integrated. In the liquid crystal control board 98, various electronic components are arranged on both the front and back surfaces, the composite chip 104, the control ROM 105, the DRAM 106, the liquid crystal control third connector CN33 and the like are arranged on the front surface 98a side, and the liquid crystal control third connector CN33 and the like are arranged on the back surface 98b side. The liquid crystal control first and second connectors CN31, CN32 and the like are arranged in.

Further, the ROM substrate 99 is adjacent to the liquid crystal control substrate 98, for example, so that the front surface 99a faces backward and the back surface 99b faces the front surface 97a of, for example, the liquid crystal interface substrate 97 of the effect interface substrate 96 and the liquid crystal interface substrate 97. It is located below it. The ROM substrate 99 is formed by directly connecting the ROM first connector CN41 arranged on the upper edge portion on the surface 99a side to the liquid crystal control third connector CN33 arranged on the lower edge portion of the liquid crystal control board 98. It is integrated with the liquid crystal control board 98. In the ROM board 99, various electronic components are arranged on both the front and back surfaces, but the CGROM 107, the ROM first connector CN41, and the like are arranged on the surface 99a side.

As described above, the boards 96 to 99 are formed by directly connecting the connectors to each other so that the front surfaces 96a and 97a of the effect interface board 96 and the liquid crystal interface board 97 and the back surfaces 98b and 99b of the liquid crystal control board 98 and the ROM board 99 are connected. Are connected and integrated in a state where they face each other with a predetermined gap. Therefore, when the substrates 96 to 99 are connected to each other, the back surface 98b side of the liquid crystal control substrate 98 is hidden behind the effect interface substrate 96 and the liquid crystal interface substrate 97 and cannot be visually recognized.

The effect substrate case 100 is made of a transparent synthetic resin, and is formed in a substantially box shape by a base body 111 that covers the back surface side of the substrates 96 to 99 and a cover body 112 that covers the front surface side of the substrates 96 to 99. When the boards 96 to 99 are stored in the effect board case 100, the liquid crystal control board 98 and the ROM board 99 are first connected to each other by direct connection of the connector, and then screwed to a predetermined position inside the cover body 112. Fix it. At this time, the surfaces 98a and 99a of the liquid crystal control substrate 98 and the ROM substrate 99 face each other with a predetermined gap on the inner surface side of the back wall 113 of the cover body 112.

Next, the effect interface board 96 and the liquid crystal interface board 97 are fitted into a predetermined position inside the cover body 112 from the back side of the liquid crystal control board 98 and the ROM board 99 in a state of being directly connected to each other by the connector. At this time, the effect IF third connector CN13 on the effect interface board 96 side is connected to the liquid crystal control first connector CN31 on the liquid crystal control board 98 side, and the liquid crystal IF third connector CN23 on the liquid crystal interface board 97 side is the liquid crystal on the liquid crystal control board 98 side. It is coupled to the control second connector CN32, respectively.

Subsequently, the base body 111 is fitted to the cover body 112 from the back surface 96b, 97b side of the effect interface board 96 and the liquid crystal interface board 97. Further, the substrates 96 to 99 are formed by screwing from the outside of the base body 111 to the screwing base 115 on the cover body 112 side via the through holes 114 of the effect interface substrate 96 and the liquid crystal interface substrate 97. It is fixed in a predetermined position in the case 100. The effect board case 100 in which the boards 96 to 99 are stored is detachably attached to the back side of the back case 91 with the base body 111 facing the front side and the cover body 112 facing the rear side.

Further, as shown in FIG. 7, a back cover 121 that covers the back side of the game board 16 so as to be openable and closable is detachably attached to the back side of the front frame 3, and the game ball tank 122 and the tank rail 123 are attached to the upper side thereof. However, the payout means 32 and the payout passage 124 are mounted on one side of each of the left and right sides, and when the game ball wins a prize in the winning opening of the large winning means 74 or the like, or a ball lending command is issued from an automatic ball lending machine (not shown). At that time, the game ball in the game ball tank 122 is paid out by the payout means 32 via the tank rail 123, and the game ball is guided to the upper plate 33 via the payout passage 124. The back cover 121 is arranged so as to cover substantially the entire effect board case 100 and a part of the upper side of the main board case 94 from the rear side.

A board mounting base 125 is detachably mounted on the lower part of the back side of the front frame 3, and a power supply board case 127 and a payout launch control board in which the power supply board 126 is stored are mounted on the back side of the board mounting base 125. The payout launch board case 129 in which 128 is stored is detachably attached to each.

FIG. 10 is a block diagram showing the overall circuit configuration of the pachinko machine. As shown in FIG. 10, the overall circuit configuration of the pachinko machine is composed of a board-side member 131 mounted on the game board 16 side and a frame-side member 132 mounted on the front frame 3 side.

The board-side member 131 includes a main control board 93 that constitutes the main control unit 92, an effect interface board 96 that constitutes the effect control unit 95, a liquid crystal interface board 97, a liquid crystal control board 98, and a ROM board 99, as well as a game board relay board. It is composed of 133, an LED connection board 134, a main control relay board 135, a power supply relay board 136, a frame LED relay board 137, and the like.

The main control board 93 comprehensively controls the game, and is a game ball detection switch provided in the ordinary symbol starting means 71, the big winning means 74, etc., an opening / closing driving means provided in the big winning means 74, etc., and a game. Various sensors for magnetism, radio waves, vibration, etc., game information display means 60, etc., arranged in each part of the board 16 are directly connected via a relay board such as the game board relay board 133 or without a relay board. Has been done. Further, the main control board 93 is connected to the effect interface board 96 via the effect control harness 138, and can transmit the control command CMD and the strobe signal STB.

The main control relay board 135, the power supply relay board 136, and the frame LED relay board 137 are for connecting the board side member 131 to the frame side member 132, and the main control board 93 is paid out and fired via the main control relay board 135. It is connected to the control board 128, and the effect interface board 96 is connected to the power supply board 126 via the power supply relay board 136, and to the LED connection board 139 under the frame via the frame LED relay board 137, respectively. The first to third connectors CN1a to CN3a on the board side are arranged on the main control relay board 135, the power supply relay board 136, and the frame LED relay board 137 on the game board 16 side, respectively, corresponding to the rear side of the game board 16. Further, on the game board mounting portion 14 (FIG. 2) on the inner frame 6 side, the frame-side first to third connectors CN1b to CN3b are arranged so as to face the board-side first to third connectors CN1a to CN3a, respectively. When the game board 16 is mounted on the game board mounting portion 14 of the inner frame 6 from the front side, the board-side first to third connectors CN1a to CN3a are coupled to the frame-side first to third connectors CN1b to CN3b, respectively. It has become so. The frame-side first connector CN1b is provided on one end side of the payout launch control relay harness 141 connected to the payout launch control board 128, and the frame side second connector CN2b is an effect control power supply connected to the power supply board 126. The third connector CN3b on the frame side is provided on one end side of the harness 142, and is provided on one end side of the lower frame LED connection harness 143 connected to the lower frame LED connection board 139.

Further, the effect interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98, and the ROM board 99 constituting the effect control unit 95 are integrated with each other by directly connecting the connectors to each other without using a harness as described above. ing.

A liquid crystal display unit 76 is connected to the liquid crystal interface board 97 via a backlight harness 144 and a liquid crystal display unit harness 145. Further, the LED connection board 134 is connected to the effect interface board 96 via the LED connection harness 146. In addition to various LED boards on the game board 16 side, the LED connection board 134 is connected to a motor used for drive control of the movable bodies 77 to 79, a movable body driving means such as a solenoid, a position detection switch, and the like.

The frame-side member 132 is mainly composed of a power supply board 126 and a payout launch control board 128. The power supply board 126 receives AC24V and outputs various DC voltages. In addition to outputting DC5V, DC12V, and DC35V to the payout launch control board 128 and DC12V to the LED connection board 139 under the frame, the power supply relay board 136 DC5V, DC12V, and DC35V are output to the effect interface board 96 via the above. A backup board 147 is connected to the payout launch control board 128, and from the payout launch control board 128 to the main control board 93, in addition to DC5V, DC12V, DC35V received from the power supply board 126, a backup power supply and a power supply abnormality A signal or the like is output via the main control relay board 135.

Further, the payout launch control board 128 is rented to connect a launch drive means 17d constituting the launch means 17, an external terminal plate 148 for outputting various information to an external host computer, and an external game ball rental device. In addition to the device connection terminal plate 149, the frame relay board 150, the saucer relay board 151, and the like are connected.

The frame relay board 150 relays the connection between the payout motor 32a, the payout counting switch 32b, the front door / inner frame opening switch 152, etc. arranged on the inner frame 6 side and the payout launch control board 128. Further, the saucer relay board 151 relays the connection between the launch connection board 153 on the front door 7 side, the ball clogging detection board 154, the frequency display board 155, and the like, and the payout launch control board 128. The launch connection board 153 is connected to a variable resistor 35a constituting the launch handle 35, a launch stop switch 35b, a touch sensor 35c, a ball feed solenoid 53c provided in the ball feed unit 53a, and the like.

Further, in addition to the lower speaker 18 on the inner frame 6 side, the lower left LED connection board 156 on the front door 7 side is connected to the lower left LED connection board 139 of the frame. The lower left LED connection board 156 of the frame is connected to the LED board 157 that constitutes the illumination on the front door 7 side, the handle LED board 158 arranged on the firing handle 35, the effect button 41, the LED board inside the effect button 41, and the like. The button LED connection board 159, the volume light amount button board 160 to which the volume / light amount adjustment buttons 39, 40, etc. are connected, the upper speaker 25, the side unit relay board 161 connected to the side unit 30, and the like are connected.

Subsequently, the circuit configurations of the effect interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98, and the ROM board 99 constituting the effect control unit 95 will be described in detail with reference to FIGS. 10 and 11.

As shown in FIG. 10, the effect interface board 96 reproduces an audio signal based on an instruction received from a CPU circuit 171 (FIG. 11) mounted on the composite chip 104 of the liquid crystal control board 98 in addition to various input / output buffers. The audio processor 101 is provided, an audio ROM 103 that stores compressed audio data that is the original data of the audio signal to be reproduced, a digital amplifier 102 that receives an audio signal output from the audio processor 101, and the like. The voice processor 101 has a built-in WDT circuit that automatically resets the set value of the internal circuit to the default value when the internal circuit operates abnormally, and a voice control register SRG. The voice control register SRG is the composite chip 104. The audio ROM 103 is accessed based on the operation parameters received from the CPU circuit 171 to reproduce a necessary audio signal and output it to the digital amplifier 102.

The various input / output buffers mounted on the effect interface board 96 include an input buffer and a frame LED for receiving a control command CMD and a strobe signal STB from the main control board 93 and transferring them to the composite chip 104 of the liquid crystal control board 98. An input buffer for receiving a switch signal such as an effect button 41 via the relay board 137 and transferring it to the composite chip 104 of the liquid crystal control board 98, and a serial signal received from the liquid crystal control board 98 via the frame LED relay board 137. Then, it receives a switch signal of a movable body position detection switch or the like via an output buffer for transferring to a driver IC such as an LED board and an LED connection board 134 and transfers it to a composite chip 104 of the liquid crystal control board 98. There are an input buffer, an output buffer for transferring a serial signal received from the liquid crystal control board 98 to a driver IC such as an LED board via the LED connection board 134, and the like.

Further, the liquid crystal control board 98 has a composite chip (chip) 104 having a built-in CPU circuit 171 and a control ROM (ROM connected to the chip) 105 for storing a control program of the CPU circuit 171, and a large amount of data at high speed. An accessible DRAM (Dynamic Random Access Memory) 106 is mounted, and a ROM board 99 connected to the liquid crystal control board 98 is mounted with a CGROM 107 that stores a large amount of CG data required for effect control. ing.

The control ROM 105 is positioned in the address space CS0 selected by the chip select signal CS0. Further, the DRAM 106 is positioned in the address space CS5 selected by the chip select signal CS5.

FIG. 11 is a circuit block diagram showing the composite chip 104 mounted on the liquid crystal control board 98, including related circuit elements. As shown in the figure, the composite chip 104 has a CPU circuit 171 that issues a display list DL at predetermined time intervals, and a VDP circuit 172 that generates image data based on the issued display list DL and drives the liquid crystal display unit 76. And are built-in. The CPU circuit 171 and the VDP circuit 172 are connected to each other via a CPU IF circuit 173 that relays transmission / reception data to each other.

The CPU circuit 171 frequency-multiplies (for example, 8-multiplies) the oscillation output (for example, 100/3 MHz) from the oscillator OSC1 received at the HCLKI terminal of the composite chip 104 to obtain a CPU operating clock of about 266.7 MHz. Here, the oscillator OSC1 is configured to output spectrum diffused waves to take EMI (Electromagnetic Interference) measures to prevent radio interference / electromagnetic interference.

On the other hand, in the VDP circuit 172, the oscillation output (for example, 40 MHz) from the oscillator OSC2 received at the PLLREF terminal of the composite chip 104 is frequency-multiplied as necessary, and then the system clock of the VDP circuit 172 and the display for the display device are displayed. It is used as a clock (dot clock, etc.) and as a DDR clock of an external DRAM 106. That is, the output of the oscillator OSC2 functions as a reference clock for the entire VDP circuit 172.

Therefore, in consideration of the importance of this reference clock, the oscillator OSC2 is operated at the same power supply voltage of 3.3V as the VDP circuit 172, and the output enable terminal OE is set to H level (= 3.3V). , The reference clock is oscillated and output, and when the power supply voltage 3.3V drops below a predetermined level, an unmaskable interrupt (NMI) is generated.

Further, the composite chip 104 is provided with an HBTSL terminal, and a ROM for storing a boot program (initial setting program) executed after the power is turned on (CPU reset) is specified based on the logic level of the HBTSL terminal. .. As shown in the figure, in this embodiment, HBTSL = L is set, and the zero address of the address space CS0 of the CPU circuit 171 is assigned to the control ROM 105.

A control ROM 105 that non-volatilely stores a control program and necessary control data and a work memory (RAM) 174 having a storage capacity of about 2 Mbytes are connected to the CPUIF circuit 173, and the CPU circuit 171 and VDP, respectively. It is accessible from circuit 172.

The control ROM 105 is positioned in the address space CS0 selected by the chip select signal CS0, and the work memory 174 is positioned in the address space CS6 selected by the chip select signal CS6. In the work memory 174, a DL buffer BUF for temporarily storing a display list DL in which a series of instruction commands for specifying one frame of the liquid crystal display unit 76 is described is secured.

The CPU circuit 171 is a circuit having the same performance as a general-purpose one-chip microcomputer, and has an effect control CPU 181 that comprehensively controls image effects based on a control program of the control ROM 105, and a storage capacity of about 16 kbytes. A serial input having a built-in RAM 182 used as a work area of the CPU, a DMAC (Direct Memory Access Controller) 183 for realizing data transfer without going through the effect control CPU 181 and a plurality of input ports Si and output ports So. An output port (SIO) 184, a parallel input / output port (PIO) 185 having a plurality of input ports Pi and output ports Po, and a control register (REG) 186 in which set values are set to control the operation of each part, etc. It has.

The parallel input / output port 185 is connected to an external device (effect interface board 96) via an input / output circuit 187 or the like, and the effect control CPU 181 passes through the input / output circuit 187 to control switch signals such as the effect button 41. It is designed to receive command CMD, interrupt signal STB, and the like.

Further, in the present embodiment, the SMC unit (Serial Management Controller) 188 of the VDP circuit 172 is used for the light emission effect and the movable body effect. The SMC unit 188 has a built-in LED controller and a motor controller, and can output a serial signal by a clock synchronization method. Further, the motor controller can output a latch pulse at an arbitrary timing based on a set value in a predetermined control register, and can input a serial signal by a clock synchronization method. Therefore, in the present embodiment, the motor drive signal and the LED drive signal are output from the SMC unit 187 in synchronization with the clock signal, while the latch pulse is output as the operation control signal ENABLE at an appropriate timing. Further, the origin sensor signals SN0 to SNn from the motor groups M1 to Mn constituting the movable body driving means are serially input by the clock synchronization method.

Subsequently, the details of the wiring pattern and the like of the liquid crystal control board 98 constituting the effect control unit 95 will be described. The liquid crystal control board 98 has a plurality of wiring layers on the board body 190 (see FIG. 8), specifically, a first wiring layer L1 on the front surface (first surface) 98a side and a first wiring layer L1 on the back surface (second surface) 98b side. A total of 6 first to sixth wiring layers L1 to L6 (FIGS. 12 to 17) including 6 wiring layers L6 and 2nd to 5th wiring layers L2 to L5 arranged between them are provided. There is. The second wiring layer L2 (FIG. 13) is a solid wiring layer connected to the ground, and the fifth wiring layer L5 (FIG. 16) is a solid wiring layer connected to the power supply. Further, the substrate main body 190 of the liquid crystal control substrate 98 is provided with a large number of vias (interlayer conductive portions) in the plate thickness direction, and the plurality of wiring layers L1 to L6 are provided with each other via the vias (interlayer conductive portions). It is conducting. The via used in the present embodiment is a through-hole type via in which the through hole is plated, and penetrates from the front surface (first surface) 98a of the substrate main body 190 to the back surface (second surface) 98b.

In the following description, regarding the in-plane directions and orientations of the wiring layers L1 to L6, as shown in the coordinate system in FIGS. 12 to 17, the horizontal direction in the same figure is the X direction, and the vertical direction is the Y direction. The direction is right / left as + X / -X direction (side), and upward / downward as + Y / -Y direction (side). Further, the diagonal direction is also expressed as diagonal + XY direction and diagonal-XY direction. As is clear from FIGS. 7 and 8, when the liquid crystal control board 98 is mounted on the gaming machine main body 1, the + X direction of the liquid crystal control board 98 faces upward, and the + Y direction also faces right toward the gaming machine main body 1. (To the left when viewed from the back).

As shown in FIG. 12, in the first wiring layer L1 on the surface 98a side, a composite chip arrangement area (first arrangement area) 191 in which the composite chip (first electronic component) 104 is arranged and a control ROM (second). A control ROM arrangement area (second arrangement area) 192 in which the electronic component (electronic component, specific electronic component) 105 is arranged is provided. The composite chip arrangement region 191 is a substantially square shape corresponding to the shape of the composite chip 104, and is arranged near the central portion on the surface 98a of the liquid crystal control substrate 98. In the composite chip arrangement area 191, dot-shaped terminal connection portions corresponding to the terminals of the composite chip 104 are arranged in a matrix at substantially equal intervals. The composite chip 104 is provided with a total of 1020 terminals arranged in 32 rows and 32 columns (however, the four corners are missing) on the bottom surface side, and each of these terminals is connected to the corresponding terminal connection portion. It is mounted in the composite chip arrangement area 191 in the state.

The control ROM arrangement area 192 is a substantially rectangular shape that is long in the Y direction corresponding to the shape of the ROM socket 193 (see FIG. 8) in which the control ROM 105 is mounted, and the length of the long side thereof is the length of one side of the composite chip arrangement area 191. It is about the same as. The control ROM arrangement area 192 is arranged in the vicinity of the + X side with respect to the composite chip arrangement area 191 and is the long side of the −X side and the + X side of the control ROM arrangement area 192. , 192b, the first edge portion 192a faces the first edge portion 191a on the + X side in the composite chip arrangement region 191 at a predetermined distance in a state of being displaced in the −Y direction.

In the control ROM arrangement area 192, a plurality of terminal connection portions (ROM terminal connection portions) are arranged along both long sides, that is, along the first and second edge portions 192a and 192b, respectively (35 in this case). ing. A ROM socket 193 that detachably supports the control ROM 105 is fixed in the control ROM arrangement area 192, and the control ROM 105 is detachably attached to the ROM socket 193 (FIG. 8). A plurality of terminals (35 each in this case) are arranged in the control ROM 105 along both ends thereof, and each terminal is connected to each terminal connection portion of the control ROM arrangement area 192 via the ROM socket 193. It is connected.

As shown in FIG. 8, the ROM socket 193 removably holds both the substantially rectangular bottom wall 193a corresponding to the control ROM arrangement area 192 and the control ROM 105 mounted on the bottom wall 193a. A pair of ROM holding portions 193b are provided, and the bottom wall 193a is fixed to the surface 98a of the liquid crystal control substrate 98 in a state of covering substantially the entire control ROM arrangement area 192. Therefore, the wiring pattern (via, etc.) in the control ROM arrangement area 192 in the first wiring layer L1 is shielded by the bottom wall (shielding wall) 193a of the ROM socket 193 even when the control ROM 105 is removed from the ROM socket 193. It cannot be seen from the outside. As a result, it is possible to improve the preventability against goto acts such as illegally modifying the wiring pattern connecting the composite chip 104 and the control ROM 105. Further, by drawing a wiring pattern in the control ROM arrangement area 192, it is possible to secure a wiring space in other areas.

Further, as shown in FIG. 17, in the sixth wiring layer L6 on the back surface 98b side, the first connector arrangement area 194 in which the liquid crystal control first connector CN31 is arranged and the second connector CN32 in which the liquid crystal control second connector CN32 is arranged are arranged. A connector arrangement area 195 is provided. The first connector arrangement area 194 is a substantially rectangular shape long in the X direction, and is arranged near the + Y side edge of the back surface 98b of the liquid crystal control substrate 98. In the first connector arrangement area 194, a plurality of terminal connection portions (70 each in this case) corresponding to each terminal of the liquid crystal control first connector CN31 are arranged along a pair of long sides. The second connector arrangement area 195 is a substantially rectangular shape long in the X direction, and is arranged near the edge on the −Y side on the back surface 98b of the liquid crystal control substrate 98. Within the second connector arrangement area 195, a plurality of terminal connection portions (here, 50 each) corresponding to each terminal of the liquid crystal control second connector CN32 are arranged along a pair of long sides.

Of all the terminals of the composite chip 104, the terminals connected to the control ROM 105 are centrally arranged in the vicinity of the first edge portion 191a on the control ROM 105 side in the composite chip arrangement area 191. FIG. 18 shows the types (terminal information) of some of the terminals in the vicinity of the first edge portion 191a among all the terminals of the composite chip 104. The arrangement of the terminals in FIG. 18 matches the arrangement of the terminal connection portions in the composite chip arrangement area 191 in FIG.

In FIG. 18, HAD0 to HAD25 are address output terminals for outputting address information, HDT0 to HDT15 are data input / output terminals for inputting / outputting data information, and HCS0 is a chip select output terminal for outputting chip select signals. , HRD is a lead strobe output terminal for outputting a read strobe signal, and HREST is a system reset terminal for inputting a system reset signal. In the following description, it is assumed that the terminals of the corresponding composite chip 104, such as HAD0 to HAD25 and HDT0 to HDT15, are used as they are for the terminal connection portion in the composite chip arrangement area 191. For example, the terminal connection portion HRD indicates a terminal connection portion corresponding to the lead strobe output terminal HRD.

Further, FIG. 19 shows the types (terminal information) of each terminal of the control ROM 105. Of the terminals shown in FIG. 19, A0 to A24 are address input terminals for inputting address information, Q0 to Q15 are data input / output terminals for inputting and outputting data information, and address output terminals of the composite chip 104, respectively. , Connected to the data input / output terminal. CE # is a chip select input terminal for inputting a chip select signal, and is connected to a chip select output terminal of the composite chip 104. WE # is a writable input terminal, and by connecting to a power supply and always setting the H level, it is possible to switch the mode according to the value (H / L) of the OE # terminal. The OE # is an output-capable input terminal and is connected to the lead strobe output terminal of the composite chip 104.

RESET # is a reset terminal, and is connected to a power supply voltage monitoring integrated circuit (reset IC) together with the system reset input terminal HRESET of the composite chip 104. WP # / ACC is a write-protected / program input terminal, and by connecting to ground (L level) or power supply (H level), it is possible to switch between write prohibition / permission and program execution prohibition / permission. There is. In this embodiment, the WP # / ACC terminal is connected to the power supply and set to H level. BYTE # is an 8-bit mode selection terminal, and by connecting to the ground (L level) or power supply (H level), it is possible to select either the 8-bit communication mode or the 16-bit communication mode.

In the following description, the terminals A0 to A24, Q0 to Q15, CE #, and the like of the corresponding control ROM 105 terminals are used as they are for the terminal connection portion corresponding to the control ROM arrangement area 192. For example, the terminal connection portion RESET # indicates a terminal connection portion corresponding to the reset terminal RESET #.

Hereinafter, among a large number of wiring lines provided on the liquid crystal control board 98, a plurality of types of wiring lines P1 to P47 including a wiring line connecting the composite chip 104 and the control ROM 105 will be focused on, and details thereof will be drawn. Will be explained with reference to. 20 to 25 show only the portions constituting the wiring paths P1 to P47 extracted from the wiring patterns of the first to sixth wiring layers L1 to L6 shown in FIGS. 12 to 17. 26 to 34 are partially enlarged views thereof. Further, FIGS. 35 to 40 schematically show the wiring paths of the wiring paths P1 to P47. In addition, in FIGS. 35 to 40, the vias displayed in gray (for example, the via v86 in the wiring path P1 of FIG. 35) indicate the vias (specific interlayer conduction portion) arranged in the control ROM arrangement area 192, and are thick lines. The wiring path indicated by (for example, the wiring path cp13 in the wiring path P2 in FIG. 35) indicates a wiring path connected to the terminal connection portion on the control ROM 105 side from the inside of the control ROM arrangement area 192.

First, the wiring lines P1 to P26 connected to the address output terminals HAD0 to HAD25 of the composite chip 104 will be described. In the present embodiment, of the address output terminals HAD0 to HAD25, HAD1 to HAD25 are connected to the address input terminals A0 to A24 on the control ROM 105 side, respectively, and are also connected to the liquid crystal control first connector CN31. On the other hand, the address output terminal HAD0 is connected to the liquid crystal control first connector CN31, but is not connected to the terminal on the control ROM 105 side.

Comparing the arrangement of the address output terminals HAD1 to HAD25 of the composite chip 104 (FIG. 18) with the arrangement of the corresponding address input terminals A0 to A24 of the control ROM 105 (FIG. 19), the two are clearly different. There is. That is, the address output terminals HAD1 to HAD25 of the composite chip 104 are arranged in 6 rows as shown in FIG. 18, and the number of columns is different for each row, but the arrangement order is constant, whereas the control As shown in FIG. 19, the address input terminals A0 to A24 of the ROM 105 are arranged in two columns, and there is no fixed regularity in the order of arrangement in each column. Moreover, since the arrangement positions of the composite chip 104 and the control ROM 105 and the large number of wiring patterns are related, the wiring patterns are very complicated to be routed. Therefore, it is very important to optimize the wiring pattern routing that connects the composite chip 104 and the control ROM 105, which makes it possible to shorten the wire length of the wiring pattern, reduce noise, and slim down the entire board. It leads to the plan. Further, the same can be said not only in the relationship between the composite chip 104 and the control ROM 105, but also in the relationship between the composite chip 104 and electronic components such as various connectors. In particular, with respect to wiring patterns connected to a plurality of electronic components such as composite chips 104 such as HAD1 to HAD25 and HDT1 to HDT25, a control ROM 105, and various connectors, the above-mentioned problems are large, and the effect of optimization is also large. It becomes a thing.

Of the wiring paths P1 to P26, in the wiring path P1 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD0 provided in the composite chip arrangement area 191 of the first wiring layer L1 is provided by the wiring path cp0. It is connected to a via v0 arranged in the vicinity in the oblique-XY direction. The via v0 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD0) arranged around the via v0. As shown in FIG. 28, the via v0 is connected to the via v41 by a wiring path cp1 provided in the third wiring layer L3. The via v41 is arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. Then, as shown in FIG. 31, the via v41 is connected to the via v86 arranged in the control ROM arrangement area 192 by the wiring path cp2 provided in the fourth wiring layer L4. In this way, the wiring path drawn out from the terminal connection portion HAD0 in the first wiring layer L1 is connected to the via v86 in the control ROM arrangement area 192 via the two wiring layers L3 and L4.

The wiring line that reaches the via v86 from the terminal connection portion HAD0 is branched into two by this via v86. As shown in FIGS. 28 and 29, the first branch path is a first connector arrangement area 194 from the via v86 via the via v205 constituting the test point TP28 by the wiring path cp3 provided in the third wiring layer L3. It is connected to the via v146 inside, and further, as shown in FIG. 33, is connected to the terminal connection portion had0 from the inside of the first connector arrangement area 194 by the wiring path cp4 provided in the sixth wiring layer L6. .. Further, as shown in FIG. 32, the second branch path is connected from the via v86 to the terminating resistor RA16 by the wiring path cp5 provided in the sixth wiring layer L6. The other end of the terminating resistor RA16 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (omitted in the wiring diagram).

In the wiring path P2 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD1 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located near the diagonally −XY direction by the wiring path cp11. It is connected to the via v5 arranged in. The via v5 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD1) arranged around the via v5. As shown in FIG. 31, the via v5 is connected to the via v85 arranged in the control ROM arrangement area 192 by the wiring path cp12 provided in the fourth wiring layer L4. In this way, the wiring path drawn out from the terminal connection portion HAD1 does not pass through the third wiring layer L3, but is arranged in the control ROM via the fourth wiring layer L4, unlike the wiring path drawn out from the terminal connection portion HAD0. It is connected to via v85 in region 192.

The wiring line that reaches the via v85 from the terminal connection portion HAD1 is branched into four by the via v85. As shown in FIG. 27, the first branch path is connected from the via v85 to the terminal connection portion A0 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp13 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA16 from the via v85 by the wiring path cp14 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v85 to the via v145 in the first connector arrangement area 194 by the wiring path cp15 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp16 provided in the sixth wiring layer L6 is connected to the terminal connection portion had1 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v85 to the via v182 by the wiring path cp17 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v182. 6 The wiring path cp18 provided in the wiring layer L6 is connected to the decoder IC12 constituting the decoding circuit.

Although omitted in the wiring diagram of FIG. 34 and the like, the decoding circuit including the decoders IC12 to IC14 is configured as shown in FIG. 41. As shown in FIG. 41, the decoders IC13 and IC14 are connected to the liquid crystal display unit 76 and the like via the liquid crystal IF third connector CN23 and the like, and are connected to the data input / output terminals HDT0 to HDT15 of the composite chip 104 when the power is turned on. Data information is entered. Since the decoders IC13 and IC14 output data information to the liquid crystal display unit 76 or the like based on the clock synchronized with the CPU input from the decoder IC12, the CPU does not need to transmit fixed data information every time. As a result, it is not necessary to output the same data information from the CPU at predetermined time intervals, and the CPU only needs to transmit new data information only when the content of the data information is changed, which simplifies the control program. It becomes possible to change.

In the wiring path P3 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD2 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located in the vicinity of the diagonal + XY direction by the wiring path cp21. It is connected to the placed via v4. The via v4 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD2) arranged around the via v4. As shown in FIG. 31, the via v4 is connected to the via v84 arranged in the control ROM arrangement area 192 by the wiring path cp22 provided in the fourth wiring layer L4.

The wiring path that reaches the via v84 from the terminal connection portion HAD2 is branched into four by the via v84. As shown in FIG. 27, the first branch path is connected from the via v84 to the terminal connection portion A1 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp23 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA16 from the via v84 by the wiring path cp24 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v84 to the via v144 in the first connector arrangement area 194 by the wiring path cp25 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp26 provided in the sixth wiring layer L6 is connected to the terminal connection portion had2 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v84 to the via v184 by the wiring path cp27 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v184. 6 The wiring path cp28 provided in the wiring layer L6 is connected to the decoder IC 12 constituting the decoding circuit.

In the wiring path P4 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD3 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located in the vicinity of the diagonal + XY direction by the wiring path cp31. It is connected to the arranged via v13. The via v13 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD3) arranged around the via v13. As shown in FIG. 31, the via v13 is connected to the via v83 arranged in the control ROM arrangement area 192 by the wiring path cp32 provided in the fourth wiring layer L4.

The wiring path that reaches the via v83 from the terminal connection portion HAD3 is branched into four by the via v83. As shown in FIG. 27, the first branch path is connected from the via v83 to the terminal connection portion A2 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp33 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA16 from the via v83 by the wiring path cp34 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v83 to the via v143 in the first connector arrangement area 194 by the wiring path cp35 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp36 provided in the sixth wiring layer L6 is connected to the terminal connection portion had3 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v83 to the via v181 by the wiring path cp37 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v181. 6 The wiring path cp38 provided in the wiring layer L6 is connected to the decoder IC 12 constituting the decoding circuit.

In the wiring path P5 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD4 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located in the vicinity of the diagonal + XY direction by the wiring path cp41. It is connected to the placed via v20. The via v20 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD4) arranged around the via v20. As shown in FIG. 31, the via v20 is connected to the via v82 arranged in the control ROM arrangement area 192 by the wiring path cp42 provided in the fourth wiring layer L4.

The wiring path that reaches the via v82 from the terminal connection portion HAD4 is branched into three by the via v82. As shown in FIG. 27, the first branch path is connected from the via v82 to the terminal connection portion A3 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp43 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA15 from the via v82 by the wiring path cp44 provided in the sixth wiring layer L6. The other end of the terminating resistor RA15 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v82 to the via v142 in the first connector arrangement area 194 by the wiring path cp45 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp46 provided in the sixth wiring layer L6 is connected to the terminal connection portion had4 from the inside of the first connector arrangement area 194.

In the wiring path P6 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD5 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp51. Specifically, it is connected to the via v34 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HAD5 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 31, the via v34 is connected to the via v81 arranged in the control ROM arrangement area 192 by the wiring path cp52 provided in the fourth wiring layer L4.

The wiring path that reaches the via v81 from the terminal connection portion HAD5 is branched into three by the via v81. As shown in FIG. 27, the first branch path is connected from the via v81 to the terminal connection portion A4 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp53 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA15 from the via v81 by the wiring path cp54 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v81 to the via v141 in the first connector arrangement area 194 by the wiring path cp55 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp56 provided in the sixth wiring layer L6 is connected to the terminal connection portion had5 from the inside of the first connector arrangement area 194.

In the wiring path P7 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD6 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp61. Specifically, it is connected to a via v39 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HAD6 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. 31, the via v39 is connected to the via v80 arranged in the control ROM arrangement area 192 by the wiring path cp62 provided in the fourth wiring layer L4.

The wiring path that reaches the via v80 from the terminal connection portion HAD6 is branched into three by the via v80. As shown in FIG. 27, the first branch path is connected from the via v80 to the terminal connection portion A5 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp63 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected from the via v80 to the terminating resistor RA15 by the wiring path cp64 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v80 to the via v140 in the first connector arrangement area 194 by the wiring path cp65 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp66 provided in the sixth wiring layer L6 is connected to the terminal connection portion had6 from the inside of the first connector arrangement area 194.

In the wiring path P8 (FIG. 35), as shown in FIG. 26, the terminal connection portion HAD7 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located in the vicinity of the diagonal + XY direction by the wiring path cp71. It is connected to the placed via v3. The via v3 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD7) arranged around the via v3. As shown in FIG. 31, the via v3 is connected to the via v79 arranged in the control ROM arrangement area 192 by the wiring path cp72 provided in the fourth wiring layer L4.

The wiring path that reaches the via v79 from the terminal connection portion HAD7 is branched into three by the via v79. As shown in FIG. 27, the first branch path is connected from the via v79 to the terminal connection portion A6 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp73 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected from the via v79 to the terminating resistor RA15 by the wiring path cp74 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v79 to the via v139 in the first connector arrangement area 194 by the wiring path cp75 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp76 provided in the sixth wiring layer L6 is connected to the terminal connection portion had7 from the inside of the first connector arrangement area 194.

In the wiring path P9 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD8 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located in the vicinity of the diagonal + XY direction by the wiring path cp81. It is connected to the placed via v12. The via v12 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD8) arranged around the via v12. As shown in FIG. 31, the via v12 is connected to the via v78 arranged in the control ROM arrangement area 192 by the wiring path cp82 provided in the fourth wiring layer L4.

The wiring path that reaches the via v78 from the terminal connection portion HAD8 is branched into three by the via v78. As shown in FIG. 27, the first branch path is connected from the via v78 to the terminal connection portion A7 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp83 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA13 from the via v78 by the wiring path cp84 provided in the sixth wiring layer L6. The other end of the terminating resistor RA13 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v78 to the via v138 in the first connector arrangement area 194 by the wiring path cp85 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp86 provided in the sixth wiring layer L6 is connected to the terminal connection portion had8 from the inside of the first connector arrangement area 194.

In the wiring path P10 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD9 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp91. Specifically, it is connected to the via v33 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HAD9 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 31, the via v33 is connected to the via v77 arranged in the control ROM arrangement area 192 by the wiring path cp92 provided in the fourth wiring layer L4.

The wiring path that reaches the via v77 from the terminal connection portion HAD9 is branched into three by the via v77. As shown in FIG. 27, the first branch path is connected from the via v77 to the terminal connection portion A8 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp93 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected from the via v77 to the terminating resistor RA13 by the wiring path cp94 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v77 to the via v137 in the first connector arrangement area 194 by the wiring path cp95 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp96 provided in the sixth wiring layer L6 is connected to the terminal connection portion had9 from the inside of the first connector arrangement area 194.

In the wiring path P11 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD10 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp101. Specifically, it is connected to a via v38 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HAD10 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. 31, the via v38 is connected to the via v76 arranged in the control ROM arrangement area 192 by the wiring path cp102 provided in the fourth wiring layer L4.

The wiring path that reaches the via v76 from the terminal connection portion HAD10 is branched into three by the via v76. As shown in FIG. 27, the first branch path is connected from the via v76 to the terminal connection portion A9 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp103 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA13 from the via v76 by the wiring path cp104 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v76 to the via v136 in the first connector arrangement area 194 by the wiring path cp105 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp106 provided in the sixth wiring layer L6 is connected to the terminal connection portion had10 from the inside of the first connector arrangement area 194.

In the wiring path P12 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD11 provided in the composite chip arrangement area 191 of the first wiring layer L1 is arranged in the vicinity of the diagonally −X + Y direction by the wiring path cp111. It is connected to the via v2. The via v2 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD11) arranged around the via v2. As shown in FIG. 31, the via v2 is connected to the via v75 arranged in the control ROM arrangement area 192 by the wiring path cp112 provided in the fourth wiring layer L4.

The wiring path that reaches the via v75 from the terminal connection portion HAD11 is branched into three by the via v75. As shown in FIG. 27, the first branch path is connected from the via v75 to the terminal connection portion A10 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp113 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA13 from the via v75 by the wiring path cp114 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v75 to the via v135 in the first connector arrangement area 194 by the wiring path cp115 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp116 provided in the sixth wiring layer L6 is connected to the terminal connection portion had11 from the inside of the first connector arrangement area 194.

In the wiring path P13 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD12 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located in the vicinity of the diagonal + XY direction by the wiring path cp121. It is connected to the placed via v19. The via v19 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD12) arranged around the via v19. As shown in FIG. 31, the via v19 is connected to the via v74 arranged in the control ROM arrangement area 192 by the wiring path cp122 provided in the fourth wiring layer L4.

The wiring path that reaches the via v74 from the terminal connection portion HAD12 is branched into three by the via v74. As shown in FIG. 27, the first branch path is connected from the via v74 to the terminal connection portion A11 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp123 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA11 from the via v74 by the wiring path cp124 provided in the sixth wiring layer L6. The other end of the terminating resistor RA11 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v74 to the via v134 in the first connector arrangement area 194 by the wiring path cp125 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp126 provided in the sixth wiring layer L6 is connected to the terminal connection portion had12 from the inside of the first connector arrangement area 194.

In the wiring path P14 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD13 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp131. Specifically, it is connected to the via v49 arranged on the + Y side of the control ROM arrangement area 192. The terminal connection portion HAD 13 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 31, the via v49 is connected to the via v73 arranged in the control ROM arrangement area 192 by the wiring path cp132 provided in the fourth wiring layer L4.

The wiring path that reaches the via v73 from the terminal connection portion HAD13 is branched into two by the via v73. As shown in FIG. 32, the first branch path is connected to the terminating resistor RA11 from the via v73 by the wiring path cp133 provided in the sixth wiring layer L6.

Further, as shown in FIG. 28, the second branch path is connected from the via v73 to the via v107 arranged in the control ROM arrangement area 192 by the wiring path cp134 provided in the third wiring layer L3. , Here it is further branched into two. As shown in FIG. 27, the first branch path of the second a is a control ROM arrangement area from the via v107 to the terminal connection portion A12 of the control ROM 105 by the wiring path cp135 provided in the first wiring layer L1. It is connected from the inside of 192. Further, as shown in FIGS. 28 and 29, the second branch path of the second b is from the via v107 to the via v133 in the first connector arrangement area 194 by the wiring path cp136 provided in the third wiring layer L3. It is connected, and as shown in FIG. 33, it is connected to the terminal connection portion had13 from the inside of the first connector arrangement area 194 by the wiring path cp137 provided in the sixth wiring layer L6.

In the wiring path P15 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD14 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp141. Specifically, it is connected to the via v50 arranged on the + Y side of the control ROM arrangement area 192. The terminal connection portion HAD14 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. 31, the via v50 is connected to the via v72 arranged in the control ROM arrangement area 192 by the wiring path cp142 provided in the fourth wiring layer L4.

The wiring path that reaches the via v72 from the terminal connection portion HAD14 is branched into two by the via v72. As shown in FIG. 32, the first branch path is connected from the via v72 to the terminating resistor RA11 by the wiring path cp143 provided in the sixth wiring layer L6.

Further, as shown in FIG. 28, the second branch path is connected from the via v72 to the via v106 arranged in the control ROM arrangement area 192 by the wiring path cp144 provided in the third wiring layer L3. , Here it is further branched into two. As shown in FIG. 27, the first branch path of the second a is a control ROM arrangement area from the via v106 to the terminal connection portion A13 of the control ROM 105 by the wiring path cp145 provided in the first wiring layer L1. It is connected from the inside of 192. Further, as shown in FIGS. 28 and 29, the second branch path of the second b is from the via v106 to the via v132 in the first connector arrangement area 194 by the wiring path cp146 provided in the third wiring layer L3. Further, as shown in FIG. 33, the wiring path cp147 provided in the sixth wiring layer L6 is connected to the terminal connection portion had 14 from the inside of the first connector arrangement area 194.

In the wiring path P16 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD15 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located near the diagonal + XY direction by the wiring path cp151. It is connected to the placed via v11. The via v11 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD15) arranged around the via v11. As shown in FIG. 31, the via v11 is connected to the via v71 arranged in the control ROM arrangement area 192 by the wiring path cp152 provided in the fourth wiring layer L4.

The wiring path that reaches the via v71 from the terminal connection portion HAD15 is branched into two by the via v71. As shown in FIG. 32, the first branch path is connected from the via v71 to the terminating resistor RA11 by the wiring path cp153 provided in the sixth wiring layer L6.

Further, as shown in FIG. 28, the second branch path is connected from the via v71 to the via v105 arranged in the control ROM arrangement area 192 by the wiring path cp154 provided in the third wiring layer L3. , Here it is further branched into two. As shown in FIG. 27, the first branch path of the second a is a control ROM arrangement area from the via v105 to the terminal connection portion A14 of the control ROM 105 by the wiring path cp155 provided in the first wiring layer L1. It is connected from the inside of 192. Further, as shown in FIGS. 28 and 29, the second branch path of the second b is from the via v105 to the via v131 in the first connector arrangement area 194 by the wiring path cp156 provided in the third wiring layer L3. Further, as shown in FIG. 33, the wiring path cp157 provided in the sixth wiring layer L6 is connected to the terminal connection portion had15 from the inside of the first connector arrangement area 194.

In the wiring path P17 (FIG. 36), as shown in FIG. 26, the terminal connection portion HAD16 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located near the diagonal + XY direction by the wiring path cp161. It is connected to the placed via v18. The via v18 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD16) arranged around the via v18. As shown in FIG. 31, the via v18 is connected to the via v70 arranged in the control ROM arrangement area 192 by the wiring path cp162 provided in the fourth wiring layer L4.

The wiring path that reaches the via v70 from the terminal connection portion HAD16 is branched into two by the via v70. As shown in FIG. 32, the first branch path is connected to the terminating resistor RA10 from the via v70 by the wiring path cp163 provided in the sixth wiring layer L6. The other end of the terminating resistor RA10 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIG. 28, the second branch path is connected from the via v70 to the via v104 arranged in the control ROM arrangement area 192 by the wiring path cp164 provided in the third wiring layer L3. , Here it is further branched into two. As shown in FIG. 27, the first branch path of the second a is a control ROM arrangement area from the via v104 to the terminal connection portion A15 of the control ROM 105 by the wiring path cp165 provided in the first wiring layer L1. It is connected from the outside of 192. Further, as shown in FIGS. 28 and 29, the second branch path of the second b is from the via v104 to the via v130 in the first connector arrangement area 194 by the wiring path cp166 provided in the third wiring layer L3. It is connected, and as shown in FIG. 33, it is connected to the terminal connection portion had16 from the inside of the first connector arrangement area 194 by the wiring path cp167 provided in the sixth wiring layer L6.

In the wiring path P18 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD17 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp171. Specifically, it is connected to the via v51 arranged on the + Y side of the control ROM arrangement area 192. The terminal connection portion HAD17 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 31, the via v51 is connected to the via v69 arranged in the control ROM arrangement area 192 by the wiring path cp172 provided in the fourth wiring layer L4.

The wiring path that reaches the via v69 from the terminal connection portion HAD17 is branched into two by this via v69. As shown in FIG. 32, the first branch path is connected to the terminating resistor RA10 from the via v69 by the wiring path cp173 provided in the sixth wiring layer L6.

Further, as shown in FIG. 28, the second branch path is connected from the via v69 to the via v103 arranged in the control ROM arrangement area 192 by the wiring path cp174 provided in the third wiring layer L3. , Here it is further branched into two. As shown in FIG. 27, the first branch path of the second a is a control ROM arrangement area from the via v103 to the terminal connection portion A16 of the control ROM 105 by the wiring path cp175 provided in the first wiring layer L1. It is connected from the outside of 192. Further, as shown in FIGS. 28 and 29, the second branch path of the second b is from the via v103 to the via v129 in the first connector arrangement area 194 by the wiring path cp176 provided in the third wiring layer L3. Further, as shown in FIG. 33, the wiring path cp177 provided in the sixth wiring layer L6 is connected to the terminal connection portion had17 from the inside of the first connector arrangement area 194.

In the wiring line P19 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD18 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp181. Specifically, it is connected to the via v52 arranged on the + Y side of the control ROM arrangement area 192. The terminal connection portion HAD18 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. 31, the via v52 is connected to the via v68 arranged in the control ROM arrangement area 192 by the wiring path cp182 provided in the fourth wiring layer L4.

The wiring path that reaches the via v68 from the terminal connection portion HAD18 is branched into three by the via v68. As shown in FIG. 27, the first branch path is connected from the via v68 to the terminal connection portion A17 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp183 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA10 from the via v68 by the wiring path cp184 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v68 to the via v128 in the first connector arrangement area 194 by the wiring path cp185 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp186 provided in the sixth wiring layer L6 is connected to the terminal connection portion had18 from the inside of the first connector arrangement area 194.

In the wiring path P20 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD19 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located near the diagonal + XY direction by the wiring path cp191. It is connected to the placed via v1. The via v1 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD19) arranged around the via v1. As shown in FIG. 31, the via v1 is connected to the via v67 arranged in the control ROM arrangement area 192 by the wiring path cp192 provided in the fourth wiring layer L4.

The wiring path that reaches the via v67 from the terminal connection portion HAD19 is branched into three by the via v67. As shown in FIG. 27, the first branch path is connected from the via v67 to the terminal connection portion A18 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp193 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA10 from the via v67 by the wiring path cp194 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v67 to the via v127 in the first connector arrangement area 194 by the wiring path cp195 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp196 provided in the sixth wiring layer L6 is connected to the terminal connection portion had19 from the inside of the first connector arrangement area 194.

In the wiring path P21 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD20 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located in the vicinity of the diagonal + XY direction by the wiring path cp201. It is connected to the placed via v10. The via v10 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD20) arranged around the via v10. As shown in FIG. 31, the via v10 is connected to the via v66 arranged in the control ROM arrangement area 192 by the wiring path cp202 provided in the fourth wiring layer L4.

The wiring path that reaches the via v66 from the terminal connection portion HAD20 is branched into three by the via v66. As shown in FIG. 27, the first branch path is connected from the via v66 to the terminal connection portion A19 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp203 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA9 from the via v66 by the wiring path cp204 provided in the sixth wiring layer L6. The other end of the terminating resistor RA9 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v66 to the via v126 in the first connector arrangement area 194 by the wiring path cp205 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp206 provided in the sixth wiring layer L6 is connected to the terminal connection portion had20 from the inside of the first connector arrangement area 194.

In the wiring path P22 (FIG. 37), as shown in FIGS. 26 and 27, the terminal connection portion HAD21 provided in the composite chip arrangement area 191 of the first wiring layer L1 is connected to the composite chip arrangement area 191 by the wiring path cp211. It is connected to the via v54 arranged on the + Y side of the control ROM arrangement area 192. The terminal connection portion HAD21 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. 31, the via v54 is connected to the via v65 arranged in the control ROM arrangement area 192 by the wiring path cp212 provided in the fourth wiring layer L4.

The wiring path that reaches the via v65 from the terminal connection portion HAD21 is branched into three by the via v65. As shown in FIG. 27, the first branch path is connected from the via v65 to the terminal connection portion A20 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp213 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA9 from the via v65 by the wiring path cp214 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v65 to the via v125 in the first connector arrangement area 194 by the wiring path cp215 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp216 provided in the sixth wiring layer L6 is connected to the terminal connection portion had21 from the inside of the first connector arrangement area 194.

In the wiring path P23 (FIG. 37), as shown in FIGS. 26 and 27, the terminal connection portion HAD22 provided in the composite chip arrangement area 191 of the first wiring layer L1 is connected to the composite chip arrangement area 191 by the wiring path cp221. It is connected to the via v53 arranged on the + Y side of the control ROM arrangement area 192. The terminal connection portion HAD 22 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 31, the via v53 is connected to the via v64 arranged in the control ROM arrangement area 192 by the wiring path cp222 provided in the fourth wiring layer L4.

The wiring path that reaches the via v64 from the terminal connection portion HAD22 is branched into three by the via v64. As shown in FIG. 27, the first branch path is connected from the via v64 to the terminal connection portion A21 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp223 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA9 from the via v64 by the wiring path cp224 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v64 to the via v124 in the first connector arrangement area 194 by the wiring path cp225 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp226 provided in the sixth wiring layer L6 is connected to the terminal connection portion had22 from the inside of the first connector arrangement area 194.

In the wiring path P24 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD23 provided in the composite chip arrangement area 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring path cp231. It is connected to the via v21. The via v21 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD23) arranged around the via v21. As shown in FIG. 31, the via v21 is located outside the composite chip arrangement area 191, specifically, the composite chip arrangement area 191 and the control ROM arrangement area 192 by the wiring path cp232 provided in the fourth wiring layer L4. It is connected to the via v36 arranged between the two, and as shown in FIGS. 26 and 27, the wiring path cp233 provided in the first wiring layer L1 connects the via v63 arranged in the control ROM arrangement area 192. It is connected.

The wiring path that reaches the via v63 from the terminal connection portion HAD23 is branched into three by the via v63. As shown in FIG. 27, the first branch path is connected from the via v63 to the terminal connection portion A22 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp234 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA9 from the via v63 by the wiring path cp235 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v63 to the via v123 in the first connector arrangement area 194 by the wiring path cp236 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp237 provided in the sixth wiring layer L6 is connected to the terminal connection portion had23 from the inside of the first connector arrangement area 194.

In the wiring path P25 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD24 provided in the composite chip arrangement area 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring path cp241. It is connected to the via v14. The via v14 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD24) arranged around the via v14. As shown in FIG. 31, the via v14 is located outside the composite chip arrangement area 191, specifically, the composite chip arrangement area 191 and the control ROM arrangement area 192 by the wiring path cp242 provided in the fourth wiring layer L4. It is connected to the via v35 arranged between the two, and as shown in FIGS. 26 and 27, the wiring path cp243 provided in the first wiring layer L1 connects the via v62 arranged in the control ROM arrangement area 192. It is connected.

The wiring path that reaches the via v62 from the terminal connection portion HAD24 is branched into four by the via v62. As shown in FIG. 27, the first branch path is connected from the via v62 to the terminal connection portion A23 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp244 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor R45 from the via v62 by the wiring path cp245 provided in the sixth wiring layer L6. The other end of the terminating resistor R45 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v62 to the via v122 in the first connector arrangement area 194 by the wiring path cp246 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp247 provided in the sixth wiring layer L6 is connected to the terminal connection portion had24 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v62 to the via v183 by the wiring path cp248 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v183. 6 The wiring path cp249 provided in the wiring layer L6 is connected to the decoder IC 12 constituting the decoding circuit.

In the wiring path P26 (FIG. 37), as shown in FIG. 26, the terminal connection portion HAD25 provided in the composite chip arrangement area 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring path cp251. It is connected to the via v6. The via v6 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HAD25) arranged around the via v6. As shown in FIG. 31, the via v6 is located outside the composite chip arrangement area 191, specifically, the composite chip arrangement area 191 and the control ROM arrangement area 192 by the wiring path cp252 provided in the fourth wiring layer L4. It is connected to the via v40 arranged between the two, and as shown in FIGS. 26 and 27, the wiring path cp253 provided in the first wiring layer L1 connects the via v61 arranged in the control ROM arrangement area 192. It is connected.

The wiring path that reaches the via v61 from the terminal connection portion HAD25 is branched into three by the via v61. As shown in FIG. 27, the first branch path is connected from the via v61 to the terminal connection portion A24 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp254 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor R44 from the via v61 by the wiring path cp255 provided in the sixth wiring layer L6. The other end of the terminating resistor R44 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v61 to the via v121 in the first connector arrangement area 194 by the wiring path cp256 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp257 provided in the sixth wiring layer L6 is connected to the terminal connection portion had25 from the inside of the first connector arrangement area 194.

Subsequently, the wiring lines P27 to P42 connected to the data input / output terminals HDT0 to HDT15 of the composite chip 104 will be described. The data input / output terminals HDT0 to HDT15 are connected to the data input / output terminals Q0 to Q15 on the control ROM 105 side, respectively, and are also connected to the liquid crystal control first connector CN31.

Comparing the arrangement of the data input / output terminals HDT0 to HDT15 of the composite chip 104 (FIG. 18) with the arrangement of the corresponding data input / output terminals Q0 to Q15 of the control ROM 105 (FIG. 19), the two are clearly different. doing. That is, the data input / output terminals HDT0 to HDT15 of the composite chip 104 are arranged in four rows as shown in FIG. 18, and the number of columns is different for each row, but the arrangement order is constant. The data input / output terminals Q0 to Q15 of the control ROM 105 are arranged in two columns as shown in FIG. 19, and there is no fixed regularity in the order of arrangement in each column. Moreover, since the arrangement positions of the composite chip 104 and the control ROM 105 and the large number of wiring patterns are related, the wiring patterns are very complicated to be routed. Therefore, it is very important to optimize the wiring pattern routing that connects the composite chip 104 and the control ROM 105, which makes it possible to shorten the wire length of the wiring pattern, reduce noise, and slim down the entire board. It leads to the plan. Further, the same can be said not only in the relationship between the composite chip 104 and the control ROM 105, but also in the relationship between the composite chip 104 and electronic components such as various connectors. In particular, with respect to wiring patterns connected to a plurality of electronic components such as composite chips 104 such as HAD1 to HAD25 and HDT1 to HDT25, a control ROM 105, and various connectors, the above-mentioned problems are large, and the effect of optimization is also large. It becomes a thing.

Of the wiring lines P27 to P42, in the wiring line P27 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT0 provided in the composite chip arrangement area 191 of the first wiring layer L1 is provided by the wiring line cp301. It is connected to the outside of the composite chip placement area 191, specifically, the via v32 arranged between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection portion HDT0 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. 31, the via v32 is connected to the via v102 arranged in the control ROM arrangement area 192 by the wiring path cp302 provided in the fourth wiring layer L4.

The wiring path that reaches the via v102 from the terminal connection portion HDT0 is branched into four by the via v102. As shown in FIG. 27, the first branch path is connected from the via v102 to the terminal connection portion Q0 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp303 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA34 from the via v102 by the wiring path cp304 provided in the sixth wiring layer L6. The other end of the terminating resistor RA34 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v102 to the via v162 in the first connector arrangement area 194 by the wiring path cp305 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp306 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt0 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v102 to the via v197 by the wiring path cp307 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v197. 6 The wiring path cp308 provided in the wiring layer L6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring path P28 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT1 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp311. Specifically, it is connected to the via v31 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT1 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 31, the via v31 is connected to the via v101 arranged in the control ROM arrangement area 192 by the wiring path cp312 provided in the fourth wiring layer L4.

The wiring path that reaches the via v101 from the terminal connection portion HDT1 is branched into four by the via v101. As shown in FIG. 27, the first branch path is connected from the via v101 to the terminal connection portion Q1 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp313 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA34 from the via v101 by the wiring path cp314 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v101 to the via v161 in the first connector arrangement area 194 by the wiring path cp315 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp316 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt1 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v101 to the via v198 by the wiring path cp317 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v198. 6 The wiring path cp318 provided in the wiring layer L6 is connected to the decoder IC13 constituting the decoding circuit.

In the wiring path P29 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT2 provided in the composite chip arrangement area 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring path cp321. It is connected to the via v24. The via v24 is arranged substantially in the center of four terminal connection portions (including the terminal connection portion HDT2) arranged around the via v24. As shown in FIG. 31, the via v24 is connected to the via v100 arranged in the control ROM arrangement area 192 by the wiring path cp322 provided in the fourth wiring layer L4.

The wiring path that reaches the via v100 from the terminal connection portion HDT2 is branched into four by the via v100. As shown in FIG. 27, the first branch path is connected from the via v100 to the terminal connection portion Q2 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp323 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected from the via v100 to the terminating resistor RA34 by the wiring path cp324 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v100 to the via v160 in the first connector arrangement area 194 by the wiring path cp325 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp326 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt2 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v100 to the via v199 by the wiring path cp327 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v199. 6 The wiring path cp328 provided in the wiring layer L6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring path P30 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT3 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located near the diagonally −XY direction by the wiring path cp331. It is connected to the via v8 arranged in. The via v8 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT3) arranged around the via v8. As shown in FIG. 31, the via v8 is connected to the via v99 arranged in the control ROM arrangement area 192 by the wiring path cp332 provided in the fourth wiring layer L4.

The wiring path that reaches the via v99 from the terminal connection portion HDT3 is branched into four by the via v99. As shown in FIG. 27, the first branch path is connected from the via v99 to the terminal connection portion Q3 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp333 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA34 from the via v99 by the wiring path cp334 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v99 to the via v159 in the first connector arrangement area 194 by the wiring path cp335 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp336 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt3 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v99 to the via v200 by the wiring path cp337 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v200. 6 The wiring path cp338 provided in the wiring layer L6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring path P31 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT4 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp341. Specifically, it is connected to a via v37 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT4 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. 31, the via v37 is connected to the via v98 arranged in the control ROM arrangement area 192 by the wiring path cp342 provided in the fourth wiring layer L4.

The wiring path that reaches the via v98 from the terminal connection portion HDT4 is branched into four by the via v98. As shown in FIG. 27, the first branch path is connected from the via v98 to the terminal connection portion Q4 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp343 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA32 from the via v98 by the wiring path cp344 provided in the sixth wiring layer L6. The other end of the terminating resistor RA32 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v98 to the via v158 in the first connector arrangement area 194 by the wiring path cp345 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp346 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt4 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v98 to the via v189 by the wiring path cp347 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v189. 6 The wiring path cp348 provided in the wiring layer L6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring path P32 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT5 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp351. Specifically, it is connected to the via v46 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT5 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 31, the via v46 is connected to the via v97 arranged in the control ROM arrangement area 192 by the wiring path cp352 provided in the fourth wiring layer L4.

The wiring path that reaches the via v97 from the terminal connection portion HDT5 is branched into four by the via v97. As shown in FIG. 27, the first branch path is connected from the via v97 to the terminal connection portion Q5 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp353 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA32 from the via v97 by the wiring path cp354 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v97 to the via v157 in the first connector arrangement area 194 by the wiring path cp355 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp356 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt5 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v97 to the via v190 by the wiring path cp357 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v190. 6 The wiring path cp358 provided in the wiring layer L6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring path P33 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT6 provided in the composite chip arrangement area 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring path cp361. It is connected to the via v17. The via v17 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT6) arranged around the via v17. As shown in FIG. 31, the via v17 is connected to the via v96 arranged in the control ROM arrangement area 192 by the wiring path cp362 provided in the fourth wiring layer L4.

The wiring path that reaches the via v96 from the terminal connection portion HDT6 is branched into four by the via v96. As shown in FIG. 27, the first branch path is connected from the via v96 to the terminal connection portion Q6 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp363 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA32 from the via v96 by the wiring path cp364 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v96 to the via v156 in the first connector arrangement area 194 by the wiring path cp365 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp366 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt6 from the inside of the first connector arrangement area 194. Further, as shown in FIGS. 28 and 30, the fourth branch path is connected from the via v96 to the via v195 by the wiring path cp367 provided in the third wiring layer L3, and further, as shown in FIG. 34, the fourth branch path is connected to the via v195. 6 The wiring path cp368 provided in the wiring layer L6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring path P34 (FIG. 38), as shown in FIG. 26, the terminal connection portion HDT7 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp371. Specifically, it is connected to the via v45 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT7 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. 31, the via v45 is connected to the via v95 arranged in the control ROM arrangement area 192 by the wiring path cp372 provided in the fourth wiring layer L4.

The wiring path that reaches the via v95 from the terminal connection portion HDT7 is branched into four by the via v95. As shown in FIG. 27, the first branch path is connected from the via v95 to the terminal connection portion Q7 of the control ROM 105 from the outside of the control ROM arrangement area 192 by the wiring path cp373 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA32 from the via v95 by the wiring path cp374 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v95 to the via v155 in the first connector arrangement area 194 by the wiring path cp375 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp376 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt7 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v95 to the via v196 by the wiring path cp377 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v196. 6 The wiring path cp378 provided in the wiring layer L6 is connected to the decoder IC 13 constituting the decoding circuit.

In the wiring path P35 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT8 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp381. Specifically, it is connected to the via v44 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT8 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 31, the via v44 is connected to the via v94 arranged in the control ROM arrangement area 192 by the wiring path cp382 provided in the fourth wiring layer L4.

The wiring path that reaches the via v94 from the terminal connection portion HDT8 is branched into four by the via v94. As shown in FIG. 27, the first branch path is connected from the via v94 to the terminal connection portion Q8 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp383 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA30 from the via v94 by the wiring path cp384 provided in the sixth wiring layer L6. The other end of the terminating resistor RA30 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v94 to the via v154 in the first connector arrangement area 194 by the wiring path cp385 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp386 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt8 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v94 to the via v191 by the wiring path cp387 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v191. 6 The wiring path cp388 provided in the wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P36 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT9 provided in the composite chip arrangement area 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring path cp391. It is connected to the via v23. The via v23 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT9) arranged around the via v23. As shown in FIG. 31, the via v23 is connected to the via v93 arranged in the control ROM arrangement area 192 by the wiring path cp392 provided in the fourth wiring layer L4.

The wiring path that reaches the via v93 from the terminal connection portion HDT9 is branched into four by the via v93. As shown in FIG. 27, the first branch path is connected from the via v93 to the terminal connection portion Q9 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp393 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA30 from the via v93 by the wiring path cp394 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v93 to the via v153 in the first connector arrangement area 194 by the wiring path cp395 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp396 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt9 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v93 to the via v192 by the wiring path cp397 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v192. 6 The wiring path cp398 provided in the wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P37 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT10 provided in the composite chip arrangement area 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring path cp401. It is connected to the via v16. The via v16 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT10) arranged around the via v16. As shown in FIG. 31, the via v16 is connected to the via v92 arranged in the control ROM arrangement area 192 by the wiring path cp402 provided in the fourth wiring layer L4.

The wiring path that reaches the via v92 from the terminal connection portion HDT10 is branched into four by the via v92. As shown in FIG. 27, the first branch path is connected from the via v92 to the terminal connection portion Q10 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp403 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA30 from the via v92 by the wiring path cp404 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v92 to the via v152 in the first connector arrangement area 194 by the wiring path cp405 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp406 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt10 from the inside of the first connector arrangement area 194. Further, as shown in FIGS. 28 and 30, the fourth branch path is connected from the via v92 to the via v193 by the wiring path cp407 provided in the third wiring layer L3, and further, as shown in FIG. 34, the fourth branch path is connected to the via v193. 6 The wiring path cp408 provided in the wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P38 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT11 provided in the composite chip arrangement area 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring path cp411. It is connected to the via v7. The via v7 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT11) arranged around the via v7. As shown in FIG. 31, the via v7 is connected to the via v91 arranged in the control ROM arrangement area 192 by the wiring path cp412 provided in the fourth wiring layer L4.

The wiring path that reaches the via v91 from the terminal connection portion HDT11 is branched into four by the via v91. As shown in FIG. 27, the first branch path is connected from the via v91 to the terminal connection portion Q11 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp413 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA30 from the via v91 by the wiring path cp414 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v91 to the via v151 in the first connector arrangement area 194 by the wiring path cp415 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp416 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt11 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v91 to the via v194 by the wiring path cp417 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v194. 6 The wiring path cp418 provided in the wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P39 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT12 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp421. Specifically, it is connected to the via v43 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT12 is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. 31, the via v43 is connected to the via v90 arranged in the control ROM arrangement area 192 by the wiring path cp422 provided in the fourth wiring layer L4.

The wiring path that reaches the via v90 from the terminal connection portion HDT12 is branched into four by the via v90. As shown in FIG. 27, the first branch path is connected from the via v90 to the terminal connection portion Q12 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp423 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA17 from the via v90 by the wiring path cp424 provided in the sixth wiring layer L6. The other end of the terminating resistor RA17 is connected to the solid wiring layer (GND) of the second wiring layer L2 via a predetermined via (omitted in the wiring diagram).

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v90 to the via v150 in the first connector arrangement area 194 by the wiring path cp425 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp426 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt12 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v90 to the via v185 by the wiring path cp427 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v185. 6 The wiring path cp428 provided in the wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P40 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT13 provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp431. Specifically, it is connected to the via v42 arranged between the composite chip arrangement area 191 and the control ROM arrangement area 192. The terminal connection portion HDT13 is arranged in the second row from the outer peripheral side of the composite chip arrangement area 191. As shown in FIG. 31, the via v42 is connected to the via v89 arranged in the control ROM arrangement area 192 by the wiring path cp432 provided in the fourth wiring layer L4.

The wiring path that reaches the via v89 from the terminal connection portion HDT13 is branched into four by the via v89. As shown in FIG. 27, the first branch path is connected from the via v89 to the terminal connection portion Q13 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp433 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA17 from the via v89 by the wiring path cp434 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v89 to the via v149 in the first connector arrangement area 194 by the wiring path cp435 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp436 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt13 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v89 to the via v186 by the wiring path cp437 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v186. 6 The wiring path cp438 provided in the wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P41 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT14 provided in the composite chip arrangement area 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring path cp441. It is connected to the via v22. The via v22 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT14) arranged around the via v22. As shown in FIG. 31, the via v22 is connected to the via v88 arranged in the control ROM arrangement area 192 by the wiring path cp442 provided in the fourth wiring layer L4.

The wiring path that reaches the via v88 from the terminal connection portion HDT14 is branched into four by the via v88. As shown in FIG. 27, the first branch path is connected from the via v88 to the terminal connection portion Q14 of the control ROM 105 from the inside of the control ROM arrangement area 192 by the wiring path cp443 provided in the first wiring layer L1. Has been done. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA17 from the via v88 by the wiring path cp444 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v88 to the via v148 in the first connector arrangement area 194 by the wiring path cp445 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp446 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt14 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v88 to the via v187 by the wiring path cp447 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v187. 6 The wiring path cp448 provided in the wiring layer L6 is connected to the decoder IC 14 constituting the decoding circuit.

In the wiring path P42 (FIG. 39), as shown in FIG. 26, the terminal connection portion HDT15 provided in the composite chip arrangement area 191 of the first wiring layer L1 is arranged in the vicinity of the diagonal + X + Y direction by the wiring path cp451. It is connected to the via v15. The via v15 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HDT15) arranged around the via v15. As shown in FIG. 31, the via v15 is connected to the via v87 arranged in the control ROM arrangement area 192 by the wiring path cp452 provided in the fourth wiring layer L4.

The wiring path that reaches the via v87 from the terminal connection portion HDT15 is branched into four by the via v87. As shown in FIG. 27, the first branch path is a control ROM arrangement area 192 from the via v87 to the terminal connection portion Q15 / A-1 of the control ROM 105 by the wiring path cp453 provided in the first wiring layer L1. It is connected from the inside of. Further, as shown in FIG. 32, the second branch path is connected to the terminating resistor RA17 from the via v87 by the wiring path cp454 provided in the sixth wiring layer L6.

Further, as shown in FIGS. 28 and 29, the third branch path is connected from the via v87 to the via v147 in the first connector arrangement area 194 by the wiring path cp455 provided in the third wiring layer L3, and further. As shown in FIG. 33, the wiring path cp456 provided in the sixth wiring layer L6 is connected to the terminal connection portion hdt15 from the inside of the first connector arrangement area 194. Further, the fourth branch path is connected from the via v87 to the via v188 by the wiring path cp457 provided in the third wiring layer L3 as shown in FIGS. 28 and 30, and further, as shown in FIG. 34, the fourth branch path is connected to the via v188. 6 The wiring path cp458 provided in the wiring layer L6 is connected to the decoder IC14.

Subsequently, wiring paths P43 to P45 connected to the chip select output terminal HCS0, the lead strobe output terminal HRD, and the system reset terminal HREST of the composite chip 104 will be described.

In the wiring path P43 (FIG. 40), as shown in FIG. 26, the terminal connection portion HCS0 provided in the composite chip arrangement area 191 of the first wiring layer L1 is arranged in the vicinity of the diagonally −X + Y direction by the wiring path cp501. It is connected to the via v9, which is branched into two here. The via v9 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HCS0) arranged around the via v9. As shown in FIG. 25, the first branch path in the via v9 is connected to the via v60 arranged in the control ROM arrangement area 192 by the wiring path cp502 provided in the sixth wiring layer L6, and further, FIG. 27. As shown in the above, the wiring path cp503 provided in the first wiring layer L1 is connected to the terminal connection portion CE # from the inside of the control ROM arrangement area 192.

Further, as shown in FIG. 23, the second branch path in the via v9 is connected to the via v173 by the wiring path cp504 provided in the fourth wiring layer L4, and is further branched into two here. As shown in FIG. 25, the second branch path of the via v173 is connected to the via v201 by the wiring path cp505 provided in the sixth wiring layer L6. This via v201 constitutes a test point TP33. Further, as shown in FIG. 20, the branch path of the second b in the via v173 is connected to DC 3.3V (fifth wiring layer L5) via the resistor RA12 by the wiring path cp506 provided in the first wiring layer L1. There is.

In the wiring path P44 (FIG. 40), as shown in FIG. 20, the terminal connection portion HRD provided in the composite chip arrangement area 191 of the first wiring layer L1 is located in the vicinity of the diagonal + XY direction by the wiring path cp511. It is connected to the arranged via v25 and branches into two here. The via v25 is arranged substantially in the center of the four terminal connection portions (including the terminal connection portion HRD) arranged around the via v25. As shown in FIG. 25, the first branch path in the via v25 is controlled by the wiring path cp512 provided in the sixth wiring layer L6 to the outside of the composite chip placement area 191, specifically to the composite chip placement area 191. It is connected to the via v47 arranged between the ROM arrangement area 192 and further, as shown in FIG. 27, the control ROM is arranged with respect to the terminal connection portion OE # by the wiring path cp513 provided in the first wiring layer L1. It is connected from the outside of the area 192.

Further, as shown in FIG. 22, the second branch path in the via v25 is connected to the via v172 by the wiring path cp514 provided in the third wiring layer L3, and is further branched into two here. As shown in FIG. 22, the second branch path of the via v172 is connected to the via v171 arranged near the outside of the first connector arrangement area 194 by the wiring path cp515 provided in the third wiring layer L3. Further, as shown in FIG. 25, the wiring path cp516 provided in the sixth wiring layer L6 is connected to the terminal connection portion hd from the outside of the first connector arrangement area 194. Further, as shown in FIG. 20, the branch path of the second b in the via v172 is connected to DC 3.3V (fifth wiring layer L5) via the resistor RA8 by the wiring path cp517 provided in the first wiring layer L1. There is.

In the wiring path P45 (FIG. 40), as shown in FIG. 20, the terminal connection portion HREST provided in the composite chip arrangement area 191 of the first wiring layer L1 is located outside the composite chip arrangement area 191 by the wiring path cp521. It is connected to the via v26 arranged on the + X side). The terminal connection portion HREST is arranged on the outermost side of the composite chip arrangement area 191. As shown in FIG. 23, the via v26 is connected to the via v202 by a wiring path cp522 provided in the fourth wiring layer L4, and further, as shown in FIG. 25, the via v26 is connected to the wiring path cp523 provided in the sixth wiring layer L6. It is connected to via v174 by, and here it branches into two.

As shown in FIG. 25, the first branch path in the via v174 is located in the via v108 arranged near the outside (+ X side) of the control ROM arrangement area 192 by the wiring path cp524 provided in the sixth wiring layer L6. It is connected, and as shown in FIG. 27, it is connected to the terminal connection portion SETET # from the inside of the control ROM arrangement area 192 by the wiring path cp525 provided in the first wiring layer L1. As shown in FIG. 25, the wiring path cp524 of the sixth wiring layer L6 is connected to DC 3.3V (fifth wiring layer L5) via the resistor R40, and is grounded (second wiring layer) via the capacitor C151. It is connected to L2).

Further, as shown in FIG. 20, the second branch path in the via v174 is connected to the via v204 by the wiring path cp526 provided in the first wiring layer L1. The via v204 constitutes a test point TP17. The via v204 is connected to the reset circuit on the sixth wiring layer L6 side. That is, as shown in FIG. 25, the via v204 is connected to the resistor built-in transistor T1 by the wiring path cp527 provided in the sixth wiring layer L6, further connected to the logical integrated circuit IC7 by the wiring path cp528, and further connected to the logical integrated circuit IC7 by the wiring path cp528. Therefore, it is connected to the WDT built-in reset integrated circuit (reset IC) IC10 via the via v203 constituting the test point TP23. The wiring path cp528 is connected to DC 3.3V (fifth wiring layer L5) via the resistor R19, and the wiring path cp529 is connected to the ground (second wiring layer L2) via the capacitor C40 and the resistor R26. They are connected to DC 3.3V (fifth wiring layer L5) via DC 3.3V (fifth wiring layer L5), respectively.

The reset circuit on the 6th wiring layer L6 side is configured as shown in FIG. 42. A system reset signal can be input to the logic integrated circuit IC7 via the liquid crystal control first connector CN31, and a reset signal can be input from the WDT built-in reset integrated circuit (reset IC) IC10. When a signal is input, a reset signal is transmitted to the composite chip 104 and the control ROM 105 via the resistor built-in transistor T1 for noise suppression. The LED data output terminal ASIBLDTB of, for example, the composite chip 104 is connected to the WDT built-in reset integrated circuit (reset IC) IC10 for WDT reset.

Here, the test point TP23 is for checking when the reset integrated circuit IC10 is activated, and as shown in FIG. 25, is on the wiring path cp421 on the sixth wiring layer L6 side and in the vicinity of the reset integrated circuit IC10. The display of "TP23", which is the identification information indicating the test point TP23, is arranged on the sixth wiring layer L6 side where the wiring path cp421 is provided, that is, on the back surface 98b side by silk printing. Is normal. On the other hand, the check work by the test point TP23 needs to be performed in the state where the board is assembled (see FIGS. 8 and 9) or the board is assembled (installed) in the game machine main body. The back surface 98b of the 98 is behind the opposite effect interface board 96 and the liquid crystal interface board 97, and the tester cannot be applied to it. Therefore, in the present embodiment, as shown in FIG. 43, the display of "TP23", which is the identification information indicating the test point TP23, is displayed on the front surface instead of the wiring path cp421 side where the test point TP23 is arranged, that is, the back surface 98b side. It is arranged on the 98a side. Since the test point TP23 is composed of the via v203 penetrating the substrate body 190, the tester can be applied from the surface 98a side of the substrate body 190 as well.

Further, the test point TP17 is provided in the via v204 connecting the wiring path cp418 on the first wiring layer L1 side and the wiring path cp419 on the sixth wiring layer L6 side, and the identification information indicating the test point TP17 is provided. The display of "TP17" is also arranged on the surface 98a side like the test point TP23.

The same applies to the other test points TP28 and TP33 described above. That is, the test point TP28 is provided on the wiring path cp3 of the third wiring layer L3, and the display of "TP28", which is the identification information indicating the test point TP28, is arranged on the surface 98a side. Further, the test point TP33 is provided on the wiring path cp505 of the sixth wiring layer L6, and the display of "TP33", which is the identification information indicating the test point TP33, is arranged on the surface 98a side.

Subsequently, the wiring paths P46 and P47 connected to the 8/16 bit mode selection terminal BYTE #, the writable input terminal WE #, and the write-protected / program input terminal WP # / ACC of the control ROM 105 will be described. These wiring lines P46 and P47 are not connected to the composite chip 104.

In the wiring path P46 (FIG. 40), as shown in FIG. 27, the terminal connection portion BYTE # provided in the control ROM arrangement area 192 of the first wiring layer L1 is connected to the via v48 by the wiring path cp531. This via v48 is arranged in the vicinity of the terminal connection portion BYTE # on the outside (-X side) of the control ROM arrangement area 192, and as shown in FIG. 24, becomes DC 3.3V via the fifth wiring layer L5. It is connected. As described above, in the present embodiment, the 16-bit communication mode is selected by connecting the 8/16 bit mode selection terminal BYTE # of the control ROM 105 to the power supply (H level).

In the wiring path P47 (FIG. 40), as shown in FIG. 27, the terminal connection portion WE # (first predetermined terminal) provided in the control ROM arrangement area 192 of the first wiring layer L1 is connected to the via v111 by the wiring path cp541. Is connected to. The via v111 (first predetermined interlayer conduction portion) is arranged in the vicinity of the terminal connection portion WE # on the outside (+ X side) of the control ROM arrangement area 192, and as shown in FIG. 24, the fifth wiring layer L5. It is connected to DC 3.3V via. As described above, in the present embodiment, since the writable input terminal WE # of the control ROM 105 is connected to the power supply (H level), the output impossible mode and the L level (when reading) are in the H level (when not reading). ) Is set to the output mode, and the mode can be switched according to the value (H / L) of the outputable input terminal OE #. The outputable input terminal OE # is connected to the lead strobe output terminal HRD of the composite chip 104 as described above.

Further, in the wiring path P47, as shown in FIG. 27, the terminal connection portion WP # / ACC (second predetermined terminal) provided in the control ROM arrangement area 192 of the first wiring layer L1 is connected to the via v112 by the wiring path cp542. It is connected. The via v112 is arranged near the terminal connection portion WP # / ACC on the outside (+ X side) of the control ROM arrangement area 192. Further, as shown in FIG. 25, the via v112 (second predetermined interlayer conduction portion) is connected to the via v111 via the resistor R43 by the wiring path cp543 provided in the sixth wiring layer L6. The via v111 is connected to DC 3.3V via the fifth wiring layer L5 as described above. As described above, in the present embodiment, the write-protection / program input terminal WP # / ACC of the control ROM (specific electronic component) 105 is connected to the power supply (H level), so that the control ROM (specific electronic component) 105 is set to be writable and program executable. ing. Further, by connecting to the power supply via the resistor R43, the input exceeding the H level is eliminated so that the H level can be stably obtained.

For example, depending on the type of control ROM, when there is an input exceeding the H level and a mode setting different from write prohibition / tolerance and program execution prohibition / tolerance is performed, the mode is set through a resistor in this way. By configuring the H level to be stable, even if the input exceeds the H level due to noise or the like, the control ROM has a mode setting different from write prohibition / tolerance and program execution prohibition / tolerance. It is possible to prevent this from happening.

Summarizing the configurations of the wiring lines P1 to P47 described above, first, among the wiring lines P2 to P45 connecting the composite chip 104 and the control ROM 105, the wiring lines P2 to P43 and P45 (specific wiring lines) are shown in FIG. 27. , As shown in FIGS. 35 to 40, vias v60 to v108 (specific interlayer conductive portions; vias shown in gray in FIGS. 35 to 40) arranged in the control ROM arrangement area (second arrangement area) 192. It is connected to the terminal connection part on the control ROM 105 side, and the wiring paths P2 to P16, P19 to P23, P35 to P43, and P45 (first specific wiring path) among them are connected to the terminals on the control ROM 105 side. Parts A0 to A14, A17 to A21, Q8 to Q15, CE #, and SETET # are connected from the inside of the control ROM arrangement area 192 (wiring lines shown by thick lines in FIGS. 35 to 40). In this way, the wiring path connecting the composite chip 104 and the control ROM 105 is arranged so as to pass through the control ROM arrangement area 192 having a relatively large space, and the terminals of the control ROM 105 are arranged as much as possible. By connecting from the inside of the control ROM arrangement area 192, the wiring pattern on the substrate can be arranged more efficiently, and the limited space can be used more effectively.

Wiring that connects the vias v60 to v108 (specific interlayer conduction portion) arranged in the control ROM arrangement area (second arrangement area) 192 to the terminal connection portion on the control ROM 105 side from the outside of the control ROM arrangement area 192. As for the road, specifically, the wiring path cp165, cp175, cp234, cp244, cp254, cp343, cp353, cp3633, cp373, cp303, cp313, cp323, cp333, as shown in FIG. 27, the length of the control ROM arrangement area 192. The sides 192a and 192b are arranged so as to cross the outside of each terminal connection portion. With this configuration, the wiring length can be shortened as compared with the case of wiring while avoiding the control ROM arrangement area 192, so that the wiring efficiency can be improved and noise can be reduced. Further, in the range shown by the control ROM arrangement area 192, since the control ROM 105 is actually located, the wiring pattern cannot be visually observed, and thus it is possible to prevent unauthorized access to the wiring pattern. It is possible.

Further, a wiring path connected by the first wiring layer L1 to the vias v60 to v108 (specific interlayer conduction portion) arranged in the control ROM arrangement area (second arrangement area) 192, specifically, the wiring path cp233. , Cp243 and cp253 are also arranged so as to cross the long side 192a of the control ROM arrangement area 192 outside each terminal connection portion, as shown in FIG. 27. By making such a configuration at a plurality of places in combination with the configuration of the previous stage, the effect described in the previous stage becomes more effective.

Further, a ROM socket 193 (FIG. 8) is fixed to the control ROM arrangement area 192, and the bottom wall (shielding wall corresponding to the specific interlayer conduction portion) 193a of the ROM socket 193 shields the control ROM arrangement area 192. Even when the control ROM 105 is removed from the ROM socket 193, the wiring pattern in the control ROM arrangement area 192 including the vias v60 to v108 (specific interlayer conduction portion) cannot be visually recognized or accessed from the outside.

The vias v60 to v108 (specific interlayer conductive portions) in the control ROM arrangement area 192 penetrate from the front surface (first surface) 98a to the back surface (second surface) 98b of the substrate main body 190 to enhance the heat dissipation effect. Further, the vias v60 to v108 (specific interlayer conduction portion) in the control ROM arrangement area 192 are connected to predetermined electronic components such as ICs, resistors, capacitors, and connectors on the back surface 98b side, that is, the sixth wiring layer L6 side. ..

Further, regarding the wiring paths P2 to P45 connecting the composite chip 104 and the control ROM 105, the predetermined via and the control ROM 105 are connected to the predetermined via from the first wiring portion connecting the composite chip 104 and the predetermined via (predetermined interlayer conduction portion). It is branched into a second wiring part for connecting the above and a third wiring part for connecting the predetermined via and other electronic components such as the liquid crystal control first connector CN31. Then, the second wiring portion is in the first predetermined wiring layer such as the first wiring layer L1, and the third wiring portion is in the second predetermined wiring layer L3, the sixth wiring layer L6, etc., which is different from the first predetermined wiring layer. It is arranged in each wiring layer.

Further, among the wiring paths P2 to P45, in the wiring paths P2 to P42 for transmitting address / data information, a predetermined via (predetermined interlayer conduction portion), which is a branching point, is a control ROM arrangement area (second arrangement area). ) It is a specific interlayer conductive part (via shown in gray in FIGS. 35 to 40) arranged in 192, and the second wiring part is in the first wiring layer L1 and at least a part of the first wiring part. Is provided in the fourth wiring layer L4 (an example of a predetermined wiring layer different from the first wiring layer), and the third wiring portion is provided in the first wiring layer L1 (first predetermined wiring layer). This makes it possible to improve the preventability against goto acts such as illegally modifying the wiring pattern and vias that transmit address / data information. Further, by drawing a wiring pattern in the control ROM arrangement area 192, it is possible to secure a wiring space in other areas. Further, especially with respect to the branch points, since the wiring patterns tend to be densely packed over a plurality of layers of the board, a sufficient wiring space is required in the portion where the branch points are provided, but from that point as well, there is a margin in the wiring space. It is effective to arrange the branch portion in the control ROM arrangement area 192 with a certain position.

Further, among the vias v60 to v107 (specific interlayer conduction portion) in the control ROM arrangement area 192, the vias v61 to v85 and v103 constituting a part of the wiring paths P2 to P26 (address wiring) for transmitting address information. ~ V107 (first specific interlayer conductive portion) and vias v87 to v102 (second specific interlayer conductive portion) forming a part of wiring paths P27 to P42 (data wiring) for transmitting data information are controlled. The terminals are arranged in the Y direction (first direction), which is the arrangement direction of the terminals in the ROM 105.

Further, the address output terminals HAD1 to HAD25 on the composite chip 104 side, the data input / output terminals HDT0 to HDT15 (first terminal), and the corresponding address input terminals A0 to A24 on the control ROM 105 side, and the data input / output terminals Q0 to Q15. The arrangement is different from that of (second terminal), and the wiring paths P2 to P42 connecting them have vias v60 to v85 and v87 to v107 (specific interlayer conduction portions) in the control ROM arrangement area 192. The arrangement of vias v60 to v85 and v87 to v107 (specific interlayer conduction portion) in the control ROM arrangement area 192 is approximated to the arrangement of the corresponding terminals (specific second terminal) on the control ROM 105 side. As a result, the wiring pattern connecting the specific interlayer conductive portion and the terminal of the control ROM can be organized, and it is not necessary to route the patterns so that the positional relationship between the plurality of wiring patterns changes (twists), for example. Therefore, the connection method is easier, and the space in the control ROM arrangement area 192 can be used more effectively. In this way, when the terminal arrangement of the composite chip 104 and the terminal arrangement of the control ROM 105 are different, a wiring pattern having a relatively short wiring distance from the specific interlayer conductive portion in the arrangement area of the control ROM 105 to the terminal of the control ROM 105. Rather than devising the routing of the specific interlayer conductive portion, the arrangement of the specific interlayer conductive portion is approximated to the terminal arrangement of the control ROM 105 by devising the routing of the wiring pattern having a relatively long wiring distance from the composite chip 104 to the specific interlayer conductive portion. Can be said to be more effective in terms of wiring efficiency.

Specifically, as shown in FIG. 27, for example, address input terminals A0 to A6 and corresponding vias v85 to v79, address input terminals A17 to A20 and corresponding vias v68 to v64, and data input / output terminals Q12 to Q15. And the corresponding vias v90 to v87 are arranged in substantially the same order in the Y direction, respectively, and the address input terminals A23, A22, A24, A16, A15 and the corresponding vias v62, v63, v61, v103, v104. ,, Data input / output terminals Q0 to Q3 and corresponding vias v102 to v99, data input / output terminals Q8 to Q11 and corresponding vias v94 to v91, data input / output terminals Q4 to Q7 and corresponding vias v98 to v95. Are arranged in substantially reverse order in the Y direction, respectively. In this way, instead of devising the arrangement of the specific interlayer conduction portion in consideration of only the terminal arrangement of the control ROM 105, the terminal arrangement on the composite chip 104 side and the terminal arrangement on the liquid crystal control first connector CN31 side, which are also in a connection relationship. In consideration of the above, the specific interlayer conductive portions may be arranged. As a result, the connection relationship with the control ROM 105 is partially complicated, but the composite chip 104 located farther than the terminal of the control ROM 105 and the liquid crystal control first connector CN31 side with the specific interlayer conduction portion as a reference. Since the connection relationship with the terminals is simplified, it is possible to improve the wiring efficiency of the entire board. That is, the wiring efficiency of the entire substrate can be improved by devising the arrangement of the specific interlayer conduction portions as necessary in the control ROM arrangement area 192. Further, the wiring efficiency of the entire board can be improved not only in the control ROM arrangement area 192 but also by devising the arrangement of the vias serving as branch points as described above.

Further, the address output terminals HAD1 to HAD25 and the data input / output terminals HDT0 to HDT15 (first terminal) on the composite chip 104 side are the address input terminals A0 to A24 and the data input / output terminals Q0 to Q15 on the control ROM 105 side corresponding to them. The arrangement is different not only from (second terminal) but also from each terminal had1 to had25 and hdt0 to hdt15 (third terminal) of the liquid crystal control first connector CN31, and vias v61 to v85 and v87 to v102 (specific interlayer conduction). The arrangement of (part) is matched (approximate) with the arrangement of the terminals had1 to had25 and hdt0 to hdt15 (third terminal) of the liquid crystal control first connector CN31. That is, as shown in FIGS. 28, 29, and 33, the arrangement of the vias v61 to v85 and v87 to v102 (specific interlayer conduction portions) in the Y direction corresponds to each terminal of the liquid crystal control first connector CN31 had1 to Since it matches the arrangement of had25 and hdt0 to hdt15 in the X direction, the wiring path group (third wiring path group) connecting them can be arranged in parallel without twisting. As a result, the wiring path group (2nd terminal) connecting the vias v61 to v85, v87 to v102 (specific interlayer conduction portion), the address input terminals A0 to A24 on the control ROM 105 side, and the data input / output terminals Q0 to Q15 (second terminal) ( The second wiring path group) has a complicated wiring pattern including twisting, but this can be easily realized by arranging it in the control ROM arrangement area 192 having a relatively large space.

Of the wiring paths P2 to P42 that transmit address / data information, the wiring paths P2 to P13 and P19 to P42 have vias v61 to v68, v74 to v85, and v87 to v102 in the control ROM arrangement area 192. The control ROM 105 side and the liquid crystal control first connector CN31 side are branched in the specific interlayer conduction portion), but the wiring paths P14 to P18 are on the control ROM 105 side in the vias v69 to v73 in the control ROM arrangement area 192. Vias v103 to v107 are separately provided on the wiring path connecting the vias v69 to v73 and the liquid crystal control first connector CN31 and in the control ROM arrangement area 192 without branching, and the vias v103 to v107 branch to the control ROM 105 side. ing. With this configuration, the wiring to the liquid crystal control first connector CN31 is arranged in parallel without twisting in harmony with the other wiring lines, and the wiring to the control ROM 105 also interferes with the other wiring lines. It is possible to arrange efficiently while avoiding it.

Further, the specific one-end side terminals A0 to A7, A17, A18, A20, A21, Q0 to Q3, Q8 to Q11 included in the one-end side terminals arranged on one end side of the control ROM (second electronic component) 105, and those. The first specific terminals HAD0 to HAD7, HAD17, HAD18, HAD20, HAD21, HDT0 to HDT3, HDT8 to HDT11 on the corresponding composite chip (first electronic component) 104 side are via v65 to v68, v78 to v85, v91 to v94. , V99 to v102 (first interlayer conductive portion), and a plurality of one-end side wiring paths P2 to P9, P19, P20, P22, P23, P27 to P30, P35 to P38, and a control ROM (second electron). Specific other end side terminals A8 to A16, A19, A22 to A24, Q4 to Q7, Q12 to Q15 included in the other end side terminal arranged on the other end side of 105 and a composite chip corresponding to them (first). Electronic components) The second specific terminals HAD8 to HAD16, HAD19, HAD22 to HAD24, HDT4 to HDT7, HDT12 to HDT15 on the 104 side are via v61 to v63, v66, v74 to v77, v87 to v90, v95 to v98 (second). A plurality of other end side wiring paths P10 to P18, P21, P24 to P26, P31 to P34, P39 to P42, which are connected to each other via the interlayer conductive portion), are provided, and the first interlayer conductive portion and the second interlayer conductive portion are provided. Are arranged in a different arrangement from the first specific terminal and the second specific terminal, respectively, and are arranged close to each other so as to be arranged so as to correspond to the specific one end side terminal and the specific other end side terminal.

Further, the inner connection wiring portion connected from the inside of the control ROM arrangement area 192 and the outer connection wiring portion connected from the outside are alternately arranged with respect to the plurality of ROM terminal connection portions arranged in a row. That is, as shown in FIG. 27, with respect to the terminal connection portions Q0, Q8, Q1, Q9, Q2, Q10, Q3, and Q11 of the control ROM arrangement area 192, the external connection wiring portions cp303, cp313, cp323, and cp333 are included. The connection wiring portions cp383, cp393, cp403, and cp413 are alternately connected. Moreover, the vias v102 to v99 on the other end side of the external connection wiring portions cp303, cp313, cp323 and cp333 are arranged close to each other, and the vias v94 to v91 on the other end side of the internal connection wiring portions cp383, cp393, cp403 and cp413 are arranged close to each other. Are also located close to each other. Similarly, for the terminal connection portions Q15 / A-1, Q7, Q14, Q6, Q13, Q5, Q12, and Q4 of the control ROM arrangement area 192, the internal connection wiring portions cp453, cp443, cp433, and cp423 are externally connected. The wiring portions cp373, cp363, cp353, and cp343 are alternately connected. Moreover, the vias v87 to v90 on the other end side of the internal connection wiring portions cp453, cp443, cp433, cp423 are arranged close to each other, and the vias v95 to v98 on the other end side of the external connection wiring portions cp3733, cp3633, cp353, cp343 are arranged close to each other. Are also located close to each other. In this way, by arranging and grouping the inner connection wiring portion and the outer connection wiring portion in the vicinity instead of the terminal arrangement of the control ROM 105, the wiring pattern can be simplified and the wiring efficiency can be improved. ..

Further, the first wiring path P2 to P42 for transmitting address information or data information and the second wiring path P43 for transmitting chip select information are different wiring layers, that is, the first wiring layer P2 to P42 is the fourth wiring. The layers L4 and the second wiring path P43 are connected to the vias v61 to v85, v87 to v101, and v60 (specific interlayer conduction portions) in the control ROM arrangement area 192 from the composite chip 104 side in the sixth wiring layer L6. In this way, by wiring the chip select signal, which is important in data transmission, using a wiring layer different from the wiring pattern for transmitting address information or data information, transmission of the wiring pattern for transmitting address information or data information is performed. It is possible to make it difficult for noise to get on the chip select signal, and it is possible to make a configuration that is resistant to noise. In addition, by making the wiring path pattern of the chip select signal different from other wiring paths, it becomes relatively easy to identify the wiring of the chip select signal, and whether the wiring pattern is short-circuited or not. It is possible to perform a check and an energization check relatively easily.

Further, in the wiring path P45 constituting the reset circuit, the wiring paths cp418 to cp421 (reset first wiring path) connecting the reset integrated circuit (reset IC) IC10 and the via v174 (predetermined interlayer conduction portion) and the via v174. The wiring paths cp413 to cp415 (reset second wiring path) connecting the (predetermined interlayer conductive portion) and the reset terminal HSET of the composite chip 104, the via v174 (predetermined interlayer conductive portion), and the reset terminal SETT # of the control ROM 105 are connected. A test point TP17 (first) that is provided with wiring paths cp416 and cp417 (reset third wiring path) to be connected and penetrates the liquid crystal control board 98 in the plate thickness direction on the wiring paths cp418 to cp421 (reset first wiring path). (Test point) and test point TP23 (second test point) are arranged, and the identification information "TP17" and "TP23" indicating the test points TP17 and TP23 are used, the liquid crystal control board 98 is used as another effect interface board 96, and the liquid crystal interface. When assembled together with the substrate 97 and the like, it is displayed on the front side, that is, the surface (first surface) 98a on the side opposite to the substrates 96 and 97. The reset integrated circuit (reset IC) IC10 is arranged on the back surface (second surface) 98b side. As a result, when the board is assembled (see FIGS. 8 and 9) or when the board is assembled (installed) on the main body of the gaming machine, the portion of the wiring path where the test points TP17 and TP23 are arranged cannot be visually recognized. Nevertheless, it is possible to easily perform the check operation by the test points TP17 and TP23 based on the identification information displayed on the visible surface 98a side.

Further, the wiring paths cp418 to cp421 (reset first wiring path) are arranged on the wiring path cp418 (first wiring path) arranged on the front surface (first surface) 98a side and on the back surface (second surface) 98b side. It has wiring paths cp420 and cp421 (second wiring path) and via v204 (reset first interlayer conduction portion) connecting them, and test point TP17 (first test point) is placed on the via v204 for testing. The point TP23 (second test point) is arranged on the wiring path cp421 (second wiring path).

Further, the control ROM (specific electronic component) 105 operates in an operation mode corresponding to the voltage level of the write-protected / program input terminal WP # / ACC (second predetermined terminal), and the writable input terminal WE # (first). The predetermined terminal) is connected to the power supply wiring path of the fifth wiring layer L5 via the via v111 (first predetermined interlayer conduction portion), and the write-protected / program input terminal WP # / ACC (second predetermined terminal) is a resistor. It is connected to via v111 (first predetermined interlayer conduction portion) via R43. Further, a control ROM (specific electronic component) 105 is arranged on the front surface (first surface) 98a of the liquid crystal control substrate 98, and a resistor R43 is arranged on the back surface (second surface) 98b, respectively, and via v112 (second predetermined interlayer conduction portion). The write-protection / program input terminal WP # / ACC (second predetermined terminal) and the resistor R43 are connected to each other via. In this way, the via that connects the WP # / ACC (second predetermined terminal) to the power supply wiring line via the resistor R43 is common as the via that connects the WE # (first predetermined terminal) to the power supply wiring path. It is possible to reduce the number of vias as compared with the case of connecting individually via vias.

Further, a plurality of terminals are arranged in a matrix on the bottom surface side of the composite chip 104, and among the plurality of terminals, an outer terminal arranged near the outer periphery of the composite chip arrangement region (first arrangement area) 191. For example, the terminals HDT0, HDT1, HDT4, HDT5 and the like arranged on the outermost peripheral side and the second row inside the outermost peripheral side are connected to the control ROM 105 by the first wiring lines P27, P28, P31, P32 and the like, and are inside the outer terminal. The inner terminals to be arranged, for example, terminals HDT2, HDT3, HDT6, etc. are connected to the control ROM 105 by the second wiring lines P29, P30, P33, etc., and the first wiring lines P27, P28, P31, P32, etc. are the composite chip arrangement area. Vias v32, v31, v37, v46, etc. (first interlayer conductive portion) arranged outside 191 and outer terminals HDT0, HDT1, HDT4, HDT5, etc. are connected by the first wiring layer L1 and the second wiring path P29. , P30, P33, etc. connect the vias v24, v8, v17, etc. (second interlayer conductive portion) arranged inside the composite chip arrangement area 191 and the inner terminals HDT2, HDT3, HDT6, etc. with the first wiring layer L1. doing. Further, the distance from the inner terminals HDT2, HDT3, HDT6, etc. to the vias v24, v8, v17, etc. It is shorter than the distance to (the first interlayer conductive part).

In the composite chip 104 in which a plurality of terminals are arranged in a matrix in this way, the outer terminals arranged near the outer periphery of the arrangement area of the composite chip 104 are connected to the vias arranged outside the composite chip 104. As a result, a wiring space is created near the outer periphery of the composite chip 104, and the wiring pattern of the inner terminal of the composite chip 104 can be easily routed to the outer side of the composite chip, so that the wiring efficiency can be improved. Further, regarding the above-mentioned wiring space, since the wiring space near the outer periphery of the composite chip is generated in the plurality of wiring layers of the substrate, no matter which wiring layer among the plurality of wiring layers is used, the wiring space is outside the composite chip. Needless to say, it becomes easier to wire the wiring pattern.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, in the embodiment, the wiring paths P2 to P42 for transmitting address information / data information between the composite chip 104 and the control ROM 105 are subjected to specific interlayer conduction arranged in the control ROM arrangement area (second arrangement area) 192. Although it is assumed to have a portion, at least a part of those wiring paths P2 to P42 may not have a specific interlayer conduction portion.

In the embodiment, in the wiring paths P2 to P42, the arrangement of the vias v61 to v85 and v87 to v102 (specific interlayer conduction portions) in the Y direction is arranged in the Y direction, and the corresponding terminals of the liquid crystal control first connector CN31 have each terminal had1 to had25, hdt0 to 0. Although it is matched with the arrangement in the X direction of hdt15, the arrangement in the Y direction of vias v61 to v85 and v87 to v102 (specific interlayer conduction portion) may be matched (or approximated) with the terminal arrangement of the control ROM 105.

In the embodiment, regarding the test points that need to be checked with the board assembled, the check target is on the outer surface of the board with the board assembled, regardless of whether the check target is on the front or back of the board. Although it is configured to display the identification information of the test points, the identification information may be displayed on both sides of the substrate for such test points.

In the embodiment, among the terminals of the composite chip 104, the terminals (outer terminals) arranged in the outermost peripheral side of the composite chip arrangement region (first arrangement region) 191 and the innermost second row thereof are the first wiring layer. It is connected to the interlayer conductive portion arranged outside the composite chip arrangement region 191 in L1, and the terminals (inner terminals) inside the interlayer conduction portion are arranged inside the composite chip arrangement region 191 in the first wiring layer L1. Although it is configured to be connected to the interlayer conductive portion, only the terminal on the outermost peripheral side in the composite chip arrangement region 191 may be used as the outer terminal, or the terminals from the outermost peripheral side to the third row may be used as the outer terminal.

Further, in the embodiment, only the wiring related to the terminal on one edge side of the composite chip 104 is specifically illustrated, but the present invention is not limited to this, and the same configuration or embodiment is also used on the other edge side of the composite chip 104. It may be configured so as to have the contents described in. As described above, by adopting the configuration described in this embodiment also on each edge side of the composite chip 104, it is possible to further improve the wiring efficiency. For example, the configuration shown in FIG. 12 can be given as an example.

In the embodiment, an example in which the first to sixth wiring layers L1 to L6 are provided on the liquid crystal control substrate 98 is shown, but the number of wiring layers may be smaller or larger than this. When reducing the number of wiring layers, the solid wiring layer for ground connection and the solid wiring layer for power supply connection may be omitted.

Regarding the connection between the terminal of the composite chip 104 and the via in the composite chip arrangement area 191, the distance between each terminal and each via may be designed to be substantially the same distance. As a result, the distances between the plurality of terminals and the vias are approximately equal, so that noise is less likely to occur and the arrangement of the vias can be arranged in a more appropriate state.

Further, regarding the direction in which the wiring is drawn from the terminal of the composite chip 104 toward the via, it is desirable that the wiring drawing direction (via arrangement direction) is common to the terminals adjacent to each other in the vertical and horizontal directions. Further, when those terminals are regarded as one group, it is desirable that the wiring lead-out direction (via arrangement direction) is different from the above-mentioned direction for the terminal group different from the terminal group. By setting the wiring lead-out direction (via placement direction) for each terminal group in this way, it is easy to check and recognize the information of each terminal by the wiring pattern, so it is easy to inspect and check after completion. Become. Further, by setting the terminals for transmitting address information as one group or the terminals for transmitting data information as one group, the above-mentioned effect can be further exhibited. Further, with respect to the terminals of individual signals such as chip select signals, vias may be provided in a wiring lead-out direction different from that of the above-mentioned group 1 to facilitate confirmation and recognition. Further, by providing vias in the common wiring lead-out direction for the terminals of the chip select signal, it is possible to make it difficult to identify important terminals such as the chip select signal and signal lines, and to have a configuration that is resistant to fraudulent activity.

As shown in FIG. 26, a wiring pattern may be provided so as to reach within or near the control ROM arrangement area 192 without via vias, such as the wiring path cp221 connected to the HAD22 terminal of the composite chip 104. By wiring in this way, the number of vias around the composite chip 104 can be reduced, so that the space can be used as an installation location for other wiring and vias. Further, although the wiring path cp221 is connected to the via v53, the wiring path cp221 may be configured to be connected to the terminal of the control ROM 105 without passing through the via.

As shown in FIG. 27, address information and data information are transmitted for wiring patterns of special terminals such as OE #, WE #, BYTE #, WP # ACC, CE #, and SETET # among the terminals of the control ROM 105. The connection distance from the via may be set shorter than the wiring pattern. As a result, it is possible to easily distinguish the types of wiring patterns at the time of assembling the substrate, at the time of inspection, and the like. On the contrary, by setting a long connection distance, it may be configured so that the types of wiring patterns can be easily distinguished. Further, since it is a terminal connection pattern for controlling the operation of the control ROM 105, it is desirable to set a relatively short wiring pattern in consideration of noise and the like.

As shown in FIG. 27, in the control ROM arrangement area 192, the first via arrangement group (v61 to v85, etc.) and the second via arrangement group (v87 to v102, etc.) are arranged so as to be shifted in the X-axis direction. It is possible to easily draw out the wiring pattern from each array group in the Y-axis direction. If the first via array group and the second via array group are arranged in the Y-axis direction without being shifted in the X-axis direction, they will not fit in the control ROM arrangement area 192 and will protrude in the X-axis direction. By staggering and arranging them so as to overlap in the Y-axis direction, the first via arrangement group and the second via arrangement group can be accommodated in the control ROM arrangement area 192, and the wiring space in the control ROM arrangement area 192 can be further increased. It can be used effectively.

Further, even if the first via array group and the second via array group are shifted in the Y-axis direction and arranged so as to overlap in the X-axis direction, if they fit within the control ROM arrangement area 192, they are shifted in the Y-axis direction. They may be arranged so as to overlap in the X-axis direction. In this case, it becomes difficult to draw out the wiring pattern from each array group in the Y-axis direction, but at least the drawing out in the X-axis direction is not limited. Further, for example, when the first via array group or the second via array group is the branching point, the arrangement of the connection terminals at the branch destination is taken into consideration, and the first via array group or the second via array group is arranged so as to be shifted in the Y-axis direction and overlapped in the X-axis direction. If the arrangement is more efficient, it may be configured as such. Similarly, they may be arranged so as to be displaced in the X-axis direction and overlapped in the Y-axis direction. Depending on the shape of the control ROM arrangement area 192 and the wiring pattern routing method, it may be possible that the arrangement relationship is more suitable.

As shown in FIG. 20, the physical connection distance is determined by determining the arrangement relationship between the composite chip 104 and the control ROM 105 according to the position of the terminal arrangement of the composite chip 104 having a connection relationship with the terminals of the control ROM 105. It may be configured to be close to each other. This is not particularly limited to the control ROM 105, and the wiring efficiency is improved by determining the arrangement position, arrangement direction, distance, etc. of the electronic components connected to those terminals with reference to the position of each terminal of the composite chip 104. be able to. Of course, only the specific electronic components such as the control ROM 105 may have the above-mentioned arrangement relationship, whereby the partial wiring efficiency can be improved, but more preferably, a plurality of electronic components have the same arrangement relationship. By doing so, the wiring efficiency of the entire substrate can be improved.

Further, for wiring that requires connecting the composite chip 104 and a plurality of electronic components, such as a wiring pattern for transmitting address information and data information, the first electronic component (eg, control) that is close to the composite chip 104 (eg, control). Wiring efficiency is achieved by providing the first electronic component, which is closer to the ROM 105) and the second electronic component farther away (eg, the liquid crystal control first connector CN31), on the side where the connection terminal of the composite chip 104 is located. May be increased. Further, it goes without saying that the wiring efficiency can be further improved by providing both the first electronic component and the second electronic component farther away from the first electronic component on the side where the connection terminal of the composite chip is located. Further, the wiring efficiency may be improved by providing the distant second electronic component of the first electronic component and the second electronic component on the side where the connection terminal of the composite chip 104 is located. In this case, the first electronic component is arranged on a side different from the side where the connection terminal of the composite chip is located, which may seem inefficient at first glance, but wiring for transmitting address information and data information on the entire board. When considering the wiring efficiency of the pattern, it may be more effective. Further, the first electronic component is not limited to the control ROM, and may be a connector, a (terminating) resistor, or the like. Similarly, the second electronic component is not limited to the connector, but may be a control ROM or a (terminating) resistor.

As shown in FIG. 19, the terminals of the control ROM 105 include terminals (NC terminals and the like) that are not connected to the terminals of the composite chip 104, and in FIG. 27 (although the NC terminals and the like are omitted here), control is performed. Vias for connecting wiring patterns that are connected to terminals other than NC terminals to locations (areas) that are displaced in the X-axis direction with respect to locations in the ROM layout area 192 where the NC terminals of the control ROM 105 are located (FIG. 27). In the above, v80 to v85 and the like may be provided). The reason for configuring in this way is that NC terminals and the like do not need to consider the wiring pattern to be connected and the arrangement of vias, so wiring space tends to be relatively likely to occur around them, so that area is utilized. This is because the via can be arranged. Further, since there is a margin of space around the NC terminal or the like, there is an advantage that the wiring pattern from the via can be easily drawn out in the Y-axis direction or the X-axis direction. Further, not only the NC terminal but also the VCS terminal and the GND terminal have the same configuration, so that the above-mentioned effect can be obtained.

As shown in FIG. 31, vias (examples: v49 to v54) for connecting the wiring pattern for connecting the terminal of the composite chip 104 and the terminal of the control ROM 105 are placed near or around the outside of the control ROM arrangement area 192. By providing and configuring the wiring pattern so as to be routed in the control ROM arrangement area 192 via the via, the via can be visually recognized from the outside of the board without being shielded by the control ROM 105 or the like, so that the control ROM is arranged. Compared with a wiring pattern in which vias are not provided near or around the outer side of the area 192, it becomes easier to check and inspect the wiring pattern connecting the terminals of the composite chip 104 and the terminals of the control ROM 105, and the control ROM arrangement area 192 Wiring efficiency can be further improved by arranging vias near the outside.

As shown in FIGS. 27 and 28, the vias v69 to v73 are arranged and arranged together with the other vias in the control ROM arrangement area 192, but the vias v103 to v107 are arranged in connection with the terminals of the control ROM 105. The wiring pattern is drawn out to the control ROM arrangement area 192 via the above. In this way, the wiring pattern for connecting the vias (v69 to v73) arranged together with the other specific interlayer conductive portions and the terminals of the control ROM 105 is set in the control ROM arrangement area 192 via another via (v103 to v107). It can be configured to increase the wiring efficiency by routing the. Further, even in that case, since the vias v69 to v73 are arranged in the same manner as the other vias, it is possible to relatively easily perform inspections such as confirmation of connection relationship and energization check.

In the embodiment, the composite chip 104 of VDP + CPU is illustrated, but a CPU chip having no VDP function may be used. Further, the control ROM is not limited to the storage medium for storing the control program of the CPU, and may be a ROM for storing audio data and image data.

Vias located in the composite chip placement area 191 and the control ROM placement area 192 may be used as test points for continuity check. In this case, it is desirable to configure the test point notation (display of identification information) by silk printing in the vicinity or the periphery of the via located in the composite chip arrangement area 191 or the control ROM arrangement area 192. As a result, the continuity check of the composite chip 104 and the control ROM 105 can be easily performed, and the silk-printed notation of the test point can be arranged by utilizing the composite chip arrangement area 191 and the control ROM arrangement area 192.

As shown in FIG. 42, by connecting the SRESET signal and the WTDOG signal to the common logic integrated circuit IC7, it is possible to appropriately perform the reset process when the reset signal is input due to any reset factor. It has become. Further, the output information (reset signal) from the logic integrated circuit IC7 is output not only to the composite chip 104 and / or the control ROM 105, but also to the decoders IC13 and IC14 shown in FIG. 41 (FIG. 42). By configuring the system so as to output from the IO-RST of the above, it is possible to execute the reset process for the liquid crystal display unit 76. As a result, it is possible to realize a reset operation synchronously or at substantially the same timing by hardware such as different electronic components.

Further, in order to reset an external ROM such as a CG ROM or an audio ROM, a reset signal may be separately output to the composite chip 104 (output from the DDR-RST of FIG. 42). In this way, even if the output target is the same composite chip 104, it may be configured to output a different reset signal for each reset target. As a result, the circuit configuration can be configured so that the reset process can be performed according to the reset target and the reset purpose. Further, as shown in FIG. 42, the IO-RST signal and the DDR-RST signal are also signals output from the logic integrated circuit IC7, and the SRESET signal and / or the WTDOG signal are logical as in the CPU-RST signal. This is a signal that is output as a trigger when it is input to the integrated circuit IC7.

Further, although the common logic integrated circuit IC7 is used in the embodiment, the present invention is not limited to this, and a plurality of logic integrated circuits may be provided. In this case, a different logic integrated circuit may be used for each of the CPU-RST signal, IO-RST signal, and DDR-RST signal, or the CPU-RST signal and the IO-RST signal and DDR-RST signal are different. It may be configured to use a logic integrated circuit. When a plurality of logic integrated circuits are used in this way, although it is costly, it is possible to prevent the reset signal from being output to all the hardware due to a defect. Even in this case, a common SRESET signal and / or WTDOG signal is input to different logic integrated circuits.

As shown in FIG. 19, the terminals of the control ROM 105 include terminals (NC or the like) that are not connected to the terminals of the composite chip 104, and the control ROM is arranged in FIG. 27 (although the NC terminal or the like is omitted here). A location (area) shifted in the X-axis direction with respect to the location of the NC terminal of the control ROM in the region 192, and a location (region) shifted in the X-axis direction with respect to the location of the terminal other than the NC terminal. Therefore, the number of vias installed in the control ROM arrangement area 192 may be different. In this way, by making the number of vias arranged different for each corresponding location (area), the space in the control ROM arrangement area 192 may be effectively utilized. In addition, as a matter of course, the wiring pattern drawn from the via is connected to the terminals other than the NC terminal, so there is an advantage that the connection distance is shortened when arranging in the vicinity, and conversely, the NC terminal is located. When the wiring pattern drawn from the via drawn from the part (area) shifted in the X-axis direction is connected to the part to be connected, the connection distance becomes long, but the wiring space is relatively large. , There is a merit that it becomes easy to route.

Further, among the vias in the control ROM arrangement area 192, vias that are not directly connected to the terminals of the control ROM (example: a plurality of vias located between v68 and v74 in FIG. 27) are as shown in FIG. 27. In addition, it may be provided at a location (region) shifted in the X-axis direction with respect to a location where terminals other than the NC terminal are located. This is because the wiring pattern is not drawn out from these vias on the first wiring layer L1, so that there is little possibility that the wiring space is obstructed in the control ROM arrangement area 192. On the contrary, it may be provided at a position (area) shifted in the X-axis direction with respect to the position where the NC terminal of the control ROM 105 is located in the control ROM arrangement area 192. In this case, a wiring space can be provided at a location (region) shifted in the X-axis direction with respect to a location where terminals other than the NC terminal are located. In any case, in the embodiment, the via array as shown in FIG. 27 is constructed while considering the above-mentioned merits and considering the connection relationship with electronic components (example: connector) other than the control ROM. ing.

In the example of FIG. 27, vias for conducting wiring patterns for transmitting address information are arranged in a predetermined array, and vias for conducting wiring patterns for transmitting data information are arranged in a predetermined array. The via arrangement was installed so as to be a group, but the vias are not limited to this, and the vias that conduct the wiring pattern for transmitting address information and the vias that conduct the wiring pattern for transmitting data information are arranged in a predetermined arrangement. They may be installed so as to form one via group by arranging them side by side. In this case, since the vias that conduct the wiring patterns that transmit different information can be densely packed, the installation range of the vias can be made relatively small. Further, as in the vias v87 to v90 shown in FIG. 27, some vias may be arranged as a small group in the array of vias for conducting the wiring pattern for transmitting data information. The same configuration may be used for vias that conduct a wiring pattern for transmitting address information.

In the example of FIG. 27, vias for conducting the wiring pattern for transmitting address information and vias for conducting the wiring pattern for transmitting data information are arranged in a predetermined arrangement in the control ROM arrangement area 192, respectively. However, the present invention may be limited to this, and the vias may be arranged in a predetermined arrangement outside the control ROM arrangement area 192. In this case, the control ROM arrangement area 192 cannot be utilized, but since the wiring pattern is connected from the outside of the control ROM arrangement area 192 to the terminals of the control ROM 105, check the connection status for each terminal of the control ROM. There is a merit that it becomes easier. However, since the required wiring space is relatively large as compared with the case where the control ROM arrangement area 192 is used, it is desirable to adopt such a configuration when there is a relatively large space.

As shown in FIG. 27, regarding the wiring pattern of special terminals such as OE #, WE #, BYTE #, WP # / ACC among the terminals of the control ROM 105, the wiring pattern is from the outside of the control ROM arrangement area 192 to the terminals. May be configured to make it easier to check the connection status by connecting. Further, CE # and SETET # may have the same configuration. However, in the embodiment, CE #, which is a chip select input terminal for inputting a chip select signal, and RESET #, which is a reset terminal for inputting a reset signal, are liable to be subject to problems and problems, and therefore are wired. A wiring pattern is connected to each terminal from within the control ROM arrangement area 192 so that the pattern is not tampered with.

As shown in FIG. 26, the composite chip is similar to the terminal of the composite chip linearly arranged in the Y-axis direction (and / or the X-axis direction) with respect to the terminal of the composite chip 104 and the via in the composite chip arrangement area 191. By arranging the vias in the arrangement area 191 so as to be linearly arranged in the Y-axis direction (and / or the X-axis direction), it is easy to check the arrangement of each terminal and the arrangement of the vias, and a space is provided. Vias can be arranged in an aligned manner within the composite chip arrangement area 191 with a small margin.

Further, as shown in FIG. 26, the terminals of the composite chip 104 linearly arranged in the Y-axis direction (and / or the X-axis direction) and the vias linearly arranged in the Y-axis direction (and / or the X-axis direction). Are preferably arranged so that they do not overlap in the Y-axis direction (and / or the X-axis direction). With such a configuration, vias can be arranged while avoiding terminals located next to each other or in the vicinity, for example, so that a wiring pattern from the vias can be easily arranged.

Further, as shown in FIG. 26, the via in the composite chip placement area 191 is an outer terminal (eg, HAD18, HAD14, HAD10, HAD6, HAD21, HDT12, HDT7, HDT4) arranged near the outer periphery of the composite chip placement area 191. , HDT0) and / or terminals arranged inside it (eg, HAD17, HAD13, HAD9, HAD5, HAD22, HDT13, HDT8, HDT5, HDT1), respectively, overlapping in the X-axis direction (and / or Y-axis direction). It is desirable to arrange them in a position where they do not become. As a result, the vias can be arranged while avoiding the outer terminals and / or the terminals arranged inside the outer terminals, so that the wiring pattern from the vias can be easily arranged. That is, if the vias are arranged in the first wiring layer L1 while avoiding the outer terminals and / or the terminals arranged inside the outer terminals, the outer terminals and / or the inner sides thereof are obtained when the wiring patterns are drawn from the vias in different wiring layers. It is possible to draw out the wiring pattern linearly in the X-axis direction (and / or the Y-axis direction) without worrying about the terminals arranged in.

Further, the outer terminals (eg, HAD18, HAD14, HAD10, HAD6, HAD21, HDT12, HDT7, HDT4, HDT0) arranged near the outer periphery of the composite chip arrangement area 191 shown in FIG. The first specific via (example: v18- For v24) and the second specific via (eg v11 to v17) located inside the composite chip 104 than the first specific via, avoid the outer terminals and / or the terminals located inside. As a result, the first wiring layer L1 is arranged so as to overlap each other in the X-axis direction. In this case, the second specific via located inside the composite chip 104 than the first specific via is, for example, in a wiring layer different from the first wiring layer L1 as shown in FIG. 31. 1 The wiring pattern may be configured to avoid a specific via. In this way, the plurality of wiring layers are used and arranged inside the composite chip arrangement area 191 so as to avoid the outer terminals arranged near the outer periphery of the composite chip arrangement area 191 and / or the terminals arranged inside the outer terminals. The first specific via and the second specific via may be provided, and a wiring pattern drawn from the second specific via may be provided so as to avoid the first specific via. As a result, it is possible to efficiently draw out the wiring pattern from the inside of the composite chip arrangement area 191 where the wiring space is relatively small to the outside of the composite chip arrangement area 191. Further, here, a specific terminal and a specific via are shown as an example based on FIGS. 26 and 31, but the present invention is not limited to this, and other terminals and vias may have the same configuration. For example, in FIG. 26, one edge side of the composite chip 104 is taken as an example, but the same configuration may be made on the other edge side. Further, when the first wiring layer L1 in the composite chip arrangement area 191 has a relatively large wiring space, the first specific via is set in the X-axis direction (and / or the Y-axis direction) in the first wiring layer L1. It may be configured to install a second specific via to avoid it.

As described above, the vias in the composite chip arrangement region 191 shown in FIG. 26 are arranged so as to be linearly arranged in the Y-axis direction (and / or the X-axis direction), and as a matter of course, they are shown in FIG. Even in different wiring layers, the vias in the composite chip arrangement region 191 are arranged linearly in the Y-axis direction (and / or the X-axis direction). Here, the first via (example: v21), the second via (example: v14) located inside the composite chip placement area 191 from the first via, and the inside of the composite chip placement area 191 from the second via. There is a third via (eg v6) located in, the first via advances out of the composite chip placement area 191 by a wiring pattern drawn linearly in the X-axis direction, and the second via is the first via. The first wiring pattern drawn linearly in the X-axis direction through the wiring pattern drawn out for the first distance in the direction avoiding the above and the control ROM 105 to be connected are linearly drawn out in the direction in which they are located. The wiring pattern advances to the outside of the composite chip arrangement area 191 by the two wiring patterns, and the third via is drawn out by the first distance in the direction of avoiding the first via and / or the second via (avoid the first via from the second via). A wiring pattern drawn linearly in the Y-axis direction (the same direction as the wiring pattern drawn out by the first distance in the direction) and a wiring pattern drawn out linearly in the Y-axis direction (the wiring pattern length up to this point is the first in the direction of avoiding the first via from the second via). The first wiring pattern drawn linearly in the X-axis direction and the control ROM 105 to be connected are drawn linearly in the direction in which the control ROM 105 is located. It is configured to travel out of the composite chip arrangement area 191 according to the wiring pattern. In this way, when the first via, the second via, and the third via are arranged in this order toward the inside of the composite chip arrangement area 191, the via located on the outside is first placed in the composite chip arrangement area 191. The wiring pattern may be provided so as to avoid it. As a result, the wiring space in the composite chip arrangement area 191 can be effectively utilized.

Further, in the above-mentioned example, the relationship between the first via, the second via, and the third via is shown by taking a specific via as an example, but the same configuration can be applied to other vias shown. desirable. As described above, by making the same configuration at a plurality of locations, it is possible to effectively utilize the wiring space in the composite chip arrangement area 191 as compared with the case where the configuration is performed at a single location. Further, the above-mentioned example shows that the wiring layer is different from the first wiring layer L1 in the composite chip arrangement area 191. However, the present invention is not limited to this, and the wiring layer L1 is configured to be used. You may. However, since a plurality of terminals of the composite chip 104 are arranged in the first wiring layer L1, it is assumed that there is relatively little margin in the wiring space. Is desirable.

Further, in the example of FIG. 26, like the terminals of the composite chip 104 linearly arranged in the Y-axis direction from HAD1 to HAD0, the drawing directions of the wiring patterns drawn from the respective terminals are different (example: HAD1 and HAD0 are different). The vias connected to each terminal are arranged linearly in the Y-axis direction in the −XY direction, HAD8, HAD3, HAD15, HAD20 in the + XY direction, and HAD11 in the −X + Y direction). In this way, the vias connected by the wiring pattern to the terminals of the composite chip 104 linearly arranged in the Y-axis direction (and / or the X-axis direction) are linearly arranged in the Y-axis direction (and / or the X-axis direction). It is not necessary to arrange them so that they are arranged in a line, and the vias connected by wiring patterns to the terminals of the composite chips 104 that are not related to each other and are linearly arranged in the Y-axis direction (and / or the X-axis direction) are connected in the Y-axis direction. (And / or in the X-axis direction) may be arranged so as to be aligned in a straight line. Even with this configuration, as a result, the terminal arrangement and via arrangement of the composite chip 104 can be arranged so as to be linearly arranged in the Y-axis direction (and / or the X-axis direction). It is possible to achieve the same effect as.

In the example of FIG. 26, wiring patterns are drawn out in substantially the same direction from a plurality of terminals (eg, HDT6, HDT10, HDT15, HAD24) of the composite chip 104 arranged in a straight line in the Y-axis direction, and the composite chip arrangement is performed respectively. Vias (eg, v17 to v14) are arranged so as to be linearly arranged in the Y-axis direction in the region 191. Then, as shown in FIG. 31, the wiring pattern is led from the first wiring layer L1 to the fourth wiring layer L4 through these vias, and the wiring pattern is drawn out from the fourth wiring layer L4. In this way, with respect to the terminals of the composite chip 104 having a common conduction destination (here, the fourth wiring layer L4) from the via, the wiring pattern may be drawn out from each terminal in the same direction. Similarly, the vias connected to each terminal may be arranged so as to be linearly arranged in the Y-axis direction within the composite chip arrangement area 191. Further, in this case, as shown in FIG. 26, the address output terminal for outputting the address information and the data input / output terminal for inputting / outputting the data information may have the above-described configuration, or the address. The above configuration may be made only with the address output terminal for outputting information or only the data input / output terminal for inputting / outputting data information. With such a configuration, it becomes easy to confirm the arrangement of each terminal, the arrangement of vias, and the wiring pattern serving as the connection path. Further, not only the terminals of the composite chip 104 having the common conduction destination (here, the fourth wiring layer L4) from the via, but also the connection connected from the via to the connection destination (example: control ROM 105) through the wiring pattern. The terminals of the composite chip 104 having the same type may be configured as described above. In addition, the wiring path (which wiring layer passes through, what kind of wiring pattern is used for wiring, etc.) from the via to the connection destination (example: control ROM 105) through the wiring pattern is almost common. The terminals of the composite chip 104 may have the above-described configuration. With such a configuration, it becomes easy to confirm the arrangement of each terminal, the arrangement of vias, and the wiring pattern serving as the connection path.

In the above description, "the arrangement of vias v60 to v85 and v87 to v107 (specific interlayer conduction portion) in the control ROM arrangement area 192 is approximated to the arrangement of the corresponding terminals (specific second terminal) on the control ROM 105 side. The word "approximate" is used, such as "is.", But this "approximate" may mean that all the terminals and vias that are in a connection relationship have the same arrangement, or that they are in a connection relationship. The arrangement may be the same for some terminals and vias. Further, when there are a plurality of terminals having a connection relationship (eg, a terminal of the control ROM and a connector terminal for a predetermined via), the arrangement of one or both terminals may be the same. Further, when there are a plurality of connection destinations, there is no problem if they are the same electronic component, but if they are different electronic components, there is a high possibility that the arrangement of both terminals is different. In that case, it is practically impossible to have a via array that exactly matches the array of both terminals. Therefore, in order to match the arrangement of both terminals as much as possible, the arrangement may be partially common. For example, a part of the terminals of the first connection destination (a part of the terminals of the control ROM 105) and a part of the terminals of the second connection destination (a part of the terminals of the connector), respectively. There may be a via array corresponding to a part of the array of 1st via array that does not correspond to a part of the array of terminals (a part of the array of the terminals of the connector) and an array of a part of the terminals of the first connection destination (an array of a part of the terminals of the control ROM) However, it may be configured to include a second via array corresponding to a part of the arrangement of the terminals of the second connection destination (a part of the arrangement of the terminals of the connector). Then, it is assumed that such an array of vias also has the above-mentioned "approximate" relationship.

Regarding the assembly of boards, "assembly" may mean that one control board is completed by combining a plurality of boards, or a state in which a harness is inserted into a connector for one board to make it conductive. It may also be connected to another substrate via a harness. Further, the present invention is not limited to a plurality of substrates or a single substrate, and various electronic components necessary for operation may be attached to the substrate.

The contents of the above examples can be combined in any way, and by combining them, the wiring efficiency can be improved more effectively, and the board configuration can be made resistant to noise and fraudulent activities.

In addition, all the terminal arrangements, wiring patterns, installation positions of electronic components, etc. shown in the figure were constructed in search of the optimum solution, and as a result of combining all the configurations shown in the figure, more suitable wiring efficiency was obtained. , The substrate can be reduced in size and noise can be reduced.

Further, the present invention can be similarly implemented in various ball game machines such as arrange ball machines and sparrow ball game machines, as well as in game machines other than ball game machines such as slot machines.

98 LCD control board (board)
104 Composite chip (chip)
105 Control ROM (ROM)
191 Composite chip placement area (first placement area)
192 Control ROM placement area (second placement area)
v0 to via (interlayer conduction part)
L1
~ L6 1st to 6th wiring layers

Claims (1)

A substrate having a plurality of wiring layers and an interlayer conduction portion in the plate thickness direction for conducting the plurality of wiring layers with each other is provided.
A game in which a first arrangement area in which a chip containing a CPU circuit is arranged and a second arrangement area in which a ROM connected to the chip is arranged are provided in the first wiring layer of the plurality of wiring layers. In the machine
A specific interlayer conductive portion among the interlayer conductive portions is arranged in the second arrangement region, and the interlayer conductive portion is arranged.
The plurality of wiring lines connecting the chip and the ROM include a plurality of specific wiring lines wired via the specific interlayer conduction portion.
The plurality of specific wiring paths include a first wiring path for transmitting address information or data information and a second wiring path for transmitting chip select information.
A gaming machine characterized in that the first wiring path and the second wiring path are connected to the specific interlayer conductive portion from the chip side by the wiring layers different from each other.

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