JP2021153207A - Electronic device - Google Patents

Abstract

To provide an electronic device excellent in signal transmission between chips and in stable supply of power to the chips.SOLUTION: Wiring layers are provided between a first region of a first chip and a third region of a second chip, between a second region of the first chip and a fifth region of the third chip, between a first terminal and a fourth region of the second chip, and between a second terminal and a sixth region of a third chip. A fourth conductive member is provided between the first region of the first chip and a third region of the second chip and connects a first conductive member of the first chip and the second conductive member of the second chip. A fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip and connects the first conductive member of the first chip and a third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.SELECTED DRAWING: Figure 1

Description

Embodiments of the present invention relate to electronic devices.

The fan-out wiring layer plays a role of connecting signal lines between a plurality of chips and a role of supplying power to the chips.

Japanese Patent No. 5466203 Japanese Unexamined Patent Publication No. 2015-188052

An embodiment of the present invention provides an electronic device excellent in signal transmission between chips and stable power supply performance to chips.

According to an embodiment of the present invention, the electronic device includes a first chip, a second chip, a third chip, a first terminal which is a metal pad or a metal bump, and a second terminal which is a metal pad or a metal bump. And a wiring layer. The first chip includes a first conductive member, a first region, and a second region. The second chip includes a second conductive member, a third region, and a fourth region. The third chip includes a third conductive member, a fifth region, and a sixth region. The wiring layer is between the first region of the first chip and the third region of the second chip, and between the second region of the first chip and the fifth region of the third chip. , The first terminal and the fourth region of the second chip, and between the second terminal and the sixth region of the third chip. The wiring layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip, and the first conductive member of the first chip and the second chip of the second chip. Connect to the second conductive member. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip, and the first conductive member of the first chip and the third chip of the third chip. Connect with the third conductive member. The first chip is provided between the first terminal and the second terminal. The second chip and the third chip are provided on one surface of the wiring layer, and the first chip, the first terminal, and the second terminal are provided on the other surface of the wiring layer. There is.

(A) is a schematic cross-sectional view illustrating the electronic device according to the first embodiment, and (b) and (c) are schematic enlarged cross-sectional views of a first chip in the electronic device according to the first embodiment. , (D) are schematic views showing the connection relationship between the first chip, the second chip, and the third chip in the electronic device according to the first embodiment. (A) is a schematic plan view showing an arrangement example of the first chip, the second chip, and the third chip in the electronic device which concerns on 1st Embodiment, and (b) is a schematic plan view which shows the arrangement example of 3rd chip, and (b) is the electronic device which concerns on 1st Embodiment. It is a schematic plan view of the 2nd chip, the 3rd chip, and a resin part. It is a schematic cross-sectional view which shows the example of the manufacturing method of the electronic device which concerns on 1st Embodiment. It is a schematic cross-sectional view which shows the example of the manufacturing method of the electronic device which concerns on 1st Embodiment. It is a schematic cross-sectional view which shows the example of the manufacturing method of the electronic device which concerns on 1st Embodiment. It is a schematic cross-sectional view which shows the example of the manufacturing method of the electronic device which concerns on 1st Embodiment. It is a schematic cross-sectional view which illustrates the electronic device which concerns on 2nd Embodiment. (A) and (b) are schematic diagrams showing the connection relationship between the first chip, the second chip, and the third chip in the electronic device according to the second embodiment. It is a schematic diagram which shows the connection relationship of the 1st chip, the 2nd chip, and the 3rd chip in the electronic device which concerns on 3rd Embodiment. It is a schematic cross-sectional view which illustrates the electronic device which concerns on 4th Embodiment. (A) is a schematic cross-sectional view illustrating the electronic device according to the fifth embodiment, and (b) is a schematic cross-sectional view showing another example of the electronic device according to the fifth embodiment. It is a schematic plan view which shows the arrangement example of the 1st chip and the 2nd chip in the electronic device which concerns on 5th Embodiment. It is a schematic cross-sectional view which illustrates the electronic device which concerns on 6th Embodiment. It is a schematic diagram which shows the connection relationship between the 1st chip and the 2nd chip in the electronic device which concerns on 6th Embodiment. It is a schematic plan view which shows the structure of the 1st chip in the electronic device which concerns on 6th Embodiment. (A) is a schematic cross-sectional view showing the connection relationship between the first chip, the second chip, and the third chip in the electronic device according to the seventh embodiment, and (b) is the electronic device according to the eighth embodiment. It is a schematic cross-sectional view which shows the connection relationship of the 1st chip and the 2nd chip in the above. It is a schematic cross-sectional view which shows the modification of the electronic device shown in FIG. 1 (a). It is a schematic cross-sectional view which shows the modification of the electronic device shown in FIG. 7. It is a schematic cross-sectional view which shows the modification of the electronic device shown in FIG. It is a schematic cross-sectional view which shows the modification of the electronic device shown in FIG. It is a schematic cross-sectional view of the electronic device which concerns on 9th Embodiment. It is a schematic diagram which shows the arrangement and connection of the 1st chip, the 2nd chip, the 3rd chip, and the wiring layer in 2nd Embodiment. It is a schematic plan view of the electronic device shown in FIG. It is a schematic diagram in which the position of the 2nd chip and the position of the 3rd chip in FIG. 23 are exchanged. It is a schematic plan view which shows the application example of the electronic device of 2nd Embodiment to a neural network. It is explanatory drawing of the neural network. It is a schematic diagram which shows the application example of the electronic device of 2nd Embodiment to a neural network. It is a schematic plan view which shows the full grid tile structure of the 1st chip, the 2nd chip, and the 3rd chip in the electronic device of 2nd Embodiment. FIG. 8 is a schematic plan view showing an example of application of the embodiment shown in FIG. 28 to a neural network. It is a schematic cross-sectional view of an example of the 3rd chip of embodiment.

Hereinafter, each embodiment of the present invention will be described with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between the parts, etc. are not always the same as the actual ones. Even if the same part is represented, the dimensions and ratios of each may be represented differently depending on the drawing.
In the specification of the present application and each figure, the same elements as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and detailed description thereof may be omitted.
In the following embodiments, the electronic device is, for example, a semiconductor device.

(First Embodiment)
FIG. 1A is a schematic cross-sectional view illustrating the electronic device 1 according to the first embodiment.
1B and 1C are schematic enlarged cross-sectional views of the first chip 10 in the electronic device 1.
FIG. 1D is a schematic diagram showing a connection relationship between the first chip 10, the second chip 20, and the third chip 30 in the electronic device 1.
FIG. 2A is a schematic plan view showing an arrangement example of the first chip 10, the second chip 20, and the third chip 30 in the electronic device 1.
FIG. 2B is a schematic plan view of the second chip 20, the third chip 30, and the resin portion 51 in the electronic device 1.

As shown in FIG. 1A, a plurality of electronic devices 1 according to the first embodiment include a wiring layer 40, a first chip 10, a second chip 20, a third chip 30, and a resin portion 51. First terminal 81 and a plurality of second terminals 82 are included.

The first chip 10 includes a first region 10a and a second region 10b. The second chip 20 includes a third region 20a and a fourth region 20b. The third chip 30 includes a fifth region 30a and a sixth region 30b.

The direction from the first region 10a of the first chip 10 to the third region 20a of the second chip 20 is along the first direction. The direction from the second region 10b of the first chip 10 to the fifth region 30a of the third chip 30 is along the first direction.

The first direction is the Z-axis direction. One direction perpendicular to the Z-axis direction is defined as the X-axis direction. The direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction.

The wiring layer 40 is, for example, along the XY plane.

The second direction from the second chip 20 to the third chip 30 intersects the first direction. In this example, the second direction is along the X-axis direction.

The direction from the first region 10a of the first chip 10 to the fourth region 20b of the second chip 20 intersects the first direction and the second direction. The direction from the second region 10b of the first chip 10 to the sixth region 30b of the third chip 30 intersects the first direction and the second direction.

The wiring layer 40 is between the first region 10a of the first chip 10 and the third region 20a of the second chip 20, and between the second region 10b of the first chip 10 and the fifth region 30a of the third chip 30. , It is provided between the first terminal 81 and the fourth region 20b of the second chip 20, and between the second terminal 82 and the sixth region 30b of the third chip 30.

As shown in FIG. 1B, the first chip 10 includes a substrate 12 and a wiring layer 14. The thickness of the substrate 12 along the Z-axis direction is thicker than the thickness of the wiring layer 14 along the Z-axis direction.

The substrate 12 is, for example, a silicon substrate or a glass substrate. The wiring layer 14 is, for example, a wiring layer formed by a damascene method or a semi-additive process. The wiring layer 14 includes an insulating layer 13 and a first conductive member 11. When the first chip 10 is a bridge chip that does not include an element and has only a function of wiring, a high resistance silicon substrate can be used as the substrate 12. The specific resistance of this high resistivity silicon substrate is, for example, 10 Ωcm or more.

The first conductive member 11 is, for example, a metal member. The first conductive member 11 includes a plurality of electrode terminals 11a and a conductive layer 11b connected to the electrode terminals 11a. The conductive layer 11b is provided between the electrode terminal 11a and the substrate 12.

Alternatively, as shown in FIG. 1 (c), the first chip 10 includes only the wiring layer 14 including the first conductive member 11, and does not include the substrate 12. After forming the wiring layer 14 on the substrate 12, the substrate 12 can be removed.

As shown in FIG. 1A, an insulating portion 55 is provided between the first chip 10 and the wiring layer 40. The insulating portion 55 is made of, for example, a resin material or an inorganic material. The insulating portion 55 covers the first conductive member 11. For example, after connecting the first conductive member 11 to the wiring layer 40, the insulating portion 55 can be injected. Alternatively, a manufacturing method may be used in which the insulating portion 55 is formed in advance in a region including the periphery of the first conductive member 11 and the insulating portion 55 is connected to the wiring layer 40 at the same time as the first conductive member 11.

As shown in FIG. 1A, the second chip 20 includes a second conductive member 21. The second conductive member 21 is, for example, a metal member. The second conductive member 21 includes a first signal terminal 21a, a first power supply terminal 21b, and a conductive layer (not shown) connected to the first signal terminal 21a and the first power supply terminal 21b. The second chip 20 includes, for example, a logic element. Logic elements are mainly used for functions related to information calculation and control, for example.

As shown in FIG. 1A, the third chip 30 includes a third conductive member 31. The third conductive member 31 is, for example, a metal member. The third conductive member 31 includes a second signal terminal 31a, a second power supply terminal 31b, and a conductive layer (not shown) connected to the second signal terminal 31a and the second power supply terminal 31b. The third chip 30 includes, for example, a memory element. The memory element is mainly used for a function related to information storage, for example.

The wiring layer 40 includes an insulating layer 45, a fourth conductive member 41, a fifth conductive member 42, a sixth conductive member 43, and a seventh conductive member 44.

The insulating layer 45 is, for example, a resin layer. The insulating layer 45 is provided between the fourth conductive member 41, the fifth conductive member 42, the sixth conductive member 43, and the seventh conductive member 44, respectively. The insulating layer 45 insulates and separates the fourth conductive member 41, the fifth conductive member 42, the sixth conductive member 43, and the seventh conductive member 44, respectively. The insulating layer 45 may be a layer of an inorganic insulating material.

The fourth conductive member 41 is provided between the first region 10a of the first chip 10 and the third region 20a of the second chip 20, and is the first conductive member 11 of the first chip 10 and the second chip 20. 1 It is connected to the signal terminal 21a. The fourth conductive member 41 is, for example, a metal via extending along the Z-axis direction. By arranging the plurality of fourth conductive members 41 in an array in the XY plane, a large number of chip-to-chip wiring connections are possible.

The fifth conductive member 42 is provided between the second region 10b of the first chip 10 and the fifth region 30a of the third chip 30, and is the first conductive member 11 of the first chip 10 and the third chip 30. 2 It is connected to the signal terminal 31a. The fifth conductive member 42 is, for example, a metal via extending along the Z-axis direction. By arranging the plurality of fifth conductive members 42 in an array in the XY plane, a large number of chip-to-chip wiring connections are possible.

The sixth conductive member 43 is provided between the first terminal 81 and the fourth region 20b of the second chip 20, and connects the first power supply terminal 21b and the first terminal 81 of the second chip 20. ..

The seventh conductive member 44 is provided between the second terminal 82 and the sixth region 30b of the third chip 30, and connects the second power supply terminal 31b and the second terminal 82 of the third chip 30. ..

The sixth conductive member 43 and the seventh conductive member 44 are, for example, metal wiring. The first terminal 81 and the second terminal 82 are external terminals for connecting the electronic device 1 to an external circuit. The first terminal 81 and the second terminal 82 are, for example, solder balls. The first terminal 81 and the second terminal 82 may be metal pads or metal bumps.

The first chip 10 is provided between the first terminal 81 and the second terminal 82. The direction from the first terminal 81 toward the first chip 10 is along the X-axis direction. The direction from the second terminal 82 to the first chip 10 is along the X-axis direction.

The resin portion 51 covers at least a part of the side surface of the second chip 20 and the third chip 30. This side surface intersects the XY plane. In the example shown in FIG. 1A, the surfaces of the second chip 20 and the third chip 30 opposite to the wiring layer 40 are also covered with the resin portion 51, but are opposite to the wiring layer 40. It is optional to expose the surface from the resin portion 51.

As shown in FIG. 1A, the resin portion 51 includes a first resin region 51a, a second resin region 51b, and a third resin region 51c. As shown in FIG. 2B, the resin portion 51 further includes a fourth resin region 51d and a fifth resin region 51e. The first resin region 51a to the fifth resin region 51e are continuous with each other.

In the example shown in FIG. 1A, the resin portion 51 is also arranged in the peripheral portion of the second conductive member 21 and the peripheral portion of the third conductive member 31, but the peripheral portion of the second conductive member 21 The peripheral portion of the third conductive member 31 does not have to be the resin portion 51, and may be, for example, a different insulating material.

The second chip 20 is provided between the first resin region 51a and the third resin region 51c. The direction from the first resin region 51a to the third resin region 51c is along the X-axis direction. The third chip 30 is provided between the third resin region 51c and the second resin region 51b. The third resin region 51c is provided between the second chip 20 and the third chip 30. The direction from the third resin region 51c to the second resin region 51b is along the X-axis direction.

The second chip 20 is provided between the fourth resin region 51d and the fifth resin region 51e. The third chip 30 is provided between the fourth resin region 51d and the fifth resin region 51e. The direction from the fourth resin region 51d to the fifth resin region 51e is along the Y-axis direction.

A wiring layer 40 is also provided between the first terminal 81 and the first resin region 51a, and between the second terminal 82 and the second resin region 51b.

The electronic device 1 according to the first embodiment further includes a fourth chip 70, an eighth conductive member 52, a ninth conductive member 53, and a semiconductor package device 60.

The fourth chip 70 includes, for example, an IPD (Integrated Passive Device) or a passive element. Passive elements include, for example, discrete components such as capacitors, inductors, and resistor elements. The fourth chip 70 is connected to, for example, the sixth conductive member 43.

A wiring layer 40 is provided between the fourth chip 70 and the fourth region 20b of the second chip 20. The direction from the fourth chip 70 to the second chip 20 is along the Z-axis direction.

The fourth chip 70 is provided between the first terminal 81 and the first chip 10. The direction from the fourth chip 70 to the first chip 10 is along the X-axis direction.

The eighth conductive member 52 is, for example, a columnar metal via extending in the Z-axis direction. The ninth conductive member 53 is, for example, a solder ball.

The semiconductor package device 60 includes, for example, a DRAM (Dynamic Random Access Memory) element, an NVM (Non Volatile Memory) typified by a flash memory, and the like.

An eighth conductive member 52, a ninth conductive member 53, a second chip 20, a third chip 30, and a resin portion 51 are provided between the semiconductor package device 60 and the wiring layer 40.

The ninth conductive member 53 is provided between the eighth conductive member 52 and the semiconductor package device 60, and is connected to the eighth conductive member 52 and the semiconductor package device 60.

The eighth conductive member 52 is provided between the wiring layer 40 and the ninth conductive member 53. The eighth conductive member 52 is connected to the ninth conductive member 53, the sixth conductive member 43 of the wiring layer 40, and the seventh conductive member 44.

As shown in FIGS. 1A and 2, the length of the first chip 10 along the X-axis direction is the length of the second chip 20 along the X-axis direction and the length of the third chip 30 along the X-axis. Shorter than the length along the direction.

The first conductive member 11 of the first chip 10 is electrically connected to the first signal terminal 21a of the second chip 20 through the fourth conductive member 41. The first conductive member 11 of the first chip 10 is electrically connected to the second signal terminal 31a of the third chip 30 through the fifth conductive member 42. Therefore, the first signal terminal 21a of the second chip 20 passes through the fourth conductive member 41, the first conductive member 11 of the first chip 10, and the fifth conductive member 42 with the second signal terminal 31a of the third chip 30. It is electrically connected.

Power is supplied to the first power supply terminal 21b of the second chip 20 through the first terminal 81 and the sixth conductive member 43, and is supplied to the second power supply terminal of the third chip 30 through the second terminal 82 and the seventh conductive member 44. It is supplied to 31b.

The fourth conductive member 41 and the sixth conductive member 43 are not connected to each other, and the fifth conductive member 42 and the seventh conductive member 44 are not connected to each other. Therefore, no power is supplied to the first chip 10, and it simply functions as a wiring member that connects the second chip 20 and the third chip 30. The first chip 10 does not include an active element such as a transistor and a passive element.

According to the electronic device 1 according to the first embodiment, the second chip 20 and the third chip 30 are connected through the first chip 10. High-density fine wiring can be formed on the first chip 10 at low cost by, for example, a wafer process. The wiring layer 40 on which the second chip 20 and the third chip 30 are mounted does not need to form high-density fine wiring for connecting between the chips, and is a rough line that can be formed at a large-area panel level. Only wiring with and space can be used. This not only enables cost reduction, but also reduces the power supply impedance to the second chip 20 and the third chip 30 through the sixth conductive member 43 and the seventh conductive member 44, which contributes to the improvement of the power supply performance.

Further, the first chip 10 can have a structure of only wiring without including active elements and passive elements, and the cost can be significantly reduced. Further, since the element is not included, the chip size of the first chip 10 can be reduced, and a wide area for arranging the first terminal 81 and the second terminal 82 can be secured. This makes it possible to reduce the distance between the first terminal 81 and the first power supply terminal 21b of the second chip 20, and the distance between the second terminal 82 and the second power supply terminal 31b of the third chip 30. , The power supply impedance of the second chip 20 and the third chip 30 can be lowered. This reduction in power supply impedance suppresses fluctuations in power supply voltage and enables stable operation.

The third chip 30 includes, for example, a cache memory as a memory element. The semiconductor package device 60 can include, for example, a DRAM as a main memory having a storage capacity larger than that of a cache memory, and an NVM (Non Volatile Memory) as a storage memory represented by a flash memory or the like. The second chip 20 can also have a function of controlling the third chip 30 and the semiconductor package device 60.

According to such an embodiment, for example, a large-capacity cache memory can be incorporated as a system in one package as compared with a configuration in which a cache memory is integrated and built in the second chip 20, and system performance can be improved. Moreover, it is possible to reduce the cost of the inter-chip connection wiring and realize high power supply performance to each chip.

3 (a) to 6 (d) are schematic cross-sectional views showing an example of a manufacturing method of the electronic device 1 according to the first embodiment.

As shown in FIG. 3A, the wiring layer 40 is formed on the support 100. The wiring layer 40 includes the above-mentioned insulating layer 45, the fourth conductive member 41, the fifth conductive member 42, the sixth conductive member 43, and the seventh conductive member 44.

6 (a) to 6 (d) show, for example, a step of forming the fourth conductive member 41. Note that in FIGS. 6 (b) to 6 (d), the support 100 is not shown.

Further, a release layer may be arranged between the wiring layer 40 and the support 100, but this is omitted. The release layer is a layered material for imparting a function of separating the wiring layer 40 and the support 100 by applying mechanical stress or optical energy (laser irradiation or the like).

After forming the pad 92 on the support 100, the insulating layer 91 covering the pad 92 is formed. A hole 91a reaching the pad 92 is formed in the insulating layer 91.

As shown in FIG. 6B, a via 93 is formed in the hole 91a. The end of the via 93 is also formed on the insulating layer 91. At the same time as the via 93, the conductive layer 94 included in the sixth conductive member 43 and the conductive layer 95 included in the seventh conductive member 44 are formed on the insulating layer 91.

As shown in FIG. 6C, the insulating layer 96 is further laminated on the insulating layer 91. A hole 96a reaching the end of the via 93 is formed in the insulating layer 96. A via 97 is formed in the hole 96a as shown in FIG. 6 (d). After that, an insulating layer may be further formed, a hole may be formed in the insulating layer, and a via may be formed in the hole.

The step of forming the insulating layer, the step of forming a hole in the insulating layer, and the step of forming a via in the hole are repeated a plurality of times, and include a plurality of vias 93 and 97 interconnected in the Z-axis direction. A fourth conductive member 41 having a stacked tovia structure is formed. Similarly, the fifth conductive member 42 having a stack to via structure is also formed in the same manner as the fourth conductive member 41. The via 93 and the via 97 are not limited to being aligned linearly along the Z-axis direction, and as shown in FIG. 6E, the via 93 and the via 97 are aligned in the X-axis direction (or the Y-axis direction). The position may be misaligned.

After forming the wiring layer 40, as shown in FIG. 3B, the eighth conductive member 52 is fixed to the wiring layer 40. Further, as shown in FIG. 4A, the second chip 20 and the third chip 30 are fixed to the wiring layer 40. The second chip 20 and the third chip 30 may be fixed to the wiring layer 40 before the eighth conductive member 52.

The eighth conductive member 52, the second chip 20, and the third chip 30 are covered with the resin portion 51 as shown in FIG. 4 (b). The resin portion 51 is laminated on the wiring layer 40.

After forming the resin portion 51, the support 100 is removed. The support 100 may be removed by utilizing the function of the release layer described above, or the support 100 may be removed by a method such as grinding or etching. By these processes, the surface of the wiring layer 40 facing the support 100 is exposed as shown in FIG. 5A.

As shown in FIG. 5B, the first chip 10 and the fourth chip 70 are fixed to the exposed surface of the wiring layer 40. After fixing the first chip 10 to the wiring layer 40, the substrate 12 of the first chip 10 shown in FIG. 1B may be removed.

After that, the first terminal 81 and the second terminal 82 shown in FIG. 1 are fixed to the wiring layer 40, and the semiconductor package device 60 is further laminated. The order in which the semiconductor package devices 60 are laminated may be after the first terminal 81 and the second terminal 82 are fixed.

(Second Embodiment)
FIG. 7 is a schematic cross-sectional view illustrating the electronic device 2 according to the second embodiment.
FIG. 8A is a schematic view showing the connection relationship between the first chip 110, the second chip 20, and the third chip 30 in the electronic device 2. FIG. 8B is a schematic view showing the connection relationship between the first chip 110, the second chip 20, and the third chip 30 in a plane.

As shown in FIG. 7, the electronic device 2 according to the second embodiment includes a wiring layer 40, a first chip 110, a second chip 20, a third chip 30, a resin portion 51, and a plurality of first chips. A terminal 81 and a plurality of second terminals 82 are included.

The first chip 110 includes a first conductive member 111, a first region 110a, and a second region 110b. The direction from the first region 110a of the first chip 110 to the third region 20a of the second chip 20 is along the first direction. The direction from the second region 110b of the first chip 110 to the fifth region 30a of the third chip 30 is along the first direction.

The first region 110a of the first chip 110 is a connection region facing the third region 20a of the second chip 20 and being connected to the third region 20a of the second chip 20. The third region 20a of the second chip 20 is an region facing the first region 110a of the first chip 110 and being connected to the first region 110a of the first chip 110. The second region 110b of the first chip 110 is a connection region facing the fifth region 30a of the third chip 30 and being connected to the fifth region 30a of the third chip 30. The fifth region 30a of the third chip 30 is a connection region facing the second region 110b of the first chip 110 and being connected to the second region 110b of the first chip 110.

The direction from the first region 110a of the first chip 110 to the fourth region 20b of the second chip 20 intersects the first direction and the second direction. The direction from the second region 110b of the first chip 110 to the sixth region 30b of the third chip 30 intersects the first direction and the second direction.

The wiring layer 40 is between the first region 110a of the first chip 110 and the third region 20a of the second chip 20, and between the second region 110b of the first chip 110 and the fifth region 30a of the third chip 30. , It is provided between the first terminal 81 and the fourth region 20b of the second chip 20, and between the second terminal 82 and the sixth region 30b of the third chip 30.

The fourth conductive member 41 of the wiring layer 40 is provided between the first region 110a of the first chip 110 and the third region 20a of the second chip 20, and is provided between the first conductive member 111 and the second of the first chip 110. It is connected to the first signal terminal 21a of the chip 20. By arranging the plurality of fourth conductive members 41 in an array in the XY plane, a large number of chip-to-chip wiring connections are possible.

The fifth conductive member 42 of the wiring layer 40 is provided between the second region 110b of the first chip 110 and the fifth region 30a of the third chip 30, and is provided between the first conductive member 111 and the third of the first chip 110. It is connected to the fourth signal terminal 31a of the chip 30. By arranging the plurality of fifth conductive members 42 in an array in the XY plane, a large number of chip-to-chip wiring connections are possible.

The first chip 110 is provided between the first terminal 81 and the second terminal 82. The direction from the first terminal 81 toward the first chip 110 is along the X-axis direction. The direction from the second terminal 82 to the first chip 110 is along the X-axis direction.

The length of the first chip 110 along the X-axis direction is shorter than the length of the second chip 20 along the X-axis direction and the length of the third chip 30 along the X-axis direction.

The first chip 110 includes a first conductive member 111 that connects between the second chip 20 and the third chip 30 in the same manner as the first chip 10 of the first embodiment. Further, the first chip 110 may include the first memory element 113 as shown in FIG. 8A. The first memory element 113 is, for example, a cache memory.

The third chip 30 includes a second memory element 115. The second memory element 115 is, for example, a main memory and may be a DRAM. When the first chip 110 includes the first memory element 113, the storage capacity of the second memory element 115 is larger than the storage capacity of the first memory element 113.

FIG. 7 shows an example in which a plurality of third chips 30 are laminated in the Z-axis direction. The operation speed of the first memory element 113 is faster than that of the second memory element 115. Various methods are used as the connection method between the plurality of third chips 30, for example, TSV (Through Silicon Via) or metal wire connection may be used. Since the third chip 30 including the second memory element 115 is provided on the opposite side of the mounting surface of the electronic device 2 to the board, it is easy to stack the plurality of third chips 30, and the second memory element 115 It is easy to increase the capacity.

The second chip 20 includes, for example, a logic element, and controls the first memory element 113 of the first chip 110 and the second memory element 115 of the third chip 30. Alternatively, the logic element of the second chip 20 may control only the second memory element 115 of the third chip 30. As used herein, "control" includes mutual data transfer between a logic element and a memory element and its control, data movement within the memory element and its control.

As shown in FIG. 8A, the first conductive member 111 of the first chip 110 includes a plurality of wirings 112 connecting the second chip 20 and the third chip 30. The wiring 112 is, for example, a metal wiring. Alternatively, the wiring 112 may be an optical wiring (or an optical waveguide). The wiring 112 functions as a bus for transferring data from the second chip 20 to the third chip 30.

As shown in FIGS. 8A and 8B, the second chip 20 includes a plurality of second signal terminals 21aa and a plurality of third signal terminals 21ab. The second signal terminal 21aa and the plurality of third signal terminals 21ab are provided in the third region 20a of the second chip 20.

The first memory element 113 includes a plurality of first signal terminals 113a. The first signal terminal 113a is provided in the first region 110a of the first chip 110 and is electrically connected to the first memory element 113.

The fourth conductive member 41 of the wiring layer 40 includes a plurality of metal vias 41a and a plurality of metal vias 41b. The metal via 41a connects the second signal terminal 21aa of the second chip 20 and the first signal terminal 113a of the first chip 110. The metal via 41b connects the third signal terminal 21ab of the second chip 20 and the wiring 112.

The third chip 30 includes a plurality of fourth signal terminals 31a. The fourth signal terminal 31a is provided in the fifth region 30a of the third chip 30, and is connected to the second memory element 115. The fourth signal terminal 31a is connected to the wiring 112 of the first chip 110.

The wiring 112 of the first chip 110 connects the third signal terminal 21ab of the second chip 20 and the fourth signal terminal 31a of the third chip 30. The wiring 112 is not connected to the sixth conductive member 43 and the seventh conductive member 44 of the wiring layer 40, which are wirings for connecting the first chip 110, the second chip 20, and the third chip 30 to the outside. .. The wiring of the wiring layer 40 is also, for example, metal wiring. Alternatively, the wiring of the wiring layer 40 may be an optical wiring (or an optical waveguide).

The connection between the second chip 20 and the first memory element 113 is a via connection by a metal via 41a without going through the wiring 112.

Power is supplied to the first chip 110 including the first memory element 113. The first conductive member 111 of the first chip 110 shown in FIG. 7 is electrically connected to the first terminal 81 through the sixth conductive member 43. Alternatively, the first conductive member 111 of the first chip 110 is electrically connected to the second terminal 82 through the seventh conductive member 44. Power can also be supplied to the first chip 110 via the second chip 20 or the third chip 30.

The wiring 112 provided on the first chip 110 is a so-called on-chip wiring formed by the semiconductor wafer process. On the other hand, the sixth conductive member 43 and the seventh conductive member 44, which are the wirings in the wiring layer 40, can be rough wirings formed at a panel level larger than that of the semiconductor wafer. That is, the minimum spacing of the wiring 112 of the first chip 110 is smaller than the minimum spacing of the wiring of the wiring layer 40.

Also in the electronic device 2 according to the second embodiment, the second chip 20 and the third chip 30 are connected through the first chip 110. High-density fine wiring can be formed on the first chip 110 at low cost by, for example, a wafer process. The wiring layer 40 on which the second chip 20 and the third chip 30 are mounted does not need to form high-density fine wiring for connecting between the chips, and has a rough line and space that can be formed at the panel level. It can be only the wiring that has. This allows for cost savings.

Further, the first chip 110 mainly serves the function of inter-chip wiring, and the chip size can be reduced. Therefore, a wide area for arranging the first terminal 81 and the second terminal 82 can be secured. This makes it possible to reduce the distance between the first terminal 81 and the first power supply terminal 21b of the second chip 20, and the distance between the second terminal 82 and the second power supply terminal 31b of the third chip 30. , The power supply impedance of the second chip 20 and the third chip 30 can be lowered. This reduction in power supply impedance suppresses fluctuations in power supply voltage and enables stable operation.

Further, according to the second embodiment, the first chip 110 may not only carry out the inter-chip connection but also have a memory function. According to such a second embodiment, it is possible to improve the system performance and increase the capacity by increasing the number of layers of the memory hierarchical structure.

(Third Embodiment)
FIG. 9 is a schematic view showing the connection relationship between the first chip 110', the second chip 20, and the third chip 30 in the electronic device according to the third embodiment.

The electronic device according to the third embodiment has a structure in which the first chip 110 is replaced with the first chip 110'in the electronic device 2 according to the second embodiment shown in FIG. 7. That is, the first chip 110'also includes the same wiring 112, the first region 110a, and the second region 110b as the first chip 110.

Further, the first chip 110'includes the first memory element 113 and the control unit 114, as shown in FIG. The first memory element 113 is, for example, a cache memory. The first chip 110'includes a plurality of first signal terminals 113a electrically connected to the first memory element 113.

The third chip 30 includes a second memory element 115, a plurality of fourth signal terminals 31a, and a plurality of sixth signal terminals 31b. The fourth signal terminal 31a and the sixth signal terminal 31b are electrically connected to the second memory element 115.

The second chip 20 includes a plurality of second signal terminals 21aa, a plurality of third signal terminals 21ab, and a plurality of fifth signal terminals 21ac.

The control unit 114 of the first chip 110'is connected to the sixth signal terminal 31b of the third chip 30 through a plurality of metal vias 42. The control unit 114 controls the second memory element 115 of the third chip 30. That is, the first chip 110'also has a function of controlling the second memory element 115 having a large capacity.

The control unit 114 of the first chip 110'is connected to the first memory element 113 through a plurality of wirings 116 in the first chip 110' and controls the first memory element 113.

Further, the control unit 114 of the first chip 110'is connected to the fifth signal terminal 21ac of the second chip 20 through the wiring 117 provided in the wiring layer 40.

Power is supplied to the first chip 110'through the first terminal 81 and the sixth conductive member 43. Alternatively, power is supplied to the first chip 110'through the second terminal 82 and the seventh conductive member 44.

According to the configuration shown in FIG. 9, the control unit 114 of the first chip 110'can control both the second memory element 115 of the third chip 30 and the first memory element 113 of the first chip 110'. .. This optimizes the data arrangement in the memory hierarchical structure without consuming the information processing time and operating energy associated with the control of both the second memory element 115 and the first memory element 113 of the logic element of the second chip 20. To enable. For example, when the first memory element 113 is a cache memory, the data required by the logic element of the second chip 20 is appropriately moved from the second memory element 115 of the third chip 30 to the first memory element 113. This can be achieved without relying on the control of the second chip 20.

(Fourth Embodiment)
FIG. 10 is a schematic cross-sectional view illustrating the electronic device 3 according to the fourth embodiment.

The electronic device 3 according to the fourth embodiment includes a wiring layer 240, a first chip 210, a second chip 220, a third chip 230, a resin portion 51, a plurality of first terminals 81, and a plurality of first terminals. Includes 2 terminals 82.

The first chip 210 includes a first optical element 211, a second optical element 212, and an optical waveguide 213. The first optical element 211 includes a first electrode terminal 211a, and the second optical element 212 includes a second electrode terminal 212a.

The first optical element 211 is, for example, a light emitting element or a light receiving element. The second optical element 212 is, for example, a light emitting element or a light receiving element. The optical waveguide 213 is provided between the first optical element 211 and the second optical element 212. The first optical element 211 and the second optical element 212 are optically coupled to the optical waveguide 213.

The second chip 220 includes a first region 220a and a second region 220b. The third chip 230 includes a third region 230a and a fourth region 230b.

The direction from the first optical element 211 of the first chip 210 toward the first region 220a of the second chip 20 is along the first direction. The direction from the second optical element 212 of the first chip 210 toward the third region 230a of the third chip 30 is along the first direction. The second direction from the second chip 220 to the third chip 230 intersects the first direction. In this example, the second direction is along the X-axis direction. The direction from the first optical element 211 to the second optical element 212 is along the second direction.

The direction from the first optical element 211 of the first chip 210 toward the second region 220b of the second chip 220 intersects the first direction and the second direction. The direction from the second optical element 212 of the first chip 210 toward the fourth region 230b of the third chip 230 intersects the first direction and the second direction.

The wiring layer 240 is formed between the first optical element 211 of the first chip 210 and the first region 220a of the second chip 220, the second optical element 212 of the first chip 210, and the third region 230a of the third chip 230. Between the first terminal 81 and the second region 220b of the second chip 220, and between the second terminal 82 and the fourth region 230b of the third chip 230.

An insulating portion 255 is provided between the first chip 210 and the wiring layer 240. The insulating portion 255 is made of, for example, a resin material or an inorganic material. The insulating portion 255 covers the first electrode terminal 211a of the first optical element 211 and the second electrode terminal 212a of the second optical element 212. For example, after connecting the first electrode terminal 211a and the second electrode terminal 212a to the wiring layer 240, the insulating portion 255 can be injected. Alternatively, the insulating portion 255 is formed in advance in a region including the periphery of the first electrode terminal 211a and the second electrode terminal 212a, and the insulating portion 255 is simultaneously provided on the wiring layer 240 at the same time as the first electrode terminal 211a and the second electrode terminal 212a. You may use the manufacturing method of connecting.

The second chip 220 includes a first conductive member 221. The first conductive member 221 is, for example, a metal member. The first conductive member 221 includes a first signal terminal 221a, a first power supply terminal 221b, and a conductive layer (not shown) connected to the first signal terminal 221a and the first power supply terminal 221b. The second chip 220 includes, for example, a logic element.

The third chip 230 includes a second conductive member 231. The second conductive member 231 is, for example, a metal member. The second conductive member 231 includes a second signal terminal 231a, a second power supply terminal 231b, and a conductive layer (not shown) connected to the second signal terminal 231a and the second power supply terminal 231b. The third chip 230 includes, for example, a memory element or a logic element.

The wiring layer 240 includes an insulating layer 45, a third conductive member 241, a fourth conductive member 242, a fifth conductive member 243, and a sixth conductive member 244.

The insulating layer 45 is, for example, a resin layer. The insulating layer 45 is provided between the third conductive member 241 and the fourth conductive member 242, the fifth conductive member 243, and the sixth conductive member 244, respectively.

The third conductive member 241 is provided between the first optical element 211 of the first chip 210 and the first region 220a of the second chip 220, and is provided between the first electrode terminal 211a of the first optical element 211 and the second chip 220. Is electrically connected to the first signal terminal 221a of the above. The third conductive member 241 is, for example, a metal via extending along the Z-axis direction. By arranging the plurality of third conductive members 241 in an array in the XY plane, a large number of chip-to-chip wiring connections are possible.

The fourth conductive member 242 is provided between the second optical element 212 of the first chip 210 and the third region 230a of the third chip 230, and is provided between the second electrode terminal 212a of the second optical element 212 and the third chip 230. The second signal terminal 231a of the above is electrically connected. The fourth conductive member 242 is, for example, a metal via extending along the Z-axis direction. By arranging the plurality of fourth conductive members 242 in an array in the XY plane, a large number of chip-to-chip wiring connections are possible.

The fifth conductive member 243 is provided between the first terminal 81 and the second region 220b of the second chip 220, and connects the first power supply terminal 221b and the first terminal 81 of the second chip 220. ..

The sixth conductive member 244 is provided between the second terminal 82 and the fourth region 230b of the third chip 230, and connects the second power supply terminal 231b and the second terminal 82 of the third chip 230. ..

The first chip 210 is provided between the first terminal 81 and the second terminal 82. The direction from the first terminal 81 to the first chip 210 is along the X-axis direction. The direction from the second terminal 82 to the first chip 210 is along the X-axis direction.

The resin portion 51 covers the second chip 20 and the third chip 30. The resin portion 51 includes a first resin region 51a, a second resin region 51b, and a third resin region 51c. The second chip 220 is provided between the first resin region 51a and the third resin region 51c. The third chip 230 is provided between the third resin region 51c and the second resin region 51b. The third resin region 51c is provided between the second chip 220 and the third chip 230.

Power is supplied to the first power supply terminal 221b of the second chip 220 through the first terminal 81 and the fifth conductive member 243, and through the second terminal 82 and the sixth conductive member 244, the second power supply terminal of the third chip 230. It is supplied to 231b.

According to the electronic device 3 according to the fourth embodiment, the second chip 220 and the third chip 230 are connected to each other through an optical waveguide 213 formed on the first chip 210. The first optical element 211 converts an electric signal from the second chip 220 into an optical signal and outputs it to the optical waveguide 213. Alternatively, the first optical element 211 converts the optical signal from the optical waveguide 213 into an electric signal and outputs it to the second chip 220. The second optical element 212 converts the electric signal from the third chip 230 into an optical signal and outputs it to the optical waveguide 213. Alternatively, the second optical element 212 converts the optical signal from the optical waveguide 213 into an electric signal and outputs it to the third chip 230.

According to such a fourth embodiment, by making a part of the wiring between the second chip 220 and the third chip 230 optical wiring, wide band and high speed signal transmission becomes possible. The wiring layer 240 on which the second chip 220 and the third chip 230 are mounted does not need to form high-density fine conductor wiring or an optical waveguide for connecting between the chips, and can be formed at a large area panel level. Only rough wiring can be used. This enables thermal separation between the second chip 220 and the second chip 230 by cost reduction, high-speed inter-chip communication, and an optical waveguide capable of transmitting signals with low loss even over long distances. ..

(Fifth Embodiment)
FIG. 11A is a schematic cross-sectional view illustrating the electronic device 4 according to the fifth embodiment.
FIG. 12 is a schematic plan view showing an arrangement example of the first chip 310 and the second chip 20 in the electronic device 4.

As shown in FIG. 11A, the electronic device 4 according to the fifth embodiment includes a first wiring layer 340, a first chip 310, a second chip 20, a resin portion 51, and a plurality of first terminals. 81 and a plurality of second terminals 82 are included.

The first chip 310 includes a first region 310a and a second region 310b. The second chip 20 includes a third region 20a and a fourth region 20b.

The first chip 310 includes, for example, a memory element. The memory element is, for example, a cache memory. The second chip 20 includes, for example, a logic element.

The direction from the first region 310a of the first chip 310 to the third region 20a of the second chip 20 is along the first direction. The first direction is along the X-axis direction. The second direction intersects the first direction. In this example, the second direction is orthogonal to the first direction and is along the Y-axis direction.

The direction from the first region 310a of the first chip 310 to the fourth region 20b of the second chip 20 intersects the first direction and the second direction. The direction from the second region 310b of the first chip 310 toward the third region 20a of the second chip 20 intersects the first direction and the second direction.

The resin portion 51 covers at least a part of the side surface of the second chip 20. The resin portion 51 includes a first resin region 51a and a second resin region 51b. The second chip 20 is provided between the first resin region 51a and the second resin region 51b. In the example shown in FIG. 11A, the surface of the second chip 20 opposite to the wiring layer 340 is also covered with the resin portion 51, but the surface opposite to the wiring layer 340 is covered from the resin portion 51. Exposure is optional. Further, in the example shown in FIG. 11A, the resin portion 51 is also arranged around the second conductive member 21, but the peripheral portion of the second conductive member 21 is not the resin portion 51. It may be different, for example, different insulating materials may be used.

The first wiring layer 340 is located between the first region 310a of the first chip 310 and the third region 20a of the second chip 20, and between the second region 310b and the second resin region 51b of the first chip 310. It is provided between the 1st terminal 81 and the 4th region 20b of the 2nd chip 20, between the 1st terminal 81 and the 1st resin region 51a, and between the 2nd terminal 82 and the 2nd resin region 51b. ..

The first chip 310 includes a first conductive member 311. The first conductive member 311 is, for example, a metal member, and includes an electrode terminal and a conductive layer.

An insulating portion 55 is provided between the first chip 310 and the first wiring layer 340. The insulating portion 55 is made of, for example, a resin material or an inorganic material. For example, after connecting the first conductive member 311 to the first wiring layer 340, the insulating portion 55 can be injected. Alternatively, a manufacturing method may be used in which the insulating portion 55 is formed in advance in a region including the periphery of the first conductive member 311 and the insulating portion 55 is connected to the first wiring layer 340 at the same time as the first conductive member 311.

The second chip 20 includes a second conductive member 21. The second conductive member 21 is, for example, a metal member. The second conductive member 21 includes a first signal terminal 21a, a first power supply terminal 21b, and a conductive layer (not shown) connected to the first signal terminal 21a and the first power supply terminal 21b.

The first wiring layer 340 includes an insulating layer 45, a third conductive member 341, a fourth conductive member 343, and a sixth conductive member 344.

The insulating layer 45 is, for example, a resin layer. The insulating layer 45 is provided between the third conductive member 341, the fourth conductive member 343, and the sixth conductive member 344, respectively. The insulating layer 45 may be an inorganic insulating material.

The third conductive member 341 is provided between the first region 310a of the first chip 310 and the third region 20a of the second chip 20, and is the first conductive member 311 of the first chip 310 and the second chip 20. 1 It is connected to the signal terminal 21a. The third conductive member 341 is, for example, a metal via extending along the Z-axis direction. By arranging the plurality of third conductive members 341 in an array in the XY plane, a large number of chip-to-chip wiring connections are possible.

The fourth conductive member 343 is provided between the first terminal 81 and the fourth region 20b of the second chip 20, and connects the first power supply terminal 21b and the first terminal 81 of the second chip 20. ..

The sixth conductive member 344 connects the first conductive member 311 of the first chip 310 and the second terminal 82.

The first chip 310 is provided between the first terminal 81 and the second terminal 82. The direction from the first terminal 81 toward the first chip 310 is along the X-axis direction. The direction from the second terminal 82 to the first chip 310 is along the X-axis direction.

A first wiring layer 340 is also provided between the first terminal 81 and the first resin region 51a, and between the second terminal 82 and the second resin region 51b.

The electronic device 4 according to the fifth embodiment further includes the eighth conductive member 52, the ninth conductive member 53, and the semiconductor package device 60, similarly to the electronic device 1 of the first embodiment shown in FIG. 1 described above. ..

The electronic device 4 further includes a third chip 170 and a fourth chip 171. The third chip 170 and the fourth chip 171 include, for example, an IPD (Integrated Passive Device) or a passive element. Passive elements include, for example, discrete components such as capacitors, inductors, and resistor elements.

The third chip 170 is connected to, for example, the third conductive member 343, and the fourth chip 171 is connected to, for example, the fourth conductive member 344.

A first wiring layer 340 is provided between the fourth region 20b of the second chip 20 and the third chip 170. The third chip 170 is provided between the first terminal 81 and the first chip 310.

A first wiring layer 340 is provided between the fourth chip 171 and the second region 310b of the first chip 310. The fourth chip 171 is covered with the second resin region 51b.

As shown in FIGS. 11A and 12, the length of the first chip 310 along the X-axis direction may be shorter than the length of the second chip 20 along the X-axis direction.

The first conductive member 311 of the first chip 310 is electrically connected to the first signal terminal 21a of the second chip 20 through the third conductive member 341.

Power is supplied to the first power supply terminal 21b of the second chip 20 through the first terminal 81 and the fourth conductive member 343. Further, power is supplied to the first chip 310 through the second terminal 82 and the fifth conductive member 344.

According to the electronic device 4 according to the fifth embodiment, the wiring between the first chip 310 and the second chip 20 is not a wiring extending in the direction along the XY plane, but a via-shaped wiring extending in the Z-axis direction. 3 It can be connected by a conductive member 341. It is not necessary to form high-density fine wiring for chip-to-chip connection in the first wiring layer 340, and only wiring having a rough line and space that can be formed at a large-area panel level is sufficient. This allows for cost savings.

For example, the first region 310a of the first chip 310 including the memory element is approximately a memory interface region, and the first region 310a faces the second chip 20 with the first wiring layer 40 sandwiched in the Z-axis direction. There is. The first chip 310 includes a second region 310b that does not face the second chip 20.

Such a chip layout widens the area where the first terminal 81 is arranged, and reduces the distance between the first power supply terminal 21b formed in the fourth area 20b of the second chip 20 and the first terminal 81. to enable. This reduces the power supply impedance of the second chip 20. This reduction in power supply impedance suppresses fluctuations in power supply voltage and enables stable operation.

The first chip 310 includes, for example, a cache memory as a memory element. The semiconductor package device 60 includes, for example, a DRAM as a main memory having a storage capacity larger than that of the cache memory. The second chip 20 controls the first chip 310 and the semiconductor packaging device 60.

In such a configuration, a large-capacity cache memory can be incorporated as a system in one package as compared with a configuration in which a cache memory is integrated and built in the second chip 20, system performance can be improved, and chip-to-chip connection can be achieved. It is possible to reduce the wiring cost and realize stable electrode supply to the chip.

FIG. 11B is a schematic cross-sectional view of the electronic device 4'of another example of the fifth embodiment.

The electronic device 4'also includes a second wiring layer 540 as compared with the electronic device 4 of FIG. 11 (a). The second wiring layer 540 is provided between the first wiring layer 340 and the plurality of terminals 83. The first wiring layer 340 is provided between the second wiring layer 540 and the resin portion 51.

The terminal 83 is an external terminal for connecting the electronic device 4'to an external circuit. The terminal 83 is, for example, a solder ball. The terminal 83 may be a metal pad or a metal bump.

The second wiring layer 540 includes an insulating layer 545 and a fifth conductive member 546.

The insulating layer 545 is, for example, a resin layer. The insulating layer 545 covers the first chip 310 and the third chip 170.

The fifth conductive member 546 is, for example, a metal member, and is connected to the fourth conductive member 343, the sixth conductive member 344, and the terminal 83 of the first wiring layer 340.

The insulating layer 545 includes an insulating portion 545a provided between the terminal 83 and the first chip 310. The first chip 310 is provided between the insulating portion 545a and the first wiring layer 340.

Power is supplied to the second chip 20 through the terminal 83, the fifth conductive member 546 of the second wiring layer 540, and the fourth conductive member 343 of the first wiring layer 340.

Power is supplied to the first chip 310 through the terminal 83, the fifth conductive member 546 of the second wiring layer 540, and the sixth conductive member 344 of the first wiring layer 340.

The plurality of terminals 83 can be arranged over a wide area of the second wiring layer 540 without being restricted by the arrangement position of the first chip 310. This makes it possible to cope with an increase in the number of external input / output terminals due to the functional expansion of the electronic device 4'.

(Sixth Embodiment)
FIG. 13 is a schematic cross-sectional view illustrating the electronic device 5 according to the sixth embodiment.
FIG. 14 is a schematic diagram showing a connection relationship between the first chip 410 and the second chip 520 in the electronic device 5.

As shown in FIG. 13, the electronic device 5 according to the sixth embodiment includes a wiring layer 440, a first chip 410, a second chip 520, a resin portion 51, and a plurality of third terminals 181.

The first chip 410 includes the conductive member 411, and the second chip 520 includes the conductive member 521. The conductive member 411 and the conductive member 521 are, for example, metal members.

The resin portion 51 covers at least a part of the side surface of the second chip 520. This side surface intersects the XY plane. The resin portion 51 includes a first resin region 51a and a second resin region 51b. The second chip 520 is provided between the first resin region 51a and the second resin region 51b. In the example shown in FIG. 13, the surface of the second chip 520 opposite to the wiring layer 440 is also covered with the resin portion 51, but the surface opposite to the wiring layer 440 is exposed from the resin portion 51. Is optional. Further, in the example shown in FIG. 13, the resin portion 51 is also arranged in the peripheral portion of the second conductive member 521, but the peripheral portion of the second conductive member 521 does not have to be the resin portion 51. For example, different insulating materials may be used.

The wiring layer 440 is provided between the first chip 410 and the second chip 520, between the third terminal 181 and the second chip 520, between the third terminal 181 and the first resin region 51a, and the third terminal 181. It is provided between the second resin region 51b and the second resin region 51b.

An insulating portion 55 is provided between the first chip 410 and the wiring layer 440. The insulating portion 55 is made of, for example, a resin material or an inorganic material. For example, after connecting the first conductive member 411 to the wiring layer 440, the insulating portion 55 can be injected. Alternatively, a manufacturing method may be used in which the insulating portion 55 is formed in advance in a region including the periphery of the first conductive member 411, and the insulating portion 55 is connected to the wiring layer 440 at the same time as the first conductive member 411.

The wiring layer 440 includes an insulating layer 45, a first conductive member 441, a second conductive member 442, and a third conductive member 443.

The insulating layer 45 is, for example, a resin layer. The insulating layer 45 is provided between each of the first conductive member 441, the second conductive member 442, and the third conductive member 443.

The conductive member 411 of the first chip 410 is electrically connected to the conductive member 521 of the second chip 520 through the first conductive member 441 and the second conductive member 442.

The third terminal 181 is an external terminal for connecting the electronic device 5 to an external circuit. The third terminal 181 is, for example, a solder ball. The third terminal 181 may be a metal pad or a metal bump.

The first chip 410 is provided between the plurality of third terminals 181.

The length of the first chip 410 along the X-axis direction is shorter than the length of the second chip 520 along the X-axis direction.

A wiring layer 440 is also provided between the third terminal 181 and the first resin region 51a, and between the third terminal 181 and the second resin region 51b.

The electronic device 5 according to the sixth embodiment further includes the eighth conductive member 52, the ninth conductive member 53, and the semiconductor package device 60, similarly to the electronic device 1 of the first embodiment shown in FIG. 1 described above. ..

As shown in FIG. 14, the first chip 410 includes a memory element 421 and a first capacitor 422.

FIG. 15 is a schematic plan view showing the arrangement relationship between the first element region 621 in which the memory element 421 is arranged and the second element region 622 in which the first capacitor 422 is arranged in the first chip 410.

The memory element 421 is, for example, a DRAM. The DRAM includes a transistor 551 and a second capacitor 552.

The first capacitor 422 has the same structure as the second capacitor 552 of the DRAM (for example, a stacked capacitor, a trench capacitor, etc.).

In the example shown in FIG. 15, the second element region 622 is arranged between the two first element regions 621. An insulation separation portion 650 is provided between the first element region 621 and the second element region 622. The insulation separation unit 650 is, for example, STI (Shallow Trench Isolation).

The insulation separation unit 650 cuts off the connection between the memory element 421 and the first capacitor 422. The memory element 421 and the first capacitor 422 are not physically or electrically connected.

The second chip 520 includes, for example, a logic element that controls the memory element 421 of the first chip 410. As shown in FIG. 14, the conductive member 521 of the second chip 520 includes a first terminal 521a, a second terminal 521b, and a fourth terminal 521c.

The first terminal 521a is a signal terminal, the second terminal 521b is a power supply terminal, and the fourth terminal 521c is a ground terminal.

The conductive member 411 of the first chip 410 includes an electrode of the memory element 421 and an electrode of the first capacitor element 422.

The memory element 421 of the first chip 410 is electrically connected to the first terminal 521a of the second chip 520 through the first conductive member 441 of the wiring layer 440.

The first capacitor 422 of the first chip 410 is electrically connected to the second terminal 521b and the fourth terminal 521c of the second chip 520 through the second conductive member 442 of the wiring layer 440.

The first capacitor 422 of the first chip 410, the second terminal 521b and the fourth terminal 521c of the second chip 520 are electrically connected to the third terminal 181 through the third conductive member 443 of the wiring layer 440.

According to the electronic device 5 according to the sixth embodiment, the wiring between the first chip 410 and the second chip 520 is not a wiring extending in the direction along the XY plane, but a via-shaped wiring extending in the Z-axis direction. It can be connected by one conductive member 441 and a second conductive member 442. It is not necessary to form high-density fine wiring for chip-to-chip connection in the wiring layer 440, and only wiring having a rough line and space that can be formed at a large-area panel level can be used. This allows for cost savings.

The first capacitor 422 integrated with the memory element 421 on the first chip 410 is, for example, a decoupling capacitor connected to the power supply line of the second chip 520, and suppresses fluctuations in the power supply voltage of the second chip 520. This enables stable operation of the second chip 520.

FIG. 16A is a schematic cross-sectional view showing the connection relationship between the first chip 10, the second chip 20, and the third chip 30 in the electronic device according to the seventh embodiment.

The electronic device according to the seventh embodiment is a signal transmission unit between the first chip 10 and the second chip 20 and the first chip 10 and the third chip 30 in the electronic device 1 shown in FIG. 1 (a). It has a structure in which the signal transmission portion between and is replaced with an inductive coupling pair or a capacitive coupling pair instead of the conductive members 41 and 42.

The first chip 10 includes a first coupling element 11d provided in the first region 10a and a second coupling element 11e provided in the second region 10b. The second chip 20 includes a third coupling element 21d provided in the third region 20a. The third chip 30 includes a fourth coupling element 31d provided in the fifth region 30a.

The insulating layer 45 of the wiring layer 40 is provided between the first coupling element 11d and the third coupling element 21d, and between the second coupling element 11e and the fourth coupling element 31d. It is not necessary to provide the conductive member of the wiring layer 40 between the first coupling element 11d and the third coupling element 21d, and between the second coupling element 11e and the fourth coupling element 31d.

The direction from the first coupling element 11d to the third coupling element 21d is along the Z-axis direction, and the direction from the second coupling element 11e to the fourth coupling element 31d is along the Z-axis direction. The direction from the first coupling element 11d to the second coupling element 11e is along the X-axis direction, and the direction from the third coupling element 21d to the fourth coupling element 31d is along the X-axis direction.

The first chip 10 can be fixed to the wiring layer 40 with, for example, an adhesive. Alternatively, the first chip 10 can be directly bonded to the wiring layer 40 by utilizing the dehydration condensation reaction.

The first coupling element 11d, the second coupling element 11e, the third coupling element 21d, and the fourth coupling element 31d are inductive coupling elements or capacitive coupling elements.

The first coupling element 11d of the first chip 10 and the third coupling element 21d of the second chip 20 are inductively coupled or capacitively coupled. The second coupling element 11e of the first chip 10 and the fourth coupling element 31d of the third chip 30 are inductively coupled or capacitively coupled.

The first chip 10 further includes a conductive layer 11b, similarly to the first chip 10 of the first embodiment shown in FIG. 1 (d). The conductive layer 11b electrically connects the first coupling element 11d and the second coupling element 11e.

The signal is an inductive coupling or a capacitive coupling between the first coupling element 11d and the third coupling element 21d, an inducibility of the conductive layer 11b of the first chip 10, the second coupling element 11e, and the fourth coupling element 31d. It transmits between the second chip 20 and the third chip 30 through a bond or a capacitive bond.

The seventh embodiment can include the following configurations.

A first chip containing a first coupling element, a second coupling element, and a first conductive member,
A second chip containing a third coupling element and
A third chip containing a fourth coupling element and
An insulating layer provided between the first coupling element and the third coupling element, and between the second coupling element and the fourth coupling element, and
With
The first coupling element and the third coupling element are inductively coupled or capacitively coupled, and the second coupling element and the fourth coupling element are inductively coupled or capacitively coupled.
The first conductive member is an electronic device that electrically connects the first coupling element and the second coupling element.

FIG. 16B is a schematic cross-sectional view showing the connection relationship between the first chip 310 and the second chip 20 in the electronic device according to the eighth embodiment.

In the electronic device 4 shown in FIG. 11A, the electronic device according to the eighth embodiment has an inductive coupling of the signal transmission unit between the first chip 310 and the second chip 20 instead of the conductive member 341. It has a structure in which it is replaced with a pair or a capacitive coupling pair.

The first chip 310 includes a first coupling element 311a provided in the first region 310a. The second chip 20 includes a second coupling element 21e provided in the third region 20a.

The insulating layer 45 of the wiring layer 340 is provided between the first coupling element 311a and the second coupling element 21e. The conductive member of the wiring layer 340 is not provided between the first coupling element 311a and the second coupling element 21e.

The direction from the first coupling element 311a to the second coupling element 21e is along the Z-axis direction.

The first chip 310 can be fixed to the wiring layer 340 with, for example, an adhesive. Alternatively, the dehydration condensation reaction can be used to directly bond the first chip 310 to the wiring layer 340.

The first coupling element 311a and the second coupling element 21e are inductive coupling elements or capacitive coupling elements.

The first coupling element 311a of the first chip 310 and the second coupling element 21e of the second chip 20 are inductively coupled or capacitively coupled.

The signal is transmitted between the first chip 310 and the second chip 20 through an inductive coupling or a capacitive coupling between the first coupling element 311a and the second coupling element 21e.

The eighth embodiment can include the following configurations.

The first chip including the first coupling element and
A second chip containing a second coupling element and
An insulating layer provided between the first coupling element and the second coupling element,
With
The first coupling element and the second coupling element are electronic devices that are inductively coupled or capacitively coupled.

FIG. 17 is a schematic cross-sectional view of the electronic device 1'of a modified example of the electronic device 1 shown in FIG. 1 (a).

The electronic device 1'has a structure in which the electronic device 1 shown in FIG. 1A is provided with the second wiring layer 540 shown in FIG. 11B. The plurality of terminals 83 can be arranged over a wide area of the second wiring layer 540 without being restricted by the arrangement position of the first chip 10. This makes it possible to cope with an increase in the number of external input / output terminals due to the functional expansion of the electronic device 1'.

FIG. 18 is a schematic cross-sectional view of the electronic device 2'of a modified example of the electronic device 2 shown in FIG.

The electronic device 2'has a structure in which the electronic device 2 shown in FIG. 7 is provided with the second wiring layer 540 shown in FIG. 11B. The plurality of terminals 83 can be arranged over a wide area of the second wiring layer 540 without being restricted by the arrangement position of the first chip 110. This makes it possible to cope with an increase in the number of external input / output terminals due to the functional expansion of the electronic device 1'.

FIG. 19 is a schematic cross-sectional view of the electronic device 3'of a modified example of the electronic device 3 shown in FIG.

The electronic device 3'has a structure in which the electronic device 3 shown in FIG. 10 is provided with the second wiring layer 540 shown in FIG. 11 (b). The plurality of terminals 83 can be arranged over a wide area of the second wiring layer 540 without being restricted by the arrangement position of the first chip 210. This makes it possible to cope with an increase in the number of external input / output terminals due to the functional expansion of the electronic device 1'.

FIG. 20 is a schematic cross-sectional view of the electronic device 5'of a modified example of the electronic device 5 shown in FIG.

The electronic device 5'has a structure in which the electronic device 5 shown in FIG. 13 is provided with the second wiring layer 540 shown in FIG. 11B. The plurality of terminals 83 can be arranged over a wide area of the second wiring layer 540 without being restricted by the arrangement position of the first chip 410. This makes it possible to cope with an increase in the number of external input / output terminals due to the functional expansion of the electronic device 1'.

FIG. 21 is a schematic cross-sectional view of the electronic device according to the ninth embodiment.

The electronic device according to the ninth embodiment has a structure in which a third wiring layer 700 is provided in any of the above-mentioned electronic devices 1 to 5.

The third wiring layer 700 includes a conductive member 701 including metal wiring, metal vias, and metal pads. Any of the electronic devices 1 to 5 is mounted on the third wiring layer 700 via the plurality of terminals 81. The terminal 81 is connected to the conductive member 701 of the third wiring layer 700.

A plurality of terminals 84 are provided on the opposite surface of the third wiring layer 700 from the mounting surface of the electronic devices 1 to 5. The terminal 84 is, for example, a solder ball. The terminal 84 is connected to the conductive member 701 of the third wiring layer 700. The plurality of terminals 84 can be arranged over a wide area of the third wiring layer 700 without being restricted by the above-mentioned arrangement position of the first chip of the electronic devices 1 to 5. This makes it possible to cope with an increase in the number of external input / output terminals due to the expansion of the functions of electronic devices.

Hereinafter, an example in which the electronic device of the second embodiment shown in FIGS. 7 to 9 described above is applied to a large-scale system will be described with reference to FIGS. 22 to 26.

FIG. 22 is a schematic view showing the arrangement and connection of the first chip 110, 110', the second chip 20, the third chip 30, and the wiring layer 40. The wiring layer 40 is schematically represented by one straight line.
FIG. 23 is a schematic plan view of the electronic device shown in FIG. 22.
FIG. 24 is a schematic view in which the position of the second chip 20 and the position of the third chip 30 in FIG. 23 are interchanged.

According to the examples shown in FIGS. 22 to 24, a plurality of first chips 110 and 110', a plurality of second chips 20, and a plurality of third chips 30 are mounted on the wiring layer 40. The third chip 30 can function as a shared memory between adjacent second chips 20.

FIG. 25 is a schematic plan view showing an example of application of the electronic device of the second embodiment to a neural network.

The second memory element 115 of the third chip 30 stores input / output information, connection information, and the like between artificial neurons (nodes), and the logic element of the second chip 20 executes arithmetic processing based on the information. By arranging the second chip 20 and the third chip 30 in a matrix and interconnecting them by the first chips 10, 110, 110', a large-scale parallel neural network can be realized. When the first chip includes a memory element, it may be used for temporarily storing calculation information.

Data transfer to a distant node may be performed by using the wiring of the wiring layer 40 or by sharing the memory of the third chip 30. By uniformly mixing and tightly coupling a plurality of memory elements and a plurality of logic elements, it is possible to construct a scalable system while minimizing data transfer energy.

FIG. 26 is an explanatory diagram of the neural network.

A neural network is a model in which artificial neurons (nodes) that form a network by synaptic connection change the synaptic connection strength by learning and have problem-solving ability. As shown in FIG. 26, a network in which these are connected in multiple layers is called a deep neural network, and has been used in various fields in recent years.

FIG. 27 is a schematic diagram showing an example of application of the electronic device of the second embodiment to a neural network.

Input / output information, connection information, etc. between artificial neurons (nodes) are stored in the second memory element 115 of the third chip 30 and shared among a plurality of second chips 20, and the logic elements of the second chip 20 are those. Performs arithmetic processing based on the information in.

In the processing of a neural network using a conventional GPU (Graphics Processing Unit) or the like, it is necessary to repeat data transfer between the memory element and the logic element for the calculation for each layer, and there is a limit in energy efficiency and processing performance.

In the present embodiment, as shown in FIG. 27, it is possible to approach the information processing performance and efficiency in the actual brain by spatially distributing and executing the multi-layer arithmetic processing in multiple parallels.

FIG. 28 is a schematic plan view showing the full grid tile structure of the first chip 110, 110', the second chip 20, and the third chip 30.

The plurality of second chips 20 and the plurality of third chips 30 are tightly coupled by the plurality of first chips 110 and 110'to form a full grid tile structure.

The full grid tile structure shown in FIG. 28 can also be applied to a neural network as shown in FIG. 29.

The configuration shown in FIG. 28 can improve the calculation performance and the neural network processing efficiency per unit area as compared with the configuration shown in FIG. 25.

The embodiments described above can include the following configurations.

The wiring layers 40, 240, 340, 440, and 540 are along a plane including a second direction and a third direction. The second direction is along the X-axis direction and the third direction intersects the second direction. For example, the third direction is orthogonal to the second direction and is along the Y-axis direction.

The plurality of first terminals 81, the plurality of second terminals 82, the plurality of third terminals 181 and the plurality of terminals 83 described above are in the second direction and the third direction in a plane including the second direction and the third direction. Lined up in. That is, the plurality of first terminals 81, the plurality of second terminals 82, the plurality of third terminals 181 and the plurality of terminals 83 are arranged in an array in a plane including the second direction and the third direction. ..

The conductive members 41, 42, 241, 242, 341, 441, and 442 described above are along the first direction intersecting the plane. The conductive members 41, 42, 241, 242, 341, 441, and 442 are, for example, along a direction substantially perpendicular to the plane.

The first chip 10 of the embodiment shown in FIGS. 1A and 1B is a chip-shaped electrical wiring member including a first conductive member 11 that electrically connects the second chip 20 and the third chip 30. Does not include memory elements, transistors, and passive elements.

The first chip 310 or the second chip 20 shown in FIGS. 11 (a), 11 (b), and 16 (b) includes a memory element.

FIG. 30 is a schematic cross-sectional view of an example of the third chip 30 in the above-described embodiment.

The third chip 30 has a stacked memory structure including a plurality of memory chips 32 and one logic chip 33. The plurality of memory chips 32 are stacked on the logic chip 33. Each of the plurality of memory chips 32 includes the second memory element 115 shown in FIGS. 8 (a) to 9 (a). The plurality of memory chips 32 are connected to each other through a plurality of metal pads (or metal bumps) 34. The memory chip 32 is electrically connected to the logic chip 33 through a plurality of metal pads (or metal bumps) 34. The logic chip 33 is electrically connected to the signal terminals 31a and 31b of the third chip 30 shown in FIGS. 8A to 9. The plurality of memory chips 32 are molded with the resin 35.

(Appendix 1)
A first chip including a first optical element, a second optical element, and an optical waveguide optically coupled to the first optical element and the second optical element.
A first conductive member, a second chip including a first region, and a second region,
A third chip including a second conductive member, a third region, and a fourth region,
1st terminal and
2nd terminal and
Between the first optical element of the first chip and the first region of the second chip, between the second optical element of the first chip and the third region of the third chip, the first. A wiring layer provided between the terminal 1 and the second region of the second chip, and between the second terminal and the fourth region of the third chip.
With
The wiring layer is
The first optical element of the first chip and the first conductive member of the second chip are provided between the first optical element of the first chip and the first region of the second chip. With the third conductive member to be connected
The second optical element of the first chip and the second conductive member of the third chip are provided between the second optical element of the first chip and the third region of the third chip. Including a fourth conductive member to be connected,
The first chip is an electronic device provided between the first terminal and the second terminal.

(Appendix 2)
The second chip further includes a first power supply terminal.
The third chip further includes a second power supply terminal.
The wiring layer further includes a fifth conductive member that connects the first power supply terminal and the first terminal, and a sixth conductive member that connects the second power supply terminal and the second terminal. The electronic device described.

(Appendix 3)
A first chip including a memory element and a first capacitor,
A second chip including a first terminal connected to the memory element and a second terminal connected to the first capacitor.
Electronic device equipped with.

(Appendix 4)
A wiring layer provided between the first chip and the second chip is provided.
The wiring layer is
A first conductor that is provided between the memory element of the first chip and the first terminal of the second chip and connects the memory element of the first chip and the first terminal of the second chip. Parts and
A second capacitor provided between the first capacitor of the first chip and the second terminal of the second chip, and connecting the first capacitor of the first chip and the second terminal of the second chip. 2. The electronic device according to Appendix 3, which includes a conductive member.

(Appendix 5)
With a third terminal
The wiring layer is provided between the third terminal and the second terminal of the second chip, and is a third conductive member that connects the third terminal and the second terminal of the second chip. The electronic device according to Appendix 4, further comprising.

(Appendix 6)
The electronic device according to any one of Supplementary note 3 to 5, wherein the first chip further includes an insulating separation portion provided between the memory element and the first capacitor.

(Appendix 7)
The electronic device according to any one of Supplementary note 3 to 6, wherein the memory element is a DRAM (Dynamic Random Access Memory) including a second capacitor.

(Appendix 8)
A first chip including a first conductive member, a first region, and a second region,
A second chip including a second conductive member, a third region, and a fourth region,
A third chip including a third conductive member, a fifth region, and a sixth region,
1st terminal and
2nd terminal and
The first terminal between the first region of the first chip and the third region of the second chip, between the second region of the first chip and the fifth region of the third chip. And the wiring layer provided between the fourth region of the second chip and between the second terminal and the sixth region of the third chip.
With
The wiring layer is
It is provided between the first region of the first chip and the third region of the second chip, and connects the first conductive member of the first chip and the second conductive member of the second chip. 4th conductive member to be
It is provided between the second region of the first chip and the fifth region of the third chip, and connects the first conductive member of the first chip and the third conductive member of the third chip. Including the fifth conductive member
The first chip is an electronic device provided between the first terminal and the second terminal.

(Appendix 9)
The electronic device according to Appendix 8, wherein the first chip is an electrical wiring member that connects the second chip and the third chip through the first conductive member, the fourth conductive member, and the fifth conductive member. ..

(Appendix 10)
The electronic device according to Appendix 9, wherein the first chip does not include a substrate.

(Appendix 11)
The electronic device according to Appendix 9, wherein the third chip includes a memory element.

(Appendix 12)
The electronic device according to Appendix 8, wherein the first chip further includes a first memory element connected to the fourth conductive member.

(Appendix 13)
The electronic device according to Appendix 12, wherein the third chip further includes a second memory element connected to the fifth conductive member.

(Appendix 14)
The electronic device according to Appendix 13, wherein the storage capacity of the second memory element is larger than the storage capacity of the first memory element.

(Appendix 15)
The electronic device according to Appendix 13 or 14, wherein the first chip further includes a control unit connected to the fifth conductive member.

(Appendix 16)
The second chip further includes a first power supply terminal.
The third chip further includes a second power supply terminal.
The wiring layer further includes a sixth conductive member that connects the first power supply terminal and the first terminal, and a seventh conductive member that connects the second power supply terminal and the second terminal. The electronic device according to any one of 15 to 15.

(Appendix 17)
The wiring layer further includes an insulating layer provided between the fourth conductive member and the sixth conductive member, and between the fifth conductive member and the seventh conductive member.
The electronic device according to Appendix 16, wherein the fourth conductive member and the sixth conductive member are insulated and separated, and the fifth conductive member and the seventh conductive member are insulated and separated.

(Appendix 18)
A first chip including a first conductive member, a first region, and a second region,
A second chip including a second conductive member, a third region, and a fourth region,
A resin portion including a first resin region and a second resin region,
With terminals
Between the first region of the first chip and the third region of the second chip, between the second region of the first chip and the first resin region, of the terminal and the second chip. A first wiring layer provided between the fourth region and between the terminal and the second resin region,
With
The first wiring layer is provided between the first region of the first chip and the third region of the second chip, and the first conductive member of the first chip and the second chip of the second chip. Includes a third conductive member that connects to the second conductive member
The second chip is an electronic device provided between the first resin region and the second resin region of the resin portion.

(Appendix 19)
The second chip further includes a power supply terminal.
The electronic device according to Appendix 18, wherein the first wiring layer further includes a fourth conductive member that connects the power supply terminal and the terminal.

(Appendix 20)
A second wiring layer provided between the first wiring layer and the terminal is further provided.
The second wiring layer includes a fifth conductive member connected to the terminal and an insulating portion provided between the terminal and the first chip.
The electronic device according to Appendix 18 or 19, wherein the first chip is provided between the insulating portion and the first wiring layer.

(Appendix 21)
The electronic device according to any one of Supplementary note 18 to 20, wherein the first chip or the second chip includes a memory element.

(Appendix 22)
A first chip having a first connection area and a second connection area,
A second chip having a third connection region facing the first connection region of the first chip, and
A third chip having a fourth connection region facing the second connection region of the first chip, and a third chip.
With
The first chip is provided in the first memory element, a plurality of first wirings provided in the first connection area and the second connection area, and the first connection area, and is electrically connected to the first memory element. Has a plurality of first signal terminals connected to each other
The second chip has a plurality of second signal terminals provided in the third connection region and a plurality of third signal terminals provided in the third connection region.
The third chip has a second memory element and a plurality of fourth signal terminals provided in the fourth connection region and electrically connected to the second memory element.
The second signal terminal of the second chip is connected to the first signal terminal of the first memory element.
The first wiring is an electronic device connected to the third signal terminal of the second chip and the fourth signal terminal of the third chip.

(Appendix 23)
Further, a wiring layer provided between the first chip and the second chip and between the first chip and the third chip is further provided.
The wiring layer is
A plurality of first metal vias connecting the second signal terminal of the second chip and the first signal terminal of the first chip.
A plurality of second metal vias connecting the third signal terminal of the second chip and the first wiring, and
A plurality of third metal vias connecting the fourth signal terminal of the third chip and the first wiring, and
A plurality of second wirings for connecting the second chip and the third chip to the outside,
22. The electronic device according to Appendix 22.

(Appendix 24)
The electronic device according to Appendix 23, wherein the minimum spacing of the plurality of first wirings provided on the first chip is smaller than the minimum spacing of the plurality of second wirings provided on the wiring layer.

(Appendix 25)
The electronic device according to any one of Supplementary note 22 to 24, wherein the storage capacity of the second memory element is larger than the storage capacity of the first memory element.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, with respect to the specific configuration of each element such as the wiring layer, the electric element, the optical element, and the resin portion included in the electronic device, the present invention is similarly carried out by appropriately selecting from a range known to those skilled in the art. As long as the same effect can be obtained, it is included in the scope of the present invention.

Further, a combination of any two or more elements of each specific example to the extent technically possible is also included in the scope of the present invention as long as the gist of the present invention is included.

In addition, all electronic devices and manufacturing methods thereof that can be appropriately designed and implemented by those skilled in the art based on the electronic devices and manufacturing methods thereof described above as embodiments of the present invention also include the gist of the present invention. As long as it belongs to the scope of the present invention.

In addition, within the scope of the idea of the present invention, those skilled in the art can come up with various modified examples and modified examples, and it is understood that these modified examples and modified examples also belong to the scope of the present invention. ..

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

1 to 5 ... Electronic devices, 10,110,110', 210,310,410 ... First chip, 10a, 110a, 310a ... First region, 10b, 110b, 310b ... Second region, 11,111,221, 311,441 ... 1st conductive member, 20,220,520 ... 2nd chip, 20a, 230a ... 3rd region, 20b, 230b ... 4th region, 21,231,442 ... 2nd conductive member, 30,230 ... 3rd chip, 30a ... 5th region, 30b ... 6th region 31,241,341 ... 3rd conductive member, 40, 240, 340, 440 ... Wiring layer, 41,242 ... 4th conductive member, 42 ... 5 Conductive member, 43 ... 6th conductive member, 44 ... 7th conductive member, 51 ... Resin part, 51a ... 1st resin region, 51b ... 2nd resin region, 51c ... 3rd resin region, 81 ... 1st terminal, 82 ... 2nd terminal, 211 ... 1st optical element, 212 ... 2nd optical element, 213 ... optical waveguide, 181 ... 3rd terminal, 421 ... memory element, 422 ... 1st capacitor, 521a ... 1st terminal, 521b ... 2nd terminal, 552 ... 2nd capacitor, 650 ... Insulation separation part

Claims (1)

A first chip including a first conductive member, a first region, and a second region,
A second chip including a second conductive member, a third region, and a fourth region,
A third chip including a third conductive member, a fifth region, and a sixth region,
With the first terminal, which is a metal pad or metal bump,
With a second terminal that is a metal pad or metal bump,
The first terminal between the first region of the first chip and the third region of the second chip, between the second region of the first chip and the fifth region of the third chip. And the wiring layer provided between the fourth region of the second chip and between the second terminal and the sixth region of the third chip.
With
The wiring layer is
It is provided between the first region of the first chip and the third region of the second chip, and connects the first conductive member of the first chip and the second conductive member of the second chip. 4th conductive member to be
It is provided between the second region of the first chip and the fifth region of the third chip, and connects the first conductive member of the first chip and the third conductive member of the third chip. Including the fifth conductive member
The first chip is provided between the first terminal and the second terminal.
The second chip and the third chip are provided on one surface of the wiring layer.
The first chip, the first terminal, and the second terminal are electronic devices provided on the other surface of the wiring layer.

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