JP2021150446A - Nitride semiconductor substrate - Google Patents

Abstract

To provide a technique for improving a breakdown voltage of a nitride semiconductor substrate using a silicon substrate.SOLUTION: In a nitride semiconductor substrate, a nitride semiconductor layer is laminated on a silicon substrate. The nitride semiconductor layer comprises a first layer formed by laminating a plurality of nitride semiconductor crystal layers having different compositions, and a second layer formed on the first layer and containing carbon. The average oxygen concentration of the second layer is less than 1×1016 cm-3.SELECTED DRAWING: Figure 2

Description

The present invention relates to a nitride semiconductor substrate.

As a semiconductor substrate, there is a nitride semiconductor substrate in which a nitride semiconductor is epitaxially grown on a base substrate. The nitride semiconductor is a wide bandgap semiconductor and has excellent dielectric breakdown strength. Therefore, application of nitride semiconductors to semiconductor devices that require high withstand voltage is being studied. For example, Patent Document 1 proposes a nitride semiconductor substrate in which a silicon substrate is used as a base substrate and a nitride semiconductor is epitaxially grown on the silicon substrate.

JP-A-2018-88501

An object of the present invention is to provide a technique for improving the withstand voltage of a nitride semiconductor substrate using a silicon substrate.

According to one aspect of the invention
A nitride semiconductor substrate in which a nitride semiconductor layer is laminated on a silicon substrate.
The nitride semiconductor layer is
A first layer formed by laminating a plurality of nitride semiconductor crystal layers having different compositions, and
A second layer formed on the first layer and containing carbon is provided.
A nitride semiconductor substrate is provided in which the average oxygen concentration of the second layer is ^{less than 1 × 10 16} cm ^-3.

According to the present invention, the withstand voltage of a nitride semiconductor substrate using a silicon substrate can be improved.

FIG. 1 is a schematic cross-sectional view of the nitride semiconductor substrate 100 according to the first embodiment of the present invention. FIG. 2 is an example of an impurity concentration profile of the nitride semiconductor substrate 100 according to the first embodiment of the present invention and an aluminum (Al) composition profile. FIG. 3 is a schematic configuration diagram of a crystal growth apparatus 300 used in the method for manufacturing a nitride semiconductor substrate 100 according to the first embodiment of the present invention. FIG. 4 is a flowchart showing an example of a method for manufacturing the nitride semiconductor substrate 100 according to the first embodiment of the present invention. FIG. 5 is a timing chart conceptually showing an example of control of growth conditions in the stress generation layer forming step S104, the surface modification step S105, and the high resistance layer forming step S106 according to the first embodiment of the present invention.

<Findings obtained by the inventor>
First, the findings obtained by the inventor will be described.

Nitride semiconductor substrates used in power devices and the like are required to have high withstand voltage. When a nitride semiconductor is epitaxially grown on a silicon substrate by, for example, the Metalorganic Chemical Vapor Deposition (MOCVD) method, carbon in the organic metal raw material is taken in and used as an acceptor to increase the pressure resistance. It has been realized.

However, if the carbon concentration in the nitride semiconductor crystal is high, the crystallinity may deteriorate. Since the deterioration of crystallinity lowers the performance and life of the semiconductor device, a technique for improving crystallinity while ensuring withstand voltage is desired.

Further, since oxygen in the nitride semiconductor crystal acts as a donor, it is preferable to lower the oxygen concentration while increasing the carbon concentration from the viewpoint of improving the withstand voltage.

The inventor of the present application has conducted diligent research on the above-mentioned events. As a result, it has been found that the crystallinity can be improved while ensuring the withstand voltage by performing the step of modifying the surface of the nitride semiconductor crystal before forming the high resistance layer for ensuring the withstand voltage. It was also found that the oxygen concentration can be lowered while increasing the carbon concentration by controlling the surface morphology of the nitride semiconductor crystal.

[Details of Embodiments of the present invention]
Next, an embodiment of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to these examples, and is indicated by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

<First Embodiment of the present invention>
(1) Configuration of Nitride Semiconductor Substrate 100 First, the configuration of the nitride semiconductor substrate 100 of the present embodiment will be described.

FIG. 1 is a schematic cross-sectional view of the nitride semiconductor substrate 100 of the present embodiment. As shown in FIG. 1, the nitride semiconductor substrate 100 of the present embodiment includes, for example, a silicon substrate 110 and a nitride semiconductor layer 120 laminated on the silicon substrate 110.

The silicon substrate 110 is a base substrate for heteroepitaxially growing the nitride semiconductor layer 120. As the silicon substrate 110, for example, a silicon substrate 110 having a large diameter of 150 mm or more can be used. Further, as the silicon substrate 110, for example, it is preferable to use a p-type silicon substrate doped with boron. This makes it easier to control the warp of the nitride semiconductor substrate 100. The thickness of the silicon substrate 110 can be arbitrarily designed according to the application of the nitride semiconductor substrate 100. Further, the specific resistance of the silicon substrate 110 is, for example, 0.02 Ω · cm or more and 200 Ω · cm or less.

As shown in FIG. 1, for example, the nitride semiconductor layer 120 has a reaction suppressing layer 130, an intermediate layer 140, a stress generating layer 150 as the first layer, and a second layer in this order from the silicon substrate 110 side. A high resistance layer 160, a low resistance layer 170 as a third layer, and a barrier layer 180 are provided.

The reaction suppression layer 130 is, for example, a layer formed on the silicon substrate 110 and containing AlN (aluminum nitride) (preferably a layer composed of AlN). The reaction suppression layer 130 is interposed between the silicon substrate 110 and the intermediate layer 140 to react (alloy) the silicon (Si) contained in the silicon substrate 110 and the gallium (Ga) contained in the intermediate layer 140. Suppress. As a material constituting the reaction suppression layer 130, Al _x Ga _1-x N (0.9 ≦ x ≦ 1) may be used. _{Further, a layer made of SiN y} (1 ≦ y ≦ 2) may be sandwiched between the reaction suppressing layer 130 and the silicon substrate 110. The reaction suppression layer 130 also has a function of forming an initial nucleus of the nitride semiconductor layer 120 grown above the reaction suppression layer 130. The thickness of the reaction suppression layer 130 is, for example, 30 nm or more and 300 nm or less.

The intermediate layer 140 is, for example, a layer formed on the reaction suppression layer 130 and containing AlGaN (aluminum gallium nitride) (a layer composed of AlGaN containing Al and Ga as group III elements). The intermediate layer 140 expands the initial nuclei formed in the reaction suppressing layer 130 and has a flat upper surface than the upper surface of the reaction suppressing layer 130, so that the intermediate layer 140 is under the stress generating layer 150 grown above the intermediate layer 140. Make up the ground. The Al composition of the intermediate layer 140 is selected to be smaller than the Al composition of the reaction suppression layer 130. The thickness of the intermediate layer 140 is, for example, 40 nm or more and 1000 nm or less. The intermediate layer 140 preferably grows coherently with respect to the reaction suppression layer 130, but it is not essential that the intermediate layer 140 grows completely coherently with respect to the reaction suppression layer 130, and lattice relaxation may occur.

The stress generating layer 150 is formed by laminating a plurality of nitride semiconductor crystal layers having different compositions. The stress generating layer 150 is, for example, a layer formed on the intermediate layer 140 and generating compressive stress for reducing the warp of the entire nitride semiconductor substrate 100. By repeatedly laminating nitride semiconductor crystal layers having different AlGaN compositions, compressive stress can be generated in the layer formed above the stress generating layer 150, and the warpage of the entire nitride semiconductor substrate 100 is reduced. be able to.

As shown in FIG. 1, for example, the stress generating layer 150 is a repeating multi-crystal layer 153 in which a first nitride semiconductor crystal layer 151 and a second nitride semiconductor crystal layer 152 having different AlGaN compositions are alternately laminated. It has a laminated-Layer Superlattice (SLS) structure. The first nitride semiconductor crystal layer 151 is formed from, for example, a group III nitride crystal having a lattice constant of a1 in a bulk crystal. The second nitride semiconductor crystal layer 152 is formed from, for example, a group III nitride crystal in which the lattice constant in the bulk crystal is a2 (a1 <a2) larger than the lattice constant a1 of the first nitride semiconductor crystal layer 151. Will be done. The AlGaN compositions of the first nitride semiconductor crystal layer 151 and the second nitride semiconductor crystal layer 152 are not particularly limited as long as the relationship of the lattice constants is a1 <a2. For example, the AlGaN composition of the first nitride semiconductor crystal layer 151 _{is preferably Al p} Ga _1-p N (0.9 ≦ p ≦ 1). Further, the second nitride semiconductor crystal layer 152 has a higher ga than the first nitride semiconductor crystal layer 151 from the viewpoint of making the lattice constant a2 larger than the lattice constant a1 of the first nitride semiconductor crystal layer 151. The ratio is preferably high, and for example, the AlGaN composition thereof is preferably Al _q Ga _1-q N (0 ≦ q ≦ 0.3).

In the stress generating layer 150, the thicknesses of the first nitride semiconductor crystal layer 151 and the second nitride semiconductor crystal layer 152 and the number of repetitions of the multiple crystal layer 153 are not particularly limited, and the nitride semiconductor substrate 100 It may be changed as appropriate according to the intended use. For example, the thickness of the first nitride semiconductor crystal layer 151 is preferably 1 nm or more and 20 nm or less, and more preferably 5 nm or more and 20 nm or less. The thickness of the second nitride semiconductor crystal layer 152 is preferably 5 nm or more and 300 nm or less, and more preferably 10 nm or more and 300 nm or less. The number of layers of the multilayer crystal layer 153 is, for example, 2 or more and 500 or less. The uppermost layer of the stress generating layer 150 is preferably the first nitride semiconductor crystal layer 151. Thereby, the surface roughness of the uppermost layer of the stress generating layer 150 can be suppressed.

Further, for example, the stress generating layer 150 is a third nitride having a lattice constant of a3 (a2 <a3) in the bulk crystal in addition to the first nitride semiconductor crystal layer 151 and the second nitride semiconductor crystal layer 152. It may be a three-layer laminated structure with a semiconductor crystal layer. Further, for example, the stress generating layer 150 may be composed of a graded crystal layer in which the lattice constant in the bulk crystal increases continuously or stepwise as the distance from the silicon substrate 110 increases (as it goes upward).

The high resistivity layer 160 is, for example, a layer formed on the stress generating layer 150 and mainly for ensuring a withstand voltage by containing carbon, and its resistivity is higher than that of the low resistivity layer 170. The high resistance layer 160 is, for example, an Al _a Ga _1-a N (0 ≦ a <1) layer, preferably a GaN layer. The thickness is, for example, 100 nm or more and 2000 nm or less (preferably 300 nm or more and 1000 nm or less). In the present specification, the withstand voltage means the withstand voltage of the nitride semiconductor substrate 100 in the thickness direction unless otherwise specified.

The low resistivity layer 170 is, for example, a carrier layer formed on the high resistivity layer 160 for electrons to travel, and its specific resistance is lower than that of the high resistivity layer 160. The low resistance layer 170 is, for example, an Al _b Ga _1-b N (0 ≦ b <1) layer, preferably a GaN layer. Its thickness is, for example, 100 nm or more and 1000 nm or less (preferably 500 nm or less).

The barrier layer 180 is formed on, for example, the low resistance layer 170 and is a layer for supplying electrons to the low resistance layer 170. The barrier layer 180 is, for example, an Al _c Ga _1-c N (0 <c ≦ 1, b <c) layer, preferably an Al _c Ga _1-c N (0.1 <c ≦ 0.3) layer. Is. Its thickness is, for example, 10 nm or more and 100 nm or less.

(Impurity concentration profile)
FIG. 2 is an example of an impurity concentration profile of carbon (C), hydrogen (H) and oxygen (O) of the nitride semiconductor substrate 100 of the present embodiment and an aluminum (Al) composition profile. Specifically, FIG. 2 shows the impurity concentration profiles of C, H, and O in the depth direction in a part of the stress generating layer 150, the high resistance layer 160, and a part of the low resistance layer 170, and Al. It is an example with a composition profile. The impurity concentration profile and Al composition profile of this embodiment were measured by secondary ion mass spectrometry (SIMS). In FIG. 2, the impurity concentrations of C, H, and O are indicated by the display ^{on the left axis (Concentration (Atoms / cm 3)).} Regarding the Al composition, the Al composition is indicated as the count number of SIMS corresponding to the Al composition by the display of the right axis (Chemical ion integrity (counts / sec)). Note that FIG. 2 shows a profile in which fine irregularities such as noise are leveled. The SIMS measurement conditions are as follows.
Ion source: Cesium ion (Cs ⁺ )
Ion energy: 14.5 keV
Depth resolution: 10 to 20 nm
Measuring part area: 30 μmφ

In the present specification, the interface 200 between the stress generating layer 150 and the high resistance layer 160 and the interface 210 between the high resistance layer 160 and the low resistance layer 170 are defined as follows using the measured values of SIMS. NS. The interface 200 is a position in the upper portion 201 of the stress generating layer 150 where the Al composition decreases to 50% with respect to the average Al composition in the thickness direction (that is, the position where the SIMS count number decreases to 50%). .. The interface 210 is located at a position ^{where the carbon concentration decreases to 1 × 10 18} cm ^-3 from the high resistance layer 160 to the low resistance layer 170. The upper portion 201 of the stress generating layer 150 indicates a range from 10% to 50% of the thickness of the high resistance layer 160 from the interface 200 to the stress generating layer 150 side. Further, in the present specification, a region within 10% of the thickness of the high resistance layer 160 is defined as the interface vicinity 202 above and below the interface 200.

FIG. 2 shows an impurity concentration profile and an Al composition profile when the high resistance layer 160 and the low resistance layer 170 are GaN layers. The fact that the high resistance layer 160 and the low resistance layer 170 are GaN layers means that the Al composition of each of these layers 160 and 170 is less than 0.001.

In order to make it easier to control the carbon concentration profile in the high resistance layer 160, it is preferable that the Al composition in the high resistance layer 160 is constant. The constant Al composition in the high resistance layer 160 means, for example, a portion (center) located at the center of the high resistance layer 160 in the thickness direction and having a thickness of 50% of the thickness of the high resistance layer 160. It means that the fluctuation amount of the Al composition is less than 0.001 in the portion having a thickness of 25% above and below each, hereinafter also referred to as the central portion of the high resistance layer 160).

(Carbon concentration)
As can be seen from FIG. 2, in the carbon concentration profile of the present embodiment, a characteristic dent is observed in the vicinity of the interface 202. Since the nitride semiconductor substrate 100 of the present embodiment has such a carbon concentration profile, its crystallinity can be improved while ensuring the withstand voltage. The details of the carbon concentration profile of this embodiment will be described below.

The average carbon concentration of the stress generating layer 150 is preferably, for example, 2 × 10 ¹⁹ cm ^-3 or more and 8 × 10 ¹⁹ cm ^-3 or less. Thereby, the withstand voltage of the nitride semiconductor substrate 100 can be improved. The average carbon concentration of the stress generating layer 150 is defined by the carbon concentration averaged in the thickness direction in the upper portion 201 of the stress generating layer 150. That is, the average carbon concentration of the stress generating layer 150 can be rephrased as the average carbon concentration in the upper portion 201 of the stress generating layer 150.

The average carbon concentration of the high resistance layer 160 is preferably 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less, for example. Thereby, the withstand voltage of the nitride semiconductor substrate 100 can be improved. The average carbon concentration of the high resistance layer 160 is defined by the carbon concentration averaged in the thickness direction in the central portion of the high resistance layer 160.

The low resistance layer 170 preferably contains substantially no carbon, and its average carbon concentration is lower than the average carbon concentration of the high resistance layer 160. Specifically, the average carbon concentration of the low resistance layer 170 is, for example, ^{less than 1 × 10 18} cm ^-3 (more preferably less than 1 × 10 ¹⁷ cm ^-3 , still more preferably less than 2 × 10 ¹⁶ cm ^-3. ) Is preferable. Thereby, the electrical characteristics of the nitride semiconductor substrate 100 can be improved. The average carbon concentration of the low resistance layer 170 is located at the center of the low resistance layer 170 in the thickness direction, and has a thickness of 50% of the thickness of the low resistance layer 170 (25 from the center to the top and bottom respectively). It is defined by the carbon concentration averaged in the thickness direction in the portion having a thickness of%, hereinafter also referred to as the central portion of the low resistance layer 170).

The average carbon concentration of the lower portion 220 of the high resistance layer 160 is lower than the average carbon concentration of the upper portion 230 of the high resistance layer 160. Thereby, for example, the crystallinity of the upper layer portion 230 of the high resistance layer 160, the low resistance layer 170, and the barrier layer 180 can be improved. The lower layer portion 220 of the high resistance layer 160 is, for example, the lower side when the high resistance layer 160 is divided into upper and lower halves with half the thickness thereof, and the upper layer portion 230 of the high resistance layer 160 is on the upper side thereof. be. Further, the average carbon concentration of the lower layer portion 220 and the average carbon concentration of the upper layer portion 230 are located at the center in the thickness direction of each portion, and have a thickness of 50% of the thickness of each portion (center). It is defined by the carbon concentration averaged in the thickness direction in the portion having a thickness of 25% above and below each.

The average carbon concentration of the lower portion 220 of the high resistance layer 160 is lower than the average carbon concentration of the stress generating layer 150. Thereby, for example, the crystallinity of the upper layer portion 230 of the high resistance layer 160, the low resistance layer 170, and the barrier layer 180 can be improved.

In the nitride semiconductor substrate 100 of the present embodiment, the low carbon region 240 having a carbon concentration of 70% or less (preferably 60% or less, more preferably 50% or less) of the average carbon concentration of the stress generating layer 150 is located near the interface. It exists in 202. Thereby, the crystallinity of the nitride semiconductor substrate 100 can be improved. The line AA in FIG. 2 is a line showing 70% of the average carbon concentration of the stress generating layer 150.

The minimum value of the carbon concentration in the low carbon region 240 is, for example, 3 × 10 ¹⁸ cm ^-3 or more (more preferably 5 × 10 ¹⁸ cm ^-3 or more, still more preferably 1 × 10 ¹⁹ cm ^-3 or more) 3 × 10 It is preferably ¹⁹ cm ^{-3 or less.} If the minimum value of the carbon concentration in the low carbon region 240 is ^{less than 3 × 10 18} cm ^-3 , it becomes difficult to sufficiently increase the carbon concentration in the upper portion 230 of the high resistance layer 160, for example, and the nitride semiconductor substrate 100 The pressure resistance may decrease. On the other hand, the minimum value of the carbon concentration in the low carbon region 240 is set to 3 × 10 ¹⁸ cm ^-3 or more (more preferably 5 × 10 ¹⁸ cm ^-3 or more, still more preferably 1 × 10 ¹⁹ cm ^-3 or more). As a result, for example, it is possible to sufficiently increase the carbon concentration in the upper layer portion 230 of the high resistance layer 160, and it is possible to suppress a decrease in the withstand voltage of the nitride semiconductor substrate 100. On the other hand, if the minimum value of the carbon concentration in the low carbon region 240 ^{exceeds 3 × 10 19} cm ^-3 , it is difficult to obtain the effect of improving the crystallinity. On the other hand, by setting the minimum value of the carbon concentration in the low carbon region 240 to 3 × 10 ¹⁹ cm ^-3 or less, for example, the upper layer 230 of the high resistance layer 160, the low resistance layer 170, and the barrier layer 180 Crystallinity can be improved.

The thickness of the low carbon region 240 is preferably 2% or more and 50% or less of the thickness of the high resistance layer 160, for example. If the thickness of the low carbon region 240 is less than 2% of the thickness of the high resistance layer 160, it is difficult to obtain the effect of improving crystallinity. On the other hand, by setting the thickness of the low carbon region 240 to 2% or more of the thickness of the high resistance layer 160, for example, the upper portion 230 of the high resistance layer 160, the low resistance layer 170, and the barrier layer 180 can be formed. Crystallinity can be improved. On the other hand, if the thickness of the low carbon region 240 exceeds 50% of the thickness of the high resistance layer 160, for example, it becomes difficult to sufficiently increase the carbon concentration in the upper portion 230 of the high resistance layer 160, and the nitride semiconductor The withstand voltage of the substrate 100 may decrease. On the other hand, by setting the thickness of the low carbon region 240 to 50% or less of the thickness of the high resistance layer 160, for example, the carbon concentration in the upper portion 230 of the high resistance layer 160 can be sufficiently increased. , It is possible to suppress a decrease in the withstand voltage of the nitride semiconductor substrate 100.

The low carbon region 240 preferably exists across the interface 200 between the stress generating layer 150 and the high resistance layer 160. That is, it is preferable that the interface 200 exists in the low carbon region 240. As a result, a nitride semiconductor crystal having good crystallinity can be grown from the start of growth of the high resistance layer 160.

In the nitride semiconductor substrate 100 of the present embodiment, the high carbon region 250 having a carbon concentration of 70% or more (preferably 80% or more, more preferably 90% or more) of the average carbon concentration of the stress generating layer 150 has a high resistance. It is present in the upper portion 230 of the layer 160. Thereby, the withstand voltage of the nitride semiconductor substrate 100 can be improved.

The maximum value of the carbon concentration in the high carbon region 250 is preferably about the same as the average carbon concentration of the stress generating layer 150. Specifically, the maximum value of the carbon concentration in the high carbon region 250 is preferably, for example, 95% or more and 120% or less of the average carbon concentration of the stress generating layer 150. If the maximum carbon concentration in the high carbon region 250 is less than 95% of the average carbon concentration of the stress generating layer 150, it is difficult to obtain the effect of improving the withstand voltage of the nitride semiconductor substrate 100. On the other hand, by setting the maximum value of the carbon concentration in the high carbon region 250 to 95% or more of the average carbon concentration of the stress generating layer 150, the withstand voltage of the nitride semiconductor substrate 100 can be further improved. On the other hand, when the maximum value of the carbon concentration in the high carbon region 250 exceeds 120% of the average carbon concentration of the stress generating layer 150, the carrier density difference between the high resistance layer 160 and the stress generating layer 150 becomes large, so that the nitride semiconductor The electrical characteristics of the substrate 100 may deteriorate. On the other hand, by setting the maximum carbon concentration in the high carbon region 250 to 120% or less of the average carbon concentration of the stress generating layer 150, the carrier density difference between the high resistance layer 160 and the stress generating layer 150 becomes small. , The electrical characteristics of the nitride semiconductor substrate 100 can be stabilized.

(Hydrogen concentration)
As can be seen from FIG. 2, in the impurity concentration profile of the high resistance layer 160 of the present embodiment, the value of the carbon concentration changes significantly, whereas the value of the hydrogen concentration changes little. Since the nitride semiconductor substrate 100 of the present embodiment has such a hydrogen concentration profile, it is possible to suppress fluctuations in the density of defects that act as traps. The details of the hydrogen concentration profile of this embodiment will be described below.

The average hydrogen concentration of the high resistance layer 160 is, for example, 15% or more and 100% or less of the average hydrogen concentration of the stress generating layer 150. The average hydrogen concentration of the high resistance layer 160 is defined by the hydrogen concentration averaged in the thickness direction in the central portion of the high resistance layer 160. Further, the average hydrogen concentration of the stress generating layer 150 is defined by the hydrogen concentration averaged in the thickness direction in the upper portion 201 of the stress generating layer 150. When the average hydrogen concentration of the high resistance layer 160 is less than 15% of the average hydrogen concentration of the stress generation layer 150, the density variation of defects acting as traps between the stress generation layer 150 and the high resistance layer 160 becomes large, and nitrided. The electrical characteristics of the physical semiconductor substrate 100 may deteriorate. On the other hand, by setting the average hydrogen concentration of the high resistance layer 160 to 15% or more of the average hydrogen concentration of the stress generation layer 150, defects that act as traps between the stress generation layer 150 and the high resistance layer 160 Density fluctuation can be suppressed. On the other hand, when the average hydrogen concentration of the high resistance layer 160 exceeds 100% of the average hydrogen concentration of the stress generating layer 150, for example, hydrogen diffuses into the low resistance layer 170 having a lower hydrogen concentration than the high resistance layer 160. The electrical characteristics of the nitride semiconductor substrate 100 may deteriorate. On the other hand, by setting the average hydrogen concentration of the high resistance layer 160 to 100% or less of the average hydrogen concentration of the stress generating layer 150, the diffusion of hydrogen is reduced and the electrical characteristics of the nitride semiconductor substrate 100 are stabilized. be able to.

The average hydrogen concentration of the stress generating layer 150 is, for example, 1 × 10 ¹⁸ cm ^-3 or more and 6 × 10 ¹⁸ cm ^-3 , and the average hydrogen concentration of the high resistance layer 160 is within the above range (average hydrogen of the stress generating layer 150). From the viewpoint of 15% or more and 100% or less of the concentration), the average hydrogen concentration of the high resistance layer 160 is preferably, for example, 4 × 10 ¹⁷ cm ^-3 or more and 1 × 10 ¹⁸ cm ^-3 or less.

In the nitride semiconductor substrate 100 of the present embodiment, the hydrogen concentration of the high resistance layer 160 is a substantially constant value. Specifically, the fluctuation amount of the hydrogen concentration in the high resistance layer 160 is, for example, ± 20% or less. In the present specification, the fluctuation amount of the hydrogen concentration of the high resistance layer 160 means the ratio of the fluctuation of the hydrogen concentration to the average hydrogen concentration of the high resistance layer 160 in the central portion of the high resistance layer 160. By reducing the fluctuation amount of the hydrogen concentration in the thickness direction in the high resistance layer 160, the density fluctuation in the thickness direction of the defect acting as a trap can be suppressed. When a semiconductor device is manufactured using such a nitride semiconductor substrate 100, its life and performance can be improved.

(Oxygen concentration)
As can be seen from FIG. 2, in the impurity concentration profile of the high resistance layer 160 of the present embodiment, the carbon concentration has a large change in its value, while the oxygen concentration has a small fluctuation amount. Since the nitride semiconductor substrate 100 of the present embodiment has such an oxygen concentration profile, the electrical characteristics can be stabilized. The details of the hydrogen concentration profile of this embodiment will be described below.

The average oxygen concentration of the high resistance layer 160 is, for example, less than ^{1 × 10 16} cm ^-3. The average oxygen concentration of the high resistance layer 160 is defined by, for example, the oxygen concentration averaged in the thickness direction in the central portion of the high resistance layer 160. Since oxygen acts as a donor in the high resistance layer 160, if the average oxygen concentration of the high resistance layer 160 is 1 × 10 ¹⁶ cm ^-3 or more, the withstand voltage of the nitride semiconductor substrate 100 may decrease. On the other hand, by setting the average oxygen concentration of the high resistance layer 160 to ^{less than 1 × 10 16} cm ^-3 , the withstand voltage of the nitride semiconductor substrate 100 can be improved. The lower limit of the average oxygen concentration of the high resistance layer 160 is not particularly limited, but is exemplified by ^{1 × 10 15} cm ^{-3 or more.}

In the nitride semiconductor substrate 100 of the present embodiment, the oxygen concentration of the high resistance layer 160 is a substantially constant value. Specifically, the fluctuation amount of the oxygen concentration of the high resistance layer 160 is, for example, ± 50% or less. In the present specification, the fluctuation amount of the oxygen concentration of the high resistance layer 160 means the ratio of the fluctuation of the oxygen concentration to the average oxygen concentration of the high resistance layer 160 in the central portion of the high resistance layer 160. By reducing the fluctuation amount of the oxygen concentration in the high resistance layer 160 in the thickness direction, the electrical characteristics of the nitride semiconductor substrate 100 can be stabilized.

(2) Manufacturing Method of Nitride Semiconductor Substrate 100 Next, a manufacturing method of the nitride semiconductor substrate 100 of the present embodiment will be described.

(Crystal Growth Device 300)
FIG. 3 is a schematic configuration diagram of the crystal growth apparatus 300 used in the method for manufacturing the nitride semiconductor substrate 100. As shown in FIG. 3, the crystal growth apparatus 300 includes a reactor 310 and a control unit 370. A susceptor 320 for mounting the silicon substrate 110 is arranged in the reaction furnace 310. Above the susceptor 320, a top plate 342 made of quartz (silicon oxide) is supported and fixed so as to face the upper surface of the susceptor 320 at a distance from each other.

The space 350 partitioned between the susceptor 320 and the top plate 342 serves as a flow path for supplying the group III raw material gas Ga1, the group V raw material gas Ga2, and the carrier gas Gb1. The carrier gas supplied together with the group III raw material gas Ga1 and the carrier gas supplied together with the group V raw material gas Ga2 are collectively referred to as a carrier gas Gb1. The space 351 between the top plate 342 and the inner wall of the reactor 310, which is arranged on the opposite side of the top plate 342 from the susceptor 320, serves as a flow path to which the cooling gas Gb2 for cooling the top plate 342 is supplied. The flow rates and compositions of the gases Ga1, Ga2, Gb1 and Gb2 are adjusted by a flow rate adjusting mechanism (not shown) controlled by the control unit 370. In FIG. 3, gas Ga1, Ga2, Gb1 and Gb2 flow from the left to the right of the paper surface.

A susceptor cover 341 made of quartz is placed on the susceptor 320. The susceptor cover 341 has a function of covering and protecting the susceptor 320 so that the susceptor 320 is not contaminated by the raw material gas. The susceptor cover 341 is provided with an opening 331, and the silicon substrate 110 is placed in the opening 331. FIG. 3 illustrates a mode in which the silicon substrate 110 is placed via the rotation mechanism 330. The rotation mechanism 330 allows each layer constituting the nitride semiconductor layer 120 to grow on the silicon substrate 110 while rotating the silicon substrate 110.

The susceptor 320 is provided with an outer peripheral side heater 361 and an inner peripheral side heater 362. The outer peripheral side heater 361 can heat the susceptor cover 341 mounted on the susceptor 320. The inner peripheral side heater 362 can heat the silicon substrate 110 mounted on the susceptor 320 via the rotation mechanism 330. Each of the outer peripheral side heater 361 and the inner peripheral side heater 362 is controlled by the control unit 370 so as to reach a predetermined growth temperature at a predetermined timing.

FIG. 4 is a flowchart showing an example of a method for manufacturing the nitride semiconductor substrate 100 of the present embodiment. The method for manufacturing the nitride semiconductor substrate 100 of the present embodiment is, for example, a substrate preparation step S101, a reaction suppression layer forming step S102, an intermediate layer forming step S103, a stress generating layer forming step S104, and a surface modification step S105. A high resistance layer forming step S106, a low resistance layer forming step S107, and a barrier layer forming step S108.

(Substrate preparation step S101)
First, in the substrate preparation step S101, the silicon substrate 110 is prepared. The silicon substrate 110 is placed in the reactor 310 (inside the opening 331).

(Reaction suppression layer forming step S102)
After the silicon substrate 110 is placed in the reaction furnace 310, the reaction suppression layer 130 is formed on the silicon substrate 110 by growing AlGaN (preferably AlN) on the silicon substrate 110, for example, by the MOCVD method. Of the group III raw material gas Ga1, at least one of trimethylgallium (Ga (CH ₃ ) ₃ , TMG) gas and triethyl gallium (Ga (C ₂ H ₅ ) ₃ , TEG) gas is used as the Ga raw material gas. Can be done. As the Al raw material gas among the group III raw material gas Ga1, for example, trimethylaluminum (Al (CH ₃ ) ₃ , TMA) gas can be used. As the nitrogen (N) raw material gas which is the group V raw material gas Ga2, for example, ammonia (NH ₃ ) gas can be used. As the carrier gas Gb1, for example, _{at least one of nitrogen (N 2} ) gas and hydrogen (H ₂ ) gas can be used. As the cooling gas Gb2, for example, _{at least one of N 2} gas and H ₂ gas can be used. In the subsequent steps as well, the above-mentioned various gases can be used as the gases Ga1, Ga2, Gb1 and Gb2.

The growth temperature in the reaction suppression layer forming step S102 can be selected, for example, in the range of 900 ° C. or higher and 1260 ° C. or lower, and the V / III ratio, which is the flow rate ratio of the group V raw material gas Ga2 to the group III raw material gas Ga1, is, for example. It can be selected in the range of 10 or more and 10000 or less.

(Intermediate layer forming step S103)
After the reaction suppression layer 130 is formed, the intermediate layer 140 is formed on the reaction suppression layer 130 by, for example, growing AlGaN by the MOCVD method.

The growth temperature in the intermediate layer forming step S103 can be selected, for example, in the range of 900 ° C. or higher and 1260 ° C. or lower, and the V / III ratio can be selected in the range of 10 or more and 10000 ° C. or lower, for example.

(Stress generation layer forming step S104)
After the intermediate layer 140 is formed, AlN as the first nitride semiconductor crystal layer 151 and AlGaN as the second nitride semiconductor crystal layer 152 are alternately laminated on the intermediate layer 140, for example, by the MOCVD method. This forms the stress generating layer 150. When forming the first nitride semiconductor crystal layer 151, for example, TMA gas is supplied to the space 350 as the group III raw material gas Ga1, and when forming the second nitride semiconductor crystal layer 152, for example, III. TMA gas and TMG gas are supplied to the space 350 as the group raw material gas Ga1.

The growth temperature in the stress generation layer forming step S104 can be selected, for example, in the range of 900 ° C. or higher and 1260 ° C. or lower, and the V / III ratio can be selected in the range of 10 or more and 10000 ° C. or lower, for example.

FIG. 5 is a timing chart conceptually showing an example of control of growth conditions in the stress generation layer forming step S104, the surface modification step S105, and the high resistance layer forming step S106. Timing charts of the top of FIG. 5, III group material gas Ga1 in each step (TMA gas, TMG gas, TEG gas), V group material gas Ga2 (NH ₃ gas) and the carrier gas Gb1 _{(H 2} gas, _{N 2} gas ) Indicates an increase or decrease in the supply amount. The timing chart at the bottom of FIG. 5 shows the control temperatures of the outer peripheral side heater 361 and the inner peripheral side heater 362 in each step. The control temperature of the outer peripheral side heater 361 and the inner peripheral side heater 362 can be rephrased as the growth temperature in the stress generation layer forming step S104 and the high resistance layer forming step S106.

As shown in FIG. 5, in the stress generation layer forming step S104, for example, at the timing of increasing the supply amount of TMG gas, that is, at the timing of forming the second nitride semiconductor crystal layer 152, the group V raw material gas Ga2 ( it is preferable to increase the supply amount of the NH ₃ gas). Thereby, the crystallinity of the second nitride semiconductor crystal layer 152 can be improved. By improving the crystallinity of the second nitride semiconductor crystal layer 152, defects acting as traps are reduced, so that the hydrogen concentration of the stress generating layer 150 can be lowered. As a result, the difference in hydrogen concentration between the stress generating layer 150 and the high resistance layer 160 becomes small, and the density fluctuation between the layers of the defects acting as traps can be suppressed.

As shown in FIG. 5, the stress generation layer forming step S104, the top layer of stress-creating layers 150 (e.g., the first nitride semiconductor crystal layer 151) at a timing of forming a, V group material gas Ga2 (NH ₃ gas ) Is preferably increased. As a result, the carbon concentration in the vicinity of the interface 202 (particularly on the stress generating layer 150 side) can be lowered. Further, the low carbon region 240 can be present across the interface 200. As a result, a nitride semiconductor crystal having good crystallinity can be grown from the start of growth of the high resistance layer 160.

(Surface modification step S105)
After forming the stress generation layer 150, the silicon substrate 110, and a nitride semiconductor layer 120 formed before (after stress generation layer forming step S104) to perform the surface modification step S105, NH ₃ gas atmosphere The surface of the stress generating layer 150 is modified by holding it inside for a certain period of time. As a result, the surface of the stress generating layer 150 can be rearranged and the surface can be flattened. Further, carbon can be desorbed from the surface of the stress generating layer 150 to reduce the carbon concentration in the vicinity of the interface 202. That is, the low carbon region 240 can be present in the vicinity of the interface 202. As a result, a nitride semiconductor crystal having good crystallinity can be grown in the high resistance layer forming step S106 described later.

As shown in FIG. 5, the surface modification step S105, the stress generation layer forming step S104, to keep the supply amount of the group V material gas when forming the uppermost layer of stress-creating layers 150 Ga2 (NH ₃ gas) Is preferable. That is, it is preferable to perform the surface modification step S105 while increasing the supply amount of _{NH 3 gas.} As a result, the surface of the stress generating layer 150 can be quickly modified. In the surface modification step S105, it may further increase the supply amount of the NH ₃ gas.

As shown in FIG. 5, in the surface modification step S105, it is preferable that the control temperature of the outer peripheral side heater 361 and the inner peripheral side heater 362 is higher than the growth temperature in the stress generation layer forming step S104. Specifically, the control temperature of the outer peripheral side heater 361 and the inner peripheral side heater 362 is preferably, for example, 1000 ° C. or higher and 1300 ° C. or lower. If the control temperature of the outer peripheral side heater 361 and the inner peripheral side heater 362 is less than 1000 ° C., it may be difficult to proceed with the modification of the surface of the stress generating layer 150. On the other hand, by setting the control temperature of the outer peripheral side heater 361 and the inner peripheral side heater 362 to 1000 ° C. or higher, the surface of the stress generating layer 150 can be quickly modified. On the other hand, if the control temperatures of the outer peripheral side heater 361 and the inner peripheral side heater 362 exceed 1300 ° C., etching of the surface of the stress generating layer 150 may proceed and the stress generating layer 150 may be decomposed. On the other hand, by setting the control temperature of the outer peripheral side heater 361 and the inner peripheral side heater 362 to 1300 ° C. or lower, the decomposition of the stress generating layer 150 can be suppressed.

The time for performing the surface modification step S105 is preferably, for example, 1 minute or more and 10 minutes or less. If the time for performing the surface modification step S105 is less than 1 minute, the surface of the stress generating layer 150 may not be sufficiently modified. On the other hand, by setting the time for performing the surface modification step S105 to 1 minute or more, the surface of the stress generating layer 150 can be sufficiently modified. On the other hand, if the time for performing the surface modification step S105 exceeds 10 minutes, the etching of the surface of the stress generating layer 150 proceeds, and the stress generating layer 150 may be decomposed. On the other hand, by setting the time for performing the surface modification step S105 to 10 minutes or less, the decomposition of the stress generating layer 150 can be suppressed. In addition, damage to the silicon substrate 110 can be suppressed.

(High resistance layer forming step S106)
After modifying the surface of the stress generating layer 150, the high resistance layer 160 is formed by growing AlGaN (preferably GaN) on the stress generating layer 150, for example, by the MOCVD method. Since the surface of the stress generating layer 150 is modified in the surface modification step S105, a nitride semiconductor crystal having good crystallinity can be grown in the high resistance layer forming step S106.

The growth temperature in the high resistance layer forming step S106 can be selected, for example, in the range of 900 ° C. or higher and 1260 ° C. or lower, and the V / III ratio can be selected in the range of 10 or more and 10000 ° C. or lower, for example.

As shown in FIG. 5, the high-resistance layer formation step S106, the supply amount of group V material gas Ga2 (NH ₃ gas), is smaller than the supply amount of the NH ₃ gas in the surface modification step S105. Preferably, the high-resistance layer formation step S106, the supply amount of the NH ₃ gas, reducing than the supply amount of the NH ₃ gas in the stress generating layer forming step S104. By reducing the supply amount of the NH ₃ gas, since the uptake of carbon surface of the crystal rough gradually increases, the carbon concentration was once lowered by surface modification step S105, increasing again with the crystal growth be able to. That is, in the present embodiment, the amount of carbon uptake can be increased and the carbon concentration can be increased by controlling the surface morphology. As a result, the crystallinity of the nitride semiconductor substrate 100 can be improved while ensuring the withstand voltage.

As shown in FIG. 5, in the high resistance layer forming step S106, the growth temperature is preferably lower than the control temperatures of the outer peripheral side heater 361 and the inner peripheral side heater 362 in the surface modification step S105, and the stress generating layer forming step. It is more preferable that the temperature is about the same as the growth temperature in S104. As a result, the carbon concentration can be increased as the crystal grows. As a result, the high carbon region 250 can be present in the upper portion 230 of the high resistance layer 160. In the present specification, the same degree of growth temperature means, for example, that the temperature difference is ± 20 ° C. or less (preferably ± 10 ° C. or less, more preferably ± 5 ° C. or less).

As shown in FIG. 5, at the start of the high resistance layer forming step S106 (at the start of growth of the high resistance layer 160), TEG gas is used as the Ga raw material gas, and the supply amount of TEG gas is gradually reduced as the crystal grows. It is preferable to gradually increase the supply amount of TMG gas. The total supply amount of the group III raw material gas Ga1 can be kept constant. Although it depends on the growth conditions such as temperature and pressure, in many cases, in TEG gas, carbon in the raw material gas is less likely to be incorporated into the crystal than in TMG gas. Therefore, by using TEG gas at the start of growth of the high resistance layer 160, the carbon concentration in the vicinity of the interface 202 can be lowered. Further, by subsequently reducing the supply amount of TEG gas and increasing the supply amount of TMG gas, the carbon concentration can be increased as the crystal grows. As a result, the maximum value of the carbon concentration in the high carbon region 250 can be made to be about the same as the average carbon concentration of the stress generating layer 150.

In the high resistance layer forming step S106, the hydrogen concentration of the high resistance layer 160 may be selectively controlled by controlling the supply amount _{of the H 2 gas as the carrier gas Gb1.} Specifically, as shown in FIG. 5, in the high resistance layer forming step S106, it is preferable to increase the supply amount of _{H 2} gas and decrease the supply amount of _{N 2 gas as the carrier gas Gb1.} Thereby, the hydrogen concentration of the high resistance layer 160 can be selectively increased while maintaining the total pressure in the crystal growth apparatus 300. Normally, the high resistance layer 160 tends to have a lower hydrogen concentration than the stress generation layer 150. Therefore, by selectively increasing the hydrogen concentration of the high resistance layer 160, the stress generation layer 150 and the high resistance layer 160 can be combined. The difference in hydrogen concentration becomes small, and the density fluctuation between the layers of defects that act as traps can be suppressed.

In the high resistance layer forming step S106, the total supply amount of the group III raw material gas Ga1 may be increased. As a result, the crystal growth rate increases, so that the hydrogen concentration and the oxygen concentration can be lowered, respectively. Further, in the present embodiment, since the carbon concentration is increased by controlling the surface morphology as described above, the hydrogen concentration and the oxygen concentration can be decreased while increasing the carbon concentration.

In the high resistance layer forming step S106, it is preferable that the V / III ratio is constant during the growth of the high resistance layer 160. That is, in this step, it is preferable that the entire supply amount of the group III raw material gas Ga1 is constant and the supply amount of the group V raw material gas Ga2 is constant. As a result, the crystal growth rate in the high resistance layer forming step S106 becomes constant, so that the hydrogen concentration and the oxygen concentration in the high resistance layer 160 can be kept substantially constant.

(Low resistance layer forming step S107)
After the high resistance layer 160 is formed, the low resistance layer 170 is formed by growing AlGaN (preferably GaN) on the high resistance layer 160, for example, by the MOCVD method. In the low resistance layer forming step S107, the growth conditions are controlled so that the carbon concentration of the low resistance layer 170 is lower than the carbon concentration of the high resistance layer 160. Thereby, the electrical characteristics of the nitride semiconductor substrate 100 can be improved.

The growth temperature in the low resistance layer forming step S107 can be selected, for example, in the range of 900 ° C. or higher and 1260 ° C. or lower, and the V / III ratio can be selected in the range of 10 or more and 10000 ° C. or lower, for example.

(Barrier layer forming step S108)
After the low resistance layer 170 is formed, the barrier layer 180 is formed on the low resistance layer 170 by, for example, growing AlGaN by the MOCVD method.

The growth temperature in the barrier layer forming step S108 can be selected, for example, in the range of 900 ° C. or higher and 1260 ° C. or lower, and the V / III ratio can be selected in the range of 10 or more and 20000 ° C. or lower, for example.

Through the above steps, a nitride semiconductor substrate 100 having an impurity profile as shown in FIG. 2 can be obtained.

(3) Effects of the present embodiment According to the present embodiment, one or more of the following effects are exhibited.

(A) In the nitride semiconductor substrate 100 of the present embodiment, the average oxygen concentration of the high resistance layer 160 is, for example, less than ^{1 × 10 16} cm ^-3. Since oxygen acts as a donor in the high resistance layer 160, if the average oxygen concentration of the high resistance layer 160 is 1 × 10 ¹⁶ cm ^-3 or more, the withstand voltage of the nitride semiconductor substrate 100 may decrease. On the other hand, by setting the average oxygen concentration of the high resistance layer 160 to ^{less than 1 × 10 16} cm ^-3 , the withstand voltage of the nitride semiconductor substrate 100 can be improved.

(B) In the nitride semiconductor substrate 100 of the present embodiment, the fluctuation amount of the oxygen concentration of the high resistance layer 160 is, for example, ± 50% or less. By reducing the fluctuation amount of the oxygen concentration in the high resistance layer 160 in the thickness direction, the electrical characteristics of the nitride semiconductor substrate 100 can be stabilized.

(C) In the nitride semiconductor substrate 100 of the present embodiment, the low carbon region 240 having a carbon concentration of 70% or less (preferably 60% or less, more preferably 50% or less) of the average carbon concentration of the stress generating layer 150 is provided. , Located near the interface 202. Thereby, for example, the crystallinity of the upper layer portion 230 of the high resistance layer 160, the low resistance layer 170, and the barrier layer 180 can be improved.

(D) In the nitride semiconductor substrate 100 of the present embodiment, the minimum value of the carbon concentration in the low carbon region 240 is, for example, 3 × 10 ¹⁸ cm ^-3 or more (more preferably 5 × 10 ¹⁸ cm ^-3 or more, and more preferably 5 × 10 18 cm -3 or more. It is preferably 1 × 10 ¹⁹ cm ^-3 or more) 3 × 10 ¹⁹ cm ^-3 or less. As a result, it is possible to suppress a decrease in the withstand voltage of the nitride semiconductor substrate 100. Further, for example, the crystallinity of the upper layer portion 230 of the high resistance layer 160, the low resistance layer 170, and the barrier layer 180 can be improved.

(E) In the nitride semiconductor substrate 100 of the present embodiment, the thickness of the low carbon region 240 is preferably 2% or more and 50% or less of the thickness of the high resistance layer 160, for example. Thereby, for example, the crystallinity of the upper layer portion 230 of the high resistance layer 160, the low resistance layer 170, and the barrier layer 180 can be improved. Further, it is possible to suppress a decrease in the withstand voltage of the nitride semiconductor substrate 100.

(F) In the nitride semiconductor substrate 100 of the present embodiment, the low carbon region 240 preferably exists across the interface 200 between the stress generating layer 150 and the high resistance layer 160. As a result, a nitride semiconductor crystal having good crystallinity can be grown from the start of growth of the high resistance layer 160.

(G) In the nitride semiconductor substrate 100 of the present embodiment, the high carbon region 250 having a carbon concentration of 70% or more (preferably 80% or more, more preferably 90% or more) of the average carbon concentration of the stress generating layer 150 is provided. , Exists in the upper portion 230 of the high resistance layer 160. Thereby, the withstand voltage of the nitride semiconductor substrate 100 can be improved.

(H) In the nitride semiconductor substrate 100 of the present embodiment, the maximum value of the carbon concentration in the high carbon region 250 is preferably, for example, 95% or more and 120% or less of the average carbon concentration of the stress generating layer 150. Thereby, the withstand voltage of the nitride semiconductor substrate 100 can be further improved. Further, since the carrier density difference between the high resistance layer 160 and the stress generating layer 150 becomes small, the electrical characteristics of the nitride semiconductor substrate 100 can be stabilized.

<Other Embodiments of the Present Invention>
Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof.

In the above-described embodiment, the nitride semiconductor layer 120 is composed of the reaction suppressing layer 130, the intermediate layer 140, the stress generating layer 150 as the first layer, and the high resistance layer as the second layer in this order from the silicon substrate 110 side. Although the case where the 160, the low resistance layer 170 as the third layer, and the barrier layer 180 are provided has been described, the present invention is not limited to this embodiment. For example, a transition layer or the like that does not adversely affect the effects of the present invention may be inserted between the layers constituting the nitride semiconductor layer 120.

Further, for example, a cap layer made of GaN can be provided on the barrier layer 180. Magnesium may be added to the cap layer to obtain p-type electrical conductivity. By providing such a cap layer, the threshold voltage can be set to the positive side, and the normalization off operation becomes easy.

Further, the present invention may be an embodiment of a semiconductor device formed of a nitride semiconductor substrate 100 as a material. More specifically, for example, it may be an embodiment of a high electron mobility transistor (HEMT) in which a source electrode, a gate electrode, a drain electrode and the like are provided on the nitride semiconductor layer 120.

<Preferable Aspect of the Present Invention>
Hereinafter, preferred embodiments of the present invention will be added.

(Appendix 1)
According to one aspect of the invention
A nitride semiconductor substrate in which a nitride semiconductor layer is laminated on a silicon substrate.
The nitride semiconductor layer is
A first layer formed by laminating a plurality of nitride semiconductor crystal layers having different compositions, and
A second layer formed on the first layer and containing carbon is provided.
Provided is a nitride semiconductor substrate in which the average carbon concentration of the lower portion of the second layer is lower than the average carbon concentration of the upper portion of the second layer.
Preferably, the first layer is a strain superlattice in which a first nitride semiconductor crystal layer and a second nitride semiconductor crystal layer having a larger lattice constant than the first nitride semiconductor crystal layer are alternately laminated. It has a lattice structure.
Preferably, the nitride semiconductor layer further includes a third layer formed on the second layer and having an average carbon concentration lower than the average carbon concentration of the second layer.

(Appendix 2)
The nitride semiconductor substrate according to Appendix 1, wherein the nitride semiconductor substrate is used.
The average carbon concentration of the lower portion of the second layer is lower than the average carbon concentration of the first layer.
Preferably, the average carbon concentration of the first layer is 2 × 10 ¹⁹ cm ^-3 or more and 8 × 10 ¹⁹ cm ^-3 or less.

(Appendix 3)
The nitride semiconductor substrate according to Appendix 1 or Appendix 2, wherein the nitride semiconductor substrate is used.
A low carbon region having a carbon concentration of 70% or less (preferably 60% or less, more preferably 50% or less) of the average carbon concentration of the first layer is located near the interface between the first layer and the second layer. exist.

(Appendix 4)
The nitride semiconductor substrate according to Appendix 3, wherein the nitride semiconductor substrate is used.
The minimum value of carbon concentration in the low carbon region is 3 × 10 ¹⁸ cm ^-3 or more (preferably 5 × 10 ¹⁸ cm ^-3 or more, more preferably 1 × 10 ¹⁹ cm ^-3 or more) 3 × 10 ¹⁹ cm ^{−. It is 3} or less.

(Appendix 5)
The nitride semiconductor substrate according to Appendix 3 or Appendix 4, wherein the nitride semiconductor substrate is used.
The thickness of the low carbon region is 2% or more and 50% or less of the thickness of the second layer.

(Appendix 6)
The nitride semiconductor substrate according to any one of Supplementary note 3 to Supplementary note 5.
The low carbon region exists across the interface between the first layer and the second layer.

(Appendix 7)
The nitride semiconductor substrate according to any one of Supplementary note 1 to Supplementary note 6.
A high carbon region having a carbon concentration of 70% or more (preferably 80% or more, more preferably 90% or more) of the average carbon concentration of the first layer exists in the upper layer portion of the second layer.

(Appendix 8)
The nitride semiconductor substrate according to Appendix 7, wherein the nitride semiconductor substrate is used.
The maximum value of the carbon concentration in the high carbon region is 95% or more and 120% or less of the average carbon concentration of the first layer.

(Appendix 9)
According to another aspect of the invention
A nitride semiconductor substrate in which a nitride semiconductor layer is laminated on a silicon substrate.
The nitride semiconductor layer is
A first layer formed by laminating a plurality of nitride semiconductor crystal layers having different compositions, and
A second layer formed on the first layer and containing carbon is provided.
Provided is a nitride semiconductor substrate in which the average hydrogen concentration of the second layer is 15% or more and 100% or less of the average hydrogen concentration of the first layer.
Preferably, the first layer is a strain superlattice in which a first nitride semiconductor crystal layer and a second nitride semiconductor crystal layer having a larger lattice constant than the first nitride semiconductor crystal layer are alternately laminated. It has a lattice structure.
Preferably, the nitride semiconductor layer further includes a third layer formed on the second layer and having an average carbon concentration lower than the average carbon concentration of the second layer.
Preferably, the average hydrogen concentration of the second layer is 4 × 10 ¹⁷ cm ^-3 or more and 1 × 10 ¹⁸ cm ^-3 or less.

(Appendix 10)
The nitride semiconductor substrate according to Appendix 9, wherein the nitride semiconductor substrate is used.
The fluctuation amount of the hydrogen concentration in the second layer is ± 20% or less.

(Appendix 11)
The nitride semiconductor substrate according to Appendix 9 or Appendix 10, wherein the nitride semiconductor substrate is used.
The average carbon concentration of the lower portion of the second layer is lower than the average carbon concentration of the upper portion of the second layer.

(Appendix 12)
The nitride semiconductor substrate according to any one of Supplementary note 9 to Supplementary note 11.
The average carbon concentration of the lower portion of the second layer is lower than the average carbon concentration of the first layer.
Preferably, the average carbon concentration of the first layer is 2 × 10 ¹⁹ cm ^-3 or more and 8 × 10 ¹⁹ cm ^-3 or less.

(Appendix 13)
The nitride semiconductor substrate according to any one of Supplementary note 9 to Supplementary note 12.
A low carbon region having a carbon concentration of 70% or less (preferably 60% or less, more preferably 50% or less) of the average carbon concentration of the first layer is located near the interface between the first layer and the second layer. exist.

(Appendix 14)
The nitride semiconductor substrate according to Appendix 13, wherein the nitride semiconductor substrate is used.
The minimum value of carbon concentration in the low carbon region is 3 × 10 ¹⁸ cm ^-3 or more (preferably 5 × 10 ¹⁸ cm ^-3 or more, more preferably 1 × 10 ¹⁹ cm ^-3 or more) 3 × 10 ¹⁹ cm ^{−. It is 3} or less.

(Appendix 15)
The nitride semiconductor substrate according to Appendix 13 or Appendix 14, wherein the nitride semiconductor substrate is used.
The thickness of the low carbon region is 2% or more and 50% or less of the thickness of the second layer.

(Appendix 16)
The nitride semiconductor substrate according to any one of Supplementary note 13 to Supplementary note 15.
The low carbon region exists across the interface between the first layer and the second layer.

(Appendix 17)
The nitride semiconductor substrate according to any one of Supplementary note 9 to Supplementary note 16.
A high carbon region having a carbon concentration of 70% or more (preferably 80% or more, more preferably 90% or more) of the average carbon concentration of the first layer exists in the upper layer portion of the second layer.

(Appendix 18)
The nitride semiconductor substrate according to Appendix 17, wherein the nitride semiconductor substrate is used.
The maximum value of the carbon concentration in the high carbon region is 95% or more and 120% or less of the average carbon concentration of the first layer.

(Appendix 19)
According to another aspect of the invention
A nitride semiconductor substrate in which a nitride semiconductor layer is laminated on a silicon substrate.
The nitride semiconductor layer is
A first layer formed by laminating a plurality of nitride semiconductor crystal layers having different compositions, and
A second layer formed on the first layer and containing carbon is provided.
A nitride semiconductor substrate is provided in which the average oxygen concentration of the second layer is ^{less than 1 × 10 16} cm ^-3.
Preferably, the first layer is a strain superlattice in which a first nitride semiconductor crystal layer and a second nitride semiconductor crystal layer having a larger lattice constant than the first nitride semiconductor crystal layer are alternately laminated. It has a lattice structure.
Preferably, the nitride semiconductor layer further includes a third layer formed on the second layer and having an average carbon concentration lower than the average carbon concentration of the second layer.
Preferably, the average oxygen concentration of the second layer is 1 × 10 ¹⁵ cm ^-3 or more.

(Appendix 20)
The nitride semiconductor substrate according to Appendix 19, wherein the nitride semiconductor substrate is used.
The amount of fluctuation in the oxygen concentration of the second layer is ± 50% or less.

(Appendix 21)
The nitride semiconductor substrate according to Appendix 19 or Appendix 20.
The average carbon concentration of the lower portion of the second layer is lower than the average carbon concentration of the upper portion of the second layer.
Preferably, the average carbon concentration of the second layer is 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less.

(Appendix 22)
The nitride semiconductor substrate according to any one of Supplementary note 19 to Supplementary note 21.
The average carbon concentration of the lower portion of the second layer is lower than the average carbon concentration of the first layer.
Preferably, the average carbon concentration of the first layer is 2 × 10 ¹⁹ cm ^-3 or more and 8 × 10 ¹⁹ cm ^-3 or less.

(Appendix 23)
The nitride semiconductor substrate according to any one of Supplementary note 19 to Supplementary note 22.
A low carbon region having a carbon concentration of 70% or less (preferably 60% or less, more preferably 50% or less) of the average carbon concentration of the first layer is located near the interface between the first layer and the second layer. exist.

(Appendix 24)
The nitride semiconductor substrate according to Appendix 23.
The minimum value of carbon concentration in the low carbon region is 3 × 10 ¹⁸ cm ^-3 or more (preferably 5 × 10 ¹⁸ cm ^-3 or more, more preferably 1 × 10 ¹⁹ cm ^-3 or more) 3 × 10 ¹⁹ cm ^{−. It is 3} or less.

(Appendix 25)
The nitride semiconductor substrate according to Appendix 23 or Appendix 24, wherein the nitride semiconductor substrate is used.
The thickness of the low carbon region is 2% or more and 50% or less of the thickness of the second layer.

(Appendix 26)
The nitride semiconductor substrate according to any one of Supplementary note 23 to Supplementary note 25.
The low carbon region exists across the interface between the first layer and the second layer.

(Appendix 27)
The nitride semiconductor substrate according to any one of Supplementary note 19 to Supplementary note 26.
A high carbon region having a carbon concentration of 70% or more (preferably 80% or more, more preferably 90% or more) of the average carbon concentration of the first layer exists in the upper layer portion of the second layer.

(Appendix 28)
The nitride semiconductor substrate according to Appendix 27.
The maximum value of the carbon concentration in the high carbon region is 95% or more and 120% or less of the average carbon concentration of the first layer.

100 Nitride semiconductor substrate 110 Silicon substrate 120 Nitride semiconductor layer 130 Reaction suppression layer 140 Intermediate layer 150 Stress generation layer 151 First nitride semiconductor crystal layer 152 Second nitride semiconductor crystal layer 153 Multilayer crystal layer 160 High resistance layer 170 Low resistance layer 180 Barrier layer 200 Interface 201 Upper 202 Interface Near 210 Interface 220 Lower layer 230 Upper layer 240 Low carbon region 250 High carbon region 300 Crystal growth device 310 Reactor 320 Suceptor 330 Rotating mechanism 331 Opening 341 Suceptor cover 342 Heaven Plate 350 Space 351 Space 361 Outer peripheral side heater 362 Inner peripheral side heater 370 Control unit S101 Substrate preparation step S102 Reaction suppression layer forming step S103 Intermediate layer forming step S104 Stress generating layer forming step S105 Surface modification step S106 High resistance layer forming step S107 Low resistance layer forming step S108 Barrier layer forming step

Claims (10)

A nitride semiconductor substrate in which a nitride semiconductor layer is laminated on a silicon substrate.
The nitride semiconductor layer is
A first layer formed by laminating a plurality of nitride semiconductor crystal layers having different compositions, and
A second layer formed on the first layer and containing carbon is provided.
A nitride semiconductor substrate having an average oxygen concentration of ^{less than 1 × 10 16} cm ^{-3 in the second layer.} The nitride semiconductor substrate according to claim 1, wherein the fluctuation amount of the oxygen concentration in the second layer is ± 50% or less. The nitride semiconductor substrate according to claim 1 or 2, wherein the average carbon concentration of the lower layer portion of the second layer is lower than the average carbon concentration of the upper layer portion of the second layer. The nitride semiconductor substrate according to any one of claims 1 to 3, wherein the average carbon concentration of the lower portion of the second layer is lower than the average carbon concentration of the first layer. Any one of claims 1 to 4, wherein a low carbon region having a carbon concentration of 70% or less of the average carbon concentration of the first layer exists in the vicinity of the interface between the first layer and the second layer. The nitride semiconductor substrate according to the above. The nitride semiconductor substrate according to claim 5, wherein the minimum value of the carbon concentration in the low carbon region is 3 × 10 ¹⁸ cm ^-3 or more and 3 × 10 ¹⁹ cm ^{-3 or less.} The nitride semiconductor substrate according to claim 5 or 6, wherein the thickness of the low carbon region is 2% or more and 50% or less of the thickness of the second layer. The nitride semiconductor substrate according to any one of claims 5 to 7, wherein the low carbon region is present across the interface between the first layer and the second layer. The nitride according to any one of claims 1 to 8, wherein a high carbon region having a carbon concentration of 70% or more of the average carbon concentration of the first layer exists in the upper layer portion of the second layer. Semiconductor substrate. The nitride semiconductor substrate according to claim 9, wherein the maximum value of the carbon concentration in the high carbon region is 95% or more and 120% or less of the average carbon concentration of the first layer.

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