JP2021144694A - Information processing device, memory control program, information processing program and information processing method - Google Patents

Abstract

To provide a technique for reducing a load of a processor by reducing the occurrence of a spinlock.SOLUTION: A computer system 1a includes: a primary memory 30 for storing data of a page unit; a secondary memory 20 for storing data of a page being a moving object from the primary memory; and a movement processing part for moving a first management information storage area 31 provided in each of a plurality of arithmetic cores 11 to store a plurality of first links 33 showing a movement order of each page in a page group allocated to each of the plurality of arithmetic cores 11 in a plurality of pages, a second management information storage area 31 provided for an operating system to store a second link 32 for managing a plurality of pages selected according to a movement order from the page group in the plurality of first links as a candidate page group to be moved to the secondary memory from the primary memory to the secondary memory.SELECTED DRAWING: Figure 1

Description

The present invention relates to an information processing device, a memory control program, an information processing program, and an information processing method.

Hierarchical memory control is sometimes used in which the memory space visible to the application is divided into high-speed memory and low-speed memory and layered. In tiered memory control, there is known a memory expansion technique that makes it possible to use a memory larger than the capacity of a DRAM (Dynamic Random Access Memory) by using a storage such as an SSD (Solid State Drive) as a low-speed memory.
In such a memory expansion technique, it is generally practiced to use a part of the DRAM as a cache memory of a low-speed memory.

The cache memory is managed on a page-by-page basis. The data size of the page is, for example, 4KB. The process of moving a page from cache memory to storage is performed by a background thread.
The data (page) to be moved from the cache memory to the storage is selected by the LRU (Least Recently Used) algorithm.

The LRU list is used to manage the priority of pages moved to storage. The LRU list stores a pointer to a page structure in which page information (address, etc.) is stored, an access flag indicating that the page has been accessed, and list link information.

Then, referring to the LRU list configured in this way, the page that has not been accessed for the longest time is determined as the page to be moved (cached out) to the storage.

Japanese Unexamined Patent Publication No. 2008-27444 Japanese Unexamined Patent Publication No. 2019-95881

In a multi-core CPU including a plurality of CPU (Central Processing Unit) cores, a plurality of threads (multi-threads) executed by the plurality of CPU cores access the LRU list. In addition, the thread that identifies the page to be moved from the cache memory to the storage also accesses to refer to the LRU list.

Therefore, when one thread accesses the LRU list, exclusive control that locks the LRU list is required to prevent the LRU list from being modified by another thread. When a thread tries to refer to the LRU list, if the LRU list is locked, the thread performs a spinlock and waits until the lock of the LRU list is released.

In such a conventional hierarchical memory control method, there is a problem that the CPU load due to the spinlock increases due to the exclusive processing by locking the LRU list, and the performance deteriorates.
In one aspect, the invention reduces the load on the processor by reducing the occurrence of spinlocks.

Therefore, this information processing device is a processor having a plurality of arithmetic cores, a primary memory for storing page-based data, a secondary memory for storing data of a page to be moved from the primary memory, and a plurality of arithmetic cores. And, a plurality of first links provided for each of the plurality of arithmetic cores and indicating the order of movement of each page in the page group assigned to each of the plurality of arithmetic cores among the plurality of pages are stored. A plurality of pages provided for the first management information storage area and the operating system and selected according to the order of movement from the page group in the plurality of first links are moved to the secondary memory. The second management information storage area for storing the second link managed as the candidate page group and the data of the page selected from the page group of the second link are moved from the primary memory to the secondary memory. It is equipped with a movement processing unit.

According to one embodiment, the load on the processor can be reduced by reducing the occurrence of spinlock.

It is a figure which shows typically the structure of the computer system as an example of 1st Embodiment. It is a figure for demonstrating the hierarchical memory control in the computer system as an example of 1st Embodiment. It is a figure for demonstrating the operation relation between the LRU list for every CPU core and the LRU list for OS in the computer system as an example of 1st Embodiment. It is a figure for demonstrating the DRAM area which the LRU list for every CPU core and the LRU list for an OS respectively target in the computer system as an example of 1st Embodiment. It is a figure which illustrates the movement information table in the computer system as an example of 1st Embodiment. It is a figure for demonstrating the page management method in the computer system as an example of 1st Embodiment. It is a flowchart for demonstrating the update process of the LRU list for every CPU core by a thread in the computer system as an example of 1st Embodiment. It is a flowchart for demonstrating the process by the page movement thread in the computer system as an example of 1st Embodiment. It is a flowchart for demonstrating the process by the page movement thread attached to the OS in the computer system as an example of 1st Embodiment. It is a flowchart for demonstrating the process by the list deletion thread in the computer system as an example of 1st Embodiment. It is a figure which shows typically the structure of the computer system as an example of 2nd Embodiment. It is a figure which illustrates the page correspondence table in the computer system as an example of 2nd Embodiment. It is a figure for demonstrating the page management method in the computer system as an example of 2nd Embodiment. It is a flowchart for demonstrating the update process of the LRU list for every CPU core by a thread in the computer system as an example of 2nd Embodiment. It is a flowchart for demonstrating the process by the page movement thread in the computer system as an example of 2nd Embodiment. It is a flowchart for demonstrating the process by the page movement thread attached to OS in the computer system as an example of 2nd Embodiment. It is a figure which shows typically the structure of the computer system as an example of 3rd Embodiment. It is a figure for demonstrating the page management method in the computer system as an example of 3rd Embodiment. It is a flowchart for demonstrating the update process of the LRU list for every CPU core by a thread in the computer system as an example of 3rd Embodiment. It is a flowchart for demonstrating the process by the page movement thread in the computer system as an example of 3rd Embodiment. It is a flowchart for demonstrating the process by the page movement thread attached to the OS in the computer system as an example of 3rd Embodiment. It is a figure which illustrates the functional structure of the computer system as an example of 4th Embodiment. It is a figure for demonstrating the process of the cache redistribution determination part of the computer system as an example of 4th Embodiment. It is a flowchart for demonstrating the page movement process in the computer system as an example of 4th Embodiment.

Hereinafter, embodiments relating to the information processing apparatus, the memory control program, the information processing program, and the information processing method will be described with reference to the drawings. However, the embodiments shown below are merely examples, and there is no intention of excluding the application of various modifications and techniques not specified in the embodiments. That is, the present embodiment can be implemented by various modifications (combining the embodiments and each modification) within a range that does not deviate from the purpose. Further, each figure does not mean that it includes only the components shown in the figure, but may include other functions and the like.

[1. Description of the first embodiment]
(A) Configuration FIG. 1 is a diagram schematically showing a configuration of a computer system 1a as an example of the first embodiment.
The computer system 1a illustrated in FIG. 1 includes a processor 10, an SSD 20, and a DRAM 30.

The processor 10 is a multi-core processor including a plurality of CPU cores 11-0, 11-1, 11-2 .... Hereinafter, when the CPU cores 11-0, 11-1, 11-2, ... Are not particularly distinguished, they are referred to as CPU cores 11. Further, the CPU core 11-0 may be referred to as the CPU core # 0. Similarly, the CPU core 11-1 may be referred to as a CPU core # 1, and the CPU core 11-2 may be referred to as a CPU core # 2.
Each CPU core 11 is an arithmetic core that executes a thread.

Further, the processor 10 includes a PCIe root (Peripheral Component Interconnect Express Root) port 12 and a memory controller 13.

The SSD 20 is connected to the PCIe root port 12, and the DRAM 30 is connected to the memory controller 13. The SSD 20 may be connected according to the NVMe (Non-Volatile Memory Express) standard, and can be modified in various ways.
The computer system 1a realizes hierarchical memory control.
FIG. 2 is a diagram for explaining hierarchical memory control in the computer system 1a as an example of the first embodiment.

In the hierarchical memory control, the DRAM 30 is used as the high-speed memory and the SSD 20 is used as the low-speed memory. Further, a part of the storage area of the DRAM 30 is used as a cache memory (hereinafter, may be simply referred to as a cache) 30a.

The cache 30a is managed on a page-by-page basis. The data size of the page is, for example, 4KB. The process of moving the page from the cache 30a to the storage is executed by the page movement thread described later. The cache 30a corresponds to a primary memory in which data for each page is stored.

In the computer system 1a, the data (page) to be moved from the cache 30a to the SSD 20 is selected by the LRU algorithm, and the selected page is moved from the cache 30a to the SSD 20.

The SSD 20 is a storage device using a semiconductor element memory, and as described above, a part of the storage area is used as a memory (low-speed memory).

Further, in the storage area of the SSD 20, pages moved from the cache 30a, which will be described later, are stored in an area other than the area used as the low-speed memory. The process of moving the page on the cache 30a to the SSD 20 may be referred to as cache-out, or may be referred to as eviction process or collection process. The SSD 20 corresponds to a secondary memory for storing the data of the page to be moved from the cache 30a.

The page ejected from the cache 30a is stored in the SSD 20. The page that has been expelled from the cache 30a and moved to the SSD 20 may be referred to as movement data. In the example shown in FIG. 1, the page of each CPU core 11 expelled from the cache 30a is stored as movement data 21.
The DRAM 30 is a semiconductor storage memory, which is a memory capable of faster data access than the SSD 20.

A part of the storage area of the DRAM 30 is used as a high-speed memory by an application executed by the CPU core 11, and the other part of the storage area is used as a cache memory (cache) 30a by the application.
In the example shown in FIG. 1, the storage area of the DRAM 30 includes a kernel area 31 and a user area 36.

The user area 36 is, for example, a storage area used by an application executed by each CPU core 11, and data 37 used by each CPU core 11 is stored.

The kernel area 31 is a storage area used by the kernel of the OS (Operating System) executed by the CPU core 11. In this embodiment, an example in which the OS is Linux (registered trademark) is shown.

In the example shown in FIG. 1, the LRU list 32 for the OS, the movement information table 34, and the LRU list 33-0, 33-1 for each CPU core are stored in the kernel area 31.

--LRU list 33 for each CPU core--
The LRU list 33-0, 33-1, ... For each CPU core is an LRU list provided for each CPU core 11.

The LRU list 33 for each CPU core has, for example, a data structure (list structure) in which link elements called structures are sequentially concatenated by pointers. The LRU list 33 for each CPU core is provided for each CPU core 11 and corresponds to a plurality of first links indicating the order of movement of each page in the page group assigned to each of the plurality of CPU cores 11 among the plurality of pages. do. Further, the kernel area 31 of the DRAM 30 that stores the LRU list 33 for each CPU core corresponds to the first management information storage area that stores the first link.

In the example shown in FIG. 1, the LRU list 33-0 for each CPU core is provided for the CPU core 11-0, and the LRU list 33-1 for each CPU core is provided for the CPU core 11-1. It is a thing. The number of LRU lists 33 for each CPU core is the same as that of the CPU cores 11 provided in the processor 10.

Hereinafter, the LRU list 33-0 for each CPU core may be referred to as the LRU list 33-0 for CPU core # 0. Similarly, the LRU list 33-1 for each CPU core may be represented as the LRU list 33-1 for CPU core # 1. Further, hereinafter, when these CPU core LRU lists 33-0, 33-1, ... Are not particularly distinguished, they are referred to as CPU core LRU list 33.

In the computer system 1a of the first embodiment, an LRU list 33 for each CPU core is provided for each CPU core 11. The LRU list 33 for each CPU core stores information about the page on which data access occurred when the CPU core 11 executes a thread. For example, the LRU list 33 for each CPU core contains a pointer to a page structure in which page information (address, etc.) is stored, an access flag indicating that the page has been accessed, and list link information. It is stored.

The LRU list 33 for each CPU core manages the pages for which data has been accessed by the CPU core 11 according to the LRU algorithm. In the LRU list 33 for each CPU core, the page on which the data access has occurred is managed according to the time when the page is not referenced. By referring to the LRU list 33 for each CPU core, it is possible to know the page accessed by the CPU core 11 in the past, that is, the page that has not been referenced by the CPU core 11 for the longest time.

The page moving thread 101 (details will be described later) executed by each CPU core 11 refers to the LRU list 33 for each CPU core, and the CPU core 11 (hereinafter referred to as own CPU core 11) that executes the page moving thread 101. Identify the page with the longest unreferenced time (may be). Then, the specified page is selected as a movement candidate page to be moved from the cache 30a to the SSD 20.

--LRU list for OS 32--

The OS LRU list 32 manages the movement candidate pages selected from the LRU list 33 for each CPU core by the LRU algorithm. That is, in the OS LRU list 32, the page movement thread 101 executed by each CPU core 11 manages the movement candidate pages selected from the LRU list 33 for each CPU core of the own CPU core 11.

The OS LRU list 32 is an LRU list used by the page moving thread 101 (details will be described later) provided as a standard function in the OS. It can be said that the LRU list 32 for the OS is an LRU list provided for the OS. The OS LRU list 32 may be referred to as a Linux LRU list 32. The OS LRU list 32 is provided for the operating system, and is a candidate for moving a plurality of pages selected according to the movement order from the page groups in the plurality of CPU cores LRU list 33 to the SSD 20. It corresponds to the second link managed as a page group. Further, the kernel area 31 of the DRAM 30 that stores the OS LRU list 32 corresponds to the second management information storage area that stores the second link.

The OS LRU list 32 corresponds to a second link indicating a candidate page group managed by the OS, selected from a plurality of CPU core LRU lists 33, and moved to the SSD 20.

The page movement thread 101 identifies the movement candidate page having the longest unreferenced time from the movement candidate pages registered in the OS LRU list 32 according to the LRU algorithm, and selects the movement candidate page as the movement target page. The page movement thread 101 stores the selected movement target page in the SSD 20.

FIG. 3 is a diagram for explaining the operation relationship between the LRU list 33 for each CPU core and the LRU list 32 for the OS in the computer system 1a as an example of the first embodiment.

The page movement thread 101, which will be described later, selects a movement target page from a plurality of movement candidate pages managed in the LRU list 33 for each CPU core, and inputs the movement target page to the OS LRU list 32 for moving the movement target page to the SSD 20. (See reference numeral P1 in FIG. 3).

The OS-attached page movement thread 102, which will be described later, selects a movement target page from a plurality of movement candidate pages managed in the LRU list 33 for each CPU core, and moves the movement target page to the SSD 20 (reference numeral P2 in FIG. 3). reference).

FIG. 4 is a diagram for explaining a DRAM area targeted by the LRU list 33 for each CPU core and the LRU list 32 for the OS in the computer system 1a as an example of the first embodiment.

As shown in FIG. 4, the LRU list 33 for each CPU core manages only the cache 30a. That is, only the pages on the cache 30a are managed by the LRU list 33 for each CPU core.

On the other hand, the OS LRU list 32 manages the entire storage area (total DRAM area) of the DRAM 30. That is, the pages on the storage area of the DRAM 30 are managed by the OS LRU list 32.
FIG. 5 is a diagram illustrating a movement information table 34 in the computer system 1a as an example of the first embodiment.

The movement information table 34 is information for managing whether or not the page has been moved to the SSD 20, and is configured by associating each page with information indicating whether or not the page has been moved to the SSD 20.

The movement information table 34 illustrated in FIG. 5 is configured by associating a movement flag with information that identifies a page. The information for identifying the page may be the address of the page, or may be the identification information set for each page, and can be implemented by various modifications.

The move flag is information indicating whether or not the page has been moved to SSD20. For example, if the page has not been moved to SSD20 (not moved), "0" is set, and the page has been moved to SSD20 (moved). In that case, "1" is set respectively. That is, the page in which the movement flag is set to "1" in the movement information table 34 is a moved page.

The movement information table 34 corresponds to the movement management information that manages the pages moved to the SSD 20 by the page movement thread 102 attached to the OS. Further, the DRAM 30 that stores the movement information table 34 corresponds to a storage unit that stores the movement information table 34.
FIG. 6 is a diagram for explaining a page management method in the computer system 1a as an example of the first embodiment.
In the computer system 1a of the first embodiment, each CPU core 11 is provided with an LRU list 33 for each CPU core.
In the example shown in FIG. 6, the processor 10 is configured as a 4-core processor including CPU cores # 0 to # 3.

In the computer system 1a of the first embodiment, it is assumed that no data is shared between the CPU cores 11. Further, the control of the LRU list 33 for each CPU core is performed independently for each CPU core 11, and the page moving thread 102 attached to the OS does not access the LRU list 33 for each CPU core.

In the computer system 1a of the first embodiment, each CPU core # 0 to # 3 executes a thread 104, a page movement thread 101, and a list deletion thread 103, respectively.
Further, among the CPU cores # 0 to # 3, for example, any CPU core 11 preset as the primary executes the OS-attached page movement thread 102.
Further, the movement information table 34 and the OS LRU list 32 are stored in the kernel area 31 of the DRAM 30 (see FIG. 1).

As described above, the LRU list 33 for each CPU core is provided corresponding to each CPU core 11. That is, the LRU list 33-0 for CPU core # 0 corresponds to CPU core # 0, and the LRU list 33-1 for CPU core # 1 corresponds to CPU core # 1 and corresponds to CPU core # 2. The LRU list 33-2 for CPU core # 2 is provided, and the LRU list 33-3 for CPU core # 3 is provided corresponding to the CPU core # 3.

Then, for example, the LRU list 33-0 for CPU core # 0 is accessed only from the thread 104, the page moving thread 101, and the list deletion thread 103 executed by the CPU core # 0.
That is, the LRU list 33-0 for each CPU core is accessed only from the CPU core # 0, and is not accessed from the other CPU cores # 1 to # 3.

Similarly, the LRU list 33-1 for each CPU core is accessed only from the thread 104 executed by the CPU core # 1, the page moving thread 101, and the list deletion thread 103. That is, the LRU list 33-1 for each CPU core is accessed only from the CPU core # 1, and is not accessed from the other CPU cores # 0, # 2, and # 3.

Further, the LRU list 33-2 for each CPU core is accessed only from the thread 104 executed by the CPU core # 2, the page moving thread 101, and the list deletion thread 103. That is, the LRU list 33-2 for each CPU core is accessed only from the CPU core # 2, and is not accessed from the other CPU cores # 0, # 1, and # 3.

Further, the LRU list 33-3 for each CPU core is accessed only from the thread 104 executed by the CPU core # 3, the page moving thread 101, and the list deletion thread 103. That is, the LRU list 33-3 for each CPU core is accessed only from the CPU core # 3, and the access from the other CPU cores # 0 to # 2 does not occur.
Here, the page management method in the computer system 1a of the first embodiment will be described by taking the processing performed in the CPU core # 0 as an example.

CPU core # 0 realizes arithmetic processing by executing thread 104. Thread 104 performs processing such as updating the access flag and adding a new page to the LRU list 33-0 for CPU core # 0 (see reference numeral S1 in FIG. 6).
Hereinafter, the fact that the CPU core 11 realizes some processing by executing the thread 104 may be expressed as the thread 104 realizing the processing.

The CPU core # 0 refers to the LRU list 33-0 for the CPU core # 0 by executing the page movement thread 101, and the LRU algorithm is selected from the pages registered in the LRU list 33 for the CPU core # 0. Select a move candidate page based on (see reference numeral S2 in FIG. 6).

Hereinafter, the fact that the CPU core 11 realizes some processing by executing the page movement thread 101 may be expressed as the page movement thread 101 realizing the processing.
The page movement thread 101 adds the selected movement candidate page to the OS LRU list 32 (see reference numeral S3 in FIG. 6).

The CPU core 11 refers to the LRU list 32 for the OS by executing the page movement thread 102 attached to the OS, and among the movement candidate pages registered in the LRU list 32 for the OS, the movement target page based on the LRU algorithm. Is selected (see reference numeral S4 in FIG. 6). Hereinafter, the fact that the CPU core 11 realizes some processing by executing the OS-attached page movement thread 102 may be expressed as the OS-attached page movement thread 102 realizing the processing.
Then, the OS-attached page movement thread 102 moves the selected movement target page to the SSD 20 (see reference numeral S5 in FIG. 6).

The CPU core 11 that executes the OS-attached page movement thread 102 corresponds to a movement processing unit that moves the data of the page selected from the page group of the OS LRU list 32 from the cache 30a to the SSD 20.

Further, the page movement thread 102 attached to the OS registers the page (moved page) moved to the SSD 20 in the movement information table 34 (see reference numeral S6 in FIG. 6). For example, the page movement thread 102 attached to the OS sets (sets a flag) “1” in the movement flag of the page in the movement information table 34.

By executing the list deletion thread 103, the CPU core # 0 deletes the page in the movement information table 34 in which the movement flag is "1" among the pages in the LRU list 33 for each CPU core. .. Hereinafter, the fact that the CPU core 11 realizes some processing by executing the list deletion thread 103 may be expressed as the list deletion thread 103 realizing the processing.

Specifically, the list deletion thread 103 refers to the movement information table 34, and is registered in the moved page registered in the movement information table 34 and the LRU list 33-0 for CPU core # 0 managed by itself. Compare with the move candidate page. Then, among the movement candidate pages registered in the LRU list 33-0 for CPU core # 0, the page matching the moved page registered in the movement information table 34 is deleted.

The list deletion thread 103 knows the moved table by referring to the movement information table 34, and deletes the moved page from the LRU list 33 for each CPU core (see reference numeral S7 in FIG. 6). The page movement thread 101 may execute the process by the list deletion thread 103 described above. Access to the movement information table 34 can be realized by lightweight exclusive processing, and atomic access can be realized.

The CPU core 11 that executes the list deletion thread 103 is provided for each of the plurality of CPU cores 11, and refers to the movement information table 34 to delete the page moved to the SSD 20 from the LRU list 33 for each CPU core. Corresponds to the department.
Similar processing is performed on the other CPU core 11.

(B) Operation The update process of the LRU list 33 for each CPU core by the thread 104 in the computer system 1a as an example of the first embodiment configured as described above will be described with reference to the flowcharts (steps A1 to A6) shown in FIG. ..

In step A1, the thread 104 confirms whether to allocate a page in the memory area. As a result of the confirmation, if the page is secured (see the YES route in step A1), the process proceeds to step A2.
In step A2, thread 104 allocates pages to thread 104 and updates the LRU list 33 for each CPU core.

In step A3, the thread 104 confirms whether the memory usage exceeds a predetermined threshold value (constant amount). As a result of the confirmation, when the amount exceeds a certain amount (see the YES route in step A3), the thread 104 activates the page movement thread 101 in step A4.

After that, the process proceeds to step A5. Further, as a result of the confirmation in step A1, even if the thread 104 does not allocate a page in the memory area (see the NO route in step A1), the process proceeds to step A5.

In step A5, thread 104 confirms whether the memory has been accessed. As a result of the confirmation, when there is a memory access (see the YES route in step A5), the process proceeds to step A6, and the LRU list 33 for each CPU core is updated. After that, the process returns to step A1.
If, as a result of the confirmation in step A3, the memory usage does not exceed a certain amount (see the NO route in step A3), the process proceeds to step A5.
If, as a result of the confirmation in step A5, there is no memory access by the thread 104 (see the NO route in step A5), the process returns to step A1.

Next, the process by the page movement thread 101 in the computer system 1a as an example of the first embodiment will be described with reference to the flowcharts (steps A11 to A13) shown in FIG. At the same time as the page movement thread 101 is activated, time counting by a timer (not shown) is started.

In step A11, the page movement thread 101 confirms whether or not it has been started from the thread 104 executed by the same CPU core 11 (own CPU core 11) as the CPU core 11 executing the page movement thread 101. do. As a result of the confirmation, when the page movement thread 101 is started from the thread 104 (see the YES route in step A11), the process proceeds to step A13.

In step A13, the page movement thread 101 refers to the LRU list 33 for each CPU core and selects a movement candidate page based on the LRU algorithm. Further, the page movement thread 101 adds the selected movement candidate page to the OS LRU list 32. Further, the timer may be reset at this timing.
The page movement thread 101 activates the page movement thread 102 attached to the OS. After that, the process returns to step A11.

Further, as a result of the confirmation in step A11, for example, when the thread 104 is activated instead of being activated as in wakeup (see the NO route in step A11), the process proceeds to step A12.

In step A12, the page movement thread 101 refers to the time clocked by the timer and confirms whether a certain time has elapsed. Here, if a certain time has not passed (see the NO route in step A12), the process returns to step A11.
On the other hand, when a certain time has passed (see the YES route in step A12), the process proceeds to step A13.

Next, the processing by the OS-attached page movement thread 102 in the computer system 1a as an example of the first embodiment will be described with reference to the flowcharts (steps A21 to A23) shown in FIG. When the page movement thread 102 attached to the OS is activated, time counting by a timer (not shown) is started.

In step A21, the OS-attached page movement thread 102 confirms whether or not it has been started from the page movement thread 101. As a result of the confirmation, when the page movement thread 102 attached to the OS is started from the page movement thread 101 (see the YES route in step A21), the process proceeds to step A23.

In step A23, the OS-attached page move thread 102 selects the move target page based on the LRU algorithm with reference to the OS LRU list 32. Further, the OS-attached page movement thread 102 stores the selected movement target page in the SSD 20, and further deletes the page that has been moved to the SSD 20 from the OS LRU list 32.

Further, the page movement thread 102 attached to the OS sets a value indicating that the page has been moved in the movement flag of the movement information table 34 for the page moved to the SSD 20. Further, the timer may be reset at this timing.
The page movement thread 101 activates the page movement thread 102 attached to the OS. After that, the process returns to step A21.

Further, as a result of the confirmation in step A21, for example, when the page movement thread 101 is activated instead of being activated (see the NO route in step A21), as in the case of waking from sleep, the process proceeds to step A22.

In step A22, the page movement thread 102 attached to the OS refers to the time clocked by the timer and confirms whether a certain time has elapsed. Here, if a certain time has not passed (see the NO route in step A22), the process returns to step A21.
On the other hand, when a certain time has passed (see the YES route in step A22), the process proceeds to step A23.

Next, the process by the list deletion thread 103 in the computer system 1a as an example of the first embodiment will be described with reference to the flowcharts (steps A31 to A33) shown in FIG. When the list deletion thread 103 is activated, time counting by a timer (not shown) is started.

In step A31, the list deletion thread 103 refers to the time clocked by the timer and confirms whether a certain time has elapsed. Here, if a certain time has not passed (see the NO route in step A31), the process returns to step A31.
On the other hand, when a certain time has passed (see the YES route in step A31), the process proceeds to step A32.

In step A32, the list deletion thread 103 confirms whether or not there is a page in the movement information table 34 in which "1" is set in the movement flag among the pages in the LRU list 33 for each CPU core of the own CPU core 11. .. As a result of the confirmation, if there is no page in the movement information table 34 in which "1" is set in the movement flag among the pages in the LRU list 33 for each CPU core of the own CPU core 11 (refer to the NO route in step A32). ), Return to step A31.

On the other hand, as a result of the confirmation in step A32, if there is a page in the movement information table 34 in which "1" is set in the movement flag among the pages in the LRU list 33 for each CPU core of the own CPU core 11 (step). (Refer to the YES route of A32), the process proceeds to step A33.

In step A33, the list deletion thread 103 deletes a page (moved page) in which "1" is set in the movement flag in the movement information table 34 from the LRU list 33 for each CPU core of the own CPU core 11. After that, the process returns to step A31.
Similar processing is performed on the other CPU core 11.

(C) Effect As described above, according to the computer system 1a as an example of the first embodiment, the LRU list 33 for each CPU core is distributed and provided for each CPU core 11, and the LRU list 33 for each CPU core is controlled. Is performed independently for each CPU core 11. As a result, the LRU list 33 for each CPU core is accessed only from the own CPU core 11, and is not accessed from other CPU cores 11. As a result, it is not necessary to perform exclusive control on the LRU list 33 for each CPU core, and spinlock is not required. As a result, the load on the processor 10 due to the page movement processing is reduced, and the processing performance of the application is improved.

By referring to the move flag of the execution movement information table 34 by the list deletion thread 103 in each CPU core 11, the moved page to the SSD 20 can be easily known, and the moved page can be easily known from the LRU list 33 for each CPU core. Can be deleted.

[2. Description of the second embodiment]
(A) Configuration FIG. 11 is a diagram schematically showing a configuration of a computer system 1b as an example of the second embodiment.

As shown in FIG. 11, the computer system 1b of the second embodiment includes a page correspondence table 35 in place of the movement information table 34 of the DRAM 30 of the first embodiment, and the other parts include the first embodiment. It is configured in the same manner as the computer system 1a of the above. Hereinafter, in the drawings, the same reference numerals as those described above indicate the same parts, and thus the description thereof will be omitted.
FIG. 12 is a diagram illustrating a page correspondence table 35 in the computer system 1b as an example of the second embodiment.

--Page correspondence table 35--
The page correspondence table 35 is information for associating a page with the CPU core 11, and represents which movement candidate page selected by the page movement thread 101 is registered in the LRU list 33 for each CPU core of which CPU core 11.

The page correspondence table 35 illustrated in FIG. 12 is configured by associating a CPU core 11 (CPU core number) for managing the page with the LRU list 33 for each CPU core for each page.

The page movement thread 102 attached to the OS identifies the CPU core 11 corresponding to the moved page moved to the SSD 20 by referring to the page correspondence table 35, and from the LRU list 33 for each CPU core of the CPU core 11 Delete the move candidate page.

For example, the OS-attached page moving thread 102 executed by the primary CPU core 11 can access the LRU list 33 for each CPU core managed by another CPU core 11 by referring to the page correspondence table 35. Access to the page correspondence table 35 can be realized by a lightweight exclusive process, and atomic access can be realized.

In the page correspondence table 35, the CPU core number associated with the page corresponds to the position information of the LRU list 33 for each CPU core corresponding to the movement candidate page.

The page correspondence table 35 corresponds to the page correspondence information that associates the page moved to the SSD 20 with the CPU core 11. Further, the DRAM 30 that stores the page correspondence table 35 corresponds to a storage unit.

FIG. 13 is a diagram for explaining a page management method in the computer system 1b as an example of the second embodiment.
The computer system 1b of the second embodiment also includes an LRU list 33 for each CPU core for each CPU core 11.
In the example shown in FIG. 13, the processor 10 is configured as a 4-core processor including CPU cores # 0 to # 3.

In the computer system 1b of the second embodiment, it is assumed that no data is shared between the CPU cores 11.
In the computer system 1b of the second embodiment, each CPU core # 0 to # 3 executes a thread 104 and a page movement thread 101, respectively.
Further, among the CPU cores # 0 to # 3, for example, any CPU core 11 preset as the primary executes the OS-attached page movement thread 102.
Further, the page correspondence table 35 and the OS LRU list 32 are stored in the kernel area 31 of the DRAM 30.

Further, an LRU list 33 for each CPU core is provided corresponding to each CPU core 11. That is, the LRU list 33-0 for CPU core # 0 corresponds to CPU core # 0, and the LRU list 33-1 for CPU core # 1 corresponds to CPU core # 1 and corresponds to CPU core # 2. The LRU list 33-2 for CPU core # 2 is provided, and the LRU list 33-3 for CPU core # 3 is provided corresponding to the CPU core # 3.

Then, for example, the LRU list 33-0 for CPU core # 0 is accessed from the thread 104 executed by the CPU core # 0 and the page movement thread 101. Further, the LRU list 33-0 for CPU core # 0 is accessed to delete the movement candidate page from the page movement thread 102 attached to the OS.

Similarly, the LRU list 33-1 for each CPU core is accessed from the thread 104 and the page movement thread 101 executed by the CPU core # 1 and the access for deleting the movement candidate page from the page movement thread 102 attached to the OS. Is done.

Further, the LRU list 33-2 for each CPU core includes access from the thread 104 and the page movement thread 101 executed by the CPU core # 2 and access for deleting the movement candidate page from the page movement thread 102 attached to the OS. It is done.

Further, the LRU list 33-3 for each CPU core has an access from the thread 104 and the page movement thread 101 executed by the CPU core # 3 and an access for deleting the movement candidate page from the page movement thread 102 attached to the OS. It is done.
Here, the page management method in the computer system 1b of the second embodiment will be described by taking the processing performed in the CPU core # 0 as an example.

CPU core # 0 realizes arithmetic processing by executing thread 104. Thread 104 performs processing such as updating the access flag and adding a new page to the LRU list 33-0 for CPU core # 0 (see reference numeral S11 in FIG. 13).

The CPU core # 0 refers to the LRU list 33-0 for the CPU core # 0 by executing the page movement thread 101, and the LRU algorithm is selected from the pages registered in the LRU list 33 for the CPU core # 0. Select a move candidate page based on (see reference numeral S12 in FIG. 13).
The page movement thread 101 adds the selected movement candidate page to the OS LRU list 32 (see reference numeral S13 in FIG. 13).

Further, the page movement thread 101 registers the CPU core number (position information of the OS LRU list 32) corresponding to the movement candidate page in the page correspondence table 35 (see reference numeral S14 in FIG. 13).

The CPU core 11 refers to the LRU list 32 for the OS by executing the page movement thread 102 attached to the OS, and among the movement candidate pages registered in the LRU list 32 for the OS, the movement target page based on the LRU algorithm. Is selected (see reference numeral S15 in FIG. 13). Then, the OS-attached page movement thread 102 moves the selected movement target page to the SSD 20 (see reference numeral S16 in FIG. 13).

The OS-attached page movement thread 102 refers to the page correspondence table 35 and acquires the CPU core number (position information of the OS LRU list 32) corresponding to the moved page (see reference numeral S17 in FIG. 13). Then, the page movement thread 102 attached to the OS deletes the moved page from the LRU list 33 for each CPU core of the CPU core 11 represented by the CPU core number acquired from the page correspondence table 35 (see reference numeral S18 in FIG. 13).

In the computer system 1b of the second embodiment, the page movement thread 102 attached to the OS refers to the page correspondence table 35 and corresponds to a deletion processing unit that deletes the page moved to the SSD 20 from the LRU list 33 for each CPU core. ..
Similar processing is performed on the other CPU core 11.

(B) Operation The update process of the LRU list 33 for each CPU core by the thread 104 in the computer system 1b as an example of the second embodiment configured as described above will be described with reference to the flowcharts (steps B1 to B6) shown in FIG. ..

In step B1, thread 104 confirms whether to allocate a page in the memory area. As a result of the confirmation, if the page is secured (see the YES route in step B1), the process proceeds to step B2.
In step B2, thread 104 allocates pages to thread 104 and updates the LRU list 33 for each CPU core.

In step B3, the thread 104 confirms whether the memory usage exceeds a predetermined threshold value (constant amount). As a result of the confirmation, when the amount exceeds a certain amount (see the YES route in step B3), the thread 104 activates the page movement thread 101 in step B4.

After that, the process proceeds to step B5. Further, as a result of the confirmation in step B1, even if the thread 104 does not allocate a page in the memory area (see the NO route in step B1), the process proceeds to step B5.

In step B5, thread 104 confirms whether the memory has been accessed. As a result of the confirmation, when there is a memory access (see the YES route in step B5), the process proceeds to step B6, and the LRU list 33 for each CPU core is updated. After that, the process returns to step B1.
If, as a result of the confirmation in step B3, the memory usage does not exceed a certain amount (see the NO route in step B3), the process proceeds to step B5.
Further, as a result of the confirmation in step B5, if there is no memory access by the thread 104 (see the NO route in step B5), the process returns to step B1.

Next, the process by the page movement thread 101 in the computer system 1b as an example of the second embodiment will be described with reference to the flowcharts (steps B11 to B13) shown in FIG. At the same time as the page movement thread 101 is activated, time counting by a timer (not shown) is started.

In step B11, the page movement thread 101 confirms whether or not it has been started from the thread 104 executed by the same CPU core 11 (own CPU core 11) as the CPU core 11 executing the page movement thread 101. do. As a result of the confirmation, when the page movement thread 101 is started from the thread 104 (see the YES route in step B11), the process proceeds to step B13.

In step B13, the page movement thread 101 refers to the LRU list 33 for each CPU core and selects a movement candidate page based on the LRU algorithm. Further, the page movement thread 101 registers the CPU core number (position information of the OS LRU list 32) corresponding to the movement candidate page in the page correspondence table 35.
Further, the page movement thread 101 adds the selected movement candidate page to the OS LRU list 32. Further, the timer may be reset at this timing.
The page movement thread 101 activates the page movement thread 102 attached to the OS. After that, the process returns to step B11.

Further, as a result of the confirmation in step B11, for example, when the thread 104 is activated instead of being activated (see the NO route in step B11), as in the case of waking from sleep, the process proceeds to step B12.

In step B12, the page movement thread 101 refers to the time clocked by the timer and confirms whether a certain time has elapsed. Here, if a certain time has not passed (see the NO route in step B12), the process returns to step B11.
On the other hand, when a certain time has passed (see the YES route in step B12), the process proceeds to step B13.

Next, the processing by the OS-attached page movement thread 102 in the computer system 1b as an example of the second embodiment will be described according to the flowchart (steps B21 to B23) shown in FIG. When the page movement thread 102 attached to the OS is activated, time counting by a timer (not shown) is started.

In step B21, the OS-attached page movement thread 102 confirms whether or not it has been started from the page movement thread 101. As a result of the confirmation, when the page movement thread 102 attached to the OS is started from the page movement thread 101 (see the YES route in step B21), the process proceeds to step B23.

In step B23, the OS-attached page move thread 102 selects the move target page based on the LRU algorithm with reference to the OS LRU list 32. Further, the OS-attached page movement thread 102 stores the selected movement target page in the SSD 20. Further, the OS-attached page movement thread 102 deletes the page that has been moved to the SSD 20 from the OS LRU list 32.

Further, the page movement thread 102 attached to the OS refers to the page correspondence table 35 for the page moved to the SSD 20, and acquires the CPU core number (position information of the LRU list 32 for the OS) corresponding to the moved page. Then, the OS-attached page movement thread 102 deletes the moved page from the LRU list 33 for each CPU core managed by the acquired CPU core number. Further, the timer may be reset at this timing. After that, the process returns to step B21.

Further, as a result of the confirmation in step B21, for example, when the page movement thread 101 is activated instead of being activated (see the NO route in step B21), as in the case of waking from sleep, the process proceeds to step B22.

In step B22, the page movement thread 102 attached to the OS refers to the time clocked by the timer and confirms whether a certain time has elapsed. Here, if a certain time has not passed (see the NO route in step B22), the process returns to step B21.
On the other hand, when a certain time has passed (see the YES route in step B22), the process proceeds to step B23.

(C) Effect As described above, according to the computer system 1b as an example of the second embodiment, by providing the LRU list 33 for each CPU core in a distributed manner for each CPU core 11, the LRU list 33 for each CPU core is provided. Reduce the number of threads to access. For example, in the example shown in FIG. 13, only the thread 104 and the page moving thread 101 of the own CPU core 11 and the page moving thread 102 attached to the OS access the LRU list 33 for each CPU core. As a result, the lock time for exclusive control in the LRU list 33 for each CPU core can be shortened, the load on the CPU core 11 due to the spinlock can be reduced, and the application performance can be improved.

By referring to the page correspondence table 35, the page movement thread 102 attached to the OS can easily know the LRU list 33 for each CPU core to delete the moved page, and delete the moved page from the LRU list 33 for each CPU core. can do.

[3. Explanation of the third embodiment]
(A) Configuration FIG. 17 is a diagram schematically showing a configuration of a computer system 1c as an example of the third embodiment.

As shown in FIG. 17, the computer system 1c of the third embodiment deletes the movement information table 34 in the DRAM 30 of the first embodiment, and the other parts are the computer system 1a of the first embodiment. It is configured in the same way.
In the figure, the same reference numerals as those described above indicate the same parts, and thus the description thereof will be omitted.
FIG. 18 is a diagram for explaining a page management method in the computer system 1c as an example of the third embodiment.
The computer system 1c of the third embodiment also includes an LRU list 33 for each CPU core for each CPU core 11.
In the example shown in FIG. 18, CPU cores # 0 to # 2 provided in the processor 10 are illustrated.
Even in the computer system 1c of the third embodiment, it is assumed that no data is shared between the CPU cores 11.

In the computer system 1c of the third embodiment, each CPU core # 0 to # 2 executes a thread 104, a page movement thread 101, and an OS-attached page movement thread 102, respectively.

Further, each CPU core # 0 to # 2 includes an OS LRU list 32, respectively. The OS LRU list 32 for each CPU core 11 is stored in the kernel area 31 of the DRAM 30.

Further, an LRU list 33 for each CPU core is provided corresponding to each CPU core 11. That is, the LRU list 33-0 for CPU core # 0 corresponds to CPU core # 0, and the LRU list 33-1 for CPU core # 1 corresponds to CPU core # 1 and corresponds to CPU core # 2. LRU list 33-2 for CPU core # 2 is provided respectively.

Then, for example, the LRU list 33-0 for CPU core # 0 is accessed from the thread 104 executed by the CPU core # 0, the page movement thread 101, and the page movement thread 102 attached to the OS.

That is, the LRU list 33-0 for CPU core # 0 is accessed only from CPU core # 0, and is not accessed from other CPU cores # 1 and # 2.

Similarly, the LRU list 33-1 for each CPU core is accessed from the thread 104 executed by the CPU core # 1, the page movement thread 101, and the page movement thread 102 attached to the OS.

That is, the LRU list 33-1 for CPU core # 1 is accessed only from CPU core # 1, and access from other CPU cores # 0 and # 2 does not occur.

Further, the LRU list 33-2 for each CPU core is accessed from the thread 104 executed by the CPU core # 2, the page movement thread 101, and the page movement thread 102 attached to the OS.

That is, the LRU list 33-2 for CPU core # 2 is accessed only from CPU core # 2, and access from other CPU cores # 0 and # 1 does not occur.
Here, the page management method in the computer system 1c of the third embodiment will be described by taking the processing performed in the CPU core # 0 as an example.

CPU core # 0 realizes arithmetic processing by executing thread 104. Thread 104 performs processing such as updating the access flag and adding a new page to the LRU list 33-0 for CPU core # 0 (see reference numeral S21 in FIG. 18).

The CPU core # 0 refers to the LRU list 33-0 for the CPU core # 0 by executing the page movement thread 101, and the LRU algorithm is selected from the pages registered in the LRU list 33 for the CPU core # 0. Select a move candidate page based on (see reference numeral S22 in FIG. 18).
The page movement thread 101 adds the selected movement candidate page to the OS LRU list 32 managed by the CPU core # 0 (see reference numeral S23 in FIG. 18).

The CPU core # 0 refers to the LRU list 32 for the OS by executing the page movement thread 102 attached to the OS, and is a movement target based on the LRU algorithm from the movement candidate pages registered in the LRU list 32 for the OS. Select a page (see reference numeral S24 in FIG. 18). Then, the OS-attached page movement thread 102 moves the selected movement target page to the SSD 20 (see reference numeral S25 in FIG. 18).

The OS-attached page movement thread 102 deletes the moved page correspondence table 35 from the LRU list 33 for each CPU core managed by the own CPU core # 0 (see reference numeral S26 in FIG. 18).
Similar processing is performed on the other CPU core 11.

In the computer system 1c of the third embodiment, the OS-attached page moving thread 102 deletes the OS LRU list 32 and the page moved to the SSD 20 from the CPU core LRU list 33 for each of the plurality of CPU cores 11. Corresponds to the processing unit.

(B) Operation The update process of the LRU list 33 for each CPU core by the thread 104 in the computer system 1c as an example of the third embodiment configured as described above will be described with reference to the flowcharts (steps C1 to C6) shown in FIG. ..

In step C1, thread 104 confirms whether to allocate a page in the memory area. As a result of the confirmation, when the page is secured (see the YES route in step C1), the process proceeds to step C2.
In step C2, thread 104 allocates pages to thread 104 and updates the LRU list 33 for each CPU core.

In step C3, the thread 104 confirms whether the memory usage exceeds a predetermined threshold value (constant amount). As a result of the confirmation, when the amount exceeds a certain amount (see the YES route in step C3), the thread 104 activates the page movement thread 101 in step C4.

After that, the process proceeds to step C5. Further, as a result of the confirmation in step C1, even if the thread 104 does not allocate a page in the memory area (see the NO route in step C1), the process proceeds to step C5.

In step C5, thread 104 confirms whether the memory has been accessed. As a result of the confirmation, when there is a memory access (see the YES route in step C5), the process proceeds to step C6, and the LRU list 33 for each CPU core is updated. After that, the process returns to step C1.
If, as a result of the confirmation in step C3, the memory usage does not exceed a certain amount (see the NO route in step C3), the process proceeds to step C5.
Further, as a result of the confirmation in step C5, if there is no memory access by the thread 104 (see the NO route in step C5), the process returns to step C1.

Next, the process by the page movement thread 101 in the computer system 1c as an example of the third embodiment will be described with reference to the flowcharts (steps C11 to C13) shown in FIG. At the same time as the page movement thread 101 is activated, time counting by a timer (not shown) is started.

In step C11, the page movement thread 101 confirms whether or not it has been started from the thread 104 executed by the same CPU core 11 (own CPU core 11) as the CPU core 11 executing the page movement thread 101. do. As a result of the confirmation, when the page movement thread 101 is started from the thread 104 (see the YES route in step C11), the process proceeds to step C13.

In step C13, the page movement thread 101 refers to the LRU list 33 for each CPU core and selects a movement candidate page based on the LRU algorithm. Further, the page movement thread 101 adds the selected movement candidate page to the OS LRU list 32. Further, the page movement thread 101 activates the OS-attached page movement thread 102 of the own CPU core 11. Further, the timer may be reset at this timing. After that, the process returns to step C11.

Further, as a result of the confirmation in step C11, for example, when the thread 104 is started instead of being started as in the case of waking up from sleep (see the NO route in step C11), the process proceeds to step C12.

In step C12, the page movement thread 101 refers to the time clocked by the timer and confirms whether a certain time has elapsed. Here, if a certain time has not passed (see the NO route in step C12), the process returns to step C11.
On the other hand, when a certain time has passed (see the YES route in step C12), the process proceeds to step C13.

Next, the processing by the OS-attached page movement thread 102 in the computer system 1c as an example of the third embodiment will be described with reference to the flowcharts (steps C21 to C23) shown in FIG. When the page movement thread 102 attached to the OS is activated, time counting by a timer (not shown) is started.

In step C21, the OS-attached page movement thread 102 confirms whether or not it has been started from the page movement thread 101. As a result of the confirmation, when the page movement thread 102 attached to the OS is started from the page movement thread 101 (see the YES route in step C21), the process proceeds to step C23.

In step C23, the OS-attached page move thread 102 selects the move target page based on the LRU algorithm with reference to the OS LRU list 32 of the own CPU core 11. Further, the OS-attached page movement thread 102 stores the selected movement target page in the SSD 20. Further, the OS-attached page movement thread 102 deletes the page that has been moved to the SSD 20 from the OS LRU list 32 of the own CPU core 11. Further, the timer may be reset at this timing. After that, the process returns to step C21.

Further, as a result of the confirmation in step C21, for example, when the page movement thread 101 is activated instead of being activated (see the NO route in step C21), as in the case of waking from sleep, the process proceeds to step C22.

In step C22, the page movement thread 102 attached to the OS refers to the time clocked by the timer and confirms whether a certain time has elapsed. Here, if a certain time has not elapsed (see the NO route in step C22), the process returns to step C21.
On the other hand, when a certain time has passed (see the YES route in step C22), the process proceeds to step C23.

(C) Effect As described above, according to the computer system 1c as an example of the third embodiment, the LRU list 33 for each CPU core is distributed and provided for each CPU core 11, and the LRU list 33 for each CPU core is controlled. Is performed independently for each CPU core 11. As a result, the LRU list 33 for each CPU core is accessed only from the own CPU core 11, and is not accessed from other CPU cores 11. As a result, it is not necessary to perform exclusive control on the LRU list 33 for each CPU core, and spinlock is not required. As a result, the load on the processor 10 due to the page movement processing is reduced, and the processing performance of the application is improved.

[4. others]
The disclosed technique is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the spirit of the present embodiment. Each configuration and each process of the present embodiment can be selected as necessary, or may be combined as appropriate.

For example, in the above-described embodiment, the computer system 1 includes an SSD 20 and uses the SSD 20 as a low-speed memory, but the present invention is not limited to this. A storage device other than the SSD 20 may be used as the low-speed memory, and various modifications can be made.

Further, in the above-described embodiment, an example in which the page to be moved to the SSD 20 is selected based on the LRU algorithm is shown, but the present invention is not limited to this. The page to be moved to SSD 20 may be selected based on other algorithms such as FIFO (First In, First Out).

Further, in the above-described embodiment, the OS LRU list 32 and the CPU core LRU list 33 are stored in the kernel area 31 of the DRAM 30. That is, the kernel area 31 of the DRAM 30 functions as the first management information storage area and the second management information storage area, but is not limited thereto. For example, at least one of the OS LRU list 32 and the CPU core LRU list 33 may be stored in another storage area such as the user area 36 of the DRAM 30 or the SSD 20, and can be modified in various ways.
Further, according to the above-mentioned disclosure, it is possible for a person skilled in the art to carry out and manufacture the present embodiment.

[4. Description of Fourth Embodiment]
In the computer systems 1a to 1c of each of the above-described embodiments, the LRU list 33 for each CPU core is provided for each CPU core 11. Then, the LRU list 33 for each CPU core is accessed only from the CPU core 11 provided with the LRU list 33, and access from other CPU cores 11 does not occur. As a result, the cache capacity cannot be redistributed between the CPU cores 11.

For example, in a two-CPU core configuration including CPU core # 0 and CPU core # 2, it is assumed that the memory access frequency of CPU core # 0 is low. In such a case, when the CPU core # 1 newly secures the cache, if there is no free space in the cache 30a, one of the pages is moved to the SSD 20.

However, even if the CPU core # 0 has a page with a low access frequency, the CPU core # 1 cannot operate the LRU list 33 for each CPU core of the CPU core # 0, so that the cache of the CPU core # 0 is set to the SSD 20. It cannot be moved, and the page is moved from the cache of CPU # 1 to SSD20.

The cache capacities of CPU core # 0 and CPU core # 1 are zero when the server is started. After the server is started, each CPU core # 0 and # 1 goes to get the cache on a first-come, first-served basis, and when the free space of the cache is finally exhausted, the amount of each cache secured by the CPU cores # 0 and # 1 is increased. This is the initial cache capacity of each CPU core # 0 and # 1. If the initial state is not the optimum ratio, it is desirable to redistribute the cache.
As a conventional method for redistributing the cache capacity between CPU cores, a method using the cache miss frequency of each CPU core as an index is known.

That is, by repeatedly releasing the cache of the CPU core having a low cache miss frequency for one page and increasing the cache of the CPU core having a high cache miss frequency by one page, the cache is gradually approached to the optimum cache capacity. Redistribute.
However, in such a conventional method, it takes a long time to reach the optimum cache capacity, and the performance deterioration during that period becomes a problem.
In the computer system 1d shown in the fourth embodiment, the time for redistributing the cache capacity can be shortened.

(A) Configuration FIG. 22 is a diagram illustrating a functional configuration of a computer system 1d as an example of the fourth embodiment.

The computer system 1d illustrated in FIG. 22 includes a cache redistribution processing unit 40 in addition to the computer system 1a of the first embodiment shown in FIG. In FIG. 22, the illustration of a part of the configuration of the computer system 1a shown in FIG. 6 is omitted.
Further, the computer system 1d of the fourth embodiment has the same hardware configuration as the computer system 1a of the first embodiment illustrated in FIG.
--Cache redistribution processing unit 40--
The cache redistribution processing unit 40 redistributes the cache capacity using the requested memory capacity of each CPU core 11 and the information on the cache miss frequency.
The cache redistribution processing unit 40 has functions as a request memory capacity totaling unit 41, a cache miss frequency totaling unit 42, and a cache redistribution determination unit 43.
The function as the cache redistribution processing unit 40 is realized by, for example, any CPU core 11 preset as the primary among the CPU cores # 0 to # 3.
--Cache capacity table 44--

The cache capacity table 44 holds a value (cache capacity value) of the cache capacity of each CPU core 11. The cache capacity value is the size of the storage area allocated to each CPU core 11 in the cache 30a, and indicates the memory size that can be used by each CPU core 11 in the cache 30a.
The page movement thread 101 of each CPU core 11 manages movement candidate pages using the cache capacity value read from the cache capacity table 44.

The page movement thread 101 reads the cache capacity value corresponding to the CPU core 11 (own CPU core 11) provided by itself from the cache capacity table 44, and the cache capacity of the own CPU core 11 may exceed this cache capacity value. Perform page movement processing so that there is no such thing.
The information constituting the cache capacity table 44 is stored in, for example, the kernel area 31 of the DRAM 30.
--Required memory capacity totaling unit 41--

When the thread 104 of each CPU core 11 makes a memory allocation request or a memory release request (reading the API), the requested memory capacity totaling unit 41 is input with such information. API is an abbreviation for Application Programming Interface.

The request memory capacity totaling unit 41 integrates the request memory capacity for each CPU core 11. The requested memory capacity totaling unit 41 integrates the requested memory capacity for each CPU core 11 by using the information of the memory capacity when the API for securing the memory is called from the thread.
As the memory capacity information, for example, the memory size included in the argument of the malloc function that allocates the dynamic memory may be used. The acquisition of the requested memory capacity information is not limited to the method using the argument of the malloc function, and can be appropriately modified and executed.
When the thread calls the API to release the memory, the requested memory capacity totaling unit 41 subtracts the memory capacity released by the thread from the requested memory capacity.
The requested memory capacity for each CPU core 11 calculated by the requested memory capacity totaling unit 41 is stored in, for example, the kernel area 31 of the DRAM 30.
--Cash miss frequency totaling unit 42--

The cache miss frequency totaling unit 42 counts the number of cache misses for each CPU core 11. For example, when a page fault interrupt occurs during memory access by a thread, the cache miss frequency totaling unit 42 determines that a cache miss has occurred (cache miss determination). When the cache miss frequency totaling unit 42 determines the cache miss, the cache miss frequency totaling unit 42 counts up (increments) the number of cache misses with respect to the CPU core 11 in which the cache miss has occurred.

The cache miss frequency totaling unit 42 totals the number of cache misses (cache miss frequency) for each predetermined time for each CPU core 11. The cache miss frequency is cleared every time a predetermined time elapses by the cache redistribution determination unit 43 described later.

The number of cache misses (cache miss frequency) for each CPU core 11 counted by the cache miss frequency totaling unit 42 is stored in, for example, the kernel area 31 of the DRAM 30.

--Cash redistribution judgment unit 43--
The cache redistribution determination unit 43 determines the cache capacity to be redistributed (redistribution cache size) based on the requested memory capacity of each CPU core 11 and the information on the cache miss frequency.

The cache redistribution determination unit 43 confirms the ratio of the maximum value and the minimum value of the cache miss frequency among the plurality of CPU cores 11 at regular time intervals, and this ratio is equal to or higher than the constant value (threshold value). If so, redistribute the cache.

The cache redistribution determination unit 43 determines the CPU core 11 that redistributes the cache and the memory capacity to be redistributed, and updates the cache capacity table 44 using the determined memory capacity. The value of the cache miss frequency totaled by the cache miss frequency totaling unit 42 is cleared at regular time intervals.
FIG. 23 is a diagram for explaining the processing of the cache redistribution determination unit 43 of the computer system 1d as an example of the fourth embodiment.
In FIG. 23, the cache capacity, the requested memory capacity, and the cache miss frequency are illustrated for each of the CPU cores # 0 to # 2.
The cache redistribution determination unit 43 executes cache redistribution when the ratio of the maximum value and the minimum value of the cache miss frequency is a certain value or more (for example, 3 or more).

In the example shown in FIG. 23, the cache miss frequency “400” of CPU core # 0 is the maximum value, and the cache miss frequency “100” of CPU core # 1 is the minimum value. Since the ratio 4 (= 400 ÷ 100) of these cache miss frequencies is equal to or higher than the threshold value “3”, the cache redistribution determination unit 43 determines that the cache redistribution is to be performed.

Further, the cache redistribution determination unit 43 determines that the CPU core 11 (CPU_L) having the lowest cache miss frequency is the transfer source of the cache capacity in the cache redistribution, and the CPU core 11 (CPU_H) having the highest cache miss frequency is used. Determine the destination to move the cache capacity.

In the example shown in FIG. 23, the cache redistribution determination unit 43 determines that the CPU core # 1 having the lowest cache miss frequency is the transfer source of the cache capacity, and the CPU core # 0 having the highest cache miss frequency is the cache capacity. Determine the destination.
In cache redistribution, the cache redistribution determination unit 43 moves the cache capacity from the CPU core 11 (CPU_L) having the lowest cache miss frequency to the CPU core 11 (CPU_H) having the highest cache miss frequency.

Further, the cache redistribution determination unit 43 determines the cache capacity (redistribution cache size) to be moved from the movement source CPU core 11 to the movement destination CPU core 11 by redistribution.

The cache redistribution determination unit 43 is a page of data to be moved by redistribution based on the ratio (required memory capacity ratio) between the required memory capacity of the CPU core 11 of the movement source and the required memory capacity of the CPU core 11 of the movement destination. Determine the number (number of pages moved). For example, the cache redistribution determination unit 43 calculates the number of moved pages based on the following equation (1).
Number of pages to move = Required memory capacity of move destination / Required memory capacity of move source ・ ・ ・ (1)

In the example shown in FIG. 23, since the required memory capacity of the destination CPU core 11 is “20G” and the required memory capacity of the destination CPU core 11 is “2G”, the cache redistribution determination unit 43 , The number of moved pages is calculated as shown below based on the equation (1).
Number of pages moved = 20/2 = 10 (pages)

Then, the cache redistribution determination unit 43 determines the redistribution cache size (for example, 40KB) by multiplying the calculated number of moved pages (for example, 10 pages) by the page data size (for example, 4KB).

The cache redistribution determination unit 43 updates the cache capacity table 44 using the calculated redistribution cache size. Specifically, the cache redistribution determination unit 43 subtracts the redistribution cache size calculated from the cache capacity value of the move source CPU core 11 in the cache capacity table 44, and also subtracts the cache capacity value of the move destination CPU core 11. Add the redistribution cache size to.

That is, the cache redistribution determination unit 43 determines the redistribution cache size according to the ratio of the requested memory capacity of the CPU core 11 of the movement source and the CPU core 11 of the movement destination.
The page movement thread 101 selects the movement target page for the movement page, and stores the movement target page for the movement page in the SSD 20 at a time.
As a result, the redistribution can be completed in a shorter time than moving the cache capacity page by page.

(B) Operation The page movement process in the computer system 1d as an example of the fourth embodiment configured as described above will be described with reference to the flowcharts (steps D1 to D9) shown in FIG. At the same time as the page movement thread 101 is activated, time counting by a timer (not shown) is started.

In step D1, the request memory capacity totaling unit 41 confirms whether the thread 104 has requested the memory (memory allocation request). If thread 104 does not request memory allocation (see NO route in step D1), the process proceeds to step D3.
Further, when the thread 104 requests the memory (see the YES route in step D1), the process proceeds to step D2.

In step D2, the request memory capacity totaling unit 41 adds the memory capacity requested by the thread 104 to the request memory capacity of the CPU core 11 that executes the thread 104. After that, the process proceeds to step D3.

In step D3, the request memory capacity totaling unit 41 confirms whether the thread 104 has released the memory. If the thread 104 has not released the memory (see the NO route in step D3), the process proceeds to step D5.
When the thread 104 releases the memory (see the YES route in step D3), the process proceeds to step D4.

In step D4, the request memory capacity totaling unit 41 subtracts the memory capacity released by the thread 104 from the request memory capacity of the CPU core 11 that executes the thread 104. After that, the process proceeds to step D5.

In step D5, the cache miss frequency totaling unit 42 confirms whether a page fault has occurred in the memory access of the thread 104. If no page fault has occurred (see the NO route in step D5), the process proceeds to step D7.
If a page fault has occurred (see the YES route in step D5), the process proceeds to step D6.

In step D6, the cache miss frequency totaling unit 42 adds (increments) the number of cache misses (cache miss frequency) of the CPU core 11 that executes the thread 104. After that, the process proceeds to step D7.

In step D7, the cache redistribution determination unit 43 refers to the time clocked by the timer and confirms whether a certain time has elapsed. Here, if a certain time has not elapsed (see the NO route in step D7), the process returns to step D1.
On the other hand, when a certain time has passed (see the YES route in step D7), the process proceeds to step D8.

In step D8, the cache redistribution determination unit 43 confirms whether the ratio of the maximum value and the minimum value of the cache miss frequency among the plurality of CPU cores 11 provided in the computer system 1d is a certain value or more. As a result of the confirmation, if the ratio of the maximum value and the minimum value of the cache miss frequency is not more than a certain value (see the NO route in step D8), the process returns to step D1.
On the other hand, when the ratio of the maximum value and the minimum value of the cache miss frequency is equal to or higher than a certain value (see the YES route in step D8), the process proceeds to step D9.

In step D9, the cache redistribution determination unit 43 determines the redistribution cache size according to the ratio of the requested memory capacity of the CPU core 11 of the movement source and the CPU core 11 of the movement destination.

Further, the cache redistribution determination unit 43 updates the cache capacity table 44 using the calculated redistribution cache size. Further, the cache redistribution determination unit 43 clears the cache miss frequency aggregated by the cache miss frequency aggregation unit 42. After that, the process returns to step D1.

(C) Effect According to the computer system 1d as an example of the fourth embodiment, the same effect as that of the computer system 1a of the first embodiment described above can be obtained, and the cache redistribution processing unit 40 is placed between the CPU cores 11. By redistributing the cache capacity, the cache capacity can be redistributed among the CPU cores 11 even in a configuration in which the LRU list of the cache (LRU list 33 for each CPU core) is separated for each CPU core 11.

In the cache redistribution processing unit 40, the cache redistribution determination unit 43 executes cache redistribution when the ratio of the maximum value and the minimum value of the cache miss frequency is a certain value or more. That is, when the cache miss frequency is biased among the plurality of CPU cores 11, the cache redistribution processing unit 40 performs the cache redistribution process to eliminate the bias in the cache miss frequency and improve the average performance. be able to.

Further, the cache redistribution determination unit 43 determines that the CPU core # 1 having the lowest cache miss frequency is the transfer source of the cache capacity, and the CPU core # 0 having the highest cache miss frequency is the move destination of the cache capacity. As a result, the bias of the cache miss frequency can be efficiently eliminated, and the average performance can be improved.

Further, the cache redistribution determination unit 43 determines the redistribution cache size according to the ratio of the required memory capacity of the CPU core 11 of the movement source and the CPU core 11 of the movement destination. As a result, the time for redistributing the cache capacity is reduced as compared with the conventional method in which the cache of the CPU core having a low cache miss frequency is released by one page and the cache of the CPU core having a high cache miss frequency is repeatedly increased by one page. Can be shortened. Further, by shortening the time for redistributing the cache capacity, the time for performance deterioration due to the cache capacity imbalance can be shortened, and the average performance can be improved.

The computer system 1d of the fourth embodiment described above is configured to include the cache redistribution processing unit 40 in the computer system 1a of the first embodiment shown in FIG. 6, but is limited to this. It's not a thing. For example, the computer system 1b of the second embodiment and the computer system 1c of the third embodiment described above may be provided with the cache redistribution processing unit 40, and may be modified in various ways.

[5. Addendum]
Regarding the above embodiments, the following additional notes will be further disclosed.
(Appendix 1)
Primary memory for storing page-by-page data and
A secondary memory that stores the data of the page to be moved from the primary memory, and
A processor with multiple arithmetic cores and
A first link provided for each of the plurality of arithmetic cores and storing a plurality of first links indicating the order of movement of each page in the page group assigned to each of the plurality of arithmetic cores among the plurality of pages. Management information storage area and
A plurality of pages provided for the operating system and selected according to the order of movement from the page group in the plurality of first links are managed as a candidate page group to be moved to the secondary memory. A second management information storage area for storing the second link, and
An information processing device including a movement processing unit that moves data of a page selected from the page group of the second link from the primary memory to the secondary memory.

(Appendix 2)
A storage unit that stores movement management information that manages pages moved to the secondary memory by the movement processing unit, and a storage unit.
A supplementary note, which is provided for each of the plurality of arithmetic cores, and includes a deletion processing unit that deletes a page moved to the secondary memory from the first link by referring to the movement management information. 1. The information processing apparatus according to 1.

(Appendix 3)
A storage unit that stores page correspondence information that associates a page moved to the secondary memory with the arithmetic core, and a storage unit.
The information processing apparatus according to Appendix 1, further comprising a deletion processing unit that deletes a page moved to the secondary memory from the first link with reference to the page correspondence information.

(Appendix 4)
The information processing apparatus according to Appendix 1, wherein each of the plurality of arithmetic cores includes the second link and a deletion processing unit that deletes a page moved to the secondary memory from the first link. ..

(Appendix 5)
Primary memory for storing page-by-page data and
A secondary memory that stores the data of the page to be moved from the primary memory, and
A processor with multiple arithmetic cores and
In an information processing device equipped with
Among the plurality of arithmetic cores, the arithmetic core that uses the primary memory
A process of registering the page for which the arithmetic core has accessed data in a plurality of first links indicating the order of movement of each page in the page group assigned to the arithmetic core is executed.
In any one of the plurality of arithmetic cores,
A second page group provided for the operating system and selected from the page groups in the plurality of first links according to the order of movement is registered as a candidate page group to be moved to the secondary memory. A memory control program comprising referring to two links and executing a process of moving data of a page selected from the page group of the second link from the primary memory to the secondary memory.

(Appendix 6)
One of the plurality of arithmetic cores is made to execute the process of storing the movement management information for managing the pages moved to the secondary memory in the storage unit.
The memory according to Appendix 5, wherein each of the plurality of arithmetic cores is referred to the movement management information to execute a process of deleting the page moved to the secondary memory from the first link. Control program.

(Appendix 7)
The page correspondence information for associating the page moved to the secondary memory with the arithmetic core is stored in the storage unit.
Addendum 5 is characterized in that any one of the plurality of arithmetic cores is made to execute a process of deleting a page moved to the secondary memory from the first link by referring to the page correspondence information. Memory control program.

(Appendix 8)
The memory control program according to Appendix 5, wherein each of the plurality of arithmetic cores is made to execute a process of deleting the second link and the page moved to the secondary memory from the first link.

(Appendix 9)
In an information processing device having a processor having a plurality of arithmetic cores,
A request memory capacity totaling unit that integrates the required memory capacity for each of the plurality of arithmetic cores,
A cache miss frequency totaling unit that counts the number of cache misses for each of the plurality of arithmetic cores,
An information processing apparatus including a cache redistribution determination unit that determines the cache capacity to be redistributed based on the required memory capacity of each arithmetic core.

(Appendix 10)
The cache redistribution determination unit is characterized in that the cache redistribution determination unit determines the cache capacity to be redistributed according to the ratio of the required memory capacity of the transfer source arithmetic core and the required memory capacity of the migration destination arithmetic core in the redistribution. The information processing apparatus according to Appendix 9.

(Appendix 11)
Appendix 9 or 10 is characterized in that the cache redistribution determination unit redistributes the cache capacity when the ratio of the maximum value and the minimum value of the cache miss frequency in the plurality of arithmetic cores is equal to or greater than a threshold value. The information processing device described in.

(Appendix 12)
The cache redistribution determination unit determines the calculation core having the lowest cache miss frequency as the transfer source of the cache capacity, and determines the calculation core having the highest cache miss frequency as the move destination of the cache capacity. 11. The information processing apparatus according to 11.

(Appendix 13)
In an information processing device having a processor having a plurality of arithmetic cores,
In any one of the plurality of arithmetic cores,
The required memory capacity for each of the plurality of arithmetic cores is integrated, and the required memory capacity is integrated.
The number of cache misses for each of the plurality of arithmetic cores is counted, and the number of cache misses is counted.
An information processing program characterized by executing a process of determining the cache capacity to be redistributed based on the required memory capacity of each arithmetic core.

(Appendix 14)
One of the plurality of arithmetic cores performs a process of determining the cache capacity to be redistributed according to the ratio of the required memory capacity of the migration source arithmetic core and the required memory capacity of the migration destination arithmetic core in the redistribution. The information processing program according to Appendix 13, characterized in that it is executed at one time.

(Appendix 15)
When the ratio of the maximum value and the minimum value of the cache miss frequency in the plurality of arithmetic cores is equal to or greater than the threshold value, the process of redistributing the cache capacity is executed by any one of the plurality of arithmetic cores. The information processing program according to Appendix 13 or 14.

(Appendix 16)
One of the plurality of arithmetic cores is made to execute the process of determining the arithmetic core having the lowest cache miss frequency as the transfer source of the cache capacity and determining the arithmetic core having the highest cache miss frequency as the migration destination of the cache capacity. The information processing program according to Appendix 15, wherein the information processing program is characterized by the above.

(Appendix 17)
In an information processing device having a processor having a plurality of arithmetic cores,
The process of accumulating the required memory capacity for each of the plurality of arithmetic cores, and
The process of counting the number of cache misses for each of the plurality of arithmetic cores,
An information processing method comprising a process of determining a cache capacity to be redistributed based on a required memory capacity of each arithmetic core.

(Appendix 18)
The appendix 17 is characterized by comprising a process of determining the cache capacity to be redistributed according to the ratio of the required memory capacity of the transfer source arithmetic core and the required memory capacity of the migration destination arithmetic core in the redistribution. The information processing method described.

(Appendix 19)
The information processing according to Appendix 17 or 18, further comprising a process of redistributing the cache capacity when the ratio of the maximum value and the minimum value of the cache miss frequency in the plurality of arithmetic cores is equal to or greater than a threshold value. Method.

(Appendix 20)
The information processing according to Appendix 19, wherein the calculation core having the lowest cache miss frequency is determined as the transfer source of the cache capacity, and the calculation core having the highest cache miss frequency is determined as the move destination of the cache capacity. Method.

1a, 1b, 1c Computer system 10 Processor 11-0, 11-1, 11-2 ..., 11 CPU core 12 PCIe root port 13 Memory controller 20 SSD
21 Mobile data 30 DRAM
30a cache 31 kernel area 32 LRU list for OS (LRU list for Linux)
33-0, 33-1, ..., 33 LRU list for each CPU core 34 Movement information table 35 page correspondence table 40 Cache redistribution processing unit 41 Request memory capacity totaling unit 42 Cache miss frequency totaling unit 43 Cache redistribution judgment unit 44 Cache capacity table 101 Page move thread 102 OS attached page move thread 103 List delete thread 104 thread

Claims (11)

Primary memory for storing page-by-page data and
A secondary memory that stores the data of the page to be moved from the primary memory, and
A processor with multiple arithmetic cores and
A first link provided for each of the plurality of arithmetic cores and storing a plurality of first links indicating the order of movement of each page in the page group assigned to each of the plurality of arithmetic cores among the plurality of pages. Management information storage area and
A plurality of pages provided for the operating system and selected according to the order of movement from the page group in the plurality of first links are managed as a candidate page group to be moved to the secondary memory. A second management information storage area for storing the second link, and
An information processing device including a movement processing unit that moves data of a page selected from the page group of the second link from the primary memory to the secondary memory. A storage unit that stores movement management information that manages pages moved to the secondary memory by the movement processing unit, and a storage unit.
The claim is provided for each of the plurality of arithmetic cores, and is provided with a deletion processing unit that deletes the page moved to the secondary memory from the first link with reference to the movement management information. Item 1. The information processing apparatus according to item 1. A storage unit that stores page correspondence information that associates a page moved to the secondary memory with the arithmetic core, and a storage unit.
The information processing apparatus according to claim 1, further comprising a deletion processing unit that deletes a page moved to the secondary memory from the first link with reference to the page correspondence information. The information processing according to claim 1, wherein each of the plurality of arithmetic cores includes the second link and a deletion processing unit that deletes a page moved to the secondary memory from the first link. Device. Primary memory for storing page-by-page data and
A secondary memory that stores the data of the page to be moved from the primary memory, and
A processor with multiple arithmetic cores and
In an information processing device equipped with
Among the plurality of arithmetic cores, the arithmetic core that uses the primary memory
A process of registering the page for which the arithmetic core has accessed data in a plurality of first links indicating the order of movement of each page in the page group assigned to the arithmetic core is executed.
In any one of the plurality of arithmetic cores,
A second page group provided for the operating system and selected from the page groups in the plurality of first links according to the order of movement is registered as a candidate page group to be moved to the secondary memory. A memory control program comprising referring to two links and executing a process of moving data of a page selected from the page group of the second link from the primary memory to the secondary memory. In an information processing device having a processor having a plurality of arithmetic cores,
A request memory capacity totaling unit that integrates the required memory capacity for each of the plurality of arithmetic cores,
A cache miss frequency totaling unit that counts the number of cache misses for each of the plurality of arithmetic cores,
An information processing apparatus including a cache redistribution determination unit that determines the cache capacity to be redistributed based on the required memory capacity of each arithmetic core. The cache redistribution determination unit is characterized in that the cache redistribution determination unit determines the cache capacity to be redistributed according to the ratio of the required memory capacity of the transfer source arithmetic core and the required memory capacity of the migration destination arithmetic core in the redistribution. 6. The information processing apparatus according to claim 6. 6. The information processing apparatus according to 7. The claim is characterized in that the cache redistribution determination unit determines the calculation core having the lowest cache miss frequency as the transfer source of the cache capacity, and determines the calculation core having the highest cache miss frequency as the move destination of the cache capacity. Item 8. The information processing apparatus according to item 8. In an information processing device having a processor having a plurality of arithmetic cores,
In any one of the plurality of arithmetic cores,
The required memory capacity for each of the plurality of arithmetic cores is integrated, and the required memory capacity is integrated.
The number of cache misses for each of the plurality of arithmetic cores is counted, and the number of cache misses is counted.
An information processing program characterized by executing a process of determining the cache capacity to be redistributed based on the required memory capacity of each arithmetic core. In an information processing device having a processor having a plurality of arithmetic cores,
The process of accumulating the required memory capacity for each of the plurality of arithmetic cores, and
The process of counting the number of cache misses for each of the plurality of arithmetic cores,
An information processing method comprising a process of determining a cache capacity to be redistributed based on a required memory capacity of each arithmetic core.

Images