JP2021136590A - Imaging device - Google Patents

Abstract

To provide an imaging device that can reduce time in which signal processing of an imaged image is performed to output.SOLUTION: An imaging device comprises: a pixel layer that has a pixel sharing structure body including a plurality of pixels in which photo-electric conversion of injected light is performed to output an image signal; and a signal processing layer that is laminated on the pixel layer, and that has a signal processing circuit processing the image signal. In the imaging device, the pixel layer has a plurality of pixel sharing structure bodies which are arranged in an array, the signal processing layer has a plurality of signal processing circuits which are arranged in an array, one pixel sharing structure body is connected to one signal processing circuit so as to be able to input the image signal, and the plurality of signal processing circuits process the input image signal in parallel to each other.SELECTED DRAWING: Figure 5

Description

The technology according to the present disclosure (the present technology) relates to, for example, an image pickup device used in a digital camera or the like.

As an image pickup device using an image pickup device such as a digital camera, for example, there is a device having a configuration disclosed in Patent Document 1. The imaging device disclosed in Patent Document 1 is an imaging device in which an imaging unit and a signal processing unit that processes a signal of an image captured by the imaging unit are laminated, and in order to increase the amount of signal processing processed by the entire imaging device. In addition, four signal processing units are stacked and provided. Further, the imaging unit is divided into four systems, and the signals captured by the pixels of the four systems are processed in the signal processing circuits of the second layer, the third layer, the fourth layer, and the fifth layer, respectively, from the top. ..

Japanese Unexamined Patent Publication No. 2017-0768872

Depending on the application, the image pickup apparatus may be required to obtain information by signal processing the captured image in the shortest possible time after capturing the image.
However, when the technique disclosed in Patent Document 1 is applied to an imaging device having high pixels (for example, 30 million pixels [6400 pixels × 4800 pixels]), each of the four pixels has 7.5 million pixels. Is provided. Therefore, the signal processing circuits of the second layer, the third layer, the fourth layer, and the fifth layer from the top sequentially process the signal of the image output from 7.5 million pixels, respectively.
Therefore, in the technique disclosed in Patent Document 1, since the image signals output from many pixels (7.5 million pixels) are sequentially processed by one signal processing circuit, a considerable amount of time is required for signal processing. There is a problem that it requires.

In view of the above problems, it is an object of the present technology to provide an image pickup device capable of shortening the time for signal processing and outputting an captured image.

The image pickup device according to one aspect of the present technology has a pixel layer having a pixel sharing structure including a plurality of pixels that photoelectrically convert incident light and output an image signal, and is laminated on the pixel layer and processes an image signal. A signal processing layer having a signal processing circuit to be used is provided. Further, the pixel layer has a plurality of pixel sharing structures arranged in an array, and the signal processing layer has a plurality of signal processing circuits arranged in an array. Then, one pixel sharing structure is connected to one signal processing circuit so that an image signal can be input, and the plurality of signal processing circuits process the input image signals in parallel with each other.

It is an equivalent circuit diagram which shows the structural example of the image pickup device which concerns on 1st Embodiment. It is a top view which shows the structure of the pixel sharing structure included in a pixel layer. It is a circuit diagram which shows the structure of the element included in a pixel layer. It is sectional drawing which shows the structural example of the image sensor. It is a bird's-eye view of a pixel sharing structure and a signal processing circuit. It is a figure which compares the area of a pixel sharing structure and a signal processing circuit. It is an equivalent circuit diagram which shows the structural example of the image pickup device which concerns on 2nd Embodiment. It is a bird's-eye view of the pixel sharing structure and the signal processing circuit provided in the image pickup device which concerns on 2nd Embodiment. It is a figure which compares the area of the pixel sharing structure and the signal processing circuit provided in the image pickup device which concerns on 2nd Embodiment. It is an equivalent circuit diagram which shows the structural example of the image pickup device which concerns on 3rd Embodiment. It is a bird's-eye view of the pixel sharing structure and the signal processing circuit provided in the image pickup device which concerns on 3rd Embodiment. It is an equivalent circuit diagram which shows the structural example of the image pickup device which concerns on 4th Embodiment.

Hereinafter, embodiments of the present technology will be described with reference to the drawings. In the description of the drawings, the same or similar parts are designated by the same or similar reference numerals, and duplicate description will be omitted. Each drawing is schematic and may differ from the actual one. The embodiments shown below exemplify devices and methods for embodying the technical idea of the present technology, and the technical idea of the present technology is specified in the devices and methods exemplified in the following embodiments. Not something to do. The technical idea of the present technology can be modified in various ways within the technical scope described in the claims.

(First Embodiment)
<Image sensor>
The image sensor according to the first embodiment is, for example, a back-illuminated solid-state image sensor. The image sensor is not limited to the back-illuminated solid-state image sensor, and may be a front-illuminated solid-state image sensor.
Further, as shown in FIG. 1, the image pickup device according to the first embodiment includes a pixel layer 10, a signal processing layer 20, and an output layer 30.

<Pixel layer>
The pixel layer 10 has a plurality of pixel circuits 11. The plurality of pixel circuits 11 are arranged in parallel when viewed from the incident direction of light (indicated as "incident direction (stacking direction)" in FIG. 1).
Note that FIG. 1 shows two pixel circuits 11a and 11b among the plurality of pixel circuits 11 included in the pixel layer 10.

The pixel circuit 11 includes a plurality of photodiode PDs and a plurality of transfer transistors TR. In addition to this, as shown in FIGS. 2 and 3, the pixel circuit 11 includes a floating diffusion FD and a pixel transistor (reset transistor RST, amplification transistor AMP, and selection transistor SEL).
Further, the pixel circuit 11 has a pixel sharing structure.

There are a plurality of pixel sharing structures (j in the direction in which the control signal line DSL connected to the transfer transistor TR extends) in the X direction of the paper in FIG. 2 (j is an integer of 2 or more) and orthogonal to the X direction. A total of j × k pixels arranged in an array of a plurality of (k, k is an integer of 2 or more) in the direction in which the pixels are electrically equal potential, and one floating diffusion FD and one floating. It is a structure that shares one amplification transistor AMP connected to the diffusion FD.
As an example of the pixel sharing structure, in the first embodiment, j = 2 and k = 4, that is, eight pixels having one photodiode PD and one transfer transistor TR per pixel are electrically equipotential. The case where one floating diffusion FD and one amplification transistor AMP and reset transistor RST connected to one floating diffusion FD are shared will be described. That is, in the first embodiment, the structure of the pixel layer 10 is a pixel sharing structure PC for 8 pixels formed by connecting a photodiode PD for 8 pixels and a transfer transistor TR to a set of pixel transistors. The case where the above is provided will be described.

Therefore, the pixel layer 10 has a pixel sharing structure PC including a plurality of pixels that photoelectrically convert the incident light and output an image signal. Further, the pixel sharing structure PC includes 8 pixels as a plurality of pixels.
Further, as shown in FIG. 4, the microlens MR is arranged on the surface of the pixel layer 10 facing the signal processing layer 20, that is, the surface on which light is incident on the pixel layer 10.

Further, as shown in FIG. 5, the pixel layer 10 has a plurality of pixel sharing structure PCs arranged in an array. In FIG. 5, the pixel sharing structure PC included in the pixel circuit 11a is referred to as “pixel sharing structure PCa”, and the pixel sharing structure PC included in the pixel circuit 11b is referred to as “pixel sharing structure PCb”. Further, in the following description, the same description may be made.
As shown in FIG. 5, the pixel sharing structure PCa and the pixel sharing structure PCb are arranged in the order of the pixel sharing structure PCa and the pixel sharing structure PCb along the X direction. A description of the X direction will be described later.

Further, in FIG. 5, the pixel layer 10 uses two pixel sharing structures including one pixel sharing structure PCa and one pixel sharing structure PCb arranged along the X direction as one repeating unit. , X and Y directions are arranged in an array. A description of the Y direction will be described later.
In other words, as shown in FIG. 5, the pixel layer 10 included in the image pickup element of the present technology has m pixel sharing structures having j pixels in the X direction and k pixels in the Y direction, and m pixels in the X direction. Arranged in an array of n in the Y direction, a pixel shared structure array containing m × n pixel shared structures is used as one repeating unit, and the repeating units are p in the X direction and in the Y direction. It has a pixel array arranged in an array of q. Here, m and n are integers of 1 or more and m × n is 2 or more, and p and q are integers of 2 or more, respectively. As an example, in the first embodiment illustrated in FIG. 4, m = 2 and n = 1, but m and n may be integers of 1 or more and m × n of 2 or more, respectively. For example, they may be arranged so that the values are other than m = 2 and n = 1.

<Photodiode>
Each of the eight photodiode PDs photoelectrically converts the incident light, and generates and stores an electric charge according to the amount of light of the photoelectric conversion. One end of the photodiode PD is grounded. The other end of the photodiode PD is connected to the transfer transistor TR.
Further, the eight photodiode PDs are parallel to the first group formed by the four photodiode PDs of 2 rows × 2 columns when viewed from the light incident direction and the first group when viewed from the light incident direction. Includes a second group placed in. In the first group, two photodiode PDs arranged diagonally form a green pixel in which a green color filter is laminated. Then, one of the remaining two photodiode PDs forms a red pixel on which a red color filter is laminated, and the other photodiode PD of the remaining two forms a blue pixel on which a blue color filter is laminated.
Therefore, the pixel sharing structure PC (pixel sharing structure for eight pixels) includes four green pixels, two red pixels, and two blue pixels.

<Transistor>
The transfer transistor TR is arranged so as to connect the photodiode PD and the floating diffusion FD described later. The eight transfer transistors TR are connected to each of the eight photodiodes PD, one for each. Further, the transfer transistor TR is formed by using polysilicon, for example.
Further, the transfer transistor TR transfers the signal charge accumulated in the photodiode PD to the floating diffusion FD according to the drive signal supplied from the timing control unit (not shown).
Therefore, the pixel sharing structure PC including the photodiode PD and the transfer transistor TR photoelectrically converts the incident light and outputs an image signal.

<Floating diffusion>
As shown in FIG. 2, one pixel-shared structure PC includes two floating diffusion FDs. One floating diffusion FD is electrically connected (shared by the four photodiodes PD) to the four photodiodes PDs that make up the first group. The other floating diffusion FD is electrically connected (shared by the four photodiodes PD) to the four photodiode PDs that make up the second group. Then, the two floating diffusion FDs are electrically connected so as to have an equipotential potential by a connection wiring JW connecting them. Further, the two floating diffusion FDs are also connected to the reset transistor RST and the amplification transistor AMP by the connection wiring JW. That is, in the pixel sharing structure PC shown in FIG. 2, on the equivalent circuit, the floating diffusion FDs that are electrically connected so as to have equal potentials and become one are provided in the pixel sharing structure PC with eight photos. It has a configuration shared by a diode PD (shared by eight pixels provided in a pixel sharing structure PC).
The signal charge accumulated in the photodiode PD is transferred to the floating diffusion FD via the transfer transistor TR. Then, the floating diffusion FD accumulates the transferred electric charge and converts it into a voltage.

<Reset transistor>
The reset transistor RST is connected to the floating diffusion FD and the power supply wiring VDD.
Further, the reset transistor RST turns on or off the discharge of the electric charge accumulated in the floating diffusion FD and the electric charge generated in the photodiode PD other than the imaging period according to the drive signal supplied from the timing control unit.

<Amplification transistor>
The amplification transistor AMP is connected to the floating diffusion FD, the power supply wiring VDD, and the selection transistor SEL.
Further, the amplification transistor AMP reads out the potential of the floating diffusion FD reset by the reset transistor RST as a reset level. Further, the amplification transistor AMP amplifies the voltage corresponding to the signal charge stored in the floating diffusion FD to which the signal charge is transferred by the transfer transistor TR. That is, each amplification transistor AMP reads the signal charge transferred to the floating diffusion FD as an electric signal, and further amplifies the read electric signal.

<Selection transistor>
As shown in FIG. 3, the selection transistor SEL is connected to the amplification transistor AMP and the vertical signal line VSL.
Further, the selection transistor SEL is a transistor that controls input of the output of the pixel circuit 11 to the image processing circuit 21. The selection transistor SEL may be formed in the pixel layer 10 as a part of the pixel circuit 11, and as shown in FIG. 1, the signal processing layer 20 may be formed as a part of the circuit connected to the signal processing circuit 21. It may be formed in or as a configuration.

Further, the selection transistor SEL turns on or off the output of the voltage signal from the amplification transistor AMP to the vertical signal line VSL according to the drive signal supplied from the timing control unit.
When the selection transistor SEL turns on the output of the voltage signal, the voltage (voltage signal) amplified by the amplification transistor AMP is output to the vertical signal line VSL via the selection transistor SEL, and is ahead of the vertical signal line VSL. It is output to the connected signal processing circuit 21. The signal processing circuit 21 will be described later.

<Signal processing layer>
The image pickup device of the present technology includes a plurality of layers of signal processing layers 20, more specifically, m × n / t layers of signal processing layers 20 stacked along the incident direction of light. Note that m and n are the numbers in which the pixel sharing structures are arranged in the X direction and the Y direction in the pixel sharing structure array which is a repeating unit constituting the pixel array described above. In the case of the image sensor of the first embodiment, as shown in FIGS. 1 and 5, m = 2 and n = 1. t is the number of pixel sharing structure PCs connected to one signal processing circuit 21. In the following description, the number of pixel sharing structure PCs connected to one signal processing circuit 21 will be referred to as the number of connections t. Further, in the case of the image sensor of the first embodiment, t = 1 as shown in FIGS. 1 and 5. Then, in the case of the image pickup device of the first embodiment, the signal processing layer 20 is provided by stacking two layers of m × n / t =. Therefore, the signal processing layer 20 is laminated on the pixel layer 10 and includes the first signal processing layer 20a and the second signal processing layer 20b.
That is, the image pickup device of the first embodiment has two layers of signal processing layers 20 (first signal processing layer 20a, second signal processing) as a plurality of layers of signal processing layers 20 stacked on each other along the incident direction of light. Layer 20b) is provided.

Further, the signal processing layer 20 is electrically connected to the pixel layer 10 by a metal direct coupling (Cu-Cu connection).
The metal direct coupling between the pixel layer 10 and the signal processing layer 20 means that the metal terminal 10t (Cu terminal) formed on the surface of the pixel layer 10 facing the signal processing layer 20 and the pixel layer 10 of the signal processing layer 20 face each other. It has a structure in which a metal terminal 20t (Cu terminal) formed on the surface is directly connected.

The structure in which the pixel layer 10 and the signal processing layer 20 are connected by direct metal bonding is formed by using the following manufacturing methods (1) to (3).
Manufacturing method (1). A photodiode PD, a transistor, and a wiring layer are formed on the semiconductor substrate on which the pixel layer 10 is formed, and a circuit to be arranged on the pixel layer 10 is formed. After that, an electrical connection means (for example, a conductive via) for connecting the formed circuit and the metal terminal formed on the outermost surface of the pixel layer 10 is formed, and further, the metal terminal 10t is provided on the outermost surface of the pixel layer 10. Form.
Manufacturing method (2). A transistor and a wiring layer are formed on the semiconductor substrate on which the signal processing layer 20 is formed, and a circuit to be arranged on the signal processing layer 20 is formed. After that, an electrical connection means (via) for connecting the formed circuit and the metal terminal formed on the outermost surface of the signal processing layer 20 is formed, and further, the metal terminal 20t is formed on the outermost surface of the signal processing layer 20. ..
Manufacturing method (3). The substrate of the pixel layer 10 having the metal terminal 10t formed on the outermost surface and the substrate of the signal processing layer 20 having the metal terminal 20t formed on the outermost surface are bonded so that the metal terminals 10t and 20t are joined to each other.

The first signal processing layer 20a is laminated on the pixel layer 10 and has a first vertical signal line VSLa and a plurality of first signal processing circuits 21a.
The first vertical signal line VSLa is a wiring that outputs an electric signal amplified by the amplification transistor AMP included in the pixel circuit 11a to the first signal processing circuit 21a. Further, a selection transistor SEL is connected to the first vertical signal line VSLa.

The first signal processing circuit 21a processes the image signal input from the pixel sharing structure PCa and outputs it to the output layer 30.
A pixel sharing structure PCa is connected to one first signal processing circuit 21a so that an image signal output by one pixel sharing structure PCa can be input. That is, in the first embodiment, an example in which the number of connections t = 1 is shown. An example in which the number of connections is other than 1 will be described later by exemplifying another embodiment.

Further, the plurality of first signal processing circuits 21a process the input image signals in parallel with each other.
Further, as shown in FIG. 5, the plurality of first signal processing circuits 21a are arranged in an array along the X direction and the Y direction. Further, as shown in FIG. 5, the pixel sharing structure PCa connected to the first signal processing circuit 21a is arranged in an array along the X direction and the Y direction.
Note that, in FIG. 1, only a part of the plurality of first signal processing circuits 21a and the pixel sharing structure PCa arranged in an array along the X direction and the Y direction in FIG. 5 are shown.

As shown in FIG. 5, the X direction is a direction orthogonal to the direction in which the first group and the second group included in the eight photodiode PDs are arranged. The Y direction is a direction in which the first group and the second group included in the eight photodiode PDs are arranged, and is a direction orthogonal to the X direction.

Further, as shown in FIG. 5, in the first signal processing circuit 21a, the area seen from the direction in which the pixel layer 10 and the signal processing layer 20 are stacked (stacking direction) is the pixel sharing structure PCa viewed from the stacking direction. Is larger than the area of.
As an example, in the first embodiment, the area of one first signal processing circuit 21a seen from the stacking direction is m × n times the area of one pixel shared structure PCa seen from the stacking direction. There is. Note that m and n are the numbers in which the pixel sharing structure PCs are arranged in the X direction and the Y direction in the pixel sharing structure array which is a repeating unit constituting the pixel array described above. In the case of the image sensor of the first embodiment, as shown in FIGS. 1 and 5, m = 2 and n = 1. Further, in the first embodiment, as an example, as shown in FIG. 6, the area of one first signal processing circuit 21a seen from the stacking direction becomes the area of one pixel shared structure PCa seen from the stacking direction. On the other hand, a case where m × n times (m = 2, n = 1) will be described.

Specifically, when viewed from the stacking direction, as shown in FIG. 5, one first signal processing circuit 21a starts from the first pixel sharing structure PC, and is the mth and Y direction in the X direction. It extends over the nth pixel sharing structure PCa (in the first embodiment, m = 2, n = 1).
Therefore, in the pair of one pixel sharing structure PCa connected to each other and one first signal processing circuit 21a, the area of the first signal processing circuit 21a seen from the stacking direction is the pixel sharing structure seen from the stacking direction. It is larger than the area of PCa, and more specifically, it has a relationship of m × n times (m = 2, n = 1). As described above, one pixel sharing structure PCa includes j × k (j = 2, k = 4) pixels. Therefore, the area of the first signal processing circuit 21a is j × k × m × n times the area of one pixel.
As described above, (A) the image pickup device of the first embodiment and (B) the image pickup device of the first embodiment are arranged in a pixel array with the signal processing circuit of a certain area as a repeating unit, for example. Comparing with an image sensor in which a signal processing circuit having the same area as the area of one pixel is arranged in a pixel array as a repeating unit, (A) the image sensor provided with the first embodiment has a larger area. It is possible to provide a large signal processing circuit, which makes it possible to perform more advanced signal processing.

The second signal processing layer 20b is laminated on the first signal processing layer 20a, and includes a second vertical signal line VSLb and a plurality of second signal processing circuits 21b.
Further, the second signal processing layer 20b is electrically connected to the first signal processing layer 20a by a metal direct coupling.
The metal direct bonding between the first signal processing layer 20a and the second signal processing layer 20b is a metal terminal 20at (Cu terminal) formed on the first signal processing layer 20a and a metal terminal formed on the second signal processing layer 20b. It has a structure in which 20 bt (Cu terminal) is directly connected. The metal terminal 20at (Cu terminal) formed on the first signal processing layer 20a is formed on a surface of the first signal processing layer 20a facing the second signal processing layer 20b. The metal terminal 20bt (Cu terminal) formed on the second signal processing layer 20b is formed on a surface of the second signal processing layer 20b facing the first signal processing layer 20a.

The second vertical signal line VSLb is a wiring that outputs an electric signal amplified by the amplification transistor AMP included in the pixel circuit 11b to the second signal processing circuit 21b. Further, a selection transistor SEL is connected to the second vertical signal line VSLb.

The second signal processing circuit 21b processes the image signal input from the pixel sharing structure PCb and outputs it to the output layer 30.
A pixel sharing structure PCb is connected to one second signal processing circuit 21b so that an image signal output by one pixel sharing structure PCb can be input. That is, in the first embodiment, an example in which the number of connections t = 1 is shown. An example in which the number of connections is other than 1 will be described later by exemplifying another embodiment.
Further, the plurality of second signal processing circuits 21b process the input image signals in parallel with each other.

Further, as shown in FIG. 5, the plurality of second signal processing circuits 21b are arranged in an array along the X direction and the Y direction. Further, as shown in FIG. 5, the pixel sharing structure PCbs connected to the second signal processing circuit 21b are arranged in an array along the X direction and the Y direction.
Note that, in FIG. 1, only a part of the plurality of second signal processing circuits 21b and the pixel sharing structure PCb arranged in an array along the X direction and the Y direction in FIG. 5 are shown.
Further, as shown in FIG. 5, the area of the second signal processing circuit 21b seen from the stacking direction is larger than the area of the pixel sharing structure PCb seen from the stacking direction.

In the first embodiment, as an example, the area of one second signal processing circuit 21b viewed from the stacking direction is an integral multiple of 2 or more with respect to the area of one pixel shared structure PCb viewed from the stacking direction. The case will be described. Further, in the first embodiment, as an example, the area of one second signal processing circuit 21b viewed from the stacking direction is m × n times the area of one pixel shared structure PCb viewed from the stacking direction. It has become. Note that m and n are the numbers in which the pixel sharing structure PCs are arranged in the X direction and the Y direction in the pixel sharing structure array which is a repeating unit constituting the pixel array described above. In the case of the image sensor of the first embodiment, as shown in FIGS. 1 and 5, m = 2 and n = 1.
Specifically, when viewed from the stacking direction, as shown in FIG. 5, one second signal processing circuit 21b starts from the first pixel sharing structure PC, and is the mth and Y direction in the X direction. It extends over the nth pixel sharing structure PCb (in the first embodiment, m = 2, n = 1).

Therefore, in the pair consisting of one pixel sharing structure PCb and one second signal processing circuit 21b connected to each other, the area of the second signal processing circuit 21b seen from the stacking direction is the pixel sharing structure seen from the stacking direction. It is larger than the area of PCb, and more specifically, it has a relationship of m × n times (m = 2, n = 1). As described above, one pixel-shared structure PCb contains j × k (j = 2, k = 4) pixels. Therefore, the area of the first signal processing circuit 21b is j × k × m × n times the area of one pixel.
Therefore, (C) the image pickup device of the first embodiment and (D) the image pickup device of the first embodiment are arranged in a pixel array with the signal processing circuit of a certain area as a repeating unit, for example. Comparing with an image sensor in which a signal processing circuit having the same area as the area of one pixel is arranged in a pixel array as a repeating unit, (C) the image sensor provided with the first embodiment has a larger area. It is possible to provide a large signal processing circuit, which makes it possible to perform more advanced signal processing.

Further, as shown in FIG. 5, the laminated structure of the pixel sharing structure PCa and the pixel sharing structure PCb, the first signal processing circuit 21a, and the second signal processing circuit 21b is a unit unit having a structure in which they are repeatedly arranged. Is forming. Then, in the pixel array included in the image sensor, the plurality of unit units are repeatedly arranged in the X direction and the Y direction. The pitch at which the unit units are repeatedly arranged is equal to the size of the unit units. In the image pickup device of the present technology, the pitch in which the unit units are repeatedly arranged is such that the pitch in the X direction is m times the length in the X direction of the pixel sharing structure PC (in other words, the length j in the X direction of one pixel). × m times), the pitch in the Y direction is n times the length of the pixel sharing structure PC in the Y direction (in other words, k × n times the length of one pixel in the Y direction). As an example, in the case of the first embodiment shown in FIG. 5, j = 2, k = 4, m = 2, and n = 1.

The pixel array provided in the image sensor of the present technology is formed by repeating the above-mentioned unit units p in the X direction and q in the Y direction and arranging them in an array. As an example, in the first embodiment (j = 2, k = 4, m = 2, n = 1) shown in FIG. 5, a pixel array in which r pixels are arranged in the X direction and s pixels are arranged in the Y direction. When configuring an imaging device having a pixel array of 30 million pixels with = 6400 and s = 4800, the unit units are r / (m × j) = 6400 / (2 × 2) = 1600 in the X direction, Y. They are arranged in an array of s / (n × k) = 4800 / (1 × 4) = 1200 in the direction. In this case, on the first signal processing layer 20a, the first signal processing circuits 21a have r / (m × j) = 6400 / (2 × 2) = 1600 in the X direction and s / (n ×) in the Y direction. k) = 4800 / (1 × 4) = 1200 are arranged in an array, and on the second signal processing layer 20b, a second signal processing circuit 21b is arranged in the X direction at r / (m × j) = 6400 /. It is arranged in an array of (2 × 2) = 1600 and s / (n × k) = 4800 / (1 × 4) = 1200 in the Y direction. That is, the image pickup device of the present technology includes (r / (m × j)) × (s / (n × k)) signal processing circuits 21 at 20 in one signal processing layer, and this signal. The processing layer is provided by laminating (m × n / t) layers. By operating the total (r / (m × j)) × (s / (n × k)) × (m × n / t) signal processing circuits 21 configured in this way in parallel, the signal processing circuits 21 are operated in parallel. It is possible to perform signal processing in a shorter time than the image pickup device described in Patent Document 1 which does not have a configuration.
In the first embodiment, referring to FIGS. 1 to 6, in the repeating unit including the pixel sharing structure PC and the signal processing circuit 21, m pixel sharing structure PCs are arranged in the X direction and n in the Y direction. An example of m = 2 and n = 1 has been described as an example of individual arrangement, but if m and n are integers of 1 or more and m × n is 2 or more, then m = 2 and n = 1. It may be arranged so that the value is other than n = 1.

Further, the timing at which the first signal processing circuit 21a processes the image signal and the timing at which the second signal processing circuit 21b processes the image signal are set to the same timing. That is, the signal processing layer 20 including the first signal processing layer 20a and the second signal processing layer 20b performs signal processing on a plurality of pixels by the plurality of signal processing circuits 21 in parallel in the same time zone.
Specifically, the eight pixels of each of the plurality of pixel sharing structure PCs share one signal processing circuit 21 connected to the eight pixels, and one signal processing circuit 21 is used in time division. Signal processing is performed. As a result, the time-division signal processing performed on the eight pixels is executed in parallel in the same time zone in the plurality of signal processing circuits 21 included in the image pickup apparatus.

Therefore, the signal processing circuit 21 of each of the plurality of layers of signal processing layers 20 processes the image signals output by the plurality of pixels of the plurality of pixel sharing structure PCs in parallel.
That is, a plurality of signal processing circuits 21 electrically arranged in parallel in the vertical direction of the pixels (incident direction of light) and the arrangement direction of the pixels (X direction and Y direction) simultaneously perform signal processing. , It is possible to perform many signal processes at the same timing.
As described above, the signal processing circuit 21 of each of the plurality of layers of signal processing layers 20 processes the input image signals in parallel with each other.

<Output layer>
The output layer 30 is laminated on the signal processing layer 20.
Further, the output layer 30 is a circuit for sequentially reading out image signals output from a plurality of unit units arranged along the X direction and the Y direction shown in FIG. That is, the output layer 30 is similar to a circuit for sequentially reading signals from, for example, analog elements such as general memory elements and pixels arranged along the X and Y directions.

Further, the output layer 30 is electrically connected to the signal processing layer 20 by a metal direct coupling.
The direct metal bonding between the signal processing layer 20 and the output layer 30 is formed on a Cu terminal formed on a surface of the signal processing layer 20 facing the output layer 30 and a surface of the output layer 30 facing the signal processing layer 20. It has a structure in which the Cu terminal is directly connected.

<Action / effect of the first embodiment>
The image sensor of the first embodiment can exert the following actions and effects.
(1) A pixel layer 10 having a pixel sharing structure PC including a plurality of pixels that photoelectrically convert incident light and output an image signal, and a signal processing circuit 21 that is laminated on the pixel layer 10 and processes an image signal. The signal processing layer 20 is provided. Further, the pixel layer 10 has a plurality of pixel sharing structure PCs arranged in an array, and the signal processing layer 20 has a plurality of signal processing circuits 21 arranged in an array. Then, one pixel sharing structure PC is connected to one signal processing circuit 21 so that the image signal output by one pixel sharing structure PC can be input. Further, the plurality of signal processing circuits 21 process the input image signals in parallel with each other.
As a result, it is possible to shorten the time for signal processing and outputting the captured image by processing the image signals input from the plurality of pixel sharing structure PCs in parallel with each other by the plurality of signal processing circuits 21. It becomes possible to provide an image pickup device.

(2) A plurality of layers of signal processing layers 20 (first signal processing layer 20a, second signal processing layer 20b) stacked on each other are provided. Further, the signal processing circuits 21 of the plurality of signal processing layers 20 process the input image signals in parallel with each other.
As a result, a plurality of image signals can be processed in parallel with each other by the signal processing circuits 21 each of the plurality of layers of signal processing layers 20 without increasing the area of the signal processing layer 20.

(3) A plurality of layers of signal processing layers 20 are provided.
As a result, the image signal can be processed in the signal processing circuit 21 included in each of the plurality of layers of the signal processing layer 20 without increasing the area of the one-layer signal processing layer 20.

(4) The plurality of layers of signal processing layers 20 are electrically connected by direct metal bonding.
As a result, it is possible to suppress the deviation of the read time due to the signal processing layers 20 of the plurality of layers with respect to the signal output from the pixel layer 10 to the signal processing layers 20 of the plurality of layers.

(5) The area of the signal processing circuit 21 seen from the stacking direction is larger than the area of one pixel seen from the stacking direction and larger than the area of the pixel sharing structure PC, more specifically, m ×. It has a relationship of n times (m = 2, n = 1). As described above, one pixel-shared structure PCb contains j × k (j = 2, k = 4) pixels. Therefore, the area of the first signal processing circuit 21b is j × k × m × n times the area of one pixel.
As a result, this configuration is not provided (that is, the area of the signal processing circuit 21 is the same as the area of the pixel sharing structure PC, or the area of the signal processing circuit 21 is the same as the area of one pixel). , The circuit area of the signal processing circuit 21 can be increased. As a result, more complicated signal processing can be performed in the signal processing circuit 21.

(6) The area of the signal processing circuit 21 seen from the stacking direction is an integral multiple of 2 or more with respect to the area of the pixel sharing structure PC seen from the stacking direction.
As a result, the signal processing circuit 21 and the pixel sharing structure PC can be efficiently arranged when viewed from the stacking direction.

(7) The pixel sharing structure PC includes 8 pixels.
As a result, the signal processing circuit 21 can process a plurality of image signals output by the four green pixels, the two red pixels, and the two blue pixels, respectively.

(8) The signal processing layer 20 is electrically connected to the pixel layer 10 by a metal direct coupling.
As a result, it is possible to suppress a deviation in the read time due to the signal processing layer 20 with respect to the signal output from the pixel layer 10 to the signal processing layer 20.

(9) An output layer 30 that is laminated on the signal processing layer 20 and reads out the image signal processed by the signal processing layer 20 is further provided. In addition to this, the output layer 30 is electrically connected to the signal processing layer 20 by a metal direct coupling.
As a result, it is possible to suppress a deviation in the read time due to the output layer 30 with respect to the signal output from the signal processing layer 20 to the output layer 30.

(Second Embodiment)
The image pickup device according to the second embodiment is different from the first embodiment in the configuration of the pixel layer and the signal processing layer. Specifically, in the first embodiment, the number of connections t, which is the number of pixel sharing structure PCs connected to one signal processing circuit 21, is 1, but in the second embodiment, the number of connections t. An example in which there is a plurality of is shown. In the following description, the description of the parts common to the first embodiment may be omitted.

<Pixel layer>
As shown in FIG. 7, the pixel layer 10 has a plurality of pixel circuits 11. The plurality of pixel circuits 11 are arranged in parallel when viewed from the stacking direction.
Note that FIG. 7 shows, as an example, four pixel circuits 11a to 11d among the plurality of pixel circuits 11 included in the pixel layer 10.

The second embodiment includes the same pixel sharing structure (FIG. 2) as the first embodiment. That is, a case where one pixel circuit 11 includes a pixel sharing structure PC including pixels for eight pixels, and the above-mentioned j = 2 and k = 4 will be described.
Further, as shown in FIG. 8, the pixel layer 10 has a plurality of pixel sharing structure PCs arranged in an array. In FIG. 8, the pixel sharing structure PC included in the pixel circuit 11a is referred to as “pixel sharing structure PCa”, and the pixel sharing structure PC included in the pixel circuit 11b is referred to as “pixel sharing structure PCb”. Similarly, the pixel shared structure PC included in the pixel circuit 11c is referred to as "pixel shared structure PCc", and the pixel shared structure PC included in the pixel circuit 11d is referred to as "pixel shared structure PCd". Further, in the following description, the same description may be made.

As shown in FIG. 8, the pixel sharing structures PCa to PCd are arranged in the order of the pixel sharing structure PCa, the pixel sharing structure PCc, the pixel sharing structure PCb, and the pixel sharing structure PCd along the X direction. It is arranged.
Further, in FIG. 8, the pixel layer 10 has four pixel sharing arranged in the order of the pixel sharing structure PCa, the pixel sharing structure PCc, the pixel sharing structure PCb, and the pixel sharing structure PCd along the X direction. The structure PC is arranged in an array along the X direction and the Y direction with the structure PC as one repeating unit. A description of the Y direction will be described later.
In other words, as shown in FIG. 8, the pixel layer 10 provided in the image pickup element of the present technology includes m pixel sharing structure PCs having j pixels in the X direction and k pixels in the Y direction. In addition, the pixel shared structure array including the m × n pixel shared structure PCs arranged in an array of n in the Y direction is used as one repeating unit, and the repeating units are p in the X direction. It includes a pixel array arranged in an array of q in the Y direction. Here, m and n are integers of 1 or more and m × n is 2 or more, and p and q are integers of 2 or more, respectively. As an example, in the second embodiment illustrated in FIG. 8, m = 4 and n = 1, but m and n are integers of 1 or more and m × n is 2 or more, respectively. , M = 4 and may be arranged so as to have a value other than n = 1.

<Signal processing layer>
The image pickup device of the present technology includes a plurality of layers of signal processing layers 20, more specifically, m × n / t layer signal processing layers 20 stacked along the incident direction of light. Here, m and n are the numbers in which the pixel sharing structure PCs are arranged in the X direction and the Y direction in the pixel sharing structure array which is a repeating unit constituting the pixel array described above. In the case of the second embodiment, as shown in FIGS. 7 and 8, m = 4, n = 1, and the number of connections t = 2. Then, in the case of the second embodiment, the signal processing layer 20 is provided by stacking m × n / t = 2, that is, two layers. The signal processing layer 20 is laminated on the pixel layer 10 and includes a first signal processing layer 20a and a second signal processing layer 20b.
That is, as in the first embodiment, the image pickup device of the second embodiment is a two-layer signal processing layer 20 (first signal processing) as a plurality of layers of signal processing layers 20 stacked on each other along the incident direction of light. A layer 20a and a second signal processing layer 20b) are provided.

The first signal processing layer 20a is laminated on the pixel layer 10, and has a first upstream side vertical signal line VSLau, a first downstream side vertical signal line VSRad, and a plurality of first signal processing circuits 21a.

The first upstream vertical signal line VSLau is a wiring that outputs an electric signal amplified by the amplification transistor AMP included in the pixel circuit 11a to the first signal processing circuit 21a. Further, a selection transistor SEL is connected to the first upstream side vertical signal line VSLau.
The first downstream vertical signal line VSRad is a wiring that outputs an electric signal amplified by the amplification transistor AMP included in the pixel circuit 11b to the first signal processing circuit 21a. Further, a selection transistor SEL is connected to the first downstream vertical signal line VSRad.

Pixel sharing so that the image signal output by one pixel sharing structure PCa included in the pixel circuit 11a and one pixel sharing structure PCb included in the pixel circuit 11b can be input to one first signal processing circuit 21a. The structure PCa and the pixel sharing structure PCb are connected.
That is, at least one pixel sharing structure (pixel sharing structure PCb) is additionally connected to one first signal processing circuit 21a so that an image signal can be input in addition to the pixel sharing structure PCa. , A plurality of pixel sharing structures (pixel sharing structures PCa, PCb) are connected. In other words, the second embodiment shown in FIGS. 7 and 8 shows an example of the number of connections t (that is, the number of pixel sharing structure PCs connected to one signal processing circuit 21) = 2.
Therefore, in the second embodiment, one first signal processing circuit 21a is shared by a plurality of pixel circuits 11 (two pixel circuits 11a and 11b).

Further, one first signal processing circuit 21a processes the image signal input from the pixel sharing structure PCa and the image signal input from the pixel sharing structure PCb in a time division and outputs the image signal to the output layer 30. ..
Further, each of the plurality of first signal processing circuits 21a processes the input image signals in parallel with each other.

Further, as shown in FIG. 8, the plurality of first signal processing circuits 21a are arranged in an array along the X direction and the Y direction.
Note that, in FIG. 7, only a part of the plurality of first signal processing circuits 21a and the pixel sharing structures PCa and PCb arranged in an array along the X direction and the Y direction in FIG. 8 are shown. ..
Further, as shown in FIG. 9, the area of the first signal processing circuit 21a seen from the stacking direction is larger than the area of the pixel shared structure PCa and the pixel shared structure PCb seen from the stacking direction. In FIG. 9, the position of the pixel sharing structure PCb is changed to the position of the pixel sharing structure PCc for the purpose of comparing the areas.

In the second embodiment, as an example, the area of one first signal processing circuit 21a viewed from the stacking direction is m × n with respect to the areas of the pixel shared structure PCa and the pixel shared structure PCb viewed from the stacking direction. It has doubled. Here, m and n are the numbers in which the pixel sharing structure PCs are arranged in the X direction and the Y direction in the pixel sharing structure array which is a repeating unit constituting the pixel array described above. In the case of the image sensor of the second embodiment, as shown in FIGS. 7 and 8, m = 4 and n = 1. Further, in the second embodiment, as an example, as shown in FIG. 9, the area of one first signal processing circuit 21a viewed from the stacking direction is the pixel sharing structure PCa and the pixel sharing structure viewed from the stacking direction. A case where the area is m × n times (m = 4, n = 1) with respect to the area of the PCb will be described.
Specifically, when viewed from the stacking direction, as shown in FIG. 8, one first signal processing circuit 21a starts from the first pixel sharing structure PCa and is the mth and Y direction in the X direction. It extends over the nth pixel sharing structure PCd (in the second embodiment, m = 4, n = 1).
Therefore, in the pair of the pixel sharing structure PCa and the pixel sharing structure PCb connected to each other and one first signal processing circuit 21a, the area of the first signal processing circuit 21a viewed from the stacking direction is viewed from the stacking direction. It is larger than the respective areas of the pixel-sharing structure PCa and the pixel-sharing structure PCb, and more specifically, it has a relationship of m × n times (m = 4, n = 1). As described above, each of the pixel sharing structures PCa and PCb contains j × k (j = 2, k = 4) pixels. Therefore, the area of the first signal processing circuit 21a in the second embodiment is j × k × m × n times the area of one pixel (j = 2, k = 4, m = 4, n = 1). It has become. As a result, the area of the first signal processing circuit 21a in the first embodiment (j × k × m × n times the area of one pixel and j = 2, k = 4, m = 2, n = 1). It is possible to provide a signal processing circuit having a larger area than that of the above, thereby performing more advanced signal processing.

The second signal processing layer 20b is laminated on the first signal processing layer 20a, and has a second upstream side vertical signal line VSLbu, a second downstream side vertical signal line VSLbd, and a plurality of second signal processing circuits 21b. ..
Further, the second signal processing layer 20b is electrically connected to the first signal processing layer 20a by a metal direct coupling.

The second upstream vertical signal line VSLbu is a wiring that outputs an electric signal amplified by the amplification transistor AMP included in the pixel circuit 11c to the second signal processing circuit 21b. Further, a selection transistor SEL is connected to the second upstream vertical signal line VSLbu.
The second downstream vertical signal line VSLbd is a wiring that outputs an electric signal amplified by the amplification transistor AMP included in the pixel circuit 11d to the second signal processing circuit 21b. Further, a selection transistor SEL is connected to the second downstream vertical signal line VSLbd.

Pixel sharing so that the image signal output by one pixel sharing structure PCc included in the pixel circuit 11c and one pixel sharing structure PCd included in the pixel circuit 11d can be input to one second signal processing circuit 21b. The structure PCc and the pixel sharing structure PCd are connected.
That is, at least one pixel sharing structure (pixel sharing structure PCd) is additionally connected to one second signal processing circuit 21b so that an image signal can be input in addition to the pixel sharing structure PCc. , A plurality of pixel sharing structures (pixel sharing structures PCc, PCd) are connected. In other words, the second embodiment shown in FIGS. 7 and 8 shows an example of the number of connections t (that is, the number of pixel sharing structure PCs connected to one signal processing circuit 21) = 2.
Therefore, in the second embodiment, one second signal processing circuit 21b is shared by a plurality of pixel circuits 11 (two pixel circuits 11c and 11d).

Further, one second signal processing circuit 21b processes the image signal input from the pixel sharing structure PCc and the image signal input from the pixel sharing structure PCd in a time-divided manner and outputs the image signal to the output layer 30. ..
Further, each of the plurality of second signal processing circuits 21b processes the input image signals in parallel with each other.

Further, as shown in FIG. 8, the plurality of second signal processing circuits 21b are arranged in an array along the X direction and the Y direction.
Note that, in FIG. 7, only a part of the plurality of second signal processing circuits 21b and the pixel sharing structures PCc and PCd arranged in an array along the X and Y directions in FIG. 8 are shown. ..
Further, in the second signal processing circuit 21b, the area seen from the stacking direction is larger than the areas of the pixel sharing structure PCc and the pixel sharing structure PCd seen from the stacking direction (see FIG. 9).

In the second embodiment, as an example, the area of one second signal processing circuit 21b viewed from the stacking direction is m × n with respect to the areas of the pixel shared structure PCc and the pixel shared structure PCd viewed from the stacking direction. It has doubled. Here, m and n are the numbers in which the pixel sharing structure PCs are arranged in the X direction and the Y direction in the pixel sharing structure array which is a repeating unit constituting the pixel array described above. In the case of the second embodiment, as shown in FIGS. 7 and 8, m = 4 and n = 1. Further, in the second embodiment, as an example, as shown in FIG. 5, the area of one second signal processing circuit 21b viewed from the stacking direction is the pixel sharing structure PCc and the pixel sharing structure viewed from the stacking direction. A case where m × n times (m = 4, n = 1) with respect to the area of PCd will be described.
Specifically, when viewed from the stacking direction, one second signal processing circuit 21b is the nth from the first pixel sharing structure PCa (n = 4 in the second embodiment) as shown in FIG. ) Extends over the pixel sharing structure PCd.

Therefore, in the pair of the pixel sharing structure PCc and the pixel sharing structure PCd connected to each other and one second signal processing circuit 21b, the area of the second signal processing circuit 21b viewed from the stacking direction is viewed from the stacking direction. It is larger than the respective areas of the pixel-shared structure PCc and the pixel-shared structure PCd, and more specifically, it has a relationship of m × n times (m = 4, n = 1). As described above, each of the pixel sharing structures PCc and PCd contains j × k (j = 2, k = 4) pixels. Therefore, the area of the second signal processing circuit 21b in the second embodiment is j × k × m × n times the area of one pixel (j = 2, k = 4, m = 4, n = 1). It has become. As a result, the area of the first signal processing circuit 21b in the first embodiment (j × k × m × n times the area of one pixel and j = 2, k = 4, m = 2, n = 1). Since it is possible to provide a signal processing circuit having a larger area than that of the above, it is possible to perform more advanced signal processing.
Further, as shown in FIG. 8, the laminated structure of the pixel sharing structures PCa to PCd, the first signal processing circuit 21a, and the second signal processing circuit 21b forms a unit unit having a structure repeatedly arranged. There is. Then, in the pixel array included in the image sensor, the plurality of unit units are repeatedly arranged in the X direction and the Y direction. The pitch at which the unit units are repeatedly arranged is equal to the size of the unit units. In the image pickup device of the present technology, the pitch in which the unit units are repeatedly arranged is such that the pitch in the X direction is m times the length in the X direction of the pixel sharing structure PC (j × m times the length in the X direction of one pixel). ), The pitch in the Y direction is n times the length of the pixel sharing structure PC in the Y direction (k × n times the length of one pixel in the Y direction). As an example, in the case of the second embodiment shown in FIG. 8, j = 2, k = 4, m = 4, n = 1.

In the pixel array provided in the image sensor of the present technology, p unit units in the X direction and q units in the Y direction are repeatedly arranged in an array. As an example, in the second embodiment (j = 2, k = 4, m = 4, n = 1) shown in FIG. 8, it is a pixel array in which r pixels are arranged in the X direction and s pixels are arranged in the Y direction. When configuring an imaging device having a pixel array of 30 million pixels such that = 6400 and s = 4800, the unit units are r / (m × j) = 6400 / (4 × 2) = 800 in the X direction, Y. They are arranged in an array of s / (n × k) = 4800 / (1 × 4) = 1200 in the direction. In this case, on the first signal processing layer 20a, the first signal processing circuits 21a have r / (m × j) = 6400 / (4 × 2) = 800 in the X direction and s / (n ×) in the Y direction. k) = 4800 / (1 × 4) = 1200 are arranged in an array, and on the second signal processing layer 20b, a second signal processing circuit 21b is arranged in the X direction at r / (m × j) = 6400 /. It is arranged in an array of (4 × 2) = 800 pieces and s / (n × k) = 4800 / (1 × 4) = 1200 pieces in the Y direction. That is, the image pickup device of the present technology includes (r / (m × j)) × (s / (n × k)) signal processing circuits 21 in one signal processing layer at 20, and the signal processing layer. (M × n / t) are laminated and provided. By operating the total (r / (m × j)) × (s / (n × k)) × (m × n / t) signal processing circuits 21 configured in this way in parallel, the signal processing circuits 21 are operated in parallel. It is possible to perform signal processing in a shorter time than the image pickup device described in Patent Document 1 which does not have a configuration.

In the second embodiment, referring to FIGS. 7 and 8, in the repeating unit including the pixel sharing structure PC and the signal processing circuit 21, m pixel sharing structure PCs are arranged in the X direction and n in the Y direction. As an example of individual arrangement, an example of m = 4 and n = 1 and the number of connections t = 2 has been described, but m and n are integers of 1 or more and m × n of 4 or more, respectively. If so, they may be arranged so that the values are other than m = 4 and n = 1.
Further, the timing at which the first signal processing circuit 21a processes the image signal and the timing at which the second signal processing circuit 21b processes the image signal are set to the same timing. That is, the signal processing layer 20 including the first signal processing layer 20a and the second signal processing layer 20b performs signal processing on a plurality of pixels by the plurality of signal processing circuits 21 in parallel in the same time zone.

As described above, one signal processing circuit 21 includes an image signal output by a part (for example, pixel sharing structure PCa) of the connected plurality of pixel sharing structure PCs, and a plurality of connected pixel sharing structures. The image signal output by at least one of the remaining ones (for example, the pixel sharing structure PCb) is processed by time division.
Further, the signal processing circuit 21 of each of the plurality of layers of signal processing layers 20 processes the input image signals in parallel with each other.

<Action / effect of the second embodiment>
The image sensor of the second embodiment can exert the following actions and effects.
(1) At least one pixel sharing structure PC is additionally connected to one signal processing circuit 21 so that an image signal can be input, and a plurality of the pixel sharing structure PCs are connected. In addition to this, one signal processing circuit 21 outputs an image signal that is partially output from a plurality of connected pixel-sharing structure PCs, and at least one of the remaining one of the connected plurality of pixel-sharing structure PCs. The output image signal is processed in time division.
As a result, a plurality of pixel sharing structure PCs sharing one signal processing circuit 21 process the image signal in a time-divided manner (sequentially) using one signal processing circuit 21, so that the captured image is signaled. It is possible to shorten the processing time and output time.

(2) A plurality of layers of signal processing layers 20 stacked on each other are provided. Then, the signal processing circuits 21 of the plurality of signal processing layers 20 process the input image signals in parallel with each other.
As a result, a plurality of image signals can be processed in parallel with each other by the signal processing circuits 21 each of the plurality of layers of signal processing layers 20 without increasing the area of the signal processing layer 20.

(Third Embodiment)
The image pickup device according to the third embodiment is different from the first embodiment in the configuration of the pixel layer and the signal processing layer. Specifically, in the first embodiment, an example is shown in which the number of pixel sharing structure PCs (that is, m × n) provided in the repeating unit constituting the pixel array is 2, but in the third embodiment, it is repeated. An example is shown in the case where the number of pixel sharing structure PCs provided in the unit is larger than 2. An example is shown in which the number of connections t is 1, which is the same as in the first embodiment. In the following description, the description of the parts common to the first and second embodiments may be omitted.

<Pixel layer>
As shown in FIG. 10, the pixel layer 10 has a plurality of pixel circuits 11. The plurality of pixel circuits 11 are arranged in parallel when viewed from the stacking direction.
Note that FIG. 10 shows, as an example, four pixel circuits 11a to 11d among the plurality of pixel circuits 11 included in the pixel layer 10.

The third embodiment includes the same pixel sharing structure (FIG. 2) as the first embodiment. That is, a case where one pixel circuit 11 includes a pixel sharing structure PC including pixels for eight pixels, and the above-mentioned j = 2 and k = 4 will be described.
Further, as shown in FIG. 11, the pixel layer 10 has a plurality of pixel sharing structure PCs arranged in an array. In FIG. 11, the pixel sharing structure PC included in the pixel circuit 11a is referred to as “pixel sharing structure PCa”, and the pixel sharing structure PC included in the pixel circuit 11b is referred to as “pixel sharing structure PCb”. Similarly, the pixel shared structure PC included in the pixel circuit 11c is referred to as "pixel shared structure PCc", and the pixel shared structure PC included in the pixel circuit 11d is referred to as "pixel shared structure PCd". Further, in the following description, the same description may be made.

As shown in FIG. 11, the pixel sharing structures PCa to PCd are arranged in the order of the pixel sharing structure PCa, the pixel sharing structure PCb, the pixel sharing structure PCc, and the pixel sharing structure PCd along the X direction. It is arranged.
Further, in FIG. 11, the pixel layer 10 has four pixel sharing arranged in the order of the pixel sharing structure PCa, the pixel sharing structure PCb, the pixel sharing structure PCc, and the pixel sharing structure PCd along the X direction. The structures are arranged in an array along the X direction and the Y direction as one repeating unit. A description of the Y direction will be described later.
In other words, as shown in FIG. 11, the pixel layer 10 included in the image pickup device of the present technology includes m pixel sharing structure PCs having j pixels in the X direction and k pixels in the Y direction. Moreover, they are arranged in an array of n in the Y direction. Further, a pixel shared structure array including m × n pixel shared structure PCs is used as one repeating unit, and the repeating units are arranged in an array of p in the X direction and q in the Y direction. It has an array. Here, m and n are integers of 1 or more and m × n is 4 or more, and p and q are integers of 2 or more, respectively. As an example, in the second embodiment illustrated in FIG. 8, m = 4 and n = 1, but m and n may be integers of 1 or more and m × n of 4 or more, respectively. For example, they may be arranged so that the values are other than m = 4 and n = 1. Therefore, for example, m = 2 or more and n = 2 or more may be used.

<Signal processing layer>
The image pickup device of the present technology includes a plurality of layers of signal processing layers 20, more specifically, m × n / t layer signal processing layers 20 stacked along the incident direction of light. Here, m and n are the numbers in which the pixel sharing structure PCs are arranged in the X direction and the Y direction in the pixel sharing structure array which is a repeating unit constituting the pixel array described above. In the case of the third embodiment, as shown in FIGS. 10 and 11, m = 4, n = 1 and the number of connections t (the number of pixel sharing structure PCs connected to one signal processing circuit 21). ) = 1. Then, in the case of the third embodiment, the signal processing layer 20 is provided by stacking the signal processing layers 20 in m × n / t = 4 layers. The signal processing layer 20 is laminated on the pixel layer 10, and includes a first signal processing layer 20a, a second signal processing layer 20b, a third signal processing layer 20c, and a fourth signal processing layer 20d.
That is, the image pickup element of the third embodiment has four layers of signal processing layers 20 (first signal processing layer 20a, second signal processing layer 20b, third signal processing) as a plurality of layers of signal processing layers 20 stacked on each other. A layer 20c and a fourth signal processing layer 20d) are provided.

The first signal processing layer 20a is laminated on the pixel layer 10, and includes a first vertical signal line VSLa and a plurality of first signal processing circuits 21a.
The first vertical signal line VSLa is a wiring that outputs an electric signal amplified by the amplification transistor AMP included in the pixel circuit 11a to the first signal processing circuit 21a.

The first signal processing circuit 21a processes the image signal input from the pixel sharing structure PCa and outputs it to the output layer 30.
A pixel sharing structure PCa is connected to one first signal processing circuit 21a so that an image signal output by one pixel sharing structure PCa can be input. In other words, the third embodiment shown in FIGS. 10 and 11 shows an example of the number of connections t (that is, the number of pixel sharing structure PCs connected to one signal processing circuit 21) = 1.

Further, the plurality of first signal processing circuits 21a process the input image signals in parallel with each other.
Further, as shown in FIG. 11, the plurality of first signal processing circuits 21a are arranged in an array along the X direction and the Y direction.
In FIG. 10, only a part of the plurality of first signal processing circuits 21a and 21b and the pixel sharing structures PCa, PCb, PCc and PCd arranged in an array along the X and Y directions in FIG. 11 Is described.

Further, as shown in FIG. 11, the area of the first signal processing circuit 21a seen from the stacking direction is larger than the area of the pixel sharing structure PCa seen from the stacking direction.
In the third embodiment, as an example, the area of one first signal processing circuit 21a seen from the stacking direction is m × n times the area of one pixel shared structure PCa seen from the stacking direction. There is. Here, m and n are the numbers in which the pixel sharing structure PCs are arranged in the X direction and the Y direction in the pixel sharing structure array which is a repeating unit constituting the pixel array described above. In the case of the third embodiment, as shown in FIGS. 10 and 11, m = 4 and n = 1. Further, in the third embodiment, as an example, as shown in FIG. 11, the area of one first signal processing circuit 21a seen from the stacking direction becomes the area of one pixel shared structure PCa seen from the stacking direction. On the other hand, a case where m × n times (m = 4, n = 1) will be described.

The second signal processing layer 20b is laminated on the first signal processing layer 20a, and includes a second vertical signal line VSLb and a plurality of second signal processing circuits 21b.
Further, the second signal processing layer 20b is electrically connected to the first signal processing layer 20a by a metal direct coupling.
The second vertical signal line VSLb is a wiring that outputs an electric signal amplified by the amplification transistor AMP included in the pixel circuit 11b to the second signal processing circuit 21b.

The second signal processing circuit 21b processes the image signal input from the pixel sharing structure PCb and outputs it to the output layer 30.
A pixel sharing structure PCb is connected to one second signal processing circuit 21b so that an image signal output by one pixel sharing structure PCb can be input.

Further, the plurality of second signal processing circuits 21b process the input image signals in parallel with each other.
Further, as shown in FIG. 11, the plurality of second signal processing circuits 21b are arranged in an array along the X direction and the Y direction.

Further, as shown in FIG. 11, the area of the second signal processing circuit 21b seen from the stacking direction is larger than the area of the pixel sharing structure PCb seen from the stacking direction.
Further, in the third embodiment, as an example, the area of one second signal processing circuit 21b viewed from the stacking direction is m × n times the area of one pixel shared structure PCb viewed from the stacking direction. It has become. In the case of the third embodiment, as shown in FIGS. 10 and 11, m = 4 and n = 1. Further, in the third embodiment, as an example, as shown in FIG. 11, the area of one second signal processing circuit 21b viewed from the stacking direction becomes the area of one pixel shared structure PCb viewed from the stacking direction. On the other hand, a case where m × n times (m = 4, n = 1) will be described.

The third signal processing layer 20c is laminated on the second signal processing layer 20b, and includes a third vertical signal line VSLc and a plurality of third signal processing circuits 21c.
Further, the third signal processing layer 20c is electrically connected to the second signal processing layer 20b by a metal direct coupling.
The third vertical signal line VSLc is a wiring that outputs an electric signal amplified by the amplification transistor AMP included in the pixel circuit 11c to the third signal processing circuit 21c.

The third signal processing circuit 21c processes the image signal input from the pixel sharing structure PCc and outputs it to the output layer 30.
A pixel sharing structure PCc is connected to one third signal processing circuit 21c so that an image signal output by one pixel sharing structure PCc can be input.

Further, the plurality of third signal processing circuits 21c process the input image signals in parallel with each other.
Further, as shown in FIG. 11, the plurality of third signal processing circuits 21c are arranged in an array along the X direction and the Y direction.

Further, as shown in FIG. 11, the area of the third signal processing circuit 21c seen from the stacking direction is larger than the area of the pixel sharing structure PCc seen from the stacking direction.
In the third embodiment, as an example, the area of one third signal processing circuit 21c seen from the stacking direction is m × n times the area of one pixel shared structure PCc seen from the stacking direction. There is. In the case of the third embodiment, as shown in FIGS. 10 and 11, m = 4 and n = 1. Further, in the third embodiment, as an example, as shown in FIG. 11, the area of one third signal processing circuit 21c seen from the stacking direction becomes the area of one pixel shared structure PCc seen from the stacking direction. On the other hand, a case where m × n times (m = 4, n = 1) will be described.

The fourth signal processing layer 20d is laminated on the third signal processing layer 20c, and includes a fourth vertical signal line VSLd and a plurality of fourth signal processing circuits 21d.
Further, the fourth signal processing layer 20d is electrically connected to the third signal processing layer 20c by a metal direct coupling.
The fourth vertical signal line VSLd is a wiring that outputs an electric signal amplified by the amplification transistor AMP included in the pixel circuit 11d to the fourth signal processing circuit 21d.

The fourth signal processing circuit 21d processes the image signal input from the pixel sharing structure PCd and outputs it to the output layer 30.
A pixel sharing structure PCd is connected to one fourth signal processing circuit 21d so that an image signal output by one pixel sharing structure PCd can be input.

Further, the plurality of fourth signal processing circuits 21d process the input image signals in parallel with each other.
Further, as shown in FIG. 11, the plurality of fourth signal processing circuits 21d are arranged in an array along the X direction and the Y direction.

Further, as shown in FIG. 11, the area of the fourth signal processing circuit 21d seen from the stacking direction is larger than the area of the pixel sharing structure PCd seen from the stacking direction.
In the third embodiment, as an example, the area of one fourth signal processing circuit 21d seen from the stacking direction is m × n times the area of one pixel shared structure PCd seen from the stacking direction. It has become. In the case of the third embodiment, as shown in FIGS. 10 and 11, m = 4 and n = 1. Further, in the third embodiment, as an example, as shown in FIG. 11, the area of one fourth signal processing circuit 21d seen from the stacking direction becomes the area of one pixel shared structure PCd seen from the stacking direction. On the other hand, a case where m × n times (m = 4, n = 1) will be described.
As described above, each of the pixel sharing structures PCa, PCb, PCc, and PCd contains j × k (j = 2, k = 4) pixels. Therefore, the area of the signal processing circuits 21a, 21b, 21c, 21d in the third embodiment is j × k × m × n times the area of one pixel (j = 2, k = 4, m = 4, n = 1). As a result, the area of the first signal processing circuit 21a in the first embodiment (j × k × m × n times the area of one pixel and j = 2, k = 4, m = 2, n = 1). Since it is possible to provide a signal processing circuit having a larger area than that of the above, it is possible to perform more advanced signal processing.

Further, as shown in FIG. 11, the laminated structure of the pixel sharing structure PCa to the pixel sharing structure PCd and the first signal processing circuit 21a to the fourth signal processing circuit 21d is a unit unit having a structure repeatedly arranged. Is forming. Then, in the pixel array provided in the image sensor, the plurality of unit units are repeatedly arranged in the X direction and the Y direction. The pitch at which the unit units are repeatedly arranged is equal to the size of the unit units. In the image pickup device of the present technology, the pitch in which the unit units are repeatedly arranged is such that the pitch in the X direction is m times the length in the X direction of the pixel sharing structure PC (j × m times the length in the X direction of one pixel). ), The pitch in the Y direction is n times the length of the pixel sharing structure PC in the Y direction (k × n times the length of one pixel in the Y direction). As an example, in the case of the third embodiment shown in FIG. 11, j = 2, k = 4, m = 4, n = 1.
In the pixel array provided in the image sensor of the present technology, the unit units are arranged repeatedly in an array of p in the X direction and q in the Y direction. As an example, in the third embodiment (j = 2, k = 4, m = 4, n = 1) shown in FIG. 11, a pixel array in which r pixels are arranged in the X direction and s pixels are arranged in the Y direction. When configuring an imaging device having a pixel array of 30 million pixels with = 6400 and s = 4800, the unit units are r / (m × j) = 6400 / (4 × 2) = 800 in the X direction, Y. They are arranged in an array of s / (n × k) = 4800 / (1 × 4) = 1200 in the direction. In this case, on the first signal processing layer 20a, the first signal processing circuits 21a have r / (m × j) = 6400 / (4 × 2) = 800 in the X direction and s / (n ×) in the Y direction. k) = 4800 / (1 × 4) = 1200 are arranged in an array, and on the second signal processing layer 20b, a second signal processing circuit 21b is arranged in the X direction at r / (m × j) = 6400 /. (4 × 2) = 800 pieces, s / (n × k) = 4800 / (1 × 4) = 1200 pieces in the Y direction are arranged in an array, and the third signal processing layer 20c is used for third signal processing. The circuit 21c has an array of r / (m × j) = 6400 / (4 × 2) = 800 in the X direction and s / (n × k) = 4800 / (1 × 4) = 1200 in the Y direction. In the fourth signal processing layer 20d, the fourth signal processing circuit 21d has r / (m × j) = 6400 / (4 × 2) = 800 in the X direction and s / (n) in the Y direction. × k) = 4800 / (1 × 4) = 1200 are arranged in an array.

That is, the image pickup device of the present technology includes (r / (m × j)) × (s / (n × k)) signal processing circuits 21 at 20 in one signal processing layer, and this signal. The processing layer is provided by laminating (m × n / t) layers. By operating the total (r / (m × j)) × (s / (n × k)) × (m × n / t) signal processing circuits 21 configured in this way in parallel, the signal processing circuits 21 are operated in parallel. It is possible to perform signal processing in a shorter time than the image pickup device described in Patent Document 1 which does not have a configuration.
In the third embodiment, referring to FIGS. 10 and 11, in the repeating unit including the pixel sharing structure PC and the signal processing circuit 21, m pixel sharing structure PCs are arranged in the X direction and n in the Y direction. As an example of individual arrangement, an example in which m = 4 and n = 1 and the number of connections t = 1 has been described, but m and n may be integers of 1 or more and m × n of 4 or more, respectively. For example, they may be arranged so that the values are other than m = 4 and n = 1. For example, m = 2 or more and n = 2 or more may be used.

Further, in the first signal processing circuit 21a, the second signal processing circuit 21b, the third signal processing circuit 21c, and the fourth signal processing circuit 21d, the timing of processing the image signal is set to the same timing, respectively. That is, the signal processing layer 20 including the first signal processing layer 20a to the fourth signal processing layer 20d performs signal processing on a plurality of pixels by the plurality of signal processing circuits 21 in parallel in the same time zone.

<Action / effect of the third embodiment>
The image sensor of the third embodiment can exert the following actions and effects.
(1) A four-layer signal processing layer 20 is provided.
As a result, the image signal can be processed in the signal processing circuit 21 included in each of the four layers of the signal processing layer 20 without increasing the area of the one-layer signal processing layer 20.

(2) The four-layer signal processing layer 20 is electrically connected by a metal direct coupling.
As a result, it is possible to suppress the deviation of the read time due to the signal processing layers 20 of the plurality of layers with respect to the signal output from the pixel layer 10 to the signal processing layers 20 of the plurality of layers.

(Fourth Embodiment)
<Image sensor>

As shown in FIG. 12, the image pickup device according to the fourth embodiment includes a pixel layer 10, a signal processing layer 20, and an output layer 30, and further, the pixel layer 10 includes a photodiode layer 10a and a pixel drive layer. It is configured using two stacked layers including 10b. In the following description, the description of the parts common to the first to third embodiments may be omitted.

<Pixel layer>
As shown in FIG. 12, the pixel layer 10 has a plurality of pixel circuits 11. The plurality of pixel circuits 11 are arranged in parallel when viewed from the stacking direction. In FIG. 12, the vertical signal line VSL is shown by omitting the reference numerals.
Note that FIG. 12 shows, as an example, four pixel circuits 11a to 11d among the plurality of pixel circuits 11 included in the pixel layer 10.

In the fourth embodiment, as in the first embodiment, a case where one pixel circuit 11 includes a pixel sharing structure PC for eight pixels will be described.
As shown in FIG. 12, in the image pickup device according to the fourth embodiment, the pixel layer 10 has two layers, a photodiode layer 10a and a pixel drive layer 10b arranged so as to be laminated on the photodiode layer 10a. It is configured using.
The image pickup device of the first embodiment described above as the pixel sharing structure PC for eight pixels has the configuration shown in FIG. 2, but the pixel sharing structure PC provided in the image pickup device of the fourth embodiment also has the configuration shown in FIG. It has a configuration similar to that shown in FIG.

The pixel sharing structure PC provided in the image pickup device of the fourth embodiment is formed in the photodiode layer 10a on the surface of the semiconductor substrate of the photodiode layer 10a and is in an electrically floating state in the impurity diffusion region. Two floating diffusion FDs are provided as in FIG. One floating diffusion FD is electrically connected (shared by the four photodiodes PD) to the four photodiode PDs constituting the first group via the four transfer transistors TR, and the other floating diffusion FD. Is electrically connected (shared by the four photodiodes PD) via the four photodiode PDs forming the second group and the four transfer transistors TR. Then, these two floating diffusion FDs are electrically connected so as to be equipotential by the first connection wiring JW connecting the two floating diffusion FDs. That is, the pixel sharing structure PC provided in the image pickup element of the fourth embodiment is electrically connected in the photodiode layer 10a so as to have an equal potential on the equivalent circuit as in FIG. 2, and becomes one. The floating diffusion FD is shared by eight photodiodes PD provided in the pixel sharing structure PC (shared by eight pixels provided in the pixel sharing structure PC).
On the other hand, the amplifier transistor AMP, the reset transistor RST, and the control signal line RSL for driving the reset transistor RST provided in the pixel sharing structure PC provided in the image sensor of the first embodiment shown in FIG. 2 are In the pixel sharing structure PC provided in the image pickup device of the fourth embodiment, the pixel drive layer 10b is arranged. Then, in the pixel drive layer 10b, a second connection wiring (not shown) is provided between the gate electrode of the amplifier transistor AMP to be connected to the floating diffusion FD and one end of the reset transistor RST to be connected to the floating diffusion FD. It is electrically connected via.

The image pickup device of the fourth embodiment electrically connects between a part of the pixel circuit formed in the photodiode layer 10a and a part of the pixel circuit formed in the pixel drive layer 10b. A target connection means (circuit connection means between layers or interlayer wiring, for example, a conductive plug) is provided. In the pixel sharing structure PC provided in the image pickup device of the fourth embodiment, the floating diffusion FD formed on the photodiode layer 10a and the amplifier transistor AMP and the reset transistor RST formed on the pixel drive layer 10b are described above. It is connected by using the inter-layer electrical connection means (interlayer wiring). Here, the floating diffusion FD formed on the photodiode layer 10a of the pixel sharing structure PC has a configuration in which eight pixels provided in the pixel sharing structure PC share the floating diffusion FD that is one on the equivalent circuit. It has become. Further, the gate electrode of the amplifier transistor AMP formed on the pixel drive layer 10b of the pixel sharing structure PC and one end of the reset transistor RST to be connected to the floating diffusion FD are electrically connected via the second connection wiring. Is connected. Therefore, in the pixel sharing structure PC provided in the image pickup device of the fourth embodiment, any one of the floating diffusion FD formed on the photodiode layer 10a and the first connection wiring JW, and the pixel drive layer 10b. It is only necessary to connect the amplifier transistor AMP formed in the above, the reset transistor RST, and any one of the second connection wirings by the circuit connection means between the layers described above.
By providing this configuration, a configuration that does not include this configuration (for example, a configuration in which a plurality of floating diffusion FDs provided in the pixel sharing structure PC are not electrically connected to one in the photodiode layer 10a). Alternatively, the amplifier transistor AMP provided in the pixel sharing structure PC and the reset transistor RST are not electrically connected to one in the pixel drive layer 10b), but in the pixel sharing structure PC. The number of circuit connecting means between the above-mentioned layers to be arranged in may be small. As a result, the area of the pixel sharing structure PC can be reduced, and the image sensor can be highly integrated.

Further, a circuit connecting means between the photodiode layer 10a and the pixel drive layer 10b described above (a part of the pixel circuit formed in the photodiode layer 10a and a part of the pixel circuit formed in the pixel drive layer 10b). The inter-layer electrical connection means for electrically connecting between the layers is from the metal direct coupling (Cu-Cu connection) used for the connection between the pixel layer 10 and the signal processing layer 20 in the first embodiment. Also has the feature that the area of the connecting portion is small.
This feature is brought about by the characteristics of the manufacturing method of the inter-layer electrical connection means described above. In the direct metal bonding used in the first embodiment, after the circuits have been formed on both the semiconductor substrate on which the pixel layer 10 is formed and the semiconductor substrate on which the signal processing layer 20 is formed, the metal terminals are formed on the outermost surfaces of the respective substrates. Is formed, and the two substrates having the metal terminals formed on the outermost surface are directly bonded to each other. Semiconductor substrates generally have a diameter of about 300 mm and may expand and contract. In this way, if a large and stretchable material is directly bonded, an error may occur in the bonding position in manufacturing. Therefore, it is desired that the metal terminals formed on the surface of the semiconductor substrate have a size capable of forming an electrical connection between the terminals even when such an error occurs.

On the other hand, in the fourth embodiment, the circuit connecting means between the photodiode layer 10a and the pixel drive layer 10b is formed after forming an element (photodiode PD, floating diffusion FD, transfer transistor TR) on the photodiode layer 10a. The semiconductor substrate for forming the pixel drive layer 10b is bonded in a state where the elements (amplifier transistor AMP, reset transistor RST, second connection wiring) are not formed. In this case, since the semiconductor substrate is attached in a state where the element is not formed (a state in which the circuit pattern is not formed), there is no error in the bonding position in the first place. Then, after the substrates are bonded together, the element and the circuit are formed on the semiconductor substrate for forming the pixel drive layer 10b by the element and the circuit forming method used in the usual semiconductor manufacturing method. Then, after forming at least the element, a circuit connecting means between the photodiode layer 10a and the pixel driving layer 10b is formed by an electrical connecting means (for example, a conductive plug) used in a normal semiconductor manufacturing method. Structural features (1) to (4) resulting from this manufacturing method appear in the image pickup device formed by using this manufacturing method.

Features (1). After forming the element for the photodiode layer 10a on the surface of the semiconductor substrate on which the photodiode layer 10a is formed, the semiconductor substrate for forming the pixel drive layer 10b is laminated on the surface of the semiconductor substrate, and the laminated semiconductor. An element for the pixel drive layer 10b is formed on the surface of the substrate. Therefore, the semiconductor substrate and the elements formed on the surface of the semiconductor substrate are the semiconductor substrate for the photodiode layer 10a, the element for the photodiode layer 10a, the semiconductor substrate for the pixel drive layer 10b, and the pixel drive layer. The elements for 10b are stacked in this order.
Features (2). After forming the element for the pixel drive layer 10b, the inter-layer electrical from above the element to the element formed on the surface of the semiconductor substrate of the photodiode layer 10a through the semiconductor substrate for the pixel drive layer 10b. Form connecting means (eg, conductive vias). At that time, since the inter-layer electrical connection means penetrating the semiconductor substrate for the pixel drive layer 10b insulates from the semiconductor substrate for the pixel drive layer 10b, the inter-layer electrical connection means and the pixel drive layer An insulating film is arranged between the semiconductor substrate and the semiconductor substrate for 10b.
Features (3). On the semiconductor substrate for the photodiode layer 10a on which the element is formed, the semiconductor substrate for forming the pixel drive layer 10b is bonded in a state where the element is not formed (a state in which the circuit pattern is not formed). After forming the element for the pixel drive layer 10b, the layer-to-layer electrical connection from above the element to the element formed on the surface of the semiconductor substrate of the photodiode layer 10a through the semiconductor substrate for the pixel drive layer 10b. Form means (eg, conductive plugs). Therefore, the inter-layer electrical connection means has a substantially cylindrical or substantially truncated cone shape from above the pixel drive layer 10b to the element formed on the surface of the semiconductor substrate of the photodiode layer 10a. Only the connecting means (for example, a conductive plug) is formed. Therefore, the bonding surface between the photodiode layer 10a and the pixel drive layer 10b is not provided with a terminal portion larger than the inter-layer electrical connection means (for example, a conductive plug) of a substantially cylindrical or substantially conical cone.
Features (4). After forming the element for the photodiode layer 10a, the semiconductor substrate for the pixel drive layer 10b is bonded, and the element and the wiring formed on the photodiode layer 10a are formed in order to form the element for the pixel drive layer 10b. Is subjected to the heat treatment required for forming the element for the pixel drive layer 10b. Therefore, the elements and wiring provided in the photodiode layer 10a (for example, the control signal line DSL connected to the transfer transistor) have higher heat resistance than at least a part of the material used as wiring in the pixel drive layer 10b. It is formed using a material (having a high melting point) (for example, tungsten, titanium, titanium nitride, polysilicon, etc.).

Further, the pixel drive layer 10b is electrically connected to the signal processing layer 20 by a metal direct coupling.
Further, the pixel drive layer 10b includes a first pixel drive circuit 41a, a second pixel drive circuit 41b, a third pixel drive circuit 41c, and a fourth pixel drive circuit 41d.

The pixel drive circuits 41a to 41d formed on the pixel drive layer 10b include an amplification transistor AMP and a reset transistor RST that form a pixel sharing structure PC. These transistors and the floating diffusion FD of the pixel sharing structure PC formed on the photodiode layer 10a are connected via the above-mentioned inter-layer electrical connection means. This connection is formed one by one for each pixel sharing structure PC.
Further, the pixel drive circuit 41 includes a drive circuit for driving each pixel provided in the pixel sharing structure PC. A specific example of this circuit will be described later.

Further, the pixel drive circuit 41 is connected to the signal processing circuit 21 via the control signal line 22. The control signal line 22 includes the metal direct coupling (Cu-Cu connection) described above. This connection is formed one by one for each of the pixel sharing structure PCs.
Further, the pixel drive circuit 41 is connected to the transfer transistor TR included in the pixel sharing structure PC via the interlayer wiring 42 (electrical connection means between layers).

With the above configuration, the following operations (1) to (4) are possible.
Operation (1). The pixel drive circuit 41 amplifies the electric signal of the shooting result by each pixel provided in the pixel sharing structure PC, and outputs the electric signal to the signal processing circuit 21.
Operation (2). The signal processing circuit 21 performs some kind of signal processing on the electric signal of the photographing result and outputs it to the output layer 30, or outputs the electric signal to the output layer 30 without performing signal processing.
Operation (3). The signal processing circuit 21 controls each pixel provided in the pixel sharing structure PC for the next shooting (for example, shooting of the next frame) based on the evaluation result of evaluating the magnitude of the electric signal of the shooting result. Create a signal to do. The signal processing circuit 21 outputs the created control signal to the pixel drive circuit 41.
Operation (4). The pixel drive circuit 41 uses the control signal input from the signal processing circuit 21 to create a drive signal for driving each pixel provided in the pixel sharing structure PCa. The pixel drive circuit 41 outputs the created drive signal to each pixel provided in the pixel sharing structure PC formed on the photodiode layer 10a. The pixel drive circuit 41 formed on the pixel drive layer 10b and each pixel formed on the photodiode layer 10a are connected via the above-described inter-layer electrical connection means. For example, when the drive signal is a signal that controls the shooting time of a pixel, the pixel drive circuit 41 formed in the pixel drive layer 10b and each transfer transistor TR provided in each pixel formed in the photodiode layer 10a are connected. As such, an inter-layer electrical connection means is formed.

The number of the inter-layer electrical connection means arranged is determined by the configuration of the pixel sharing structure PC and the signal processing circuit 21.
As an example, consider the case of j = 2, k = 4, m = 2, n = 2. In this case, one signal processing circuit 21 is arranged on four pixel sharing structure PCs arranged in m × n = 2 × 2, in other words, (m × j) × (n × k) = 4 × 8. It extends over the 32 pixels arranged in.

Here, as a first example in the case of j = 2, k = 4, m = 2, n = 2, as shown in FIG. 12, a pixel sharing structure PC connected to one signal processing circuit 21 Consider the case where the number t = 1. As described above, since the number of layers of the signal processing layer 20 included in the image pickup element of the present technology is m × n / t, when m = 2, n = 2, t = 1, the image pickup element is a signal processing layer. 20 is provided by stacking four layers. In this case, one signal processing circuit 21 and one pixel drive circuit 41 connected to one signal processing circuit 21 are arranged in (m × j) × (n × k) = 4 × 8. It creates a control signal that drives the transfer transistor TR provided in 1 / t of one pixel, that is, eight pixels. In the fourth embodiment, it is desirable that the j × k pixels included in one pixel sharing structure PC are driven by the same signal processing circuit 21 and the same pixel drive circuit 41. Therefore, when j = 2, k = 4, m = 2, n = 2, t = 1, one signal processing circuit 21 and one pixel drive circuit 41 connected to the signal processing circuit 21 drive eight pixels. Is preferably j × k = 2 × 4 pixels included in one pixel sharing structure PC. When j = 2, k = 4, m = 2, n = 2, and t = 1, each of the four-layer signal processing circuits 21 provided in the four-layer signal processing layer 20 is (m × j) ×. (N × k) = Extending over 32 pixels arranged in 4 × 8, and each of the four-layer signal processing circuits 21 is arranged in j × k = 2 × 4. Drives 8 pixels. Each of the four-layer signal processing circuits 21a, 21b, 21c, and 21d is independently used for the next shooting based on the imaging results of each pixel electrically connected to the respective signal processing circuits 21. It is possible to create a signal that controls the shooting operation of pixels. As a result, each of the four-layer signal processing circuits 21a, 21b, 21c, and 21d can independently control the imaging conditions of each pixel electrically connected to the respective signal processing circuits 21. .. The imaging conditions of each pixel electrically connected to one signal processing circuit 21 may be controlled independently for each pixel, or in a plurality of pixels electrically connected to one signal processing circuit 21. It may be the same.

In FIG. 12, the connection between the signal processing circuit 21a and the pixel drive circuit 41a is configured by using a metal direct coupling (Cu—Cu connection) having a large area of the connection portion. The connection between the signal processing circuit 21b and the pixel drive circuit 41b has a large area of the connecting portion formed on the wiring penetrating the signal processing layer 20a and the bonding surface between the signal processing layer 20a and the pixel drive layer 10b. It is configured using metal direct bonding (Cu-Cu connection). The connection between the signal processing circuit 21c and the pixel drive circuit 41c is the area of the connection portion formed on the wiring penetrating the signal processing layers 20b and 20a and the bonding surface of the signal processing layer 20a and the pixel drive layer 10b. It is constructed by using a large metal direct coupling (Cu-Cu connection). The connection between the signal processing circuit 21d and the pixel drive circuit 41d is a connection portion formed on a wiring penetrating the signal processing layers 20c, 20b and 20a and a bonding surface between the signal processing layer 20a and the pixel drive layer 10b. It is configured by using a metal direct coupling (Cu-Cu connection) with a large area. On the other hand, in FIG. 12, the connection between the pixel drive circuit 41 provided in the pixel drive layer 10b and the transfer transistor TR included in each pixel provided in the photodiode layer 10a has a metal direct coupling (Cu—Cu) in the area of the connection portion. It is constructed using inter-layer electrical connection means that are smaller than (connection). In FIG. 12, eight connections between the pixel drive circuit 41a and the eight transfer transistors TR provided in the eight pixels of the pixel sharing structure PCa, and the pixel drive circuit 41b and the pixel sharing structure PCb have. Eight connections between the eight transfer transistors TR provided in the eight pixels, and between the pixel drive circuit 41c and the eight transfer transistors TR provided in the eight pixels of the pixel sharing structure PCc. Eight connections and eight connections between the pixel drive circuit 41d and the eight transfer transistors TR provided in the eight pixels of the pixel sharing structure PCd, that is, a total of 32 connections, are layers. It is configured using inter-electrical connection means.
Here, the pixel drive circuit 41 and the inter-layer electrical connection means are not provided, and the four signal processing circuits 21 generate control signals for a total of 32 pixels, and the control signals are directly bonded to 32 metals (Cu). Let us consider a form of connecting to the transfer transistor TR via (-Cu connection) as a comparative example. A fourth embodiment includes a pixel drive circuit 41 and inter-layer electrical connection means between the signal processing circuit 21 and the transfer transistor TR. Therefore, in the fourth embodiment, for example, in the signal processing circuit 21, the control signals for 32 pixels are multiplexed (serialized) and created, and one space between the signal processing circuit 21 and the pixel drive circuit 41 is provided. 32 drives in a drive circuit (for example, a circuit for deserializing the multiplexed signal) provided in the pixel drive circuit 41, which is connected via a metal direct junction (Cu-Cu connection) of the above. The 32 separated drive signals are separated into signals, and the 32 separated drive signals are connected by using 32 inter-layer electrical connection means having a small connection area, which connects between the pixel drive circuit 41 and the transfer transistor TR. Is possible. As a result, the area required for the connection portion can be reduced as compared with the comparative example, and the image sensor can be highly integrated.

Next, as a second example in the case of j = 2, k = 4, m = 2, n = 2, the number t of the pixel sharing structure PC connected to one signal processing circuit 21 is other than 1. Consider the case. Here, for example, consider the case of t = 2. As described above, the number of layers of the signal processing layer 20 included in the image pickup element of the present technology is m × n / t. Therefore, when m = 2, n = 2, t = 2, the image pickup element is the signal processing layer 20. Is provided by stacking two layers. In this case, one signal processing circuit 21 and one pixel drive circuit 41 connected to the signal processing circuit 21 are 1 / of 32 pixels arranged in (m × j) × (n × k) = 4 × 8. t, that is, a control signal for driving the transfer transistor TR provided in 16 pixels is created. Therefore, one signal processing circuit 21 and one pixel drive circuit 41 connected to one signal processing circuit 21 are 16 pixels provided in the two pixel sharing structure PCs arranged side by side in the X direction. , Consider the case of driving. As shown in FIG. 2, the control signal line DSL for driving the transfer transistor TR extends in the X direction of the pixel array.
Therefore, when a plurality (r) of pixels driven at the same exposure timing are arranged in the X direction, the r transfer transistors TR provided in these r pixels are arranged in one control signal line DSL. It is possible to drive with. Therefore, the number of inter-layer electrical connection means for connecting the first pixel drive circuit 41 and the transfer transistor TR can be one for every r pixels in the X direction. When one signal processing circuit 21 and one pixel drive circuit 41 connected to the signal processing circuit 21 drive 16 pixels provided in two pixel sharing structure PCs arranged side by side in the X direction, r = 2. Become.

That is, in the 16 pixels provided in the two pixel sharing structure PCs arranged side by side in the X direction, the number of inter-layer electrical connection means for connecting the first pixel drive circuit 41a and the transfer transistor TR is X. The number of pixels may be one in every two pixels. On the other hand, as shown in FIG. 2, one control signal line DSL for driving the transfer transistor TR is required for each pixel in the Y direction. Therefore, in the 16 pixels provided in the two pixel sharing structure PCs arranged side by side in the X direction, the number of inter-layer electrical connection means for connecting the pixel drive circuit 41 and the transfer transistor TR is in the Y direction. Is required one by one for each pixel.

Therefore, in the 16 pixels provided in the two pixel sharing structure PCs arranged side by side in the X direction, the number of inter-layer electrical connection means for connecting the pixel drive circuit 41 and the transfer transistor TR is the X direction. 1 piece x 8 pieces in the Y direction = 8 pieces are required. When j = 2, k = 4, m = 2, n = 2, t = 2, the signal processing circuit 21 has 32 signals arranged in (m × j) × (n × k) = 4 × 8. The image sensor extends over the pixels and includes two layers of the signal processing circuit 21. Each of the two-layer signal processing circuits 21 includes the above-mentioned eight inter-layer electrical connection means for driving 16 pixels provided in the two pixel sharing structure PCs arranged side by side in the X direction. .. The entire 32 pixels in which the signal processing circuit extends includes 8 × 2 = 16 inter-layer electrical connection means.

In the fourth embodiment, as in the first to third embodiments, the repeating unit is configured by using the pixel layer and the signal processing layer, and the repeating unit is arranged in an array in the X direction and the Y direction. Configure a pixel array.
For example, in the third embodiment, as shown in FIG. 10, the pixel sharing structures PCa to PCd and the signal processing circuits 21a to 21d are set as repeating units, and the repeating unit is X as shown in FIG. A pixel array was constructed by arranging them in an array in the direction and the Y direction.
Further, also in the fourth embodiment, the pixel sharing structures PCa to PCd, the pixel drive circuits 41a to 41d, and the signal processing circuits 21a to 21d shown in FIG. 12 are used as repeating units, and the repeating units are shown in FIG. As shown, it is possible to form a pixel array by arranging them in an array in the X direction and the Y direction.

In the pixel array provided in the image sensor of the present technology, the above-mentioned unit units are repeatedly arranged in an array of p in the X direction and q in the Y direction. As an example, similar to the form shown in FIG. 11 (j = 2, k = 4, m = 4, n = 1), it is a pixel array in which r pixels are arranged in the X direction and s pixels are arranged in the Y direction, and r = 6400. When configuring an imaging device having a pixel array of 30 million pixels with s = 4800, the unit units are r / (m × j) = 6400 / (4 × 2) = 800 in the X direction and 800 in the Y direction. s / (n × k) = 4800 / (1 × 4) = 1200 are arranged in an array. In this case, on the first signal processing layer 20a, the first signal processing circuits 21a have r / (m × j) = 6400 / (4 × 2) = 800 in the X direction and s / (n ×) in the Y direction. k) = 4800 / (1 × 4) = 1200 are arranged in an array, and on the second signal processing layer 20b, a second signal processing circuit 21b is arranged in the X direction at r / (m × j) = 6400 /. (4 × 2) = 800 pieces, s / (n × k) = 4800 / (1 × 4) = 1200 pieces in the Y direction are arranged in an array, and the third signal processing layer 20c is used for third signal processing. The circuit 21c has an array of r / (m × j) = 6400 / (4 × 2) = 800 in the X direction and s / (n × k) = 4800 / (1 × 4) = 1200 in the Y direction. In the fourth signal processing layer 20d, the fourth signal processing circuit 21d has r / (m × j) = 6400 / (4 × 2) = 800 in the X direction and s / (n) in the Y direction. × k) = 4800 / (1 × 4) = 1200 are arranged in an array. That is, the image pickup device of the present technology includes (r / (m × j)) × (s / (n × k)) signal processing circuits 21 in one signal processing layer at 20, and this signal processing. The layers are provided by stacking (m × n / t) layers. By operating the total (r / (m × j)) × (s / (n × k)) × (m × n / t) signal processing circuits 21 configured in this way in parallel, the signal processing circuits 21 are operated in parallel. It is possible to perform signal processing in a shorter time than the image pickup device described in Patent Document 1 which does not have a configuration.

As an example in which m pixel sharing structure PCs are arranged in the X direction and n in the Y direction, an example in which m = 4 and n = 1 and the number of connections t = 1 has been described. May be arranged so as to have a value other than m = 4 and n = 1 as long as each is an integer of 1 or more and m × n is 4 or more. For example, m = 2 or more and n = 2 or more may be used.
Further, in the second embodiment, as shown in FIG. 7, the pixel sharing structures PCa to PCd and the signal processing circuits 21a to 21b are set as repeating units, and the repeating unit is X as shown in FIG. A pixel array was constructed by arranging them in an array in the direction and the Y direction.

Then, also in the fourth embodiment, as shown in FIG. 7, in the repeating unit described above, the configuration of the pixel layer 10 shown in FIG. 12 is incorporated into the configuration of the pixel layer 10, and the repeating unit constituting the pixel array is used. It is possible to do. As shown in FIG. 8, the repeating units can be arranged in an array in the X direction and the Y direction to form a pixel array.
In the pixel array provided in the image sensor of the present technology, the above-mentioned unit units are repeatedly arranged in an array of p in the X direction and q in the Y direction. As an example, a pixel array in which r pixels in the X direction and s pixels in the Y direction are arranged in the same manner as in the form shown in FIG. 8 (j = 2, k = 4, m = 4, n = 1). When configuring an imaging device having a pixel array of 30 million pixels such that = 6400 and s = 4800, the unit units are r / (m × j) = 6400 / (4 × 2) = 800 in the X direction, Y. They are arranged in an array of s / (n × k) = 4800 / (1 × 4) = 1200 in the direction. In this case, on the first signal processing layer 20a, the first signal processing circuits 21a have r / (m × j) = 6400 / (4 × 2) = 800 in the X direction and s / (n ×) in the Y direction. k) = 4800 / (1 × 4) = 1200 are arranged in an array, and on the second signal processing layer 20b, a second signal processing circuit 21b is arranged in the X direction at r / (m × j) = 6400 /. It is arranged in an array of (4 × 2) = 800 pieces and s / (n × k) = 4800 / (1 × 4) = 1200 pieces in the Y direction. That is, the image sensor of the present technology includes (r / (m × j)) × (s / (n × k)) signal processing circuits 21 at 20 in one signal processing layer, and further signals. The processing layer is provided by laminating (m × n / t) layers. By operating the total (r / (m × j)) × (s / (n × k)) × (m × n / t) signal processing circuits 21 configured in this way in parallel, the signal processing circuits 21 are operated in parallel. It is possible to perform signal processing in a shorter time than the image pickup device described in Patent Document 1 which does not have a configuration.

As an example in which m pixel sharing structure PCs are arranged in the X direction and n in the Y direction, an example in which m = 4 and n = 1 and the number of connections t = 2 has been described. n may be arranged so as to have a value other than m = 4 and n = 1 as long as each is an integer of 1 or more and m × n is an integer of 4 or more.

<Action / effect of the fourth embodiment>
The image sensor of the fourth embodiment can exert the following actions and effects.
(1) The pixel layer 10 includes a photodiode layer 10a having a pixel sharing structure PC, and a pixel drive layer 10b having a pixel drive circuit 41 that outputs a signal according to the processing result in the signal processing circuit 21 to the pixels. including. In addition to this, the pixel drive circuit 41 is electrically connected to the transfer transistor TR.
This makes it possible to electrically connect the pixel drive circuit 41 and the transfer transistor TR with an electrode having a smaller area than the direct metal coupling. Therefore, it is possible to accommodate the connection electrode of the control signal line connected to each pixel and the connection electrode of the signal line output from the pixel sharing structure PC inside the pixel sharing structure PC.

This is an action / effect that solves the following problems.
In a conventional image pickup element, it is common to use a metal direct coupling in which a circuit is created earlier for connecting the pixel layer and the signal processing layer, but in this configuration, the pixel drive circuit drives each pixel. Assuming that the signal lines are connected and one output signal line is connected to the signal processing circuit from the pixel sharing structure, when all the connections are formed by direct metal coupling, the metal is inside the pixel sharing structure. It is difficult to accommodate a directly bonded electrode. Further, in order to accommodate all the electrodes directly bonded to the metal inside the pixel sharing structure, it is necessary to increase the area of the pixel sharing structure, so that it is difficult to form a highly integrated imaging element. there were.
On the other hand, in the case of the image sensor of the fourth embodiment, as described above, the control signal line connecting electrodes connected to each pixel and the pixel sharing structure PC output from the inside of the pixel sharing structure PC. It becomes possible to accommodate the connection electrode of the signal line. This makes it possible to form a highly integrated image sensor.

(2) The pixel drive layer 10b is electrically connected to the signal processing layer 20 by a metal direct coupling.
As a result, it is possible to suppress a deviation in the read time due to the pixel drive layer 10b with respect to the signal output from the signal processing layer 20 to the pixel drive layer 10b.

(3) The interlayer wiring 42 is formed by using a material having higher heat resistance than at least a part of the material used as wiring in the pixel layer 10.
As a result, the interlayer wiring 42 is appropriate for the configuration in which the connection electrode of the control signal line connected to each pixel and the connection electrode of the signal line output from the pixel sharing structure PC are housed inside the pixel sharing structure PC. It is possible to have a different configuration.

(4) Of the control signal lines that supply drive signals to the reset transistor, at least a portion formed in the pixel layer 10 is a material having higher heat resistance than at least a part of the material used as wiring in the pixel layer 10. Is formed using.
As a result, the reset transistor has a drive signal for a configuration in which the connection electrode of the control signal line connected to each pixel and the connection electrode of the signal line output from the pixel sharing structure PC are housed inside the pixel sharing structure PC. The control signal line for supplying the above can be configured appropriately.

(Other embodiments)
As described above, embodiments of the present technology have been described, but the statements and drawings that form part of this disclosure should not be understood to limit the present technology. Various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art from this disclosure.
In addition, it goes without saying that the present technology includes various embodiments not described here, such as a configuration in which each configuration described in the above embodiment is arbitrarily applied. Therefore, the technical scope of the present technology is defined only by the matters specifying the invention relating to the reasonable claims from the above description.
It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

The present technology can have the following configurations.
(1)
A pixel layer having a pixel sharing structure including a plurality of pixels that photoelectrically convert incident light and output an image signal, and
A signal processing layer that is laminated on the pixel layer and has a signal processing circuit that processes the image signal.
The pixel layer has a plurality of the pixel sharing structures arranged in an array.
The signal processing layer has a plurality of the signal processing circuits arranged in an array.
One pixel sharing structure is connected to one signal processing circuit so that the image signal can be input.
The plurality of signal processing circuits are image pickup devices that process the input image signals in parallel with each other.
(2)
The signal processing layer having a plurality of layers stacked on each other is provided.
The image pickup device according to (1), wherein the signal processing circuit included in each of the plurality of signal processing layers processes the input image signals in parallel with each other.
(3)
The image pickup device according to (2) above, which includes two layers of the signal processing layer.
(4)
The image pickup device according to (2) above, which includes four layers of the signal processing layer.
(5)
The image pickup device according to any one of (2) to (4) above, wherein the plurality of signal processing layers are electrically connected by a metal direct coupling.
(6)
At least one pixel sharing structure is additionally connected to one signal processing circuit so that the image signal can be input, and a plurality of the pixel sharing structures are connected.
The one signal processing circuit includes an image signal output by a part of the connected plurality of pixel sharing structures and an image signal output by at least one of the remaining connected pixel sharing structures. The image pickup device according to any one of (1) to (5) above, wherein the image pickup device is processed in a time-divided manner.
(7)
The signal processing layer having a plurality of layers stacked on each other is provided.
The image pickup device according to (6), wherein the signal processing circuit included in each of the plurality of signal processing layers processes the input image signals in parallel with each other.
(8)
The image pickup device according to (7) above, which includes two layers of the signal processing layer.
(9)
The image pickup device according to (7) or (8) above, wherein the plurality of signal processing layers are electrically connected by a metal direct coupling.
(10)
The area of the signal processing circuit seen from the direction in which the pixel layer and the signal processing layer are laminated is larger than the area of the pixel shared structure seen from the laminated direction. The image pickup device described in any of the above.
(11)
The area of the signal processing circuit seen from the stacked direction is any one of the above (1) to (10), which is an integral multiple of 2 or more with respect to the area of the pixel shared structure seen from the stacked direction. The image pickup device described in 1.
(12)
The image pickup device according to any one of (1) to (11) above, wherein the pixel sharing structure includes the eight pixels.
(13)
The image pickup device according to any one of (1) to (12) above, wherein the signal processing layer is electrically connected to the pixel layer by a metal direct coupling.
(14)
An output layer that is laminated on the signal processing layer and that reads out an image signal processed by the signal processing layer is further provided.
The image pickup device according to any one of (1) to (13), wherein the output layer is electrically connected to the signal processing layer by direct metal bonding.
(15)
The pixel layer includes a photodiode layer having the pixel sharing structure and a pixel drive layer having a pixel drive circuit that outputs a signal corresponding to the result of the processing in the signal processing circuit to the pixels.
The pixel sharing structure includes a photodiode that photoelectrically converts incident light and generates and stores an electric charge according to the amount of light of the photoelectric conversion, and a transfer transistor that transfers a signal charge accumulated in the photodiode. With
The image pickup device according to any one of (1) to (14), wherein the pixel drive circuit is electrically connected to the transfer transistor.
(16)
The image pickup device according to (15), wherein the pixel drive layer is electrically connected to the signal processing layer by direct metal bonding.
(17)
The interlayer wiring connecting the pixel drive circuit and the transfer transistor is formed by using a material having higher heat resistance than at least a part of the material used as wiring in the pixel layer (15) or the above. The image pickup device according to (16).
(18)
The pixel sharing structure includes a floating diffusion that accumulates the electric charge transferred from the photodiode via the transfer transistor and converts it into a voltage, and the electric charge accumulated in the floating diffusion according to a supplied drive signal. Further equipped with a reset transistor that turns on or off the discharge of
Of the control signal lines that supply the drive signal to the reset transistor, at least a portion formed in the pixel layer uses a material having higher heat resistance than at least a part of the material used as wiring in the pixel layer. The image pickup device according to any one of (15) to (17) above.

10 ... pixel layer, 10a ... photodiode layer, 10b ... pixel drive layer, 10t ... metal terminal, 11 (11a to 11d) ... pixel circuit, 20 (20a to 20d) ... signal processing layer, 20t ... metal terminal, 20at ... Metal terminal, 20 bt ... Metal terminal, 21 (21a to 21d) ... Signal processing circuit, 22 (22a to 22d) ... Feedback signal line, 30 ... Output layer, 41 (41a to 41d) ... Pixel drive circuit, 42 (42a to) 42d) ... interlayer wiring, PD ... photodiode, TR ... transfer transistor, FD ... floating diffusion, RST ... reset transistor, AMP ... amplification transistor, SEL ... selective transistor, PC (PCa to PCd) ... pixel sharing structure, MR ... Microlens, VDD ... Power supply wiring, VSL (VSLa to VSLd, VSLau, VSLad, VSLbu, VSLbd) ... Vertical signal line, DSL ... Control signal line, RSL ... Control signal line

Claims (18)

A pixel layer having a pixel sharing structure including a plurality of pixels that photoelectrically convert incident light and output an image signal, and
A signal processing layer that is laminated on the pixel layer and has a signal processing circuit that processes the image signal.
The pixel layer has a plurality of the pixel sharing structures arranged in an array.
The signal processing layer has a plurality of the signal processing circuits arranged in an array.
One pixel sharing structure is connected to one signal processing circuit so that the image signal can be input.
The plurality of signal processing circuits are image pickup devices that process the input image signals in parallel with each other. The signal processing layer having a plurality of layers stacked on each other is provided.
The image pickup device according to claim 1, wherein the signal processing circuit included in each of the plurality of signal processing layers processes the input image signals in parallel with each other. The image pickup device according to claim 2, further comprising two layers of the signal processing layer. The image pickup device according to claim 2, further comprising four layers of the signal processing layer. The image pickup device according to claim 2, wherein the plurality of signal processing layers are electrically connected by a metal direct coupling. At least one pixel sharing structure is additionally connected to one signal processing circuit so that the image signal can be input, and a plurality of the pixel sharing structures are connected.
The signal processing circuit includes an image signal output by a part of the connected plurality of pixel sharing structures and an image signal output by at least one of the connected plurality of pixel sharing structures. The image pickup device according to claim 1, wherein the image pickup device is processed by time division. The signal processing layer having a plurality of layers stacked on each other is provided.
The image pickup device according to claim 6, wherein the signal processing circuit included in each of the plurality of signal processing layers processes the input image signals in parallel with each other. The image pickup device according to claim 7, further comprising two layers of the signal processing layer. The image pickup device according to claim 7, wherein the plurality of signal processing layers are electrically connected by a metal direct coupling. The imaging device according to claim 1, wherein the area of the signal processing circuit seen from the direction in which the pixel layer and the signal processing layer are laminated is larger than the area of the pixel shared structure seen from the laminated direction. The image pickup device according to claim 10, wherein the area of the signal processing circuit seen from the stacked direction is an integral multiple of 2 or more with respect to the area of the pixel shared structure seen from the stacked direction. The image pickup device according to claim 1, wherein the pixel sharing structure includes the pixel of 8. The image pickup device according to claim 1, wherein the signal processing layer is electrically connected to the pixel layer by direct metal bonding. An output layer that is laminated on the signal processing layer and that reads out an image signal processed by the signal processing layer is further provided.
The image pickup device according to claim 1, wherein the output layer is electrically connected to the signal processing layer by direct metal bonding. The pixel layer includes a photodiode layer having the pixel sharing structure and a pixel drive layer having a pixel drive circuit that outputs a signal corresponding to the result of the processing in the signal processing circuit to the pixels.
The pixel sharing structure includes a photodiode that photoelectrically converts incident light and generates and stores an electric charge according to the amount of light of the photoelectric conversion, and a transfer transistor that transfers a signal charge accumulated in the photodiode. With
The image pickup device according to claim 1, wherein the pixel drive circuit is electrically connected to the transfer transistor. The image pickup device according to claim 15, wherein the pixel drive layer is electrically connected to the signal processing layer by direct metal bonding. The fifteenth aspect of claim 15, wherein the interlayer wiring connecting the pixel drive circuit and the transfer transistor is formed by using a material having higher heat resistance than at least a part of the material used as the wiring in the pixel layer. Image sensor. The pixel sharing structure includes a floating diffusion that accumulates the electric charge transferred from the photodiode via the transfer transistor and converts it into a voltage, and the electric charge accumulated in the floating diffusion according to a supplied drive signal. Further equipped with a reset transistor that turns on or off the discharge of
Of the control signal lines that supply the drive signal to the reset transistor, at least a portion formed in the pixel layer uses a material having higher heat resistance than at least a part of the material used as wiring in the pixel layer. The image pickup device according to claim 15, which is formed of the above.

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