JP2021131477A - Display device and control method for the same - Google Patents

Abstract

To provide a display device including fewer pixel circuits without increasing the scale of each pixel circuit, and a control method for the same.SOLUTION: A display device 1 includes a plurality of light-emitting elements D1a, D1b, and D1c, a pixel circuit 15_1 provided commonly to the light-emitting elements D1a, D1b, and D1c and driving the light-emitting elements D1a, D1b, and D1c, and a voltage control circuit 14 that is provided between the light-emitting elements D1a, D1b, and D1c and a ground voltage source GND, and causes any one of the light-emitting elements D1a, D1b, and D1c to emit light selectively by supplying ground voltage from the ground voltage source GND selectively to any one of the light-emitting elements D1a, D1b, and D1c.SELECTED DRAWING: Figure 1

Description

The present invention relates to a display device and a control method thereof, for example, a display device suitable for reducing the number of pixel circuits without increasing the scale of each pixel circuit, and a control method thereof.

In self-luminous and active matrix type display devices such as organic EL (Electro Luminescence) displays and LED (Light Emitting Diode) displays, the pixel circuit (drive of the light emitting element) that drives the light emitting element is driven by the high integration of the light emitting element. The layout of the circuit) is becoming difficult.

A solution to such a problem is disclosed in, for example, Patent Document 1. Patent Document 1 discloses a configuration including a plurality of light emitting diodes (light emitting elements) and a microcontroller (pixel circuit) for switching and driving the plurality of light emitting diodes. As a result, the number of pixel circuits for the light emitting element is reduced, which facilitates the layout of the pixel circuits.

JP-A-2017-227878

However, in the configuration of Patent Document 1, since it is necessary to provide a switch for switching the light emitting element to be light-emitting between each pixel circuit and the plurality of light emitting elements driven by each pixel circuit, each pixel. There was a problem that the scale of the circuit would increase. As a result, for example, there is still a problem that the layout of the pixel circuit becomes difficult.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device capable of reducing the number of pixel circuits and a control method thereof without increasing the scale of each pixel circuit. do.

The display device according to one aspect of the present invention is a first pixel circuit that is commonly provided for a plurality of first light emitting elements and the plurality of first light emitting elements and drives each of the plurality of first light emitting elements. By being provided between the plurality of first light emitting elements and the reference power source and selectively supplying the reference voltage from the reference power source to any one of the plurality of first light emitting elements. A voltage control circuit for selectively emitting light from any of the first light emitting elements of the above. As a result, it is not necessary to provide a switch for switching the light emitting element to be light-emitting in each pixel circuit, so that the number of pixel circuits can be reduced without increasing the scale of each pixel circuit. As a result, for example, even when the light emitting elements are highly integrated, the layout of the pixel circuit becomes easy.

A method for controlling a display device according to one aspect of the present invention is a method that is commonly provided for a plurality of first light emitting elements and the plurality of first light emitting elements, and drives each of the plurality of first light emitting elements. It is a control method of a display device including a one-pixel circuit and a voltage control circuit provided between the plurality of first light emitting elements and a reference power source, and the plurality of first light emitting elements are provided by the voltage control circuit. By selectively supplying the reference voltage from the reference power source to any one of the light emitting elements, any one of the plurality of first light emitting elements is selectively emitted. As a result, it is not necessary to provide a switch for switching the light emitting element to be light-emitting in each pixel circuit, so that the number of pixel circuits can be reduced without increasing the scale of each pixel circuit. As a result, for example, even when the light emitting elements are highly integrated, the layout of the pixel circuit becomes easy.

INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a display device capable of reducing the number of pixel circuits and a control method thereof without increasing the scale of each pixel circuit.

It is a figure which shows the configuration example of the display device which concerns on Embodiment 1. FIG. It is a figure which shows the 1st configuration example of the pixel circuit provided in the display device shown in FIG. It is a figure which shows the 2nd structural example of the pixel circuit provided in the display device shown in FIG. It is a timing chart which shows the operation of the display device shown in FIG. It is a figure which shows the 1st modification of the display device shown in FIG. It is a timing chart which shows the operation of the display device shown in FIG. It is a figure which shows the 2nd modification of the display device shown in FIG. It is a timing chart which shows the operation of the display device shown in FIG. 7. It is a figure which shows the configuration example of the display device which concerns on Embodiment 2. FIG. It is a timing chart which shows the operation of the display device shown in FIG. It is a figure which shows the 1st modification of the display device shown in FIG. It is a timing chart which shows the operation of the display device shown in FIG. It is a figure which shows the 2nd modification of the display device shown in FIG. It is a timing chart which shows the operation of the display device shown in FIG. It is a figure which shows the configuration example of the display device which concerns on Embodiment 3. FIG. It is a timing chart which shows the operation of the display device shown in FIG. It is a figure which shows the configuration example of the display device which concerns on Embodiment 4. FIG. It is a timing chart which shows the operation of the display device shown in FIG. It is a figure which shows the configuration example of the display device which concerns on Embodiment 4. FIG. It is a timing chart which shows the operation of the display device shown in FIG.

<Embodiment 1>
FIG. 1 is a diagram showing a configuration example of the display device 1 according to the first embodiment. The display device 1 is a self-luminous and active matrix type display device such as an organic EL display or an LED display.

Specifically, the display device 1 includes at least a panel 11, a data driver 12, a gate driver 13, and a voltage control circuit 14.

A plurality of light emitting element groups 16 are regularly arranged on the panel 11. Further, on the panel 11, a pixel circuit 15 for driving each of the plurality of light emitting element groups 16 is arranged. In the example of FIG. 1, the light emitting element groups 16_1 to 16_p (p is an integer of 1 or more) are shown as a part of the plurality of light emitting element groups 16. Further, in the example of FIG. 1, pixel circuits 15_1 to 15_p for driving each of the light emitting element groups 16_1 to 16_p are shown as a part of the plurality of pixel circuits 15.

Each light emitting element group 16_1 to 16_p includes a plurality of light emitting elements D. Each light emitting element D is a self-luminous element that emits light when a voltage is applied, and is, for example, an organic EL or a light emitting diode. In this embodiment, a case where each light emitting element D is a light emitting diode will be described as an example.

In the example of FIG. 1, the light emitting element group 16_1 has a red (R) light emitting element D1a, a green (G) light emitting element D1b, and a blue (B) as a plurality of light emitting elements D (plural first light emitting elements). ) Is provided with the light emitting element D1c. Further, in the example of FIG. 1, in the light emitting element group 16_2, as a plurality of light emitting elements D (plurality of second light emitting elements), a red (R) light emitting element D2a, a green (G) light emitting element D2b, and blue The light emitting element D2c of (B) is provided. Similarly, in the example of FIG. 1, the light emitting element group 16_p is a red (R) light emitting element Dpa, a green (G) light emitting element Dpb, and a blue (B) light emitting element as a plurality of light emitting elements D. It has a Dpc.

The voltage control circuit 14 is provided between the light emitting element groups 16_1 to 16_p and the ground voltage source GND which is a reference power source. In the present embodiment, a case where the voltage control circuit 14 is provided in common for the light emitting element groups 16_1 to 16_p will be described as an example.

More specifically, in the light emitting elements D1a, D1b, and D1c constituting the light emitting element group 16_1, the respective anodes are connected to the pixel circuit 15_1 via the node N_1, and the respective cathodes are the nodes Na, Nb, Nc. It is connected to the voltage control circuit 14 via. Further, in the light emitting elements D2a, D2b, and D2c constituting the light emitting element group 16_2, the respective anodes are connected to the pixel circuit 15_2 via the node N_2, and the respective cathodes have a voltage via the nodes Na, Nb, and Nc. It is connected to the control circuit 14. Similarly, in the light emitting elements Dpa, Dpb, and Dpc constituting the light emitting element group 16_p, the respective anodes are connected to the pixel circuit 15_p via the node N_p, and the respective cathodes are connected via the nodes Na, Nb, and Nc. Is connected to the voltage control circuit 14.

The gate driver 13 outputs a pulse signal to a row scanning line provided corresponding to the pixel circuit 15 based on, for example, an instruction from a control circuit (not shown). The data driver 12 outputs the video signal for the pixel circuit 15 to the data line provided corresponding to the pixel circuit 15 to which the video signal is written.

In the example of FIG. 1, the gate driver 13 sequentially outputs pulse signals (hereinafter, referred to as gate control signals G_1 to G_p) to each of the row scanning lines G_1 to G_p provided corresponding to the pixel circuits 15_1 to 15_p. .. Further, the data driver 12 sequentially outputs a video signal for the pixel circuits 15_1 to 15_p (hereinafter, referred to as a video signal D_1) to the data line D_1 provided corresponding to the row of the pixel circuits 15_1 to 15_p.

The pixel circuit 15_1 converts the video signal D_1 for the light emitting element group 16_1 into a current signal having a current value corresponding to the video signal D_1, and outputs the video signal D_1 to the node N_1 at the timing when the gate control signal G_1 becomes active. Further, the pixel circuit 15_2 converts the video signal D_1 for the light emitting element group 16_2 into a current signal having a current value corresponding to the video signal D_1, and outputs the video signal D_1 to the node N_2 at the timing when the gate control signal G_2 becomes active. do. Similarly, the pixel circuit 15_p converts the video signal D_1 for the light emitting element group 16_p into a current signal having a current value corresponding to the video signal D_1, and the node N_p at the timing when the gate control signal G_p becomes active. Output to.

Each pixel circuit 15_1 to 15_p is configured by using, for example, a TFT (Thin Film Transistor). Hereinafter, some specific configuration examples of the pixel circuit 15_1 configured by using the TFT will be described with reference to FIGS. 2 and 3. Since the specific configuration example of the pixel circuit other than the pixel circuit 15_1 has the same circuit configuration as the pixel circuit 15_1, the description thereof will be omitted.

(First specific configuration example of the pixel circuit 15_1)
FIG. 2 is a diagram showing a first specific configuration example of the pixel circuit 15_1 as the pixel circuit 15_1a. The pixel circuit 15_1a is a PAM (Pulse Amplitude Modulation) type pixel circuit, and includes a drive transistor TR11, a switch transistor TR12, and a capacitor CS1.

In the present embodiment, the case where the drive transistor TR11 is a P-channel MOS transistor and the switch transistor TR12 is an N-channel MOS transistor will be described as an example, but the present invention is not limited to this. For example, the drive transistor TR11 may be an N-channel MOS transistor, and the switch transistor TR12 may be a P-channel MOS transistor. However, in that case, the voltage applied to the gate of each transistor is inverted and used.

The drive transistor TR11 is provided between the power supply voltage source VDD and the node N_1 on the anode side of the light emitting element group 16_1.

The switch transistor TR12 is provided between the data line D_1 and the gate of the drive transistor TR11, and switches on and off based on a pulse signal (that is, a gate control signal G_1) propagating along the row scanning line G_1. Further, the capacitor CS1 is provided between the gate and the source of the drive transistor TR11.

For example, when the switch transistor TR12 is temporarily turned on by the H-level pulse waveform of the gate control signal G_1, the video signal (that is, the video signal D_1) propagating on the data line D_1 is gated by the drive transistor TR11 via the switch transistor TR12. Is applied to. The voltage level of the video signal D_1 applied to the gate of the drive transistor TR11 is held by the capacitor CS1 until the next rise of the gate control signal G_1. That is, the voltage level of the video signal D_1 applied to the gate of the drive transistor TR11 is maintained for a period of subfields separated by the pulse waveform of the gate control signal G_1. During the period of this subfield, the node N_1 is continuously supplied with a current signal having a current value corresponding to the video signal D_1. Therefore, the node N_1 is maintained at a voltage value corresponding to this current signal.

(Second specific configuration example of the pixel circuit 15_1)
FIG. 3 is a diagram showing a second specific configuration example of the pixel circuit 15_1 as the pixel circuit 15_1b. The pixel circuit 15_1b is a PWM (Pulse Width Modulation) type pixel circuit, and includes transistors TR21, TR22, TR23, and a capacitor CS2.

In the present embodiment, the case where the transistors TR21 and TR23 are P-channel MOS transistors and the transistor TR22 is an N-channel MOS transistor has been described as an example, but the present invention is not limited to this. For example, the transistors TR21 and TR23 may be N-channel MOS transistors, and the transistors TR22 may be P-channel MOS transistors. However, in that case, the voltage applied to the gate of each transistor is inverted and used.

The transistors TR23 and TR21 are provided in series between the power supply voltage source VDD and the node N_1 on the anode side of the light emitting element group 16_1. A bias voltage Vb is applied to the gate of the transistor TR23. As a result, the transistor TR23 operates as a constant current source.

The transistor TR22 is provided between the data line D_1 and the gate of the transistor TR21, and is switched on and off based on a pulse signal (that is, a gate control signal G_1) propagating along the row scanning line G_1. Further, one end of the capacitor CS2 is connected to the gate of the transistor TR21, and a lamp signal Lamp is applied to the other end of the capacitor CS2. The ramp signal Ramp is a signal whose voltage increases at a predetermined slew rate.

For example, when the transistor TR22 is temporarily turned on by the H-level pulse waveform of the gate control signal G_1, a video signal propagating on the data line D_1 (that is, the video signal D_1) is applied to the gate of the transistor TR21. At this time, since the gate-source voltage of the transistor TR21 is adjusted in advance so as to be equal to or lower than the threshold voltage of the transistor TR21, the transistor TR21 is turned off. Therefore, the constant current from the pixel circuit 15_1b is not supplied to the node N_1.

After that, when the H-level pulse waveforms of the gate control signals G_1 to G_n are sequentially lowered (switched to the L level) and the transistor TR22 of the all-pixel circuit is turned off, the voltage of the lamp signal Lamp becomes the minimum voltage (0V). After being initialized, it begins to rise gradually. Along with this, the gate voltage of the transistor TR21 also starts to rise gradually after falling once.

Here, when the lamp signal Lamp is initialized and the gate voltage of the transistor TR21 drops once, the gate-source voltage of the transistor TR21 becomes larger than the threshold voltage, so that the transistor TR21 is turned on. At this time, the constant current generated by the transistor TR23 is supplied to the node N_1.

After that, when the gate voltage of the transistor TR21 gradually rises and the gate-source voltage of the transistor TR21 becomes equal to or lower than the threshold voltage of the transistor TR21, the transistor TR21 is turned off. Node N_1 is maintained at a predetermined voltage during the ON period of transistor TR21. Here, the ON period of the transistor TR21 depends on the video signal D_1. Therefore, a constant current is supplied to the node N_1 during the time division period according to the video signal D_1. In this way, in the pixel circuit 15_1b, the gradation of the video signal D_1 is expressed by the time division drive.

Since the PWM type pixel circuit 15_1b shown in FIG. 3 uses a constant current source, it is possible to stabilize the luminance efficiency and chromaticity of the diode element, which tends to change depending on the current density.

Further, the configuration of the pixel circuit 15_1 is not limited to the configuration of the pixel circuit 15_1a shown in FIG. 2 and the configuration of the pixel circuit 15_1b shown in FIG. 3, and can be appropriately changed to another configuration capable of realizing the same function. .. Further, the pixel circuit 15_1 may have a variation correction function. This also applies to pixel circuits other than the pixel circuit 15_1.

Hereinafter, in the present embodiment, a case where each pixel circuit 15_1 to 15_p is a PWM type pixel circuit shown in FIG. 3 will be described as an example.

Returning to FIG. 1, the explanation will be continued.
The voltage control circuit 14 is configured to be able to selectively supply the ground voltage GND to any one of the nodes Na, Nb, and Nc. The pixel circuits 15_1 to 15_p transmit a time-division period constant current signal according to the video signal D_1 in a state where the ground voltage GND is selectively supplied to any of the nodes Na, Nb, and Nc. By supplying to N_p, any one of a plurality of (three in this example) light emitting elements provided in each light emitting element group 16_1 to 16_p is selectively emitted.

For example, the voltage control circuit 14 supplies the ground voltage GND to the node Na during the period of the first subfield among the three subfields constituting one field, so that the light emitting element group 16_1 to 16_p The light emitting elements D1a to Dpa provided in each of the above are made to emit light. Further, the voltage control circuit 14 emits light emitting elements D1b to Dpb provided in each of the light emitting element groups 16_1 to 16_p by supplying the ground voltage GND to the node Nb during the period of the second subfield. Let me. Further, the voltage control circuit 14 supplies the ground voltage GND to the node Nc during the period of the third subfield to emit light emitting elements D1c to Dpc provided in each of the light emitting element groups 16_1 to 16_p. Let me.

It is preferable that the voltage control circuit 14 does not supply the reference voltage to two or more nodes of the nodes Na, Nb, and Nc at the same time. In other words, it is preferable that the voltage control circuit 14 does not overlap the supply of the reference voltage to each of the nodes Na, Nb, and Nc. As a result, it is possible to prevent unintended luminescence color mixing by the plurality of luminescent elements.

(Timing chart)
FIG. 4 is a timing chart showing the operation of the display device 1. In the example of FIG. 4, one field is composed of three subfields, which is the same as the number of light emitting elements provided in each light emitting element group 16_1 to 16_p. For example, one field at times t11 to t23 is composed of a first subfield at times t11 to t15, a second subfield at times t15 to t19, and a third subfield at times t19 to t23. .. Hereinafter, a detailed description will be given.

First, as the plurality of video signals D_1 for the light emitting elements D1a to Dpa are sequentially output, the gate control signals G_1 to G_p are temporarily raised in order (time t11 to t13). As a result, the respective video signals D_1 are supplied to the pixel circuits 15_1 to 15_p (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to the pixel circuits 15_1 to 15_p is completed (that is, when all of the gate control signals G_1 to G_p are turned down), the voltage control circuit 14 is transferred to only the node Na among the nodes Na to Nc. The ground voltage GND is supplied to the ground voltage (time t14 to t15).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Na, the constant current signals from the pixel circuits 15_1 to 15_p start to be supplied to the nodes N_1 to N_p, respectively (time t14). Then, the constant current signal continues to be supplied to the nodes N_1 to N_p during the time division period corresponding to each video signal D_1 (arbitrary range within the time t14 to t15). At this time, the nodes N_1 to N_p are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1a to Dpa, which are red light emitting diodes, emit light in the time division period assigned to each (any range within the time t14 to t15).

After that, as the plurality of video signals D_1 for the light emitting elements D1b to Dpb are sequentially output, the gate control signals G_1 to G_p are temporarily raised in order (time t15 to t17). As a result, the respective video signals D_1 are supplied to the pixel circuits 15_1 to 15_p (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to the pixel circuits 15_1 to 15_p is completed (that is, when all of the gate control signals G_1 to G_p are turned down), the voltage control circuit 14 is transferred to only the node Nb among the nodes Na to Nc. The ground voltage GND is supplied to the ground voltage (time t18 to t19).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nb, the constant current signals from the pixel circuits 15_1 to 15_p start to be supplied to the nodes N_1 to N_p, respectively (time t18). Then, the constant current signal continues to be supplied to the nodes N_1 to N_p during the time division period corresponding to each video signal D_1 (arbitrary range within the time t18 to t19). At this time, the nodes N_1 to N_p are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1b to Dpb, which are green light emitting diodes, emit light in the time division period assigned to each (any range within the time t18 to t19).

After that, as the plurality of video signals D_1 for the light emitting elements D1c to Dpc are sequentially output, the gate control signals G_1 to G_p are temporarily raised in order (time t19 to t21). As a result, the respective video signals D_1 are supplied to the pixel circuits 15_1 to 15_p (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to the pixel circuits 15_1 to 15_p is completed (that is, when all of the gate control signals G_1 to G_p are turned down), the voltage control circuit 14 is transferred to only the node Nc among the nodes Na to Nc. The ground voltage GND is supplied to the ground voltage (time t22 to t23).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nc, the constant current signals from the pixel circuits 15_1 to 15_p start to be supplied to the nodes N_1 to N_p, respectively (time t22). Then, the constant current signal continues to be supplied to the nodes N_1 to N_p during the time division period corresponding to each video signal D_1 (arbitrary range within the time t22 to t23). At this time, the nodes N_1 to N_p are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1c to Dpc, which are blue light emitting diodes, emit light in the time division period assigned to each (any range within the time t22 to t23).

That is, in the example of FIG. 4, of the periods of the first to third subfields constituting one field, the red light emitting elements D1a to Dpa are made to emit light during the period of the first subfield, and the second sub is emitted. The green light emitting elements D1b to Dpb are made to emit light during the period of the field, and the blue light emitting elements D1c to Dpc are made to emit light during the period of the third subfield.

Here, in the present embodiment, a pixel circuit (for example, pixel circuit 15_1) commonly provided for a plurality of light emitting elements (for example, light emitting elements D1a, D1b, D1c) switches the light emitting element to be light-emitting. Instead of providing, the voltage control circuit 14 provided outside the panel 11 selectively supplies a reference voltage (ground voltage GND) to any of these plurality of light emitting elements, thereby causing the light emitting element to emit light. I'm switching. As a result, the display device 1 does not need to provide a switch for switching the light emitting element to be light-emitting in each pixel circuit, so that the number of pixel circuits can be reduced without increasing the scale of each pixel circuit. ..

The light emitting elements D1a to Dpa, D1b to Dpb, and D1c to Dpc commonly connected to the voltage control circuit 14 are all preferably controlled so as to emit light at least once during the period of one field. As a result, it is possible to prevent the display data from being lost.

As described above, the display device 1 according to the present embodiment includes a plurality of light emitting elements (for example, light emitting elements D1a, D1b, D1c) and a pixel circuit (for example, a pixel circuit) commonly provided for the plurality of light emitting elements. 15_1) is provided between the plurality of light emitting elements and the reference voltage (ground voltage GND), and the reference voltage is selectively supplied to any one of the plurality of light emitting elements to obtain the plurality of light emitting elements. It includes a voltage control circuit 14 that selectively emits light from any of the two. As a result, the display device 1 according to the present embodiment does not need to provide a switch for switching the light emitting element to be light-emitting in each pixel circuit, so that the number of pixel circuits is not increased without increasing the scale of each pixel circuit. Can be reduced. As a result, for example, even when the light emitting elements are highly integrated, the layout of the pixel circuit becomes easy.

In the present embodiment, the case where each pixel circuit 15_1 to 15_p is configured by using a TFT has been described as an example, but the present invention is not limited to this. For example, each pixel circuit 15_1 to 15_p may be a microcontroller (μC) integrated circuit. When the pixel circuit is configured by using a TFT, the yield is improved by reducing the number of pixel circuits, but when the pixel circuit is a microcontroller (μC) integrated circuit, the pixel circuit By reducing the number of, the size of the microcontroller (μC) integrated circuit can be reduced, so that the cost can be reduced.

Further, in the present embodiment, the case where the common voltage control circuit 14 is provided for the light emitting element groups 16_1 to 16_p has been described as an example, but the present invention is not limited to this. For example, individual voltage control circuits 14 may be provided for each of the light emitting element groups 16_1 to 16_p. In this case, the plurality of voltage control circuits 14 can individually control the light emission of each of the light emitting element groups 16_1 to 16_p.

Subsequently, some modifications of the display device 1 will be described.

(First modification of display device 1)
FIG. 5 is a diagram showing a first modification of the display device 1 as a display device 1a. Further, FIG. 6 is a timing chart showing the operation of the display device 1a. In the display device 1a, the orientation (connection relationship) of each light emitting element is reversed as compared with the case of the display device 1.

Specifically, in the light emitting elements D1a, D1b, and D1c constituting the light emitting element group 16_1, their respective cathodes are connected to the pixel circuit 15_1 via the node N_1, and their respective anodes are connected to the pixel circuit 15_1 via the nodes Na, Nb, and Nc. It is connected to the voltage control circuit 14. Further, in the light emitting elements D2a, D2b, and D2c constituting the light emitting element group 16_2, the respective cathodes are connected to the pixel circuit 15_2 via the node N_2, and the respective anodes are connected to the voltage control circuit via the nodes Na, Nb, and Nc. It is connected to 14. Similarly, in the light emitting elements Dpa, Dpb, and Dpc constituting the light emitting element group 16_p, each cathode is connected to the pixel circuit 15_3 via the node N_3, and each anode has a voltage via the nodes Na, Nb, and Nc. It is connected to the control circuit 14.

The voltage control circuit 14 is provided between the light emitting element group 16_1 to 16_p and the power supply voltage source VDD which is the reference power supply, and selectively supplies the power supply voltage VDD to any one of the nodes Na, Nb, and Nc. It is configured to be possible. The pixel circuits 15_1 to 15_p transmit a constant current signal of a time division period according to the video signal D_1 in a state where the power supply voltage VDD is selectively supplied to any of the nodes Na, Nb, and Nc. By supplying to N_p (in other words, by applying the LED operating voltage of the time division period corresponding to the video signal D_1 to the nodes N_1 to N_p), a plurality of light emitting element groups 16_1 to 16_p are provided (this example). Then, any one of the three) light emitting elements is selectively emitted.

Since the other configurations and operations of the display device 1a are the same as those of the display device 1, the description thereof will be omitted.

The display device 1a can exhibit the same effect as that of the display device 1.

(Second modification of display device 1)
FIG. 7 is a diagram showing a second modification of the display device 1 as the display device 1b. Further, FIG. 8 is a timing chart showing the operation of the display device 1b. In the display device 1b, the number of light emitting elements constituting each light emitting element group 16_1 to 16_p is doubled (6 in this example) as compared with the case of the display device 1. In other words, the number of light emitting elements driven by each pixel circuit 15_1 to 15_p is doubled (6 in this example). In the example of FIG. 7, only the pixel circuit 15_1 and the light emitting element group 16_1 are shown on the panel 11.

Specifically, the light emitting element group 16_1 includes, as a plurality of light emitting elements D, a red (R) light emitting element D1a, a green (G) light emitting element D1b, a blue (B) light emitting element D1c, and a red (R). It includes a light emitting element D1d, a green (G) light emitting element D1e, and a blue (B) light emitting element D1f.

In the light emitting elements D1a, D1b, D1c, D1d, D1e, and D1f constituting the light emitting element group 16_1, their respective anodes are connected to the pixel circuit 15_1 via the node N_1, and their respective cathodes are the nodes Na, Nb, Nc. , Nd, Ne, Nf and are connected to the voltage control circuit 14.

The voltage control circuit 14 is configured to be able to selectively supply the ground voltage GND to any one of the nodes Na, Nb, Nc, Nd, Ne, and Nf. The pixel circuit 15_1 is a constant current signal having a time division period corresponding to the video signal D_1 in a state where the ground voltage GND is selectively supplied to any of the nodes Na, Nb, Nc, Nd, Ne, and Nf. By supplying the above to the node N_1 (in other words, by applying the LED operating voltage of the time division period corresponding to the video signal D_1 to the node N_1), a plurality (6 in this example) provided in the light emitting element group 16_1. ) Is selectively emitted from any of the light emitting elements.

For example, the voltage control circuit 14 causes the light emitting element D1a to emit light by supplying the ground voltage GND to the node Na during the period of the first subfield among the six subfields constituting one field. Further, the light emitting element D1b is made to emit light by supplying the ground voltage GND to the node Nb during the period of the second subfield. Further, the light emitting element D1c is made to emit light by supplying the ground voltage GND to the node Nc during the period of the third subfield. Further, the light emitting element D1d is made to emit light by supplying the ground voltage GND to the node Nd during the period of the fourth subfield. Further, the light emitting element D1e is made to emit light by supplying the ground voltage GND to the node Ne during the period of the fifth subfield. Further, the light emitting element D1f is made to emit light by supplying the ground voltage GND to the node Nf during the period of the sixth subfield.

Since the other configurations and operations of the display device 1b are the same as those of the display device 1, the description thereof will be omitted.

The number of light emitting elements driven by each pixel circuit 15_1 to 15_p is not limited to 3 or 6, and may be any number. However, the number of light emitting elements driven by each pixel circuit 15_1 to 15_p is preferably a multiple of 3 in consideration of increasing or decreasing in units of three color light emitting elements of RGB.

As described above, the display device 1b increases the number of light emitting elements driven by the pixel circuits 15_1 to 15_p on the condition that a sufficient driving period for causing each light emitting element to emit light can be secured. The number of circuits can be further reduced. In addition, each light emitting element may be replaced in the opposite direction as in the case of FIG.

<Embodiment 2>
FIG. 9 is a diagram showing a configuration example of the display device 2 according to the second embodiment. The display device 2 includes a panel 21 instead of the panel 11 as compared with the display device 1. The panel 21 includes a light emitting element group 26_1 to 26_p instead of the light emitting element group 16_1 to 16_p as compared with the panel 11. In the example of FIG. 9, only the pixel circuit 15_1 and the light emitting element groups 26_1 to 26_3 are shown on the panel 21.

Specifically, the light emitting element group 26_1 includes red (R) light emitting elements D1a, D1b, and D1c as a plurality of light emitting elements D. The light emitting element group 26_2 includes green (G) light emitting elements D2a, D2b, and D2c as a plurality of light emitting elements D. The light emitting element group 26_3 includes blue (B) light emitting elements D3a, D3b, and D3c as a plurality of light emitting elements D.

In the light emitting elements D1a, D1b, and D1c constituting the light emitting element group 26_1, their respective anodes are connected to the pixel circuit 15_1 via the node N_1, and their respective cathodes are connected to the pixel circuit 15_1 via the nodes Na, Nb, and Nc. It is connected to 14. In the light emitting elements D2a, D2b, and D2c constituting the light emitting element group 26_2, their respective anodes are connected to the pixel circuit 15_2 via the node N_2, and their respective cathodes are connected to the voltage control circuit via the nodes Na, Nb, and Nc. It is connected to 14. In the light emitting elements D3a, D3b, and D3c constituting the light emitting element group 26_3, the respective anodes are connected to the pixel circuit 15_3 via the node N_3, and the respective cathodes are connected to the pixel circuit 15_3 via the nodes Na, Nb, and Nc. It is connected to 14.

Since the other configurations of the display device 2 are the same as those of the display device 1, the description thereof will be omitted.

(Timing chart)
FIG. 10 is a timing chart showing the operation of the display device 2. In the example of FIG. 10, one field is composed of three subfields, which is the same as the number of light emitting elements provided in each light emitting element group 16_1 to 16_3. For example, one field at times t11 to t23 is composed of a first subfield at times t11 to t15, a second subfield at times t15 to t19, and a third subfield at times t19 to t23. .. Hereinafter, a detailed description will be given.

First, as the plurality of video signals D_1 for the light emitting elements D1a to D3a are sequentially output, the gate control signals G_1 to G_3 are temporarily raised in order (time t11 to t13). As a result, the respective video signals D_1 are supplied to the pixel circuits 15_1 to 15_3 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to the pixel circuits 15_1 to 15_3 is completed (that is, when all of the gate control signals G_1 to G_3 are turned down), the voltage control circuit 14 is transferred to only the node Na among the nodes Na to Nc. The ground voltage GND is supplied to the ground voltage (time t14 to t15).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Na, the constant current signals from the pixel circuits 15_1 to 15_3 start to be supplied to the nodes N_1 to N_3, respectively (time t14). Then, the constant current signal continues to be supplied to the nodes N_1 to N_3 during the time division period corresponding to each video signal D_1 (arbitrary range within the time t14 to t15). At this time, the nodes N_1 to N_3 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the RGB three-color light emitting elements D1a, D2a, and D3a emit light in the time-division period assigned to each (any range within the time t14 to t15).

After that, as the plurality of video signals D_1 for the light emitting elements D1b to D3b are sequentially output, the gate control signals G_1 to G_3 are temporarily raised in order (time t15 to t17). As a result, the respective video signals D_1 are supplied to the pixel circuits 15_1 to 15_3 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to the pixel circuits 15_1 to 15_3 is completed (that is, when all of the gate control signals G_1 to G_3 are turned down), the voltage control circuit 14 is transferred to only the node Nb among the nodes Na to Nc. The ground voltage GND is supplied to the ground voltage (time t18 to t19).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nb, the constant current signals from the pixel circuits 15_1 to 15_3 start to be supplied to the nodes N_1 to N_3, respectively (time t18). Then, the constant current signals continue to be supplied to the nodes N_1 to N_3 during the time division period corresponding to the respective video signals D_1 (arbitrary range within the time t18 to t19). At this time, the nodes N_1 to N_3 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the RGB light emitting elements D1b, D2b, and D3b emit light in the time division period assigned to each (any range within the time t18 to t19).

After that, as the plurality of video signals D_1 for the light emitting elements D1c to D3c are sequentially supplied, the gate control signals G_1 to G_3 are temporarily raised in order (time t19 to t21). As a result, the respective video signals D_1 are supplied to the pixel circuits 15_1 to 15_3 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to the pixel circuits 15_1 to 15_3 is completed (that is, when all of the gate control signals G_1 to G_3 are turned down), the voltage control circuit 14 is transferred to only the node Nc among the nodes Na to Nc. The ground voltage GND is supplied to the ground voltage (time t22 to t23).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nc, the constant current signals from the pixel circuits 15_1 to 15_3 start to be supplied to the nodes N_1 to N_3, respectively (time t22). Then, the constant current signal continues to be supplied to the nodes N_1 to N_3 during the time division period corresponding to each video signal D_1 (arbitrary range within the time t22 to t23). At this time, the nodes N_1 to N_3 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the RGB three-color light emitting elements D1c, D2c, and D3c emit light in the time-division period assigned to each (any range within the time t22 to t23).

That is, in the example of FIG. 10, the light emitting elements of three colors of RGB are made to emit light in each period of the first to third subfields constituting one field.

Here, in the present embodiment, a pixel circuit (for example, pixel circuit 15_1) commonly provided for a plurality of light emitting elements (for example, light emitting elements D1a, D1b, D1c) switches the light emitting element to be light-emitting. Instead of providing, the voltage control circuit 14 provided outside the panel 21 selectively supplies a reference voltage (ground voltage GND) to any of these plurality of light emitting elements, thereby causing the light emitting element to emit light. I'm switching. As a result, the display device 2 does not need to provide a switch for switching the light emitting element to be light-emitting in each pixel circuit, so that the number of pixel circuits can be reduced without increasing the scale of each pixel circuit. ..

The light emitting elements D1a to D3a, D1b to D3b, and D1c to D3c commonly connected to the voltage control circuit 14 are all preferably controlled so as to emit light at least once during the period of one field. As a result, it is possible to prevent the display data from being lost.

As described above, the display device 2 according to the present embodiment can exert the same effect as the display device 1. Further, since the display device 2 according to the present embodiment can simultaneously emit light emitting elements of three colors of RGB, color break noise can be suppressed. Further, in the display device 2 according to the present embodiment, when each pixel circuit is a PWM pixel circuit, a plurality of light emitting elements driven by each pixel circuit are made to have the same color, so that a constant current of each pixel circuit is obtained. Adjustment can be suppressed to, for example, about once per field.

In the present embodiment, the case where the common voltage control circuit 14 is provided for the light emitting element groups 26_1 to 26_3 has been described as an example, but the present invention is not limited to this. For example, individual voltage control circuits 14 may be provided for each of the light emitting element groups 26_1 to 26_3. In this case, the plurality of voltage control circuits 14 can individually control the light emission of each of the light emitting element groups 26_1 to 26_3.

Subsequently, some modifications of the display device 2 will be described.

(First modification of display device 2)
FIG. 11 is a diagram showing a second modification of the display device 2 as the display device 2a. Further, FIG. 12 is a timing chart showing the operation of the display device 2a. In the display device 2a, the orientation (connection relationship) of each light emitting element is reversed as compared with the case of the display device 2.

Specifically, in the light emitting elements D1a, D1b, and D1c constituting the light emitting element group 26_1, their respective cathodes are connected to the pixel circuit 15_1 via the node N_1, and their respective anodes are connected to the pixel circuit 15_1 via the nodes Na, Nb, and Nc. It is connected to the voltage control circuit 14. Further, in the light emitting elements D2a, D2b, and D2c constituting the light emitting element group 26_2, the respective cathodes are connected to the pixel circuit 15_2 via the node N_2, and the respective anodes are connected to the voltage control circuit via the nodes Na, Nb, and Nc. It is connected to 14. Further, in the light emitting elements D3a, D3b, and D3c constituting the light emitting element group 16_3, the respective cathodes are connected to the pixel circuit 15_2 via the node N_3, and the respective anodes are connected to the pixel circuit 15_2 via the nodes Na, Nb, and Nc. It is connected to 14.

The voltage control circuit 14 is provided between the light emitting element groups 26_1 to 26_3 and the power supply voltage source VDD which is the reference power supply, and selectively supplies the power supply voltage VDD to any of the nodes Na, Nb, and Nc. It is configured to be possible. The pixel circuits 15_1 to 15_3 transmit a constant current signal of a time division period according to the video signal D_1 in a state where the power supply voltage VDD is selectively supplied to any of the nodes Na, Nb, and Nc. By supplying to N_3 (in other words, by applying the LED operating voltage of the time division period corresponding to the video signal D_1 to the nodes N_1 to N_3), a plurality of light emitting element groups 26_1 to 26___ are provided (this example). Then, any one of the three) light emitting elements is selectively emitted.

Since the other configurations and operations of the display device 2a are the same as those of the display device 2, the description thereof will be omitted.

The display device 2a can exhibit the same effect as that of the display device 2.

(Second modification of display device 2)
FIG. 13 is a diagram showing a second modification of the display device 2 as the display device 2b. Further, FIG. 14 is a timing chart showing the operation of the display device 2b. In the display device 2b, the number of light emitting elements constituting each light emitting element group 26_1 to 26_3 is doubled (6 in this example) as compared with the case of the display device 2. In other words, the number of light emitting elements driven by each pixel circuit 15_1 to 15_3 is doubled (6 in this example). In the example of FIG. 13, only the pixel circuit 15_1 and the light emitting element group 26_1 are shown on the panel 21.

Specifically, the light emitting element group 26_1 includes red (R) light emitting elements D1a, D1b, D1c, D1d, D1e, and D1f as the plurality of light emitting elements D. Further, the light emitting element group 26_2 (not shown) includes green (G) light emitting elements D2a, D2b, D2c, D2d, D2e, and D2f as a plurality of light emitting elements D. Further, the light emitting element group 26_3 (not shown) includes blue (B) light emitting elements D3a, D3b, D3c, D3d, D3e, and D3f as a plurality of light emitting elements D.

In the light emitting elements D1a, D1b, D1c, D1d, D1e, and D1f constituting the light emitting element group 26_1, the respective anodes are connected to the pixel circuit 15_1 via the node N_1, and the respective cathodes are the nodes Na, Nb, Nc. , Nd, Ne, Nf and are connected to the voltage control circuit 14. Further, in the light emitting elements D2a, D2b, D2c, D2d, D2e, and D2f constituting the light emitting element group 26_2 (not shown), the respective anodes are connected to the pixel circuit 15_2 via the node N_2, and the respective cathodes are connected to the node Na. , Nb, Nc, Nd, Ne, Nf are connected to the voltage control circuit 14. Further, in the light emitting elements D3a, D3b, D3c, D3d, D3e, and D3f constituting the light emitting element group 26_3 (not shown), the respective anodes are connected to the pixel circuit 15_3 via the node N_3, and the respective cathodes are connected to the node Na. , Nb, Nc, Nd, Ne, Nf are connected to the voltage control circuit 14.

The voltage control circuit 14 is configured to be able to selectively supply the ground voltage GND to any one of the nodes Na, Nb, Nc, Nd, Ne, and Nf. The pixel circuits 15_1 to 15_3 determine the time division period according to the video signal D_1 in a state where the ground voltage GND is selectively supplied to any of the nodes Na, Nb, Nc, Nd, Ne, and Nf. By supplying the current signal to the nodes N_1 to N_3 (in other words, by applying the LED operating voltage of the time division period corresponding to the video signal D_1 to the nodes N_1 to N_3), each light emitting element group 26_1 to 26_3 is provided. Any one of the plurality of (6 in this example) light emitting elements is selectively emitted.

For example, the voltage control circuit 14 causes the light emitting elements D1a to D3a to emit light by supplying the ground voltage GND to the node Na during the period of the first subfield among the six subfields constituting one field. .. Further, the light emitting elements D1b to D3b are made to emit light by supplying the ground voltage GND to the node Nb during the period of the second subfield. Further, the light emitting elements D1c to D3c are made to emit light by supplying the ground voltage GND to the node Nc during the period of the third subfield. Further, the light emitting elements D1d to D3d are made to emit light by supplying the ground voltage GND to the node Nd during the period of the fourth subfield. Further, the light emitting elements D1e to D3e are made to emit light by supplying the ground voltage GND to the node Ne during the period of the fifth subfield. Further, the light emitting elements D1f to D3f are made to emit light by supplying the ground voltage GND to the node Nf during the period of the sixth subfield.

Since the other configurations and operations of the display device 2b are the same as those of the display device 2, the description thereof will be omitted.

The number of light emitting elements driven by each pixel circuit 15_1 to 15_p is not limited to 3 or 6, and may be any number. In particular, in the present embodiment, the number of light emitting elements driven by each pixel circuit 15_1 to 15_p does not need to be considered to be increased or decreased in units of three color light emitting elements of RGB, so the number is a multiple of three. It doesn't have to be.

As described above, the display device 2b increases the number of light emitting elements driven by the pixel circuits 15_1 to 15_p on the condition that a sufficient driving period for causing each light emitting element to emit light can be secured. The number of circuits can be further reduced. In addition, each light emitting element may be replaced in the opposite direction as in the case of FIG.

<Embodiment 3>
FIG. 15 is a diagram showing a configuration example of the display device 3 according to the third embodiment.
The display device 3 includes a panel 31 instead of the panel 11 as compared with the display device 1. The panel 31 is provided with a plurality of red (R) light emitting elements D having m (m is an integer of 2 or more) rows and n (n is an integer of 2 or more) columns. Although not shown, the panel 31 is also provided with a plurality of green (G) light emitting elements D and a plurality of blue (B) light emitting elements D corresponding to the plurality of red (R) light emitting elements D. ing. Hereinafter, unless otherwise specified, a plurality of red (R) light emitting elements D shown will be described, but a plurality of green (G) light emitting elements D and a plurality of blue (B) light emitting elements D (not shown) will be described. Also, the same configuration as that adopted for the plurality of red (R) light emitting elements D is adopted.

In the present embodiment, in each column of a plurality of light emitting elements D provided in a matrix of m rows × n columns, r (r is an integer of 2 or more and m or less) rows of light emitting elements D (that is, r). A light emitting element group 36 composed of the light emitting elements D) is configured. In the example of FIG. 15, in each column, a light emitting element group 36 composed of four rows of light emitting elements D is configured. Note that FIG. 15 shows four rows of light emitting element groups 36_1 to 36_4 as a part of the plurality of light emitting element groups 36.

Specifically, the light emitting element group 36_1 is composed of four light emitting elements D1a to D1d from the first row to the fourth row in the first column. Further, the light emitting element group 36_2 is composed of four light emitting elements D2a to D2d from the first row to the fourth row in the second column. Further, the light emitting element group 36_3 is composed of four light emitting elements D3a to D3d from the first row to the fourth row in the third column. Further, the light emitting element group 36_4 is composed of four light emitting elements D4a to D4d from the first row to the fourth row in the fourth column.

Further, FIG. 15 shows pixel circuits 15_1 to 15_4 for driving each of the light emitting element groups 36_1 to 36_4 as a part of the plurality of pixel circuits 15.

The voltage control circuit 14 is provided between the light emitting element groups 36_1 to 36_4 and the ground voltage source GND which is a reference power source. In this embodiment, a case where the voltage control circuit 14 is provided in common for the light emitting element groups 36_1 to 36_4 will be described as an example.

More specifically, in the light emitting elements D1a to D1d constituting the light emitting element group 36_1, each anode is connected to the pixel circuit 15_1 via the node N_1, and each cathode has a voltage via the nodes Na to Nd. It is connected to the control circuit 14. Further, in the light emitting elements D2a to D2d constituting the light emitting element group 36_2, each anode is connected to the pixel circuit 15_2 via the node N_2, and each cathode is connected to the voltage control circuit 14 via the nodes Na to Nd. It is connected. Further, in the light emitting elements D3a to D3d constituting the light emitting element group 36_3, each anode is connected to the pixel circuit 15_3 via the node N_3, and each cathode is connected to the voltage control circuit 14 via the nodes Na to Nd. It is connected. Further, in the light emitting elements D4a to D4d constituting the light emitting element group 36_4, each anode is connected to the pixel circuit 15_4 via the node N_4, and each cathode is connected to the voltage control circuit 14 via the nodes Na to Nd. It is connected.

The voltage control circuit 14 is configured to be able to selectively supply the ground voltage GND to any of the nodes Na to Nd. The pixel circuits 15_1 to 15_4 were supplied to the video signals D_1 to D_4 (data drivers 12 to the data lines D_1 to D_4) in a state where the ground voltage GND was selectively supplied to any of the nodes Na to Nd. By supplying a constant current signal of the time division period corresponding to the video signal) to the nodes N_1 to N_4 (in other words, the LED operating voltage of the time division period corresponding to the video signals D_1 to D_4 is applied to the nodes N_1 to N_4. (By this), any one of a plurality of (four in this example) light emitting elements provided in each light emitting element group 36_1 to 36_4 is selectively emitted.

For example, the voltage control circuit 14 supplies the ground voltage GND to the node Na during the period of the first subfield among the four subfields constituting one field, so that the light emitting element group 36_1 to 36_4 The light emitting elements D1a to D4a of the first row provided in each of the above are made to emit light. Further, the voltage control circuit 14 supplies the ground voltage GND to the node Nb during the period of the second subfield, so that the light emitting element D1b of the second row provided in each of the light emitting element groups 36_1 to 36_4 is provided. ~ D4b is made to emit light. Further, the voltage control circuit 14 supplies the ground voltage GND to the node Nc during the period of the third subfield, so that the light emitting element D1c in the third row provided in each of the light emitting element groups 36_1 to 36_4 is provided. ~ D4c is made to emit light. Further, the voltage control circuit 14 supplies the ground voltage GND to the node Nd during the period of the fourth subfield, so that the light emitting element D1d on the fourth row provided in each of the light emitting element groups 36_1 to 36_4 is provided. ~ D4d is made to emit light.

Since the other configurations of the display device 3 are the same as those of the display device 1, the description thereof will be omitted.

(Timing chart)
FIG. 16 is a timing chart showing the operation of the display device 3. In the example of FIG. 16, one field is composed of four subfields, which is the same as the number of light emitting elements provided in each light emitting element group 36_1 to 36_4. For example, one field at times t31 to t39 includes a first subfield at times t31 to t33, a second subfield at times t33 to t35, a third subfield at times t35 to t37, and times t37 to t39. It is composed of the fourth subfield of. Hereinafter, a detailed description will be given.

First, the gate control signal G_1 temporarily rises as the video signals D_1 to D_1 provided for the light emitting elements D1a to D4a on the first line are output (time t31). As a result, the respective video signals D_1 to D_4 are supplied to the pixel circuits 15_1 to 15_4 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to D_1 to the pixel circuits 15_1 to 15_4 is completed (that is, when the gate control signal G_1 goes down), the voltage control circuit 14 applies only to the node Na among the nodes Na to Nd. The ground voltage GND is supplied (time t32 to t33).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Na, the constant current signals from the pixel circuits 15_1 to 15_4 start to be supplied to the nodes N_1 to N_4, respectively (time t32). Then, the constant current signal continues to be supplied to the nodes N_1 to N_1 during the time division period corresponding to the respective video signals D_1 to D_4 (arbitrary range within the time t32 to t33). At this time, the nodes N_1 to N_14 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1a to D4a provided in the first line emit light in the time division period assigned to each (any range within the time t32 to t33).

After that, the gate control signal G_1 temporarily rises as the video signals D_1 to D_1 provided for the light emitting elements D1b to D4b provided on the second line are output (time t33). As a result, the respective video signals D_1 to D_4 are supplied to the pixel circuits 15_1 to 15_4 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to D_1 to the pixel circuits 15_1 to 15_4 is completed (that is, when the gate control signal G_1 goes down), the voltage control circuit 14 applies only to the node Nb among the nodes Na to Nd. The ground voltage GND is supplied (time t34 to t35).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nb, the constant current signals from the pixel circuits 15_1 to 15_4 start to be supplied to the nodes N_1 to N_4, respectively (time t34). Then, the constant current signal continues to be supplied to the nodes N_1 to N_1 during the time division period corresponding to the respective video signals D_1 to D_4 (arbitrary range within the time t34 to t35). At this time, the nodes N_1 to N_14 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1b to D4b provided in the second line emit light in the time division period assigned to each (any range within the time t34 to t35).

After that, the gate control signal G_1 temporarily rises as the video signals D_1 to D_1 provided for the light emitting elements D1c to D4c provided on the third line are output (time t35). As a result, the respective video signals D_1 to D_4 are supplied to the pixel circuits 15_1 to 15_4 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to D_1 to the pixel circuits 15_1 to 15_4 is completed (that is, when the gate control signal G_1 goes down), the voltage control circuit 14 applies only to the node Nc among the nodes Na to Nd. The ground voltage GND is supplied (time t36 to t37).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nc, the constant current signals from the pixel circuits 15_1 to 15_4 start to be supplied to the nodes N_1 to N_4, respectively (time t36). Then, the constant current signal continues to be supplied to the nodes N_1 to N_1 during the time division period corresponding to the respective video signals D_1 to D_4 (arbitrary range within the time t36 to t37). At this time, the nodes N_1 to N_14 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1c to D4c provided in the third line emit light in the time division period assigned to each (any range within the time t36 to t37).

After that, the gate control signal G_1 temporarily rises as the video signals D_1 to D_1 provided for the light emitting elements D1d to D4d provided on the fourth line are output (time t37). As a result, the respective video signals D_1 to D_4 are supplied to the pixel circuits 15_1 to 15_4 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to D_1 to the pixel circuits 15_1 to 15_4 is completed (that is, when the gate control signal G_1 goes down), the voltage control circuit 14 applies only to the node Nd among the nodes Na to Nd. The ground voltage GND is supplied (time t38 to t39).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nd, the constant current signals from the pixel circuits 15_1 to 15_4 start to be supplied to the nodes N_1 to N_4, respectively (time t38). Then, the constant current signal continues to be supplied to the nodes N_1 to N_1 during the time division period corresponding to the respective video signals D_1 to D_4 (arbitrary range within the time t38 to t39). At this time, the nodes N_1 to N_14 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1d to D4d provided on the fourth line emit light in the time division period assigned to each (any range within the time t38 to t39).

That is, in the example of FIG. 16, among the periods of the first to fourth subfields constituting one field, the light emitting elements D1a to D4a of the first row are made to emit light during the period of the first subfield, and the second During the period of the subfield, the light emitting elements D1b to D4b in the second row are made to emit light, and during the period of the third subfield, the light emitting elements D1c to D4c in the third row are made to emit light, and during the period of the fourth subfield. The light emitting elements D1d to D4d on the fourth line are made to emit light.

Here, in the present embodiment, a pixel circuit (for example, pixel circuit 15_1) commonly provided for a plurality of light emitting elements (for example, light emitting elements D1a to D1d) includes a switch for switching the light emitting element to be light-emitting. Instead, the voltage control circuit 14 provided outside the panel 31 selectively supplies a reference voltage (ground voltage GND) to any of these plurality of light emitting elements to switch the light emitting element to be light-emitting. There is. As a result, the display device 3 does not need to provide a switch for switching the light emitting element to be light-emitting in each pixel circuit, so that the number of pixel circuits can be reduced without increasing the scale of each pixel circuit. .. Specifically, in the present embodiment, the number of pixel circuits is reduced to about 1/r (1/4 in this example) as compared with the case where the pixel circuits are individually provided for each of the plurality of light emitting elements. Can be reduced to. Along with this, the scale of the gate driver 13 and the number of row scanning lines can be reduced to about 1 / r.

The light emitting elements D1a to D4a, D1b to D4b, D1c to D4c, and D1d to D4d commonly connected to the voltage control circuit 14 are all controlled to emit light at least once during the period of one field. Is preferable. As a result, it is possible to prevent the display data from being lost.

As described above, the display device 3 according to the present embodiment can exert the same effect as the display device 1. In the present embodiment, the number of pixel circuits can be reduced to about 1 / r (1/4 in this example) as compared with the case where pixel circuits are individually provided for each of the plurality of light emitting elements. can. Along with this, the scale of the gate driver 13 and the number of row scanning lines can be reduced to about 1 / r. Further, in the display device 3 according to the present embodiment, the plurality of light emitting elements arranged in the same row among the plurality of light emitting elements provided in a matrix and the voltage control circuit 14 are connected by a common power supply line. Has been done. As a result, the wiring of the power supply line becomes linear in the lateral direction (X-axis direction), for example, so that the wiring of the power supply line becomes easy. In addition, each light emitting element may be replaced in the opposite direction as in the case of other embodiments.

In the present embodiment, the case where the common voltage control circuit 14 is provided for the four rows of light emitting element groups 36_1 to 36_4 has been described as an example, but the present invention is not limited to this. A common voltage control circuit 14 may be provided for the light emitting element group 36 for any integer sequence of 1 or more and n or less.

Further, in the present embodiment, the case where the number of light emitting elements driven by each pixel circuit 15_1 to 15_4 is four has been described as an example, but the present invention is not limited to this. The number of light emitting elements driven by each pixel circuit 15_1 to 15_4 may be an arbitrary integer of 2 or more and m or less.

Further, a plurality of light emitting element groups 36 composed of r rows of light emitting elements D may be configured in each column of the plurality of light emitting elements D provided in a matrix of m rows × n columns. Specifically, for example, in the case of m = 8 and r = 4, one light emitting element group 36 is composed of four light emitting elements D from the first row to the fourth row of each column, and 5 in each column. Another light emitting element group 36 may be formed by the four light emitting elements D from the first row to the eighth row. At this time, the plurality of light emitting element groups 36 provided in each row are driven by different pixel circuits 15.

Further, in the present embodiment, the case where the plurality of light emitting elements D are all red (R) light emitting elements has been described as an example, but the present invention is not limited to this. The plurality of light emitting elements D may be green (G) light emitting elements, all may be blue (B) light emitting elements, or each of the three colors (RGB). It may be any light emitting element.

<Embodiment 4>
FIG. 17 is a diagram showing a configuration example of the display device 4 according to the fourth embodiment.
The display device 4 includes a panel 41 instead of the panel 11 as compared with the display device 1. The panel 41 is provided with a plurality of red (R) light emitting elements D having m rows and n columns. Although not shown, the panel 41 is also provided with a plurality of green (G) light emitting elements D and a plurality of blue (B) light emitting elements D corresponding to the plurality of red (R) light emitting elements D. ing. Hereinafter, unless otherwise specified, a plurality of red (R) light emitting elements D shown will be described, but a plurality of green (G) light emitting elements D and a plurality of blue (B) light emitting elements D (not shown) will be described. Also, the same configuration as that adopted for the plurality of red (R) light emitting elements D is adopted.

In the present embodiment, in each row of a plurality of light emitting elements D provided in a matrix of m rows × n columns, s (that is, s) of light emitting elements D (that is, s) for s (s is an integer of 2 or more and n or less) columns. The light emitting element group 46 including the light emitting element D) of the above is configured. In the example of FIG. 17, a light emitting element group 46 composed of four columns of light emitting elements D is configured in each row. Note that FIG. 17 shows four rows of light emitting element groups 46_1 to 46_4 as a part of the plurality of light emitting element groups 46.

Specifically, the light emitting element group 46_1 is composed of four light emitting elements D1a to D1d from the first column to the fourth column in the first row. Further, the light emitting element group 46_2 is composed of four light emitting elements D2a to D2d from the first column to the fourth column in the second row. Further, the light emitting element group 46_3 is composed of four light emitting elements D3a to D3d from the first column to the fourth column in the third row. Further, the light emitting element group 46_4 is composed of four light emitting elements D4a to D4d from the first column to the fourth column in the fourth row.

Further, FIG. 17 shows pixel circuits 15_1 to 15_4 for driving each of the light emitting element groups 46_1 to 46_4 as a part of the plurality of pixel circuits 15.

The voltage control circuit 14 is provided between the light emitting element groups 46_1 to 46_4 and the ground voltage source GND which is a reference power source. In the present embodiment, a case where the voltage control circuit 14 is provided in common for the light emitting element groups 46_1 to 46_4 will be described as an example.

More specifically, in the light emitting elements D1a to D1d constituting the light emitting element group 46_1, each anode is connected to the pixel circuit 15_1 via the node N_1, and each cathode has a voltage via the nodes Na to Nd. It is connected to the control circuit 14. Further, in the light emitting elements D2a to D2d constituting the light emitting element group 46_2, each anode is connected to the pixel circuit 15_2 via the node N_2, and each cathode is connected to the voltage control circuit 14 via the nodes Na to Nd. It is connected. Further, in the light emitting elements D3a to D3d constituting the light emitting element group 46_3, each anode is connected to the pixel circuit 15_3 via the node N_3, and each cathode is connected to the voltage control circuit 14 via the nodes Na to Nd. It is connected. Further, in the light emitting elements D4a to D4d constituting the light emitting element group 46_4, each anode is connected to the pixel circuit 15_4 via the node N_4, and each cathode is connected to the voltage control circuit 14 via the nodes Na to Nd. It is connected.

The voltage control circuit 14 is configured to be able to selectively supply the ground voltage GND to any of the nodes Na to Nd. The pixel circuits 15_1 to 15_4 transmit a constant current signal of the time division period according to the video signal D_1 to the nodes N_1 to N_1 in a state where the ground voltage GND is selectively supplied to any of the nodes Na to Nd. By supplying (in other words, by applying the LED operating voltage of the time division period corresponding to the video signal D_1 to the nodes N_1 to N_1), a plurality (4 in this example) provided in each light emitting element group 46_1 to 46___. Selectively emit light from any of the light emitting elements.

For example, the voltage control circuit 14 supplies the ground voltage GND to the node Na during the period of the first subfield among the four subfields constituting one field, so that the light emitting element group 46_1 to 46_4 The first-row light emitting elements D1a to D4a provided in each of the above are made to emit light. Further, the voltage control circuit 14 supplies the ground voltage GND to the node Nb during the period of the second subfield, so that the second row of light emitting elements D1b provided in each of the light emitting element groups 46_1 to 46_4. ~ D4b is made to emit light. Further, the voltage control circuit 14 supplies the ground voltage GND to the node Nc during the period of the third subfield, so that the light emitting elements D1c in the third row provided in each of the light emitting element groups 46_1 to 46_4 are provided. ~ D4c is made to emit light. Further, the voltage control circuit 14 supplies the ground voltage GND to the node Nd during the period of the fourth subfield, so that the light emitting elements D1d in the fourth row provided in each of the light emitting element groups 46_1 to 46_4 are provided. ~ D4d is made to emit light.

Since the other configurations of the display device 4 are the same as those of the display device 1, the description thereof will be omitted.

(Timing chart)
FIG. 18 is a timing chart showing the operation of the display device 4. In the example of FIG. 18, one field is composed of four subfields, which is the same as the number of light emitting elements provided in each light emitting element group 46_1 to 46_4. For example, one field at times t41 to t61 includes a first subfield at times t41 to t46, a second subfield at times t46 to t51, a third subfield at times t51 to t56, and times t56 to t61. It is composed of the fourth subfield of. Hereinafter, a detailed description will be given.

First, as the plurality of video signals D_1 provided for the light emitting elements D1a to D4a in the first row are sequentially output, the gate control signals G_1 to G_1 are temporarily raised in order (time t41 to t44). ). As a result, the respective video signals D_1 are supplied to the pixel circuits 15_1 to 15_4 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to the pixel circuits 15_1 to 15_4 is completed (that is, when all of the gate control signals G_1 to G_1 are turned down), the voltage control circuit 14 is transferred to only the node Na among the nodes Na to Nd. The ground voltage GND is supplied to the ground voltage (time t45 to t46).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Na, the constant current signals from the pixel circuits 15_1 to 15_4 start to be supplied to the nodes N_1 to N_4, respectively (time t45). Then, the constant current signals continue to be supplied to the nodes N_1 to N_1 during the time division period corresponding to the respective video signals D_1 (arbitrary range within the time t45 to t46). At this time, the nodes N_1 to N_14 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1a to D4a provided in the first row emit light in the time division period assigned to each (any range within the time t45 to t46).

After that, as the plurality of video signals D_1 for the light emitting elements D1b to D4b provided in the second row are sequentially output, the gate control signals G_1 to G_1 are temporarily raised in order (time t46 to t49). ). As a result, the respective video signals D_1 are supplied to the pixel circuits 15_1 to 15_4 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to the pixel circuits 15_1 to 15_4 is completed (that is, when all of the gate control signals G_1 to G_1 are turned down), the voltage control circuit 14 is transferred to only the node Nb among the nodes Na to Nd. The ground voltage GND is supplied to the ground voltage (time t50 to t51).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nb, the constant current signals from the pixel circuits 15_1 to 15_4 start to be supplied to the nodes N_1 to N_4, respectively (time t50). Then, the constant current signals continue to be supplied to the nodes N_1 to N_1 during the time division period corresponding to the respective video signals D_1 (arbitrary range within the time t50 to t51). At this time, the nodes N_1 to N_14 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1b to D4b provided in the second row emit light in the time division period assigned to each (any range within the time t50 to t51).

After that, as the plurality of video signals D_1 for the light emitting elements D1c to D4c provided in the third row are sequentially output, the gate control signals G_1 to G_1 are temporarily raised in order (time t51 to t54). ). As a result, the respective video signals D_1 are supplied to the pixel circuits 15_1 to 15_4 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to the pixel circuits 15_1 to 15_4 is completed (that is, when all of the gate control signals G_1 to G_1 are turned down), the voltage control circuit 14 is transferred to only the node Nc among the nodes Na to Nd. The ground voltage GND is supplied to the ground voltage (time t55 to t56).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nc, the constant current signals from the pixel circuits 15_1 to 15_4 start to be supplied to the nodes N_1 to N_4, respectively (time t55). Then, the constant current signals continue to be supplied to the nodes N_1 to N_1 during the time division period corresponding to the respective video signals D_1 (arbitrary range within the time t55 to t56). At this time, the nodes N_1 to N_14 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1c to D4c provided in the third row emit light in the time division period assigned to each (any range within the time t55 to t56).

After that, as the plurality of video signals D_1 for the light emitting elements D1d to D4d provided in the fourth row are sequentially output, the gate control signals G_1 to G_1 are temporarily raised in order (time t56 to t59). ). As a result, the respective video signals D_1 are supplied to the pixel circuits 15_1 to 15_4 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals D_1 to the pixel circuits 15_1 to 15_4 is completed (that is, when all of the gate control signals G_1 to G_1 are turned down), the voltage control circuit 14 is transferred to only the node Nd among the nodes Na to Nd. The ground voltage GND is supplied to the ground voltage (time t60 to t61).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nd, the constant current signals from the pixel circuits 15_1 to 15_4 start to be supplied to the nodes N_1 to N_4, respectively (time t60). Then, the constant current signals continue to be supplied to the nodes N_1 to N_1 during the time division period corresponding to the respective video signals D_1 (arbitrary range within the time t60 to t61). At this time, the nodes N_1 to N_14 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1d to D4d provided in the fourth row emit light in the time division period assigned to each (any range within the time t60 to t61).

That is, in the example of FIG. 18, among the periods of the first to fourth subfields constituting one field, the light emitting elements D1a to D4a in the first row are made to emit light during the period of the first subfield, and the second During the period of the subfield, the light emitting elements D1b to D4b in the second row are made to emit light, and during the period of the third subfield, the light emitting elements D1c to D4c in the third row are made to emit light, and during the period of the fourth subfield. The light emitting elements D1d to D4d in the fourth row are made to emit light.

Here, in the present embodiment, a pixel circuit (for example, pixel circuit 15_1) commonly provided for a plurality of light emitting elements (for example, light emitting elements D1a to D1d) includes a switch for switching the light emitting element to be light-emitting. Instead, the voltage control circuit 14 provided outside the panel 41 selectively supplies a reference voltage (ground voltage GND) to any of these plurality of light emitting elements to switch the light emitting element to be light-emitting. There is. As a result, the display device 4 does not need to provide a switch for switching the light emitting element to be light-emitting in each pixel circuit, so that the number of pixel circuits can be reduced without increasing the scale of each pixel circuit. .. Specifically, in the present embodiment, the number of pixel circuits is reduced to about 1/s (1/4 in this example) as compared with the case where pixel circuits are individually provided for each of the plurality of light emitting elements. Can be reduced to. Along with this, the scale of the data driver 12 and the number of data lines can be reduced to about 1 / s.

The light emitting elements D1a to D4a, D1b to D4b, D1c to D4c, and D1d to D4d commonly connected to the voltage control circuit 14 are all controlled to emit light at least once during the period of one field. Is preferable. As a result, it is possible to prevent the display data from being lost.

As described above, the display device 4 according to the present embodiment can exert the same effect as the display device 1. In the present embodiment, the number of pixel circuits can be reduced to about 1/s (1/4 in this example) as compared with the case where the pixel circuits are individually provided for each of the plurality of light emitting elements. can. Along with this, the scale of the data driver 12 and the number of data lines can be reduced to about 1 / s. Further, in the display device 4 according to the present embodiment, the plurality of light emitting elements arranged in the same row among the plurality of light emitting elements provided in a matrix and the voltage control circuit 14 are connected by a common power supply line. Has been done. As a result, the wiring of the power supply line becomes linear in the vertical direction (Y-axis direction), for example, so that the wiring of the power supply line becomes easy. In addition, each light emitting element may be replaced in the opposite direction as in the case of other embodiments.

In the present embodiment, the case where the common voltage control circuit 14 is provided for the light emitting element groups 46_1 to 46_4 for four rows has been described as an example, but the present invention is not limited to this. A common voltage control circuit 14 may be provided for the light emitting element group 46 for any integer line of 1 or more and m or less.

Further, in the present embodiment, the case where the number of light emitting elements driven by each pixel circuit 15_1 to 15_4 is four has been described as an example, but the present invention is not limited to this. The number of light emitting elements driven by each pixel circuit 15_1 to 15_4 may be an arbitrary integer of 2 or more and n or less.

Further, a plurality of light emitting element groups 46 composed of light emitting elements D for s columns may be configured in each row of the plurality of light emitting elements D provided in a matrix of m rows × n columns. Specifically, for example, in the case of n = 8 and s = 4, one light emitting element group 46 is composed of four light emitting elements D from the first column to the fourth column of each row, and the fifth column of each row. Another light emitting element group 46 may be formed by four light emitting elements D from the first to the eighth row. At this time, the plurality of light emitting element groups 46 provided in each row are driven by different pixel circuits 15.

Further, in the present embodiment, the case where the plurality of light emitting elements D are all red (R) light emitting elements has been described as an example, but the present invention is not limited to this. The plurality of light emitting elements D may be green (G) light emitting elements, all may be blue (B) light emitting elements, or each of the three colors (RGB). It may be any light emitting element.

<Embodiment 5>
FIG. 19 is a diagram showing a configuration example of the display device 5 according to the fifth embodiment.
The display device 5 includes a panel 51 instead of the panel 11 as compared with the display device 1. The panel 51 is provided with a plurality of red (R) light emitting elements D having m rows and n columns. Although not shown, the panel 51 is also provided with a plurality of green (G) light emitting elements D and a plurality of blue (B) light emitting elements D corresponding to the plurality of red (R) light emitting elements D. ing. Hereinafter, unless otherwise specified, a plurality of red (R) light emitting elements D shown will be described, but a plurality of green (G) light emitting elements D and a plurality of blue (B) light emitting elements D (not shown) will be described. Also, the same configuration as that adopted for the plurality of red (R) light emitting elements D is adopted.

In the display device 5, light emission composed of r rows × s columns of light emitting elements D (that is, r × s light emitting elements D) by a plurality of light emitting elements D provided in a matrix of m rows × n columns. A plurality of element groups 56 are configured. In the example of FIG. 19, a plurality of light emitting element groups 56 composed of four light emitting elements D for two rows × two columns are configured. Note that FIG. 19 shows four light emitting element groups 56_1 to 56_4 as a part of the plurality of light emitting element groups 56.

Specifically, the light emitting element group 56_1 is composed of four light emitting elements D1a to D1d from the first column to the second column in the first and second rows. Further, the light emitting element group 56_2 is composed of four light emitting elements D2a to D2d from the first column to the second column in the third to fourth rows. Further, the light emitting element group 56_3 is composed of four light emitting elements D3a to D3d from the third column to the fourth column in the first and second rows. Further, the light emitting element group 56_4 is composed of four light emitting elements D4a to D4d from the third column to the fourth column in the third to fourth rows.

Further, FIG. 19 shows pixel circuits 15_1 to 15_4 for driving each of the light emitting element groups 56_1 to 56_4 as a part of the plurality of pixel circuits 15.

The voltage control circuit 14 is provided between the light emitting element groups 56_1 to 56_4 and the ground voltage source GND which is a reference power source. In this embodiment, a case where the voltage control circuit 14 is provided in common for the light emitting element groups 56_1 to 56_4 will be described as an example.

More specifically, in the light emitting elements D1a to D1d constituting the light emitting element group 56_1, each anode is connected to the pixel circuit 15_1 via the node N_1, and each cathode has a voltage via the nodes Na to Nd. It is connected to the control circuit 14. Further, in the light emitting elements D2a to D2d constituting the light emitting element group 56_2, each anode is connected to the pixel circuit 15_2 via the node N_2, and each cathode is connected to the voltage control circuit 14 via the nodes Na to Nd. It is connected. Further, in the light emitting elements D3a to D3d constituting the light emitting element group 56_3, each anode is connected to the pixel circuit 15_3 via the node N_3, and each cathode is connected to the voltage control circuit 14 via the nodes Na to Nd. It is connected. Further, in the light emitting elements D4a to D4d constituting the light emitting element group 56_4, each anode is connected to the pixel circuit 15_4 via the node N_4, and each cathode is connected to the voltage control circuit 14 via the nodes Na to Nd. It is connected.

The voltage control circuit 14 is configured to be able to selectively supply the ground voltage GND to any of the nodes Na to Nd. The pixel circuits 15_1 to 15_4 transmit a constant current signal of the time division period according to the video signal D_1 to the nodes N_1 and N_2 in a state where the ground voltage GND is selectively supplied to any of the nodes Na to Nd. By supplying a constant current signal for a time division period corresponding to the video signal D_2 to the nodes N_3 and N_4, a plurality of (four in this example) light emitting elements provided in each light emitting element group 56_1 to 56_4 are emitted. Selectively emit light from any of the elements.

For example, the voltage control circuit 14 supplies the ground voltage GND to the node Na during the period of the first subfield among the four subfields constituting one field, so that each light emitting element group 56_1 to 56_1 The light emitting elements in the first row and the first column in 56_4 (that is, the light emitting elements on the upper left in each light emitting element group) D1a to D4a are made to emit light. Further, the voltage control circuit 14 supplies the ground voltage GND to the node Nb during the period of the second subfield, so that the light emitting elements in the second row and the first column in each light emitting element group 56_1 to 56_4 ( That is, the lower left light emitting elements) D1b to D4b in each light emitting element group are made to emit light. Further, the voltage control circuit 14 supplies the ground voltage GND to the node Nc during the period of the third subfield, so that the light emitting elements in the first row and the second column in each light emitting element group 56_1 to 56_4 ( That is, the upper right light emitting element) D1c to D4c in each light emitting element group is made to emit light. Further, the voltage control circuit 14 supplies the ground voltage GND to the node Nd during the period of the fourth subfield, so that the light emitting elements in the second row and the second column in each light emitting element group 56_1 to 56_4 ( That is, the lower right light emitting element) D1d to D4d in each light emitting element group is made to emit light.

Since the other configurations of the display device 5 are the same as those of the display device 1, the description thereof will be omitted.

(Timing chart)
FIG. 20 is a timing chart showing the operation of the display device 5. In the example of FIG. 20, one field is composed of four subfields, which is the same as the number of light emitting elements provided in each light emitting element group 56_1 to 56_4. For example, one field at times t71 to t83 includes a first subfield at times t71 to t74, a second subfield at times t74 to t77, a third subfield at times t77 to t80, and times t80 to t83. It is composed of the fourth subfield of. Hereinafter, a detailed description will be given.

First, as the video signals D_1 and D_2 for the light emitting elements D1a and D3a are output, the gate control signal G_1 temporarily rises (time t71), and subsequently, the video signals D_1 for the light emitting elements D2a and D4a. , D_2 is output, and the gate control signal G_2 temporarily rises (time t72). As a result, the respective video signals are supplied to the pixel circuits 15_1 to 15_4 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals to the pixel circuits 15_1 to 15_4 is completed (that is, when all of the gate control signals G_1 to G_4 are turned down), the voltage control circuit 14 supplies only the node Na among the nodes Na to Nd. The ground voltage GND is supplied (time t73 to t74).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Na, the constant current signals from the pixel circuits 15_1 to 15_4 start to be supplied to the nodes N_1 to N_4, respectively (time t73). Then, the constant current signal continues to be supplied to the nodes N_1 to N_1 during the time division period corresponding to each video signal (arbitrary range within the time t73 to t74). At this time, the nodes N_1 to N_14 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1a to D4a emit light in the time division period assigned to each (any range within the time t73 to t74).

After that, as the video signals D_1 and D_2 for the light emitting elements D1b and D3b are output, the gate control signal G_1 temporarily rises (time t74), and subsequently, the video signals D_1 for the light emitting elements D2b and D4b. , D_2 is output, and the gate control signal G_2 temporarily rises (time t75). As a result, the respective video signals are supplied to the pixel circuits 15_1 to 15_4 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals to the pixel circuits 15_1 to 15_4 is completed (that is, when all of the gate control signals G_1 to G_4 are turned down), the voltage control circuit 14 supplies only the node Nb among the nodes Na to Nd. The ground voltage GND is supplied (time t76 to t77).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nb, the constant current signals from the pixel circuits 15_1 to 15_4 start to be supplied to the nodes N_1 to N_4, respectively (time t76). Then, the constant current signal continues to be supplied to the nodes N_1 to N_1 during the time division period corresponding to each video signal (arbitrary range within the time t76 to t77). At this time, the nodes N_1 to N_14 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1b to D4b emit light in the time division period assigned to each (any range within the time t76 to t77).

After that, as the video signals D_1 and D_2 for the light emitting elements D1c and D3c are output, the gate control signal G_1 temporarily rises (time t77), and subsequently, the video signals D_1 for the light emitting elements D2c and D4c. , D_2 is output, and the gate control signal G_2 temporarily rises (time t78). As a result, the respective video signals are supplied to the pixel circuits 15_1 to 15_4 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of each video signal to the pixel circuits 15_1 to 15_4 is completed (that is, when all of the gate control signals G_1 to G_4 are turned down), the voltage control circuit 14 applies only to the node Nc among the nodes Na to Nd. The ground voltage GND is supplied (time t79 to t80).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nc, the constant current signals from the pixel circuits 15_1 to 15_4 start to be supplied to the nodes N_1 to N_4, respectively (time t79). Then, the constant current signal continues to be supplied to the nodes N_1 to N_1 during the time division period corresponding to each video signal (arbitrary range within the time t79 to t80). At this time, the nodes N_1 to N_14 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1c to D4c emit light in the time division period assigned to each (any range within the time t79 to t80).

After that, as the video signals D_1 and D_2 for the light emitting elements D1d and D3d are output, the gate control signal G_1 temporarily rises (time t80), and subsequently, the video signals D_1 for the light emitting elements D2d and D4d , D_2 is output, and the gate control signal G_2 temporarily rises (time t81). As a result, the respective video signals are supplied to the pixel circuits 15_1 to 15_4 (more specifically, the gate of the transistor TR21 of each pixel circuit).

When the supply of the respective video signals to the pixel circuits 15_1 to 15_4 is completed (that is, when all of the gate control signals G_1 to G_4 are turned down), the voltage control circuit 14 applies only to the node Nd among the nodes Na to Nd. And supplies the ground voltage GND (time t82 to t83).

When the voltage control circuit 14 starts supplying the ground voltage GND to the node Nd, the constant current signals from the pixel circuits 15_1 to 15_4 start to be supplied to the nodes N_1 to N_4, respectively (time t82). Then, the constant current signal continues to be supplied to the nodes N_1 to N_1 during the time division period corresponding to each video signal (arbitrary range within the time t82 to t83). At this time, the nodes N_1 to N_14 are maintained at the level of the LED operating voltage during the period during which the constant current signal is supplied (time division period).

As a result, the light emitting elements D1d to D4d emit light in the time division period assigned to each (any range within the time t82 to t83).

That is, in the example of FIG. 20, among the periods of the first to fourth subfields constituting one field, the first row and the first column (that is, that is, in each light emitting element group) in the period of the first subfield. The light emitting elements D1a to D4a (upper left) are made to emit light, and the light emitting elements D1b to D4b in the second row and the first column (that is, the lower left) in each light emitting element group are made to emit light during the period of the second subfield, and the third During the period of the subfield of, the first row and the second column (that is, the upper right) of the light emitting elements D1c to D4c in each light emitting element group are made to emit light, and during the period of the fourth subfield, two rows in each light emitting element group are emitted. The light emitting elements D1d to D4d of the eyes and the second row (that is, the lower right) are made to emit light.

Here, in the present embodiment, a pixel circuit (for example, pixel circuit 15_1) commonly provided for a plurality of light emitting elements (for example, light emitting elements D1a to D1d) includes a switch for switching the light emitting element to be light-emitting. Instead, the voltage control circuit 14 provided outside the panel 51 switches the light emitting element to be light-emitting by selectively supplying a reference voltage (ground voltage GND) to any of these plurality of light emitting elements. There is. As a result, the display device 5 does not need to provide a switch for switching the light emitting element to be light-emitting in each pixel circuit, so that the number of pixel circuits can be reduced without increasing the scale of each pixel circuit. ..

The light emitting elements D1a to D4a, D1b to D4b, D1c to D4c, and D1d to D4d commonly connected to the voltage control circuit 14 are all controlled to emit light at least once during the period of one field. Is preferable. As a result, it is possible to prevent the display data from being lost.

As described above, the display device 5 according to the present embodiment can exert the same effect as the display devices 3 and 4. In addition, each light emitting element may be replaced in the opposite direction as in the case of other embodiments.

In the present embodiment, the case where the common voltage control circuit 14 is provided for the four light emitting element groups 56_1 to 56_4 has been described as an example, but the present invention is not limited to this. A common voltage control circuit 14 may be provided for an arbitrary number of light emitting element groups 56.

Further, in the present embodiment, the case where the number of light emitting elements driven by each pixel circuit 15_1 to 15_4 is four has been described as an example, but the present invention is not limited to this. The number of light emitting elements driven by each pixel circuit 15_1 to 15_4 may be any number.

Further, in the present embodiment, the case where the plurality of light emitting elements D are all red (R) light emitting elements has been described as an example, but the present invention is not limited to this. The plurality of light emitting elements D may be green (G) light emitting elements, all may be blue (B) light emitting elements, or each of the three colors (RGB). It may be any light emitting element.

As described above, the display device according to the first to fifth embodiments includes a plurality of light emitting elements D, a pixel circuit 15 commonly provided for the plurality of light emitting elements D, and a plurality of light emitting elements D. It is provided between the reference voltage (ground voltage GND), and by selectively supplying the reference voltage to any one of the plurality of light emitting elements D, any one of the plurality of light emitting elements D is selectively emitted. It includes a voltage control circuit 14. As a result, in the display device according to the first to fifth embodiments, it is not necessary to provide a switch for switching the light emitting element D to be light-emitting in each pixel circuit, so that the pixels are not increased in scale of each pixel circuit. The number of circuits can be reduced. As a result, for example, even when the light emitting elements are highly integrated, the layout of the pixel circuit becomes easy.

In the above-described first to fifth embodiments, the case where the voltage control circuit 14 is provided in common for all the pixel circuits in the panels 11, 21, 31, 41 or 51 has been described as an example, but the present invention is limited to this. I can't. For example, the voltage control circuit 14 may be provided for each one pixel circuit in the panel, or may be provided for each of a plurality of pixel circuits connected to a common data line.

Some or all of the above embodiments may also be described, but not limited to:

(Appendix 1)
A plurality of light emitting elements arranged in a matrix of m (m is an integer of 2 or more) rows and n (n is an integer of 2 or more) columns.
Of the plurality of light emitting elements, each of the s (s is an arbitrary integer of 2 to n) light emitting elements group consisting of r (r is an arbitrary integer of 2 to m) light emitting elements in the same row is driven. With s pixel circuits
A reference voltage from the reference power source is selectively supplied to any of the r light emitting elements provided between the s light emitting element group and the reference power source and constituting each of the light emitting element groups. A voltage control circuit that selectively emits light from any of the r light emitting elements constituting each of the light emitting element groups.
A display device equipped with.

(Appendix 2)
A plurality of light emitting elements arranged in a matrix of m (m is an integer of 2 or more) rows and n (n is an integer of 2 or more) columns.
Of the plurality of light emitting elements, each of the r (r is an arbitrary integer of 2 to m) light emitting elements composed of s (s is an arbitrary integer of 2 to n) light emitting elements in the same row is driven. R pixel circuit and
A reference voltage from the reference power source is selectively supplied to any of the s light emitting elements provided between the r light emitting element group and the reference power source and constituting each of the light emitting element groups. A voltage control circuit that selectively emits light from any of the s light emitting elements constituting each of the light emitting element groups.
A display device equipped with.

(Appendix 3)
A plurality of light emitting elements arranged in a matrix of m (m is an integer of 2 or more) rows and n (n is an integer of 2 or more) columns.
Among the plurality of light emitting elements, a group of a plurality of light emitting elements composed of r × s light emitting elements in the r (r is an arbitrary integer of 2 to m) row and the s (s is an arbitrary integer of 2 to n) column. With multiple pixel circuits that drive each of
A reference voltage from the reference power source is selectively applied to any of the r × s light emitting elements provided between the plurality of light emitting element groups and the reference power source and constituting each of the light emitting element groups. A voltage control circuit that selectively emits light from any of the r × s light emitting elements constituting each of the light emitting element groups by supplying the light emitting elements.
A display device equipped with.

1,1a, 1b Display device 2,2a, 2b Display device 3 Display device 4 Display device 5 Display device 11 panel 12 Data driver 13 Gate driver 14 Voltage control circuit 21 panel 31 panel 41 panel 51 panel 15,15_1 to 15_p pixel circuit 15_1a, 15_1b Pixel circuit 16,16_1-16_p Light emitting element group 26,26_1 to 26_3 Light emitting element group 36,36_1 to 36___ Light emitting element group 46,46_1 to 46_4 Light emitting element group 56,56_1 to 56_1 Light emitting element group CS1, CS2 Condenser D1a ~ D1f light emitting element D2a to D2c light emitting element D3a to D3c light emitting element D4a to D4d light emitting element D_1 to D_4 data line G_1 to G_p line scanning line TR11, TR12 transistor TR21 to TR23 transistor

Claims (20)

With a plurality of first light emitting elements
A first pixel circuit that is commonly provided for the plurality of first light emitting elements and drives each of the plurality of first light emitting elements.
The plurality of first light emitting elements are provided between the plurality of first light emitting elements and the reference power source, and the reference voltage from the reference power source is selectively supplied to any one of the plurality of first light emitting elements. 1 A voltage control circuit that selectively emits light from any of the light emitting elements,
A display device equipped with. The plurality of first light emitting elements are provided in parallel between the first pixel circuit and the voltage control circuit.
The display device according to claim 1. The voltage control circuit is configured to emit light from each of the plurality of first light emitting elements during a period of a plurality of subfields constituting one field.
The display device according to claim 1 or 2. Each of the first light emitting elements is a light emitting diode in which the anode is connected to the first pixel circuit and the cathode is connected to the voltage control circuit.
The reference power source is a ground voltage source.
The display device according to any one of claims 1 to 3. Each of the first light emitting elements is a light emitting diode having a cathode connected to the first pixel circuit and an anode connected to the voltage control circuit.
The reference power source is a power supply voltage source.
The display device according to any one of claims 1 to 3. The plurality of first light emitting elements are
It contains at least one red light emitting element, one green light emitting element, and one blue light emitting element.
The display device according to any one of claims 1 to 5. The plurality of first light emitting elements are
All are light emitting elements of the same color,
The display device according to any one of claims 1 to 5. With multiple second light emitting elements
A second pixel circuit that is commonly provided for the plurality of second light emitting elements and drives each of the plurality of second light emitting elements.
With more
The voltage control circuit is further provided between the plurality of second light emitting elements and the reference power source, and selectively supplies the reference voltage to any one of the plurality of second light emitting elements. , It is configured to selectively emit light from any of the plurality of second light emitting elements.
The display device according to claim 1. The plurality of second light emitting elements are provided in parallel between the second pixel circuit and the voltage control circuit.
The display device according to claim 8. The voltage control circuit causes each of the plurality of first light emitting elements to emit light during a period of a plurality of subfields constituting one field, and also causes the plurality of second light emitting elements in parallel with the plurality of first light emitting elements. It is configured to emit light from each of the elements.
The display device according to claim 8 or 9. Each of the first light emitting elements is a light emitting diode in which the anode is connected to the first pixel circuit and the cathode is connected to the voltage control circuit.
Each of the second light emitting elements is a light emitting diode in which the anode is connected to the second pixel circuit and the cathode is connected to the voltage control circuit.
The reference power source is a ground voltage source.
The display device according to any one of claims 8 to 10. Each of the first light emitting elements is a light emitting diode having a cathode connected to the first pixel circuit and an anode connected to the voltage control circuit.
Each of the second light emitting elements is a light emitting diode having a cathode connected to the second pixel circuit and an anode connected to the voltage control circuit.
The reference power source is a power supply voltage source.
The display device according to any one of claims 8 to 10. The plurality of first light emitting elements are
It contains at least one red light emitting element, one green light emitting element, and one blue light emitting element.
The plurality of second light emitting elements
It contains at least one red light emitting element, one green light emitting element, and one blue light emitting element.
The display device according to any one of claims 8 to 12. The plurality of first light emitting elements are all light emitting elements of the same color.
The plurality of second light emitting elements are all light emitting elements of the same color.
The display device according to any one of claims 8 to 12. At least a plurality of light emitting elements arranged in a matrix of m (m is an integer of 2 or more) rows and n (n is an integer of 2 or more) columns are provided.
The plurality of first light emitting elements are r (r is an arbitrary integer of 2 to m) light emitting elements in the same row among the plurality of light emitting elements arranged in a matrix.
The display device according to any one of claims 1 to 7. At least a plurality of light emitting elements arranged in a matrix of m (m is an integer of 2 or more) rows and n (n is an integer of 2 or more) columns are provided.
The plurality of first light emitting elements are s (s is an arbitrary integer of 2 to n) light emitting elements in the same row among the plurality of light emitting elements arranged in a matrix.
The display device according to any one of claims 1 to 7. At least a plurality of light emitting elements arranged in a matrix of m (m is an integer of 2 or more) rows and n (n is an integer of 2 or more) columns are provided.
The plurality of first light emitting elements are r (r is an arbitrary integer of 2 to m) row and s (s is an arbitrary integer of 2 to n) columns among the plurality of light emitting elements arranged in a matrix. R × s light emitting elements of
The display device according to any one of claims 1 to 7. With a plurality of first light emitting elements
A first pixel circuit that is commonly provided for the plurality of first light emitting elements and drives each of the plurality of first light emitting elements.
A voltage control circuit provided between the plurality of first light emitting elements and a reference power supply, and
It is a control method of a display device equipped with
By selectively supplying the reference voltage from the reference power source to any of the plurality of first light emitting elements by the voltage control circuit, any one of the plurality of first light emitting elements is selectively emitted. Let,
Display device control method. The plurality of first light emitting elements are provided in parallel between the first pixel circuit and the voltage control circuit.
The control method of the display device according to claim 18. By selectively supplying the reference voltage to any one of the plurality of first light emitting elements by the voltage control circuit, the plurality of first light emitting elements are emitted during the period of the plurality of subfields constituting one field. Make each element emit light,
The method for controlling a display device according to claim 18 or 19.

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