JP2021120981A - Memory element, semiconductor device, and manufacturing method of semiconductor device - Google Patents

Abstract

To manufacture a ferroelectric memory having good characteristics while suppressing an increase in the number of steps in process steps of the ferroelectric memory.SOLUTION: A semiconductor region is provided on a semiconductor substrate. A memory element includes a side wall, a ferroelectric material portion, an upper electrode, and an embedded electrode. The side wall is formed in the semiconductor region. The ferroelectric material portion is formed inside the side wall. The upper electrode is formed on an upper part of the ferroelectric material portion. The embedded electrode is embedded inside the upper electrode.SELECTED DRAWING: Figure 2

Description

The present technology relates to a storage element. More specifically, the present invention relates to a storage element, a semiconductor device, and a method for manufacturing the semiconductor device using a ferroelectric material.

In recent years, attention has been paid to the development of non-volatile memory using a ferroelectric material. Ferroelectric memory is roughly classified into the following two types. One is a 1T (1 Transistor) type FeRAM (Ferroelectric Random Access Memory: ferroelectric RAM) in which a ferroelectric material is used for the gate oxide film of a CMOS (Complementary Metal Oxide Semiconductor) transistor (for example, Patent Document 1). reference.). The other is a 1T1C (1 Transistor 1 Capacitor) type FeRAM in which a ferroelectric capacitor is connected to the source or drain of the transistor portion (see, for example, Patent Document 2). The ferroelectric capacitor has a structure in which an upper electrode, a ferroelectric film, and a lower electrode are laminated.

Japanese Unexamined Patent Publication No. 2018-067664 Japanese Unexamined Patent Publication No. 2019-075470

In order to drive the above-mentioned two types of FeRAM, a circuit unit is required in addition to the memory array unit. Since the circuit unit is formed by CMOS logic transistors, there are problems such as an increase in the number of process steps and deterioration of characteristics due to thermal history in the formation process of each of the CMOS transistor and FeRAM. Further, in the case of a structure having both 1T type FeRAM and 1T1C type FeRAM, it is necessary to separate not only the CMOS transistor forming process but also 1T type FeRAM and 1T1C type FeRAM, so that the number of process steps is further increased and the characteristics. Deterioration becomes a problem.

This technology was created in view of such a situation, and aims to manufacture a ferroelectric memory having good characteristics while suppressing an increase in the number of process steps.

The present technology has been made to solve the above-mentioned problems, and the first aspect thereof is a semiconductor region provided on a semiconductor substrate, a sidewall formed in the semiconductor region, and the sidewall. It is a storage element including a ferroelectric material portion formed inside the semiconductor material portion, an upper electrode formed on the upper portion of the ferroelectric material portion, and an embedded electrode embedded inside the upper electrode. This brings about the action of forming a ferroelectric memory element having a damascene structure.

Further, on the first side surface, a lower electrode formed below the ferroelectric material portion may be further provided. This has the effect of forming a ferroelectric capacitor in the damascene structure.

Further, in this first aspect, it is desirable that the work function of the upper electrode is smaller than the work function of the lower electrode. It has the effect of lowering the write voltage.

Further, in this first aspect, the storage element may form a one-transistor type ferroelectric non-volatile memory. Further, a ferroelectric capacitor is further provided with a diffusion region obtained by ion implantation after the sidewall formation, and is connected to another transistor via the diffusion region to form a 1-transistor 1-capacitor type ferroelectric substance. A non-volatile memory may be formed.

Further, in the first aspect, the ferroelectric material portion may contain HfO2 (hafnia).

Further, the second aspect of the present technology is on the inside of the first semiconductor region provided on the semiconductor substrate, the first sidewall formed in the first semiconductor region, and the first sidewall. A first dielectric material portion to be formed, a first upper electrode formed on the upper portion of the first dielectric material portion, and a first embedding embedded inside the first upper electrode. A first strong dielectric non-volatile memory including electrodes, a second semiconductor region provided on the semiconductor substrate, a second sidewall formed in the second semiconductor region, and the second Embedded inside the second strong dielectric material portion formed inside the sidewall, the second upper electrode formed on the upper portion of the second strong dielectric material portion, and the second upper electrode. The second embedded electrode, the lower electrode formed under the second strong dielectric material portion, the diffusion region obtained by ion injection after the formation of the second sidewall, and the diffusion region. It is a semiconductor device including a second dielectric non-volatile memory including other transistors connected via the semiconductor, and a peripheral circuit including a transistor for accessing the first and second strong dielectric non-volatile memories. .. This has the effect of forming a semiconductor device on which a ferroelectric storage element having a damascene structure is formed.

Further, in the second aspect, the transistor of the peripheral circuit may have a gate-first structure having a thermal oxide film as an insulating film of the gate, and has a high dielectric film and a metal conductive film as the insulating film of the gate. It may have a gate-first structure, or may have a gate-last structure including a high-dielectric film and a metal conductive film as the insulating film of the gate.

Further, in the second aspect, the product-sum calculation is performed in the first ferroelectric non-volatile memory, and the product-sum calculation result and the product-sum calculation are used in the second ferroelectric non-volatile memory. A neuromorphic device may be configured to hold the weights to be used.

Further, the third aspect of the present technology is a step of forming a plurality of semiconductor regions on a semiconductor substrate, a step of forming sidewalls in each of the plurality of semiconductor regions, and a part of the plurality of semiconductor regions. A step of removing the inside of the sidewall, a step of forming a lower electrode on any of the inside of the removed sidewall, a step of forming a dielectric film on the inside of the removed sidewall, and the above. This is a method for manufacturing a semiconductor device including a step of forming an upper electrode on an upper part of a dielectric film and a step of forming an embedded electrode inside the upper electrode. This brings about the effect of manufacturing a semiconductor device in which a ferroelectric storage element is formed in a damascene structure.

Further, in the third aspect, a crystallization annealing step may be further provided after the step of forming the ferroelectric film.

Further, on the third side surface, a digging may be made in the lower electrode in the step of forming the lower electrode. This has the effect of preventing the upper electrode and the lower electrode from short-circuiting when the upper electrode is formed.

It is a figure which shows the whole structure example of the semiconductor device in embodiment of this technique. It is a figure which shows the example of the device structure of the semiconductor device in 1st Embodiment of this technique. It is a figure which shows an example of the voltage charge curve of the ferroelectric capacitor in embodiment of this technique. It is a figure which shows the circuit example of the memory array part 20 in embodiment of this technique. It is a figure which shows the example of the physical layout of the memory array part 20 in embodiment of this technique. It is a figure which shows the circuit example of the memory array part 30 in embodiment of this technique. It is a figure which shows the example of the physical layout of the memory array part 30 in embodiment of this technique. It is a 1st figure which shows an example of the manufacturing method of the semiconductor device in 1st Embodiment of this technique. It is a 2nd figure which shows an example of the manufacturing method of the semiconductor device in 1st Embodiment of this technique. FIG. 3 is a third diagram showing an example of a method for manufacturing a semiconductor device according to the first embodiment of the present technology. It is a figure which shows the example of the device structure of the semiconductor device in the 2nd Embodiment of this technique. It is a figure which shows an example of the manufacturing method of the semiconductor device in 2nd Embodiment of this technique. It is a figure which shows the example of the device structure of the semiconductor device in the 3rd Embodiment of this technique. FIG. 1 is a first diagram showing an example of a method for manufacturing a semiconductor device according to a third embodiment of the present technology. FIG. 2 is a second diagram showing an example of a method for manufacturing a semiconductor device according to a third embodiment of the present technology.

Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. First Embodiment (Example in the case where the insulating film of the transistor of the peripheral circuit has a gate-first structure including a thermal oxide film)
2. Second embodiment (example in the case where the insulating film of the transistor of the peripheral circuit has a gate first structure including a high dielectric film and a metal conductive film)
3. 3. Third Embodiment (Example in the case where the insulating film of the transistor of the peripheral circuit has a gate last structure including a high dielectric film and a metal conductive film)
4. Application example (example applied to neuromorphic devices)

<1. First Embodiment>
[Semiconductor device]
FIG. 1 is a diagram showing an overall configuration example of a semiconductor device according to an embodiment of the present technology.

The semiconductor device according to the embodiment of the present technology includes two types of memory array units 20 and 30 and a peripheral circuit unit 10. The memory array unit 20 is a 1T type FeRAM manufactured by a damascene process. The memory array unit 30 is a 1T1C type FeRAM having a ferroelectric capacitor manufactured by a damascene process. The peripheral circuit unit 10 is a CMOS transistor circuit for driving the memory array units 20 and 30.

FIG. 2 is a diagram showing an example of a device structure of a semiconductor device according to the first embodiment of the present technology. These device structures are provided in the semiconductor region on the semiconductor substrate.

A P-type transistor and an N-type transistor are usually used for the peripheral circuit unit 10, but only the N-type transistor is shown in the figure. In the peripheral circuit unit 10, each element is separated from other elements by an element separation layer 101 formed of a silicon oxide film or the like.

The transistor of the peripheral circuit unit 10 includes a gate oxide film 102 formed of a thermal oxide film or the like at the bottom of the gate. Further, a gate electrode 103 made of polysilicon or the like is provided on the upper part of the gate oxide film 102.

After the gate electrode 103 is formed, an N-type diffusion region (LDD: Lightly-Doped Drain) 104 obtained by ion implantation of P or AS is formed. Sidewalls 105 and 106 composed of a SiO2 film and a SiN film are formed on the upper part of the N-type diffusion region 104.

After the sidewalls 105 and 106 are formed, the N-type diffusion region (SD: Single Drain) 107 obtained by ion implantation of P or AS is formed. After the N-type diffusion region 107 is formed, a silicide region 108 made of Co or the like is formed on the N-type diffusion region 107 and the gate. A SiN film 109 is formed on the silicide region 108 as a contact stopper film.

Further, a contact plug 110 made of W or TiN film is formed and connected to a wiring layer 111 made of Ta or Cu.

The memory array unit 20 includes an element separation layer 201, an N-type diffusion region 204, sidewalls 205 and 206, an N-type diffusion region 207, a silicide region 208, and a SiN film 209, similarly to the peripheral circuit unit 10. Further, in the memory array unit 20, a salicide block film 212 formed of SiN or the like is provided under the SiN film 209. The salicide block film 212 is selectively provided in order to selectively perform silicide only in the N-type diffusion region 207 in the VDD step of the silicide region 208.

Further, in the memory array unit 20, instead of the gate oxide film 102 and the gate electrode 103 as in the peripheral circuit unit 10, the ferroelectric film 213, the upper electrode 214, and the embedded electrode are used as materials peculiar to the 1T type ferroelectric transistor. 215 is provided. The ferroelectric film 213 is a ferroelectric material composed of HfO2 (Hafnia film) having a size of about 10 nm formed by an ALD (Atomic Layer Deposition) device or the like. The ferroelectric film 213 is crystallized by a process flow described later. The upper electrode 214 is a TiN upper electrode of about 10 nm formed on the upper part of the ferroelectric film 213 by an ALD device or the like. The embedded electrode 215 is an embedded electrode formed by W or the like, which is formed by a PVD (Physical Vapor Deposition) device or the like.

The ferroelectric film 213, the upper electrode 214, and the embedded electrode 215 have a structure embedded inside the sidewall by a process flow described later, and are generally called a damascene structure. In the damascene structure, since the memory array portion 20 is formed after the crystallization annealing of the transistor and the salicide step, the ferroelectric film 213 can avoid the influence of those annealings, and the characteristic fluctuation is small. Further, since the sidewall 206 and the N-type diffusion region 207 are not affected by RIE (Reactive Ion Etching) when the memory array unit 20 is processed, the characteristics of the CMOS transistor of the peripheral circuit unit 10 are less likely to fluctuate.

In the memory array unit 30, a ferroelectric capacitor manufactured by a damascene process is connected to an N-type transistor via an N-type diffusion region 316 to form a 1T1C type FeRAM. The N-type transistor in the memory array unit 30 has the same structure as the transistor in the peripheral circuit unit 10 described above.

Further, the ferroelectric capacitor in the memory array unit 30 includes a salicide block film 312 formed in the same manner as the memory array unit 20. Further, in the ferroelectric capacitor, the N-type diffusion region 316 is expanded to the same size as the gate region.

Further, the ferroelectric capacitor in the memory array unit 30 includes a ferroelectric film 313, an upper electrode 314 and an embedded electrode 315, and further includes a lower electrode 317, similarly to the memory array unit 20. The lower electrode 317 is a TiN lower electrode of about 10 nm formed by an ALD device or the like. It is desirable that the work function of the material of the lower electrode 317 is higher than that of the material of the upper electrode 314. Further, it is desirable that the height of the lower electrode 317 from the Si surface is lower than that of the gate electrode, and the end surface is completely covered with the ferroelectric film 313. By adding the work function difference in this way, it is possible to reduce the write voltage when writing data to the memory array unit 30, as shown below.

[Work function]
FIG. 3 is a diagram showing an example of a voltage charge curve of a ferroelectric capacitor according to an embodiment of the present technology.

In the voltage charge curve of this ferroelectric capacitor, the vertical axis shows the charge Q stored in the ferroelectric capacitor, and the horizontal axis shows the voltage V between the plate voltage VPL and the bit voltage VBL. Therefore, the slope (Q / V) of this curve indicates the capacitance C of the ferroelectric capacitor.

In this embodiment, by making the work function of the upper electrode 314 smaller than the work function of the lower electrode 317, an internal electric field is generated in the ferroelectric film 313. As a result, the voltage shifts in the negative direction by the work function difference ΔX (= X2-X1) in the voltage direction from the normal voltage charge curve (hysteresis curve). Therefore, the maximum voltage of the voltage charge curve in this embodiment becomes "+ V-ΔX", and the voltage drops by ΔX. On the other hand, the minimum voltage becomes "-V-ΔX", and the voltage also drops by ΔX.

That is, in this embodiment, the maximum voltage of the voltage of the upper electrode 314 with reference to the lower electrode 317 is reduced by shifting the voltage charge curve in the negative direction by ΔX in the voltage direction.

As specific materials, for example, it is assumed that TiAlN is used for the lower electrode 317, TiN is used for the upper electrode 314, and the like.

[1T type FeRAM]
FIG. 4 is a diagram showing a circuit example of the memory array unit 20 according to the embodiment of the present technology. FIG. 5 is a diagram showing an example of the physical layout of the memory array unit 20 according to the embodiment of the present technology.

The memory array unit 20 is configured by arranging FeFETs (Ferroelectric Field-Effect Transistor) 200 of 1T type FeRAM in an array. In the FeFET 200, the gate is connected to the word line 226, the drain is connected to the bit line 225, and the source is connected to the source line 224. The source line 224 is shared by adjacent FeFETs 200.

The word line 226, the bit line 225, and the source line 224 are provided with a word line contact 221, a bit line contact 222, and a source line contact 223, respectively.

[1T1C type FeRAM]
FIG. 6 is a diagram showing a circuit example of the memory array unit 30 according to the embodiment of the present technology. FIG. 7 is a diagram showing an example of the physical layout of the memory array unit 30 according to the embodiment of the present technology.

The memory array unit 30 is configured by arranging a ferroelectric capacitor 300 of a 1T1C type FeRAM and an N type transistor 400 in an array. The gate of the N-type transistor 400 is connected to the word line 356, the drain is connected to the bit line 355, and the source is connected to one end of the ferroelectric capacitor 300. The other end of the ferroelectric capacitor 300 is connected to the plate line 357.

The word line 356 and the bit line 355 are provided with a word line contact 351 and a bit line contact 352, respectively.

The pattern of the ferroelectric capacitor is shown in the area of the pattern of the lower electrode 353. The pattern of the lower electrode 353 is formed independently between adjacent memory cells, and an appropriate distance is provided so as not to short-circuit with the pattern of other adjacent lower electrodes 353. Further, the larger the area of the pattern of the lower electrode 353, the more reliable the memory can be ensured, so that it is designed to be the maximum in the unit cell. As a result, the influence of the characteristic fluctuation of the memory array unit 20 described above is small, and good ferroelectric characteristics can be obtained.

[Production method]
8 to 10 are diagrams showing an example of a method for manufacturing a semiconductor device according to the first embodiment of the present technology.

From left to right, a schematic diagram of the device structure of the MPLS transistor and the NMOS transistor of the peripheral circuit unit 10, the 1T type FeRAM of the memory array unit 20, and the 1T1C type FeRAM of the memory array unit 30 is shown. It is assumed that the planer-type CMOS transistor forming step formed by the gate-first process is followed up to the activation annealing step of the SD region before salicide formation.

In a in the figure, a silicon nitride film (SiN) 511 is formed in order to form the salicide block films 212 and 312. At that time, patterning is performed by using, for example, dry etching so as to remove parts other than the dummy gates of the 1T type FeRAM and the 1T1C type FeRAM.

Next, cobalt, nickel and the like are formed into a film, and salicide annealing is performed at 400 to 800 degrees. At this time, since the dummy gate portions of the 1T type FeRAM and the 1T1C type FeRAM are covered with the silicon nitride film 511, they are not salicidal.

In b in the figure, a silicon nitride film 521 formed by a PVD device or the like is formed. Further, an oxide film 522 that functions as an interlayer insulating film is deposited.

In c in the figure, a CMP (Chemical Mechanical Polishing) operation is performed to flatten the step of the oxide film 522, and at that time, a silicon nitride film 521 having a lower polishing rate than the oxide film 522 is placed on the silicon gate. Due to its presence, polishing is stopped at the height of the gate.

In d in the figure, patterning is performed to selectively remove the dummy gate portion of the 1T type FeRAM and the silicon nitride film 521 on the dummy capacitor portion of the 1T1C type FeRAM (531). The patterning may be performed using a resist pattern, or a hard mask of an oxide film or the like may be used. Further, dry etching may be used for etching, or the hard mask of the oxide film may be first patterned and then the silicon nitride film 521 may be selectively removed by wet etching.

In e in the figure, the dummy gate portion of the 1T type FeRAM and the dummy capacitor portion of the 1T1C type FeRAM are removed. For removal, an alkaline chemical solution may be used, or dry etching may be used. Since the dummy gate portion of the 1T type FeRAM and the dummy capacitor portion of the 1T1C type FeRAM are not silicated, they can be easily removed.

In f in the figure, the lower electrode 317 of the ferroelectric capacitor portion of the 1T1C type FeRAM is patterned (541, 533).

In g in the figure, a recess (digging) of about 10 to 20 nm is inserted in the lower electrode 317 of the ferroelectric capacitor portion of the 1T1C type FeRAM. As a result, when the upper electrode 314 is formed in the subsequent process, it is possible to prevent a short circuit between the upper electrode 314 and the lower electrode 317. This recess can be formed without adding a new process by using the resist embedded in the capacitor portion used in f in the figure.

In h in the figure, the ferroelectric films 213 and 313, the upper electrodes 214 and 314, the crystallization annealing and the embedded electrodes 215 and 315 are formed (552 to 554). At that time, the gate electrode portion of the 1T type FeRAM and the ferroelectric capacitor portion of the 1T1C type FeRAM are formed at the same time. The ferroelectric films 213 and 313 are preferably based on HfO2 using an ALD device, and are preferably doped with Zr, Si, La, Nb, Al or the like. As the upper electrodes 214 and 314, for example, TiN or the like is assumed as described above. Crystallization annealing is preferably performed at an appropriate temperature depending on the ferroelectric material. For example, when a ferroelectric material obtained by doping HfO2 with Zr at a ratio of 1: 1 is formed, the crystallization annealing is performed at 400 to 600 degrees. Is desirable. The embedded electrodes 215 and 315 are preferably W, WSi, conductive Si doped with impurities, and the like. Further, the position of the crystallization annealing may be after the film formation of the embedded electrodes 215 and 315, or may be combined with the film formation temperature at the time of film formation of the embedded electrodes 215 and 315 and the thermal history of the subsequent process. On the other hand, the thermal history of crystallization annealing is added to the MOSFET transistors and NMOS transistors in the peripheral circuit section, but the thermal history of crystallization annealing is sufficiently smaller than that of activation annealing and salicide annealing in the SD region. , The effect on the characteristics is minor.

In i in the figure, the ferroelectric material formed in h in the figure is flattened by CMP. Similar to the flattening of the oxide film 522 described above, the silicon nitride film 521 functions as a stopper film. As described above, in the damascene structure, since the ferroelectric material is scraped off by CMP, damage to the ferroelectric films 213 and 313 can be avoided. Assuming that HfO2 is used as the ferroelectric material, there is a problem that HfO2 reacts with chlorine gas and is easily scraped, especially in chlorine-based dry etching. Therefore, a damascene structure that is not affected by such etching should be adopted. Is effective.

By such a procedure, it is possible to achieve both the device structures of the MOSFET transistor, the NMOS transistor, the 1T type FeRAM, and the 1T1C type FeRAM of the peripheral circuit unit 10 with a small increase in the number of process steps while reducing the characteristic fluctuation due to the thermal history. be.

As described above, according to the first embodiment of the present technology, a peripheral circuit having a gate-first structure in which the insulating film of the transistor is provided with a thermal oxide film, and a device structure including 1T type FeRAM and 1T1C type FeRAM are provided. This can be achieved with a small increase in the number of process steps while reducing characteristic fluctuations.

<2. Second Embodiment>
In the first embodiment described above, a gate-first structure is assumed in which the insulating film of the transistor of the peripheral circuit unit 10 includes a thermal oxide film, but in this second embodiment, the transistor of the peripheral circuit unit 10 is gated. It is assumed that the first structure is formed by the HKMG (High-K / Metal Gate) process.

[Semiconductor device]
FIG. 11 is a diagram showing an example of a device structure of a semiconductor device according to a second embodiment of the present technology.

Compared with the first embodiment described above, in the HKMG process, the thermal oxide film is a high-dielectric film 141 formed of HfO2 or the like. Further, a metal conductive film 142 or 143 for adjusting the work function is provided on the high dielectric film 141. This metal conductive film has a different work function for adjusting the threshold voltage of the NMOS transistor and the NMOS transistor, and a metal electrode such as TiAL is used in the NMOS and a metal electrode such as TiN is used in the NMOS.

[Production method]
FIG. 12 is a diagram showing an example of a method for manufacturing a semiconductor device according to a second embodiment of the present technology.

In the figure, a shows a step of selectively producing salicide block films 212 and 312 in the HKMG production process having a gate-first structure. Here, a dummy gate made of polysilicon is formed in the 1T type FeRAM. Further, in the 1T1C type dummy capacitor, a dummy capacitor made of polysilicon is formed on the lower electrode manufactured in the same step as the metal conductive film manufacturing step of the MIMO transistor.

Reference numeral b in the figure is a step of removing the dummy polysilicon.

In the figure, c is a step of embedding the ferroelectric film and the upper electrode film. Since it is the first embodiment described above, detailed description thereof will be omitted.

By such a procedure, it is possible to achieve both the device structures of the MOSFET transistor, the NMOS transistor, the 1T type FeRAM, and the 1T1C type FeRAM of the peripheral circuit unit 10 with a small increase in the number of process steps while reducing the characteristic fluctuation due to the thermal history. be.

As described above, according to the second embodiment of the present technology, the peripheral circuit having a gate-first structure in which the insulating film of the transistor includes a high dielectric film and a metal conductive film, a 1T type FeRAM, and a 1T1C type FeRAM. It is possible to realize a device structure including the above with a small increase in the number of process steps while reducing characteristic fluctuations.

<3. Third Embodiment>
In the second embodiment described above, it is assumed that the transistor of the peripheral circuit unit 10 is formed by the HKMG process having a gate-first structure, but in this third embodiment, the transistor of the peripheral circuit unit 10 has a gate last structure. It is assumed that it is formed by the HKMG process of. In the gate last structure, an ion implanter is applied to the portion from which the dummy gate has been removed, and then the gate is finally formed.

[Semiconductor device]
FIG. 13 is a diagram showing an example of a device structure of a semiconductor device according to a third embodiment of the present technology.

The device structure of the 1T type FeRAM of the memory array unit 20 and the 1T1C type FeRAM of the memory array unit 30 is the same as that of the first embodiment described above.

Compared with the first embodiment described above, in the HKMG process, the thermal oxide film is a high-dielectric film 151 formed of HfO2 or the like. Since this third embodiment is not affected by the activation annealing step of the SD region, a high-quality film with lower leakage than the high-dielectric film 141 of the second embodiment described above can be selected. .. Further, a metal conductive film 152 or 153 for adjusting the work function is provided on the high dielectric film 151. This metal conductive film has a different work function for adjusting the threshold voltage of the NMOS transistor and the NMOS transistor, and a metal electrode such as TiAL is used in the NMOS and a metal electrode such as TiN is used in the NMOS. Further, as the electrode 155, W, Wsi, Al, or the like is selected in order to reduce the resistance of the gate electrode.

[Production method]
14 and 15 are diagrams showing an example of a method for manufacturing a semiconductor device according to a third embodiment of the present technology.

In this third embodiment, the removal of the dummy gate is performed in two steps, that is, the peripheral circuit unit 10 and the memory array units 20 and 30.

In a in the figure, the dummy gate of the peripheral circuit unit 10 is selectively removed. At that time, dry etching may be performed using a photoresist, or wet etching may be performed using a hard mask such as SiN.

In b in the figure, the gate stack of the CMOS transistor section is embedded. Examples of the High-k material include a material based on HfO2 and doped with La, Nb, and Al. As the upper electrode, different electrodes are used for NMOS and NMOS. When they are made separately, they are made by patterning by photolithography and processing by dry etching.

In c in the figure, CMP polishing is performed in order to remove the deposited material on the surface and flatten it. Further, the dummy gate of the FeRAM section is selectively removed. Similar to a in the figure, dry etching may be performed using a photoresist, or wet etching may be performed using a hard mask such as SiN.

In d in the figure, the material of the FeRAM portion is embedded. Since this method is the same as the first and second embodiments described above, detailed description thereof will be omitted.

In e in the figure, CMP polishing is performed in order to remove the FeRAM material deposited on the surface and flatten it.

By such a procedure, it is possible to achieve both the device structures of the MOSFET transistor, the NMOS transistor, the 1T type FeRAM, and the 1T1C type FeRAM of the peripheral circuit unit 10 with a small increase in the number of process steps while reducing the characteristic fluctuation due to the thermal history. be.

As described above, according to the third embodiment of the present technology, the peripheral circuit having a gate last structure in which the insulating film of the transistor includes a high dielectric film and a metal conductive film, a 1T type FeRAM, and a 1T1C type FeRAM. It is possible to realize a device structure including the above with a small increase in the number of process steps while reducing characteristic fluctuations.

<4. Application example>
Examples of the device having the device structure of the MPLS transistor, the NMOS transistor, the 1T type FeRAM, and the 1T1C type FeRAM of the peripheral circuit unit 10 include a neuromorphic device for artificial intelligence. The neuromorphic device has an area for performing a product-sum operation, an area for buffering the operation result and the weight used for the product-sum operation, and a peripheral circuit area for controlling them.

Although the number of rewrites may be small in the area where the product-sum operation is performed, a 1T type FeRAM is suitable because a memory capable of non-destructive reading and a high array density is required. On the other hand, the buffer memory may be destructive read, but 1T1C type FeRAM is suitable because a memory having high reliability and high array density is required. CMOS peripheral circuits such as a driver and a readout circuit are required as circuits for operating these.

Therefore, the above-described embodiment is applied to the neuromorphic device, the product-sum calculation is performed in the 1T-type FeRAM of the memory array unit 20, and the product-sum calculation and the product-sum calculation are performed in the 1T1C-type FeRAM of the memory array unit 30. Hold the weight to do. This makes it possible to manufacture a neuromorphic device having a high array density with a small number of process steps.

As described above, according to the embodiment of the present technology, a device structure including a peripheral circuit, a 1T type FeRAM, and a 1T1C type FeRAM can be realized with a small increase in the number of process steps while reducing characteristic fluctuations. .. In addition, it is possible to reduce fluctuations in the characteristics of the ferroelectric substance due to SD region activation annealing in the CMOS process, and to manufacture a highly reliable ferroelectric memory. Further, it is possible to form a planar type peripheral logic circuit capable of reducing CMOS characteristic fluctuations due to ferroelectric crystallization annealing. In addition, plasma damage due to dry etching of the ferroelectric film can be reduced, and a highly reliable ferroelectric memory can be manufactured. Further, since the buffer area of the CMOS peripheral circuit portion and the memory array portion can be reduced, the chip as a semiconductor device can be miniaturized.

It should be noted that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the claims have a corresponding relationship with each other. Similarly, the matters specifying the invention within the scope of claims and the matters in the embodiment of the present technology having the same name have a corresponding relationship with each other. However, the present technology is not limited to the embodiment, and can be embodied by applying various modifications to the embodiment without departing from the gist thereof.

It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

The present technology can have the following configurations.
(1) A semiconductor region provided on a semiconductor substrate and
The sidewall formed in the semiconductor region and
The ferroelectric material portion formed inside the sidewall and
An upper electrode formed on the upper part of the ferroelectric material portion and
A storage element including an embedded electrode embedded inside the upper electrode.
(2) The storage element according to (1) above, further comprising a lower electrode formed below the ferroelectric material portion.
(3) The storage element according to (2), wherein the work function of the upper electrode is smaller than the work function of the lower electrode.
(4) A ferroelectric capacitor is further provided with a diffusion region obtained by ion implantation after the sidewall formation, and is connected to another transistor via the diffusion region to form a 1-transistor 1-capacitor type ferroelectric. The storage element according to (2) or (3) above, which forms a body non-volatile memory.
(5) The storage element according to (1) above, which forms a 1-transistor type ferroelectric non-volatile memory.
(6) The storage element according to any one of (1) to (5) above, wherein the ferroelectric material portion contains HfO2.
(7) A first semiconductor region provided on a semiconductor substrate, a first sidewall formed in the first semiconductor region, and a first ferroelectric formed inside the first sidewall. A first strength comprising a body material portion, a first upper electrode formed above the first ferroelectric material portion, and a first embedded electrode embedded inside the first upper electrode. Dielectric non-volatile memory and
A second semiconductor region provided on the semiconductor substrate, a second sidewall formed in the second semiconductor region, and a second dielectric material formed inside the second sidewall. A portion, a second upper electrode formed on the upper portion of the second dielectric material portion, a second embedded electrode embedded inside the second upper electrode, and the second dielectric material. A second dielectric having a lower electrode formed in the lower part of the material portion, a diffusion region obtained by ion injection after the formation of the second sidewall, and another transistor connected via the diffusion region. Body non-volatile memory and
A semiconductor device including peripheral circuits including transistors that access the first and second ferroelectric non-volatile memories.
(8) The semiconductor device according to (7) above, wherein the transistor of the peripheral circuit has a gate-first structure including a thermal oxide film as an insulating film of the gate.
(9) The semiconductor device according to (7) above, wherein the transistor of the peripheral circuit has a gate-first structure including a high dielectric film and a metal conductive film as an insulating film of the gate.
(10) The semiconductor device according to (7) above, wherein the transistor of the peripheral circuit has a gate last structure including a high dielectric film and a metal conductive film as an insulating film of the gate.
(11) A new product in which the product-sum operation is performed in the first ferroelectric non-volatile memory, and the result of the product-sum operation and the weight used in the product-sum operation are held in the second ferroelectric non-volatile memory. The semiconductor device according to any one of (7) to (10), which constitutes a lomorphic device.
(12) A step of forming a plurality of semiconductor regions on a semiconductor substrate and
A step of forming a sidewall in each of the plurality of semiconductor regions and
A step of removing the inside of the sidewall of a part of the plurality of semiconductor regions, and
A step of forming a lower electrode on any of the insides of the removed sidewalls,
The step of forming a ferroelectric film inside the removed sidewall and
The step of forming the upper electrode on the upper part of the ferroelectric film and
A method for manufacturing a semiconductor device, comprising a step of forming an embedded electrode inside the upper electrode.
(13) The method for manufacturing a semiconductor device according to (12) above, further comprising a crystallization annealing step after the step of forming the ferroelectric film.
(14) The method for manufacturing a semiconductor device according to (12) or (13), wherein the lower electrode is dug in the step of forming the lower electrode.

10 Peripheral circuit part 20 Memory array part (1T type FeRAM)
30 Memory array section (1T1C type FeRAM)
101, 201, 301 Element separation layer 102, 402 Gate oxide film 103, 403 Gate electrode 104, 204, 304, 404 N-type diffusion region (LDD: Lightly-Doped Drain)
105, 106, 205, 206, 305, 306, 405, 406 sidewalls 107, 207, 407 N-type diffusion region (SD: Single Drain)
108, 208, 408 VDD region 109, 209, 309, 409 SiN film 110, 210, 310, 410 Contact plugs 111, 211, 311, 411 Wiring layers 141, 151 High dielectric film 142, 143, 152, 153 Metal conductive Film 155, 215, 315 Embedded electrode 212, 312 Salicide block film 213, 313 Ferroelectric film 214, 314 Upper electrode 300 Ferroelectric capacitor 316 N-type diffusion region (SD)
317 Lower electrode 400 N-type transistor

Claims (14)

The semiconductor area provided on the semiconductor substrate and
The sidewall formed in the semiconductor region and
The ferroelectric material portion formed inside the sidewall and
An upper electrode formed on the upper part of the ferroelectric material portion and
A storage element including an embedded electrode embedded inside the upper electrode. The storage element according to claim 1, further comprising a lower electrode formed under the ferroelectric material portion. The storage element according to claim 2, wherein the work function of the upper electrode is smaller than the work function of the lower electrode. A ferroelectric capacitor is further provided with a diffusion region obtained by ion implantation after the sidewall formation, and is connected to another transistor via the diffusion region to be 1-transistor, 1-capacitor type ferroelectric non-volatile. The storage element according to claim 2, which forms a memory. The storage element according to claim 1, wherein the 1-transistor type ferroelectric non-volatile memory is formed. The storage element according to claim 1, wherein the ferroelectric material portion includes HfO2. A first semiconductor region provided on a semiconductor substrate, a first sidewall formed in the first semiconductor region, and a first ferroelectric material portion formed inside the first sidewall. A first ferroelectric non-volatile material having a first upper electrode formed on the upper part of the first ferroelectric material portion and a first embedded electrode embedded inside the first upper electrode. Sex memory and
A second semiconductor region provided on the semiconductor substrate, a second sidewall formed in the second semiconductor region, and a second dielectric material formed inside the second sidewall. A portion, a second upper electrode formed on the upper portion of the second dielectric material portion, a second embedded electrode embedded inside the second upper electrode, and the second dielectric material. A second dielectric having a lower electrode formed in the lower part of the material portion, a diffusion region obtained by ion injection after the formation of the second sidewall, and another transistor connected via the diffusion region. Body non-volatile memory and
A semiconductor device including peripheral circuits including transistors that access the first and second ferroelectric non-volatile memories. The semiconductor device according to claim 7, wherein the transistor of the peripheral circuit has a gate-first structure including a thermal oxide film as an insulating film of the gate. The semiconductor device according to claim 7, wherein the transistor of the peripheral circuit has a gate-first structure including a high dielectric film and a metal conductive film as an insulating film of the gate. The semiconductor device according to claim 7, wherein the transistor of the peripheral circuit has a gate last structure including a high dielectric film and a metal conductive film as an insulating film of the gate. A neuromorphic device that performs a product-sum operation in the first ferroelectric non-volatile memory and holds the result of the product-sum operation and the weight used in the product-sum operation in the second ferroelectric non-volatile memory. 7. The semiconductor device according to claim 7. The process of forming multiple semiconductor regions on a semiconductor substrate and
A step of forming a sidewall in each of the plurality of semiconductor regions and
A step of removing the inside of the sidewall of a part of the plurality of semiconductor regions, and
A step of forming a lower electrode on any of the insides of the removed sidewalls,
The step of forming a ferroelectric film inside the removed sidewall and
The step of forming the upper electrode on the upper part of the ferroelectric film and
A method for manufacturing a semiconductor device, comprising a step of forming an embedded electrode inside the upper electrode. The method for manufacturing a semiconductor device according to claim 12, further comprising a crystallization annealing step after the step of forming the ferroelectric film. The method for manufacturing a semiconductor device according to claim 12, wherein the lower electrode is dug in the step of forming the lower electrode.

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