JP2021105704A - Display device - Google Patents

Abstract

To reduce image retention in a display device.SOLUTION: A display device includes: a first polyimide layer 302; a first silicon oxide layer 303 formed in direct contact on the first polyimide layer; an amorphous silicon layer 304 formed in direct contact on the first silicon oxide layer; a second polyimide layer 305 formed in direct contact on the amorphous silicon layer; a plurality of light emitting elements 404 formed on the second polyimide layer; a transistor array for controlling light emission of the plurality of light emitting elements formed on the second polyimide layer; a transparent conductive layer 307 formed between the transistor array and the second polyimide layer; and a second silicon oxide layer 306 formed between the transparent conductive layer and the second polyimide layer in direct contact with each of the transparent conductive layer and the second polyimide layer.SELECTED DRAWING: Figure 4

Description

The present disclosure relates to a display device.

Since the OLED (Organic Light-Emitting Diode) element is a current-driven self-luminous element, it does not require a backlight, and has advantages such as low power consumption, a wide viewing angle, and a high contrast ratio. Further, since the flexible OLED display device using the organic EL device does not require a backlight, an ultra-thin and flexible flexible display device can be realized.

The substrate structure of a conventional flexible OLED display device has a structure in which a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are sequentially laminated on a polyimide film having a thickness of 10 um to 15 um, and a TFT (TFT) ( A Thin Film Transistor) array is formed.

JP-A-2017-216323 JP-A-2018-6671

A flexible OLED display device using a polyimide film as a substrate has a problem that image retention (reversible afterimage) is stronger than that of an OLED display device having a glass substrate.

The display device of one aspect of the present disclosure is in direct contact with the first polyimide layer, the first silicon oxide layer formed in direct contact with the first polyimide layer, and the first silicon oxide layer. The amorphous silicon layer formed in the above, the second polyimide layer formed in direct contact with the amorphous silicon layer, and the plurality of light emitting elements formed on the second polyimide layer. A transistor array formed on the second polyimide layer for controlling light emission of the plurality of light emitting elements, and a transparent conductive layer formed between the transistor array and the second polyimide layer. Includes a second silicon oxide layer formed between the transparent conductive layer and the second polyimide layer in direct contact with each of the transparent conductive layer and the second polyimide layer.

According to one aspect of the present disclosure, it is possible to prevent the laminated film constituting the display device from peeling off during manufacturing, or to reduce the image retention in the display device having improved bending resistance.

A configuration example of the OLED display device is schematically shown. A configuration example of a pixel circuit is shown. Another configuration example of the pixel circuit is shown. The comparative evaluation result of the characteristics of the TFT on the conventional flexible substrate and the TFT on the glass substrate is shown. The flexible substrate of the TFT substrate, the driving TFT and the OLED element, and the cross-sectional structure of the sealing structure portion are schematically shown. The manufacturing process of the backplane which is an example of the manufacturing method of an OLED display device is shown. The manufacturing process of the backplane which is an example of the manufacturing method of an OLED display device is shown. The cross section of the OLED display device of the comparative example is schematically shown. The cross section of the OLED display device including the transparent conductive layer of the embodiment is schematically shown.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the present embodiment is merely an example for realizing the present invention and does not limit the technical scope of the present invention. The same reference numerals are given to common configurations in each figure. In order to make the explanation easier to understand, the dimensions and shape of the illustrated object may be exaggerated.

The OLED (Organic Light-Emitting Diode) display device disclosed below includes a transparent conductive layer between a polyimide layer and a TFT (Thin Film Transistor) array. The transparent conductive layer can reduce the influence of the electric field due to the electric charge in the polyimide layer on the characteristics of the TFT, and can reduce the image retention. In addition, the transparent conductive layer can avoid the influence on the alignment in the subsequent process without patterning.

The OLED display device disclosed below further includes an adhesion improving layer between the transparent conductive layer and the polyimide layer. The adhesion improving layer can prevent the transparent conductive layer from peeling off from the polyimide layer. The features of this embodiment can be applied to a self-luminous display device different from the OLED display device.
[overall structure]

FIG. 1 schematically shows a configuration example of the OLED display device 10. The OLED display device 10 includes a TFT (Thin Film Transistor) substrate 100 on which an OLED element (light emitting element) is formed, and a sealing structure 200 for sealing the OLED element. A scanning driver 131, an emission driver 132, a protection circuit 133, a driver IC 134, and a demultiplexer 136 are arranged around a cathode electrode forming region 114 outside the display region 125 of the TFT substrate 100.

The driver IC 134 is connected to an external device via an FPC (Flexible Printed Circuit) 135. The scanning driver 131 drives the scanning lines of the TFT substrate 100. The emission driver 132 drives an emission control line to control light emission of each pixel. The protection circuit 133 prevents electrostatic destruction of the element on the TFT substrate. The driver IC 134 is mounted using, for example, an anisotropic conductive film (ACF).

The driver IC 134 supplies a power supply and a timing signal (control signal) to the scanning driver 131 and the emission driver 132. Further, the driver IC 134 supplies a power supply and a data signal to the demultiplexer 136.

The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d (d is an integer of 2 or more) data lines. The demultiplexer 136 drives the data line d times the number of output pins of the driver IC 134 by switching the output destination data line of the data signal from the driver IC 134 d times within the scanning period.
[Circuit configuration]

On the TFT substrate 100, a plurality of pixel circuits for controlling the currents supplied to the anode electrodes of the plurality of sub-pixels are formed. FIG. 2A shows a configuration example of a pixel circuit. Each pixel circuit includes a drive transistor T1, a selection transistor T2, an emission transistor T3, and a holding capacitance C1. The pixel circuit controls the light emission of the OLED element E1. The transistor is a TFT.

The selection transistor T2 is a switch that selects a sub-pixel. The selection transistor T2 is a p-channel type TFT, and the gate terminal is connected to the scanning line 106. The source terminal is connected to the data line 105. The drain terminal is connected to the gate terminal of the drive transistor T1.

The drive transistor T1 is a transistor (drive TFT) for driving the OLED element E1. The drive transistor T1 is a p-channel type TFT, and its gate terminal is connected to the drain terminal of the selection transistor T2. The source terminal of the drive transistor T1 is connected to the power supply line 108 (Vdd). The drain terminal is connected to the source terminal of the emission transistor T3. A holding capacitance C1 is formed between the gate terminal and the source terminal of the drive transistor T1.

The emission transistor T3 is a switch that controls the supply and stop of the drive current to the OLED element E1. The emission transistor T3 is a p-channel type TFT, and the gate terminal is connected to the emission control line 107. The source terminal of the emission transistor T3 is connected to the drain terminal of the drive transistor T1. The drain terminal of the emission transistor T3 is connected to the OLED element E1.

Next, the operation of the pixel circuit will be described. The scanning driver 131 outputs a selection pulse to the scanning line 106 to turn on the selection transistor T2. The data voltage supplied from the driver IC 134 via the data line 105 is stored in the holding capacity C1. The holding capacity C1 holds the stored voltage throughout one frame period. The conductance of the drive transistor T1 changes in an analog manner depending on the holding voltage, and the drive transistor T1 supplies the forward bias current corresponding to the emission gradation to the OLED element E1.

The emission transistor T3 is located on the drive current supply path. The emission driver 132 outputs a control signal to the emission control line 107 to control the on / off of the emission transistor T3. When the emission transistor T3 is on, the drive current is supplied to the OLED element E1. When the emission transistor T3 is in the off state, this supply is stopped. By controlling the on / off of the emission transistor T3, the lighting period (duty ratio) within one field cycle can be controlled.

FIG. 2B shows another configuration example of the pixel circuit. The pixel circuit has a reset transistor T4 instead of the emission transistor T3 of FIG. 2A. The reset transistor T4 controls the electrical connection between the reference voltage supply line 110 and the anode of the OLED element E1. This control is performed by supplying a reset control signal from the reset control line 109 to the gate of the reset transistor T4.

The reset transistor T4 can be used for various purposes. The reset transistor T4 may be used, for example, for the purpose of temporarily resetting the anode electrode of the OLED element E1 to a voltage sufficiently low below the black signal level in order to suppress crosstalk due to a leak current between the OLED elements E1. ..

In addition, the reset transistor T4 may be used for the purpose of measuring the characteristics of the drive transistor T1. For example, if the bias condition is selected so that the drive transistor T1 operates in the saturation region and the reset transistor T4 operates in the linear region, and the current flowing from the power supply line 108 (Vdd) to the reference voltage supply line 110 (Vref) is measured, the drive transistor T1 is driven. The voltage / current conversion characteristics of the transistor T1 can be accurately measured. If a data signal that compensates for the difference in the voltage / current conversion characteristics of the drive transistor T1 between the sub-pixels is generated by an external circuit, a highly uniform display image can be realized.

On the other hand, if the drive transistor T1 is turned off, the reset transistor T4 is operated in the linear region, and the voltage that causes the OLED element E1 to emit light is applied from the reference voltage supply line 110, the voltage and current characteristics of the OLED element E1 can be accurately measured. can do. For example, even if the OLED element E1 is deteriorated due to long-term use, a long life can be realized by generating a data signal compensating for the amount of deterioration in an external circuit.

The pixel circuits of FIGS. 2A and 2B are examples, and the pixel circuits may have other circuit configurations. Although the pixel circuits of FIGS. 2A and 2B use p-channel TFTs, the pixel circuits may use n-channel TFTs.
[Image retention]

The substrate structure of a conventional flexible OLED display device has a structure in which a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are sequentially laminated on a polyimide film having a thickness of 10 um to 15 um, and a TFT (TFT) ( A Thin Film Transistor) array is formed.

A flexible OLED display device that uses a polyimide film as a substrate has a stronger image retention (reversible afterimage) than an OLED display device that uses a glass substrate. FIG. 3 shows a comparative evaluation result of the characteristics of the TFT on the conventional flexible substrate and the TFT on the glass substrate.

In the graph shown in FIG. 3, line 251 shows the time change of the drive current when the data signal for displaying white is given to the TFT on the glass substrate and then the data signal for displaying gray is given. Line 252 shows the time change of the drive current when the data signal for displaying black is given to the TFT on the glass substrate and then the data signal for displaying gray is given.

The drive current exhibits a transient response characteristic (overshoot) with respect to a sudden change in the signal. Specifically, when switching from white to gray, as shown in line 251 the current value becomes slightly smaller than the target current value, gradually increases with time, and approaches the target current value. On the other hand, when the current value is switched from black to gray, as shown in line 252, the current value becomes slightly larger than the target current value and gradually decreases with time to approach the target current value. If the changes in the current values of the lines 251 and 252 converge in a short time and become the same value, no afterimage can be seen. However, in reality, it takes a considerable amount of time for the drive currents 251 and 252 to converge to the same value, and the difference 253 causes an afterimage.

Further, in the graph shown in FIG. 3, line 255 is the time of the drive current when the data signal for displaying white is given to the TFT on the flexible substrate (polyimide substrate) and then the data signal for displaying gray is given. Show change. Line 256 shows the time change of the drive current when the data signal for displaying black is given to the TFT on the flexible substrate and then the data signal for displaying gray is given. The difference 257 between the drive currents 255 and 256 causes an afterimage.

According to the results of comparative evaluation of the characteristics of the TFT on the conventional flexible substrate and the TFT on the glass substrate, the drive currents 251 and 252 flowing through the TFT on the glass substrate are current transients that are almost symmetrical with respect to the time axis direction. It shows the characteristics. However, the drive currents 255 and 256 flowing through the TFT on the flexible substrate lack symmetry. That is, when the TFT on the flexible substrate is driven, a current drift that is not seen in the TFT on the glass substrate occurs. It was found that the TFT continued to apply the bias, and this current drift was superimposed on the symmetric current transient characteristics inherent in the TFT, resulting in worsening the image retention.

The current flowing through the TFT on the flexible substrate in this way exhibits instability that worsens image retention. Since the TFT on the glass substrate does not show such instability, it makes sense to think that this instability is caused by the electrical bias stress caused by the polyimide film when driving the TFT. That is, the fact that the electric field from the polyimide film reaches the channel portion of the TFT and changes the characteristics of the TFT is the main cause of deterioration of image retention.

Therefore, when driving the TFT, it is effective to arrange an electrostatic shield that electrically separates the TFT and the polyimide film in order to prevent the influence of the TFT driving on the polyimide film.

Hereinafter, the structure of the flexible OLED display device that prevents the electric field from the polyimide film to the channel portion of the TFT by the electrostatic shield will be described. Moreover, the manufacturing method (process condition) of the OLED display device having the structure will be described.
[Structure of OLED display device]

The structure of the OLED display device will be described below. The outline of the structure of the pixel circuit and the light emitting element will be described. FIG. 4 schematically shows the cross-sectional structure of the flexible substrate of the TFT substrate 100, the driving TFT and the OLED element, and the sealing structure portion 200. In the following description, the top and bottom indicate the top and bottom in the drawing.

The OLED display device includes a TFT substrate 100 and a sealing structure portion 200. The TFT substrate 100 includes a flexible substrate, a pixel circuit (TFT array) configured on the flexible substrate, and an OLED element. The pixel circuit and the OLED element are configured between the flexible substrate and the sealing structure portion 200.

The flexible substrate includes a polyimide layer (first polyimide layer) 302, a silicon oxide layer (first silicon oxide layer, SiOx layer) 303, an amorphous silicon layer (a-Si layer) 304, and a polyimide layer (second) from the lower layer. Polyimide layer) 305 is included. The silicon oxide layer 303 is formed in direct contact with the polyimide layer 302. The amorphous silicon layer 304 is formed in direct contact with the silicon oxide layer 303. The polyimide layer 305 is formed in direct contact with the amorphous silicon layer 304.

The TFT substrate 100 has a silicon oxide layer (second silicon oxide layer) 306, a transparent conductive layer 307, and a silicon oxide layer (fourth silicon oxide layer) 308 on a flexible substrate (polymethyl layer 305) from the bottom. , A silicon nitride layer (SiNx layer) 309, and a silicon oxide layer (third silicon oxide layer) 310.

A pixel circuit (TFT array) and an OLED element are formed on the silicon oxide layer 310. As described above, when the flexible substrate contains a plurality of polyimide layers 302 and 305, it is possible to obtain a base layer for forming polysilicon having good characteristics as described later.

Further, it is known that the polyimide layer contains water and diffuses into the layer on which the TFT is formed to deteriorate the TFT characteristics. The lower polyimide layer 302 can reduce the water content contained in the upper polyimide layer 305 and suppress the deterioration of the TFT characteristics. In one example, the thickness of the lower polyimide layer 302 is thicker than that of the upper polyimide layer 305. As a result, the moisture contained in the upper polyimide layer 305 can be reduced, and the influence of the moisture on the TFT array can be reduced more effectively.

In a flexible laminated film composed of a plurality of films as in this example, it is very important to consider the adhesion between the films. If adhesion is not taken into consideration, the film will peel off during manufacturing, and bending resistance cannot be ensured.

The silicon oxide layer 303 and the amorphous silicon layer 304 improve the adhesion between the two polyimide layers 302 and 305. The silicon oxide layer 303 has high adhesion to the polyimide layer 302 directly below, and the amorphous silicon layer 304 has high adhesion to the silicon oxide layer 303 directly below and the polyimide layer 305 directly above. The silicon oxide layer 303 and the amorphous silicon layer 304 can prevent the upper polyimide layer 305 from peeling off from the lower polyimide layer 302.

A transparent conductive layer 307 is formed between the polyimide layer 305 and the pixel circuit. From the viewpoint of film adhesion and bending resistance, the film thickness of the transparent conductive layer 307 is, for example, 50 nm or less. The transparent conductive layer 307 reduces the influence of the electric charge present on the polyimide layer 305 or 302 on the TFT in the pixel circuit. Since the transparent conductive layer 307 is transparent, it is possible to avoid the influence on the mask alignment in the manufacturing process described later. The transparent conductive layer 307 is formed so as to cover the entire surface of the polyimide layer 305. As a result, the electric field from the polyimide layer 305 can be suppressed more effectively, and as will be described later, patterning in the manufacturing process becomes unnecessary.

In this embodiment, the transparent conductive layer 307 is used between the polyimide layer 305 and the pixel circuit, but the transparent conductive layer 307 does not have to be completely transparent, and the conductive film is not affected by the reflected light at the time of mask alignment. It should be. For example, a thin amorphous silicon film has conductivity that functions as a shielding effect, but has weak reflected light and does not affect mask alignment, and has good adhesion to an insulating film, so that it can be sufficiently applied.

The transparent conductive layer 307 is in a state where a ground potential is applied or it is electrically floated. The ground potential can be effectively suppressed by the transparent conductive layer 307 due to the influence of the electric field generated between the TFT and the polyimide film. Even in the electrically floating state, the transparent conductive layer 307 has a sufficient capacity in an area overwhelmingly larger than the element area of the TFT, so that it electrically gives a ground potential. You can get the same shielding effect as the case. The transparent conductive layer 307 of this example can simplify the configuration of the OLED display device.

The transparent conductive layer 307 is formed of, for example, an amorphous oxide such as ITO and IZO. Due to its high conductivity (low resistance), ITO can effectively suppress the electric field due to the electric charge in the polyimide. IZO can improve the bending resistance of the OLED display device.

The silicon oxide layer 306 is formed between the polyimide layer 305 and the transparent conductive layer 307 in direct contact with them. The silicon oxide layer 306 covers the entire surface of the polyimide layer 305. The silicon oxide layer 306 can improve the adhesion of the transparent conductive layer 307 to the polyimide layer 305.

The silicon oxide layer 308 is formed in direct contact with the transparent conductive layer 307. The silicon oxide layer 308 is a barrier layer against moisture and oxygen for the OLED element while improving the adhesion between the transparent conductive layer 307 and the silicon nitride layer 309. The silicon nitride layer 309 is formed in direct contact with the silicon oxide layer 308. Since the silicon nitride layer 309 also acts as a barrier layer, it is possible to effectively suppress the intrusion of moisture from the polyimide layer 305 into the layer of the OLED element.

The silicon oxide layer 310 is formed in direct contact with the silicon nitride layer 309. The silicon oxide layer 310 allows for the good properties of the polysilicon that will be formed thereafter. As described above, the silicon oxide layer 306 on the lower layer side is a barrier layer against moisture and oxygen, and its thickness is thicker than that of the silicon oxide layer 310 on the upper layer side.

The OLED element is formed on the flexible substrate including the plurality of layers. The OLED element includes a lower electrode (for example, an anode electrode 408), an upper electrode (for example, a cathode electrode 402), and an organic light emitting multilayer film 404. An organic light emitting multilayer film 404 is arranged between the cathode electrode 402 and the anode electrode 408. The plurality of anode electrodes 408 are arranged on the same surface (for example, on the flattening film 421), and one organic light emitting multilayer film 404 is arranged on one anode electrode 408. In the example of FIG. 4, the cathode electrode 402 of one sub-pixel is a part of a continuous conductor film.

FIG. 4 is an example of a top emission type (OLED element) pixel structure. In the top-emission type pixel structure, the cathode electrode 402 common to a plurality of pixels is arranged on the side where light is emitted (upper side of the drawing). The cathode electrode 402 has a shape that covers the entire surface of the display area 125. In the top emission type pixel structure, the anode electrode 408 reflects light and the cathode electrode 402 has light transmission. As a result, the light from the organic light emitting multilayer film 404 is emitted toward the sealing structure portion 200.

Compared to the bottom emission type, which extracts light to the polyimide layer 305 side, the top emission type does not require a transmission region for light extraction to be provided in the pixel region, so a light emitting portion is also formed on the pixel circuit and wiring. It has a high degree of freedom in the layout of the pixel circuit.

The bottom emission type pixel structure has a transparent anode electrode and a reflective cathode electrode, and emits light to the outside through a flexible substrate. Further, a transparent display device can be realized by forming both the anode electrode and the cathode electrode with a light-transmitting material. The flexible substrate structure of the present disclosure can be applied to any type of OLED display device among these, and further can be applied to a display device including a light emitting element different from the OLED.

Sub-pixels generally display either red, green, or blue in a full-color OLED display device. One main pixel is composed of red, green, and blue sub-pixels. The pixel circuit including the plurality of thin film transistors controls the light emission of the corresponding OLED element. The OLED element is composed of an anode electrode which is a lower electrode, an organic light emitting layer, and a cathode electrode which is an upper electrode.

Each OLED display device has a plurality of pixel circuits (TFT arrays) including a plurality of switches. Each of the plurality of pixel circuits is formed between the silicon oxide layer 310 and the anode electrode 408, and controls the current supplied to each of the plurality of anode electrodes 408. The drive TFT shown in FIG. 4 has a top gate structure. Other TFTs also have a top gate structure.

The polysilicon layer is present in direct contact on the silicon oxide layer 310. In the polysilicon layer, a channel 415 that brings about the transistor characteristics of the TFT exists at a position where the gate electrode 157 is formed later. At both ends, there are source / drain regions 416 and 417 doped with high-concentration impurities to electrically connect to the upper wiring layer.

An LDD (Lightly Doped Drain) doped with a low concentration of impurities may be formed between the channel 415 and the source / drain regions 416 and 417. The LDD is not shown because it is complicated. A gate electrode 414 is formed on the polysilicon layer via a gate insulating film 423. An interlayer insulating film 422 is formed on the layer of the gate electrode 414.

In the display region 125, source / drain electrodes 410 and 412 are formed on the interlayer insulating film 422. The source / drain electrodes 410 and 412 are formed of, for example, a refractory metal or an alloy thereof. The source / drain electrodes 410 and 421 are connected to the source / drain regions 416 and 417 of the polysilicon layer via contact holes 411 and 413 formed in the interlayer insulating film 422 and the gate insulating film 423.

An insulating organic flattening film 421 is formed on the source / drain electrodes 410 and 412. An anode electrode 408 is formed on the flattening film 421. The anode electrode 408 is connected to the source / drain electrode 412 via the contact hole 409 of the flattening film 421. The TFT of the pixel circuit is formed below the anode electrode 408.

The anode electrode 408 is composed of, for example, a central reflective metal layer and a transparent conductive layer sandwiching the reflective metal layer. The anode electrode 408 has, for example, an ITO / Ag / ITO structure or an IZO / Ag / IZO structure. Although IZO has a higher resistance than ITO, it can improve the bending resistance of the OLED display device.

An insulating pixel definition layer (Pixel Defining Layer: PDL) 407 that separates the OLED element is formed on the anode electrode 408. The OLED element is formed in the opening 406 of the pixel definition layer 407.

An organic light emitting multilayer film 404 is formed on the anode electrode 408. The organic light emitting multilayer film 404 is attached to the pixel definition layer 407 at the opening 406 of the pixel definition layer 407 and its surroundings. An organic light emitting material is formed for each of the RGB colors, and an organic light emitting multilayer film 404 is formed on the anode electrode 408.

To form the organic light emitting multilayer film 404, a metal mask is used to deposit an organic light emitting material at a position corresponding to a pixel. The organic light emitting multilayer film 404 is composed of, for example, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer from the lower layer side. The laminated structure of the organic light emitting multilayer film 404 is determined by design.

A cathode electrode 402 is formed on the organic light emitting multilayer film 404. The cathode electrode 402 is an electrode having light transmission property. The cathode electrode 402 transmits a part of visible light from the organic light emitting multilayer film 404. The layer of the cathode electrode 402 is formed by depositing, for example, a metal such as Al or Mg or an alloy containing these metals. When the resistance of the cathode electrode 402 is high and the uniformity of emission brightness is impaired, an auxiliary electrode layer is further added with a material for forming a transparent electrode such as ITO, IZO, ZnO or In2O3.

The laminated film of the anode electrode 408, the organic light emitting multilayer film 404, and the cathode electrode 402 formed in the opening 406 of the pixel definition layer 407 constitutes the OLED element. The sealing structure portion 200 is formed in direct contact with the cathode electrode 402. The sealing structure portion (thin film sealing portion) 200 includes an inorganic insulating material (for example, SiNx, AlOx) layer 401, an organic flattening film 431, and an inorganic insulating material (for example, SiNx, AlOx) layer 432 from the lower layer. The inorganic insulators 401 and 432 are lower and upper passivation layers for improving reliability, respectively.

A touch screen film 433, a λ / 4 plate 434, a polarizing plate 435, and a resin cover lens 436 are laminated on the sealing structure portion 200 from the lower layer. The λ / 4 plate 434 and the polarizing plate 435 suppress the reflection of light incident from the outside. The laminated structure of the OLED display device described with reference to FIG. 4 is an example, and a part of the layers shown in FIG. 4 may be omitted, or a layer not shown in FIG. 4 may be added. ..
[Production method]

Next, an example of a method for manufacturing an OLED display device will be described. 5A and 5B show a backplane manufacturing process of an example of a method of manufacturing an OLED display device. The following description is for explaining the features of the present embodiment, and a part of the steps in the actual manufacturing of the OLED display device is omitted.

As shown in FIG. 5A, first, in the manufacture of the OLED display device, a polyimide layer 302 (first polyimide layer) is formed on a glass substrate (insulating support substrate) (not shown) by, for example, coating and heat treatment (1st polyimide layer). S11). The polyimide layer 302 has a thickness capable of obtaining the strength required for a flexible substrate.

Next, silicon oxide is deposited on the polyimide layer 302 by, for example, a CVD (Chemical Vapor Deposition) method to form a silicon oxide layer 303 (S13). Next, amorphous silicon is deposited on the silicon oxide layer 303 by, for example, a CVD method to form the amorphous silicon layer 304 (S15).

As described above, the silicon oxide layer 303 is an adhesion improving layer to the polyimide layer 302, and the amorphous silicon layer 304 is an adhesion improving layer to the polyimide layer 305 (second polyimide layer). These layers prevent the polyimide layer 305 from peeling off from the polyimide layer 302.

Next, the polyimide layer 305 is formed on the amorphous silicon layer 304 by, for example, coating and heat treatment (S17). As described above, the polyimide layer 305 is formed thinner than the lower polyimide layer 302 in order to reduce the influence of the electric field caused by the moisture in the polyimide layer 305 on the TFT characteristics. Next, a silicon oxide layer 306 is formed on the polyimide layer 305 by, for example, a CVD method (S19). As described above, the silicon oxide layer 306 improves the adhesion of the upper transparent conductive layer 307 to the polyimide layer 305.

Next, a transparent conductor is deposited on the silicon oxide layer 306 by, for example, a sputtering method to form the transparent conductive layer 307 (S21). As the transparent conductive layer 307, for example, a metal oxide thin film such as an ITO layer or an IZO layer, or a semiconductor film such as amorphous silicon formed by a CVD method can be used.

Generally, an amorphous silicon thin film has high electrical resistance and is not suitable for use as a conductive wiring layer, but has a sufficiently low resistance value for use as a shield layer. According to the experiments of the applicants, it was confirmed that the film thickness of 10 Å or more has the effect of blocking the influence of the electric charge in the polyimide layers 305 and 302 on the TFT. It was also confirmed that if the film thickness is 50 Å or less, sufficient transmittance can be secured as in the case of the metal thin film.

More preferably, if the film thickness of the 304 amorphous silicon layer is set to 50 Å or less, it can be sufficiently used for applications using transmitted light such as a transparent display and a camera under a panel. Since the transparent conductive layer 307 is transparent, unlike the reflective metal layer, it is possible to avoid the influence on the mask alignment in the subsequent process without performing patterning.

In addition, since patterning is not performed, the entire substrate is covered with a conductive layer from the lower side of the TFT element, exerting the same effect as an apparent ground electrode against static electricity generated during the TFT manufacturing process, and defects caused by static electricity. Contributes to the reduction of characteristics and the suppression of characteristic variations caused by static electricity.

Further, even after the cathode is formed, the TFT element circuit is covered from below with an area larger than the area of the cathode, so that the same effect as electrostatically shielding the entire module can be obtained. For example, the mounting terminal of a driver IC using an anisotropic conductive film is easily affected by static electricity because it is out of the area of the cathode electrode, but with this structure, the floating conductive film covers the entire terminal area. Therefore, the influence of static electricity in the mounting process can be suppressed.

Next, silicon oxide is deposited on the transparent conductive layer 307 by, for example, a CVD method to form a silicon oxide layer 308 (S23). The silicon oxide layer 308 is a barrier layer against moisture and oxygen, and is formed with a thickness that appropriately functions as a barrier layer with an emphasis on throughput, and the thickness thereof is larger than the thickness of the upper silicon oxide layer 310.

Next, the silicon nitride layer 309, the silicon oxide layer 310, and the amorphous silicon layer are continuously formed on the silicon oxide layer 308 under the film forming conditions in which the film quality is emphasized, for example, by the CVD method (S25). These three layers are formed at a lower deposition rate than the silicon oxide layer 308 in order to obtain good film quality. Further, the amorphous silicon layer is heated to perform dehydrogenation treatment. Normally, this heat treatment is often carried out in air at 400 ° C. or higher, but in this example, it is carried out in an inert gas (for example, nitrogen gas) atmosphere at 400 ° C. or lower, for example. As a result, good TFT characteristics can be ensured while suppressing deterioration of the film quality due to crystallization of the transparent conductive layer 307 formed in the step prior to the TFT.

A flexible substrate is formed by the above steps. Each step described with reference to FIG. 5A is completed without patterning each layer.

Next, as shown in FIG. 5B, in the manufacture of the OLED display device, amorphous silicon is crystallized by ELA (Excimer Laser Annealing) to form a polysilicon film (S27), and the polysilicon layer is patterned (S29). ). ELA is carried out under conditions that emphasize the uniformity of TFT characteristics (energy considerably lower than the maximum mobility condition).

Next, impurities are doped in a high concentration in the source / drain regions 416 and 417 for connecting to the source / drain electrodes 410 and 412 to reduce the resistance (S31). Similarly low resistance polysilicon can also be used to connect elements within the display area 125.

Next, for example, a silicon oxide is deposited on the polysilicon layer containing the channel 415 by, for example, a CVD method to form a gate insulating film 423 (S33). Further, for example, a metal material is deposited by a sputtering method and patterning is performed to form a metal layer including a gate electrode 414 (S35). In addition to the gate electrode 414, the metal layer can include, for example, a holding capacitance electrode, a scanning line 106, an emission control line 107, and the like.

As the metal layer, for example, a single layer is formed by one substance selected from the group consisting of Mo, W, Nb, MoW, MoNb, Al, Nd, Ti, Cu, Cu alloy, Al alloy, Ag and Ag alloy. Alternatively, a two-layer structure of one or more materials selected from the low resistance substances Mo, Cu, Al or Ag may be formed in order to reduce the wiring resistance, or a multi-layer structure of one or more may be formed.

Next, for example, silicon nitride is deposited by a CVD method to form an interlayer insulating film 422 (S37). Next, annealing treatment is performed to activate and hydrogenate the polysilicon layer (S39). Hydrogenation utilizes hydrogen in the interlayer insulating film 422 formed of silicon nitride. This annealing treatment is carried out, for example, at 400 ° C. or lower in an atmosphere of an inert gas (for example, nitrogen gas). As a result, good TFT characteristics can be ensured while suppressing crystallization of the transparent conductive layer 307. The annealing treatment S39 may be performed after the subsequent contact hole forming S41.

Next, the interlayer insulating film 422 and the gate insulating film 423 are anisotropically etched to open a contact hole (S41). Contact holes 411 and 413 connecting the source / drain electrodes 410 and 412 and the source / drain regions 416 and 417 are formed in the interlayer insulating film 422 and the gate insulating film 423.

Next, for example, by a sputtering method, a conductive film such as Ti / Al / Ti is deposited and patterned to form a metal layer. The metal layer includes the inside of the source / drain electrodes 410,412 and the contact holes 411,413. In addition to this, a data line 105, a power supply line 108, and the like may be formed in the same layer.

Next, a photosensitive organic material is deposited to form a flattening film 421 (S45). A contact hole 409 for connecting the source / drain electrode 412 of the TFT and the anode electrode 408 is opened by exposure and development.

Next, the anode electrode 408 is formed on the flattening film 421 on which the contact hole 409 is formed (S47). The anode electrode 408 is, for example, a transparent conductive layer such as ITO, IZO, ZnO, In2O3, a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or an alloy containing these metals. It includes three layers, a reflective layer and the above-mentioned transparent conductive layer. The IZO transparent conductive layer can improve the bending resistance of the OLED display device. The three-layer configuration of the anode electrode 408 is an example and may be two layers. The anode electrode 408 is connected to the source / drain electrode 412 via the contact hole 409.

Next, for example, a photosensitive organic resin film is deposited by spin coating, and patterning is performed to form the pixel definition layer 407 (S49). An opening 406 is formed in the pixel definition layer 407 by patterning, and the anode electrode 408 of each sub-pixel is exposed at the bottom of the formed opening 406. The pixel definition layer 407 separates the light emitting regions of each sub-pixel.

By the above steps, a flexible substrate and a pixel circuit (TFT array) on the flexible substrate can be formed. The step after forming the pixel definition layer 407 can be carried out by the conventional technique, and the description thereof will be omitted.

In the manufacture of the OLED display device, the temperature in the dehydrogenation treatment S25 or the hydrogenation and activation treatment of the polysilicon layer by heating the amorphous silicon layer is the highest. Therefore, by performing these processes at, for example, 400 ° C. or lower, the entire process in the manufacture of the OLED display device is carried out at 400 ° C. or lower. Further, a holding capacity can be formed by adding a step of forming a metal layer and an interlayer insulating film to the above steps.

As described above, the OLED display device of the present embodiment includes a transparent conductive layer between the polyimide layer and the TFT array (pixel circuit). This makes it possible to further stabilize the operation of the TFT and suppress image retention by reducing the influence of the electric field contained in the polyimide layer on the TFT. Further, since the transparent conductive layer is arranged on the lower side of the TFT array, it becomes easy to adjust so that the neutral plane matches the TFT layer. The term "neutral plane" as used herein means a virtual surface in which stress is not applied at the time of bending in the cross section of the flexible laminated body.

FIG. 6A schematically shows a cross section of the OLED display device of the comparative example. The TFT layer 501 is sandwiched between the upper multilayer film 503 and the lower multilayer film 505. In the flexible OLED display device, the neutral plane 507 is located on the upper multilayer film 503 above the TFT layer 501 because the multifunctional layers are concentrated on the upper multilayer film 503.

FIG. 6B schematically shows a cross section of an OLED display device including the transparent conductive layer 519 of the present embodiment. The TFT layer 511 is sandwiched between the upper multilayer film 513 and the lower multilayer film 515. The transparent conductive layer 519 is included in the lower multilayer film 515. As described above, since the transparent conductive layer 519 exists below the TFT layer 511, it becomes easy to adjust so that the neutral plane 517 coincides with the TFT layer 511. Therefore, the bending reliability of the OLED display device can be improved.

Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments. A person skilled in the art can easily change, add, or convert each element of the above embodiment within the scope of the present disclosure. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

10 Display device, 100 TFT substrate, 200 sealed structure, 302 polyimide layer, 303 silicon oxide layer, 304 amorphous silicon layer, 305 polyimide layer, 306 silicon oxide layer, 307 transparent conductive layer, 308 silicon oxide layer, 309 Silicon nitride layer, 310 Silicon oxide layer, 401 Inorganic insulating layer, 402 cathode electrode, 404 organic light emitting thin film transistor, 406 aperture, 407 pixel definition layer, 408 anode electrode, 409 contact hole, 410, 412 source / drain Electrodes, 411, 413 Contact Holes, 414 Gate Electrodes, 415 Channels, 416, 417 Source / Drain Regions, 421 Flattening Films, 422 Interlayer Insulating Films, 423 Gate Insulating Films, 431 Flattening Films, 432 Inorganic Insulation Layers, 433 Touch screen film, 434 λ / 4 plate, 435 polarizing plate, 436 resin cover lens, 501, 511 TFT layer, 503, 513 upper multilayer film, 505, 515 lower multilayer film, 507, 517 neutral plane, 519 transparent conductive layer

Claims (16)

With the first polyimide layer
A first silicon oxide layer formed in direct contact with the first polyimide layer,
An amorphous silicon layer formed in direct contact with the first silicon oxide layer,
A second polyimide layer formed in direct contact with the amorphous silicon layer and
A plurality of light emitting elements formed on the second polyimide layer and
A transistor array formed on the second polyimide layer for controlling the light emission of the plurality of light emitting elements, and a transistor array.
A transparent conductive layer formed between the transistor array and the second polyimide layer,
A second silicon oxide layer formed between the transparent conductive layer and the second polyimide layer in direct contact with each of the transparent conductive layer and the second polyimide layer.
Display device including. The display device according to claim 1.
The second silicon oxide layer and the transparent conductive layer cover the entire surface of the second polyimide layer.
Display device. The display device according to claim 1.
The transparent conductive layer is electrically floating,
Display device. The display device according to claim 1.
The transparent conductive layer is an ITO layer or an IZO layer.
Display device. The display device according to claim 1.
The transparent conductive layer is made of amorphous silicon.
Display device. The display device according to claim 5.
The thickness of the transparent conductive layer is 10 Å or more and 50 Å or less.
Display device. The display device according to claim 6.
The sum of the thicknesses of the amorphous silicon layer and the transparent conductive layer is 50 Å or less.
Display device. The display device according to claim 1.
The transistor array is composed of a top-gate polysilicon thin film transistor.
Display device. The display device according to claim 1.
The transparent conductive layer is an IZO layer.
The anode electrodes of the plurality of light emitting elements include two IZO layers and a reflective metal layer between the two IZO layers.
Display device. The display device according to claim 1.
The polysilicon layer of the transistor array and
A third silicon oxide layer formed between the polysilicon layer and the transparent conductive layer,
A silicon nitride layer formed between the polysilicon layer and the third silicon oxide layer,
A fourth silicon oxide layer formed between the polysilicon layer and the silicon nitride layer and in direct contact with the polysilicon layer is further included.
Display device. The display device according to claim 1.
The second polyimide layer is thinner than the first polyimide layer.
Display device. It is a manufacturing method of display devices.
In the first step of forming the first silicon oxide layer directly on the first polyimide layer,
In the second step of forming the amorphous silicon layer directly on the first silicon oxide layer,
In the third step of forming the second polyimide layer directly on the amorphous silicon layer,
In the fourth step of forming the second silicon oxide layer directly on the second polyimide layer,
The fifth step of forming the transparent conductive layer directly on the second silicon oxide layer, and
The sixth step of forming a transistor array for controlling the light emission of a plurality of light emitting elements on the second silicon oxide layer.
A method of manufacturing a display device, including. The method for manufacturing a display device according to claim 12.
The fourth step is completed without depositing silicon oxide to form the second silicon oxide layer and patterning the second silicon oxide layer.
The fifth step is completed without depositing the transparent conductor to form the transparent conductive layer and patterning the transparent conductive layer.
How to manufacture a display device. The method for manufacturing a display device according to claim 12.
The sixth step comprises heat treatment in an inert gas atmosphere after the polysilicon layer is doped with impurities.
How to manufacture a display device. The method for manufacturing a display device according to claim 12.
The sixth step includes heat treatment in an inert gas atmosphere after the second amorphous silicon layer is formed and before the second amorphous silicon layer is transformed into a polysilicon layer by laser annealing.
How to manufacture a display device. The method for manufacturing a display device according to claim 12.
The first step to the sixth step are executed under a temperature condition of 400 ° or less.
How to manufacture a display device.

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