JP2021101591A - Electronic controller - Google Patents

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JP2021101591A
JP2021101591A JP2019232385A JP2019232385A JP2021101591A JP 2021101591 A JP2021101591 A JP 2021101591A JP 2019232385 A JP2019232385 A JP 2019232385A JP 2019232385 A JP2019232385 A JP 2019232385A JP 2021101591 A JP2021101591 A JP 2021101591A
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control device
electronic control
load
arithmetic unit
loads
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JP7385462B2 (en
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真也 永村
Shinya Nagamura
真也 永村
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Hitachi Astemo Ltd
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Abstract

To provide an electronic controller to be connected with a plurality of loads, the electronic controller applicable irrespective of conditions such as a current value of a load to be driven and a drive period, capable of suppressing the generation of electromagnetic noise, providing high reliability.SOLUTION: An electronic controller for controlling the driving of a plurality of loads comprises a plurality of load drive circuits connected with each of the plurality of loads independently of one another and an arithmetic unit for controlling operation timing of each of the plurality of load drive circuits. The arithmetic unit controls so that operation start timing of each of the plurality of load drive circuits overlaps each other.SELECTED DRAWING: Figure 1

Description

本発明は、電子制御装置の構成とその制御に係り、特に、高信頼性が要求される車載用電子制御装置に適用して有効な技術に関する。 The present invention relates to the configuration of an electronic control device and its control, and particularly relates to a technique effective when applied to an in-vehicle electronic control device that requires high reliability.

車両に搭載されるモータ等の負荷は、車両の燃費向上や発熱低減を目的として、一般的にPWM（Pulse Width Modulation）制御によるオンオフ制御が行われている。しかし、１台の電子制御装置で複数の負荷を同時にPWM制御する場合には、PWM信号のオンオフのタイミングが各負荷で重なる場合があり、電源から瞬間的に大きな電流が持ち出されることになる。この大きな電流変化が電磁ノイズ発生の主な要因となり、車両内の周辺に設置されている電子機器の誤動作を引き起こすという問題が発生する。 The load of the motor or the like mounted on the vehicle is generally on / off controlled by PWM (Pulse Width Modulation) control for the purpose of improving the fuel efficiency of the vehicle and reducing heat generation. However, when a single electronic control device is used for PWM control of a plurality of loads at the same time, the on / off timings of the PWM signals may overlap with each load, and a large current is instantaneously taken out from the power supply. This large change in current becomes a main factor in the generation of electromagnetic noise, which causes a problem of causing malfunction of electronic devices installed in the periphery of the vehicle.

この問題を解決する手段として、例えば下記特許文献１のような技術が知られている。特許文献１では、負荷の駆動状態に関係なく電源から持ち出される電流を均一化することのできるPWM制御装置を提供している。 As a means for solving this problem, for example, a technique such as the following Patent Document 1 is known. Patent Document 1 provides a PWM control device capable of equalizing the current taken out from the power supply regardless of the driving state of the load.

特許文献１の制御装置は、PWM信号の周期を駆動している負荷数で等分し、この等分した時間を遅れ時間として設定し、各負荷を駆動するPWM信号を遅れ時間ずつシフトさせてMOSFETを制御する。これにより、バッテリから持ち出される電流に大きな変化が生じることを防止でき、電磁ノイズの発生を抑制できる。 The control device of Patent Document 1 divides the period of the PWM signal equally by the number of loads driving the PWM signal, sets the equally divided time as the delay time, and shifts the PWM signal driving each load by the delay time. Control the MOSFET. As a result, it is possible to prevent a large change in the current taken out from the battery, and it is possible to suppress the generation of electromagnetic noise.

特開２０１４−３５７２１号公報Japanese Unexamined Patent Publication No. 2014-35721

ところで、近年、自動車の燃費向上に向けたエンジンのダウンサイジング化や環境規制への対応を目的にした排気再循環システムなど様々な取り組みが実施されている。これに伴い、電子制御装置が制御するモータ負荷の数が増加している。そのため、モータ負荷の動作により発生する電磁ノイズを小さくし、電磁ノイズによる周辺機器への影響を減らす必要がある。 By the way, in recent years, various efforts have been made such as downsizing of the engine for improving the fuel efficiency of automobiles and an exhaust gas recirculation system for the purpose of complying with environmental regulations. Along with this, the number of motor loads controlled by the electronic control device is increasing. Therefore, it is necessary to reduce the electromagnetic noise generated by the operation of the motor load and reduce the influence of the electromagnetic noise on peripheral devices.

上記特許文献１のように、負荷の駆動タイミングをPWM信号の周期を駆動している負荷数で等分し、この等分した時間を遅れ時間として設定し、各負荷を駆動するPWM信号を遅れ時間ずつシフトさせてMOSFETを動作させることで、バッテリから持ち出される電流に大きな変化が生じることを防止でき、電磁ノイズの発生を抑制する方法は存在しているが、動作させる負荷の駆動周期やデューティ比は同一であり、従来技術と同一条件のアプリケーションのみでしか使用できないという問題があった。 As in Patent Document 1, the load drive timing is equally divided by the number of loads driving the PWM signal cycle, the equally divided time is set as the delay time, and the PWM signal driving each load is delayed. By operating the MOSFET by shifting it by time, it is possible to prevent a large change in the current taken out from the battery, and there is a method to suppress the generation of electromagnetic noise, but the drive cycle and duty of the load to be operated The ratio is the same, and there is a problem that it can be used only in applications under the same conditions as the prior art.

そこで、本発明の目的は、複数の負荷が接続される電子制御装置において、駆動する負荷の電流値や駆動周期などの条件に依らず適用可能であり、なおかつ、電磁ノイズの発生を抑制可能な信頼性の高い電子制御装置とその制御方法を提供することにある。 Therefore, an object of the present invention can be applied to an electronic control device to which a plurality of loads are connected regardless of conditions such as the current value of the load to be driven and the drive cycle, and can suppress the generation of electromagnetic noise. An object of the present invention is to provide a highly reliable electronic control device and its control method.

上記課題を解決するために、本発明は、複数の負荷を駆動制御する電子制御装置であって、前記複数の負荷の各々に互いに独立して接続される複数の負荷駆動回路と、前記複数の負荷駆動回路の各々の動作タイミングを制御する演算装置と、を備え、前記演算装置は、前記複数の負荷駆動回路の各々の動作開始タイミングが重ならないように制御することを特徴とする。 In order to solve the above problems, the present invention is an electronic control device that drives and controls a plurality of loads, and includes a plurality of load drive circuits that are independently connected to each of the plurality of loads, and the plurality of load drive circuits. A calculation device for controlling the operation timing of each of the load drive circuits is provided, and the calculation device is characterized in that the operation start timings of the plurality of load drive circuits are controlled so as not to overlap each other.

また、本発明は、複数の負荷を駆動制御する電子制御装置であって、前記複数の負荷に接続される負荷駆動回路と、前記負荷駆動回路の動作タイミングを制御する演算装置と、を備え、前記負荷駆動回路は、前記複数の負荷の各々に互いに独立して接続される複数のHブリッジ回路を有し、前記演算装置は、前記複数のHブリッジ回路の各々の動作開始タイミングが重ならないように制御することを特徴とする。 Further, the present invention is an electronic control device that drives and controls a plurality of loads, and includes a load drive circuit connected to the plurality of loads and an arithmetic unit that controls the operation timing of the load drive circuit. The load drive circuit has a plurality of H-bridge circuits that are independently connected to each of the plurality of loads, and the arithmetic unit does not overlap the operation start timings of the plurality of H-bridge circuits. It is characterized by controlling to.

本発明によれば、複数の負荷が接続される電子制御装置において、駆動する負荷の電流値や駆動周期などの条件に依らず適用可能であり、なおかつ、電磁ノイズの発生を抑制可能な信頼性の高い電子制御装置とその制御方法を実現することができる。 According to the present invention, in an electronic control device in which a plurality of loads are connected, the reliability is applicable regardless of conditions such as the current value and the drive cycle of the load to be driven, and the generation of electromagnetic noise can be suppressed. It is possible to realize a high-performance electronic control device and its control method.

上記した以外の課題、構成及び効果は、以下の実施形態の説明により明らかにされる。 Issues, configurations and effects other than those described above will be clarified by the description of the following embodiments.

本発明の実施例１に係る電子制御装置の概略構成を示す機能ブロック図である。It is a functional block diagram which shows the schematic structure of the electronic control apparatus which concerns on Example 1 of this invention. モータ負荷と駆動回路の組合せ数ｎがｎ＝３の場合の駆動回路の動作波形を示す図である。It is a figure which shows the operation waveform of the drive circuit when the combination number n of a motor load and a drive circuit is n = 3. 本発明の実施例２に係る電子制御装置の概略構成を示すブロック図である。It is a block diagram which shows the schematic structure of the electronic control apparatus which concerns on Example 2 of this invention.

以下、図面を用いて本発明の実施例を説明する。なお、各図面において同一の構成については同一の符号を付し、重複する部分についてはその詳細な説明は省略する。 Hereinafter, examples of the present invention will be described with reference to the drawings. In each drawing, the same components are designated by the same reference numerals, and the detailed description of overlapping portions will be omitted.

図１及び図２を参照して、本発明の実施例１の電子制御装置とその制御方法について説明する。図１は、本実施例の電子制御装置１００の概略構成を示す機能ブロック図である。図２は、図１の電子制御装置１００に搭載されている駆動回路１〜３の動作波形を示すタイミングチャートであり、モータ負荷と駆動回路の組合せ数ｎがｎ＝３の場合を示している。 An electronic control device according to a first embodiment of the present invention and a control method thereof will be described with reference to FIGS. 1 and 2. FIG. 1 is a functional block diagram showing a schematic configuration of the electronic control device 100 of this embodiment. FIG. 2 is a timing chart showing the operation waveforms of the drive circuits 1 to 3 mounted on the electronic control device 100 of FIG. 1, and shows a case where the number of combinations n of the motor load and the drive circuit is n = 3. ..

本実施例の電子制御装置１００は、車両に搭載され、当該車両が備える電気機器を制御するための制御演算を実行する車載用電子制御装置である。 The electronic control device 100 of this embodiment is an in-vehicle electronic control device that is mounted on a vehicle and executes a control calculation for controlling an electric device included in the vehicle.

電子制御装置１００は、図１に示すように、データの演算処理を行う演算装置１０、演算装置１０から出力される駆動指令信号に基づいてモータ負荷（Ｍ−１〜Ｍ−ｎ）を駆動する駆動回路（２０−１〜２０−ｎ）、演算装置１０と駆動回路（２０−１〜２０−ｎ）間の通信を行うシリアル通信ライン（１１−１〜１１−ｎ）と信号配線（１２−１〜１２−ｎ）と（１３−１〜１３−ｎ）を有する。 As shown in FIG. 1, the electronic control device 100 drives a motor load (M-1 to Mn) based on an arithmetic unit 10 that performs data arithmetic processing and a drive command signal output from the arithmetic unit 10. Drive circuit (20-1 to 20-n), serial communication line (11-1 to 11-n) for communication between arithmetic unit 10 and drive circuit (20-1 to 20-n), and signal wiring (12-). It has 1-12-n) and (13-1 to 13-n).

駆動回路（２０−１〜２０−ｎ）は、コンデンサ３０が並列に接続されているバッテリ４０からバッテリライン４１を経由して電源が供給され、モータ負荷（Ｍ−１〜Ｍ−ｎ）を駆動する。 In the drive circuit (20-1 to 20-n), power is supplied from the battery 40 to which the capacitor 30 is connected in parallel via the battery line 41 to drive the motor load (M-1 to Mn). To do.

電子制御装置１００は、例えば中央演算ユニット（CPU）や、RAM、ROM、ハードディスク等の記憶手段からなる一体型のコンピュータとして構成することができる。 The electronic control device 100 can be configured as an integrated computer including, for example, a central processing unit (CPU) and storage means such as RAM, ROM, and a hard disk.

そして、車載用の電子制御装置１００は、例えばエンジンの各気筒の吸排気流量を制御するために、駆動回路（２０−１〜２０−ｎ）を通じてモータ負荷（Ｍ−１〜Ｍ−ｎ）の動作を制御する駆動信号を生成する役割を担っている。 Then, the in-vehicle electronic control device 100 determines the motor load (M-1 to Mn) through the drive circuit (20-1 to 20-n) in order to control the intake / exhaust flow rate of each cylinder of the engine, for example. It plays a role in generating a drive signal that controls the operation.

駆動回路（２０−１〜２０−ｎ）の各々は、ここではそれぞれ４個のトランジスタから構成され（図示せず）、モータ負荷（Ｍ−１〜Ｍ−ｎ）は、弁開時に一方向へ通電し、弁閉時に反対方向へ通電するHブリッジ回路（図示せず）が採用されている。駆動回路（２０−１〜２０−ｎ）によりそれぞれのモータ負荷（Ｍ−１〜Ｍ−ｎ）がPWM制御される。 Each of the drive circuits (20-1 to 20-n) is here composed of four transistors (not shown), and the motor load (M-1 to Mn) is unidirectional when the valve is opened. An H-bridge circuit (not shown) that energizes and energizes in the opposite direction when the valve is closed is adopted. Each motor load (M-1 to Mn) is PWM controlled by the drive circuit (20-1 to 20-n).

次に、図１のモータ負荷が３つの例を用いて、本発明の駆動開始タイミングについて説明する。説明するにあたり、３つのモータ負荷について、駆動周波数とデューティ比、負荷の電流値を仮定する。モータ負荷Ｍ−１の駆動周波数をｆとし、モータ負荷Ｍ−２の駆動周波数を３ｆ、モータ負荷Ｍ−３の駆動周波数を５ｆとする。また、デューティ比はそれぞれ５０％、負荷の電流値をモータ負荷Ｍ−１は１A、モータ負荷Ｍ−２は２A、モータ負荷Ｍ−３は３Aとして説明する。 Next, the drive start timing of the present invention will be described with reference to an example in which the motor load of FIG. 1 is three. In the explanation, the drive frequency, the duty ratio, and the current value of the load are assumed for the three motor loads. The drive frequency of the motor load M-1 is f, the drive frequency of the motor load M-2 is 3f, and the drive frequency of the motor load M-3 is 5f. Further, the duty ratio will be described as 50%, the current value of the load will be described as 1A for the motor load M-1, 2A for the motor load M-2, and 3A for the motor load M-3.

各モータ負荷（Ｍ−１〜Ｍ−ｎ）の駆動開始タイミングは、例えばクランクセンサの信号情報を使用して構成することができる。この場合、車両のエンジン始動タイミングをモータ負荷Ｍ−１の始動タイミングとして、起動時の電流変動を平均化するために各モータ負荷の電流値を各モータ負荷の電流の合計値で割った値をクランク角の数量で掛けた値の分だけモータ負荷が動作するタイミングをずらす。つまり、駆動開始タイミングのずらし方は、各モータ負荷（Ｍ−１〜Ｍ−ｎ）に流れる電流値の比で決定する。 The drive start timing of each motor load (M-1 to Mn) can be configured by using, for example, the signal information of the crank sensor. In this case, the engine start timing of the vehicle is set as the start timing of the motor load M-1, and the value obtained by dividing the current value of each motor load by the total value of the currents of each motor load in order to average the current fluctuation at the time of start is used. The timing at which the motor load operates is shifted by the value multiplied by the quantity of the crank angle. That is, how to shift the drive start timing is determined by the ratio of the current values flowing through each motor load (M-1 to Mn).

この場合、モータ負荷Ｍ−１はエンジンスタート時に駆動開始させるため、クランク１歯目のタイミングで駆動を開始する。モータ負荷Ｍ−２は、モータ負荷Ｍ−１のクランク角６０歯×１／６後１０歯目に駆動を開始する。また、モータ負荷Ｍ−３は、モータ負荷Ｍ−２のクランク角６０歯×２／６後１０歯＋２０歯＝３０歯目に駆動を開始する。 In this case, since the motor load M-1 is started to be driven when the engine is started, the driving is started at the timing of the first tooth of the crank. The motor load M-2 starts driving at the crank angle of 60 teeth × 1/6 of the motor load M-1 at the 10th tooth. Further, the motor load M-3 starts driving at the crank angle 60 teeth × 2/6 rear 10 teeth + 20 teeth = 30 teeth of the motor load M-2.

このように、各モータ負荷（Ｍ−１〜Ｍ−ｎ）の駆動開始タイミングをそれぞれずらすことで、各モータ負荷の駆動開始タイミングが各モータ負荷電流値に応じて分散し、電流変化が平均化される。また、駆動周波数を互いに割り切れない値にすることで全周期にわたり駆動タイミングが一致することがなくなる。その時の様子を示した波形が図２である。 By shifting the drive start timing of each motor load (M-1 to Mn) in this way, the drive start timing of each motor load is dispersed according to each motor load current value, and the current change is averaged. Will be done. Further, by setting the drive frequencies to values that are not divisible by each other, the drive timings do not match over the entire cycle. FIG. 2 shows a waveform showing the state at that time.

なお、図２では、各モータ負荷（Ｍ−１〜Ｍ−３）の駆動開始タイミングをそれぞれずらす制御を行う（重ならないように制御する）例を示しているが、さらに各モータ負荷（Ｍ−１〜Ｍ−３）の駆動終了タイミングをそれぞれずらす制御を行う（重ならないように制御する）ようにしてもよい。 Note that FIG. 2 shows an example in which the drive start timings of the motor loads (M-1 to M-3) are controlled to be shifted (controlled so as not to overlap), but each motor load (M-) is further controlled. Controls may be performed to shift the drive end timings of 1 to M-3) (control so that they do not overlap).

以上説明したように、本実施例の電子制御装置１００は、複数の負荷（モータ負荷Ｍ−１〜Ｍ−ｎ）の各々に互いに独立して接続される複数の負荷駆動回路（駆動回路２０−１〜２０−ｎ）と、複数の負荷駆動回路（駆動回路２０−１〜２０−ｎ）の各々の動作タイミングを制御する演算装置１０を備えており、演算装置１０は、複数の負荷駆動回路（駆動回路２０−１〜２０−ｎ）の各々の動作開始タイミングが重ならないように制御する。 As described above, the electronic control device 100 of the present embodiment has a plurality of load drive circuits (drive circuits 20-) that are independently connected to each of the plurality of loads (motor loads M-1 to Mn). 1 to 20-n) and an arithmetic unit 10 for controlling the operation timing of each of the plurality of load drive circuits (drive circuits 20-1 to 20-n) are provided, and the arithmetic unit 10 includes the plurality of load drive circuits. Control is performed so that the operation start timings of (drive circuits 20-1 to 20-n) do not overlap.

また、演算装置１０は、複数の負荷駆動回路（駆動回路２０−１〜２０−ｎ）の各々の動作終了タイミングが重ならないように制御する。 Further, the arithmetic unit 10 controls so that the operation end timings of the plurality of load drive circuits (drive circuits 20-1 to 20-n) do not overlap.

また、演算装置１０は、複数の負荷駆動回路（駆動回路２０−１〜２０−ｎ）の各々の駆動周波数を互いに割り切れない値に設定し、全周期に渡り動作開始タイミングが一致しないように制御する。 Further, the arithmetic unit 10 sets the drive frequencies of the plurality of load drive circuits (drive circuits 20-1 to 20-n) to values that are not divisible by each other, and controls so that the operation start timings do not match over the entire cycle. To do.

また、演算装置１０は、複数の負荷駆動回路（駆動回路２０−１〜２０−ｎ）の各々の駆動周波数を互いに割り切れない値に設定し、全周期に渡り動作終了タイミングが一致しないように制御する。 Further, the arithmetic unit 10 sets the drive frequencies of the plurality of load drive circuits (drive circuits 20-1 to 20-n) to values that are not divisible by each other, and controls so that the operation end timings do not match over the entire cycle. To do.

また、複数の負荷駆動回路（駆動回路２０−１〜２０−ｎ）の各々は、共通の電源供給ライン（バッテリライン４１）に接続される。 Further, each of the plurality of load drive circuits (drive circuits 20-1 to 20-n) is connected to a common power supply line (battery line 41).

また、演算装置１０は、複数の負荷（Ｍ−１〜Ｍ−ｎ）の各々の電流値の比に基づき複数の負荷駆動回路（駆動回路２０−１〜２０−ｎ）の各々の動作開始タイミングを制御する。 Further, the arithmetic unit 10 has an operation start timing of each of the plurality of load drive circuits (drive circuits 20-1 to 20-n) based on the ratio of the current values of the plurality of loads (M-1 to Mn). To control.

本実施例の電子制御装置によれば、回路構成や部品の追加無しに負荷が駆動するタイミングを全周期に渡って意図的にずらすことで、駆動する負荷の電流値に依らず、負荷駆動回路に注入される電流を均一にして、発生する電磁ノイズを最小限にすることができる。その際、駆動する負荷の電流量や駆動する負荷の特性が異なっても問題とはならない。 According to the electronic control device of this embodiment, the load driving circuit is intentionally shifted over the entire cycle without adding a circuit configuration or parts, so that the load driving circuit does not depend on the current value of the driving load. The current injected into the can be made uniform to minimize the electromagnetic noise generated. At that time, it does not matter even if the amount of current of the driving load and the characteristics of the driving load are different.

図３を参照して、本発明の実施例２の電子制御装置とその制御方法について説明する。図３は、本実施例の電子制御装置１００の概略構成を示す機能ブロック図であり、実施例１（図１）の変形例に相当する。 An electronic control device according to a second embodiment of the present invention and a control method thereof will be described with reference to FIG. FIG. 3 is a functional block diagram showing a schematic configuration of the electronic control device 100 of the present embodiment, and corresponds to a modified example of the first embodiment (FIG. 1).

図３に示す本実施例の電子制御装置１００は、駆動回路（２０−１〜２０−ｎ）の構成が実施例１とは異なる。その他の構成は、実施例１と同様であるため、以下では主に相違点について説明する。 The electronic control device 100 of the present embodiment shown in FIG. 3 has a different drive circuit (20-1 to 20-n) configuration from that of the first embodiment. Since other configurations are the same as those in the first embodiment, the differences will be mainly described below.

本実施例の電子制御装置１００は、図３に示すように、駆動回路（２０−１〜２０−ｎ）の各々が、その内部にモータ負荷（ここでは、モータ負荷Ｍ−１，Ｍ−２）を駆動させるためのHブリッジ回路２１を２個備えている。 In the electronic control device 100 of this embodiment, as shown in FIG. 3, each of the drive circuits (20-1 to 20-n) has a motor load (here, motor loads M-1 and M-2) inside the drive circuit (20-1 to 20-n). ) Is provided with two H-bridge circuits 21 for driving.

１つの駆動回路２０−１は、２つのHブリッジ回路２１−１，２１−２を内蔵しており、Hブリッジ回路２１−１，２１−２はそれぞれモータ負荷Ｍ−１，Ｍ−２に接続され、モータ負荷Ｍ−１，Ｍ−２を個別に駆動制御する。 One drive circuit 20-1 incorporates two H-bridge circuits 21-1,21-2, and the H-bridge circuits 21-1,21-2 are connected to the motor loads M-1 and M-2, respectively. Then, the motor loads M-1 and M-2 are individually driven and controlled.

本実施例では、２つのHブリッジ回路２１−１，２１−２のそれぞれの駆動開始タイミングをずらすことで、１つの駆動回路２０−１に接続されているモータ負荷Ｍ−１，Ｍ−２のそれぞれの駆動開始タイミングが各モータ負荷電流値に応じて分散し、電流変化が平均化される。また、駆動周波数を互いに割り切れない値にすることで全周期にわたり駆動タイミングが一致することがなくなる。 In this embodiment, the drive start timings of the two H-bridge circuits 21-1 and 21-2 are shifted so that the motor loads M-1 and M-2 connected to one drive circuit 20-1 are used. Each drive start timing is dispersed according to each motor load current value, and the current change is averaged. Further, by setting the drive frequencies to values that are not divisible by each other, the drive timings do not match over the entire cycle.

以上説明したように、本実施例の電子制御装置１００は、複数の負荷（モータ負荷Ｍ−１，Ｍ−ｎ）に接続される負荷駆動回路（駆動回路２０−１）と、負荷駆動回路（駆動回路２０−１）の動作タイミングを制御する演算装置１０を備えており、負荷駆動回路（駆動回路２０−１）は、複数の負荷（モータ負荷Ｍ−１，Ｍ−ｎ）の各々に互いに独立して接続される複数のHブリッジ回路（２１−１，２１−２）を有しており、演算装置１０は、複数のHブリッジ回路（２１−１，２１−２）の各々の動作開始タイミングが重ならないように制御する。 As described above, the electronic control device 100 of the present embodiment includes a load drive circuit (drive circuit 20-1) connected to a plurality of loads (motor loads M-1, Mn) and a load drive circuit (drive circuit 20-1). The arithmetic unit 10 for controlling the operation timing of the drive circuit 20-1) is provided, and the load drive circuit (drive circuit 20-1) is attached to each of the plurality of loads (motor loads M-1, Mn). It has a plurality of H-bridge circuits (21-1,21-2) that are independently connected, and the arithmetic unit 10 starts the operation of each of the plurality of H-bridge circuits (21-1,1-2). Control so that the timings do not overlap.

これにより、実施例１と同様に、駆動する負荷の電流値に依らず、複数のHブリッジ回路の各々に注入される電流を均一にして、発生する電磁ノイズを最小限にすることができる。 As a result, as in the first embodiment, the current injected into each of the plurality of H-bridge circuits can be made uniform regardless of the current value of the driving load, and the generated electromagnetic noise can be minimized.

なお、本実施例（図３）では、１つの駆動回路２０−１に２つのHブリッジ回路２１−１，２１−２が内蔵されている例を示したが、駆動回路によっては２個以上のHブリッジ回路が内蔵される場合もあるため、Hブリッジ回路２個は一例であり、数量を限定するものではない。 In this embodiment (FIG. 3), an example in which two H-bridge circuits 21-1 and 21-2 are built in one drive circuit 20-1 is shown, but depending on the drive circuit, two or more H-bridge circuits are shown. Since the H-bridge circuit may be built in, the two H-bridge circuits are an example, and the number is not limited.

なお、本発明は上記した実施例に限定されるものではなく、様々な変形例が含まれる。例えば、上記した実施例は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施例の構成の一部を他の実施例の構成に置き換えることが可能であり、また、ある実施例の構成に他の実施例の構成を加えることも可能である。また、各実施例の構成の一部について、他の構成の追加・削除・置換をすることが可能である。 The present invention is not limited to the above-described examples, and includes various modifications. For example, the above-described embodiment has been described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one including all the described configurations. Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add / delete / replace a part of the configuration of each embodiment with another configuration.

１０：演算装置
１１（１１−１〜１１−ｎ）：演算装置１０と駆動回路２０間のシリアル通信ライン
１２（１２−１〜１２−ｎ）：演算装置１０から駆動回路２０への入力ライン
１３（１３−１〜１３−ｎ）：演算装置１０から駆動回路２０への入力ライン
２０（２０−１〜２０−ｎ）：駆動回路
２１（２１−１〜２１−ｎ）：Hブリッジ回路（複数のドライバを内蔵する駆動回路の場合）
３０：コンデンサ
４０：バッテリ
４１：（バッテリ４０と駆動回路２０間の）バッテリライン
１００：電子制御装置
Ｍ（Ｍ−１〜Ｍ−ｎ）：モータ負荷 10: Arithmetic logic unit 11 (11-1 to 11-n): Serial communication line between arithmetic unit 10 and drive circuit 20 12 (12-1 to 12-n): Input line from arithmetic unit 10 to drive circuit 20 13 (13-1 to 13-n): Input line 20 (20-1 to 20-n) from the arithmetic unit 10 to the drive circuit 20: Drive circuit 21 (21-1 to 21-n): H-bridge circuit (plural) In the case of a drive circuit with a built-in driver)
30: Capacitor 40: Battery 41: Battery line (between battery 40 and drive circuit 20) 100: Electronic control device M (M-1 to Mn): Motor load

Claims (7)

複数の負荷を駆動制御する電子制御装置であって、
前記複数の負荷の各々に互いに独立して接続される複数の負荷駆動回路と、
前記複数の負荷駆動回路の各々の動作タイミングを制御する演算装置と、を備え、
前記演算装置は、前記複数の負荷駆動回路の各々の動作開始タイミングが重ならないように制御する電子制御装置。 An electronic control device that drives and controls multiple loads.
A plurality of load drive circuits connected to each of the plurality of loads independently of each other,
An arithmetic unit that controls the operation timing of each of the plurality of load drive circuits is provided.
The arithmetic unit is an electronic control device that controls so that the operation start timings of the plurality of load drive circuits do not overlap. 複数の負荷を駆動制御する電子制御装置であって、
前記複数の負荷に接続される負荷駆動回路と、
前記負荷駆動回路の動作タイミングを制御する演算装置と、を備え、
前記負荷駆動回路は、前記複数の負荷の各々に互いに独立して接続される複数のHブリッジ回路を有し、
前記演算装置は、前記複数のHブリッジ回路の各々の動作開始タイミングが重ならないように制御する電子制御装置。 An electronic control device that drives and controls multiple loads.
A load drive circuit connected to the plurality of loads and
An arithmetic unit that controls the operation timing of the load drive circuit is provided.
The load drive circuit has a plurality of H-bridge circuits connected to each of the plurality of loads independently of each other.
The arithmetic unit is an electronic control device that controls so that the operation start timings of the plurality of H-bridge circuits do not overlap. 請求項１または２に記載の電子制御装置であって、
前記演算装置は、前記複数の負荷駆動回路の各々または前記複数のHブリッジ回路の各々の動作終了タイミングが重ならないように制御する電子制御装置。 The electronic control device according to claim 1 or 2.
The arithmetic unit is an electronic control device that controls so that the operation end timings of each of the plurality of load drive circuits or the plurality of H-bridge circuits do not overlap. 請求項１または２に記載の電子制御装置であって、
前記演算装置は、前記複数の負荷駆動回路の各々または前記複数のHブリッジ回路の各々の駆動周波数を互いに割り切れない値に設定し、全周期に渡り動作開始タイミングが一致しないように制御する電子制御装置。 The electronic control device according to claim 1 or 2.
The arithmetic unit sets the drive frequencies of each of the plurality of load drive circuits or each of the plurality of H-bridge circuits to values that are not divisible by each other, and electronically controls so that the operation start timings do not match over the entire cycle. apparatus. 請求項３に記載の電子制御装置であって、
前記演算装置は、前記複数の負荷駆動回路の各々または前記複数のHブリッジ回路の各々の駆動周波数を互いに割り切れない値に設定し、全周期に渡り動作終了タイミングが一致しないように制御する電子制御装置。 The electronic control device according to claim 3.
The arithmetic unit sets the drive frequencies of each of the plurality of load drive circuits or each of the plurality of H-bridge circuits to values that are not divisible by each other, and electronically controls so that the operation end timings do not match over the entire cycle. apparatus. 請求項１に記載の電子制御装置であって、
前記複数の負荷駆動回路の各々は、共通の電源供給ラインに接続される電子制御装置。 The electronic control device according to claim 1.
Each of the plurality of load drive circuits is an electronic control device connected to a common power supply line. 請求項１または２に記載の電子制御装置であって、
前記演算装置は、前記複数の負荷の各々の電流値の比に基づき前記複数の負荷駆動回路の各々の動作開始タイミングまたは前記複数のHブリッジ回路の各々の動作開始タイミングを制御する電子制御装置。 The electronic control device according to claim 1 or 2.
The arithmetic unit is an electronic control device that controls the operation start timing of each of the plurality of load drive circuits or the operation start timing of each of the plurality of H-bridge circuits based on the ratio of the current values of the plurality of loads.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12040790B2 (en) 2022-08-31 2024-07-16 Kabushiki Kaisha Toshiba Electronic apparatus, switching system, and control method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH074291A (en) * 1993-06-18 1995-01-10 Toyota Motor Corp Fuel injection valve driving device
JP2013219907A (en) * 2012-04-06 2013-10-24 Denso Corp Electric power conversion apparatus
JP2014035721A (en) * 2012-08-10 2014-02-24 Yazaki Corp Pwm control device
JP2016122150A (en) * 2014-12-25 2016-07-07 キヤノン株式会社 Image forming apparatus
WO2019187529A1 (en) * 2018-03-29 2019-10-03 日本精工株式会社 Motor control device and failure detection method for motor control device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH074291A (en) * 1993-06-18 1995-01-10 Toyota Motor Corp Fuel injection valve driving device
JP2013219907A (en) * 2012-04-06 2013-10-24 Denso Corp Electric power conversion apparatus
JP2014035721A (en) * 2012-08-10 2014-02-24 Yazaki Corp Pwm control device
JP2016122150A (en) * 2014-12-25 2016-07-07 キヤノン株式会社 Image forming apparatus
WO2019187529A1 (en) * 2018-03-29 2019-10-03 日本精工株式会社 Motor control device and failure detection method for motor control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12040790B2 (en) 2022-08-31 2024-07-16 Kabushiki Kaisha Toshiba Electronic apparatus, switching system, and control method

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