JP2021100235A - Power amplifier module - Google Patents

Abstract

To provide a power amplifier module by which the increase in length of a region including a transistor line is suppressed and the increase in parasitic resistance from the transistor to an impedance conversion circuit or the increase in variation of the parasitic inductance can be suppressed.SOLUTION: A semiconductor chip includes a plurality of transistor lines. In accordance with the transistor lines, a first bump connected to a collector of a transistor is disposed and a second bump connected to an emitter is disposed. The transistor lines are arranged along a side of a convex polygon. A first land and a second land provided to a circuit board are connected to the first bump and the second bump, respectively. The first land and a signal output terminal are connected by a first impedance conversion circuit. The transistors in the transistor line are divided into a plurality of groups. The first impedance conversion circuit includes a reactive element disposed for each group.SELECTED DRAWING: Figure 1

Description

The present invention relates to a power amplification module.

A plurality of transistors connected in parallel to each other are used in the final stage (power stage) of the multi-stage high-frequency power amplifier circuit. An impedance conversion circuit for impedance matching is inserted between the amplifier circuit of the power stage and the load. Generally, an impedance conversion circuit that converts the output impedance of the power stage amplifier circuit into a high impedance is used.

In order to increase the output of the power amplifier circuit, it is necessary to pass a large current through the signal path from the collector as the signal output port of the transistor group to the input port of the impedance conversion circuit. The loss in the signal path is proportional to the product of the square of the current and the parasitic resistance. Therefore, as the flowing current increases, the loss increases in proportion to the square of the current. On the other hand, after passing through the impedance conversion circuit, the impedance becomes high and the current decreases, so that the contribution of the parasitic resistor that affects the loss becomes small. Therefore, in order to reduce the loss and increase the output, it is desired to reduce the parasitic resistance of the signal path through which a large current flows from the collector of the transistor to the input port of the impedance conversion circuit.

Further, in each transistor, if the parasitic resistance and the parasitic inductance generated in the signal path from the collector to the input port of the impedance conversion circuit vary among the plurality of transistors, the operation varies among the plurality of transistors. The variation in operation among a plurality of transistors becomes a factor that reduces the output of the high-frequency power amplifier circuit.

In order to increase the output, a power amplification module in which the arrangement of a plurality of transistors in the power stage amplifier circuit is devised has been proposed (Patent Document 1). In this power amplification module, a plurality of transistors are arranged in a row, and collectors of the plurality of transistors are connected to each other and connected to a signal output bump.

Japanese Unexamined Patent Publication No. 2000-106386

If the number of transistors is increased in order to further increase the output of the power amplifier circuit, the area occupied by the plurality of transistors arranged in a row becomes long. As a result, depending on the transistor, the signal path from the signal output port to the impedance conversion circuit becomes long, and the parasitic resistance increases. In addition, the length variation from the signal output port of the transistor to the impedance conversion circuit becomes large.

An object of the present invention is to suppress an increase in the length of a region occupied by a plurality of transistor trains even if the number of transistors is increased, and to increase the parasitic resistance from the transistor to the impedance conversion circuit and increase the variation in the parasitic inductance. It is to provide the power amplification module which can suppress.

According to one aspect of the invention
It has a circuit board and a semiconductor chip mounted on the circuit board.
The semiconductor chip is
With the board
It is provided with a plurality of transistor trains formed on the substrate.
Each of the plurality of transistor trains includes a plurality of power stage transistors arranged in a straight line.
Each of the plurality of power stage transistors is a bipolar transistor or field effect transistor having an emitter or source as a ground port, a collector or drain as a signal output port, and a base or gate as a signal input port.
The semiconductor chip further
A plurality of first bumps arranged corresponding to each of the plurality of transistor trains and connected to signal output ports of the plurality of power stage transistors included in the corresponding transistor trains.
It is provided with a plurality of second bumps arranged corresponding to each of the plurality of transistor trains and connected to the ground port of the plurality of power stage transistors included in the corresponding transistor trains.
The plurality of transistor trains are arranged along a plurality of sides of a convex polygon.
The circuit board
A plurality of first lands connected to the plurality of first bumps, respectively,
A plurality of second lands connected to the plurality of second bumps, respectively,
The ground pattern connected to the plurality of second lands and
Signal output terminal and
A first impedance conversion circuit for connecting the plurality of first lands and the signal output terminal is provided.
The plurality of power stage transistors are grouped into a plurality of groups, and the first impedance conversion circuit includes a power amplification module including a plurality of individual reactance elements arranged for each of the plurality of groups. Provided.

By arranging a plurality of transistor rows along a plurality of sides of a convex polygon, it is possible to suppress an increase in the length of the transistor rows as compared with the case where the plurality of transistor rows are arranged along a single straight line. .. By arranging individual reactance elements of the first impedance conversion circuit corresponding to each group of power stage transistors, the signal path from the power stage transistor to the first impedance conversion circuit can be shortened. As a result, it is possible to suppress an increase in the parasitic resistance of this signal path and an increase in the variation in the parasitic inductance.

FIG. 1 is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the first embodiment. FIG. 2 is a cross-sectional view of a part of the power amplification module according to the first embodiment. FIG. 3 is a diagram showing the positional relationship of a plurality of components of the power stage transistor in a plan view. FIG. 4 is a cross-sectional view taken along the alternate long and short dash line 4-4 of FIG. FIG. 5 is an equivalent circuit diagram of the power amplification module according to the first embodiment. FIG. 6 is a diagram showing a positional relationship in a plan view of a plurality of power stage transistors provided on a semiconductor chip of a power amplification module according to a comparative example and wiring on a circuit board. FIG. 7 is a diagram showing a positional relationship in a plan view of a plurality of power stage transistors provided on a semiconductor chip of a power amplification module according to another comparative example, and wiring on a circuit board. FIG. 8 is a diagram showing a positional relationship in a plan view of a plurality of power stage transistors provided on a semiconductor chip of a power amplification module according to still another comparative example, and wiring on a circuit board. FIG. 9 is a diagram showing the positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the modified example of the first embodiment. FIG. 10 is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the second embodiment. FIG. 11 is an equivalent circuit diagram of the power amplification module according to the second embodiment. FIG. 12 is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the third embodiment. FIG. 13 is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the fourth embodiment. FIG. 14 is an equivalent circuit diagram of the power amplification module according to the fourth embodiment. FIG. 15 is a diagram schematically showing a part of components of the power amplification module according to the fifth embodiment. FIG. 16 is a diagram showing a positional relationship in a plan view of a plurality of components of the pre-stage amplifier circuit and the power stage amplifier circuit provided on the semiconductor chip of the power amplification module according to the sixth embodiment. FIG. 17 is an equivalent circuit diagram of the front stage amplifier circuit, the second impedance conversion circuit, and the power stage amplifier circuit. FIG. 18 is a diagram showing a positional relationship in a plan view of a plurality of components of the pre-stage amplifier circuit and the power stage amplifier circuit provided on the semiconductor chip of the power amplification module according to the seventh embodiment. FIG. 19A is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the eighth embodiment. FIG. 19B is a schematic diagram for explaining the difference between the transistor array and the group of power stage transistors. FIG. 20 is a diagram showing the positional relationship of the components of the pre-stage amplifier circuit and the circuit that generates the differential signals input to the plurality of power stage transistors in a plan view. FIG. 21 is an equivalent circuit diagram of the power amplification module according to the eighth embodiment. FIG. 22 is a diagram showing a circuit for generating differential signals input to a plurality of power stage transistors of the power amplification module according to the present modification, and a positional relationship of components of the pre-stage amplifier circuit in a plan view. FIG. 23A is a diagram showing the shape of the primary coil of the power amplification module according to the eighth embodiment in a plan view, and FIGS. 23B, 23C, and 23D are views of the shape of the first portion according to a comparative example in a plan view. It is a figure which shows. FIG. 24 is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the ninth embodiment. FIG. 25 is a diagram showing the positional relationship of the components of the pre-stage amplifier circuit and the circuit that generates the differential signals input to the plurality of power stage transistors in a plan view. FIG. 26 is an equivalent circuit diagram of the power amplification module according to the ninth embodiment. FIG. 27 shows the positions of the plurality of power stage transistors, the second transformer, and the components of the pre-stage amplifier circuit in the plan view of the second transformer of the power amplification module according to the modification in which the turns ratio of the second transformer is 2: 1. It is a figure which shows the relationship. FIG. 28 shows a plan view of a plurality of power stage transistors of the second transformer of the power amplification module, the second transformer, and the components of the pre-stage amplifier circuit according to a modification in which the turns ratio of the second transformer is about 4: 3. It is a figure which shows the positional relationship. The drawings from FIGS. 29A to 29D are schematic views showing a connection form of the secondary coil of the second transformer when two rows of transistor rows are arranged. The drawings from FIGS. 30A to 30F are schematic views showing the connection form of the secondary coil of the second transformer when four rows of transistor rows are arranged. The drawings from FIGS. 31A to 31F are schematic views showing a connection form of the secondary coil of the second transformer when four rows of transistor rows are arranged. 32A and 32B are schematic views showing a connection form of the secondary coil of the first transformer when two rows of transistor rows are arranged. The drawings from FIGS. 33A to 33D are schematic views showing a connection form of the secondary coil of the first transformer when four rows of transistor rows are arranged. FIG. 34 is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the tenth embodiment. FIG. 35 is a cross-sectional view of the power amplification module according to the tenth embodiment. FIG. 36 is a diagram showing the positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the modified example of the tenth embodiment. FIG. 37 is a diagram showing a circuit for generating differential signals input to a plurality of power stage transistors of the power amplification module according to the eleventh embodiment, and a positional relationship of components of the pre-stage amplifier circuit in a plan view. FIG. 38 is an equivalent circuit diagram of the power amplification module according to the eleventh embodiment.

[First Example]
The power amplification module according to the first embodiment will be described with reference to the drawings of FIGS. 1 to 5.

FIG. 1 is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the first embodiment. The power amplification module according to the first embodiment includes a semiconductor chip and a circuit board. In FIG. 1, the conductor film formed on the semiconductor chip is provided with relatively dark hatching, and the conductor film formed on the circuit board is provided with relatively light hatching.

First, the configuration of the semiconductor chip will be described. The semiconductor chip includes a substrate made of a semiconductor and two rows of transistor rows 12 arranged on the substrate. Each of the two rows of transistor rows 12 includes a plurality of (for example, 12) power stage transistors 13 arranged in a straight line. Each of the plurality of power stage transistors 13 belongs to one of the two rows of transistor rows 12. Each of the power stage transistors 13 is a bipolar transistor having a collector as a signal output port, a base as a signal input port, and an emitter as a ground port. The detailed structure of the power stage transistor 13 will be described later with reference to FIGS. 3 and 4. In the present specification, the signal output port, signal input port, and ground port of the plurality of power stage transistors 13 of the transistor row 12 are referred to as the signal output port of the transistor row 12, the signal input port of the transistor row 12, and the transistor row 12, respectively. It may be called the ground port of.

Each of the plurality of power stage transistors 13 includes a collector mesa 20 that is long in a direction orthogonal to the arrangement direction of the power stage transistors 13 (hereinafter, referred to as a length direction of the transistor train 12) in a plan view. The collector mesa 20 includes a laminated collector layer, a base layer, and an emitter layer.

The two transistor rows 12 are arranged along the two opposite sides of the virtual convex polygon 30 which is a rectangle in a plan view. The first bump 21 and the second bump 22 are arranged corresponding to each of the two transistor rows 12. Each of the plurality of first bumps 21 is arranged at a position farther than the corresponding second bump 22 when viewed from the geometric center of the convex polygon 30. Each of the two first bumps 21 is connected to the signal output port of the corresponding transistor train 12 via the collector wiring 14. Each of the two second bumps 22 is connected to the ground port of the corresponding transistor row 12. Base wiring 15 (see FIG. 3) is connected to each of the bases of the plurality of power stage transistors 13. That is, a plurality of base wirings 15 are connected to each signal input port of the two rows of transistor rows 12.

In a plan view, the base wiring 15 is drawn out from the region where the collector mesa 20 of the power stage transistor 13 is arranged toward the inside of the convex polygon 30. The second bump 22 is arranged at a position overlapping the collector mesa 20 of the power stage transistor 13 in a plan view, and has a long shape in the arrangement direction of the power stage transistor 13. The collector wiring 14 is drawn out from the region between the collector mess 20 of the plurality of power stage transistors 13 toward the outside of the convex polygon 30, and is bundled into one for each transistor row 12. The first bump 21 is arranged at a position overlapping the bundled portion of the collector wiring 14. Each of the first bumps 21 has a long shape in a direction parallel to the length direction of the corresponding transistor train 12.

The two collector wirings 14 arranged for each of the two transistor rows 12 are connected to each other via a resistance element 46 provided on the semiconductor chip.

Next, the configuration of the circuit board will be described. In a plan view, the first land 101 is arranged in each of the regions overlapping the two first bumps 21. The output wiring 103 extends from each of the two first lands 101 toward the outside of the convex polygon 30. The two output wirings 103 are each connected to the first power supply wiring 106. A power supply voltage Vcc1 is applied to the collector of the power stage transistor 13 from the first power supply wiring 106 via the output wiring 103, the first land 101, the first bump 21, and the collector wiring 14.

One terminal of the chip capacitor 121 is connected to the tip of each of the two output wires 103. The other terminal of the two chip capacitors 121 is connected to the output wiring 104, respectively.

The output wiring 104 extends in two directions from a portion connected to each of the two chip capacitors 121. The portion extending to one side of the output wiring 104 is grounded at its tip. The portion of the output wiring 104 from the portion connected to the chip capacitor 121 to the grounded portion functions as the inductor 122. A portion of the output wiring 104 extending from a portion connected to one chip capacitor 121 to the other and a portion extending from a portion connected to the other chip capacitor 121 to the other are connected at a confluence portion 104J. The merging point 104J is connected to the signal output terminal 110. The amplified output signal Pout is output from the signal output terminal 110.

One terminal of the chip capacitor 124 is connected to the output wiring 104 between the merging point 104J and the point connected to the two chip capacitors 121, respectively. The other terminals of the two chip capacitors 124 are each connected to a grounding land 125. The grounding land 125 is grounded. The portion of the output wiring 104 from the portion connected to the chip capacitor 121 to the portion connected to the chip capacitor 124 functions as the inductor 123.

The inductors 122 and 123 including the chip capacitors 121 and 124 connected to the output wirings 104 from the confluence point 104J to the two grounding points and the output wirings 104, respectively, constitute the first impedance conversion circuit 120. The two first impedance conversion circuits 120 connect the first land 101 and the signal output terminal 110, respectively. The two first lands 101 function as input points of the first impedance conversion circuit 120, respectively.

The first impedance conversion circuit 120 is arranged for each first land 101. That is, the first impedance conversion circuit 120 is arranged corresponding to each of the signal output ports of the two transistor trains 12. The first impedance conversion circuit 120 has a function of converting the output impedance of the corresponding transistor train 12 and a function of synthesizing the power of the high frequency signal output from each of the two transistor trains 12.

The lengths of the signal paths from the first bump 21 corresponding to each of the two transistor trains 12 to the signal output terminal 110 are substantially the same. Therefore, the high-frequency signal output from one transistor row 12 and the high-frequency signal output from the other transistor row 12 do not cause a phase shift at the signal output terminal 110. For example, if the difference between the lengths of the two signal paths is 20% or less of the average value of the two signal paths, it can be said to be "almost equal".

FIG. 2 is a cross-sectional view of a part of the power amplification module according to the first embodiment. The semiconductor chip 10 is flip-chip mounted on the circuit board 100. As the circuit board 100, for example, a printed circuit board is used. The semiconductor chip 10 includes a substrate 11 made of a semiconductor, and two collector pads 27 and two emitter pads 28 are provided on the surface of the substrate 11 facing the circuit board 100. Two first bumps 21 are formed on the surfaces of the two collector pads 27, respectively. Two second bumps 22 are formed on the surfaces of the two emitter pads 28, respectively.

The two collector pads 27 are connected to the signal output ports of the plurality of power stage transistors 13 (FIG. 1) via the collector wiring 14 (FIG. 1) provided on the semiconductor chip 10, respectively. The two emitter pads 28 are connected to the emitters (grounded ports) of the plurality of power stage transistors 13 (FIG. 1) of the corresponding transistor trains 12.

The circuit board 100 has two first lands 101 and two second lands 102 provided on the surface on which the semiconductor chip 10 is mounted. Two output wirings 103 extend from each of the two first lands 101. A plurality of ground patterns 105 are arranged on the inner layer of the circuit board 100 and the surface opposite to the surface on which the semiconductor chip 10 is mounted. The plurality of ground patterns 105 are connected to each other by a plurality of via conductors. The second land 102 is connected to a plurality of ground patterns 105.

Next, the configuration of the power stage transistor 13 will be described with reference to FIGS. 3 and 4.
FIG. 3 is a diagram showing a positional relationship of a plurality of components of the power stage transistor 13 in a plan view, and FIG. 4 is a cross-sectional view taken along the alternate long and short dash line 4-4 of FIG. In FIG. 4, the description of the insulating film between the metal wiring layers is omitted.

An n-type sub-collector layer 19 is arranged on the substrate 11 made of a semiconductor. An n-type collector layer 18, a p-type base layer 17, and an n-type emitter layer 16 are laminated in this order on a part of a region of the sub-collector layer 19. The collector layer 18, the base layer 17, and the emitter layer 16 constitute the collector mesa 20. An n-type emitter mesa 16M is arranged on a part of the emitter layer 16. The collector layer 18, the base layer 17, and the emitter layer 16 are formed of, for example, n-type GaAs, p-type GaAs, and n-type InGaP, respectively, and form a heterojunction bipolar transistor (HBT).

The collector electrode 31 is arranged on the sub-collector layer 19 so as to sandwich the collector mesa 20 in a plan view. The collector electrode 31 is connected to the collector layer 18 via the sub collector layer 19.

A base electrode 32 is arranged on the emitter layer 16 so as to surround the emitter mesa 16M from three sides in a plan view. The base electrode 32 is connected to the base layer 17 via an alloy layer that penetrates the emitter layer 16 in the thickness direction. The emitter electrode 33 is arranged on the emitter mesa 16M. The emitter electrode 33 is arranged on the emitter mesa 16M. The emitter electrode 33 is connected to the emitter layer 16 via an emitter mesa 16M. In FIG. 1, the collector electrode 31, the base electrode 32, the emitter electrode 33, and the like are not shown.

The collector wiring 14 is arranged on the collector electrode 31. The emitter wiring 34 is arranged on the emitter electrode 33. The emitter pad 28 is arranged on the emitter wiring 34. The emitter pads 28 are arranged corresponding to each of the two transistor rows 12, and connect the emitter electrodes 33 of the plurality of power stage transistors 13 of the corresponding transistor rows 12 to each other. The second bump 22 is arranged on the emitter pad 28.

Although not shown in the cross section shown in FIG. 4, a collector pad arranged in the same conductor layer as the emitter pad 28 is also arranged on the collector wiring 14. The first bump 21 (FIG. 1) is connected to the collector wiring 14 via the collector pad.

The base wiring 15 is connected to the base electrode 32. The base wiring 15 intersects with the interstage signal wiring 35, and a capacitor 36 is formed at the intersection. The interstage signal wiring 35 is arranged corresponding to each of the two transistor rows 12. The base wiring 15 is connected to the bias wiring 38 via the base ballast resistance element 37. In FIG. 1, the description of the interstage signal wiring 35, the base ballast resistance element 37, the bias wiring 38, and the like is omitted.

FIG. 5 is an equivalent circuit diagram of the power amplification module according to the first embodiment.
The two transistor trains 12 formed on the semiconductor chip 10 each form two power stage amplifier circuits 45. Further, the semiconductor chip 10 is provided with a pre-stage amplifier circuit 40, a second impedance conversion circuit 50, and a resistance element 46. A high-frequency input signal Pin is input to the pre-stage amplifier circuit 40.

A power supply voltage Vcc2 is applied from the second power supply wiring 107 to the signal output port of the pre-stage amplifier circuit 40 via the inductor 51. The signal output port of the pre-stage amplifier circuit 40 is connected to two power stage amplifier circuits 45 via a capacitor 52. Specifically, the signal output port of the pre-stage amplifier circuit 40 is connected to the signal input port of the transistor train 12 via the capacitor 52, the capacitor 36, and the base wiring 15 (FIG. 3). The capacitor 52 and the inductor 51 form the second impedance conversion circuit 50. The second impedance conversion circuit 50 has a function of matching the output impedance of the front stage amplifier circuit 40 with the input impedance of the power stage amplifier circuit 45. In FIG. 1, the description of the first stage amplifier circuit 40 and the second impedance conversion circuit 50 is omitted.

A power supply voltage Vcc1 is applied to each of the two power stage amplifier circuits 45 from the first power supply wiring 106. A resistance element 46 is connected between the signal output ports of the two power stage amplifier circuits 45. The resistance element 46 has a function of stabilizing high frequency operation.

The circuit board 100 is provided with two first impedance conversion circuits 120. Each of the two first impedance conversion circuits 120 includes chip capacitors 121 and 124, and inductors 122 and 123. The output ends of the two first impedance conversion circuits 120 are both connected to the signal output terminal 110. The amplified output signal Pout is output from the signal output terminal 110.

The two first impedance conversion circuits 120 each convert the output impedance of the power stage amplifier circuit 45 into a high impedance. Further, the two first impedance conversion circuits 120 have a function of synthesizing the power of the output signals of the two power stage amplifier circuits 45.

Considering each of the two rows of transistor rows 12 as one group so that the two rows of transistor rows 12 and the two groups have a one-to-one correspondence, the inductors 122 and 123 constituting the first impedance conversion circuit 120. And reactance elements such as chip capacitors 121 and 124 are arranged corresponding to each of the two groups. In the present specification, the reactance elements arranged corresponding to each of the groups are referred to as individual reactance elements. In the first embodiment, since the two rows of transistor rows 12 and the two groups have a one-to-one correspondence, it is not necessary to distinguish between the transistor rows and the groups, but the "transistor row" is a power stage transistor. It is defined by focusing on the geometrical arrangement of 13, and the "group" is defined by focusing on the connection of the reactors elements. For example, among the plurality of power stage transistors 13, the power stage transistors 13 in which the collectors are short-circuited can be said to belong to the same group.

Next, the excellent effects of the first embodiment will be described in comparison with the comparative examples shown in FIGS. 6, 7, and 8.

6, 7, and 8 are diagrams showing the positional relationship in a plan view of the plurality of power stage transistors 13 provided on the semiconductor chip of the power amplification module according to the comparative example, and the wiring on the circuit board 100, respectively.

In the comparative example shown in FIG. 6, a plurality of power stage transistors 13 are arranged in a row along one virtual straight line. A first bump 21 connected to a collector is arranged on one side of a transistor row composed of a plurality of power stage transistors 13. The first land 101 on the circuit board 100 is connected to the first bump 21. The first land 101 is connected to the signal output terminal 110 via the output wiring 103 and one first impedance conversion circuit 120.

In the comparative example shown in FIG. 7, a plurality of power stage transistors 13 are arranged in a staggered pattern.

In the power amplification module shown in FIGS. 6 and 7, it is necessary to increase the number of power stage transistors 13 in order to further increase the output. When the number of power stage transistors 13 is increased, the transistor array becomes long, and as a result, the first bump 21 and the first land 101 also have to be lengthened. Therefore, the size of the semiconductor chip 10 becomes large, which leads to an increase in manufacturing cost. Further, the degree of freedom of arrangement at the time of mounting on the circuit board is reduced.

On the other hand, in the first embodiment, since the plurality of power stage transistors 13 are arranged separately in the two transistor rows 12, it is possible to suppress an increase in the length of each of the two transistor rows 12. it can. As a result, it becomes possible to suppress an increase in the dimensions of the semiconductor chip 10. As a result, it is possible to suppress an increase in manufacturing cost and a decrease in the degree of freedom of arrangement when mounting on the circuit board 100.

In the comparative example shown in FIG. 8, a plurality of power stage transistors 13 are arranged separately in a plurality of transistor rows as in the case of the first embodiment. A plurality of transistor trains are arranged in parallel with each other. The first bump 21 connected to the collector of each power stage transistor 13 is arranged near one end of a plurality of transistor rows. The collectors of the plurality of power stage transistors 13 are connected to the first bump 21 via the collector wiring 14. The first bump 21 is connected to the first land 101 of the circuit board. The first land 101 is connected to the signal output terminal 110 via the output wiring 103 and one first impedance conversion circuit 120.

In the comparative example shown in FIG. 8, the length of the collector wiring 14 from the collector of the plurality of power stage transistors 13 to the first bump 21 is significantly different for each power stage transistor 13. Since the collector wiring 14 is formed of the conductor film on the semiconductor chip, it is thinner than the conductor film on the circuit board, and it is difficult to reduce the resistance and the inductance. Therefore, for the power stage transistor 13 located far from the first bump 21, the parasitic resistance and the parasitic inductance of the signal path become large, and it becomes difficult to increase the output.

On the other hand, in the first embodiment, the first bump 21 (FIG. 1), which is long in the direction parallel to the length direction of the plurality of transistor rows 12, is arranged close to the transistor rows 12. Therefore, the signal path from each signal input port of the power stage transistor 13 to the first bump 21 is shortened, and the variation in the path length between the power stage transistors 13 is also small. It is possible to reduce the parasitic resistance and the parasitic inductance of the signal path from the first bump 21 to the signal output ports of the plurality of power stage transistors 13.

In the circuit board 100, the output wiring 103 connects the first land 101 connected to the first bump 21 to the chip capacitor 121 of the first impedance conversion circuit 120. Since the output wiring 103 is extended in a direction orthogonal to the longitudinal direction of the first land 101, its width can be sufficiently widened.

Further, individual reactance elements such as a chip capacitor 121 are arranged for each of the two first lands 101, that is, for each signal output port of the two transistor trains. Therefore, as compared with the configuration in which a common impedance conversion circuit is arranged for the two transistor rows 12, the signal output port of any of the transistor rows 12 is from the signal output port to the first impedance conversion circuit 120. The signal path can be shortened. Thereby, it is possible to reduce the parasitic resistance and the parasitic inductance of the signal path from each of the signal output ports of the two rows of transistor rows 12 to the corresponding first impedance conversion circuit 120.

On the other hand, in the signal path from the first impedance conversion circuit 120 to the signal output terminal 110 side, the output impedance is converted to high impedance, so that the amount of current is small. Therefore, the occurrence of loss due to parasitic resistance or the like is small. As a result, it is possible to suppress the loss generated in the signal path from the signal output ports of the plurality of power stage transistors 13 to the signal output terminals 110, and to increase the output.

Further, since the variation in the parasitic resistance and the parasitic inductance of the signal path is small among the plurality of power stage transistors 13, it is possible to obtain an excellent effect that the variation in operation among the plurality of power stage transistors 13 is also small.

Further, in the first embodiment, most of the signal paths from the signal output ports of the plurality of power stage transistors 13 to the signal output terminals 110 are provided on the circuit board 100, and the signals provided on the semiconductor chip 10 are provided. The route is short. Since the signal path provided on the circuit board 100 is thicker than the signal path provided on the semiconductor chip 10, it is advantageous in reducing the parasitic resistance and the parasitic inductance. Further, the output signal mainly flows through the first bump 21 in the lateral direction orthogonal to the longitudinal direction thereof. That is, the product of the height of the first bump 21 and the dimension in the longitudinal direction corresponds to the cross-sectional area of the signal path. As described above, the height and length of the first bump 21 greatly contribute to the expansion of the cross-sectional area of the signal path.

Further, in the first embodiment, the first impedance conversion circuit 120 can be arranged according to the positions of the two transistor rows 12. Therefore, the two transistor trains 12 can be arranged with a wide interval. By widening the distance between the two transistor rows 12, the thermal interference between the two transistor rows 12 can be reduced and the heat dissipation efficiency can be improved. As a result, it is possible to achieve higher output.

Next, a modified example of the first embodiment will be described with reference to FIG.
FIG. 9 is a diagram showing the positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the modified example of the first embodiment. In the first embodiment, one first bump 21 (FIG. 1) is arranged for each of the two transistor rows 12. On the other hand, in this modification, a plurality of first bumps 21 are arranged for each of the two transistor rows 12. The plurality of first bumps 21 are arranged side by side in a direction parallel to the arrangement direction of the plurality of power stage transistors 13 in the corresponding transistor array.

Further, a plurality of second bumps 22 are also arranged corresponding to each of the two transistor rows 12, and are arranged in a direction parallel to the arrangement direction of the plurality of power stage transistors 13 in the corresponding transistor rows.

In this modification, the area of each of the first bump 21 and the second bump 22 becomes smaller in a plan view. Thereby, the height uniformity of the first bump 21 and the second bump 22 can be improved. As a result, an excellent effect that the process of mounting the semiconductor chip 10 on the circuit board 100 is facilitated can be obtained.

Further, in the first embodiment, the HBT is used for the power stage transistor 13 (FIGS. 3 and 4), but a field effect transistor may be used instead of the HBT. When a field effect transistor is used for the power stage transistor 13, the collector, the base, and the emitter may be read as a drain, a gate, and a source, respectively, in the first embodiment.

In the first embodiment, all the reactance elements of the first impedance conversion circuit 120 are arranged corresponding to each of the plurality of first lands 101. As another configuration, some reactance elements of the first impedance conversion circuit 120 are arranged corresponding to each of the plurality of first lands 101, and some other reactance elements are shared by the two first lands 101. It may be configured to be. Further, in the first embodiment, a transistor row 12 in which a plurality of power stage transistors 13 are arranged in a row along one virtual straight line is used, but instead of this configuration, it is shown in FIG. As described above, a transistor array in which a plurality of power stage transistors 13 are arranged in a staggered pattern may be used. By arranging the plurality of power stage transistors 13 in a staggered pattern, the number of power stage transistors 13 per unit length of the transistor train 12 can be increased.

[Second Example]
Next, the power amplification module according to the second embodiment will be described with reference to FIGS. 10 and 11. Hereinafter, the description of the configuration common to the power amplification module (drawings of FIGS. 1 to 5) according to the first embodiment will be omitted.

FIG. 10 is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the second embodiment. In FIG. 10, similarly to FIG. 1, the conductor film provided on the semiconductor chip 10 is provided with relatively dark hatching, and the conductor film provided on the circuit board 100 (FIG. 2) is relatively lightly hatched. Is attached.

In the first embodiment, the first bump 21 and the collector wiring 14 (FIG. 1) are connected in a direct current manner. On the other hand, in the second embodiment, the first bump 21 and the collector wiring 14 are connected via the capacitor 24. In FIG. 10, the region where the capacitor 24 is arranged is shown by a broken line. The capacitor 24 has a metal-insulator-metal (MIM) structure and is realized, for example, by arranging a dielectric film between the collector pad directly below the first bump 21 and the collector wiring 14. The collector pad and the collector wiring 14 each function as a pair of electrodes of the capacitor 24.

The collector wiring 14 extends to a region that does not overlap with any of the first land 101 and the output wiring 103 of the circuit board 100 in a plan view, and the power supply bump 23 is arranged in this expanding region. A power supply voltage Vcc1 is applied from the circuit board 100 to the collector of the power stage transistor 13 via the power supply bump 23 and the collector wiring 14.

The capacitor 24 provided on the semiconductor chip 10 corresponds to the chip capacitor 121 (FIG. 1) of the power amplification module according to the first embodiment. Therefore, in the second embodiment, the chip capacitor 121 (FIG. 1) is not mounted on the circuit board 100, and the output wiring 103 is directly connected to the output wiring 104.

Further, in the second embodiment, the MIM structure capacitor 25 provided on the semiconductor chip 10 is used instead of the chip capacitor 124 of the power amplification module according to the first embodiment. The capacitor 25 is composed of a lower electrode 25A and an upper electrode 25B provided on different conductor layers of the semiconductor chip 10, and a dielectric film arranged between them. In a plan view, the lower electrode 25A extends to the outside of the upper electrode 25B, and a part thereof overlaps with the confluence portion 104J of the output wiring 104.

The bump 26A is arranged at a position where the lower electrode 25A and the merging point 104J overlap. The bump 26A connects the lower electrode 25A of the semiconductor chip 10 and the output wiring 104 of the circuit board 100. The bump 26B is arranged at a position overlapping the upper electrode 25B in a plan view. The upper electrode 25B is connected to the ground pattern 105 of the circuit board 100 via the bump 26B.

FIG. 11 is an equivalent circuit diagram of the power amplification module according to the second embodiment. In the first embodiment, the first impedance conversion circuit 120 (FIG. 5) provided on the circuit board 100 is composed of chip capacitors 121 and 124 and inductors 122 and 123. On the other hand, in the second embodiment, the first impedance conversion circuit 120 provided on the circuit board 100 includes only the inductors 122 and 123. Instead of the chip capacitor 121, a capacitor 24 having an MIM structure provided on the semiconductor chip 10 is used. Further, instead of the chip capacitor 124, a capacitor 25 having a MIM structure provided on the semiconductor chip 10 is used. The capacitor 25 is shared by the two first impedance conversion circuits 120.

In the second embodiment, the first impedance conversion circuit 120 provided on the circuit board 100 and the capacitors 24 and 25 provided on the semiconductor chip 10 have a function of converting the output impedance of the power stage amplifier circuit 45, and an output signal. It has a function to synthesize the electric power of.

Next, the excellent effect of the second embodiment will be described.
In the second embodiment as well, as in the first embodiment, it is possible to suppress the loss generated in the signal path from each signal output port of the two rows of transistor rows 12 to the signal output terminal 110 to increase the output. It is possible. Further, in the second embodiment, since the capacitors 24 and 25 having a MIM structure are used instead of the chip capacitors 121 and 124, the size can be further reduced as compared with the first embodiment.

[Third Example]
Next, the power amplification module according to the third embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the power amplification module according to the first embodiment shown in the drawings of FIGS. 1 to 5 will be omitted.

FIG. 12 is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the third embodiment. In the first embodiment, the two transistor rows 12 are arranged along the two opposite sides of the rectangular convex polygon 30. On the other hand, in the third embodiment, the two transistor rows 12 are arranged along the two adjacent sides of the square convex polygon 30.

Each collector mesa 20 of the power stage transistor 13 has a long shape in a direction forming 45 ° with respect to the side of the convex polygon 30 in a plan view. The first bump 21 and the first land 101 also have a long shape in a direction parallel to the arrangement direction of the plurality of power stage transistors 13 in a plan view. The first bump 21 is connected to the collector wiring 14 via a capacitor 24 having a MIM structure, as in the case of the second embodiment (FIG. 10). In FIG. 12, the region where the capacitor 24 is arranged is shown by a broken line.

The output wiring 103 provided on the circuit board 100 (FIG. 2) is directly connected to the output wiring 104 as in the case of the second embodiment (FIG. 10). Instead of the two chip capacitors 124 (FIG. 1) of the power amplification module according to the first embodiment, two capacitors 25 having a MIM structure are provided on the semiconductor chip. Each structure of the capacitor 25 is the same as the structure of the capacitor 25 (FIG. 10) of the power amplification module according to the second embodiment.

Next, a modified example of the third embodiment will be described. In the third embodiment, it is explained that the two transistor rows 12 are arranged along the two adjacent sides of the virtual square, but the two transistor rows 12 are at right angles. It can also be said that they are arranged along two sides that sandwich the right angle of an isosceles triangle. That is, the virtual convex polygon 30 is not limited to an even-numbered polygon, but may be an odd-numbered polygon. When the virtual convex polygon 30 is a triangle, the convex polygon 30 is not limited to a right-angled isosceles triangle, but is not limited to another triangle, for example, an isosceles triangle whose angle formed by two equal sides is other than a right-angled triangle. It may be a triangle or the like.

Next, the excellent effect of the third embodiment will be described. In the third embodiment as well, as in the first embodiment, it is possible to suppress the loss generated in the signal path from each signal output port of the two rows of transistor rows 12 to the signal output terminal 110 to increase the output. It is possible. Further, as in the second embodiment, it is possible to reduce the size of the power amplification module.

[Fourth Example]
Next, the power amplification module according to the fourth embodiment will be described with reference to FIGS. 13 and 14. Hereinafter, the description of the configuration common to the power amplification module according to the first embodiment shown in the drawings of FIGS. 1 to 5 will be omitted.

FIG. 13 is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the fourth embodiment. In FIG. 13, similarly to FIG. 1, the conductor film provided on the semiconductor chip 10 is provided with relatively dark hatching, and the conductor film provided on the circuit board 100 (FIG. 2) is relatively lightly hatched. Is attached.

First, the configuration of the semiconductor chip 10 will be described. In the first embodiment, the two transistor rows 12 are arranged along the two opposite sides of the rectangular convex polygon 30. On the other hand, in the fourth embodiment, the four transistor rows 12 are arranged along the four sides of the convex polygon 30 which is a square. The configuration of each of the four transistor rows 12 is the same as the configuration of the transistor rows 12 (FIG. 1) of the power amplification module according to the first embodiment.

The collector wiring 14 arranged corresponding to the two transistor rows 12 along the adjacent sides of the convex polygon 30 is the position of the vertices (upper and lower vertices in FIG. 13) of the convex polygon 30. Are interconnected in. A power supply bump 23 is arranged at a position where the collector wiring 14 is connected to each other. The power supply voltage Vcc1 is applied to the collector of each power stage transistor 13 of the four transistor rows 12 via the power supply bump 23 and the collector wiring 14.

The first bump 21 is arranged corresponding to each of the four transistor rows 12. Each of the first bumps 21 has a long shape in a direction parallel to the length direction of the corresponding transistor row 12. Each of the four first bumps 21 is connected to the corresponding collector wiring 14 via a capacitor 24 having a MIM structure, as in the case of the second embodiment (FIG. 10).

Of the four vertices of the convex polygon 30, the resistance element 46 is arranged at the positions of the two vertices (the right and left vertices in FIG. 13) where the power supply bump 23 is not arranged. The resistance element 46 connects the two collector wirings 14 on both sides thereof to each other.

Next, the configuration of the circuit board 100 will be described. The first land 101 is arranged at a position overlapping the four first bumps 21 in a plan view. The four first lands 101 are connected to the corresponding first bumps 21 respectively. In a plan view, the output wiring 103 extends from each of the four first lands 101 toward the outside of the convex polygon 30. The four output wirings 103 are connected to the output wiring 104 at their tips. The output wiring 104 has an annular shape that surrounds the four transistor rows 12 in a plan view.

The output wiring 104 is divided into four parts at four connection points to which the four output wirings 103 are connected. Of the output wiring 104, two portions facing each other (the right and left portions in FIG. 13) are grounded at their centers. The output wiring 112 branches from the center of the other two parts (upper and lower parts in FIG. 13) of the output wiring 104, and the two output wirings 112 are connected to each other at the confluence 112J. ing. The merging point 112J is connected to the signal output terminal 110.

One terminal of the chip capacitor 124 is connected between the two connection points of the output wiring 112 and the output wiring 104 and the confluence point 112J, respectively. The other terminals of the two chip capacitors 124 are each connected to a grounding land 125.

Of the output wiring 104, four portions between each of the two grounding points and the points connected to the output wirings 103 on both sides of the output wiring 104 function as inductors 122, respectively. Of the output wiring 104, four portions between each of the two locations where the output wiring 112 branches and the locations connected to the output wiring 103 on both sides of the output wiring 112 function as the inductor 123, respectively. Of the output wiring 112, the portion between the connection portion with the output wiring 104 and the connection portion with the chip capacitor 124 functions as the inductor 126.

The lengths of the four signal paths from the four first bumps 21 to the signal output terminal 110 via the output wirings 103, 104, and 112, respectively, are the same. Therefore, at the position of the signal output terminal 110, the phase shift of the high frequency signal output from each of the four transistor trains 12 does not occur.

FIG. 14 is an equivalent circuit diagram of the power amplification module according to the fourth embodiment. The power amplification module (FIG. 5) according to the first embodiment includes two power stage amplifier circuits 45. On the other hand, in the fourth embodiment, the power amplification module includes four power stage amplifier circuits 45 corresponding to the four rows of transistor rows 12. The output ends of two power stage amplifier circuits 45 out of the four power stage amplifier circuits 45 are connected to each other by a resistance element 46. Further, the output ends of the other two power stage amplifier circuits 45 are connected to each other by a resistance element 46.

The output ends of the four power stage amplifier circuits 45 are connected to the signal output terminal 110 via the capacitor 24, the inductor 123, and the inductor 126, respectively. The point where the capacitor 24 and the inductor 123 are connected is grounded via the inductor 122. The end of the inductor 126 on the signal output terminal 110 side is grounded via the chip capacitor 124.

The four inductors 122, the four inductors 123, the two inductors 126, and the two chip capacitors 124 form the first impedance conversion circuit 120. The first impedance conversion circuit 120 and the four MIM-structured capacitors 24 have a function of converting the output impedance of the four power stage amplifier circuits 45.

The capacitors 24, inductors 122, and 123 are arranged corresponding to each of the four rows of transistor rows 12. The inductor 126 and the chip capacitor 124 are shared by the two rows of transistor rows 12.

Next, the excellent effect of the fourth embodiment will be described.
In the fourth embodiment, the inductor 122 and the inductor 123 of the first impedance conversion circuit 120 are provided corresponding to the four transistor trains 12, respectively. Four first lands 101 are arranged corresponding to each of the signal output ports of the four rows of transistor rows 12, and four capacitors 24, 4 correspond to each of the four first lands 101. The inductors 122 and 123 are arranged. Therefore, the signal path from the signal output port of the four rows of transistor rows 12 to the corresponding first impedance conversion circuit 120 can be shortened. As a result, as in the case of the first embodiment, it is possible to suppress the loss generated in the signal path from each of the signal output ports of the four rows of transistor rows 12 to the signal output terminal 110, and to increase the output. Is.

Further, in the fourth embodiment, since the power stage amplifier circuit 45 is composed of four transistor rows 12, the power stage amplifier circuit 45 is composed of two transistor rows 12 (FIG. 1) in the first embodiment. As compared with the above, it is possible to increase the number of power stage transistors 13 while keeping the lengths of the transistor rows 12 the same. Therefore, it is possible to further increase the output of the power amplification module.

[Fifth Example]
Next, the power amplification module according to the fifth embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the power amplification module (FIGS. 13 and 14) according to the fourth embodiment will be omitted.

FIG. 15 is a diagram schematically showing a part of components of the power amplification module according to the fifth embodiment. In the fourth embodiment, the four transistor rows 12 (FIG. 13) are arranged along the four sides of the convex polygon 30, which is a square, respectively. On the other hand, in the fifth embodiment, the eight transistor rows 12 are arranged along the eight sides of the convex polygon 30 which is a regular octagon. The first bump 21 is arranged corresponding to each of the plurality of transistor rows 12.

The circuit board 100 (FIG. 2) has a first land 101 arranged so as to overlap each of the eight first bumps 21 in a plan view. The output wiring 103 extends from each of the eight first lands 101 toward the outside of the convex polygon 30. An annular output wire 104 surrounds the convex polygon 30 and is connected to the tips of eight output wires 103.

To distinguish each of the eight transistor trains 12. Serial numbers 1 to 8 are sequentially assigned in the first rotation direction (clockwise direction in FIG. 15) of the convex polygon 30 in the circumferential direction. In FIG. 15, the serial number assigned to each transistor row 12 is represented by a number with a pound sign. From the connection point with the output wiring 103 corresponding to the odd-numbered transistor row 12 in the output wiring 104 to the connection point with the output wiring 103 corresponding to the transistor row 12 adjacent to each other in the first rotation direction in the circumferential direction. The midpoint 128 of the part is grounded.

From the connection point with the output wiring 103 corresponding to the even-numbered transistor row 12 of the output wiring 104 to the connection point with the output wiring 103 corresponding to the transistor row 12 adjacent to each other in the first rotation direction in the circumferential direction. The intermediate point of the portion (hereinafter referred to as the output side intermediate point 129) is connected to the signal output terminal 110. One signal output terminal 110 and four output side intermediate points 129 are connected in a tournament manner, and the path length of the signal path from each of the four output side intermediate points 129 to the signal output terminal 110 is determined. All equal.

A part of the output wiring 104 functions as inductors 122 and 123 as in the case of the fourth embodiment. The signal path from the output-side intermediate point 129 to the signal output terminal 110 functions as the inductors 126 and 127. Of the signal paths from the output-side intermediate point 129 to the signal output terminal 110, the signal path from the output-side intermediate point 129 to the first confluence functions as the inductor 126. One terminal of the chip capacitor 124 is connected to the signal path from the first confluence point to the next confluence point when viewed from the output side intermediate point 129. The other terminal of the chip capacitor 124 is grounded. The signal path from the first confluence point seen from the output side intermediate point 129 to the point where the chip capacitor 124 is connected functions as the inductor 127.

Next, the excellent effect of the fifth embodiment will be described.
In the fifth embodiment as well, as in the case of the fourth embodiment, it is possible to suppress the loss generated in the signal path from the transistor row 12 to the signal output terminal 110 and to increase the output. Further, in the fifth embodiment, when the total number of power stage transistors 13 is constant, the length of each of the transistor rows 12 is shortened by increasing the number of the transistor rows 12. As a result, the variation in the operating conditions of the power stage transistor 13 depending on the position of the transistor row 12 can be further reduced.

Next, a modified example of the fifth embodiment will be described. In the fifth embodiment, a regular octagon is adopted as the virtual convex polygon 30, but other general convex polygons may be adopted as the convex polygon 30. In addition, in order to branch the signal path from one signal output terminal 110 to the plurality of transistor rows 12 into a tournament type and make the lengths of the signal paths equal, it is preferable that the number of transistor rows 12 is a power of 2. .. Even when the number of transistor trains 12 is a power of 2, it is not necessary to adopt a convex polygon having a power of 2 as the virtual convex polygon 30. A number of sides corresponding to the number of transistor rows 12 may be selected from the plurality of sides of the virtual convex polygon 30, and the plurality of transistor rows 12 may be arranged along each of the selected sides.

Considering a virtual straight line along which each of the plurality of transistor rows 12 is considered, if the plurality of virtual straight lines constitute at least a part of the plurality of sides of the convex polygon, the plurality of transistor rows 12 may be formed. It can be said that they are arranged along the sides of a virtual convex polygon.

[Sixth Example]
Next, the power amplification module according to the sixth embodiment will be described with reference to FIGS. 16 and 17. Hereinafter, the description of the configuration common to the power amplification module according to the first embodiment shown in the drawings of FIGS. 1 to 5 will be omitted. In the first embodiment, the configuration from the power stage amplifier circuit 45 (FIG. 5) and the power stage amplifier circuit 45 to the signal output terminal 110 (FIG. 5) has been described in detail. In the sixth embodiment, the configuration from the pre-stage amplifier circuit 40 (FIG. 5) to the power stage amplifier circuit 45 (FIG. 5) will be described in detail.

FIG. 16 shows the positional relationship of the plurality of components of the front-stage amplifier circuit 40 and the power-stage amplifier circuit 45 (FIG. 5) provided on the semiconductor chip 10 (FIG. 2) of the power amplification module according to the sixth embodiment in a plan view. It is a figure which shows. The configurations of the two transistor trains 12, the collector wiring 14, the first bump 21, the second bump 22, and the resistance element 46 are the same as those of the power amplification module (FIG. 1) according to the first embodiment. Further, the configurations of the base wiring 15 and the interstage signal wiring 35 are also the same as the configurations of the base wiring 15 (FIG. 3) and the interstage signal wiring 35 (FIG. 3) of the power amplification module according to the first embodiment. The interstage signal wiring 35 is arranged corresponding to each of the two transistor rows 12. A capacitor 36 is formed in a region where the base wiring 15 and the interstage signal wiring 35 overlap in a plan view.

The front-stage amplifier circuit 40 is arranged inside the convex polygon 30 in a plan view. The pre-stage amplifier circuit 40 includes a plurality of pre-stage transistors 42. The plurality of pre-stage transistors 42 are connected to each other in parallel. Each of the plurality of front-stage transistors 42 has a structure similar to that of the power stage transistor 13 (FIGS. 3 and 4) of the power stage amplifier circuit 45 (FIG. 5). The front-stage transistor 42 and the power-stage transistor 13 may have different dimensions in a plan view of each component. The collector wiring 43 connected to the collector of the front-stage transistor 42 is connected to the two interstage signal wirings 35. In FIG. 16, the description of the base ballast resistance element 37 (FIG. 3) and the bias wiring 38 (FIG. 3) is omitted.

The base wiring 44 is connected to each base of the plurality of front-stage transistors 42. One end of one signal input wiring 47 overlaps with a plurality of base wirings 44 in a plan view. Capacitors 48 are formed in the regions where the plurality of base wirings 44 and the signal input wirings 47 overlap each other. The signal input wiring 47 is connected to the signal input bump 49 at the other end. The input signal Pin is input from the circuit board 100 (FIG. 2) to the base of the front-stage transistor 42 via the signal input bump 49, the signal input wiring 47, the capacitor 48, and the base wiring 44. In FIG. 16, the description of the bias circuit of the front-stage transistor 42 is omitted.

The collector wiring 43 connected to the collector of the pre-stage transistor 42 is connected to the power supply bump 53 via a spiral (spiral) inductor 51. Insulation is ensured by the multilayer wiring structure at the portion where the wirings constituting the inductor 51 intersect with each other. The power supply bump 53 is connected to the second power supply wiring 107 of the circuit board 100 (FIG. 2). The power supply voltage Vcc2 is applied from the second power supply wiring 107 to the collector of the front-stage transistor 42 via the inductor 51 and the collector wiring 43.

The inductor 51 and the plurality of capacitors 36 form the second impedance conversion circuit 50. The plurality of capacitors 36 also function as DC cut capacitors that prohibit the inflow of DC current from the power supply voltage Vcc2 to the base of the power stage transistor 13. A plurality of capacitors 36 are arranged corresponding to each of the two rows of transistor rows 12. One inductor 51 is shared by two rows of transistor rows 12.

FIG. 17 is an equivalent circuit diagram of the front stage amplifier circuit 40, the second impedance conversion circuit 50, and the power stage amplifier circuit 45. FIG. 17 shows only one of the two power stage amplifier circuits 45 (FIG. 5).

The collector of the pre-stage transistor 42 constituting the pre-stage amplifier circuit 40 functions as a signal output port of the pre-stage amplifier circuit 40. The collector wiring 43 is connected to the signal output port of the front transistor 42. The high frequency signal amplified by the amplifier circuit 40 in the previous stage is output from the signal output port. The bases of the plurality of power stage transistors 13 constituting the power stage amplifier circuit 45 function as signal input ports. A capacitor 36 is connected to the signal input port of the power stage transistor 13 via the base wiring 15. The second impedance conversion circuit 50 is inserted between the signal output port of the pre-stage amplifier circuit 40 and the signal input port of the plurality of power stage transistors 13.

The plurality of capacitors 36 provided corresponding to the plurality of power stage transistors 13 correspond to the capacitors 52 (FIG. 5) of the second impedance conversion circuit 50 according to the first embodiment. The collectors of the plurality of power stage transistors 13 are connected to the first bump 21 via the collector wiring 14. The emitters of the plurality of power stage transistors 13 are connected to the second bump 22.

Next, the excellent effect of the sixth embodiment will be described.
In the sixth embodiment, the base wiring 15 extends from the signal input port of the power stage transistor 13 toward the inside of the convex polygon 30. Further, the pre-stage amplifier circuit 40 is arranged inside the convex polygon 30 in a plan view. Therefore, the distance from the signal output port of the pre-stage amplifier circuit 40 to the signal input port of the power stage transistor 13 can be shortened for all the transistor trains 12. As a result, the loss in the signal path including the second impedance conversion circuit 50 from the front stage amplifier circuit 40 to the power stage amplifier circuit 45 can be reduced, and the gain of the power amplification module can be kept high.

Further, a plurality of elements of the pre-stage amplifier circuit 40 can be centrally arranged in a narrow region. Therefore, the plurality of front-stage transistors 42 can be easily shared by the plurality of transistor rows 12 of the power stage amplifier circuit 45. Further, in the sixth embodiment, the inductor 51 of the second impedance conversion circuit 50 is shared by the plurality of transistor rows 12 of the power stage amplifier circuit 45. In this way, by sharing a part of the reactance elements of the pre-stage amplifier circuit 40 and the second impedance conversion circuit 50 with the plurality of transistor trains 12, the second impedance conversion circuit 50 can be used in the semiconductor chip 10 (FIG. 2). The occupied area of some reactance elements can be reduced.

Next, a modified example of the sixth embodiment will be described. In the sixth embodiment, the inductor 51, which is the inductance element of the second impedance conversion circuit 50, is shared between the two transistor rows 12. As another configuration, the capacitive element may be shared between the two transistor trains 12. Further, in the sixth embodiment, a spiral inductor 51 is used, but an arc-shaped or spiral-shaped inductor may be used depending on the required inductance.

[7th Example]
Next, the power amplification module according to the seventh embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the power amplification module (FIGS. 16 and 17) according to the sixth embodiment will be omitted.

FIG. 18 shows the positional relationship of the plurality of components of the front-stage amplifier circuit 40 and the power-stage amplifier circuit 45 (FIG. 5) provided on the semiconductor chip 10 (FIG. 2) of the power amplification module according to the seventh embodiment in a plan view. It is a figure which shows. In the sixth embodiment, two rows of transistor rows 12 are arranged. On the other hand, in the seventh embodiment, four transistor rows 12 are arranged as in the case of the fourth embodiment (FIG. 13). An interstage signal wiring 35 is arranged corresponding to each of the four transistor rows 12.

In the seventh embodiment as well, as in the case of the sixth embodiment, the front stage amplifier circuit 40 and the inductor 51 are arranged inside the convex polygon 30 in a plan view. The collector wiring 43 connected to the collectors (signal output ports) of the plurality of front-stage transistors 42 constituting the front-stage amplifier circuit 40 is connected to the four interstage signal wirings 35. A capacitor 36 formed in a region where the interstage signal wiring 35 and the base wiring 15 overlap in a plan view constitutes the second impedance conversion circuit 50 together with the inductor 51.

Next, the excellent effect of the seventh embodiment will be described.
In the seventh embodiment as in the case of the sixth embodiment, the loss in the signal path including the second impedance conversion circuit 50 from the front stage amplifier circuit 40 to the power stage amplifier circuit 45 is reduced, and the power amplification module The gain can be kept high. Further, a plurality of elements of the pre-stage amplifier circuit 40 can be centrally arranged in a narrow region.

[8th Example]
Next, the power amplification module according to the eighth embodiment will be described with reference to the drawings from FIGS. 19A to 23D. Hereinafter, the description of the configuration common to the power amplification module according to the first embodiment shown in the drawings of FIGS. 1 to 5 will be omitted.

FIG. 19A is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the eighth embodiment. In FIG. 19A, similarly to FIG. 1, the conductor film provided on the semiconductor chip 10 (FIG. 2) is provided with relatively dark hatching, and is relative to the conductor film provided on the circuit board 100 (FIG. 2). It has a light hatching.

First, the semiconductor chip 10 (FIG. 2) will be described. In the eighth embodiment as well, as in the case of the first embodiment (FIG. 1), the two rows of transistor rows 12 are arranged along the two opposite sides of the rectangular convex polygon 30. There is.

In the eighth embodiment, each of the two rows of transistor rows 12 is divided into two blocks at the center in the length direction thereof. The plurality of power stage transistors 13 belong to any block. One of the two blocks is defined as the first block 12A and the other is defined as the second block 12B. Further, the first block 12A and the second block 12B are defined so that the first block 12A and the second block 12B are alternately arranged in the circumferential direction of the convex polygon 30. When two rows of transistor rows 12 are arranged parallel to each other, the first block 12A of one transistor row 12 faces the second block 12B of the other transistor row 12.

The collector wiring 14, the first bump 21, and the interstage signal wiring 35 are arranged corresponding to each of the plurality of blocks. The collector wiring 14 is connected to collectors (signal output ports) of a plurality of power stage transistors 13 in the corresponding block. The plurality of first bumps 21 are connected to the corresponding collector wiring 14. The interstage signal wiring 35 overlaps with the base wiring 15 drawn from the bases (signal input ports) of the plurality of power stage transistors 13 in the corresponding blocks. A capacitor 36 is formed in the overlapping region of both.

A signal input port of a power stage transistor 13 belonging to the first block 12A (hereinafter, may be referred to as a signal input port of the first block 12A) via an interstage signal wiring 35, a capacitor 36, and a base wiring 15. A high-frequency input signal Pin + is input. An input signal Pin− having a phase opposite to that of the input signal Pin + is input to the signal input port of the power stage transistor 13 belonging to the second block 12B (hereinafter, may be referred to as a signal input port of the second block 12B). In this way, the differential signal is input to the signal input port of the first block 12A and the signal input port of the second block 12B. The circuit configuration for generating the differential signal will be described later with reference to FIG.

A capacitor 68 having a MIM structure connects the collector wirings 14 corresponding to the first block 12A and the second block 12B in the same transistor row 12 to each other.

Next, the circuit board 100 (FIG. 2) will be described. In a plan view, the first land 101 is arranged at a position overlapping the four first bumps 21. The first land 101 corresponding to the second block 12B of one transistor row 12 and the first land 101 corresponding to the first block 12A of the other transistor row 12 are connected by the primary coil 131 of the first transformer 130. Has been done. In other words, the primary coil 131 has the number of the first land 101 corresponding to the second block 12B of each of the plurality of transistor rows 12 and the number of transistor rows 12 in the first rotation direction in the circumferential direction of the convex polygon 30. It is connected to the first land 101 corresponding to the first block 12A of the transistor row 12 at the position moved by one row.

Each of the two primary coils 131 is arranged outside the convex polygon 30 and substantially makes a half circumference around the convex polygon 30. The lengths of the two primary coils 131 are approximately equal. Here, "almost equal" means that, as will be described later with reference to FIG. 21, a variation in length that does not interfere with the differential operation of the power stage amplifier circuit 45 is allowed. As an example, if the difference between the lengths of the two primary coils (actual lengths, not electrical lengths) is 20% or less of the average value of the two lengths, it can be said to be "almost equal". Two primary coils 131 are arranged so as to surround almost the entire circumference of the convex polygon 30.

Each of the primary coils 131 has a first portion 131A extending outward from the convex polygon 30 from the first land 101 in a plan view, and a second portion 131A extending outward from the tip of the first portion 131A in the circumferential direction of the convex polygon 30. Includes portion 131B. The shape of the first portion 131A in a plan view is trapezoidal. The first portion 131A is connected to the first land 101 at the lower bottom of the trapezoid and is connected to the second portion 131B at the upper bottom. The lower bottom is longer than the upper bottom. Of the two trapezoidal legs, the leg located on the center side of the transistor row 12 and the lower base are orthogonal to each other.

Each of the primary coils 131 is connected to the first power supply wiring 106 at substantially the center in the length direction. Here, "almost the center" means that, as will be described later with reference to FIG. 21, the position variation to the extent that the differential operation of the power stage amplifier circuit 45 is not hindered is allowed. The power supply voltage Vcc1 is applied to the collector of the power stage transistor 13 from the first power supply wiring 106 via the primary coil 131, the first land 101, the first bump 21, and the collector wiring 14.

The secondary coil 132 of the first transformer 130 is arranged along the second portion 131B of the two primary coils 131 in a plan view. The secondary coil 132 makes substantially two orbits around the convex polygon 30. One end of the secondary coil 132 is grounded, and the other end is connected to the signal output terminal 110 via the first auxiliary impedance conversion circuit 135. The first lap portion of the secondary coil 132 is arranged inside the second portion 131B of the primary coil 131, starting from the grounded end, and the second lap portion is the primary coil 131. It is arranged outside the second portion 131B. With this configuration, the strength of coupling with the primary coil 131 is equalized between the first and second laps of the secondary coil 132. The secondary coils 132 are dispersedly arranged in a plurality of layers of the surface layer or the inner layer of the circuit board 100 (FIG. 2).

Next, with reference to FIG. 19B, a group in which a plurality of power stage transistors 13 are classified will be described.
FIG. 19B is a schematic diagram for explaining the difference between the transistor row 12 and the group 70. As described with reference to FIG. 19A, each of the two transistor trains 12 is divided into a first block 12A and a second block 12B. The power stage transistor 13 of the first block 12A of one transistor row 12 and the power stage transistor 13 of the second block 12B of the other transistor row 12 belong to one group 70. The primary coil 131 connects the power stage transistor 13 of the first block 12A and the power stage transistor 13 of the second block 12B in the same group 70.

The collectors of the plurality of power stage transistors 13 belonging to each of the first block 12A and the second block 12B are short-circuited with each other. A plurality of power stage transistors 13 in which collectors are short-circuited with each other belong to the same group. Further, a plurality of power stage transistors 13 in which the collectors are connected to each other via a common primary coil 131 even if the collectors are not short-circuited to each other also belong to the same group. In this way, the plurality of power stage transistors 13 can be divided into two groups 70 depending on whether or not they are connected to the common primary coil 131.

FIG. 20 is a diagram showing the positional relationship of the components of the pre-stage amplifier circuit 40 and the circuit that generates the differential signals input to the plurality of power stage transistors 13 in a plan view. A circuit for generating a differential signal and a pre-stage amplifier circuit 40 are provided on the semiconductor chip 10 (FIG. 2).

The front stage amplifier circuit 40 is arranged inside the convex polygon 30. The pre-stage amplifier circuit 40 is composed of two pre-stage transistors 42 connected in parallel to each other, similarly to the pre-stage amplifier circuit 40 of the power amplification module (FIG. 16) according to the sixth embodiment. The base wiring 44 connected to the base of the pre-stage transistor 42 is connected to the signal input wiring 47 via the capacitor 48. The signal input wiring 47 is connected to the signal input bump 49. A high-frequency input signal Pin is input from the signal input bump 49 to the base of the pre-stage transistor 42 via the signal input wiring 47, the capacitor 48, and the base wiring 44.

One end of the primary coil 141 of the second transformer 140 is connected to the collector wiring 43 connected to the collector (signal output port) of the front transistor 42. The other end of the primary coil 141 is grounded. The primary coil 141 surrounds the front-stage transistor 42 and makes two rounds around the front-stage transistor 42. In FIG. 20, relatively light hatching is attached to the primary coil 141, the collector wiring 43, and the signal input wiring 47.

Interstage signal wiring 35 is arranged corresponding to the first block 12A and the second block 12B of the two transistor trains 12, respectively. Two interstage signal wirings 35 corresponding to the first block 12A and the second block 12B of the same transistor row 12 are connected by a capacitor 69 having a MIM structure.

The interstage signal wiring 35 corresponding to the second block 12B of one transistor row 12 and the interstage signal wiring 35 corresponding to the first block 12A of the other transistor row 12 are connected to the secondary coil 142 of the second transformer 140. Connects. The pre-stage amplifier circuit 40 is arranged between the two secondary coils 142. The lengths of the two secondary coils 142 are approximately equal and are grounded approximately in the center of each length direction. Here, "almost equal" and "almost center" mean variations in length and position that do not interfere with the differential operation of the power stage amplifier circuit 45, as will be described later with reference to FIG. Means to tolerate. A part of the secondary coil 142 is arranged along the primary coil 141, and the primary coil 141 and the secondary coil 142 form the second transformer 140. The portion of the secondary coil 142 of the second transformer 140 along the primary coil 141 is arranged between the first and second laps of the primary coil 141.

The connection points between the secondary coil 142 and the interstage signal wiring 35 are arranged at positions biased toward the center side in the length direction of the transistor train 12 with respect to the length direction of the interstage signal wiring 35. That is, the connection points between the secondary coil 142 and the interstage signal wiring 35 are biased in the direction in which the number of turns of each of the two secondary coils 142 increases. The secondary coil 142 is connected to the base (signal input port) of the power stage transistor 13 via the interstage signal wiring 35, the capacitor 36, and the base wiring 15. In FIG. 20, the description of the circuit that supplies power to the preceding transistor 42 is omitted.

FIG. 21 is an equivalent circuit diagram of the power amplification module according to the eighth embodiment. The signal output port of the pre-stage amplifier circuit 40 and the signal input port of the power stage amplifier circuit 45 are connected via the second transformer 140. The primary coil 141 is connected between the signal output port of the pre-stage amplifier circuit 40 and the ground. Two secondary coils 142 are coupled to the primary coil 141.

The secondary coil 142 connects the signal input port of the first block 12A of one transistor row 12 and the signal input port of the second block 12B of the other transistor row 12, respectively. Each of the secondary coils 142 is grounded at the center in the longitudinal direction. The second transformer 140 inputs high-frequency signals of opposite phases to the power stage amplifier circuit 45 of the first block 12A and the power stage amplifier circuit 45 of the second block 12B. Further, in-phase high-frequency signals are input to the power stage amplifier circuits 45 of the two first blocks 12A, and in-phase high-frequency signals are also input to the power stage amplifier circuits 45 of the two second blocks 12B.

The second transformer 140 has a function of matching the output impedance of the pre-stage amplifier circuit 40 with the input impedance of the power stage amplifier circuit 45, similarly to the second impedance conversion circuit 50 of the power amplification module (FIG. 5) according to the first embodiment. Have. For example, the turns ratio of the primary coil 141 having approximately two turns to the secondary coil 142 having approximately 1/2 turns is approximately 4: 1. The output impedance of the pre-stage amplifier circuit 40 is converted to about 1/16 times according to the ratio of the number of turns of the primary coil 141 and the secondary coil 142. Further, the output impedance is further converted to 1/4 times by the differential operation of the power stage amplifier circuit 45. As a result, the output impedance of the pre-stage amplifier circuit 40 is converted to about 1/64 times.

Further, the second transformer 140 has a function of converting the high frequency signal output from the front stage amplifier circuit 40 into a differential signal and inputting it to the power stage amplifier circuit 45. One front-stage amplifier circuit 40 and one second transformer 140 are shared by two rows of transistor rows 12. Capacitors 68 and 69 connected to the signal input port and the signal output port of the power stage amplifier circuit 45 are provided for stabilizing high frequency operation.

The signal output port of the first block 12A of one transistor row 12 and the signal output port of the second block 12B of the other transistor row 12 are connected by the primary coil 131 of the first transformer 130. The primary coil 131 is coupled to the secondary coil 132 of the first transformer 130. The power supply voltage Vcc1 is applied to the central position in the length direction of the primary coil 131. The primary coil 131 is AC grounded at the center in the length direction.

The first transformer 130 has a function of converting the output impedance of the power stage amplifier circuit 45 into a high impedance, and also has a function of synthesizing the power of high frequency signals output from the plurality of power stage amplifier circuits 45. The high frequency signal induced in the secondary coil 132 of the first transformer 130 is output from the signal output terminal 110 via the first auxiliary impedance conversion circuit 135. The first transformer 130 and the first auxiliary impedance conversion circuit 135 have the same functions as the first impedance conversion circuit 120 of the power amplification module (FIG. 5) according to the first embodiment. As a result, the output impedance of the power amplification module can be matched with the input impedance of a load such as an antenna connected to the signal output terminal 110. If sufficient impedance matching can be obtained with only the first transformer 130, the first auxiliary impedance conversion circuit 135 is unnecessary.

Next, the excellent effect of the eighth embodiment will be described.
A plurality of power stage transistors 13 belonging to the first block 12A of one transistor row 12 and a plurality of power stage transistors 13 belonging to the second block 12B of the other transistor row 12 belong to the same group 70. The power stage transistor 13 of the above is grouped into two groups 70. At this time, the two primary coils 131 of the first transformer 130 can be considered as individual reactance elements arranged corresponding to each of the two groups 70. Since the individual reactance elements of the first transformer 130 are arranged for each group 70 of the plurality of power stage transistors 13, the individual reactance elements are compared with the case where one reactance element is connected to all of the plurality of power stage transistors 13. Can be arranged close to the signal output port of the power stage transistor 13.

For example, in the eighth embodiment, four first lands 101 are arranged corresponding to the first block 12A and the second block 12B of the two rows of transistor rows 12, respectively, and each of the first lands 101 is arranged. , Connected to the primary coil 131 of the first transformer 130. Therefore, the signal path length from the signal output port of the power stage transistor 13 to the input end of the first transformer 130 can be shortened without depending on the arrangement of the transistor trains 12. Therefore, as in the case of the first embodiment, it is possible to suppress the loss generated in the signal path from the signal output port of the plurality of power stage transistors 13 to the signal output terminal 110 and to increase the output. ..

Further, in the eighth embodiment, the impedance conversion ratio can be changed by changing the turns ratio between the primary coil 141 and the secondary coil 142 of the second transformer 140. This makes it possible to bring the impedance matching between the pre-stage amplifier circuit 40 and the power stage amplifier circuit 45 closer to the ideal state. As a result, it becomes possible to increase the gain of the power amplification module. Further, in the eighth embodiment as well as in the first embodiment (drawings of FIGS. 1 to 5), the loss generated in the signal path from the signal output port of the plurality of power stage transistors 13 to the signal output terminal 110 is generated. It is possible to suppress and increase the output. Further, there are an excellent effect that the variation in operation among the plurality of power stage transistors 13 is reduced, an excellent effect that it is advantageous in reducing the parasitic resistance and the parasitic inductance, and an excellent effect that the heat dissipation effect can be enhanced. can get.

Next, with reference to FIG. 22, a modified example in which the turns ratio between the primary coil 141 and the secondary coil 142 of the second transformer 140 is different from that in the eighth embodiment will be described.

FIG. 22 is a diagram showing a circuit for generating differential signals input to a plurality of power stage transistors 13 of the power amplification module according to the present modification, and a positional relationship of the components of the pre-stage amplifier circuit 40 in a plan view. In FIG. 22, the description of the capacitor 69 (FIG. 20) is omitted.

In the eighth embodiment, each of the secondary coils 142 connects the signal input port of the first block 12A and the signal input port of the second block 12B of the transistor train 12 which are different from each other. On the other hand, in this modification, each of the secondary coils 142 connects the signal input port of the first block 12A and the signal input port of the second block 12B of the same transistor row 12. Due to the difference in the connection configuration of the secondary coil 142, in this modified example, each of the secondary coils 142 goes around the pre-stage amplifier circuit 40 approximately once. Each of the secondary coils 142 is grounded at the center in the length direction as in the case of the eighth embodiment.

Further, in the eighth embodiment, the number of turns of the primary coil 141 of the second impedance conversion circuit 50 is about two turns, but in this modified example, it is one turn. Therefore, in this modification, the turns ratio between the primary coil 141 and the secondary coil 142 of the second transformer 140 is about 1: 1. Therefore, impedance conversion according to the turns ratio is not performed. By the differential operation of the power stage amplifier circuit 45, the output impedance of the front stage amplifier circuit 40 is converted to 1/4 times. Therefore, as a whole, the output impedance of the pre-stage amplifier circuit 40 is converted to 1/4 times.

As in the eighth embodiment or the present modification, the turns ratio between the primary coil 141 and the secondary coil 142 of the second transformer 140 may be set according to the required impedance conversion ratio.

Next, the excellent effect based on the shape of the first portion 131A (FIG. 19A) of the primary coil 131 will be described with reference to the drawings from FIGS. 23A to 23D.

FIG. 23A is a diagram showing the shape of the primary coil 131 of the power amplification module according to the eighth embodiment in a plan view. In a plan view, a region in which two transistor rows 12, four first bumps 21, and four first lands 101 are arranged is surrounded by two primary coils 131. Each of the two primary coils 131 connects two first lands 101 facing each other with the convex polygon 30 in between in a plan view.

The first portion 131A of the primary coil 131 is connected to the first land 101 at one end thereof, and extends in a direction away from the transistor row 12 (a direction toward the outside of the convex polygon 30). The second portion 131B extends from the tip of the first portion 131A toward one side in a direction parallel to the length direction of the transistor row 12 (circumferential direction of the convex polygon 30).

As described with reference to FIG. 19A, the shape of the first portion 131A in a plan view is trapezoidal. The first portion 131A is connected to the first land 101 at the lower bottom of the trapezoid and is connected to the second portion 131B at the upper bottom. The lower bottom is longer than the upper bottom. Of the two trapezoidal legs, the leg located on the center side of the transistor row 12 and the lower base are orthogonal to each other. That is, the first portion 131A is unevenly distributed from the first land 101 toward the tip of the first portion 131A in the direction in which the length of the second portion 131B becomes longer.

23B, 23C, and 23D are diagrams showing the shapes of the first portion 131A in a plan view according to a comparative example, respectively. In the comparative example shown in FIG. 23B, the first portion 131A is thinner in the entire length direction as compared with the first portion 131A according to the eighth embodiment. Therefore, the parasitic resistance and the parasitic inductance of the first portion 131A become large.

In the comparative example shown in FIG. 23C, the first portion 13A is shorter than in the case of the comparative example shown in FIG. 23B. In this case, the parasitic resistance and the parasitic inductance of the first portion 131A itself are reduced, but the ends of the first land 101 and the second portion 131B come closer to each other. As a result, the magnetic coupling between the two becomes large. Of the second portion 131B, the portion magnetically coupled to the first land 101 does not function as the primary coil of the first transformer 130, and the performance of the first transformer 130 deteriorates.

In the comparative example shown in FIG. 23D, the first portion 131A is thicker than in the case of the comparative example shown in FIG. 23B. In this case, the portion of the second portion 131B connected to the first portion 131A does not function as the primary coil of the first transformer 130, and the performance of the first transformer 130 deteriorates.

In the eighth embodiment, the average width of the first portion 131A is wider than that of the comparative example of FIG. 23B. Therefore, it is possible to suppress an increase in the parasitic resistance and the parasitic inductance of the first portion 131A. Further, in the eighth embodiment, the end portion of the second portion 131B is moved away from the first land 101 as compared with the comparative example of FIG. 23C. Therefore, the increase of the magnetic coupling between the first land 101 and the second portion 131B is suppressed. Further, in the eighth embodiment, the upper base of the trapezoid corresponding to the shape of the first portion 131A in a plan view is shorter than the lower base. Therefore, the expansion of the portion of the second portion 131B that does not function as the primary coil of the first transformer 130 is suppressed. In the eighth embodiment, it is possible to suppress a decrease in the output of the power amplification module due to these effects.

The shape of the first portion 131A of the primary coil 131 in a plan view is not limited to the trapezoidal shape. For example, it is preferable that the width of the first portion 131A is narrowed from the first land 101 toward the tip of the first portion 131A. Here, the width direction of the first portion 131A is defined as a direction parallel to the length direction of the transistor train 12 corresponding to the first portion 131A. Further, it is preferable that the line 133 connecting the center points in the width direction of the first portion 131A is inclined in the direction in which the second portion 131B becomes longer, with reference to the direction orthogonal to the length direction of the transistor row 12.

[9th Example]
Next, the power amplification module according to the ninth embodiment will be described with reference to FIGS. 24, 25, and 26. Hereinafter, the description of the configuration common to the power amplification module (FIGS. 19A, 20 and 21) according to the eighth embodiment will be omitted.

FIG. 24 is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the ninth embodiment. In FIG. 24, similarly to FIG. 19A, the conductor film provided on the semiconductor chip 10 (FIG. 2) is provided with relatively dark hatching, and is relative to the conductor film provided on the circuit board 100 (FIG. 2). It has a light hatching.

In the eighth embodiment (FIG. 19A), two rows of transistor rows 12 are arranged, but in the ninth embodiment, the transistor rows 12 are arranged along the four sides of the square convex polygon 30. Has been done. Each of the transistor rows 12 is divided into a first block 12A and a second block 12B at the center in the length direction of the transistor rows 12 as in the case of the eighth embodiment. In a plan view, the first block 12A and the second block 12B are alternately arranged in the circumferential direction of the convex polygon 30.

Similar to the case of the eighth embodiment (FIG. 19A), the collector wiring 14 on the semiconductor chip 10 (FIG. 2), the first bump 21, the interstage signal wiring 35, and the first on the circuit board 100 (FIG. 2). Lands 101 are arranged corresponding to the first block 12A and the second block 12B of the transistor row 12. A capacitor 68 having a MIM structure connects the collector wiring 14 corresponding to the first block 12A of the same transistor row 12 and the collector wiring 14 corresponding to the second block 12B. The capacitor 68 is provided for stabilizing high frequency operation.

The first land 101, which is adjacent to the convex polygon 30 in the circumferential direction and corresponds to the first block 12A and the second block 12B belonging to different transistor rows 12, is connected by the primary coil 131 of the first transformer 130. There is. Each of the primary coils 131 is composed of two first portions 131A and a second portion 131B connecting the two first portions 131A, as in the case of the eighth embodiment (FIG. 19A). The four primary coils 131 have the same length and are connected to the first power supply wiring 106 at the center in the length direction.

In the eighth embodiment, each of the primary coils 131 (FIG. 19A) makes a substantially half circumference around the convex polygon 30, but in the ninth embodiment, each of the primary coils 131 is a convex polygon 30. It makes almost 1/4 lap around. Four primary coils 131 make a substantially circle around the convex polygon 30.

In the eighth embodiment, the secondary coil 132 (FIG. 19A) of the first transformer 130 makes substantially two orbits around the convex polygon 30, but in the ninth embodiment, the secondary coil 132 of the first transformer 130 Makes almost one round around the convex polygon 30.

A high-frequency input signal Pin + is input to the signal input port of the first block 12A. An input signal Pin− having a phase opposite to that of the input signal Pin + is input to the signal input port of the second block 12B.

FIG. 25 is a diagram showing the positional relationship in a plan view of the circuit that generates the differential signals input to the plurality of power stage transistors 13 and the components of the pre-stage amplifier circuit 40. A circuit for generating a differential signal and a pre-stage amplifier circuit 40 are provided on the semiconductor chip 10 (FIG. 2). The pre-stage amplifier circuit 40 is arranged inside the convex polygon 30 in a plan view.

The signal input port of the first block 12A and the signal input port of the second block 12B, which are adjacent to each other in the circumferential direction of the convex polygon 30 and belong to different transistor rows 12, are connected by a secondary coil 142. In the eighth embodiment, each of the two secondary coils 142 (FIG. 20) makes about half a circumference around the front amplifier circuit 40, but in the ninth embodiment, each of the four secondary coils 142. However, it orbits about 1/4 around the pre-stage amplifier circuit 40. The four secondary coils 142 have the same length and are grounded at the center in the length direction.

The interstage signal wiring 35 corresponding to the first block 12A and the second block 12B of the same transistor row 12 is connected by a capacitor 69 having a MIM structure. The capacitor 69 has a function of stabilizing high frequency operation.

In the eighth embodiment, the front-stage amplifier circuit 40 (FIG. 20) is composed of two front-stage transistors 42, but in the ninth embodiment, the front-stage amplifier circuits 40 are connected to each other in parallel with four. It is composed of a front-stage transistor 42. A signal input wiring 47 is connected to the base of the four front-stage transistors 42 via a capacitor 48. The primary coil 141 of the second transformer 140 connected to the collector (signal output port) of the pre-stage transistor 42 makes two rounds around the pre-stage amplifier circuit 40. In FIG. 25, the primary coil 141 and the signal input wiring 47 are provided with relatively light hatching.

FIG. 26 is an equivalent circuit diagram of the power amplification module according to the ninth embodiment. A second transformer 140 is composed of a primary coil 141 and four secondary coils 142. The second transformer 140 has a function of an impedance matching circuit that converts the output impedance of the front stage amplifier circuit 40 and matches it with the input impedance of the power stage amplifier circuit 45. Further, the second transformer 140 is a differential signal that supplies high frequency signals of opposite phases to the power stage amplifier circuit 45 corresponding to the first block 12A and the power stage amplifier circuit 45 corresponding to the second block 12B. Functions as a generator circuit.

In the ninth embodiment, the turns ratio of the primary coil 141 having approximately two turns of the second transformer 140 to the secondary coil 142 having about 1/4 turn each is about 8: 1. The output impedance of the pre-stage amplifier circuit 40 is converted to about 1/64 times by this ratio of the number of turns. Further, the output impedance is further converted to 1/4 times by the differential operation of the power stage amplifier circuit 45. As a result, the output impedance of the pre-stage amplifier circuit 40 is converted to about 1/256 times.

The first transformer 130 is composed of four primary coils 131 and a secondary coil 132. The first transformer 130 and the first auxiliary impedance conversion circuit 135 function as an impedance conversion circuit that converts the output impedance of the power stage amplifier circuit 45 into a high impedance. As a result, the output impedance of the power stage amplifier circuit 45 can be matched with the input impedance of a load such as an antenna. If sufficient impedance matching can be achieved with only the first transformer 130, the first auxiliary impedance conversion circuit 135 may be omitted. Further, the first transformer 130 has a function of synthesizing the power of the high frequency signal output from the eight power stage amplifier circuits 45.

In the ninth embodiment as well, as in the case of the eighth embodiment, the primary coil 131 of the first transformer 130 is arranged for each group of the plurality of power stage transistors 13 grouped into a plurality of groups. .. The primary coil 131 can be considered as an individual reactance element of the first transformer 130 arranged corresponding to each of the plurality of groups.

Next, the excellent effect of the ninth embodiment will be described.
In the ninth embodiment as well, as in the case of the eighth embodiment (FIGS. 19A, 20 and 21), the loss generated in the signal path from the signal output port of the plurality of power stage transistors 13 to the signal output terminal 110 It is possible to suppress the above and increase the output. Further, in the ninth embodiment, since the transistor rows 12 are arranged in four rows, the number of power stage transistors 13 can be increased as compared with the case of the eighth embodiment, and higher output can be achieved.

Further, in the ninth embodiment, the impedance conversion ratio can be changed by changing the turns ratio between the primary coil 141 and the secondary coil 142 of the second transformer 140. This makes it possible to bring the impedance matching between the pre-stage amplifier circuit 40 and the power stage amplifier circuit 45 closer to the ideal state. As a result, it becomes possible to increase the gain of the power amplification module.

Next, with reference to FIGS. 27 and 28, a modified example in which the turns ratio between the primary coil 141 and the secondary coil 142 of the second transformer 140 is different from that in the ninth embodiment will be described. In FIGS. 27 and 28, the primary coil 141 is provided with relatively light hatching, and the secondary coil 142 is provided with relatively dark hatching.

FIG. 27 shows the configuration of the plurality of power stage transistors 13, the second transformer 140, and the pre-stage amplifier circuit 40 of the second transformer 140 of the power amplification module according to the modified example in which the turns ratio of the second transformer 140 is about 2: 1. It is a figure which shows the positional relationship in the plan view of an element.

In the ninth embodiment, the signal input port of the first block 12A and the signal input port of the second block 12B, which are adjacent to each other in the circumferential direction of the convex polygon 30 and belong to different transistor rows 12, are connected by a secondary coil 142. ing. On the other hand, in this modification, the signal input port of the first block 12A of one of the two transistor rows 12 along the opposite sides of the convex polygon 30 and the other transistor row 12 The signal input port of the second block 12B is connected by the secondary coil 142. The primary coil 141 of the second transformer 140 goes around the pre-stage amplifier circuit 40 once.

In this modification, the turns ratio of the second transformer 140 is about 2: 1. The output impedance of the pre-stage amplifier circuit 40 is converted to about 1/4 times by this ratio of the number of turns. Further, the output impedance is further converted to 1/4 times by the differential operation of the power stage amplifier circuit 45. As a result, the output impedance of the pre-stage amplifier circuit 40 is converted to about 1/16 times.

FIG. 28 shows the configuration of the plurality of power stage transistors 13, the second transformer 140, and the pre-stage amplifier circuit 40 of the second transformer 140 of the power amplification module according to the modified example in which the turns ratio of the second transformer 140 is about 4: 3. It is a figure which shows the positional relationship in the plan view of an element.

In that the signal input ends of the first block 12A and the signal input ends of the second block 12B, which are adjacent to each other in the circumferential direction of the convex polygon 30 and belong to different transistor rows 12, are connected by the secondary coil 142. This is common to the modified example and the ninth embodiment. However, in the ninth embodiment, each of the secondary coils 142 orbits about 1/4 of the circumference of the pre-stage amplifier circuit 40, whereas in this modified example, each of the secondary coils 142 is a pre-stage amplifier circuit. It makes about 3/4 laps around 40.

The primary coil 141 of the second transformer 140 goes around the pre-stage amplifier circuit 40 once. The primary coil 141 is composed of two annular wires connected in parallel to each other, but the number of turns of the primary coil is one. 2 on the inside of the annular wiring on the inner peripheral side, between the annular wiring on the inner peripheral side and the annular wiring on the outer peripheral side, and outside the annular wiring on the outer peripheral side, which constitute the primary coil 141. The next coil 142 is arranged. The reason why the primary coil 141 is composed of two annular wires is to reduce the variation in the strength of coupling between each of the secondary coils 142 and the primary coil 141.

In this modification, the turns ratio of the second transformer 140 is about 4: 3. The output impedance of the pre-stage amplifier circuit 40 is converted to about 9/16 times by this ratio of the number of turns. Further, the output impedance is further converted to 1/4 times by the differential operation of the power stage amplifier circuit 45. As a result, the output impedance of the pre-stage amplifier circuit 40 is converted to about 9/64 times.

By adjusting the turns ratio of the second transformer 140 as in the modified examples shown in FIGS. 27 and 28, the impedance conversion ratio of the output impedance of the pre-stage amplifier circuit 40 can be changed. The turns ratio of the second transformer 140 may be selected according to the impedance conversion ratio required to match the impedance between the pre-stage amplifier circuit 40 and the power stage amplifier circuit 45. For example, the number of turns of the primary coil 141 of the second transformer 140 may be selected from an arbitrary integer.

When the transistor rows 12 are arranged in two rows as in the eighth embodiment (FIGS. 19A and 20), the number of turns of the secondary coil 142 may be selected from a value obtained by an integral multiple of about 1/2. When four transistor rows 12 are arranged as in the ninth embodiment (FIGS. 24 and 25), the number of turns of the secondary coil 142 may be selected from a value obtained by an integral multiple of about 1/4.

[Connection form of the secondary coil of the second transformer]
Next, referring to the drawings from FIGS. 29A to 31F, the connection form of the secondary coil of the second transformer 140 applied to the power amplification module according to the eighth embodiment, the ninth embodiment, and these modifications. Will be described.

The drawings from FIGS. 29A to 29D are schematic views showing a connection form of the secondary coil 142 of the second transformer 140 when the transistor rows 12 are arranged in two rows. Transistor rows 12 are arranged along two sides of the rectangular convex polygon 30 facing each other. Each of the transistor rows 12 is divided into a first block 12A and a second block 12B. The first block 12A and the second block 12B are arranged so that the direction from the first block 12A to the second block 12B in each of the transistor rows 12 is equal to the direction of rotating clockwise in the circumferential direction of the convex polygon 30. Define. In the drawings from FIGS. 29A to 29D, only one of the plurality of secondary coils 142 is displayed.

The signal input port of each second block 12B of the transistor row 12 and the first block 12A of the transistor row 12 at a position moved by m rows in the number of transistor rows 12 clockwise in the circumferential direction of the convex polygon 30. The signal input port of is connected by a secondary coil 142. Here, the parameter m is a natural number.

FIG. 29A corresponds to the case of m = 1. This connection configuration corresponds to the eighth embodiment shown in FIG.

FIG. 29B corresponds to the case of m = 2. That is, the signal input port of the second block 12B of the same transistor row 12 and the signal input oil of the first block 12A are connected by a secondary coil 142 that makes about one revolution in the circumferential direction of the convex polygon 30. This connection configuration corresponds to the modified example shown in FIG.

FIG. 29C corresponds to the case of m = 3. The combination of the first block 12A and the second block 12B to which the signal input ports are connected is the same as in the case of m = 1 (FIG. 29A), but in the case of m = 3, the secondary coil 142 is The convex polygon 30 makes about 1.5 turns in the circumferential direction.

FIG. 29D corresponds to the case of m = 4. The combination of the first block 12A and the second block 12B to which the signal input ports are connected is the same as in the case of m = 2 (FIG. 29B), but in the case of m = 4, the secondary coil 142 is It makes about two turns in the circumferential direction of the convex polygon 30.

The drawings from FIGS. 30A to 31F are schematic views showing a connection form of the secondary coil 142 of the second transformer 140 when four transistor rows 12 are arranged. Transistor rows 12 are arranged along the four sides of the square convex polygon 30. Each of the transistor rows 12 is divided into a first block 12A and a second block 12B. Similar to the case shown in the drawings of FIGS. 29A to 29D, the direction from the first block 12A to the second block 12B in each of the transistor rows 12 is the direction in which the convex polygon 30 rotates clockwise in the circumferential direction. The first block 12A and the second block 12B are defined so as to be equal to. In the drawings from FIGS. 30A to 31F, only one of the plurality of secondary coils 142 is displayed.

The secondary coil 142 makes the signal input port of each second block 12B of the transistor row 12 and the transistor row 12 the number of transistor rows 12 clockwise or counterclockwise in the circumferential direction of the convex polygon 30 m. The secondary coil 142 is connected to the signal input port of the first block 12A of the transistor row 12 at the position moved by the row. Here, the parameter m is a natural number. 30A, 30C, 30E, 31A, 31C, 31E are examples of clockwise movement, m = 1, m = 2, m = 3, m = 4, m = 5, m, respectively. Corresponds to the case of = 6. 30B, 30D, 30F, 31B, 31D, 31F are examples of counterclockwise movement, m = 1, m = 2, m = 3, m = 4, m = 5, respectively. This corresponds to the case of m = 6.

By changing the parameter m, the turns ratio of the second transformer 140 can be changed, and as a result, the impedance conversion ratio can be changed. The number of turns of the secondary coil 142 of the second transformer 140 _{is expressed as m 2,} and the number of turns of the primary coil 141 is expressed _{as m 1.} When the transistor rows 12 are arranged in two rows, the number of turns m ₂ of the secondary coil can be set to an integral multiple of about 1/2, and when the transistor rows 12 are arranged in four rows, the secondary coil is secondary. The number of turns m _{2 of the} coil can be set to an integral multiple of about 1/4.

Depending on the turns ratio of the second transformer 140, the output impedance of the preamplifier circuit 40 _{(m 2 /} m ¹⁾ is converted to ^2-fold. Further, the impedance is converted to 1/4 times by the differential operation of the power stage transistor 13. Therefore, as a whole, the impedance conversion ratio _{will ^{(m 2 / m 1) 2}} /4 times.

In the examples of FIGS. 29A to 31F, more strictly speaking, to the interstage signal wiring 35 (FIGS. 20, 25, 27) connected to the signal input ports of the first block 12A and the second block 12B. The number of turns of the secondary coil 142 changes depending on the connection position of the secondary coil 142. The connection position of the secondary coil 142 to the interstage signal wiring 35 may be determined according to the preferred number of turns.

[Connection form of the primary coil of the first transformer]
Next, with reference to the drawings from FIGS. 32A to 33D, the connection of the primary coil 131 of the first transformer 130 applied to the power amplification module according to the eighth embodiment, the ninth embodiment, and these modifications. The form will be described.

32A and 32B are schematic views showing a connection form of the secondary coil 142 of the first transformer 130 when two rows of transistor rows 12 are arranged. In FIGS. 32A and 32B, only one of the plurality of primary coils 131 is displayed. Transistor rows 12 are arranged along two sides of the rectangular convex polygon 30 facing each other. Each of the transistor rows 12 is divided into a first block 12A and a second block 12B as in the drawings of FIGS. 29A to 29D.

The drawings from FIGS. 33A to 33D are schematic views showing a connection form of the secondary coil 142 of the first transformer 130 when four transistor rows 12 are arranged. In the drawings from FIGS. 33A to 33D, only one of the plurality of primary coils 131 is displayed. Transistor rows 12 are arranged along the four sides of the square convex polygon 30. Each of the transistor rows 12 is divided into a first block 12A and a second block 12B as in the drawings of FIGS. 30A to 31F.

As shown in the drawings from FIGS. 32A to 33D, the first land 101 corresponding to the second block 12B of each of the plurality of transistor rows 12 and the transistor row 12 are arranged clockwise in the circumferential direction of the convex polygon 30. The primary coil 131 connects to the first land 101 corresponding to the first block 12A of the transistor row 12 at a position moved by n rows in terms of the number of transistor rows 12. Here, the parameter n is a natural number. The connection modes shown in FIGS. 32A and 32B correspond to the cases of n = 1 and n = 2, respectively. The connection modes shown in FIGS. 33A, 33B, 33C, and 33D correspond to the cases of n = 1, n = 2, n = 3, and n = 4, respectively.

By changing the parameter n, the turns ratio of the first transformer 130 can be changed. As a result, the impedance conversion ratio of the first transformer 130 can be changed.

[10th Example]
Next, the power amplification module according to the tenth embodiment will be described with reference to FIGS. 34 and 35. Hereinafter, the description of the configuration common to the power amplification module (FIGS. 19A, 20 and 21) according to the eighth embodiment will be omitted.

FIG. 34 is a diagram showing a positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the tenth embodiment. In FIG. 19A corresponding to the eighth embodiment, the conductor film on the circuit board 100 (FIG. 2) connected to the emitter (grounded port) of the power stage transistor 13 is not shown, but in FIG. 34, the emitter is used. The conductor film 108 to be connected is displayed. In FIG. 34, among the conductor films on the circuit board 100 (FIG. 2), the conductor film connected to the collector (signal output port) of the power stage transistor 13 and the secondary coil 132 of the first transformer 130 are relatively light. The hatching is attached, and the conductor film connected to the emitter is attached with a relatively dark hatching.

The emitter of the power stage transistor 13 is connected to the second land 102 on the circuit board 100 (FIG. 2) via the second bump 22. The second land 102 is arranged for each transistor row 12. A conductor film 108 including two second lands 102 partially surrounds the second transformer 140 in a plan view.

FIG. 35 is a cross-sectional view of the power amplification module according to the tenth embodiment. The collector pad 27, the emitter pad 28, and the second transformer 140 are arranged on the surface of the substrate 11 of the semiconductor chip 10 facing the circuit board 100. The second transformer 140 is composed of a primary coil 141 and a secondary coil 142.

The first land 101, the second land 102, and the first transformer 130 are arranged on the surface of the circuit board 100 on which the semiconductor chip 10 is mounted. The second land 102 forms a part of the annular conductor film 108 (FIG. 34). The collector pad 27 is connected to the first land 101 via the first bump 21, and the emitter pad 28 is connected to the second land 102 via the second bump 22. The first transformer 130 is composed of a primary coil 131 and a secondary coil 132. The second land 102 is connected to a ground pattern 105 provided on the circuit board 100.

Next, the excellent effect of the tenth embodiment will be described. A high-frequency magnetic field is generated by the high-frequency current flowing through the first transformer 130. When this high-frequency magnetic field interlinks with the primary coil 141 and the secondary coil 142 of the second transformer 140, a high-frequency current is induced in the primary coil 141 and the secondary coil 142 of the second transformer 140. When this high-frequency current is fed back to the power stage amplifier circuit 45, the operation of the power stage amplifier circuit 45 becomes unstable.

In the tenth embodiment, when a high-frequency current flows through the first transformer 130, a high-frequency current is induced in the annular conductor film 108. The magnetic field generated by the high-frequency current induced in the conductor film 108 cancels the magnetic field generated by the high-frequency current flowing through the first transformer 130. As a result, the influence on the second transformer 140 can be reduced. As a result, an excellent effect that the phenomenon that the operation of the power stage amplifier circuit 45 becomes unstable is less likely to occur can be obtained.

Next, the power amplification module according to the modified example of the tenth embodiment will be described with reference to FIG. 36.

FIG. 36 is a diagram showing the positional relationship in a plan view of a plurality of components of the power stage amplifier circuit and the output impedance conversion circuit of the power amplification module according to the modified example of the tenth embodiment. In the tenth embodiment, the conductor film 108 has an annular shape surrounding the second transformer 140 in a plan view. On the other hand, in the modified example shown in FIG. 36, the conductor film 108 includes the second transformer 140 in a plan view.

In this modification, as compared with the case of the tenth embodiment, it is possible to enhance the effect that the influence of the high frequency magnetic field caused by the high frequency current flowing through the first transformer 130 is less likely to reach the second transformer 140.

Next, another modification of the tenth embodiment will be described. In the tenth embodiment, the conductor film 108 is arranged on the uppermost layer (first layer counting from the mounting surface) of the circuit board 100, but may be arranged on the second layer counting from the mounting surface.

[11th Example]
Next, the power amplification module according to the eleventh embodiment will be described with reference to FIGS. 37 and 38. Hereinafter, the description of the configuration common to the power amplification module (FIGS. 19A, 20 and 21) according to the eighth embodiment will be omitted.

FIG. 37 is a diagram showing a circuit for generating differential signals input to a plurality of power stage transistors 13 of the power amplification module according to the eleventh embodiment, and a positional relationship of components of the pre-stage amplifier circuit 40 in a plan view. .. In the eighth embodiment, the collector wiring 43 connected to the signal output port of the first stage amplifier circuit 40 (FIG. 20) is directly connected to the primary coil 141 of the second transformer 140. On the other hand, in the modified example shown in FIG. 37, the second auxiliary impedance conversion circuit 59 is inserted between the collector wiring 43 and the primary coil 141 of the second transformer 140.

The second auxiliary impedance conversion circuit 59 includes an inductor 57 and a capacitor 58 having a MIM structure. One end of the inductor 57 is connected to the collector wiring 43, and the other end is connected to the second power supply wiring 107 of the circuit board 100 (FIG. 2). The capacitor 58 is inserted in series between the collector wiring 43 and the primary coil 141.

FIG. 38 is an equivalent circuit diagram of the power amplification module according to the eleventh embodiment. A second auxiliary impedance conversion circuit 59 is inserted between the signal output port of the first stage amplifier circuit 40 and the primary coil 141 of the second transformer 140. Other configurations are the same as the equivalent circuit diagram (FIG. 21) of the power amplification module according to the eighth embodiment.

Next, the excellent effect of the eleventh embodiment will be described.
In the power amplification module (FIG. 21) according to the eighth embodiment, since the conversion ratio of the output impedance of the pre-stage amplifier circuit 40 is determined by the turns ratio of the second transformer 140, it is difficult to continuously change the output impedance. In the eleventh embodiment, the impedance conversion ratio can be finely adjusted by providing the second auxiliary impedance conversion circuit 59. Thereby, the impedance between the front stage amplifier circuit 40 and the power stage amplifier circuit 45 can be matched more accurately. As a result, an excellent effect that the gain of the power amplification module becomes larger can be obtained.

It goes without saying that each of the above embodiments is exemplary and the configurations shown in different examples can be partially replaced or combined. Similar effects and effects due to the same configuration of a plurality of examples will not be mentioned sequentially for each example. Furthermore, the present invention is not limited to the above-mentioned examples. For example, it will be obvious to those skilled in the art that various changes, improvements, combinations, etc. are possible.

10 Semiconductor chip 11 Substrate 12 Transistor row 12A 1st block 12B 2nd block 13 Power stage transistor 14 Collector wiring 15 Base wiring (signal input end)
16 Emitter layer 16M Emitter mesa 17 Base layer 18 Collector layer 19 Sub collector layer 20 Collector mesa 21 First bump (collector bump)
22 Second bump (emitter bump)
23 Power supply bump 24, 25 Capacitor 25A Lower electrode 25B Upper electrode 26A, 26B Bump 27 Collector pad 28 Emitter pad 30 Convex polygon 31 Collector electrode 32 Base electrode 33 Emitter electrode 34 Emitter wiring 35 Interstage signal wiring 36 Capacitor 37 Base ballast Resistance element 38 Bias wiring 40 Pre-stage amplifier circuit 42 Pre-stage transistor 43 Collector wiring 44 Base wiring 45 Power stage amplifier circuit 46 Resistance element 47 Signal input wiring 48 Capacitor 49 Signal input bump 50 Second impedance conversion circuit 51 Capacitor 52 Condenser 53 Power supply bump 57 Capacitor 58 Capacitor 59 2nd Auxiliary Impacitor Conversion Circuit 68, 69 Capacitor 70 Power Stage Transistor Group 100 Circuit Board 101 1st Land 102 2nd Land 103, 104 Output Wiring 104J Confluence 105 Ground Pattern 106 1st Power Supply Wiring 107 2 Power supply wiring 108 1st conductor film 110 Signal output terminal 112 Output wiring 112J Confluence 120 1st impedance conversion circuit 121 Chip capacitor 122, 123 Inverter 124 Chip capacitor 125 Grounding land 126, 127 Inlayer 128 Midpoint 129 Output side midpoint 130 1st Transformer 131 1st Coil 131A 1st Part of Primary Coil 131B 2nd Part of Primary Coil 132 2nd Coil 133 Line connecting center points of width of 1st part 135 1st Auxiliary Amplifier Conversion Circuit 140 2nd Transformer 141 Primary capacitor 142 Secondary coil

A base electrode 32 is arranged on the emitter layer 16 so as to surround the emitter mesa 16M from three sides in a plan view. The base electrode 32 is connected to the base layer 17 via an alloy layer that penetrates the emitter layer 16 in the thickness direction. The emitter electrode 33 is arranged on the emitter mesa 16M . Emitter electrode 33 is connected to the emitter layer 16 via the emitter mesa 16M. In FIG. 1, the collector electrode 31, the base electrode 32, the emitter electrode 33, and the like are not shown.

In order to distinguish each of the eight transistor trains 12, serial numbers 1 to 8 are sequentially assigned in the first rotation direction (clockwise in FIG. 15) of the convex polygon 30 in the circumferential direction. In FIG. 15, the serial number assigned to each transistor row 12 is represented by a number with a pound sign. From the connection point with the output wiring 103 corresponding to the odd-numbered transistor row 12 in the output wiring 104 to the connection point with the output wiring 103 corresponding to the transistor row 12 adjacent to each other in the first rotation direction in the circumferential direction. The midpoint 128 of the part is grounded.

The connection points between the secondary coil 142 and the interstage signal wiring 35 are arranged at positions biased toward the center side in the length direction of the transistor train 12 with respect to the length direction of the interstage signal wiring 35. That is, the connection points between the secondary coil 142 and the interstage signal wiring 35 are biased in the direction in which the number of turns of each of the two secondary coils 142 increases. The secondary coil 142 is connected to the base (signal input port) of the power stage transistor 13 via the interstage signal wiring 35, the capacitor 36, and the base wiring 15. In FIG. 20, the description of the circuit that supplies power to the preceding transistor 42 is omitted .

In the comparative example shown in FIG. 23C, the first portion 131A is shorter than in the case of the comparative example shown in FIG. 23B. In this case, the parasitic resistance and the parasitic inductance of the first portion 131A itself are reduced, but the ends of the first land 101 and the second portion 131B come closer to each other. As a result, the magnetic coupling between the two becomes large. Of the second portion 131B, the portion magnetically coupled to the first land 101 does not function as the primary coil of the first transformer 130, and the performance of the first transformer 130 deteriorates.

FIG. 29B corresponds to the case of m = 2. That is, the signal input port of the second block 12B of the same transistor array 12 and the signal input port of the first block 12A are connected by about one turn to the secondary coil 142 in the circumferential direction of the convex polygon 30. This connection configuration corresponds to the modified example shown in FIG.

32A and 32B are schematic views showing a connection form of the primary coil 131 of the first transformer 130 when two rows of transistor rows 12 are arranged. In FIGS. 32A and 32B, only one of the plurality of primary coils 131 is displayed. Transistor rows 12 are arranged along two sides of the rectangular convex polygon 30 facing each other. Each of the transistor rows 12 is divided into a first block 12A and a second block 12B as in the drawings of FIGS. 29A to 29D.

The drawings from FIGS. 33A to 33D are schematic views showing a connection form of the primary coil 131 of the first transformer 130 when four transistor rows 12 are arranged. In the drawings from FIGS. 33A to 33D, only one of the plurality of primary coils 131 is displayed. Transistor rows 12 are arranged along the four sides of the square convex polygon 30. Each of the transistor rows 12 is divided into a first block 12A and a second block 12B as in the drawings of FIGS. 30A to 31F.

Claims (21)

It has a circuit board and a semiconductor chip mounted on the circuit board.
The semiconductor chip is
With the board
It is provided with a plurality of transistor trains formed on the substrate.
Each of the plurality of transistor trains includes a plurality of power stage transistors arranged in a straight line.
Each of the plurality of power stage transistors is a bipolar transistor or field effect transistor having an emitter or source as a ground port, a collector or drain as a signal output port, and a base or gate as a signal input port.
The semiconductor chip further
A plurality of first bumps arranged corresponding to each of the plurality of transistor trains and connected to signal output ports of the plurality of power stage transistors included in the corresponding transistor trains.
It is provided with a plurality of second bumps arranged corresponding to each of the plurality of transistor trains and connected to the ground port of the plurality of power stage transistors included in the corresponding transistor trains.
The plurality of transistor trains are arranged along a plurality of sides of a convex polygon.
The circuit board
A plurality of first lands connected to the plurality of first bumps, respectively,
A plurality of second lands connected to the plurality of second bumps, respectively,
The ground pattern connected to the plurality of second lands and
Signal output terminal and
A first impedance conversion circuit for connecting the plurality of first lands and the signal output terminal is provided.
The plurality of power stage transistors are grouped into a plurality of groups, and the first impedance conversion circuit is a power amplification module including a plurality of individual reactance elements arranged for each of the plurality of groups. The first aspect of claim 1, wherein the shape of each of the plurality of first bumps in a plan view is long in a direction parallel to the arrangement direction of the plurality of power stage transistors belonging to the transistor train corresponding to each of the plurality of first bumps. Power amplification module. A plurality of the plurality of first bumps are arranged corresponding to each of the plurality of transistor rows, and are arranged side by side in a direction parallel to the arrangement direction of the plurality of power stage transistors included in the corresponding transistor rows. The power amplification module according to claim 1. The semiconductor chip further
Any one of claims 1 to 3, further comprising a capacitor connected between each of the plurality of first bumps and the signal output ports of the plurality of power stage transistors included in the corresponding transistor trains. The power amplification module described in. Each of the plurality of first bumps is arranged at a position farther than the corresponding second bump when viewed from the geometric center of the convex polygon.
The semiconductor chip further
A front-stage amplifier circuit that is arranged inside the convex polygon in a plan view and outputs a high-frequency signal input to the plurality of power stage transistors.
The power amplification module according to any one of claims 1 to 4, further comprising a second impedance conversion circuit connected between the pre-stage amplifier circuit and the plurality of power stage transistors. The second impedance conversion circuit
Reactance elements arranged corresponding to each of the plurality of transistor rows, and
The power amplification module according to claim 5, further comprising another reactance element shared by the plurality of transistor trains. The power amplification module according to any one of claims 1 to 6, wherein the plurality of transistor trains and the plurality of groups have a one-to-one correspondence. Each of the plurality of transistor trains has the first block at the center in the length direction of each of the plurality of transistor trains so that the first block and the second block are alternately arranged in the circumferential direction of the convex polygon. It is divided into one block and the second block.
The plurality of first bumps and the plurality of first lands are arranged corresponding to the first block and the second block of the plurality of transistor trains, respectively.
The circuit board also includes power supply wiring.
The first impedance conversion circuit includes a first transformer.
Each of the plurality of individual reactance elements of the first impedance conversion circuit
With the parameter n as a natural number, the first land corresponding to the second block of each of the plurality of transistor rows and the number of transistor rows in the first rotation direction in the circumferential direction of the convex polygon are moved by n rows. The primary coil of the first transformer is formed by connecting the first land corresponding to the first block of the transistor row at the position.
The first transformer further includes a secondary coil connected to the signal output terminal.
The length of the plurality of primary coils is substantially the same, and each of the plurality of primary coils is connected to the power supply wiring at substantially the center in the length direction, according to any one of claims 1 to 4. The power amplification module described in. The convex polygon is a square or a rectangle
The plurality of transistor trains are composed of two transistor trains arranged along two opposite sides of the convex polygon.
The parameter n is 1,
The power amplification module according to claim 8, wherein a plurality of primary coils of the first transformer surround the convex polygon. The convex polygon is a square
The plurality of transistor trains are composed of four transistor trains arranged along the four sides of the convex polygon.
The parameter n is 1,
The power amplification module according to claim 8, wherein a plurality of primary coils of the first transformer surround the convex polygon. The circuit board according to any one of claims 8 to 10, further comprising a first auxiliary impedance conversion circuit inserted between the secondary coil of the first transformer and the signal output terminal. Power amplification module. Each of the plurality of primary coils extends from the first land toward the outside of the convex polygon and from the tip of the first portion in the circumferential direction of the convex polygon in a plan view. The power amplification module according to any one of claims 8 to 11, further comprising a second portion, wherein the width of the first portion is narrowed from the first land toward the tip of the first portion. When the width direction of the first portion is defined as a direction parallel to the arrangement direction of the plurality of power stage transistors to which the first portion is connected, a line connecting the center points of the width of the first portion is defined as The power amplification module according to claim 12, wherein the second portion is inclined in a direction in which the second portion becomes longer with reference to a direction orthogonal to the arrangement direction of the plurality of power stage transistors. The power amplification module according to any one of claims 8 to 13, wherein the at least one front-stage transistor is shared by the plurality of transistor rows. The convex polygon is a square or a rectangle
The plurality of transistor trains are composed of two transistor trains arranged along two opposite sides of the convex polygon.
Each of the plurality of first bumps is arranged at a position farther than the corresponding second bump when viewed from the geometric center of the convex polygon.
The semiconductor chip further
A front-stage amplifier circuit that is arranged inside the convex polygon in a plan view and outputs a high-frequency signal input to the plurality of power stage transistors.
It is provided with a second impedance conversion circuit connected between the pre-stage amplifier circuit and a plurality of power stage transistors.
The second impedance conversion circuit inputs in-phase high-frequency signals to the plurality of power stage transistors in the first block of the two transistor trains, and the plurality of power stages in the second block of the two transistor trains. The power amplification module according to any one of claims 8 to 14, wherein a high-frequency signal having a phase opposite to that of the high-frequency signal input to the plurality of power stage transistors in the first block is input to the transistor. The second impedance conversion circuit includes a second transformer.
The second transformer is
The primary coil connected to the pre-stage amplifier circuit and
The signal input ports of the plurality of power stage transistors in the first block of the two transistor trains and the signal input ports of the plurality of power stage transistors in the second block of the same transistor train or the other transistor train, respectively. It is equipped with two secondary coils to connect the
The power amplification module according to claim 15, wherein each of the two secondary coils is grounded substantially at the center in the length direction. The convex polygon is a square
The plurality of transistor trains are composed of four transistor trains arranged along the four sides of the convex polygon.
Each of the plurality of first bumps is arranged at a position farther than the corresponding second bump when viewed from the geometric center of the convex polygon.
The semiconductor chip further
A front-stage amplifier circuit that is arranged inside the convex polygon in a plan view and includes a signal output end that outputs a high-frequency signal,
A second impedance conversion inserted in the signal path between the pre-stage amplifier circuit and the signal input ports of a plurality of power stage transistors included in the first block and the second block of each of the four transistor trains. Equipped with a circuit,
The second impedance conversion circuit inputs in-phase high-frequency signals to the plurality of power stage transistors in the first block of the four transistor trains, and the plurality of power stages in the second block of the four transistor trains. The power amplification module according to any one of claims 8 to 14, wherein a high-frequency signal having a phase opposite to that of the high-frequency signal input to the plurality of power stage transistors in the first block is input to the transistor. The second impedance conversion circuit includes a second transformer.
The second transformer is
The primary coil connected to the pre-stage amplifier circuit and
When the parameter m is a natural number, the signal input ports of the plurality of power stage transistors in the second block of each of the four transistor trains and the transistor trains in the first rotation direction in the circumferential direction of the convex polygon. It is provided with a plurality of secondary coils for connecting the signal input ports of the plurality of power stage transistors in the first block of the transistor row at positions moved by m rows in number.
The power amplification module according to claim 17, wherein each of the plurality of secondary coils is grounded substantially at the center in the length direction. The circuit board further comprises a conductor film connected to the plurality of second lands.
The power amplification module according to claim 16 or 18, wherein the plurality of second lands and the conductor film surround the second transformer in a plan view. The circuit board further comprises a conductor film connected to the second land.
The power amplification module according to claim 16 or 18, wherein the conductor film includes the second transformer in a plan view. The semiconductor chip further comprises any one of claims 16, 18 to 20, further comprising a second auxiliary impedance conversion circuit inserted in the signal path between the pre-stage amplifier circuit and the second transformer. Power amplification module.

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