JP2021097489A - Voltage monitoring circuit and power unit - Google Patents

Abstract

To improve accuracy of voltage monitoring in a voltage monitoring circuit.SOLUTION: A voltage monitoring circuit (10) includes: a contrast voltage output unit (12) configured to output contrast voltages (VA, VB) according to input digital values (DA, DB) using D/A converters (12A, 12B); a voltage comparison unit (13) configured to compare a monitoring target voltage (VOUT) with the contrast voltages; and a control unit (11). The control unit, in setting-operation, executes a sweep process to vary the contrast voltages through a variation of the input digital values, and obtains the input digital values when a high-low relationship between the monitoring target voltage and the contrast voltages is reversed during the sweep process as criterion values (DAREF, DBREF), and then, in monitoring operation, after setting abnormality determination values (DA_TH, DB_TH) based on the criterion values as the input digital values, determines whether or not there is an abnormality in the monitoring target voltage on the basis of a comparison result of the voltage comparison unit.SELECTED DRAWING: Figure 1

Description

The present invention relates to a voltage monitoring circuit and a power supply device.

Power supply devices are required to continuously output a voltage satisfying a desired accuracy, and there are many power supply devices to which an output voltage monitoring function is added. In particular, for example, in the fields of automatic driving and advanced driver assistance systems, a function of monitoring the output voltage of a power supply device is indispensable due to the need for functional safety. As the sophistication of various functions of autonomous driving and advanced driver assistance systems progresses, the required accuracy of voltage monitoring is increasing.

FIG. 10 shows the configuration of a general power supply device 901 with a voltage monitoring function. The power supply device 901 includes a voltage monitoring circuit 910 and a power supply circuit 920. The power supply circuit 920 generates an output voltage Vout to be stabilized at a target voltage Vtg (for example, 5V) from the input voltage Vin. The voltage monitoring circuit 910 compares the output voltage Vout with the overvoltage determination voltage Vovd, which is the upper abnormality determination voltage, or the undervoltage determination voltage Vuvd, which is the lower abnormality determination voltage, so that the output voltage Vout becomes too high. Or judge and monitor the presence or absence of abnormalities that become too low.

Japanese Unexamined Patent Publication No. 2010-20454

FIG. 11 shows a design value of the output voltage Vout (that is, a value of the target voltage Vtg), a design value Vovd_tg of the overvoltage determination voltage Vovd, and a design value Vuvd_tg of the undervoltage determination voltage Vuvd in the power supply device 901 of FIG. Show the relationship. The power supply circuit 920 is designed and configured with the aim of matching the output voltage Vout with the target voltage Vtg, but the output voltage Vout varies by ΔVa above and below the target voltage Vtg even if there is no abnormality (this). The variation is called the absolute value variation of the output voltage).

Therefore, in the voltage monitoring circuit 910, it is necessary to set the determination voltages Vovd and Vuvd in consideration of the variation in the output voltage Vout. On the other hand, unavoidable variations (this variation is referred to as absolute value variation of the determination voltage) also occur in each of the determination voltages Vovd and Vuvd used in the voltage monitoring circuit 910. Therefore, in the voltage monitoring circuit 910, it is necessary to determine each design value of the determination voltage Vovd and Vuvd after considering all the variation in the absolute value of the output voltage and the variation in the absolute value of the determination voltage. Due to the variation in the absolute value of the judgment voltage, the actual overvoltage judgment voltage Vovd varies by ΔVb to the upper and lower sides based on the design value Vovd_tg, and the actual undervoltage judgment voltage Vuvd varies to the upper and lower sides based on the design value Vuvd_tg. Only vary.

For example, if the target voltage Vtg is 5.00V and the voltage ΔVa corresponding to the absolute value variation of the output voltage Vout is 0.1V, the output voltage Vout is abnormal when “Vout> 5.10V”. Voltage monitoring can be performed so that it is determined that there is. In this case, for example, if the voltage ΔVb corresponding to the variation in the absolute value of the overvoltage determination voltage Vovd is 0.08V, it is necessary to set the design value Vovd_tg of the overvoltage determination voltage Vovd to be higher than 5.18V. The same applies to the design value Vuvd_tg.

In the actual voltage monitoring circuit 910, the direction and magnitude of the variation of each determination voltage Vovd and Vuvd are undefined. Therefore, in the power supply device 901 of FIG. 10, for example, even if the output voltage Vout, which initially matches the target voltage Vtg, rises for some reason and becomes “Vout> Vtg + ΔVa”, the occurrence of an abnormality cannot be recognized. It can be determined that an abnormality has occurred only when "Vout> Vtg + ΔVovd = Vtg + ΔVa + 2 · ΔVb" (provided that "Vovd_tg = Vtg + ΔVa + ΔVb"). Similarly, when the output voltage Vout is lower than the target voltage Vtg, it can be determined that an abnormality has occurred only when "Vout <Vtg-ΔVuvd = Vtg- (ΔVa + 2 · ΔVc)". "Vuvd_tg = Vtg-ΔVa-ΔVc"). It can be said that the voltages ΔVovd and ΔVuvd are related to the voltage monitoring accuracy, and the voltage monitoring accuracy decreases as the voltages ΔVovd and ΔVuvd increase.

As described above, in the power supply device 901 of FIG. 10, it is difficult to improve the voltage monitoring accuracy due to the influence of the absolute value variations of the output voltage and the determination voltage.

An object of the present invention is to provide a voltage monitoring circuit and a power supply device that contribute to improvement of voltage monitoring accuracy.

The voltage monitoring circuit according to the present invention is a voltage monitoring circuit that monitors a monitored voltage, and compares a contrast voltage output unit that outputs a contrast voltage using a D / A converter with the monitored voltage and the contrast voltage. A voltage comparison unit for performing a setting operation or a control unit for executing a monitoring operation is provided, and the contrast voltage output unit outputs the contrast voltage according to an input digital value from the control unit from the D / A converter. Then, in the setting operation, the control unit executes a sweep process that fluctuates the contrast voltage through the fluctuation of the input digital value, and in the process of the sweep process, the height relationship between the monitored voltage and the contrast voltage. The input digital value at the time of inversion is acquired as a reference value, and then, in the monitoring operation, an abnormality determination value based on the reference value is set as the input digital value, and then based on the comparison result of the voltage comparison unit. This is a configuration (first configuration) for determining the presence or absence of an abnormality in the monitored voltage.

In the voltage monitoring circuit according to the first configuration, the control unit determines the abnormality based on the reference value so that the relative voltage in the monitoring operation is higher or lower than the monitored voltage in the setting operation. It may be a configuration (second configuration) set to a value.

In the voltage monitoring circuit according to the second configuration, the control unit sets the abnormality determination value based on the reference value so that the relative voltage in the monitoring operation is higher than the monitored voltage in the setting operation. When a signal indicating that the monitored voltage is higher than the contrast voltage corresponding to the abnormality determination value in the monitoring operation is output from the voltage comparison unit, it is determined that the monitored voltage has an abnormality. It may be a determination configuration (third configuration).

In the voltage monitoring circuit according to the second configuration, the control unit sets the abnormality determination value based on the reference value so that the relative voltage in the monitoring operation is lower than the monitored voltage in the setting operation. When a signal indicating that the monitored voltage is lower than the contrast voltage corresponding to the abnormality determination value in the monitoring operation is output from the voltage comparison unit, it is determined that the monitored voltage has an abnormality. It may be a determination configuration (fourth configuration).

The voltage monitoring circuit according to any one of the first to fourth configurations further includes a memory that holds a predetermined fixed value, and the control unit is based on the reference value and the fixed value in the setting operation. , The configuration (fifth configuration) for determining the presence or absence of an abnormality in the monitored voltage may be used.

In the voltage monitoring circuit according to the first configuration, the contrast voltage output unit is a first D / A converter that outputs the first contrast voltage by D / A converting the first input digital value from the control unit. A second D / A converter that outputs a second contrast voltage by D / A converting a second input digital value from the control unit, and the voltage comparison unit has the monitored voltage and the first voltage. It has a first comparison unit for comparing one contrast voltage and a second comparison unit for comparing the monitored voltage with the second comparison voltage, and the control unit has the first input digital in the setting operation. The first sweep process that fluctuates the first contrast voltage through the fluctuation of the value is executed, and the height relationship between the monitored voltage and the first contrast voltage is reversed in the process of the first sweep process. The 1-input digital value is acquired as the first reference value, and the second sweep process that fluctuates the second contrast voltage through the fluctuation of the second input digital value is executed, and the monitoring is performed in the process of the second sweep process. The second input digital value when the height relationship between the target voltage and the second contrast voltage is reversed is acquired as the second reference value, and then, in the monitoring operation, the first abnormality determination based on the first reference value is performed. After setting the value to the first input digital value and setting the second abnormality determination value based on the second reference value to the second input digital value, each of the first comparison unit and the second comparison unit. A configuration (sixth configuration) may be used in which the presence or absence of an abnormality in the monitored voltage is determined based on the comparison result.

In the voltage monitoring circuit according to the sixth configuration, the control unit has the first reference value based on the first reference value so that the first contrast voltage in the monitoring operation is higher than the monitored voltage in the setting operation. 1 Abnormality determination value is set, and the second abnormality determination value is set based on the second reference value so that the second contrast voltage in the monitoring operation is lower than the monitoring target voltage in the setting operation. (7th configuration) may be used.

In the voltage monitoring circuit according to the seventh configuration, the control unit has a signal indicating that the monitored voltage is higher than the first contrast voltage corresponding to the first abnormality determination value in the monitoring operation. When output from 1 comparison unit, or in the monitoring operation, a signal indicating that the monitoring target voltage is lower than the second comparison voltage corresponding to the second abnormality determination value is output from the second comparison unit. When this is done, the configuration may be such that it is determined that the monitored voltage has an abnormality (eighth configuration).

In the voltage monitoring circuit according to any one of the sixth to eighth configurations, a memory for holding a predetermined first fixed value and a predetermined second fixed value is further provided, and the control unit is described in the setting operation. With a configuration (9th configuration) for determining the presence or absence of an abnormality in the monitored voltage based on the first reference value and the first fixed value, or based on the second reference value and the second fixed value. There may be.

In the voltage monitoring circuit according to any one of the first to ninth configurations, the control unit has a configuration (tenth configuration) capable of executing the setting operation each time the voltage monitoring circuit is activated. Is also good.

In the voltage monitoring circuit according to any one of the first to tenth configurations, the control unit can execute the setting operation based on a signal from a higher-level control circuit connected to the voltage monitoring circuit (a configuration in which the setting operation can be executed. It may be the eleventh configuration).

The power supply device according to the present invention includes a voltage monitoring circuit according to any one of the first to eleventh configurations and a power supply circuit that generates an output voltage based on an input voltage, and the output voltage is the voltage monitoring circuit. This is the configuration (12th configuration) that is the monitored voltage to be monitored in.

According to the present invention, it is possible to provide a voltage monitoring circuit and a power supply device that contribute to improvement of voltage monitoring accuracy.

It is an overall block diagram of the power supply device which concerns on embodiment of this invention. It is a figure which shows the input / output relation of the D / A converter which concerns on embodiment of this invention. It is a flowchart of the actual operation operation of the voltage monitoring circuit which concerns on embodiment of this invention. FIG. 5 is an explanatory diagram of a first sweep process and a second sweep process executed by a setting operation according to an embodiment of the present invention. It is a figure which shows the storage content in the memory of the voltage monitoring circuit which concerns on embodiment of this invention. It is a figure which shows the relationship between the output voltage at the time of a setting operation, and the abnormality determination voltage of the upper side and the lower side, according to the embodiment of this invention. It is a figure which shows the storage content in the memory of the voltage monitoring circuit which concerns on 1st Example which belongs to the Embodiment of this invention. It is a figure which shows the storage content in the memory of the voltage monitoring circuit which concerns on 2nd Example which belongs to the Embodiment of this invention. It is a figure which shows the state that the power supply device is mounted on the vehicle with respect to the 4th Embodiment belonging to the embodiment of this invention. It is an overall block diagram of the power supply device which concerns on a reference technique. It is a figure which shows the relationship of a plurality of voltages in the power supply device of FIG.

Hereinafter, examples of embodiments of the present invention will be specifically described with reference to the drawings. In each of the referenced figures, the same parts are designated by the same reference numerals, and duplicate explanations regarding the same parts will be omitted in principle. In this specification, for the sake of simplification of description, by describing a symbol or a code that refers to an information, a signal, a physical quantity, an element or a part, etc. Etc. may be omitted or abbreviated. For example, the first reference value referred to by _{"D AREF} " described later (see FIG. 5) may be expressed as _{the first reference value D AREF} , or simply abbreviated as the _{reference value D AREF} or simply the value D _AREF. It is possible, but they all refer to the same thing.

First, some terms used in the description of the embodiments of the present invention will be described.
The ground refers to a conductive portion having a reference potential of 0 V (zero volt) or the potential of 0 V itself. The potential of 0 V may be referred to as the ground potential. In the embodiment of the present invention, the voltage shown without any particular reference represents the potential seen from the ground.

Level refers to the level of potential, where a high level has a higher potential than a low level for any signal or voltage. For any signal or voltage, a signal or voltage at a high level means that the signal or voltage level is at a high level, and a signal or voltage at a low level means that the signal or voltage level is at a low level. Means that it is in. A level for a signal is sometimes referred to as a signal level, and a level for a voltage is sometimes referred to as a voltage level.

For any signal or voltage, switching from low level to high level is called up edge, and timing of switching from low level to high level is called up edge timing. Similarly, for any signal or voltage, switching from high level to low level is referred to as down edge, and timing of switching from high level to low level is referred to as down edge timing.

For any signal having a high level or low level signal level, a section in which the level of the signal is high level is referred to as a high level section, and a section in which the level of the signal is low level is referred to as a low level section. The same is true for any voltage that has a high or low level voltage level.

FIG. 1 is an overall configuration diagram of a power supply device 1 according to an embodiment of the present invention. The power supply device 1 is a power supply device having a voltage monitoring function, and includes a voltage monitoring circuit 10 and a power supply circuit 20. The host control circuit 30 is connected to the voltage monitoring circuit 10. It can be considered that the power supply system is composed of the voltage monitoring circuit 10, the power supply circuit 20, and the host control circuit 30.

The power supply circuit 20 is an arbitrary power supply circuit that generates and outputs an _{output voltage V OUT} that should be stabilized at a predetermined target voltage V _{TG based on the input voltage V IN.} The target voltage V _TG and the output voltage V _OUT are DC voltages. The output voltage V _OUT may be supplied to the load device LD as the power supply voltage of the load device LD. The load device LD is an arbitrary load driven based on the _{output voltage V OUT.} For example, the power supply circuit 20 is a DC / DC converter that generates a DC positive output voltage V _{OUT from a DC positive input voltage V IN.} The output voltage V _OUT and the target voltage V _TG may be lower or higher than the input voltage V _IN. Further, the input voltage V _IN or the output voltage V _OUT may be a negative DC voltage. The power supply circuit 20 may be a switching type DC / DC converter or a series type DC / DC converter. The power supply circuit 20 may be an AC / DC converter (that is, the input voltage _VIN may be an AC voltage).

In the following, it is assumed that the target voltage V _TG is a positive DC voltage, and therefore, the output voltage V _OUT is also a positive DC voltage _{during normal operation of the power supply circuit 20 (ideally, “V OUT} = V _TG ”). ). Further, the power supply circuit 20 has a function of outputting a _{signal PGOOD} based on the _{output voltage V OUT.} When the power supply circuit 20 is activated and the output voltage V _OUT rises, the signal P _GOOD becomes a high level when the output voltage V _OUT reaches “k × V _{TG”. The signal PGOOD} is at a low level when the output voltage V _OUT is less than “k × V _TG”. The coefficient k has a predetermined value (for example, 0.8) that is greater than 0 and less than 1.

The voltage monitoring circuit 10 has _{a function of monitoring the output voltage V OUT} of the power supply circuit 20 as a monitoring target voltage and outputting the monitoring result to the outside. The voltage monitoring circuit 10 includes a control unit 11, a contrast voltage output unit 12, a voltage comparison unit 13, a memory 14, a reference voltage generation unit 15, and a plurality of external terminals including terminals TM1 to TM6. The contrast voltage output unit 12 includes two D / A converters (digital / analog converters), DAC12A and DAC12B. The voltage comparison unit 13 includes comparators 13A and 13B.

The power supply voltage VDD of the voltage monitoring circuit 10 is supplied to the terminal TM1, and each circuit in the voltage monitoring circuit 10 is driven based on the power supply voltage VDD. The power supply voltage VDD may be an output voltage V _{OUT or} another DC voltage generated based on the input voltage V _IN. The terminal TM2 is connected to the ground. _{The output voltage V OUT} of the power supply circuit 20 is input to the terminal TM3.

The signal P _GOOD is input to the terminal TM4. The signal P _GOOD functions as an enable signal EN for the control unit 11. The control unit 11 does not operate in the low-level section of the enable signal EN, but operates in the high-level section of the enable signal EN. The control unit 11 starts the operation when the enable signal EN is switched from the low level to the high level. In the following, it is assumed that the enable signal EN is maintained at a high level unless otherwise specified.

The terminal TM5 is connected to the control unit 11. The control unit 11 can output the abnormality detection signal DET to an external circuit (not shown) of the voltage monitoring circuit 10 via the terminal TM5. The external circuit here is an external circuit connected to the terminal TM5, and may be an upper control circuit 30. The significance of the abnormality detection signal DET will be described later.

The terminal TM6 is composed of a plurality of communication terminals, and the control unit 11 can perform bidirectional communication with the host control circuit 30 via the terminal TM6. This communication method is arbitrary, and for example, communication by SPI (Serial Peripheral Interface) or communication by I2C (Inter-Integrated Circuit) can be used.

The control unit 11 individually inputs digital signals to each of the DACs 12A and 12B. Referring to digital signal input from the control unit 11 to DAC12A symbol at "IN _A", referring to the digital signal input from the control unit 11 to DAC12B symbol at "IN _B". Digital signal IN _A has a digital value D _A expressed by a predetermined number of bits, the digital signal IN _B has a digital value D _B represented by a predetermined number of bits.

DAC12A generates a comparison voltage _{V A} digital signal IN _A based on a predetermined reference voltage _{V REF} by D / A conversion (digital / analog conversion). D / A conversion of the digital signal IN _A has the same meaning as D / A conversion of the digital values _{D A.} The DAC 12B generates a _{contrast voltage V B} by D / A conversion (digital / analog conversion) of the digital signal IN _B based on a predetermined reference voltage V _REF. D / A conversion of the digital signal IN _B has the same meaning as D / A conversion of the digital value _{D B.}

As shown in FIG. 2 (a) and (b), comparing the voltage V _A with increasing digital value D _A is linear manner monotonously increased, compared voltage V _B increases linearly monotonically with increasing digital value D _B It shall be. The reference voltage V _REF is a positive DC voltage generated by the reference voltage generation unit 15 based on the power supply voltage VDD. Here, a factor proportional to the digital value D _A and a voltage obtained by and multiplying 1 the following coefficients in the reference voltage V _REF is generated as contrasted voltage V _A, a factor proportional to the digital value D _{B Moreover} , it is assumed that the voltage obtained by multiplying the reference voltage V REF by a coefficient of 1 or less _{is generated as the contrast voltage V B.}

Contrast voltage _{V A} output from DAC12A is input to the inverting input terminal of the comparator 13A. The non-inverting input terminal of the comparator 13A is connected to the terminal TM3 and receives an input of an _{output voltage V OUT as a monitoring target voltage.} Thus, the comparator 13A compares the output voltage _{V OUT} Contrast voltage _{V A,} and outputs a signal _{S A} indicating the comparison result. Signal _{S A} is input to the control unit 11. Signal S _A is a binary signal which takes either of the signal level of the high level or low level, represents the height relationship between the comparison voltage V _A and the output voltage V _OUT. Specifically, the signal _{S A} in (when ie _"V OUT> _{V A")} when the output voltage _{V OUT} is higher than the comparison voltage _{V A} becomes high level, than the output voltage _{V OUT} is compared voltage _{V A} signal _{S a} becomes a low level at low time (i.e. when the _{"V OUT <V a")} . When the output voltage _{V OUT} is exactly coincides with the comparison voltage _{V A,} the signal _{S A} becomes the high level or low level.

Signal S _A is abnormal to the output voltage V _OUT becomes too high is a signal indicating whether or not (hereinafter, overvoltage abnormality called), the monitoring operation to be described later, "1" signal S _A with a logical value of the overvoltage anomalies Indicates occurrence and existence. In this example, the positive logic adopted for the signals S _A, signal S _A of the high level has a logical value of "1", the signal S _A of a low level is a logical value of "0" It is assumed that there is. However, may also be negative logic is employed for the signal S _A, in this case, the type the comparison voltage V _A to the non-inverting input terminal of the comparator 13A, the output voltage V _OUT inversion of the comparator 13A You can input to the input terminal.

_{The contrast voltage V B} output from the DAC 12B is input to the non-inverting input terminal of the comparator 13B. The inverting input terminal of the comparator 13B is connected to the terminal TM3 and receives an input of an _{output voltage V OUT as a monitoring target voltage.} Therefore, the comparator 13B compares the output voltage _{V OUT} Contrast voltage _{V B,} and outputs a signal _{S B} indicating the comparison result. Signal _{S B} is input to the control unit 11. Signal S _B is a binary signal which takes either of the signal level of the high level or low level, represents the height relationship between the comparison voltage V _B and the output voltage V _OUT. Specifically, the signal _{S B} in the output voltage _{V OUT} is lower than the comparison voltage _{V B} (i.e., when the _"V OUT _{<V B")} becomes a high level, the output voltage _{V OUT} is than compared voltage _{V B} signal _{S B} becomes a low level at high time (i.e. when the _{"V OUT> V B")} . When the output voltage _{V OUT} is exactly coincides with the comparison voltage _{V B,} the signal _{S B} becomes the high level or low level.

Signal S _B is abnormal to the output voltage V _OUT becomes too low is a signal indicating whether or not (hereinafter, a low voltage is referred to as error), the signal S _B is a low voltage having a logic value of the monitoring operation to be described later, "1" Indicates the occurrence and existence of anomalies. In this example, the positive logic adopted for the signal S _B, has a logical value of high level of the signal S _B is "1", the signal S _B of low level has a logical value of "0" It is assumed that there is. However, may also be negative logic is employed for the signal S _B, in this case, the type the comparison voltage V _B to the inverting input terminal of the comparator 13B, the output voltage V _OUT of the non-inverting comparator 13B You can input to the input terminal.

The memory 14 reads and writes arbitrary data under the control of the control unit 11. The memory 14 includes a volatile memory 14a and a non-volatile memory 14b. The volatile memory 14a can be configured by a DRAM (Dynamic Random Access Memory) or the like, and the non-volatile memory 14b can be configured by a flash memory or the like.

The operation in the test process executed before the shipment of the voltage monitoring circuit 10 will also be described later, but first, the operation of the power supply device 1 and the power supply system after the test process (this is referred to as an actual operation operation) will be described. In the actual operation, the voltage monitoring circuit 10 can perform a setting operation or a monitoring operation.

FIG. 3 is an operation flowchart of the voltage monitoring circuit 10 in the actual operation. In the actual operation, when the voltage monitoring circuit 10 is activated, the setting operation is executed in step S1, and thereafter, the monitoring operation in step S3 is continuously executed through the process of step S2. However, the process of step S2 may be considered to belong to the setting operation or the monitoring operation. It may be considered that the voltage monitoring circuit 10 operates in any of the operation modes of the setting mode in which the setting operation is performed and the monitoring mode in which the monitoring mode is performed. In this case, it can be considered that a mode setting unit for setting the setting mode or the monitoring mode to the operation mode is provided in the control unit 11.

The setting operation of step S1 will be described. In the actual operation, the setting operation of step S1 is executed by the control unit 11 every time the power supply device 1 is started (hence, every time the voltage monitoring circuit 10 is started). However, it is assumed that the setting operation is executed at the timing when the output voltage V _OUT is considered to be stabilized at the target voltage V _TG. For example, it is preferable that the setting operation is performed after a predetermined time has elapsed from the up-edge timing of _{the signal PGOOD.}

The setting operation includes a first sweep process and a second sweep process. The first and second sweep processes may be executed in parallel at the same time, but they may be executed sequentially at different timings.

In the first sweep process, the control unit 11, as shown in FIG. 4 (a), the digital value _{D A} input to DAC12A from a predetermined lower digital value _{D A_RANGE_L} to a predetermined upper digital value _{D A_RANGE_H} "1" Increase in increments ( _{DA_RANGE_L} < _{DA_RANGE_H} ). Thus, in the first sweep process, comparing the voltage _{V A is} in the predetermined first sweep voltage range up voltage when the voltage when a _{"D A = D A_RANGE_L"} is _{"D A =} D _{A_RANGE_H"} It will increase monotonically.

As _"D A _{= D A_RANGE_L"} comparison voltage _{V A} when a is sufficiently lower than the target voltage _{V TG, and,} from _{"D A = D A_RANGE_H"} target voltage _{V TG} is compared voltage _{V A} when it is _{The digital values DA_RANGE_L} and _{DA_RANGE_H} are set so as to be sufficiently high. _Therefore, when it is _{"D A = D A_RANGE_L"} is _{"V A <V OUT"} While the sounding signal _{S A} becomes high _level, when a _{"D A = D A_RANGE_H"} is _{"V A>} V _OUT" and becomes the signal S _a becomes low level, the process by the signal S _a monotonically increasing the contrast voltage V _a at the first sweep process is changed from the high level to the low level. Control unit 11, in the course of monotonic increase in the contrast voltage V _A at the first sweep process, to obtain the preceding or digital values D _A immediately after the signal S _A is switched from the high level to the low level as the first reference value D _AREF .. In the setting operation of step S1, the acquired first reference value D _AREF is stored in the memory (volatile memory) 14a (see also FIG. 5).

Incidentally, it may be reduced by "1" to the lower digital value _{D A_RANGE_L} digital values _{D A} from the upper digital value _{D A_RANGE_H} in the first sweep process. In this case, since the comparison voltage V _A at the first sweep process decreases monotonically, before or digital values D _A immediately after the first reference value signal S _A in the course of its monotonously decreasing is switched from the low level to the high level It may be acquired as _{D AREF.}

In summary, in the setting operation in step S1, the first sweep process to vary the contrast voltage V _A through the variation of digital values D _A is executed, between the output voltage V _OUT and comparison voltage V _A in the course of the first sweep process digital values _{D a} when the height relationship is inverted is obtained as a first reference value _{D AREF.} When the inversion was observed by the signal S _A of the high and low relationship between the output voltage V _OUT and comparison voltage V _A, and ends the variation of digital values D _A in the first sweep process (hence variations in the contrast voltage V _A) Is also good.

In the second sweep process, the control unit 11, as shown in FIG. 4 (b), the digital value _{D B} input to DAC12B from a predetermined lower digital value _{D B_RANGE_L} to a predetermined upper digital value _{D B_RANGE_H} "1" Increase in increments ( _{DB_RANGE_L} < _{DB_RANGE_H} ). Thus, in the second sweep process, comparing the voltage _{V B is} within a predetermined second sweep voltage range from the voltage when a _{"D B = D B_RANGE_L"} up voltage when a _{"D B =} D _{B_RANGE_H"} It will increase monotonically.

As _"D B _{= D B_RANGE_L"} comparison voltage _{V B} when a is sufficiently lower than the target voltage _{V TG, and,} from _{"D B = D B_RANGE_H"} target voltage _{V TG} is compared voltage _{V B} when a _{The digital values DB_RANGE_L} and _{DB_RANGE_H} are set so as to be sufficiently high. _Therefore, when it is _{"D B = D B_RANGE_L"} is _{"V B <V OUT"} While becomes the signal _{S B} becomes a low _level, when it is _{"D B = D B_RANGE_H"} is _{"V B>} V _OUT" and becomes the signal S _B becomes high level, the signal S _B monotonically increases in the course of comparing the voltage V _B at the second sweep process is switched from the low level to the high level. Control unit 11, a monotonic increase in the course of the comparison voltage V _B at the second sweep process, the signal S _B to obtain the immediately before or after the digital value D _B changes over from the low level to the high level as the second reference value D _BREF .. In the setting operation of step S1, the acquired second reference value D _BREF is stored in the memory (volatile memory) 14a (see also FIG. 5).

Incidentally, it may be reduced by "1" to the lower digital value _{D B_RANGE_L} digital value _{D B} from the upper digital value _{D B_RANGE_H} in the second sweep process. In this case, since the comparison voltage V _B at the second sweep process decreases monotonically, the digital value D _B immediately before or after the process signal S _B of the monotonous decrease is switched from the high level to the low level second reference value It _may be acquired as D BREF.

In summary, in the setting operation in step S1, the second sweep process is performed to vary the contrast voltage V _B through a variation of digital values D _B, between the output voltage V _OUT and comparison voltage V _B in the course of the second sweep process _{The digital value D B} when the high-low relationship is reversed is acquired as the second reference value D _BREF. When the inversion was observed by the signal S _B of high and low relationship between the output voltage V _OUT and comparison voltage V _B, and ends the variation of digital values D _B in the second sweep process (hence variations in the contrast voltage V _B) Is also good.

Incidentally, the variation range of the digital values D _A in the first sweep process (the variation range of the comparison voltage V _A in other words), the variation of the variation range (contrast in other words the voltage V _B of the digital value D _B in the second sweep process The ranges) may be in agreement with each other or may be different.

After step S1, in step S2, the control unit 11 sets the first abnormality determination value _{DA_TH based on the first reference value D AREF} , and sets the second abnormality determination value D A_TH based on the second reference value D _BREF. Set _{B_TH. Specifically,} according to _{"D A_TH = D AREF + ΔD} A" and _{"D B_TH = D BREF -ΔD B} ", sets the abnormality determination value _{D A_TH} and _{D B_TH.} ΔD _A is a positive first predetermined value corresponding to the upper voltage monitoring width, and ΔD _B is a positive second predetermined value corresponding to the lower voltage monitoring width. The predetermined values ΔD _A and ΔD _B may be in agreement with each other or may be different from each other.

The _"D A _{= D A_TH"} comparison voltage _{V A} at the time is, referred to as a first abnormality determination voltage (or the upper abnormality determination voltage), is referred to by the symbol _{"V A_TH".} The _"D B _{= D B_TH"} a comparison voltage _{V B} when it is referred to as a second abnormality determination voltage (or the lower abnormality determination voltage), is referred to by the symbol _{"V B_TH".}

FIG. 6 shows the relationship between the _{output voltage V OUT} , the first abnormality determination voltage V _{A_TH} , and the second abnormality determination voltage V _{B_TH} when the setting operation of step S1 is executed. Respect to the output voltage _{V OUT} at the time of execution of the setting operation in step S1, the first abnormality determination voltage _{V A_TH} is higher by above the voltage monitoring width [Delta] V _A corresponding to the first predetermined value [Delta] D _A, the second abnormality determination voltage _{V B_TH} low by the voltage monitoring width [Delta] V _B of the lower side corresponding to the second predetermined value [Delta] D _B. The voltage monitoring widths ΔVA _A and ΔV _B may be the same as each other or may be different from each other.

In step S3 following step S2, a monitoring operation is executed. The monitoring operation is continuously executed after steps S1 and S2. In the monitoring operation, the control unit _11, (a i.e. _{"V A =} V _{A_TH"} and _{"V B = V B_TH")} "D A = D A_TH" a and _{"D B =} D _{B_TH",} on the comparator based on 13A and 13B output signals _{S a} and _{S B} of the monitors an abnormality presence or absence of the output voltage _{V OUT} to be monitored voltage. The abnormalities of the output voltage V _OUT include the above-mentioned overvoltage abnormality and undervoltage abnormality.

In the monitoring operation, the control unit 11, "1" signal S _A with a logical value when is being output _(here signal S _A of the high _level), i.e., the output voltage V _OUT is the first abnormality determination voltage V when the signal S _a indicating that higher than _{A_TH} is output from the comparator 13A, determines that the overvoltage abnormality has occurred. When the control unit 11 determines that an overvoltage abnormality has occurred, the control unit 11 can output a predetermined abnormality signal to an external circuit (not shown) of the voltage monitoring circuit 10 as an abnormality detection signal DET via the terminal TM5. Alternatively, it can be output (transmitted) to the host control circuit 30 by communication via the terminal TM6. The external circuit of the voltage monitoring circuit 10 may be the host control circuit 30. The abnormality signal output when it is determined that an overvoltage abnormality has occurred is an overvoltage abnormality signal indicating that an overvoltage abnormality has occurred.

In the monitoring operation, the control unit 11, "1" signal S _B with a logical value when is being output _(here the high level of the signal S _{B is),} i.e., the output voltage V _OUT is the second abnormality determination voltage V when the signal S _B indicating that less than _{B_TH} is output from the comparator 13B, it determines that the low-voltage abnormality has occurred. When the control unit 11 determines that a low voltage abnormality has occurred, the control unit 11 can output a predetermined abnormality signal to an external circuit (not shown) of the voltage monitoring circuit 10 as an abnormality detection signal DET via the terminal TM5. Alternatively, it can be output (transmitted) to the host control circuit 30 by communication via the terminal TM6. The external circuit of the voltage monitoring circuit 10 may be the host control circuit 30. The abnormality signal output when it is determined that a low voltage abnormality has occurred is a low voltage abnormality signal indicating that a low voltage abnormality has occurred.

The abnormal signal output when it is determined that an overvoltage abnormality has occurred and the abnormal signal output when it is determined that an undervoltage abnormality has occurred are two types of abnormalities that can be distinguished from each other. It may be a signal or a common abnormal signal. When they are common abnormal signals, it is possible to distinguish whether an overvoltage abnormality or an undervoltage abnormality has occurred in the circuit that received the abnormal signal (external circuit of voltage monitoring circuit 10 or higher control circuit 30). Not done.

The circuit (external circuit of the voltage monitoring circuit 10 or the host control circuit 30) that has received the abnormality signal executes a predetermined abnormality handling process. The content of the abnormality handling process is arbitrary. For example, in the abnormality handling process, the operation of the power supply circuit 20 can be stopped, or a predetermined warning display can be performed using an image display unit or a light emitting unit (not shown).

In the power supply device 901 of FIG. 10, since it is unknown in which direction the output voltage and the abnormality determination voltage vary with respect to the target (Vtg, Vovd_tg, Vuvd_tg), a form including the absolute value variation thereof. You can only monitor the voltage with. On the other hand, according to the power supply device 1 according to the present embodiment _{, the output voltage V OUT} and the contrast voltage ( _VA , V _B ) are referred to with reference to _{the actual output voltage V OUT reflecting the direction and magnitude of the variation. The abnormality determination voltages VA_TH} and _{VB_TH,} which are the thresholds for the presence or absence of an abnormality, can be set with reference to the contrast voltage when the high-low relationship between them is actually reversed. Therefore, the variation in the absolute values of the output voltage and the abnormality determination voltage is canceled, and the voltage monitoring accuracy can be expected to be improved.

Hereinafter, applied technology, deformation technology, and the like related to the power supply device 1 will be described in a plurality of examples. The matters described above in the present embodiment are applied to the following examples unless otherwise specified and there is no contradiction, and in each embodiment, the description in each embodiment is prioritized for matters contradictory to the above-mentioned matters. May be done. Further, as long as there is no contradiction, the matters described in any of the plurality of examples shown below can be applied to any other example (that is, any two or more of the plurality of examples). It is also possible to combine the examples of).

[First Example]
The first embodiment will be described. As shown in FIG. 7, it is preferable that the design upper limit value _{DA_LIM which is an example of the first fixed value and the design lower limit value D B_LIM} which is an example of the second fixed value are stored in the non-volatile memory 14b in advance.

The design upper limit value _{DA_LIM} is a design allowable upper limit value with respect to the first reference value D _AREF. When there is no abnormality in the output voltage V _{OUT , the maximum expected value of the first reference value D AREF} to be acquired in the setting operation of step S1 (FIG. 3) is estimated at the design stage of the power supply device 1. Can be done. Based on the maximum value of the expected value (for example, a value obtained by adding a predetermined margin to the maximum value of the expected value), the design upper limit value _{DA_LIM} can be set.

The design lower limit value D _{B_LIM} is a design allowable lower limit value with respect to the second reference value D _BREF. When there is no abnormality in the output voltage V _{OUT , the minimum expected value of the second reference value D BREF} to be acquired in the setting operation of step S1 (FIG. 3) is estimated at the design stage of the power supply device 1. Can be done. Based on the minimum value of the expected value (for example, a value obtained by subtracting a predetermined margin from the minimum value of the expected value), the design lower limit value _{DB_LIM} can be set.

A state in which the first reference value D _AREF exceeds the design upper limit value D _{A_LIM} corresponds to an overvoltage state of the output voltage V _{OUT, and} a state in which the second reference value D _BREF is lower than the design lower limit value D _{B_LIM} is the output voltage V _OUT . Corresponds to the low voltage state.

Therefore, in the setting operation of step S1, when the control unit 11 _{acquires the first reference value D AREF} and the second reference value D _BREF , the control unit 11 compares the first reference value D _AREF with the design upper limit value _{DA_LIM} and makes a second. 2 The reference value D _BREF is compared with the design lower limit value D _{B_LIM,} and if the inequality "D _AREF > D _{A_LIM} " is satisfied, it may be determined that the output voltage V _OUT is in an overvoltage state, and the inequality "D BREF <D _{" may be determined. When} "B_LIM" is satisfied, it may be determined that the output voltage V _OUT is in the low voltage state. In the setting operation of step S1, the inequality _{"D AREF>} D _{A_LIM"} determination that the time is not satisfied is in an overvoltage condition of not made, the determination that the time not satisfied the inequality _{"D BREF <D B_LIM"} is in the low voltage state Not done.

Operation after the output voltage V _OUT is determined to be in an over-voltage condition or a low voltage state in the setting operation step, after the output voltage V _OUT in the monitoring operation phase is determined to be in an over-voltage condition or a low voltage state It may be the same as the operation of. That is, when the control unit 11 determines that the output voltage V _OUT is in the overvoltage state or the undervoltage state at the stage of the setting operation, the control unit 11 uses the predetermined abnormality signal as the abnormality detection signal DET via the terminal TM5 of the voltage monitoring circuit 10. It can be output to an external circuit (not shown), or can be output (transmitted) to the host control circuit 30 by communication via the terminal TM6. The external circuit of the voltage monitoring circuit 10 may be the host control circuit 30. The circuit that has received the abnormality signal (external circuit of the voltage monitoring circuit 10 or the upper control circuit 30) may execute a predetermined abnormality handling process such as stopping the operation of the power supply circuit 20.

The monitoring operation in step S3, it is possible to reference the output voltage V _OUT at the time of execution setting operation of step S1, to monitor whether the output voltage V _OUT fluctuates beyond the voltage range [Delta] V _A or [Delta] V _B (See FIG. 6). If the method of the first embodiment is added, it is possible to determine whether or not there is an abnormality at the absolute value level of the _{output voltage V OUT before the monitoring operation.}

[Second Example]
A second embodiment will be described. As shown in FIG. 8, the non-volatile memory 14b, is also an example of a first fixed value is an example of a first initial reference value _{D AREF_INI} and second fixed value second initial reference value _{D BREF_INI} is not stored in advance good.

The values D _{AREF_INI} and D _{BREF_INI} are stored in the non-volatile memory 14b at the stage of the test process executed before the shipment of the voltage monitoring circuit 10.

In the test step, a board on which the voltage monitoring circuit 10 and the power supply circuit 20 are mounted is prepared, and for example, a predetermined test command signal is input from the test circuit (not shown) to the control unit 11 via the terminal TM6. In the test process, it is assumed that the power supply circuit 20 is operating and the output voltage V _{OUT aiming at the target voltage V TG} is output. In the test step, when the control unit 11 receives the test command signal, the control unit 11 executes the above-mentioned first sweep process and second sweep process. Control unit 11 obtains the digital value _{D A} when the height relationship between the output voltage _{V OUT} and comparison voltage _{V A} in the course of the first sweep process test process is reversed as the first initial reference value _{D AREF_INI,} test to obtain a digital value _{D B} when the high-low relationship between the second step in the output voltage _{V OUT} and comparing the voltage of the sweep process _{V B} step is inverted as the second initial reference value _{D BREF_INI.}

The acquired first initial reference value D _{AREF_INI} and the second initial reference value D _{BREF_INI} are stored in the non-volatile memory 14b. The storage in the non-volatile memory 14b may be performed by the control unit 11 or may be realized by another circuit prepared in the test step.

_{The usage of the values D AREF_INI} and D _{BREF_INI} in the actual operation after the test process will be described. In the setting operation of step S1 in the actual operation, when the control unit 11 _{acquires the first reference value D AREF} and the second reference value D _BREF , the control unit 11 sets the first reference value D _AREF as the first initial reference value D _{AREF_INI} . the second reference value _{D BREF} comparing the second initial reference value _{D BREF_INI} with comparison. Then, when the first difference absolute value | D _AREF- D _{AREF_INI} | or the second difference absolute value | D _BREF- D _{BREF_INI} | exceeds a predetermined difference upper limit value, the control unit 11 sets the output voltage V _OUT . It may be determined that there is an abnormality (when both the first absolute value of the difference and the second absolute value of the difference are equal to or less than the predetermined upper limit of the difference, it is not determined that the _{output voltage V OUT is abnormal).} This is because the state in which the first or second absolute difference value exceeds the predetermined difference upper limit value is considered to correspond to the state in which the _{output voltage V OUT becomes abnormally high or abnormally low due to aged deterioration or the like.}

When the control unit 11 determines that an abnormality has occurred based on the above-mentioned first or second absolute difference difference, the control unit 11 outputs a predetermined abnormality signal indicating that there is an abnormality _{in the output voltage V OUT at the stage of the setting operation.} , The abnormality detection signal DET can be output to the external circuit (not shown) of the voltage monitoring circuit 10 via the terminal TM5, or can be output (transmitted) to the host control circuit 30 by communication via the terminal TM6. .. The external circuit of the voltage monitoring circuit 10 may be the host control circuit 30. The circuit that has received the abnormality signal (external circuit of the voltage monitoring circuit 10 or the upper control circuit 30) may execute a predetermined abnormality handling process such as stopping the operation of the power supply circuit 20.

The monitoring operation in step S3, it is possible to reference the output voltage V _OUT at the time of execution setting operation of step S1, to monitor whether the output voltage V _OUT fluctuates beyond the voltage range [Delta] V _A or [Delta] V _B (See FIG. 6). If the method of the second embodiment is added, it is possible to determine whether or not there is an abnormality _{in the output voltage V OUT before the monitoring operation.}

Further, in the test step, _{it is checked whether the output voltage V OUT} satisfies the predetermined inspection specifications, and only the power supply device 1 satisfying the predetermined inspection specifications is shipped and proceeds to the actual operation operation of FIG. Test specifications are more stringent than the specifications to be satisfied by the output voltage V _OUT at a production operation (e.g., output voltage V _OUT is the voltage accuracy to be satisfied, if a 2% ± in the specification of the production operation, inspection ± 1% in the specifications). Therefore, if the reference values (D _AREF , D _BREF ) acquired in the actual operation match or are close to the initial reference values (D _{AREF_INI} , D _{BREF_INI} ) in the test process, the output voltage V in the actual operation is V. _{Satisfaction of OUT} specifications is guaranteed. It is advisable to set the above difference upper limit value so that the specifications of the output voltage V _{OUT are satisfied in the actual operation.}

The first embodiment and the second embodiment can be combined. In this case, based on the first reference value D _AREF and the second reference value D _BREF and the four fixed values _{DA_LIM} , D _{AREF_INI} , _{DB_LIM} and D _{BREF_INI} (see FIGS. 7 and 8), the setting operation is performed. The presence or absence of an abnormality in the output voltage V _{OUT can be determined in steps.}

[Third Example]
A third embodiment will be described. In the actual operation, it was stated that the setting operation is executed when the power supply device 1 is started, but after the power supply device 1 is started (hence, after the voltage monitoring circuit 10 is started), the setting operation is performed at an arbitrary timing. You may.

For example, the control unit 11 may perform the setting operation when it receives a predetermined command signal requesting the execution of the setting operation from the host control circuit 30. Apart from this, the setting operation may be executed even when the power supply device 1 is started.

That is, for example, when the power supply device 1 is activated (thus, when the voltage monitoring circuit 10 is activated), the control unit 11 performs the setting operation of step S1 as the first setting operation as described above with reference to FIG. , The monitoring operation of step S3 is started through the process of step S2. After that, when the control unit 11 receives the command signal, the setting operation of step S1 is performed for the second time, and then the monitoring operation of step S3 is restarted through the processing of step S2.

By the second setting operation, the reference values D _AREF and D _BREF stored in the memory 14a are updated with _{the reference values D AREF} and D _BREF acquired in the second setting operation. In the monitoring operation restarted after the second setting operation, the abnormality judgment values _{DA_TH} and _{DB_TH} are reset _{based on the reference values D AREF} and D _{BREF acquired in the second setting operation.} Then, the presence or absence of abnormality of the output voltage V _{OUT is monitored.}

The following usage patterns can be considered. There are a plurality of modes including the first mode and the second mode as the operation mode of the load device LD (see FIG. 1), and the operation mode of the load device LD is compared with the case where the operation mode of the load device LD is the first mode. When is the second mode, the power consumption of the load device LD is assumed to be large. In this case, it is assumed that the operation mode of the load device LD is initially the first mode, and the first setting operation is performed when the operation mode of the load device LD is the first mode. After that, when the operation mode of the load device LD is switched from the first mode to the second mode under the control of the upper control circuit 30 or under the control of another circuit, the upper control is performed after switching to the second mode. The circuit 30 transmits the above command signal to the control unit 11. The control unit 11 performs the second setting operation when the command signal is received.

_{When the load dependence of the output voltage V OUT} of the power supply circuit 20 _{is relatively large, the output voltage V OUT} may fluctuate to a non-negligible level before and after switching from the first mode to the second mode. Therefore, when the mode is switched from the first mode to the second mode, it is _{preferable to reacquire the reference values V AREF} and V BREF suitable for the second mode by performing the setting operation again, which is more appropriate. Voltage monitoring can be performed. The same applies when switching from the second mode to the first mode.

In each of the first setting operation and the second setting operation, the processes shown in the first and second embodiments may be performed. Further, in the second setting operation, the first reference value V _AREF acquired in the first setting operation and the first reference value V _AREF acquired in the second setting operation are compared. When the absolute value of the difference is equal to or greater than a predetermined value, the control unit 11 _{determines that there is an abnormality in the output voltage V OUT} , and transmits a predetermined abnormality signal indicating the existence and occurrence of the abnormality via the terminal TM5. The abnormality detection signal DET may be output to an external circuit (not shown) of the voltage monitoring circuit 10 or may be output (transmitted) to the host control circuit 30 by communication via the terminal TM6. If the power supply circuit 20 is operating normally, it is considered that the first reference value _VAREF is unlikely to fluctuate to exceed a predetermined value between the first setting operation and the second setting operation. Is.

Similarly, in the second setting operation, the second reference value V _BREF acquired in the first setting operation is compared with _{the second reference value V BREF} acquired in the second setting operation. When the difference between them is an absolute value or more, the control unit 11 _{determines that there is an abnormality in the output voltage V OUT} , and sends a predetermined abnormality signal indicating the existence and occurrence of the abnormality to the terminal TM5. The abnormality detection signal DET may be output to an external circuit (not shown) of the voltage monitoring circuit 10 via the terminal TM6, or may be output (transmitted) to the host control circuit 30 by communication via the terminal TM6.

The external circuit of the voltage monitoring circuit 10 may be the host control circuit 30. The circuit that has received the abnormality signal (external circuit of the voltage monitoring circuit 10 or the upper control circuit 30) may execute a predetermined abnormality handling process such as stopping the operation of the power supply circuit 20.

[Fourth Example]
A fourth embodiment will be described.

The power supply device 1 according to the present embodiment can be mounted on any device, and can be mounted on a vehicle such as an automobile. FIG. 9 shows a schematic configuration of a vehicle CC, which is an automobile equipped with the power supply device 1. The output voltage of the battery VS provided in the vehicle CC can be the _{input voltage VIN.} Alternatively, a voltage generated by a power supply device (not shown) other than the power supply device 1 based on the output voltage of the battery VS may be used as the input voltage _VIN of the power supply device 1. The load device LD may be any electrical device provided in the vehicle CC. For example, the load device LD may be an ECU (Electronic Control Unit). The ECU performs travel control of the vehicle CC, drive control of an air conditioner, a lamp, a power window, and an airbag provided in the vehicle CC. Alternatively, for example, those air conditioners, lamps, power windows or airbags may be load device LDs. The load device LD may include a power supply circuit different from the power supply circuit 20.

_{Although it was stated that the reference values D AREF} and D _BREF are saved in the memory 14a in the setting operation in the actual operation operation (see FIGS. 3 and 5), the reference values D _AREF and D _BREF are replaced with the reference values D _AREF and D _BREF. Other values based on (for example, abnormality determination values _{DA_TH} and _{DB_TH} ) may be stored in the memory 14a. In conjunction with this, in the test process, _{instead of the initial reference values D AREF_INI} and D _{BREF_INI} (see FIG. 8) _{, other values based on the initial reference values D AREF_INI} and D _{BREF_INI} are stored in the non-volatile memory 14b. Is also good.

In the voltage monitoring circuit 10 described above, _{both the overvoltage state and the undervoltage state of the output voltage V OUT} can be detected, but in the voltage monitoring circuit 10, only any one of the overvoltage state and the undervoltage state can be detected. It may be detectable. That is, for example, the DAC 12B and the comparator 13B may be deleted from the voltage monitoring circuit 10 of FIG. 1 when only the overvoltage state is detected, and from the voltage monitoring circuit 10 of FIG. 1 when only the low voltage state is detected. The DAC 12A and the comparator 13A may be deleted.

The voltage monitoring circuit 10 may be formed in the form of a semiconductor integrated circuit. A semiconductor device including a semiconductor integrated circuit including a voltage monitoring circuit 10 and a housing for accommodating the semiconductor integrated circuit can be configured.

For any signal or voltage, the high-level and low-level relationships may be reversed in a manner that does not compromise the above-mentioned gist.

The voltage monitoring circuit according to one aspect of the present invention is _{a voltage monitoring circuit (10) that monitors the monitored voltage (V OUT} ), and uses a D / A converter (12A, 12B) to compare the voltage ( _VA , 12B). A contrast voltage output unit (12) that outputs V _B ), a voltage comparison unit (13) that compares the monitored voltage with the contrast voltage, and a control unit (11) that executes a setting operation or a monitoring operation. wherein the comparison voltage output unit may output the input digital value from the control unit _{(D a,} D _B) of the comparison voltage corresponding to from the D / a converter, the control unit, in the setting operation, A sweep process that fluctuates the contrast voltage through the fluctuation of the input digital value is executed, and the input digital value when the height relationship between the monitored voltage and the contrast voltage is reversed in the process of the sweep process is used as a reference value. (DA _AREF , D _BREF ), and then, in the monitoring operation, the abnormality determination values ( _{DA_TH} , _{DB_TH} ) based on the reference value are set to the input digital values, and then the comparison result of the voltage comparison unit is set. Based on the above, the presence or absence of abnormality in the monitored voltage is determined.

In the voltage monitoring circuit according to one aspect of the present invention, the comparison voltage output unit has a first input digital value from the control unit (D _A) of the first comparison voltage by converting D / _A (V A) and the 1D / a converter for outputting (12A), the 2D / a for outputting a second input digital value _{(D B)} a second comparison voltage by converting D / a _{(V B)} from the control unit The voltage comparison unit has a converter (12B), and the voltage comparison unit compares the monitoring target voltage with the second comparison voltage with the first comparison unit (13A) for comparing the monitoring target voltage with the first comparison voltage. A second comparison unit (13B) is provided, and the control unit executes a first sweep process that fluctuates the first contrast voltage through a fluctuation of the first input digital value in the setting operation. In the process of the first sweep process, the first input digital value when the height relationship between the monitored voltage and the first contrast voltage is reversed _{is acquired as the first reference value (DAREF} ), and the second When the second sweep process that fluctuates the second contrast voltage through the fluctuation of the input digital value is executed, and the height relationship between the monitored voltage and the second contrast voltage is reversed in the process of the second sweep process. The second input digital value is _{acquired as the second reference value (DBREF} ), and then, in the monitoring operation, the first abnormality determination value ( _{DA_TH} ) based on the first reference value is used as the first input digital value. After setting and setting the second abnormality determination value ( _{DB_TH} ) based on the second reference value to the second input digital value, the above is made based on the comparison results of the first comparison unit and the second comparison unit. It may be configured to determine the presence or absence of an abnormality in the monitored voltage.

In the present embodiment, the output voltage V _OUT of the power supply circuit 20 is the monitored voltage for the voltage monitoring circuit 10, but the monitored voltage is not limited to this, and any DC voltage that needs to be monitored is not limited to this. It may be.

The embodiments of the present invention can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present invention, and the meanings of the terms of the present invention and the constituent requirements are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

1 Power supply 10 Voltage monitoring circuit 11 Control unit 12 Contrast voltage output unit 13 Voltage comparison unit 14 Memory 14a Volatile memory 14b Non-volatile memory 20 Power supply circuit 30 Upper control circuit

Claims (12)

A voltage monitoring circuit that monitors the monitored voltage.
A contrast voltage output unit that outputs a contrast voltage using a D / A converter,
A voltage comparison unit that compares the monitored voltage with the contrast voltage,
It is equipped with a control unit that executes setting operation or monitoring operation.
The contrast voltage output unit outputs the contrast voltage according to the input digital value from the control unit from the D / A converter.
The control unit
In the setting operation, a sweep process for varying the contrast voltage through fluctuations in the input digital value is executed, and the input when the height relationship between the monitored voltage and the contrast voltage is reversed in the process of the sweep process. Get the digital value as the reference value,
After that, in the monitoring operation, the abnormality determination value based on the reference value is set to the input digital value, and then the presence or absence of the abnormality of the monitored voltage is determined based on the comparison result of the voltage comparison unit. Voltage monitoring circuit. 1. The control unit is characterized in that the abnormality determination value is set based on the reference value so that the relative voltage in the monitoring operation is higher or lower than the monitored voltage in the setting operation. The voltage monitoring circuit described in. The control unit
The abnormality determination value is set based on the reference value so that the relative voltage in the monitoring operation is higher than the monitoring target voltage in the setting operation.
When a signal indicating that the monitored voltage is higher than the contrast voltage corresponding to the abnormality determination value in the monitoring operation is output from the voltage comparison unit, it is determined that the monitored voltage has an abnormality. 2. The voltage monitoring circuit according to claim 2. The control unit
The abnormality determination value is set based on the reference value so that the relative voltage in the monitoring operation is lower than the monitoring target voltage in the setting operation.
When a signal indicating that the monitored voltage is lower than the contrast voltage corresponding to the abnormality determination value is output from the voltage comparison unit in the monitoring operation, it is determined that the monitored voltage has an abnormality. 2. The voltage monitoring circuit according to claim 2. Further equipped with a memory that holds a predetermined fixed value,
The voltage monitoring according to any one of claims 1 to 4, wherein the control unit determines whether or not there is an abnormality in the monitored voltage based on the reference value and the fixed value in the setting operation. circuit. The contrast voltage output unit outputs the first contrast voltage by D / A converting the first input digital value from the control unit, and the second input digital value from the control unit. It has a second D / A converter that outputs a second contrast voltage by D / A conversion.
The voltage comparison unit includes a first comparison unit that compares the monitored voltage with the first comparison voltage, and a second comparison unit that compares the monitoring target voltage with the second comparison voltage.
The control unit
In the setting operation, the first sweep process that fluctuates the first contrast voltage through the fluctuation of the first input digital value is executed, and in the process of the first sweep process, between the monitored voltage and the first contrast voltage. The first input digital value when the high-low relationship of is reversed is acquired as the first reference value, and the second sweep process that fluctuates the second contrast voltage through the fluctuation of the second input digital value is executed. In the process of the second sweep process, the second input digital value when the height relationship between the monitored voltage and the second contrast voltage is reversed is acquired as the second reference value.
After that, in the monitoring operation, the first abnormality determination value based on the first reference value is set to the first input digital value, and the second abnormality determination value based on the second reference value is set to the second input digital value. The voltage monitoring circuit according to claim 1, wherein after setting, it is determined whether or not there is an abnormality in the monitored voltage based on the comparison results of the first comparison unit and the second comparison unit. The control unit sets the first abnormality determination value based on the first reference value so that the first contrast voltage in the monitoring operation becomes higher than the monitoring target voltage in the setting operation, and also sets the setting operation. The voltage monitoring according to claim 6, wherein the second abnormality determination value is set based on the second reference value so that the second contrast voltage in the monitoring operation is lower than the monitoring target voltage in the above. circuit. The control unit
When a signal indicating that the monitored voltage is higher than the first contrast voltage corresponding to the first abnormality determination value in the monitoring operation is output from the first comparison unit, or
When a signal indicating that the monitored voltage is lower than the second contrast voltage corresponding to the second abnormality determination value in the monitoring operation is output from the second comparison unit.
The voltage monitoring circuit according to claim 7, wherein it is determined that the monitored voltage has an abnormality. Further provided with a memory for holding a predetermined first fixed value and a predetermined second fixed value,
In the setting operation, the control unit has an abnormality in the monitored voltage based on the first reference value and the first fixed value, or based on the second reference value and the second fixed value. The voltage monitoring circuit according to any one of claims 6 to 8, wherein the voltage monitoring circuit is characterized in that. The voltage monitoring circuit according to any one of claims 1 to 9, wherein the control unit can execute the setting operation each time the voltage monitoring circuit is activated. The voltage monitoring circuit according to any one of claims 1 to 10, wherein the control unit can execute the setting operation based on a signal from a higher-level control circuit connected to the voltage monitoring circuit. The voltage monitoring circuit according to any one of claims 1 to 11.
It is equipped with a power supply circuit that generates an output voltage based on the input voltage.
A power supply device characterized in that the output voltage is a monitored voltage to be monitored by the voltage monitoring circuit.

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