JP2021093556A - RC-IGBT semiconductor device - Google Patents

Abstract

To provide an RC-IGBT semiconductor device in which the peak forward surge current tolerance amount can be improved.SOLUTION: An RC-IGBT semiconductor device 1 includes: a semiconductor layer 2 including a front surface and a rear surface 2b; a gate pad 9 covering the front surface apart from one side of the front surface in an X direction in a plan view and electrically connected to a gate structure; a p-type collector region 23 formed in a surface layer part of the rear surface 2b; and a plurality of n-type first lines 52 (cathode line regions) formed on the surface layer part of the rear surface 2b so as not to overlap with the gate pad 9 in a plan view, extending in a band shape along the X direction in a plan view, and arranged with a space in a Y direction orthogonal to the X direction in a plan view. Each of the first lines 52 includes a first end part on the gate pad 9 side and a second end part on the opposite side in a plan view. The second end parts in the X direction are aligned in the Y direction.SELECTED DRAWING: Figure 10

Description

The present invention relates to an RC-IGBT (Reverse Conducting --Insulated Gate Bipolar Transistor) semiconductor device.

FIG. 2 of Patent Document 1 discloses a reverse conductive insulated gate bipolar transistor called RC (Reverse Conducting) -IGBT as an example of a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor) and a diode. Has been done.
The reverse conductive insulated gate bipolar transistor according to FIG. 2 of Patent Document 1 includes a semiconductor layer. A p-type channel region is formed on the surface layer portion on the surface side of the semiconductor layer. An n-type emitter region is formed on the surface layer of the channel region. An n-type drift region is formed on the back surface side of the semiconductor layer with respect to the channel region so as to be electrically connected to the channel region. A p-type collector region and a plurality of n-type cathode regions are formed on the surface layer portion on the back surface side of the semiconductor layer so as to be electrically connected to the drift region. The plurality of n-type cathode regions are formed in a matrix-like regular arrangement with respect to the back surface of the semiconductor layer at intervals in one direction and along the orthogonal direction in the one direction.

Japanese Unexamined Patent Publication No. 2010-263215

In the configuration disclosed in FIG. 2 of Patent Document 1, increasing the plan-view area of a plurality of cathode regions tends to improve the peak forward surge current withstand, which is the withstand for the peak forward _{surge current I FSM of the semiconductor device.} There is. On the other hand, if the plan-view area of the plurality of cathode regions is reduced, the peak forward surge current withstand capability of the semiconductor device tends to decrease. That is, in the configuration disclosed in FIG. 2 of Patent Document 1, a substantially linear relationship is established between the plan-view area of the plurality of cathode regions and the peak forward surge current withstand capability of the semiconductor device.

Therefore, even if the plan-viewing areas of the plurality of cathode regions are adjusted, as a result, the peak forward surge current withstand capability of the semiconductor device can be adjusted only within the linear relationship. There is a problem that it is difficult to adjust the peak forward surge current withstand capability of the semiconductor device.
Therefore, an object of the present invention is to provide an RC-IGBT semiconductor device capable of improving the peak forward surge current withstand capability.

In one embodiment of the present invention, a semiconductor layer having a first main surface on one side and a second main surface on the other side, a gate structure formed on the first main surface, and the first main surface in a plan view. A gate pad that covers the first main surface at a distance from one side in the first direction X and is electrically connected to the gate structure, and a first conductive type formed on the surface layer portion of the second main surface. It is formed on the surface layer portion of the second main surface so as not to overlap the gate pad in the plan view and the collector region of the above, and extends in a strip shape along the first direction X in the plan view, and the first in the plan view. A plurality of second conductive type cathode line regions arranged at intervals in a second direction Y orthogonal to the direction X, and the plurality of cathode line regions are located on the gate pad side in a plan view. Each of the first end portion and the second end portion located on the side opposite to the gate pad is provided, and the plurality of the second end portions are in the first direction in a plan view with respect to the plurality of the cathode line regions. The position of X provides an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) semiconductor device aligned in the second direction Y.

According to this structure, unlike the conventional semiconductor device in which a linear relationship is established between the plan-view area of the cathode region and the withstand voltage of the semiconductor device, the withstand voltage of the RC-IGBT semiconductor device is increased by separating from the linear relationship. be able to.

FIG. 1 is a schematic top view of the semiconductor substrate of the semiconductor device according to the first embodiment of the present invention as viewed from the surface side. FIG. 2 is a schematic partially cutaway perspective view of the region surrounded by the alternate long and short dash line II of FIG. FIG. 3 is a circuit diagram showing an electrical structure of the semiconductor device of FIG. FIG. 4 is a schematic bottom view of the semiconductor substrate of the semiconductor device of FIG. 1 as viewed from the back surface side. FIG. 5 is a schematic bottom view of the semiconductor substrate of the semiconductor device according to the reference example as viewed from the back surface side. FIG. 6 is a graph showing the simulation results of the peak forward surge current of the semiconductor device according to the first embodiment and the peak forward surge current of the semiconductor device according to the reference example. FIG. 7 is a graph showing a simulation result of a collector current when a collector-emitter voltage is applied between a collector electrode and an emitter electrode to operate as an IGBT in the semiconductor device according to the first embodiment. FIG. 8 is a graph showing a simulation result of a forward current when a forward voltage is applied between a collector electrode and an emitter electrode to operate the semiconductor device according to the first embodiment as a freewheeling diode. FIG. 9 is a schematic cross-sectional view of the semiconductor device according to the second embodiment of the present invention. FIG. 10 is a schematic bottom view of the semiconductor substrate as viewed from the back surface side, and is a diagram showing a first modification of the cathode region. FIG. 11 is a schematic bottom view of the semiconductor substrate as viewed from the back surface side, and is a diagram showing a second modification of the cathode region. FIG. 12 is a schematic bottom view of the semiconductor substrate as viewed from the back surface side, and is a diagram showing a third modification example of the cathode region.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First Embodiment>
FIG. 1 is a schematic top view of the semiconductor substrate 2 of the semiconductor device 1 according to the first embodiment of the present invention as viewed from the surface 2a side. FIG. 2 is a schematic partially cutaway perspective view of the region surrounded by the alternate long and short dash line II of FIG. FIG. 3 is a circuit diagram showing an electrical structure of the semiconductor device 1 of FIG.

The semiconductor device 1 according to the present embodiment includes an RC (Reverse Conducting) -IGBT (Insulated Gate Bipolar Transistor) including an IGBT (Insulated Gate Bipolar Transistor) and a free wheeling diode (Free Wheeling Diode). There is. With reference to FIGS. 1 and 2, the semiconductor device 1 includes a semiconductor substrate 2 as an example of the semiconductor layer of the present invention. In the present embodiment, the semiconductor substrate 2 is a silicon FZ substrate formed by the FZ (Floating Zone) method. The semiconductor substrate 2 is formed in a chip shape having a rectangular shape in a plan view, and includes a front surface 2a, a back surface 2b on the opposite side thereof, and a side surface 2c connecting the front surface 2a and the back surface 2b.

The semiconductor substrate 2 is set with an active region 3 in which a part of the IGBT and a part of the freewheeling diode are formed, and an outer region 4 outside the active region 3. In the present embodiment, the active region 3 is set in the inner region of the semiconductor substrate 2 in a rectangular shape in a plan view having four sides parallel to each side surface 2c of the semiconductor substrate 2. The outer region 4 is set in a square ring in a plan view so as to surround the active region 3.

A surface electrode 5 for supplying electric power to the active region 3 is formed on the surface 2a of the semiconductor substrate 2. The surface electrode 5 includes a gate electrode 6 formed along the periphery of the active region 3 in a plan view, and an emitter electrode 7 formed so as to cover the active region 3.
The gate electrode 6 includes a gate finger 8 and a gate pad 9 in this embodiment. The gate finger 8 is arranged in the outer region 4 so as to surround the active region 3, and is formed in a rectangular ring in a plan view extending along each side surface 2C of the semiconductor substrate 2. The gate finger 8 may be formed along the three side surfaces 2C of the semiconductor substrate 2 so as to sandwich the active region 3 from three directions. Further, the gate finger 8 may be formed so as to cross the inside of the active region 3 from each side surface 2C side according to the size of the active region 3.

The gate pad 9 is connected to the gate finger 8 at the central portion in the longitudinal direction of one gate finger 8 extending along one side surface 2C of the semiconductor substrate 2. The gate pad 9 is formed in a rectangular shape in a plan view having four sides parallel to each side surface 2c of the semiconductor substrate 2. The gate pad 9 may be connected to two gate fingers 8 extending in directions orthogonal to each other at one corner of the semiconductor substrate 2. Further, when the gate finger 8 is formed so as to cross the active region 3, the gate pad 9 may be connected to the gate finger 8 formed so as to cross the active region 3.

In the region surrounded by the gate electrode 6, an insulating region 10 extending in a band shape along the inner edge of the gate finger 8 and the inner edge of the gate pad 9 and forming an endless shape (closed ring) in a plan view is formed. There is. The insulating region 10 is a region where the insulating layer 43, which will be described later, is exposed from the gate electrode 6 and the emitter electrode 7 without the electrode material present. The emitter electrode 7 is formed in a region surrounded by the insulating region 10.

With reference to FIG. 2, in the active region 3, a p ^- type channel region 21 is formed on the surface layer portion on the surface 2a side of the semiconductor substrate 2. The active region 3 is defined in the present embodiment by a region surrounded by the periphery of the channel region 21 in a plan view. That is, in the present embodiment, the active region 3 is a region in which the channel region 21 is projected onto the front surface 2a and the back surface 2b of the semiconductor substrate 2.

In the active region 3, the rear surface 2b side of the semiconductor substrate 2 to the channel region 21, n as electrically with the channel region 21 connected ^- -type drift region 22 is formed. In the present embodiment, an n ^- type semiconductor substrate is used as the semiconductor substrate 2, and the drift region 22 is formed by utilizing a part of the semiconductor substrate 2.
^{In the active region 3, a p +} type collector region 23 and an n ⁺ type cathode region 24 are formed on the surface layer portion on the back surface 2b side of the semiconductor substrate 2 so as to be electrically connected to the drift region 22. There is. In the present embodiment, an n-type buffer region 25 is formed so as to extend between the drift region 22 and the collector region 23, and between the drift region 22 and the cathode region 24, and the collector region 23 and the cathode region 23 are formed. 24 is electrically connected to the drift region 22 via the buffer region 25. The collector region 23 and the cathode region 24 are formed so as to be exposed from the back surface 2b of the semiconductor substrate 2.

The cathode region 24 is formed so as to cross the boundary between the collector region 23 and the buffer region 25, and the end portion of the cathode region 24 on the surface 2a side of the semiconductor substrate 2 is located in the buffer region 25. In addition, each configuration of the collector region 23 and the cathode region 24 will be described in detail later.
In the active region 3, a plurality of trench gate structures 31 extending in a plan view band shape are formed on the surface layer portion on the surface 2a side of the semiconductor substrate 2. Each trench gate structure 31 includes an embedded gate electrode 34 embedded in a gate trench 32 formed by digging down a semiconductor substrate 2 with a gate insulating film 33 interposed therebetween. The gate trench 32 penetrates the channel region 21 and has a bottom located within the drift region 22. In this embodiment, the gate insulating film 33 also covers the surface 2a of the semiconductor substrate 2.

^{An n +} type emitter region 35 is formed on the surface layer portion of the channel region 21 on the side of each trench gate structure 31 so as to be exposed from the surface 2a of the semiconductor substrate 2. ^{As a result, on the side of each trench gate structure 31, the n +} type emitter region 35, the p ⁻ type channel region 21 and the n ⁻ type are sequentially formed from the front surface 2a side to the back surface 2b side of the semiconductor substrate 2. A drift region 22 is formed. The channel region 21 is shared by a plurality of trench gate structures 31 adjacent to each other. The embedded gate electrode 34 faces the emitter region 35, the channel region 21, and the drift region 22 with the gate insulating film 33 interposed therebetween in the gate trench 32.

A plurality of contact recesses 41 are formed between the plurality of trench gate structures 31 in the surface layer portion of the channel region 21. Each contact recess 41 is formed in a plan view band shape extending along the same direction as the plurality of trench gate structures 31. Each contact recess 41 is formed by digging down a surface layer portion on the surface 2a side of the semiconductor substrate 2 so that the bottom portion thereof is located in the channel region 21. With respect to the thickness direction of the semiconductor substrate 2, the depth of the contact recess 41 is smaller than the depth of the trench gate structure 31 (gate trench 32).

The above-mentioned emitter region 35 is exposed from the side portion of each contact recess 41. ^{In the present embodiment, the p +} having a p-type impurity concentration higher than the p-type impurity concentration of the channel region 21 in the channel region 21 along the side and bottom of the contact recess 41 from below the emitter region 35. A contact region 42 of the mold is further formed. The emitter region 35 may be exposed over the entire side portion of the contact recess 41, and the contact region 42 may be formed along only the bottom of the contact recess 41.

An insulating layer 43 is formed on the surface 2a of the semiconductor substrate 2 so as to cover the trench gate structure 31. The insulating layer 43 may have a laminated structure in which a plurality of insulating films are laminated, or may have a single-layer structure composed of one insulating film. The insulating layer 43 may include, for example, an oxide film (SiO ₂ ) or a nitride film (SiN). The insulating layer 43 is formed with contact holes 44 that expose the contact recesses 41 formed in the semiconductor substrate 2.

The contact hole 44 extends in a plan view band shape along the same direction as the contact recess 41, and communicates with the contact recess 41 formed on the surface layer portion on the surface 2a side of the semiconductor substrate 2. The inner wall of the contact hole 44 is formed flush with the inner wall of the contact recess 41.
The above-mentioned emitter electrode 7 is formed on the insulating layer 43 via the barrier metal layer 45. The barrier metal layer 45 is a metal layer for suppressing the emitter electrode 7 from diffusing to the outside of the contact hole 44 and the contact recess 41. In the present embodiment, the titanium layer is laminated in this order from the semiconductor substrate 2 side. It has a laminated structure including a titanium nitride layer. In the barrier metal layer 45, the surface on the semiconductor substrate 2 side and the opposite surface are formed along the inner wall of the contact recess 41, the inner wall of the contact hole 44, and the surface of the insulating layer 43 outside the contact hole 44.

The emitter electrode 7 is formed on the barrier metal layer 45 so as to fill the contact recess 41 and the contact hole 44 and cover the entire surface of the insulating layer 43. The emitter electrode 7 is electrically connected to the channel region 21, the emitter region 35, the contact region 42, and the like via the barrier metal layer 45 in the contact recess 41.
The gate electrode 6 is formed on the insulating layer 43 at intervals from the emitter electrode 7 with the above-mentioned insulating region 10 formed of a part of the insulating layer 43 interposed therebetween. The trench gate structure 31 described above is drawn from, for example, the active region 3 to the region directly below the gate finger 8. The gate finger 8 is electrically connected to the trench gate structure 31 via, for example, a contact hole (not shown) formed in the insulating layer 43. A collector electrode 46 as a back surface electrode is formed on the back surface 2b side of the semiconductor substrate 2 so as to be electrically connected to the collector region 23 and the cathode region 24.

With reference to FIG. 3, the semiconductor device 1 according to the present embodiment has a structure in which an IGBT and a freewheeling diode are formed on a common semiconductor substrate 2. The freewheeling diode is formed by a pn junction between the channel region 21 and the drift region 22. The freewheeling diode includes a channel region 21 as an anode region. The freewheeling diode is electrically connected to the emitter electrode 7 via the channel region 21 and electrically connected to the collector electrode 46 via the cathode region 24.

In this way, the semiconductor device 1 according to the present embodiment has a structure in which the anode of the freewheeling diode is electrically connected to the emitter electrode 7 of the IGBT and the cathode of the freewheeling diode is electrically connected to the collector electrode 46 of the IGBT. have.
One of the features of the semiconductor device 1 according to the present embodiment is that the cathode region 24 is formed in a predetermined pattern on the surface layer portion on the back surface 2b side of the semiconductor substrate 2. Hereinafter, a specific configuration of the cathode region 24 will be described with reference to FIG. FIG. 4 is a schematic bottom view of the semiconductor substrate 2 of the semiconductor device 1 of FIG. 1 as viewed from the back surface 2b side. In FIG. 4, the cathode region 24 is shown by cross-hatching for clarity.

With reference to FIG. 4, on the back surface 2b of the semiconductor substrate 2, a collector region 23 and a cathode region 24 are formed in the active region 3. In the present embodiment, the collector region 23 is formed in a plan view shape that substantially matches the plan view shape of the active region 3 (that is, the plan view shape of the channel region 21).
The cathode region 24 has a continuously drawn line-like pattern within the active region 3. In the present embodiment, the cathode region 24 has an n-type impurity concentration higher than the p-type impurity concentration in the collector region 23, and the active region so that the p-type impurities in the collector region 23 are offset by the n-type impurities. It is formed in 3.

In the present embodiment, the active region 3 is set with a first region 50 in which only the collector region 23 is formed and a second region 51 in which both the collector region 23 and the cathode region 24 are formed. The first region 50 is a region where only the IGBT is formed, and the second region 51 is a region where the IGBT and the freewheeling diode are formed.
The first region 50 is set along the peripheral edge portion of the semiconductor substrate 2, more specifically, the central region of one side surface 2C of the semiconductor substrate 2. More specifically, in the present embodiment, the first region 50 is set in the region directly below the gate pad 9 described above, and faces the entire area where the gate pad 9 overlaps the active region 3 in a plan view. doing. The first region 50 surrounds the peripheral edge of the portion where the gate pad 9 overlaps the active region 3 from the outside in a plan view. The first region 50 may be a region partitioned in a rectangular shape in a plan view.

On the other hand, the second region 51 is a planar vision concave region set in the region outside the first region 50 in the active region 3, and is set in the region directly below the emitter electrode 7 described above. By setting the first region 50 and the second region 51 in the active region 3, the cathode region 24 is formed in a region outside the gate pad 9 in a plan view, and is not compatible with the back surface 2b of the semiconductor substrate 2. It is formed in an even pattern (arrangement).

The cathode region 24 includes a line-shaped pattern that is continuously routed in a knot shape in a plan view within the second region 51 of the active region 3. In the following, for convenience of explanation, the + X direction and the −X direction and the + Y direction and the −Y direction shown in FIG. 4 may be used. The + X direction and the −X direction are two directions along one side of the semiconductor substrate 2, and when these are collectively referred to, they are simply referred to as “X direction”. The + Y direction and the −Y direction are two directions along the other side orthogonal to the one side of the semiconductor substrate 2, and when these are collectively referred to, they are simply referred to as “Y direction”. The X direction is also the direction in which the gate pad 9 is pulled out from the gate finger 8 in the present embodiment.

The cathode region 24 includes a plurality of first lines 52 extending along the X direction and formed at intervals along the Y direction, and a plurality of first lines extending along the Y direction and adjacent to each other in the Y direction. A plurality of second lines 53 connecting the lines 52 to each other are included.
The plurality of first lines 52 include a plurality of first lines 52A formed on the + Y direction end side of the active region 3 and a plurality of first lines 52B formed on the −Y direction end side of the active region 3. And a plurality of first lines 52C formed between the first line 52A and the first line 52B.

The plurality of first lines 52A and the plurality of first lines 52B of the first region 50 (gate pad 9) so as to face each other in the Y direction with the first region 50 (gate pad 9) interposed therebetween in a plan view. It is pulled out to the areas on both sides in the Y direction. The X-direction widths of the plurality of first lines 52A and the X-direction widths of the plurality of first lines 52B are set to substantially equal values in the present embodiment.

The plurality of first lines 52C are formed in a region facing the first region 50 (gate pad 9) in the X direction in a plan view. The width in the X direction of the plurality of first lines 52C is set to a value smaller than the width in the X direction of the plurality of first lines 52A and the width in the X direction of the plurality of first lines 52B.
Each of the plurality of first lines 52 has a line length that exceeds the width of the gate pad 9 in the X direction. Further, each of the plurality of first lines 52 has a line width less than the width of the gate pad 9 in the Y direction.

When a cross line that intersects the central portion of the back surface 2b in the X direction and the Y direction is set so as to divide the back surface 2b into four regions in a plan view, a part of the plurality of first lines 52 is at least a part of the four regions. Included in one area. The plurality of first lines 52 are arranged line-symmetrically with respect to the line when a line crossing the gate pad 9 in the X direction is set in a plan view.

The plurality of first lines 52 have an −X direction end (first end) located on the gate pad 9 side in a plan view and a + X direction end (second end) located on the opposite side of the gate pad 9. Each has a part). With respect to the plurality of first lines 52, the positions of the plurality of + X direction end portions (second end portions) in the X direction are aligned in the Y direction in a plan view.
With respect to the plurality of first lines 52, the positions of the plurality of −X direction ends (first end portions) in the X direction are not aligned in the Y direction in a plan view. Specifically, the -X direction ends of the plurality of first lines 52A and the -X direction ends of the plurality of first lines 52B are aligned in the Y direction, but the -X direction ends of the plurality of first lines 52C. The portions are displaced in the + X direction from the −X direction ends of the plurality of first lines 52A and the plurality of first lines 52B, and the plurality of first lines 52A and the plurality of first lines 52B are displaced in the −X direction in the Y direction. Not aligned with the edges.

The second line 53 includes a second line 53A that connects the + X direction ends of two adjacent first lines 52 along the Y direction, and-of two adjacent first lines 52 along the Y direction. A second line 53B that connects the ends in the X direction is included. The second line 53A and the second line 53B are formed alternately along the Y direction. In this way, in the present embodiment, the cathode region 24 is formed in a continuously continuous plane-viewing knotted line-like pattern. Further, the cathode region 24 includes a plurality of first lines 52A, 52B, 52C having different widths in the X direction, whereby the cathode region 24 is formed in an uneven pattern (arrangement) with respect to the active region 3.

The line width of the cathode region 24 defined by the width in the Y direction of the first line 52 and the width in the X direction of the second line 53 is, for example, 1 μm or more and 100 μm or less, more preferably 10 μm or more and 50 μm or less. The cathode region 24 may have a uniform line width or may have a non-uniform line width. For example, the cathode region 24 may have first lines 52A, 52B, 52C having different widths in the Y direction, or may have second lines 53A, 53B having different widths in the X direction.

The ratio _S 1 / _{S A} of the area _{S 1} of the first region 50 to the area _{S A} of the active region 3, for example, 0.03 (3%) 0.3 (30%) or less. Also, in plan view, the ratio _S K / _{S A} of the area _{S K} of the cathode region 24 to the area _{S A} of the active region 3 (hereinafter, referred to. Simply "area ratio of the cathode region 24 _S K / _{S A")} is the ratio _S C / _{S a} of the area _{S C} of the collector region 23 to the area _{S a} of the active region 3 (hereinafter, simply referred to as "area ratio of the collector region 23 _S C / _{S a".)} is set to a value smaller than There is. The area ratio _S K / _{S A} of the cathode region 24, for example, 0.1 (10%) or less, more specifically, less than or equal 0.01 (1%) or more 0.07 (7%).

In order to compare with the electrical characteristics of the semiconductor device 1 according to the present embodiment, the semiconductor device 101 according to the reference example shown in FIG. 5 was prepared. FIG. 5 is a schematic bottom view of the semiconductor layer of the semiconductor device 101 according to the reference example as viewed from the back surface side.
In the semiconductor device 101 according to the reference example, a plurality of cathode regions 24 having a circular shape in a plan view are formed in the active region 3. The plurality of cathode regions 24 are evenly formed in a matrix-like regular arrangement at intervals along the X and Y directions. In the semiconductor device 101 according to the reference example, the cathode region 24 is also formed in a region directly below the gate pad 9. In the semiconductor device 101 according to the reference example, other configurations are substantially the same as the respective configurations of the semiconductor device 1 according to the present embodiment, and thus the same reference numerals are given and the description thereof will be omitted.

FIG. 6 is a graph showing simulation results _{of the peak forward surge current I FSM} of the semiconductor device 1 according to the present embodiment and the peak forward surge current I _{FSM of the} semiconductor device 101 according to the reference example.
6, the horizontal axis, the area ratio of the cathode region 24 shows the _S K / _{S A,} the vertical axis represents the peak forward surge current _{I FSM.} The peak forward surge current I _FSM is a peak value of a commercial sinusoidal half-wave current having one or more cycles allowed within a range in which the semiconductor device is not destroyed. Thus, the higher the value of the peak forward surge current _{(non-repetitive)} I _FSM, tolerance for peak forward surge current _{(non-repetitive)} I _FSM semiconductor device (hereinafter, simply referred to as "peak forward surge current rating".) Said to have excellent.

In Figure 6, the area ratio _S K / _{S A} cathode region 24 of the semiconductor device 1 according to this embodiment, the simulation results of the peak forward surge current _{(non-repetitive) I FSM} if it is 0.037 (3.7%) of It is shown in plot P1. Further, in FIG. 6, the area ratio _S K _{/ S} A cathode region 24 of the semiconductor device 101 according to the reference example, 0.012 (1.2%), 0.019 (1.9%), 0.023 _{Simulation results of the peak forward surge current I FSM} at (2.4%) and 0.032 (3.2%) are shown in plots P2 to P5. In FIG. 6, plots P2 to P5 are connected by an approximate straight line L.

Referring to FIG. 6, in the semiconductor device 1 according to the reference example, reducing the area ratio S _{K /} S _A of the cathode region 24 by reducing the plan view area of the plurality of cathode regions 24, peak forward surge current _{(non-repetitive)} I _FSM Is declining. In the semiconductor device 101 according to the reference example, by increasing the area ratio S _{K /} S _A cathode region 24 to increase the plan view area of the plurality of cathode regions 24, peak forward surge current _{(non-repetitive)} I _FSM is improved .. Therefore, it can be said that the semiconductor device 101 according to the reference example, the approximate linear relationship between the viewed area and peak forward surge current _{(non-repetitive)} I _FSM plurality of cathode regions 24 is established.

However, in the semiconductor device 101 according to the reference example, also the area ratio of the cathode region 24 _S K / _{S A} is in either case, peak forward surge current _{(non-repetitive) I FSM} was below the relatively low value 300A .. For approximate line L, in the semiconductor device 101 according to the reference example, the closer the area ratio S _{K /} S _A cathode region 24 to "1", also considered possible to achieve proper peak forward surge current _{(non-repetitive)} I _FSM Be done.

However, in practice, as the area ratio _S K / _{S A} cathode region 24 approaches to "1", the area ratio _S C / _{S A} of the collector region 23 approaches to "0", the function of IGBT is lost To go. Therefore, the linear in the semiconductor device 101 according to the reference example, even when adjusting the area ratio S _{K /} S _A of the cathode region 24 by the adjustment of the plan view area of the plurality of cathode regions 24, indicated by the approximate straight line L as a result It can be said that the peak forward surge current I _FSM can be adjusted only in such a relationship, and it is difficult to obtain a relatively high peak forward surge current I _FSM.

In the semiconductor device 101 according to the reference example, a plurality of cathode regions 24 having a circular shape in a plan view are formed in the active region 3, but this problem is caused by a plurality of cathode regions 24 having a polygonal shape in a plan view such as a rectangular shape in a plan view. The same occurs when is formed in the active region 3 in a regular arrangement.
On the other hand, in the semiconductor device 1 according to the present embodiment having the cathode region 24 formed by a continuous line-shaped pattern, the peak forward surge current _IFSM is 1000 A or more, and the semiconductor device according to the reference example. _{Unlike 101, the peak forward surge current IFSM} deviates from the approximate straight line L and is relatively high. Therefore, it was found that by forming the cathode region 24 in a continuous line-like pattern, a relatively high peak forward surge current _IFSM can be realized by separating from the linear relationship indicated by the approximate straight line L.

7, in the semiconductor device 1 according to this embodiment, the collector between the collector electrode 46 and emitter electrode 7 - shows when operated as an IGBT is applied to emitter voltage V _CE, the simulation result of the collector current I _C It is a graph. 7, the horizontal axis, the collector - shows the emitter voltage V _CE, the vertical axis represents the collector current I _C.
Generally, in a semiconductor device comprising an IGBT and freewheeling diode on a common semiconductor substrate 2, a collector of a relatively small value (e.g. 2.5V below the range of 0V) - the emitter voltage V _CE is applied, snapback phenomenon Is known to occur.

As shown in FIG. 7, in the semiconductor device 1 according to the present embodiment, the occurrence of the snapback phenomenon is suppressed even when _{a collector-emitter voltage VCE having a relatively small value is given.} It is considered that this is because the first region 50 having a relatively large plan view area where only the collector region 23 is formed is formed in the active region 3. Therefore, even when the cathode region 24 is formed in a continuous line-like pattern as in the semiconductor device 1 according to the present embodiment, the IGBT can be operated satisfactorily.

8, in the semiconductor device 1 according to this embodiment, when operating as a free wheel diode by applying a forward voltage V _F across the collector electrode 46 and emitter electrode 7, the simulation results of the forward current I _F It is a graph which shows. 8, the horizontal axis represents the forward voltage V _F, the vertical axis represents the forward current I _F.
With reference to FIG. 8, even when the cathode region 24 is formed in a continuous line-like pattern as in the semiconductor device 1 according to the present embodiment, it can be operated satisfactorily as a freewheeling diode.

As described above, the semiconductor device 1 according to the present embodiment includes a line-shaped pattern in which the cathode region 24 is continuously routed. Therefore, unlike the semiconductor device 101 according to the reference example in which a linear relationship is established between the plan-view area of the cathode region 24 and the peak forward surge current _{IFSM, a relatively high value is separated from the linear relationship.} The peak forward surge current I _FSM can be obtained.

_{Moreover, the peak forward surge current IFSM} of the semiconductor device 1 can be easily adjusted by adjusting the region around the cathode region 24 in the active region 3 (second region 51) on the back surface 2b side of the semiconductor substrate 2. You can also. Therefore, in the configuration including the IGBT and the freewheeling diode, it is possible to provide the semiconductor device 1 having a structure capable of increasing the degree of freedom in design and at the same time improving the peak forward surge current withstand capability.

<Second Embodiment>
FIG. 9 is a schematic cross-sectional view of the semiconductor device 61 according to the second embodiment of the present invention.
With reference to FIG. 9, the semiconductor device 61 according to the present embodiment is different from the semiconductor device 1 according to the first embodiment in that it has a planar gate structure 62 instead of the trench gate structure 31. There is. In FIG. 9, the same reference numerals are given to the same configurations as those described in the first embodiment described above, and the description thereof will be omitted.

The semiconductor device 61 according to this embodiment includes the above-mentioned semiconductor substrate 2. The above-mentioned channel regions 21 are formed at intervals on the surface layer portion on the surface 2a side of the semiconductor substrate 2. The above-mentioned emitter region 35 is formed on the surface layer portion of each channel region 21 at intervals inward from the peripheral edge of the channel region 21.
In the present embodiment, the above-mentioned drift is provided so as to be electrically connected to the channel region 21 in the region between the channel regions 21 adjacent to each other and the region on the back surface 2b side of the semiconductor substrate 2 with respect to each channel region 21. Region 22 is formed. The collector region 23 and the cathode region 24 are formed on the surface layer portion on the back surface 2b side of the semiconductor substrate 2 so as to be electrically connected to the drift region 22 via the buffer region 25. The collector region 23 and the cathode region 24 have the same configuration as that of the first embodiment described above.

The planar gate structure 62 includes a gate electrode 64 that faces at least the channel region 21 with the gate insulating film 63 formed on the surface 2a of the semiconductor substrate 2 interposed therebetween. More specifically, the gate electrode 64 faces the emitter region 35, the channel region 21, and the drift region 22 with the gate insulating film 63 interposed therebetween. In the surface layer portion of the channel region 21, the above-mentioned contact region 42 is formed on the side opposite to the gate electrode 64 with respect to the emitter region 35.

Then, the above-mentioned insulating layer 43 is formed so as to cover the planar gate structure 62. The insulating layer 43 is formed with contact holes 65 that expose the channel region 21 and the emitter region 35. The above-mentioned emitter electrode 7 enters the contact hole 65 from above the insulating layer 43 via the above-mentioned barrier metal layer 45, and electrically with the channel region 21, the emitter region 35, and the contact region 42 in the contact hole 65. It is connected. The collector electrode 46 as a back surface electrode is formed on the back surface 2b side of the semiconductor substrate 2 so as to be electrically connected to the collector region 23 and the cathode region 24.

In the present embodiment, the above-mentioned active region 3 is defined by the region in which a plurality of unit cells 66 shown in FIG. 9 are formed. In the present embodiment, the unit cell 66 is a region in which two channel regions 21 are formed for one planar gate structure 62, as shown in FIG.
As described above, the semiconductor device 61 according to the present embodiment can also exert the same effect as that described in the above-described first embodiment.

Although the embodiments of the present invention have been described above, the present invention can also be implemented in other embodiments.
For example, in the above-mentioned first embodiment, an example in which the cathode region 24 includes a line-shaped pattern formed in a plane view knot shape has been described. However, the cathode region 24 may be formed in a pattern as shown in FIGS. 10 to 12 instead.

FIG. 10 is a schematic bottom view of the semiconductor substrate 2 viewed from the back surface 2b side, and is a diagram showing a first modification of the cathode region 24. In FIG. 10, the cathode region 24 is shown by cross-hatching for clarity. In FIG. 10, the same reference numerals are given to the same configurations as those described in the first embodiment described above, and the description thereof will be omitted.
With reference to FIG. 10, the cathode region 24 according to the first modification extends in the X direction and is formed at intervals along the Y direction, as in the first embodiment described above. It includes one line 52 and a plurality of second lines 53 extending along the Y direction and connecting a plurality of first lines 52 adjacent to each other in the Y direction.

In the cathode region 24 according to the first modification, the widths in the X direction of the plurality of first lines 52A and 52B described above are all set to substantially the same values as the widths in the X direction of the first line 52C. Therefore, in the cathode region 24 according to the first modification, in a plan view, the plurality of first lines 52A and the plurality of first lines 52B face each other in the Y direction with the first region 50 (gate pad 9) interposed therebetween. It is formed so as to be unevenly distributed on the + X direction side of the active region 3 without any problem. That is, the above-mentioned first region 50 is formed in a rectangular shape in a plan view extending along the Y direction at the end portion of the active region 3 on the −X direction side.

In other words, the back surface 2b is located in the facing region facing the gate pad 9, the first region located on the + Y direction side with respect to the facing region, and the back surface 2b on the −Y direction side with respect to the facing region. A second region facing the first region with the facing region interposed therebetween is included. The plurality of first lines 52 are formed on the surface layer portion of the second main surface so as not to be located in the opposite region, the first region, and the second region of the back surface 2b in a plan view. In such a structure, the plurality of first lines 52 are at least one first line 52A facing the first region in the X direction in the plan view, and at least one facing the second region in the X direction in the plan view. Includes one first line 52B.

When a cross line that intersects the central portion of the back surface 2b in the X direction and the Y direction is set so as to divide the back surface 2b into four regions in a plan view, a part of the plurality of first lines 52 is at least a part of the four regions. Included in one area. The plurality of first lines 52 are arranged line-symmetrically with respect to the line when a line crossing the gate pad 9 in the X direction is set in a plan view.

The plurality of first lines 52 have an −X direction end (first end) located on the gate pad 9 side in a plan view and a + X direction end (second end) located on the opposite side of the gate pad 9. Each has a part). With respect to the plurality of first lines 52, the positions of the plurality of + X direction end portions (second end portions) in the X direction are aligned in the Y direction in a plan view. Further, with respect to the plurality of first lines 52, the positions of the plurality of -X direction end portions (first end portions) in the X direction are aligned in the Y direction in a plan view.

As described above, the cathode region 24 according to the first modification is unevenly distributed on the + X direction side of the active region 3, and the cathode region 24 is formed in an uneven pattern (arrangement) with respect to the active region 3. There is. Even with such a configuration, the same effect as that described in the above-described first embodiment can be obtained. Also in the second embodiment described above, the cathode region 24 according to the first modification may be applied.

FIG. 11 is a schematic bottom view of the semiconductor substrate 2 viewed from the back surface 2b side, and is a diagram showing a second modification of the cathode region 24. In FIG. 11, the cathode region 24 is shown by cross-hatching for clarity. In FIG. 11, the same reference numerals are given to the same configurations as those described in the first embodiment described above, and the description thereof will be omitted.
With reference to FIG. 11, the cathode region 24 according to the second modification extends along the X direction and is formed at intervals along the Y direction, as in the first embodiment described above. It includes one line 52 and a plurality of second lines 53 extending along the Y direction and connecting a plurality of first lines 52 adjacent to each other in the Y direction. In the cathode region 24 according to the second modification, the second line 53 connects the + X direction ends of the two adjacent first lines 52 along the Y direction.

As described above, the cathode region 24 according to the second modification is configured to include a line-shaped pattern formed in a comb-teeth shape in a plan view, and the cathode region 24 is uneven with respect to the active region 3. It is formed by a pattern (arrangement). Even with such a configuration, the same effect as that described in the above-described first embodiment can be obtained. Also in the second embodiment described above, the cathode region 24 according to the second modification may be applied.

FIG. 12 is a schematic bottom view of the semiconductor substrate 2 viewed from the back surface 2b side, and is a diagram showing a third modification of the cathode region 24. In FIG. 12, the cathode region 24 is shown by cross-hatching for clarity. In FIG. 12, the same reference numerals are given to the same configurations as those described in the first embodiment described above, and the description thereof will be omitted.
In the third modification, the first region 50 described above is set in a square shape in a plan view at the center of the active region 3, and the second region 51 described above is a square ring in a plan view so as to surround the first region 50. Is set to. That is, in the third modification, the gate pad 9 described above is arranged at the center of the semiconductor substrate 2 in a plan view.

Similar to the first embodiment described above, the cathode region 24 according to the third modification has a plurality of first lines 52 extending along the X direction and formed at intervals along the Y direction, and the Y direction. Includes a plurality of second lines 53 extending along the line and connecting the plurality of first lines 52 adjacent to each other in the Y direction.
The cathode region 24 according to the third modification includes a line-shaped pattern formed by the first line 52 and the second line 53 in a spiral shape of a square in a plan view parallel to the side surface 2c of the semiconductor substrate 2. Therefore, the cathode region 24 is formed so as to be unevenly distributed on the peripheral edge side of the active region 3, whereby the cathode region 24 is formed in an uneven pattern (arrangement) with respect to the active region 3. There is.

Even with such a configuration, the same effect as that described in the above-described first embodiment can be obtained. Also in the second embodiment described above, the cathode region 24 according to the third modification may be applied. The cathode region 24 may have a circular spiral shape in a plan view, or may have a polygonal spiral shape in a plan view other than a quadrangle, such as an octagonal spiral shape in a plan view.
Further, in each of the above-described embodiments, the cathode region 24 may have a configuration including a plurality of line-shaped patterns having different plan-view shapes or the same plan-view shapes. For example, the cathode region 24 is composed of a line-shaped pattern formed in a knotted shape in a plan view, a line-shaped pattern formed in a comb-shaped shape in a plan view, and a line-shaped pattern formed in a spiral shape in a plan view. It may include at least one selected pattern.

Further, in each of the above-described embodiments, an example in which the semiconductor substrate 2 manufactured by the FZ method is adopted as an example of the semiconductor layer has been described. However, instead of the semiconductor substrate 2, the semiconductor layer may include, for example, a p ^{- type semiconductor substrate made of silicon and an n-} type epitaxial layer formed by epitaxially growing the silicon of the semiconductor substrate. Good. In this case, the p ^- type semiconductor substrate has a configuration corresponding to the collector region 23, and the epitaxial layer has a configuration corresponding to the drift region 22. In this case, the cathode region 24 is formed by injecting an n-type impurity into the semiconductor substrate (collector region 23). From this technical idea, it is understood that the collector region 23 may be formed over the entire back surface 2b.

Further, in each of the above-described embodiments, a configuration in which the conductive type of each semiconductor portion is inverted may be adopted. That is, the p-type portion may be n-type and the n-type portion may be p-type.
Hereinafter, examples of features extracted from this specification and drawings will be shown. Hereinafter, in a configuration including a collector region and a cathode region, a semiconductor device capable of increasing the degree of freedom in design and at the same time improving the peak forward surge current withstand capability will be provided.

[A1] A semiconductor layer having a first main surface and a second main surface on the opposite side thereof, a first conductive type channel region formed on the surface layer portion of the semiconductor layer on the first main surface side, and the channel. A second conductive type emitter region formed on the surface layer portion of the region and a second main surface side of the semiconductor layer with respect to the channel region so as to be electrically connected to the channel region. The two conductive type drift regions and the first conductive type collector region and the second conductive type collector region formed on the surface layer portion on the second main surface side of the semiconductor layer so as to be electrically connected to the drift region. A semiconductor device comprising a cathode region and at least a gate electrode facing the channel region with an insulating film interposed therebetween, wherein the cathode region includes a continuously drawn line-shaped pattern.

This semiconductor device includes a line-like pattern in which the cathode region is continuously routed. As a result, unlike the conventional semiconductor device in which a linear relationship is established between the plan-view area of the cathode region and the withstand voltage of the semiconductor device, the withstand voltage of the semiconductor device can be increased by separating from the linear relationship. Moreover, the withstand voltage of the semiconductor device can be easily adjusted by adjusting the region around which the cathode region is routed on the second main surface side of the semiconductor layer. Therefore, it is possible to provide a semiconductor device having a structure capable of increasing the degree of freedom in design and at the same time improving the withstand voltage.

[A2] The semiconductor device according to A1, wherein the cathode region is formed in an uneven pattern with respect to the second main surface of the semiconductor layer.
[A3] A first region in which only the collector region is formed and a second region in which the collector region and the cathode region are formed are set on the second main surface of the semiconductor layer. The semiconductor device according to A1 or A2, wherein the first region is set on the peripheral edge of the second main surface of the semiconductor layer in a plan view.

[A4] A first region in which only the collector region is formed and a second region in which the collector region and the cathode region are formed are set on the second main surface of the semiconductor layer. The semiconductor device according to A1 or A2, wherein the first region is set in the central portion of the second main surface of the semiconductor layer in a plan view.
[A5] A gate pad arranged on the first main surface of the semiconductor layer is further included so as to be electrically connected to the gate electrode, and the first region is set directly below the gate pad. The semiconductor device according to A3 or A4.

[A6] Further includes a gate pad arranged on the first main surface of the semiconductor layer so as to be electrically connected to the gate electrode, and the cathode region is formed with the gate pad in a plan view. The semiconductor device according to A1 or A2, which is formed in a region outside the region.
[A7] The semiconductor device according to any one of A1 to A6, wherein the cathode region includes the line-shaped pattern formed in a curved shape in a plan view.

[A8] The semiconductor device according to any one of A1 to A6, wherein the cathode region includes the line-shaped pattern formed in a comb-teeth shape in a plan view.
[A9] The semiconductor device according to any one of A1 to A6, wherein the cathode region includes the line-shaped pattern formed in a spiral shape in a plan view.
[A10] The line-like pattern of the cathode region includes A1 to A9 including a first line extending along the first direction and a second line extending along a second direction intersecting the first direction. The semiconductor device according to any one of the above.

[A11] A plurality of the first lines are formed at intervals along the second direction, and the second line connects the plurality of first lines adjacent to each other in the second direction. The semiconductor device according to A10, which is formed in plurality.
[A12] in the semiconductor layer is the active region is set, the collector region and the cathode region, the are formed in the active region, in plan view, the cathode to an area S _A of the active region the ratio _S K / _{S a} of the area _{S K} region, the smaller than the ratio _S C / _{S a} of the area _{S C} of the collector region to the area _{S a} of the active region, according to any one of A1~A11 Semiconductor equipment.

[A13] The ratio _S K / _{S A} of the area _{S K} of the cathode region to an area _{S A} of the active region is 0.1 or less, the semiconductor device according to A12.
[A14] Described in any one of A1 to A13, further including a collector electrode arranged on the second main surface side of the semiconductor layer so as to be electrically connected to the collector region and the cathode region. Semiconductor device.

In addition, various design changes can be made within the scope of the matters described in the claims.

1 Semiconductor device 2 Semiconductor substrate 2a Front surface of semiconductor substrate 2b Back surface of semiconductor substrate 3 Active region 9 Gate pad 21 Channel region 22 Drift region 23 Collector region 24 Cathode region 33 Gate insulating film 34 Gate electrode 35 Emitter region 46 Collector electrode 50 1st region 51 area of the area _{S K} cathode region of the second region 52 area _{S C} collector region of the first line 53 second line 61 semiconductor device 63 gate insulating film 64 gate electrode _{S a} active region

Claims (20)

A semiconductor layer having a first main surface on one side and a second main surface on the other side,
The gate structure formed on the first main surface and
In a plan view, a gate pad that covers the first main surface at a distance from one side of the first main surface in the first direction X and is electrically connected to the gate structure.
The first conductive type collector region formed on the surface layer of the second main surface, and
It is formed on the surface layer of the second main surface so as not to overlap the gate pad in a plan view, extends in a strip shape along the first direction X in a plan view, and is orthogonal to the first direction X in a plan view. Includes a plurality of second conductive cathode line regions, spaced apart from each other in the second direction Y.
The plurality of cathode line regions have a first end portion located on the gate pad side and a second end portion located on the side opposite to the gate pad in a plan view, respectively.
With respect to the plurality of cathode line regions, the positions of the plurality of second end portions in the first direction X are aligned in the second direction Y in a plan view, and the RC-IGBT (Reverse Conducting --Insulated Gate Bipolar Transistor) ) Semiconductor device. The RC-IGBT semiconductor device according to claim 1, wherein the gate pad is arranged on the peripheral edge of the first main surface in a plan view. The plurality of cathode line regions are at least one cathode line region that does not face the gate pad in the first direction X in a plan view, and at least one that does not face the gate pad in the second direction Y in a plan view. The RC-IGBT semiconductor device according to claim 1 or 2, which includes the two cathode line regions. The plurality of cathode line regions according to any one of claims 1 to 3, wherein the plurality of cathode line regions include at least one cathode line region that does not face the gate pad in the first direction X and the second direction Y in a plan view. The RC-IGBT semiconductor device described. The RC-IGBT semiconductor device according to any one of claims 1 to 4, wherein the gate pad is arranged along an intermediate portion of the one side of the first main surface in a plan view. In a plan view, the second main surface has a region facing the gate pad, a first region located on one side of the second direction Y with respect to the facing region, and the facing region. It is located on the other side of the second direction Y and includes a second region facing the first region with the facing region in between.
The plurality of cathode line regions are formed on the surface layer portion of the second main surface so as not to be located in the facing region, the first region, and the second region of the second main surface in a plan view. The RC-IGBT semiconductor device according to any one of claims 1 to 5. The plurality of cathode line regions face at least one cathode line region facing the first region in the first direction X in a plan view, and the second region facing the first direction X in a plan view. The RC-IGBT semiconductor device according to claim 6, wherein the RC-IGBT semiconductor device includes at least one cathode line region. The aspect of any one of claims 1 to 7, wherein the positions of the plurality of first end portions in the first direction X are aligned in the second direction Y with respect to the plurality of cathode line regions in a plan view. The RC-IGBT semiconductor device described. The RC-IGBT semiconductor device according to any one of claims 1 to 8, wherein each of the plurality of cathode line regions has a line length exceeding the width of the gate pad with respect to the first direction X. .. The RC-IGBT semiconductor device according to any one of claims 1 to 9, wherein the plurality of cathode line regions each have a line width smaller than the width of the gate pad in the second direction Y. When a cross line intersecting the first direction X and the second direction Y is set in the central portion of the second main surface so as to divide the second main surface into four regions in a plan view, a plurality of the above The RC-IGBT semiconductor device according to any one of claims 1 to 10, wherein a part of the cathode line region is included in at least one region of the four regions. One of claims 1 to 11, wherein the plurality of cathode line regions are arranged line-symmetrically with respect to the line when a line crossing the gate pad in the first direction X is set in a plan view. The RC-IGBT semiconductor device according to the section. The collector region is formed over the entire surface layer portion of the second main surface.
The RC-IGBT semiconductor device according to any one of claims 1 to 12, wherein the plurality of cathode line regions are formed so as to replace the first conductive type of the collector region with a second conductive type. The RC-IGBT semiconductor device according to any one of claims 1 to 13, wherein the plurality of gate structures are arranged in a striped pattern. It further comprises a gate finger that is electrically connected to the gate pad, is selectively routed over the first main surface, and includes a linear portion that extends in the first direction X in plan view.
The RC-IGBT semiconductor device according to any one of claims 1 to 14, wherein the plurality of cathode line regions extend parallel to the straight line portion of the gate finger in a plan view. The gate structure is composed of a trench formed on the first main surface, a gate insulating film covering the wall surface of the trench, and a trench gate structure including a gate electrode embedded in the trench with the gate insulating film interposed therebetween. The RC-IGBT semiconductor device according to any one of claims 1 to 15. A first conductive type channel region formed on the surface layer portion of the first main surface so as to be exposed from the trench, and
A second conductive type emitter region formed on the surface layer of the channel region so as to be exposed from the trench,
It further comprises an emitter pad that covers the first main surface at a distance from the gate pad and is electrically connected to the emitter region.
The RC-IGBT semiconductor device according to claim 16, wherein the plurality of cathode line regions are formed on a surface layer portion of the second main surface so as to overlap the emitter pad in a plan view. A contact recess formed on the first main surface at a distance from the gate electrode so as to expose the emitter region,
The RC-IGBT semiconductor device according to claim 17, further comprising a first conductive type contact region formed in a region along the contact recess in the channel region and having a higher impurity concentration than the channel region. Further including an insulating layer covering the first main surface,
The RC-IGBT semiconductor device according to claim 17 or 18, wherein the gate pad and the emitter pad are arranged on the insulating layer. The RC-IGBT semiconductor device according to any one of claims 1 to 19, further comprising a collector electrode covering the second main surface and electrically connected to the collector region and the plurality of cathode line regions. ..

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