JP2021082839A - Semiconductor switching element and method of manufacturing the same - Google Patents

Abstract

To provide a technology capable of suppressing reduction in withstanding voltage.SOLUTION: A semiconductor switching element comprises a first gate electrode and a second gate electrode. The first gate electrode reaches a semiconductor layer from an upper surface of an emitter region, and is arranged in a first trench crossing the emitter region, a base region and a charge storage layer via a first gate insulating film. The second gate electrode reaches the semiconductor layer from an upper surface of the emitter region and a conductive region, and is arranged in a second trench adjacent to the emitter region, the base region, the charge storage layer and the conductive region via a second gate insulating film. A depth of the second trench is shallower than that of the first trench, and a width of the second trench is narrower than that of the first trench.SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor switching element and a method for manufacturing the same.

In recent years, from the viewpoint of energy saving, inverter circuits have come to be widely used for controlling home appliances and industrial power devices. In an inverter circuit, power is controlled by a power semiconductor device including a semiconductor switching element that repeatedly turns on and off a voltage or current. When the rated voltage is 300 V or more, an insulated gate bipolar transistor (hereinafter abbreviated as "IGBT") is mainly used as a semiconductor switching element because of its characteristics.

By the way, in the IGBT, in the configuration in which the emitter region and the trench type gate electrode are uniformly provided, the element may be short-circuited due to an abnormal operation or the like, and a huge current may flow, which may adversely affect the element. Therefore, for example, in the configurations disclosed in Patent Documents 1 and 2, the emitter region and the trench-type gate electrode are partially thinned out so that the current can be suppressed even if the element is short-circuited.

Japanese Unexamined Patent Publication No. 2011-204803 Japanese Unexamined Patent Publication No. 2014-063961

However, as described above, in the configuration in which the trench-type gate electrode is not provided in the place where there is no emitter region and the charge storage layer capable of reducing the on-resistance is totally added, the element is blocked. There is a problem that the charge storage layer is not depleted and the withstand voltage is lowered when the voltage is applied.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of suppressing a decrease in withstand voltage.

The semiconductor switching element according to the present invention is a semiconductor layer having a first conductive type, and charge storage arranged on each of two first surfaces provided apart from each other on the upper surface of the semiconductor layer. A base region having a second conductive type, which is arranged on the charge storage layer on the layer and each of the two first surfaces, and arranged on the base region on each of the two first surfaces. An emitter region having a first conductive mold and a conductive region having a second conductive mold arranged on a second surface sandwiched between the two first surfaces of the upper surface of the semiconductor layer. In each of the two first surfaces, a first trench that penetrates the first surface from the upper surface of the emitter region, reaches the semiconductor layer, and intersects the emitter region, the base region, and the charge storage layer. In the first gate electrode disposed inside via the first gate insulating film, and in each of the two first surfaces, the first surface and the second surface are formed from the upper surfaces of the emitter region and the conductive region. It penetrates the upper surface of the semiconductor layer between the semiconductor layers and reaches the semiconductor layer, and is interposed through a second gate insulating film in a second trench adjacent to the emitter region, the base region, the charge storage layer, and the conductive region. A second gate electrode disposed on the conductive region and an emitter electrode disposed on the conductive region and in contact with the conductive region are provided, and the depth of each of the second trenches is shallower than the depth of each of the first trenches. Moreover, the width of each of the second trenches is narrower than the width of each of the first trenches.

According to the present invention, since the depth of the second trench is shallower than the depth of the first trench and the width of the second trench is narrower than the width of the first trench, it is possible to suppress a decrease in withstand voltage.

It is a top view which shows the structure of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing in the AA' line which shows the structure of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing in the BB'line which shows the structure of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 1. FIG. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 1. FIG. FIG. 5 is a cross-sectional view taken along the line AA'showing the configuration of the semiconductor switching element according to the modified example of the first embodiment. FIG. 5 is a cross-sectional view taken along the line AA'showing the configuration of the semiconductor switching element according to the modified example of the first embodiment. FIG. 5 is a cross-sectional view taken along the line AA'showing the configuration of the semiconductor switching element according to the second embodiment. It is sectional drawing in the BB'line which shows the structure of the semiconductor switching element which concerns on Embodiment 2. FIG. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 2. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 2. It is sectional drawing which shows the manufacturing method of the semiconductor switching element which concerns on Embodiment 2. It is sectional drawing which shows the structure of the 1st related switching element. It is sectional drawing which shows the structure of the 2nd related switching element.

Hereinafter, embodiments will be described with reference to the attached drawings. It should be noted that the drawings are shown schematically, and the interrelationship between the sizes and positions of the components shown in the different drawings is not always accurately described and can be changed as appropriate.

<1st and 2nd related switching elements>
First, before explaining the semiconductor switching element according to the first embodiment of the present invention, the first and second semiconductor switching elements (hereinafter, referred to as "first and second related switching elements") related thereto will be described. To do.

FIG. 22 is a cross-sectional view showing the configuration of the first related switching element. The first related switching element is a charge storage type insulated gate bipolar transistor. Hereinafter, the first conductive type will be described as being N type, and the second conductive type will be described as being P type, but the first conductive type may be P type and the second conductive type may be N type. The N type includes N ⁻ type and N ⁺ type, and the P type includes P ⁻ type and P ⁺ type.

The first related switching element includes ^{a semiconductor layer 1 having an N −} type, a base region 2a having a P ^{type, an emitter region 3 having an N +} type, a charge storage layer 4, a first trench 5a, and a first. A gate electrode 6a, a first gate oxide film 7a which is a first gate insulating film, an insulating film 8, an emitter electrode 9, a buffer region 10 having an N type, a collector region 11 having a P type, and a collector electrode. 12 and a high concentration region 13 having ^{a P + type.}

The charge storage layer 4 is arranged on the cell region on the upper surface of the semiconductor layer 1. The charge storage layer 4 is, for example, an N-type impurity layer having a higher impurity concentration than the semiconductor layer 1 and is a layer for reducing on-resistance.

A base region 2a formed by diffusing P-type impurities is disposed on the charge storage layer 4. An emitter region 3 formed by selectively diffusing a high-concentration N-type impurity is disposed on the base region 2a. Further, on the base region 2a, a high-concentration region 13 is arranged adjacent to the emitter region 3 and formed by selectively diffusing high-concentration P-type impurities.

The first trench 5a reaching the semiconductor layer 1 from the upper surface of the emitter region 3 is provided so as to intersect the emitter region 3, the base region 2a, and the charge storage layer 4. Here, a plurality of first trenches 5a are evenly provided in the horizontal direction, and each first trench 5a is provided so as to be orthogonal to the emitter region 3.

The first gate electrode 6a is arranged in the first trench 5a via the first gate oxide film 7a. Here, the first gate electrode 6a is embedded in the first trench 5a. Of the base region 2a interposed between the emitter region 3 and the semiconductor layer 1, the peripheral edge portion of the first gate electrode 6a functions as a channel region.

The insulating film 8 covers the upper surface of the first gate electrode 6a and the upper portion of the peripheral portion of the first gate electrode 6a. The emitter electrode 9 is arranged so as to cover the portion of the high-concentration region 13 exposed from the insulating film 8 and the insulating film 8.

A buffer region 10 formed of N-type impurities is disposed on the back surface of the semiconductor layer 1. A collector region 11 formed of P-type impurities is disposed on the lower surface of the buffer region 10. Further, the collector electrode 12 is arranged on the entire lower surface of the collector region 11.

Next, the on-operation of the first related switching element will be described with reference to FIG. _{With a predetermined positive collector voltage VCE} applied between the emitter electrode 9 and the collector electrode 12, a _{predetermined positive gate voltage VGE} is applied between the emitter electrode 9 and the first gate electrode 6a. Suppose the gate is turned on. At this time, the channel region of the base region 2a is inverted from P-type to N-type to form a channel, and electrons are injected from the emitter electrode 9 into the semiconductor layer 1 through this channel. The injected electrons put a forward bias state between the collector region 11 and the semiconductor layer 1, and holes are injected from the collector region 11 into the semiconductor layer 1. As a result, the resistance of the semiconductor layer 1 is significantly reduced, and the on-resistance of the first related switching element is significantly reduced, so that the current capacity is increased. Further, since the holes supplied from the collector region 11 are stored directly under the charge storage layer 4 by the charge storage layer 4, the effect of further lowering the on-resistance of the first related switching element can be obtained.

However, as shown in FIG. 22, in the configuration in which the emitter region 3 is arranged in all the first trenches 5a, the element may be short-circuited due to an abnormal operation or the like, and a huge current may flow, which may adversely affect the element.

FIG. 23 is a cross-sectional view showing a configuration of a second related switching element for solving this problem. The second related switching element has a structure in which some emitter regions 3 of the first related switching element are thinned out. By partially thinning the emitter region 3 within a range in which the on-voltage does not rise as much as possible, the current flowing can be suppressed even when the element is short-circuited.

However, in such a configuration, the first gate electrode 6a in the place where the emitter region 3 does not exist becomes a parasitic capacitance of the element. As the input capacitance of the device increases due to this parasitic capacitance, there is a problem that the gate drive charge increases and the switching speed decreases.

Therefore, in the techniques of Patent Documents 1 and 2, the first gate electrode 6a is also partially thinned out. However, in such a configuration, in the configuration in which the charge storage layer capable of reducing the on-resistance is added as a whole, the charge storage layer is not depleted when the element is interrupted and a voltage is applied. However, there was a problem that the withstand voltage was lowered. Therefore, the semiconductor switching element according to the first embodiment of the present invention described below can solve this problem.

<Embodiment 1>
FIG. 1 is a plan view showing a configuration of a semiconductor switching element according to the first embodiment of the present invention. 2 and 3 are cross-sectional views taken along the AA'line and the BB' line of FIG. Note that, in FIG. 1, some of the components shown in FIGS. 2 and 3 are not shown.

The semiconductor switching element according to the first embodiment is a charge storage type insulated gate bipolar transistor like the first and second related switching elements. Hereinafter, among the components described in the first embodiment, the same or similar components as those described above will be designated by the same reference numerals, and different components will be mainly described.

The semiconductor switching element according to the first embodiment has a P-shaped conductive region 2b, a second trench 5b, a second gate electrode 6b, and a second gate insulating film, in addition to the configuration of the first related switching element. The second gate oxide film 7b is provided.

As shown in FIG. 2, on the cell region, which is the first surface of the upper surface of the semiconductor layer 1, the charge storage layer 4, the base region 2a, and the emitter region 3 are located on the cell region, similarly to the first related switching element. They are arranged in order. Although the position of the emitter region 3 and the position of the charge storage layer 4 in the depth direction are different, the pattern of the emitter region 3 in the plan view of FIG. 1 and the position of the charge storage layer 4 in the plan view of FIG. 1 are different. It is the same as the pattern.

A conductive region 2b is arranged on the second surface of the upper surface of the semiconductor layer 1. The first and second trenches 5a and 5b are not provided inside the conductive region 2b.

In the first embodiment, as shown in FIG. 1, a plurality of conductive regions 2b, a plurality of first trenches 5a, and a plurality of second trenches 5b are arranged in the lateral direction of FIG. The plurality of emitter regions 3 are arranged in the vertical direction of FIG. 1 in which the first and second trenches 5a and 5b extend, and are arranged so as to be separated from each other by the base region 2a and the high concentration region 13. There is. As shown in FIG. 3, the high concentration region 13 is arranged on the base region 2a.

As shown in FIG. 2, the first trench 5a reaching the semiconductor layer 1 from the upper surface of the emitter region 3 is provided so as to be orthogonal to, that is, intersect with the emitter region 3, the base region 2a, and the charge storage layer 4.

Here, the semiconductor switching element according to the first embodiment is provided with the second trench 5b. The second trench 5b reaches the semiconductor layer 1 from the upper surfaces of the emitter region 3 and the conductive region 2b. The second trench 5b is adjacent to the emitter region 3, the base region 2a, the charge storage layer 4, and the conductive region 2b. The depth of the second trench 5b is shallower than the depth of the first trench 5a, and the width of the second trench 5b is narrower than the width of the first trench 5a.

The first gate electrode 6a is arranged in the first trench 5a via the first gate oxide film 7a. Similarly, the second gate electrode 6b is disposed in the second trench 5b via the second gate oxide film 7b. The depth of the second gate electrode 6b is shallower than the depth of the first gate electrode 6a. Of the base region 2a interposed between the emitter region 3 and the semiconductor layer 1, the peripheral portions of the first and second gate electrodes 6a and 6b function as channel regions.

<Operation>
The operation of the semiconductor switching element according to the first embodiment will be described. _{In FIGS. 2 and 3, a predetermined positive collector voltage VCE} is applied between the emitter electrode 9 and the collector electrode 12, and between the emitter electrode 9 and the first gate electrode 6a and between the emitter electrode 9 and the emitter electrode 9. It is assumed that a predetermined positive gate voltage _VGE is applied between the and the second gate electrode 6b to turn on the gate. At this time, the channel region of the base region 2a is inverted from P-type to N-type to form a channel, and electrons are injected from the emitter electrode 9 into the semiconductor layer 1 through this channel. The injected electrons put a forward bias state between the collector region 11 and the semiconductor layer 1, and holes are injected from the collector region 11 into the semiconductor layer 1. As a result, the resistance of the semiconductor layer 1 is significantly reduced, and the on-resistance of the semiconductor switching element is significantly reduced, so that the current capacity is increased. Further, since the holes supplied from the collector region 11 are stored directly under the charge storage layer 4 by the charge storage layer 4, the effect of further lowering the on-resistance of the semiconductor switching element can be obtained.

Next, the operation when the semiconductor switching element according to the first embodiment is turned off from the on state to the off state will be described. _{In FIGS. 1 and 2, the gate voltage VGE} applied between the emitter electrode 9 and the first gate electrode 6a and between the emitter electrode 9 and the second gate electrode 6b is changed from positive to zero or negative ( Reverse bias). As a result, the channel region that has been inverted to the N-type returns to the P-type, and the injection of electrons from the emitter electrode 9 into the semiconductor layer 1 is stopped. By stopping the injection of electrons, the injection of holes from the collector region 11 into the semiconductor layer 1 is also stopped. After that, the electrons accumulated in the semiconductor layer 1 are collected in the collector electrode 12, and the holes accumulated in the semiconductor layer 1 are collected in the emitter electrode 9, or are recombined with each other and disappear.

_{At this time, since a predetermined positive collector voltage VCE} is applied to the element between the emitter electrode 9 and the collector electrode 12, the PN junction composed of the semiconductor layer 1 and the base region 2a and the bottom of the second trench 5b The maximum electric field is applied to and. Here, since the charge storage layer 4 is sandwiched between trenches arranged at intervals of a predetermined distance or less and the charge storage layer 4 is not provided under the conductive region 2b, the charge storage layer 4 is in the off state. Is depleted. Therefore, even if the collector voltage _VCE is applied to the element, the withstand voltage of the element does not decrease.

Further, since the depth of the second trench 5b is shallower than the depth of the first trench 5a, the PN junction composed of the semiconductor layer 1 and the base region 2a is close to the bottom of the second trench 5b. That is, the parts to which the maximum electric field is applied are close to each other. This makes it easier to balance the electric field, so it is possible to suppress a decrease in withstand voltage at this point.

<Manufacturing method>
4 to 14 are views showing an example of a method for manufacturing a semiconductor switching element according to the first embodiment, and specifically, are cross-sectional views showing a state of the semiconductor switching element at each stage of the manufacturing process. .. 4 (a) to 14 (a) show the cross-sectional state in the line AA'of FIG. 1, and FIGS. 4 (b) to 14 (b) are the lines BB'of FIG. The cross-sectional state in.

In the steps shown in FIGS. 4 (a) and 4 (b), a ^{substrate 31 containing N-} type silicon is prepared. The substrate 31 may be a substrate containing a wide bandgap semiconductor such as gallium nitride and silicon carbide.

Next, in the steps shown in FIGS. 5 (a) and 5 (b), the P-type region 2 is formed by diffusing P-type impurities on the upper part of the substrate 31. The P-shaped region 2 finally becomes a base region 2a and a conductive region 2b. The portion of the substrate 31 other than the P-shaped region 2 is finally substantially the semiconductor layer 1. Therefore, in the following, the portion of the substrate 31 other than the P-shaped region 2 will be described as the semiconductor layer 1.

Then, in the steps shown in FIGS. 6 (a) and 6 (b), the emitter region 3 is formed in a part of the upper part of the P-type region 2, and a part of the part between the semiconductor layer 1 and the P-type region 2 is formed. The charge storage layer 4 is formed on the surface. At this time, since the pattern of the emitter region 3 in the plan view and the pattern of the charge storage layer 4 in the plan view are the same, the emitter region can be obtained simply by changing the acceleration voltage of impurity injection using the same photomask. 3 and the charge storage layer 4 can be formed almost at the same time.

In the steps shown in FIGS. 7 (a) and 7 (b), the high concentration region 13 is formed in another part of the upper part of the P-type region 2.

Next, in the steps shown in FIGS. 8 (a) and 8 (b), the first trench 5a penetrating the emitter region 3, the P-shaped region 2 and the charge storage layer 4 is formed, and the end of the emitter region 3 is formed. A second trench 5b is formed adjacently and penetrates the P-shaped region 2. At this time, by making the width of the second trench 5b narrower than the width of the first trench 5a, it is possible to simultaneously form the first and second trenches 5a and 5b having different depths in the same etching process due to the microloading effect. it can. By forming the second trench 5b, the P-shaped region 2 is separated into a base region 2a and a conductive region 2b. Although the base region 2a, the conductive region 2b, the emitter region 3 and the charge storage layer 4 are formed by the above steps, the order of formation thereof is not limited to the above order.

Then, in the steps shown in FIGS. 9 (a) and 9 (b), the first gate oxide film 7a is formed in the first trench 5a, and the second gate oxide film 7b is formed in the second trench 5b. Then, the first gate electrode 6a is embedded in the first trench 5a via the first gate oxide film 7a, and the second gate electrode 6b is embedded in the second trench 5b via the second gate oxide film 7b. Then, an insulating film 8 is formed to cover the upper surfaces of the first and second gate electrodes 6a and 6b and the upper portions of the peripheral portions of the first and second gate electrodes 6a and 6b.

In the steps shown in FIGS. 10A and 10B, the emitter electrode 9 covering the conductive region 2b, the emitter region 3 and the high concentration region 13 exposed from the insulating film 8 and the insulating film 8 is formed. To do.

In the steps shown in FIGS. 11A and 11B, the back surface of the semiconductor layer 1 is polished to adjust the thickness of the semiconductor layer 1 to a predetermined thickness. Next, in the steps shown in FIGS. 12 (a) and 12 (b), the buffer region 10 is formed at a predetermined depth from the back surface of the semiconductor layer 1. Then, in the steps shown in FIGS. 13 (a) and 13 (b), the collector region 11 is formed on the lower surface of the buffer region 10. Finally, in the steps shown in FIGS. 14 (a) and 14 (b), the collector electrode 12 is formed on the lower surface of the collector region 11. Through the above steps, the semiconductor switching element according to the first embodiment shown in FIGS. 2 and 3 can be obtained.

<Summary of Embodiment 1>
According to the semiconductor switching element according to the first embodiment as described above, even if the first gate electrode 6a is partially thinned out from the second related switching element of FIG. 23, the withstand voltage in the off state is as high as possible. The decrease can be suppressed. Further, since the depth of the second trench 5b is shallower than the depth of the first trench 5a, the PN junction composed of the semiconductor layer 1 and the base region 2a is close to the bottom of the second trench 5b. This makes it easier to balance the electric field, so it is possible to suppress a decrease in withstand voltage at this point. Further, by not providing the gate electrode in the conductive region 2b, the parasitic capacitance of the element can be reduced. As a result, it is possible to suppress an increase in the current driving the gate and suppress a decrease in the switching speed.

<Modified Example of Embodiment 1>
FIG. 15 is a cross-sectional view taken along the line AA'showing the configuration of the semiconductor switching element according to the modified example of the first embodiment. As shown in FIG. 15, the number of the base region 2a, the emitter region 3, the first trench 5a, the first gate electrode 6a, and the first gate oxide film 7a between the two conductive regions 2b is the embodiment. It may be increased from these numbers of 1. Even with such a configuration, it is possible to suppress a decrease in withstand voltage as in the first embodiment.

FIG. 16 is a cross-sectional view taken along the line AA'showing the configuration of the semiconductor switching element according to another modification of the first embodiment. As shown in FIG. 16, the width of the conductive region 2b may be wider than the width of the conductive region 2b of the first embodiment. Even with such a configuration, it is possible to suppress a decrease in withstand voltage as in the first embodiment.

The above modification can be similarly applied to the second embodiment described later.

<Embodiment 2>
The planar configuration of the semiconductor switching element according to the second embodiment of the present invention is the same as the planar configuration of the semiconductor switching element according to the first embodiment (FIG. 1). 17 and 18 are cross-sectional views taken along the AA'line and the BB' line of FIG. Hereinafter, among the components described in the second embodiment, the same or similar components as those described above will be designated by the same reference numerals, and different components will be mainly described.

As shown in FIGS. 17 and 18, the semiconductor switching element according to the second embodiment includes a cathode region 14 having an N type in addition to the components of the semiconductor switch element according to the first embodiment. The cathode region 14 is a region formed by N-type impurities, and is arranged below the conductive region 2b and below the semiconductor layer 1.

In the second embodiment, the cathode region 14 is arranged directly below the conductive region 2b and on the lower surface of the buffer region 10. The side portion of the cathode region 14 is adjacent to the collector region 11. The cathode region 14 does not have to be arranged below all the conductive regions 2b, and may be arranged below one or more conductive regions 2b. The semiconductor switching element according to the second embodiment configured in this way functions as a reverse conduction type insulated gate transistor. The reverse conduction type insulated gate transistor here includes a charge storage type insulated gate bipolar transistor described in the first embodiment and a freewheeling diode. Further, the freewheeling diode here includes a cathode region 14 and a conductive region 2b above the cathode region 14.

<Operation>
The operation of the semiconductor switching element according to the second embodiment will be described. The operation of the charge storage type insulated gate bipolar transistor among the semiconductor switching elements according to the second embodiment is the same as the operation described in the first embodiment. Hereinafter, the operation of the freewheeling diode among the semiconductor switching elements according to the second embodiment will be described.

In the structures of FIGS. 17 and 18, when a forward bias (anode voltage VAK) exceeding a predetermined threshold value is applied between the emitter electrode 9 and the collector electrode 12, holes are injected from the conductive region 2b into the semiconductor layer 1. Then, electrons are injected into the semiconductor layer 1 from the cathode region 14, and the forward voltage (VF) drops significantly. As a result, a current flows between the emitter electrode 9 and the collector electrode 12. Here, in the semiconductor switching element according to the second embodiment, the charge storage layer 4 is not arranged directly above the cathode region 14. Therefore, since the electrons supplied from the cathode region 14 are not hindered by the charge storage layer 4, a lower forward voltage can be obtained.

<Manufacturing method>
19 to 21 are views showing an example of a method for manufacturing a semiconductor switching element according to the second embodiment, and specifically, a cross section showing a state of the semiconductor switching element at each stage of a part of the manufacturing process. It is a figure. 19 (a) to 21 (a) show the cross-sectional state in the line AA'of FIG. 1, and FIGS. 19 (b) to 21 (b) are the lines BB'of FIG. The cross-sectional state in.

First, the steps shown in FIGS. 4 (a) and 4 (b) to the steps shown in FIGS. 12 (a) and 12 (b) described in the first embodiment are performed.

Next, in the steps shown in FIGS. 19A and 19B, the collector region 11 is formed on the lower surface of the buffer region 10 except immediately below the conductive region 2b. Then, in the steps shown in FIGS. 20 (a) and 20 (b), the cathode region 14 is formed directly below the conductive region 2b and on the lower surface of the buffer region 10. Finally, in the steps shown in FIGS. 21 (a) and 21 (b), the collector electrode 12 is formed on the lower surfaces of the collector region 11 and the cathode region 14. Through the above steps, the semiconductor switching element according to the second embodiment shown in FIGS. 17 and 18 can be obtained.

<Summary of Embodiment 2>
According to the semiconductor switching element according to the second embodiment as described above, it is possible to suppress the decrease in withstand voltage and reduce the parasitic capacitance of the element as in the first embodiment. Further, the cathode region 14 is arranged below the conductive region 2b without the charge storage layer 4 and below the semiconductor layer 1. Therefore, since the electrons supplied from the cathode region 14 are not hindered by the charge storage layer 4, a lower forward voltage (VF) can be obtained.

In the present invention, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted within the scope of the invention.

1 Semiconductor layer, 2a base region, 2b conductive region, 3 emitter region, 4 charge storage layer, 5a first trench, 5b second trench, 6a first gate electrode, 6b second gate electrode, 7a first gate oxide film, 7b 2nd gate oxide film, 14 cathode region.

Claims (4)

The semiconductor layer having the first conductive type and
A charge storage layer disposed on each of the two first surfaces of the upper surface of the semiconductor layer, which are provided apart from each other.
In each of the two first surfaces, a base region having a second conductive type, which is arranged on the charge storage layer, and
An emitter region having a first conductive type, which is arranged on the base region on each of the two first surfaces,
A conductive region having a second conductive mold, which is arranged on a second surface sandwiched between the two first surfaces of the upper surface of the semiconductor layer,
In each of the two first surfaces, the top surface of the emitter region penetrates the first surface to reach the semiconductor layer, and into a first trench intersecting the emitter region, the base region, and the charge storage layer. The first gate electrode disposed via the first gate insulating film and
In each of the two first surfaces, the top surface of the emitter region and the conductive region penetrates the upper surface of the semiconductor layer between the first surface and the second surface, reaches the semiconductor layer, and reaches the emitter. A second gate electrode disposed via a second gate insulating film in a second trench adjacent to the region, the base region, the charge storage layer, and the conductive region.
An emitter electrode arranged on the conductive region and in contact with the conductive region is provided.
A semiconductor switching device in which the depth of each of the second trenches is shallower than the depth of each of the first trenches, and the width of each of the second trenches is narrower than the width of each of the first trenches. The semiconductor switching element according to claim 1.
A semiconductor switching element further comprising a cathode region having a first conductive type, which is arranged below the conductive region and below the semiconductor layer. (A) A charge storage layer arranged on each of two first surfaces provided apart from each other on the upper surface of the semiconductor layer having the first conductive type.
In each of the two first surfaces, a base region disposed on the charge storage layer and having a second conductive type, and
In each of the two first surfaces, an emitter region disposed on the base region and having a first conductive type, and an emitter region.
A step of forming a conductive region having a second conductive mold, which is arranged on a second surface sandwiched between the two first surfaces of the upper surface of the semiconductor layer.
(B) A first surface of each of the two first surfaces, which penetrates the first surface from the upper surface of the emitter region, reaches the semiconductor layer, and intersects the emitter region, the base region, and the charge storage layer. The trench is formed, and each of the two first surfaces penetrates the upper surface of the semiconductor layer between the first surface and the second surface from the upper surfaces of the emitter region and the conductive region. A step of reaching the semiconductor layer and forming a second trench adjacent to the emitter region, the base region, the charge storage layer, and the conductive region.
(C) A step of forming a first gate electrode in the first trench via a first gate insulating film and forming a second gate electrode in the second trench via a second gate insulating film. ,
(D) The step of forming an emitter electrode in contact with the conductive region on the conductive region is provided.
A method for manufacturing a semiconductor switching element, wherein the depth of each of the second trenches is shallower than the depth of each of the first trenches, and the width of each of the second trenches is narrower than the width of each of the first trenches. The method for manufacturing a semiconductor switching element according to claim 3.
(E) A method for manufacturing a semiconductor switching element, further comprising a step of forming a cathode region having a first conductive mold below the conductive region and below the semiconductor layer.

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