JP2021082186A - Linear regulator - Google Patents

Abstract

To reduce heat generation and destruction of a power supply circuit, a load circuit or the like when a short-circuit state occurs, and to eliminate the need for a circuit design of phase compensation.SOLUTION: In this linear regulator, a main control circuit 20 drives a control terminal of an output transistor 14 according to a feedback voltage FB so that an output voltage VOUT matches a rated value. When an output current OUT exceeds a limit value, an overcurrent limiting circuit 36 controls a gate voltage of the output transistor 14 via a node N1 and limits the output current IOUT by means of a drooping characteristic. If a state in which the output current IOUT is restricted by the overcurrent limiting circuit 36 and the feedback voltage FB is lower than a threshold value FBTH exceeds a fixed limit, a cutoff-and-recovery circuit 40 brings an output transistor 14 into a completely off-state to stop a control operation of the main control circuit 20 and, after measuring a preset pause time, releases the off-state of the output transistor 14 to resume the control operation of the main control circuit 20.SELECTED DRAWING: Figure 1

Description

The present invention relates to a linear regulator that steps down a direct current input voltage by an on-resistance of a transistor and converts it into a direct current output voltage, and particularly relates to an LDO (low dropout) type linear regulator.

Today, linear regulators are used everywhere as a compact and simple regulated DC power supply that can output a stable power supply voltage with little voltage ripple and voltage noise. In general, a linear regulator changes the on-resistance of an output transistor connected in series with a load to lower the input voltage V _IN , and even if the input voltage V _IN fluctuates, the output voltage V _OUT is set to a set value or a rated value V. It is designed to keep on _LAT. In particular, LDO-type linear regulators are _{designed to operate stably even when the input voltage V IN} drops close to the rated value V _LAT (even if the voltage difference between the input and output, that is, the dropout becomes considerably small). ing.

_{Conventionally, the LDO type linear regulator monitors the current (output current) I OUT} output from the output transistor in order to protect the device circuit from heat generation and destruction due to overcurrent, and the output current I _OUT is a predetermined limit. When the value I _LIM is exceeded and an overcurrent state occurs, _{a foldback control type overcurrent control circuit that controls the output current I OUT} and the output voltage V _OUT with the F-shaped characteristic as shown in FIG. 8 is provided. There is. According to this, when it is over-current condition is operated overcurrent control circuit, while squeezing the output current I _OUT lowers the output voltage V _OUT, and the output current I _OUT in accordance with the decrease in the output voltage V _OUT the as narrowing, to follow the output current _{I OUT} and the output voltage _{V OUT} to fold-decrease-lowering simultaneously bring the output stop state of _V OUT _{= 0, I} OUT = _{I S} in the case of an output short circuit ..

Here, the output of between stop state also continues to flow a constant current (limit current) I _S is to automatically return when the short circuit state is canceled. In this type of linear regulator, load is connected to an output capacitor in parallel, if it is released short-circuited state, the charging voltage, i.e. the output voltage V _OUT of the output capacitor rises by the lowest current I _S, the curve characteristics of the full As the output voltage V _OUT rises, the output current I _OUT also increases, and eventually returns to the _{normal output voltage V OUT} and output current I _OUT.

Japanese Unexamined Patent Publication No. 2006-155501 JP-A-2015-64866

However, in the foldback control as described above, not only a considerable amount of heat is generated in the process of narrowing down the _{output current I OUT according to the F-shaped characteristic, but also while the output voltage V OUT} is zero. since continues to flow a constant lower limit current I _S, the output transistor continues to fever, is large power loss. Further, when the overcurrent is generated in the not so low impedance as ground fault or short circuit, the output voltage V _OUT is not lowered to zero, yet lower-limit current I _S output current I _OUT at a large amount of current than is It continues to flow while the output is stopped, and heat generation is unavoidable even on the load side. Further, in the process of controlling the output current I _OUT and the output voltage V _{OUT following} the letter F, the feedback control system of the main control circuit is likely to cause abnormal oscillation. Therefore, a capacitor for phase compensation must be provided around the error amplifier of the main control circuit, which has the disadvantage that the circuit design is troublesome.

The present invention solves the above-mentioned problems of the prior art, and provides a linear regulator that reduces heat generation or destruction of a power supply circuit, a load circuit, etc. when a short-circuit state occurs, and eliminates the need for phase compensation circuit design. To do.

The linear regulator of the present invention has an output transistor connected between an input terminal for inputting an input voltage and an output terminal for outputting an output voltage, and a feedback voltage generation circuit that divides the output voltage to generate a feedback voltage. And, based on the feedback voltage, the main control circuit that controls the voltage of the control terminal of the output transistor via the first node so that the output voltage matches or approximates, and the output current flowing through the output transistor. An overcurrent limiting circuit that monitors and controls the voltage of the control terminal of the output transistor via the first node and limits the output current with a drooping characteristic when the output current exceeds a predetermined limit value. When the feedback voltage and the output current are monitored and the output current is limited by the overcurrent limiting circuit and the feedback voltage is below a predetermined voltage threshold exceeds a certain limit. , The output transistor is completely turned off to stop the control operation of the main control circuit, the preset pause time is timed, and then the off state of the output transistor is released to perform the control operation of the main control circuit. It has a cutoff / return circuit to restart.

In the linear regulator having the above configuration, the main control circuit performs negative feedback control operation so as to keep the output voltage close to the set value, and controls the control voltage of the output transistor in the direction of increasing the output current when the output voltage drops. If the output voltage rises, the control voltage of the output transistor is controlled in the direction of reducing the output current.

However, when the output current exceeds the limit value, the overcurrent limit circuit operates and limits the output current to or near the limit value due to the drooping characteristic. Then, when the feedback voltage obtained from the feedback voltage generation circuit falls below the voltage threshold, the cutoff / recovery circuit starts operating, the output current is limited to the vicinity of the limit value by the overcurrent limiting circuit, and the feedback voltage sets the voltage threshold. When the voltage falls below a certain limit, the output transistor is forcibly turned off completely and the control operation of the main control circuit is stopped.

During this output stop period, not only the output voltage becomes zero, but also the output current does not flow at all, so that the output transistor does not generate heat at all. Then, after a certain pause time elapses, the cutoff / recovery circuit releases the off state of the output transistor and restarts the control operation of the main control circuit. Therefore, if the short-circuit state is released during the pause time, it is normal. It can be returned to the output state.

Further, since the cutoff / return circuit in the present invention performs the operation of logic control, the feedback control system of the main control circuit does not cause abnormal oscillation. Therefore, a troublesome phase compensation design such as providing a phase compensation capacitor is unnecessary.

According to the linear regulator of the present invention, the above configuration and operation can reduce heat generation or destruction of the power supply circuit, load circuit, etc. when a short-circuit state occurs, and eliminate the need for phase compensation circuit design. ..

It is a block diagram which shows the whole structure of the linear regulator in one Embodiment of this invention. It is a circuit diagram which shows the concrete configuration example of. It is a figure which shows the state or the waveform of each part in the linear regulator of FIG. 2 when the state of an overcurrent occurs by the output short circuit. It is a figure which shows the state or the waveform of each part in the linear regulator of FIG. 2 when the state of an overcurrent occurs by a ground fault or a rare short circuit. It is a figure which shows the state or the waveform of each part when the state of an overcurrent occurs by a temporary overload. It is a figure which shows the characteristic _{of the output current I OUT} − output voltage V _OUT in the case of FIG. 3A. It is a figure which shows the characteristic _{of the output current I OUT} − output voltage V _OUT in the case of FIG. 3B. It is a figure which shows the characteristic _{of the output current I OUT} − output voltage V _OUT in the case of FIG. 3C. It is a figure which shows the cycle of the automatic return operation and its action (waveform of an output current) when a short-circuit state continues for a while in the linear regulator of FIG. FIG. 5 is a macroscopic view of the period and current waveforms of FIG. It is a figure which shows the layout structure of the compound power supply IC which can apply this invention. It is a figure which shows the F-shaped characteristic of output current-output voltage in the prior art.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
[Overall configuration of the linear regulator in the embodiment]

FIG. 1 shows the overall configuration of the linear regulator according to the embodiment of the present invention. This linear regulator is configured as a series regulator, and an output transistor 14 is provided between the _{V IN} input terminal 10 and the V _{OUT output terminal 12 in series with the load.}

A DC voltage V _IN higher than the set value or rated value V _{LAT of the output voltage V OUT is input to the V IN} input terminal 10 from a battery, a storage battery or another DC power supply (not shown). Not only the load but also the output capacitor 16 is connected between the V _{OUT output terminal 12 and the ground potential terminal.}

This linear regulator includes a main control circuit 20 and a feedback voltage generation circuit 22 as basic elements. The feedback voltage generation circuit 22 is composed of _{two resistors 24 and 26 connected in series between the V OUT} output terminal 12 and the ground potential terminal, and is proportional to the output voltage V _{OUT from the node N 0 between the two resistors.} The voltage dividing voltage is taken out as the feedback voltage FB.

The main control circuit 20 is configured to change the on-resistance of the output transistor 14 according to the feedback voltage FB so that _{the output voltage V OUT} matches or approximates the rated value V _LAT. More specifically, the main control circuit 20 compares the reference voltage source 28 that outputs the fixed reference voltage VREF1 with the reference voltage circuit 30 that outputs the variable reference voltage SST, and the lower of the reference voltages VREF1 and SST. an error amplifier 32 for generating an error signal ER by using the reference voltage represents a comparison error between it and the feedback voltage FB, driver circuit 34 which drives via the node N ₁ to the control terminal of the output transistor 14 in response to the error signal ER And have.

Here, a fixed reference voltage VREF1 that is output from the reference voltage source 28, has a fixed voltage level corresponding to the rated value V _RAT of the output voltage V _OUT, using the comparison reference voltage after completing boot completion or return Be done. On the other hand, the variable reference voltage SST output from the reference voltage circuit 30 has a variable _{voltage level between a ground potential lower than the first reference voltage VREF1 and a VIN} level (input voltage level) higher than VREF1. Is used as a reference voltage for comparison at startup or recovery.

This linear regulator is also configured as an LDO type linear regulator and includes an overcurrent limiting circuit 36. _{The overcurrent limiting circuit 36 monitors the output current I OUT} flowing through the output transistor 14, and when the output current I _OUT exceeds the preset limit value _ILIM , the node N takes precedence over the main control circuit 20. The gate voltage of the output transistor 14 is controlled via _{1 , and the output current I OUT} is limited by the drooping characteristic.

_{In the series regulator, the current I IN} flowing on the input side of the output transistor 14 _{and the current I OUT} flowing on the output side are exactly the same (in the case of a field effect transistor) or substantially the same (in the case of a bipolar transistor). If). Therefore, the overcurrent limiting circuit 36 may detect the _{current I IN} flowing on the input side of the output transistor 14 as the output current I _OUT.

Further, this linear regulator is provided with a cutoff / recovery circuit (protection circuit) 40 for protecting the power supply circuit and load circuit from heat generation and destruction when various short-circuit states such as output short circuit, ground fault, and rare short circuit occur. doing.

Blocking and restoring circuit 40, a feedback voltage FB and the output current I _OUT and monitored via a feedback voltage generating circuit 22 and the overcurrent limiting circuit 36, the output current I _OUT is limited by the overcurrent limiting circuit 36, and feedback When the state in which the voltage FB is _{below the predetermined voltage threshold FB TH} exceeds a certain limit, the output transistor 14 is completely turned off to stop the control operation of the main control circuit 20, and the preset pause time DT After the time is measured, the off state of the output transistor 14 is released, and the control operation of the main control circuit 20 is restarted.

[Specific configuration of the linear regulator in the embodiment]

FIG. 2 shows a specific configuration of the linear regulator in this embodiment.

The output transistor 14 is composed of a epitaxial transistor, the source is _{connected to the V IN} input terminal 10, the drain is connected to the V _OUT output terminal 12, and the gate is connected to the node N1.

In the main control circuit 20, the DC voltage circuit 30 that outputs a variable reference voltage SST has a constant current source 42 and a capacitor 44 in series between the _VIN supply terminal corresponding to the _{VIN input terminal 10 and the ground potential terminal.} The variable reference voltage SST is output from the node N2 between the _two.

Node N ₂ is connected to one non-inverting input terminal (+) of the error amplifier 32, and is also connected to the drain of the NMOS transistor 94 of the cutoff / recovery circuit 40 and the inverting input terminal (-) of the comparator 82, which will be described later. Has been done. While the NMOS transistor 94 is off, the capacitor 44 is applied to the constant current are fully charged, the node _{N 2} than _{V IN} level of the reference voltage SST error amplifier 32 and the comparator 82 from the constant current source 42 .. However, when the NMOS transistor 94 is turned on, the capacitor 44 is _{discharged via the node N 2} and the on state NMOS transistor 94, and the ground potential reference voltage SST is given to the error amplifier 32 and the comparator 82 from _{the node N 2.} Then, when the NMOS transistor 94 changes from the on state to the off state, the constant current from the constant current source 42 flows into the capacitor 44, and the charging voltage of the capacitor 44, that is, the reference voltage SST on the _{node N 2 changes from the ground potential to VIN.} It is designed to rise linearly to the level.

The driver circuit 34 _is connected in series with the resistor 46 and the NMOS transistor 48 between the _{V IN} supply terminal and the ground potential terminal via the node _{N 1.} Here, NMOS transistor 48 has a source connected to the ground potential terminal, the drain is connected to the node N _1, and inputs an error signal ER from the error amplifier 32 to the gate.

In the main control circuit 20 having such a configuration, when the feedback voltage FB becomes lower than the comparison reference voltage (VREF1 or SST), the voltage level of the error signal ER becomes higher and the drain current i ₄₈ of the NMOS transistor 48 and thus the resistor 46 voltage drop increases, decreases the gate voltage of the node _{N 1} of the potential, that the output transistor (PMOS transistor) 14. As a result, the drain current of the output transistor 14, that is, the output current I _OUT increases. On the contrary, when the feedback voltage FB becomes high, each part changes in the opposite direction to the above, and the output current I _OUT decreases accordingly.

However, the overcurrent limiting circuit 36 and the shutoff-recovery circuit 40 will be described later are also connected to the node N _1, preferentially the gate voltage of the output transistor 14 to the main control circuit 20 when these circuits 36 and 40 operate Is designed to control.

The overcurrent limiting circuit 36 includes a MOSFET transistors 50, 52, 54, a resistor 56 and an NMOS transistor 58.

More specifically, PMOS transistor 50 has a source connected to V _IN input terminal 10, the drain is connected to the ground potential terminal via the node N ₃ and a resistor 56, a gate connected to node N _1. PMOS transistor 52 has a source connected to _{V IN} input terminal 10, a drain connected to the node _{N 4,} the gate is connected to the drain and the node _{N 4.} PMOS transistor 54 has a source connected to _{V IN} input terminal 10, a drain connected to the node _{N 1,} a gate connected to the gate and drain of the PMOS transistor 52. Both epitaxial transistors 52 and 54 form a current mirror circuit. NMOS transistor 58 has a source connected to the ground potential terminal, the drain is connected to the node N _4, a gate connected to the node N _3.

In this overcurrent limiting circuit 36, the gate of the PMOS transistor 50 are commonly connected to the gate of the output transistor (PMOS transistor) 14 via the node _{N 1.} As a result, a drain current i _{50 corresponding to the output current I OUT} flows through the epitaxial transistor 50, and a _{drain current i 50 and} thus a voltage VN ₃ corresponding to the output current I _OUT are generated as a voltage drop of the resistor 56 at the node N _3. It has become so.

When the voltage VN ₃ of the node _{N 3} is greater than the threshold value _{TH 58} of the NMOS transistor 58, NMOS transistor 58 is turned on, now flowing drain current _{i 52} of the PMOS transistor 52 is further PMOS by a current mirror effect The same amount or a proportional amount of drain current i ₅₄ flows through the transistor 54 as well. In this way, the currents flowing through the epitaxial transistors 50, 52, and 54 correspond to the _{output currents I OUT, respectively.} In this embodiment, the resistance value of the resistor 56 is set so that the voltage VN ₃ of the node N ₃ exceeds the threshold value TH _{58 of the NMOS transistor 58 when the output current I OUT} exceeds the allowable value _ILIM. The drain current _{i 54} of the PMOS transistor 54 is a part of the drain current _{i 48} of the NMOS transistor 48 of the driver circuit 34 via the node _{N 1.} Therefore, the voltage drop of the resistor 46 decreases _{, the voltage of N 1} rises, and the overcurrent is suppressed.

If the voltage VN ₃ of the node _{N 3} is less than the threshold value _{TH 58} of the NMOS transistor 58, NMOS transistor 58 is turned off, the drain current _{i 52, i 54} in the PMOS transistors 52 and 54 does not flow.

The cutoff / return circuit 40 includes an output state monitoring circuit 60, a determination circuit 62, an enable circuit 64, a latch circuit 66, and a timer circuit 100.

Output state monitoring circuit 60 _connects the two PMOS transistors 70 and 72 in series between the _{V IN} input terminal 10 and the node _{N 5.} Here, one of the PMOS transistor 70 is for monitoring the output current _{I OUT,} a source connected to _{V IN} input terminal 10, a drain connected to the source of the PMOS transistor 72, a gate node _{N 4} It is connected to the drain and gate of the epitaxial transistor 52 of the overcurrent limiting circuit 36 via. When the epitaxial transistor 72 is on, the epitaxial transistor 70 _{causes a drain current i 70} which is a current mirror or a copy _{of the drain current i 52} of the epitaxial transistor 52 to flow.

PMOS transistor 72 is for monitoring the output voltage _{V OUT} or the feedback voltage FB, its source connected to the drain of the PMOS transistor 70, its drain connected to the node _{N 5,} the feedback voltage generation circuit to the gate The feedback voltage FB from 22 is input. PMOS transistor 72, then the gate voltage, i.e. the feedback voltage FB is higher than a predetermined voltage threshold FB _TH keeps the off state, the feedback voltage FB is adapted to turn on if the lower electric pressure threshold FB _TH. The voltage threshold value FB _TH is preferably a value that can detect an abnormal drop in the feedback voltage FB at an early stage, and may be set to _{, for example, FB TH = 0.7 to 0.8 VREF1.}

The node N _5, the decision circuit 62 and the enable circuit 64 is also connected. The determination circuit 62 is for determining whether it is due to a short circuit or a temporary overload when an overcurrent state occurs, and has a capacitor 74, a resistor 76, and a comparator 78. ing. Capacitor 74 and resistor 76 are connected in parallel between the node N ₅ and the ground potential terminal. The comparator 78 is connected to one input terminal (+) of the node N _5, the other input terminal (-) is connected to a reference voltage source 80. The reference voltage source 80 provides a reference voltage VREF2 for determination.

The capacitor 74 is charged by _{the drain current i 70} of the epitaxial transistor 70 when the epitaxial transistor 72 is on. Voltage VCHG of the charging voltage, i.e. node _{N 5} of the capacitor 74 is compared with the determination reference voltage VREF2 by the comparator 78. The output DET of the comparator 78 is L level when VCHG <VREF2 and H level when VCHG> VREF2. When the output DET of the comparator 78 changes from the L level to the H level, the latch circuit 66 described later responds to this.

The enable circuit 64 includes a comparator 82, a reference voltage source 84, and an NMOS transistor 86. A variable reference voltage SST is input from the reference voltage circuit 30 of the main control circuit 20 to one input terminal (-) of the comparator 82. A predetermined reference voltage VREF3 is input from the reference voltage source 84 to the other input terminal (+). The output of the comparator 82 is H level when SST <VREF3 and L level when SST> VREF3. The reference voltage VREF ₃ is set to a somewhat lower value than _{V I} level which is the maximum value of the SST.

NMOS transistor 86 has a source connected to the ground potential terminal, the drain is connected to the node N _5, receives the output of the comparator 82 to the gate. When SST <VREF3, the output of the comparator 82 is H level, and the NMOS transistor 86 is on. In this state, the capacitor 74 cannot be charged, and the determination circuit 62 is placed in an disabled state.

However, when SST> VREF3, the output of the comparator 82 becomes the L level, the NMOS transistor 86 is turned off, the capacitor 74 can be charged, and the determination circuit 62 is enabled.

The latch circuit 66 includes an RS flip-flop 88, an NMOS transistors 90, 92, 94, a MOSFET transistor 96 and a resistor 98.

In the RS flip-flop 88, the set input terminal (S) is connected to the output terminal of the comparator 78 of the determination circuit 62, and the output terminal (Q) is connected to the gate of the NMOS transistors 90, 92, 94 and the input terminal of the timer circuit 100. Then, the reset input terminal (R) is connected to the output terminal of the timer circuit 100.

When the output DET of the comparator 78 changes from the L level to the H level, the RS flip-flop 88 latches the output DET of the comparator 78, sets the (Q) output SET to the H level, and cuts off the output SET to the NMOS transistors 90, 92, 94. The timer circuit 100 is made to perform the time counting operation for the automatic return as well as the switch operation for the above.

The NMOS transistors 90, 92, and 94 are turned on and off in conjunction with each other according to the (Q) output SET of the RS flip-flop 88. That is, when the (Q) output SET is at the L level, the NMOS transistors 90, 92, 94 are off, and when the (Q) output SET is at the H level, the NMOS transistors 90, 92, 94 are turned on. It has become.

The NMOS transistor 90 functions as a switch for forcibly turning off the output transistor 14, the source is connected to the ground potential terminal, the drain is connected to the gate of the NMOS transistor 96, and the _VIN input is via a resistor 98. It is connected to the terminal 10. The source of the PMOS transistor 96 is connected to _{V IN} input terminal 10, the drain is connected to node _{N 1.} The MOSFET transistor 96 functions as a switch having a master-slave relationship with the NMOS transistor 90.

That is, when the NMOS transistor 90 is off, the NMOS transistor 96 is also off, and when the NMOS transistor 90 is on, the NMOS transistor 96 is also on. When the PMOS transistor 96 is turned on, the node _{N 1} is clamped to _{V IN} level via the PMOS transistor 96 in the ON state, the output transistor 14 becomes completely off state.

Then, when the return operation is performed, the (Q) output SET of the RS flip-flop 88 changes from the H level to the L level as described later, so that the NMOS transistor 90 is turned off and the NMOS transistor 96 is turned off accordingly. Switch to.

When the output transistor 14 is forcibly turned off, the NMOS transistor 92 functions as a switch for forcibly turning off the NMOS transistor 48 of the driver circuit 34 in conjunction with the output transistor 14. The source of the NMOS transistor 92 is connected to the ground potential terminal and the drain is connected to the gate of the NMOS transistor 48.

When the NMOS transistor 92 is off, the NMOS transistor 48 can drive the output transistor 14 in response to the error signal ER from the error amplifier 32. However, when the NMOS transistor 92 is turned on, the gate of the NMOS transistor 48 is clamped to the ground potential, and the NMOS transistor 48 is completely turned off.

Then, when the return operation is performed, the (Q) output SET of the RS flip-flop 88 changes from the H level to the L level, and the NMOS transistor 92 is turned off, so that the NMOS transistor 48 of the driver circuit 34 is enabled. ..

The NMOS transistor 94 functions as a switch for lowering the variable reference voltage SST of the reference voltage circuit 30 _{from the VIN level to the ground potential in conjunction with the forced off of the output transistor 14.} The source of the NMOS transistor 94 is connected to the ground potential terminal, the drain is connected to the node N ₂ of the reference voltage circuit 30.

When the NMOS transistor 94 is off, the constant current source 42 charges the capacitor 44 in the reference voltage circuit 30, or maintains the fully charged state, the error from the node N ₂ charge voltage as a reference voltage SST capacitor 44 It is output to the amplifier 32 and the comparator 82. However, when the NMOS transistor 94 is turned on, the capacitor 44 is discharged, the reference voltage SST on node _{N 2} drops to ground potential from _{V IN} level instantly.

When performing the return operation, the (Q output) SET of the RS flip flop 88 changes from the H level to the L level, and the NMOS transistor 94 is turned off, so that the capacitor 44 is transmitted from the constant current source 42 in the reference voltage circuit 30. It is charged by the constant current, a reference voltage SST on node N ₂ is gradually increased from the ground potential to V _iN level.

The timer circuit 100 has, for example, a clock generation circuit and a counter circuit, and when the (Q) output SET of the RS flip-flop 88 changes from the L level to the H level, the timer circuit 100 starts the timing operation in response to the change and is set in advance. After measuring the pause time DT, the reset input terminal (R) of the RS flip-flop 88 is configured to give an H level reset signal RESET. The pause time DT can be set to any length, and is set to, for example, several hundred milliseconds.

When the RS flip-flop 88 receives the reset signal RESET from the timer circuit 100, the RS flip-flop 88 changes the (Q) output SET from the previous H level to the L level in response to the reset signal RESET. Then, the NMOS transistors 90, 92, and 94 change from the on state to the off state, and the return operation is started.

[Operation of linear regulator in the embodiment]

The operation of this linear regulator in an overcurrent state will be described below with reference to FIGS. 3A to 3C, 4A to 4C, and FIGS. 5 and 6.
<< In case of output short circuit >>

FIG. 3A shows the state or waveform of each part when an overcurrent state occurs due to an output short circuit. FIG. 4A shows the characteristics _{of the output current I OUT} − output voltage V _OUT in the case of FIG. 3A.

In this case, the _{output state is stable until the time point t 0} , and neither the overcurrent limiting circuit 36 nor the cutoff / recovery circuit 40 is operating. In the overcurrent limiting circuit 36, the epitaxial transistor 50 causes _{the drain current i 50} , which is a current mirror of the _{output current I OUT} , to flow, but the voltage VN _{3 of the node N 3} is lower than the threshold value TH _{58 of the} NMOS transistor 58, so that the current is limited. The NMOS transistor 58 of the operation switch is in the off state, whereby both PMMOS transistors 52 and 54 of the current mirror circuit are turned off.

Also in cutoff-recovery circuit 40, since the feedback voltage PMOS transistor 72 of the monitoring switch is turned off, the voltage VCHG at the node _{N 5} is in the ground potential, the output DET is L level of the comparator 78 in the decision circuit 62, a latch In the circuit 66, the (Q) output SET of the RS flip-flop 88 is set to the L level, the NMOS transistors 90, 92, and 94 are set to the off state, and the NMOS transistors 96 are also set to the off state. The timer circuit 100 is not performing a timekeeping operation.

Accordingly, the gate voltage of the output transistor 14 is controlled exclusively by the main control circuit 20 via the node N _1. At this time, the NMOS transistor 48 of the driver circuit 34 _{passes a drain current i 48} corresponding to the error signal ER, the same current i ₄₈ also flows through the _{resistor 46, and a voltage lower than the input voltage VIN} by the voltage drop of the resistor 46 is a node. It is given to the gate of the output transistor 14 via _{N 1.} By the negative feedback control of the main control circuit 20, the output voltage V _OUT is stably maintained near the rated value V _{LAT even if the input voltage V IN} and the output current I _{OUT fluctuate to some extent.}

However, it occurs output short at time t _0, which causes the output current I _OUT exceeds the limit value I _LIM rapidly increasing As soon as the overcurrent limiting circuit 36 is operated. That is, at _{the moment when the output current I OUT} exceeds the limit value _ILIM , the voltage VN ₃ of the node N ₃ exceeds the threshold value TH ₅₈ of the NMOS transistor 58, and the NMOS transistor 58 of the limiting operation switch is turned on. Then, the epitaxial transistor 52 starts _{to flow the drain current i 52} , and the epitaxial transistor 54 flows _{the drain current i 54} which is a current mirror or a copy of the _{drain current i 52.} The drain current i ₅₄ of the epitaxial transistor _{54 corresponds to the drain current i 50} of the epitaxial transistor 50, and thus corresponds to the output current I _OUT flowing through the output transistor 14.

Drain current _{i 54} of the PMOS transistor 54 is joined to the current flowing through the resistor 46 at node _{N 1,} a part of the drain current _{i 48} of the NMOS transistor 48 of the driver circuit 34. Thus, even a drain current _{i 48} of the NMOS transistor 48 is the same, the current flowing through the resistor 46 is reduced by the drain current _{i 54} of the PMOS transistor 54. In this way, the gate voltage of the output transistor 14 is rate-determined and increased by _{the drain current i 54 of the epitaxial transistor 54, and the output current I OUT} is limited to or near the _{limit value ILIM.}

Originally, in the main control circuit 20, _{if the output voltage V OUT} decreases, the output voltage of the error amplifier 32, that is, the voltage of the error signal ER increases, and _{the drain current i 48 of the NMOS transistor 48 of the driver circuit 34 increases.} thereby lowers the gate voltage of the voltage, i.e. the output transistor 14 of the node N _1, the output current I _OUT is should increase. However, when the overcurrent limiting circuit 36 operates, the drain current i ₅₄ of the epitaxial transistor 54 dominates the voltage of the node N ₁ , that is, the gate voltage of the output transistor 14, and the output current I _OUT is set to the limit value I _LIM. It is designed to be restricted to the vicinity.

On the other hand, when an output short circuit occurs, the output capacitor 16 is instantaneously discharged on the load side, the output voltage V _OUT drops sharply to the vicinity of the ground potential, and the feedback voltage FB also drops sharply to the vicinity of the ground potential accordingly. At this time, to be precise, when the feedback voltage FB _{falls below the voltage threshold FB TH} (time point t ₁ ), the epitaxial transistor 72 of the output state monitoring circuit 60 is turned on by the cutoff / recovery circuit 40, and the epitaxial transistor 70 is the output transistor 14 A drain current i _70, which is a current mirror of the output current I _{OUT of the above,} is started to flow, and charging of the capacitor 74 by the _{drain current i 70 is started.} In the enable circuit 64, since SST> VREF3, the output of the comparator 82 is at the L level, and the NMOS transistor 86 is off.

Then, when the overcurrent limiting circuit 36 limits the output current I _OUT to the vicinity of the limiting _{value ILIM as described above, and the state in which the feedback voltage FB is below the voltage threshold FB TH} continues as it is, the circuit is cut off and restored. when the voltage VCFG node _{N 5} in the judgment circuit 62 of the circuit 40 exceeds the monitoring value VREF2 (time _t 2), output DET from the comparator 78 changes from L level to H level. Then, in response to this, the (Q) output SET of the RS flip-flop 88 of the latch circuit 66 changes from the L level to the H level, and the NMOS transistors 90, 92, 94, and 96 are turned on, respectively, so that the output transistor 14 is turned on. The control operation of the main control circuit 20 is stopped by forcibly turning it off completely.

In this way, when the output transistor 14 is completely turned off, the output current I _OUT does not flow at all, the output voltage V _OUT is also held at the ground potential, and the output is completely stopped. Under such a completely output stop state, not only the load but also the output transistor 14 does not generate heat at all. When the output current I _OUT is cut off, no internal current flows even in the overcurrent limiting circuit 36, and the transistors 50, 52, 54, and 58 are placed in the off state. Further, even in the cutoff / recovery circuit 40, the NMOS transistor 70 is turned off and the drain current i70 does not flow, and the capacitor 74 is discharged by the NMOS transistor 86.

On the other hand, when the (Q) output SET of RS flip-flop 88 changes from L level to H level (time _{t 2),} the timer circuit 100 starts measuring operation. Then, when counting a predetermined dwell time DT (time _{t 3),} the timer circuit 100 outputs a reset signal RESET, Soreni response you want to bring RS flip-flop 88 is the (Q) output SET to L level. Then, the NMOS transistors 90, 92, 94, and 96 are turned off, respectively, and the output transistor 14, the NMOS transistor 48 of the driver circuit 34, and the reference voltage circuit 30 are released from the cutoff / recovery circuit 40. Then, the following return operation by soft start is started.

That, NMOS transistor 90 and PMOS transistor 96 of the shutoff-recovery circuit 40 by turning off the gate or node _{N 1} of the output transistor 14 is released from the clamp potential forced off _{(V IN).} Further, when the NMOS transistor 92 is turned off, the gate of the NMOS transistor 48 of the driver circuit 34 in the main control circuit 20 is released from the clamp potential (ground potential) of forced off. On the other hand, NMOS transistor 94 by turning off, the capacitor 44 is charged by the reference voltage circuit 30. In the reference voltage SST on node _{N 2} is gradually increased to _{V IN} level from the ground potential.

In this way, while both the overcurrent limiting circuit 36 and the cutoff / recovery circuit 40 are in the stopped state, the main control circuit 20 is in the enabled state, and the variable reference voltage SST that gradually rises in the reference voltage circuit 30 is fixed. Assuming that the output short circuit was released during the pause time DT by being used as the comparison reference voltage of the error amplifier 32 until it exceeded the reference voltage VREF1, as shown in FIG. 3A, as the reference voltage SST increased. The output current I _OUT , output voltage V _OUT, and feedback voltage FB also gradually increase or rise, and return to the normal output state.

As described above, in this linear regulator, when the impedance on the load side is substantially zero and an output short circuit occurs, _{the characteristics of output current I OUT} − output voltage V _OUT as shown in FIG. 4A can be obtained. Unlike the F-shaped characteristic (FIG. 8) of the prior art _{, not only the output voltage V OUT} becomes zero but also the output current I _OUT does not flow at all during the output stop period, so that the output transistor 14 does not generate heat at all. Moreover, after the output transistor 14 is completely turned off in response to an output short circuit, if a certain pause time DT elapses, a recovery operation is automatically performed to return to the normal output state.

Further, the cutoff / recovery circuit 40 in the present embodiment immediately forces the output transistor 14 when it is determined that the overcurrent is due to a short circuit using a _{predetermined threshold value (FB TH) or monitoring value (VREF2).} Turn off. In this way, the cutoff / return circuit 40 performs a logical control operation independently of the feedback control system of the main control circuit 20. Therefore, the feedback control system of the main control circuit 20 does not cause abnormal oscillation, and a capacitor for phase compensation is not required.

《In the case of rare shorts》

FIG. 3B shows the state or waveform of each part in the event of a not-so-low impedance short circuit (eg, ground fault or rare short circuit). FIG. 4B shows the characteristics _{of the output current I OUT} − output voltage V _OUT in the case of FIG. 3B.

In this case as well, the _{output state is stable until the time point t 0} , and neither the overcurrent limiting circuit 36 nor the cutoff / recovery circuit 40 is operating as in the case of the output short circuit described above (FIG. 3A). Even if the input voltage V _IN and the output current I _{OUT fluctuate to some extent, the output voltage V OUT} is stably maintained near the rated value V _RAT by the negative feedback control of the main control circuit 20.

Then, the operation of each part immediately after a ground fault or a rare short circuit occurs near the time point t _{0 and the output current I OUT} exceeds the limit value _ILIM is almost the same as the case of the output short circuit described above (FIG. 3A). However, unlike the case of an output short circuit, the impedance of the load does not become extremely low, so that the output voltage V _OUT drops relatively slowly according to the discharge characteristics of the output capacitor 14. Therefore, the timing when the feedback voltage FB falls below the voltage threshold value FB _TH is slightly delayed, so that the timing at which the epitaxial transistor 72 of the monitoring switch is turned on in the cutoff / recovery circuit 40 and the capacitor 74 of the determination circuit 62 start charging. The timing (t ₁ ') to do is delayed.

However, even in this case, the overcurrent limiting circuit 36 limits the output current _{I OUT} near limit value _{I LIM,} and unless the feedback voltage FB is a state below the voltage threshold _{FB TH} a while persists, the circuit breaking and recovery circuit 40 charging voltage VCHG of the capacitor 74 exceeds the monitoring value VREF2, the output DET from the comparator 78 at the timing (time _{t 2} ') is changed from L level to H level, the RS flip-flop 88 (Q) output SET is L level Changes from to H level. As a result, the output transistor 14 is completely turned off in the same manner as described above, and the control operation of the main control circuit 20 is also stopped. Then, the subsequent measures are exactly the same as in the case of the output short circuit, and after the pause time DT elapses, the return operation by the soft start as described above is performed.

In this way, when a short circuit occurs in which the impedance on the load side does not become so low, the characteristics of _{output current I OUT} − output voltage V _{OUT as shown in FIG. 4B can be obtained.} Also in this case, unlike the F-shaped characteristic (FIG. 8) of the prior art, the output current I _OUT does not flow at all (and the output voltage V _OUT becomes zero) during the output stop period, so that the output transistor 14 generates heat. There is no load and no load heat generation. Further, even if the output transistor 14 is kept completely off, the return operation can be automatically performed after the lapse of the predetermined pause time DT to return to the normal output current I _OUT and output voltage V _OUT . Further, the feedback control system of the main control circuit 20 does not oscillate in the process of controlling the output current I _OUT and the output voltage V _OUT.

<< In case of temporary overload >>

FIG. 3C shows the state or waveform of each part when an overcurrent occurs due to a temporary overload. FIG. 4C shows the characteristics _{of the output current I OUT} − output voltage V _OUT in the case of FIG. 3C.

In this case, the overcurrent limiting circuit 36 first operates to limit the output current I _OUT to the vicinity of the limit _{value ILIM.} Then, when the feedback voltage FB _{falls below the voltage threshold value FB TH} , the cutoff / recovery circuit 40 also starts operating, and the charging voltage VCHG of the capacitor 74 rises. However, when the overcurrent this time is temporary due to overload, the output voltage V _OUT immediately recovers to the vicinity of the rated value V _LAT , and the feedback voltage FB _{becomes higher than the voltage threshold FB TH} , the timing (time point t). _{At a} ), the epitaxial transistor 72 of the monitoring switch is turned off, and the charging of the capacitor 74 is stopped before reaching the monitoring value VREF2.

In this way, in the cutoff / recovery circuit 40, the output DET of the comparator 78 keeps the L level state, and the (Q) output SET of the RS flip-flop 88 also keeps the L level state. As a result, the cutoff / recovery circuit 40 does not forcibly turn off the output transistor 14 and does not stop the control operation of the driver circuit 32, and the variable reference voltage SST of the reference voltage circuit 30 is set. It does not drop to the ground potential.

In this way, when an overcurrent occurs due to a temporary overload, the characteristics of _{output current I OUT} − output voltage V _{OUT as shown in FIG. 4C can be obtained.} Unlike the F-shaped characteristic (FIG. 8) of the prior art, the output current I _{OUT exceeding the limit value ILIM} is limited by the overcurrent limiting circuit 36, _{and even if the output voltage V OUT drops} once, it is immediately overloaded. When the state is released and the output voltage V _OUT becomes higher than the voltage threshold FB _TH , the cutoff / recovery circuit 40 forcibly turns off the output transistor 14. Further, even if the overcurrent due to the overload is prolonged and the cutoff / recovery circuit 40 turns off the output transistor 14, the soft start recovery operation as described above is automatically performed after the pause time DT elapses. It can be returned to the normal output state as soon as the load state is released.

If various short circuits occur as shown in FIGS. 3A and 3B and the short circuit state continues for a while even after the cutoff / recovery circuit 40 turns off the output transistor 14 for a while, as shown in FIG. _{The output current I OUT} that rises with a constant gradient due to the soft start exceeds the limit value _ILIM as it is, is limited by the overcurrent limiting circuit 36, and is cut off by the cutoff / recovery circuit 40. In this way, the return operation of the soft start is repeated several times or many times with the pause time DT in between.

In this case, the pause time DT is several hundred milliseconds, while the _{time FT when the output current I OUT} flows during the soft start is only a few millimeters. Therefore, from a macroscopic point of view, as shown in FIG. 6, the time during which the output current I _OUT flows intermittently due to the return operation of the soft start while the short-circuit state continues is only a moment, and the current consumption and heat generation are generated. Is so small that it can be ignored.
[Other Embodiments or Modifications]

Although preferred embodiments of the present invention have been described above, the above-described embodiments do not limit the present invention. Those skilled in the art can make various modifications and changes in specific embodiments without departing from the technical idea and scope of the present invention.

For example, in the above-described embodiment, the cutoff / recovery circuit 40 _{monitors the output current I OUT} via the internal current of the overcurrent limiting circuit 36, but directly outputs the output current I _{OUT without passing through the overcurrent limiting circuit 36.} It is also possible to have a configuration for monitoring.

In the above-described embodiment, when the cutoff / recovery circuit 40 completely turns off the output transistor 14 to stop the control operation of the main control circuit 20, the MOSFET transistor 70 is turned on and the gate of the output transistor 14 is set to the node N1. _{And the first cutoff operation that clamps to the VIN} level via the MOSFET transistor 70 in the on state, and the NMOS transistor 94 is turned on for the main control circuit 20, and the gate of the NMOS transistor 48 of the driver circuit 34 is grounded. It was used in combination with the second shutoff operation of clamping to the potential. As described above, the transition to the completely off state according to the present invention can be reliably performed at high speed by the double cutoff operation in which the output transistor 14 is turned off and the main control circuit 20 is stopped simultaneously and individually. However, although there is a certain decrease in high-speed certainty, it is possible to omit either the first blocking operation or the second blocking operation.

Further, in the above-described embodiment, the output current I _OUT and the feedback voltage FB are monitored as the output state of the output transistor 14, but it can be replaced by monitoring other parameters (for example, the input / output state of the driver circuit 34). Is.

The linear regulator of the present invention is manufactured as a semiconductor integrated circuit (IC) in which a MOS transistor is a main circuit element. In that case, it may be manufactured as a single power supply IC on a one-chip semiconductor substrate, or it may be manufactured in a composite power supply IC.

FIG. 7 shows an example of a composite power supply IC. This composite power supply IC mounts two switching regulators 100 and 102 and one linear regulator 104 on a one-chip semiconductor substrate. Here, the linear regulator 104 _{inputs the output voltage V OUT} 1 of the switching regulator 100 to the V _IN input terminal 10, and the _{voltage level is lower than the voltage V OUT 1 from the V OUT} output terminal 12, but the output voltage V has low ripple and low noise. Output _OUT3.

In such a composite power supply IC, if the linear regulator 104 generates a lot of heat, not only heat is transferred from the linear regulator 104 to the adjacent switching regulators 100 and 102, but also thermal distortion occurs in the semiconductor substrate, so that the switching regulators 100 and 102 are generated. May cause malfunction. Such a problem can be solved by applying the present invention to the linear regulator 104.

10 V _IN input terminal 12 V _OUT output terminal 14 Output transistor 20 Main control circuit 22 Feedback voltage generation circuit 28 (Fixed) Reference voltage source 30 (Variable) Reference voltage circuit 32 Error amplifier 34 Driver circuit 36 Overcurrent limit circuit 40 Break Return circuit 50, 52, 54 ProLiant transistor 58 NMOS transistor 70,72 ProLiant transistor 74 Condenser 78 Comparator 88 RS flip flop 90, 92, 94 NMOS transistor 96 ProLiant transistor 100 Timer circuit

Claims (11)

An output transistor provided between the input terminal that inputs the input voltage and the output terminal that outputs the output voltage,
A feedback voltage generation circuit that divides the output voltage to generate a feedback voltage,
A main control circuit that controls the voltage of the control terminal of the output transistor via the first node so that the output voltage matches or approximates the set value based on the feedback voltage.
The output current flowing through the output transistor is monitored, and when the output current exceeds a predetermined limit value, the voltage of the control terminal of the output transistor is controlled via the first node, and the output has a drooping characteristic. An overcurrent limiting circuit that limits the current and
The feedback voltage and the output current are monitored, and when the output current is limited by the overcurrent limiting circuit and the state where the feedback voltage is below a predetermined voltage threshold exceeds a certain limit, the said The output transistor is completely turned off to stop the control operation of the main control circuit, and after measuring a preset pause time, the output transistor is released from the off state to restart the control operation of the main control circuit. A linear regulator with a cutoff / recovery circuit. The overcurrent limiting circuit has a first transistor provided between the input terminal and the first node, and corresponds to the output current when the output current exceeds the limit value. A first internal current is passed through the first transistor to control the voltage of the control terminal of the output transistor.
The linear regulator according to claim 1. The overcurrent limiting circuit is
A second transistor in which a control terminal is connected to the first node and a second internal current corresponding to the output current flows,
A resistor that generates a voltage drop according to the second internal current,
A third transistor that inputs the voltage drop of the resistor as a control voltage and turns on when the output current exceeds the limit value, and
The linear according to claim 2, wherein the input terminal and the reference voltage terminal are connected in series with the third transistor and have the first transistor and a fourth transistor constituting the current mirror circuit. regulator. The cutoff / recovery circuit has a fifth transistor provided between the input terminal and the first node, the output current is limited by the overcurrent limiting circuit, and the feedback voltage is limited. The linear according to any one of claims 1 to 3, wherein when the state below a predetermined voltage threshold exceeds a certain limit, the fifth transistor is turned on and the output transistor is turned off. regulator. The cutoff / recovery circuit is
A sixth transistor that inputs the feedback voltage as a control voltage and turns on when the feedback voltage falls below a preset voltage threshold value.
When the output current exceeds the limit value, a seventh transistor that allows a third internal current corresponding to the output current to flow through the sixth transistor in the ON state, and a seventh transistor.
A capacitor charged by the third internal current and
A comparator that compares the charging voltage of the capacitor with a predetermined monitoring value and outputs a comparison result of binary logic that expresses the high-low relationship between the two.
It has a latch circuit that turns on the fifth transistor in response to the output of the comparator when the charging voltage of the capacitor exceeds the monitoring value.
When the feedback voltage becomes higher than the voltage threshold value before the charging voltage exceeds the monitoring value, the sixth transistor is turned off and charging of the capacitor by the third internal current is stopped. The capacitor discharges,
The linear regulator according to claim 4. The linear regulator according to claim 5, wherein the seventh transistor currently mirrors an internal current generated in the overcurrent limiting circuit in order to monitor the output current to generate the third internal current. .. The main control circuit
A reference voltage source that outputs a first reference voltage corresponding to the set value of the output voltage, and
A reference voltage circuit that outputs a second reference voltage that varies from the ground potential to the input voltage level by charging and discharging the capacitor,
An error amplifier that compares the feedback voltage with the lower of the first and second reference voltages to generate an error signal that represents a comparison error.
It has a driver circuit that outputs a voltage to be applied to the control terminal of the output transistor in response to the error signal.
When the cutoff / recovery circuit holds the second reference voltage in the reference voltage circuit at the ground potential and releases the off state of the output transistor while the output transistor is kept off. Gradually raises the second reference voltage from the ground potential to the input voltage level.
The linear regulator according to any one of claims 1 to 6. The driver circuit
A resistor provided between the input terminal and the first node,
The linear regulator according to claim 7, further comprising an eighth transistor connected between the first node and the reference potential terminal and input to the control terminal the error signal from the error amplifier. When the cutoff / recovery circuit releases the off state of the output transistor and restarts the control operation of the main control circuit, the feedback voltage is waited after the second reference voltage exceeds a predetermined reference voltage for determination. The linear regulator according to claim 7 or 8, wherein the monitoring of the output current is started. The linear regulator according to any one of claims 1 to 9, wherein the cutoff / return circuit has a timer circuit for measuring the pause time. An output transistor provided between the input terminal that inputs the input voltage and the output terminal that outputs the output voltage,
A feedback voltage generation circuit that divides the output voltage to generate a feedback voltage,
A main control circuit that controls the voltage of the control terminal of the output transistor so that the output voltage matches or approximates the set value based on the feedback voltage.
The output current flowing through the output transistor is monitored, and when the output current exceeds a predetermined limit value, the voltage of the control terminal of the output transistor is controlled in preference to the main control circuit, and the output current is controlled by the output current. An overcurrent limiting circuit that limits below the limit value, and
The output state of the output transistor is monitored, and when the output state exceeds a predetermined limit, the output transistor is forcibly turned off to stop the control operation of the main control circuit, and a preset pause time is set. A linear regulator having a cutoff / return circuit that releases the off state of the output transistor after timing and restarts the control operation of the main control circuit.

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