JP2021077282A - Timing constraint extraction device, timing constraint extraction method, and timing constraint extraction program - Google Patents

Abstract

To allow automatic extraction of a multi-timing path to reduce the man-hours required for determination of a multi-cycle path and prevent the occurrence of wrong determination.SOLUTION: A timing constraint extraction device determines a candidate for a multi-cycle path based on timing information on a signal input/output between a pair of flip-flops connected via a combinational circuit, extracts a logic cone connected to the flip-flop at the end point of the candidate for the multi-cycle path based on connection information on the circuit, extracts a signal state of a terminal of a circuit included in the extracted logic cone by using a logic simulation result, adds the flip-flop to the logic cone including the candidate for the multi-cycle path to create a circuit for verification of the multi-cycle path, provides the extracted signal state to the extracted circuit in the logic cone and the circuit for verification to execute equivalence verification, and determines and outputs the equivalent candidate for the multi-cycle path as a true multi-cycle path.SELECTED DRAWING: Figure 1

Description

The present invention relates to a timing constraint extraction device, a timing constraint extraction method, and a timing constraint extraction program.

A logic circuit that operates in synchronization with a clock may include a multi-cycle path that allows signal delay across multiple cycles. In this type of logic circuit, a method for determining whether or not a set multi-cycle path location is correct by giving an indefinite value of a specified number of cycles to a predetermined location and executing a logic simulation is disclosed. (Patent Document 1).

In order to efficiently verify the logic circuit including the multi-cycle path, it is preferable to automatically extract the multi-cycle path included in the logic circuit. However, conventionally, the designer or the like relies on the information at the time of circuit design to determine whether or not the path is a multi-cycle path. Therefore, when the logical scale becomes large, there is a problem that the man-hours required for the judgment increase and the risk of erroneous judgment as to whether or not it is a multi-cycle path increases.

The disclosed technology was developed in view of the above problems, and by making it possible to automatically extract the multi-timing path, the man-hours required for determining the multi-cycle path can be reduced and the occurrence of a judgment error can be prevented. The purpose is.

In order to solve the above technical problems, the timing constraint extraction device of one embodiment of the present invention is a timing constraint extraction device that extracts the timing constraints of the logic circuit mounted on the semiconductor integrated circuit, and in the logic circuit to be verified, Timing information indicating the timing of signals input / output between a pair of flipflops connected via a combination circuit is input from the timing information storage unit, and a candidate for a multi-cycle path is determined based on the input timing information. Logic that inputs the connection information of the multi-cycle path candidate determination means and the logic circuit to be verified from the connection information storage unit, and is connected to the flip flop at the end point of the multi-cycle path candidate based on the input connection information. The cone extraction means for extracting the cone and storing the connection information of the circuit included in the extracted logic cone in the logic cone storage unit and the logic simulation result of the logic circuit to be verified are input from the simulation result storage unit and input. Using the logic simulation result, the signal state extracting means of extracting the signal state of the terminal of the circuit included in the logic cone extracted by the cone extracting means and storing the extracted signal state in the signal state storage unit, and the signal state extracting means. Of the extracted logic cones, a flip flop is added to the logic cone containing the candidate for the multi-cycle path to create a multi-cycle path verification circuit, and the connection information of the created verification circuit is stored in the verification circuit storage unit. The logic cone storage unit and the verification circuit storage unit store the verification circuit creating means stored in the above, the connection information of the circuit included in the extracted logic cone, the connection information of the verification circuit, and the extracted signal state. Input from each unit and the signal state storage unit, give the extracted signal state to the input circuit connection information, execute equivalence verification, and select the equivalent multicycle path candidate as a true multicycle. It is characterized by having a determination means for determining a path and an output means for outputting timing constraint information indicating the timing constraint of the true multicycle path determined by the determination means.

By making it possible to automatically extract the multi-timing path, it is possible to reduce the man-hours required for determining the multi-cycle path and prevent the occurrence of a determination error.

It is a block diagram which shows an example of the timing constraint extraction apparatus which concerns on 1st Embodiment of this invention. It is a circuit diagram which shows an example of the logic circuit used for explaining the operation of the timing constraint extraction apparatus of FIG. It is a timing diagram which shows an example of the signal waveform of the input / output terminal of FF1 and FF2 which are the multi-cycle path candidates shown in FIG. It is a timing diagram which shows another example of the signal waveform of the input / output terminal of FF1 and FF2 which are the multi-cycle path candidates shown in FIG. It is a block diagram which shows an example of the multi-cycle path candidate determination part of FIG. It is explanatory drawing which shows an example of the timing report file of FIG. It is a timing diagram explaining an example of timing satisfaction (MET) / crack (VIOLATED) and margin (slack). It is a timing diagram explaining another example of timing satisfaction (MET) / crack (VIOLATED) and margin (slack). FIG. 5 is a timing diagram illustrating yet another example of timing satisfaction (MET) / cracking (VIOLATED) and margin (slack). It is a block diagram which shows an example of the peripheral logic cone circuit extraction part of FIG. It is explanatory drawing which shows an example of the logic cone extracted from the logic circuit of FIG. It is a block diagram which shows an example of the peripheral logic cone property extraction part of FIG. It is explanatory drawing which shows an example which extracts the property of the logic cone 1 of FIG. It is explanatory drawing which shows an example which extracts the property of the logic cone 3 of FIG. It is explanatory drawing which shows an example which determines whether a circuit operates normally in a multi-cycle path. It is a block diagram which shows an example of the circuit creation part for multi-cycle verification and the multi-cycle pass possibility determination part of FIG. It is explanatory drawing which shows an example of adding a flip-flop by the flip-flop addition part of FIG. It is explanatory drawing which shows an example of the equivalence verification by the equivalence verification apparatus of FIG. It is a block diagram which shows an example of the hardware composition of the information processing apparatus of FIG.

Hereinafter, embodiments will be described with reference to the drawings. In each drawing, the same components may be designated by the same reference numerals, and duplicate description may be omitted.

FIG. 1 is a block diagram showing an example of a timing constraint extraction device according to an embodiment of the present invention. The timing constraint extraction device 10 shown in FIG. 1 is realized by being mounted on an information processing device 100, which is a computer such as a server, together with a logic synthesis device 30, a timing analysis device 31, and a logic simulation device 32.

For example, the information processing device 100 realizes the functions of the timing constraint extraction device 10, the logic synthesis device 30, the timing analysis device 31, and the logic simulation device 32 by software. An information processing device that realizes the function of the timing constraint extraction device 10 may be provided separately from the information processing device that realizes the logic synthesis device 30, the timing analysis device 31, and the logic simulation device 32.

For example, in each function of the timing constraint extraction device 10, a processor such as a CPU (Central Processing Unit) mounted on the information processing device 100 executes a timing constraint extraction program to execute a timing constraint extraction method. It will be realized. The information processing device 100 may realize at least a part of the timing constraint extraction device 10 by hardware.

The logic synthesizer 30 performs logic synthesis using the clock information 20 and the RTL (Register Transfer Level) description 21 to generate a netlist 40 in which the logic circuit is shown at the gate level. The timing analysis device 31 executes timing analysis of the logic circuit using the timing information such as the clock information 20 and the netlist 40, and outputs the analysis result as the timing report file 41. The timing report file 41 is an example of timing information indicating the timing of signals input / output between a pair of flip-flops connected via a combinational circuit in the logic circuit to be verified. A storage device such as a hard disk device in which the timing report file 41 is stored is an example of a timing information storage unit.

The logic simulation device 32 executes the logic simulation using the RTL description 21 of the logic circuit and the test pattern 22, and outputs the logic simulation (SIM) result 42. A storage device such as a hard disk device in which the logical simulation (SIM) result 42 is stored is an example of a simulation result storage unit. Since the logic synthesis device 30, the timing analysis device 31, and the logic simulation device 32 are existing devices, detailed description thereof will be omitted.

The logic synthesis device 30, the timing analysis device 31, and the logic simulation device 32 are used when designing and verifying a logic circuit. Therefore, the timing constraint extraction device 10 extracts a multi-cycle path as described later by using information such as the netlist 40, the timing report file 41, and the logic simulation result 42 obtained at the time of designing and verifying the logic circuit. be able to.

The timing constraint extraction device 10 includes a multi-cycle path candidate determination unit 11, a peripheral logic cone circuit extraction unit 12, and a peripheral logic cone property extraction unit 13. Further, the timing constraint extraction device 10 includes a multi-cycle verification circuit creation unit 14, a multi-cycle pass passability determination unit 15, and a timing constraint output unit 16.

The multi-cycle path candidate determination unit 11 is an example of multi-cycle path candidate determination means, the peripheral logic cone circuit extraction unit 12 is an example of cone extraction means, and the peripheral logic cone property extraction unit 13 is a signal state extraction unit. This is an example. The multi-cycle verification circuit creation unit 14 is an example of the verification circuit creation means, the multi-cycle pass passability determination unit 15 is an example of the determination means, and the timing constraint output unit 16 is an example of the output means.

The timing constraint extraction device 10 inputs the netlist 40, the timing report file 41, and the logical simulation result 42, and generates the netlist 50, the property information 51, and the netlist 52. Then, the timing constraint extraction device 10 automatically generates the multi-cycle timing constraint 53 indicating the information of the path determined to be the true multi-timing path among the internally generated multi-timing path candidates without human intervention. Since the formats of various files such as the RTL description 21 and the netlists 40, 50, and 52 shown in FIG. 1 are all general, the description thereof is omitted here.

The multi-cycle path candidate determination unit 11 is a multi-cycle path candidate based on timing information indicating the timing of signals input / output between a pair of flip-flops connected via a combinational circuit in the logic circuit to be verified. Determine a multi-cycle path candidate.

The peripheral logic cone circuit extraction unit 12 inputs the netlist 40 of the logic circuit to be verified, extracts the logic cone connected to the flip-flop at the end point of the multicycle path candidate based on the netlist 40, and extracts the netlist 50. Output as.

The peripheral logic cone property extraction unit 13 inputs the logic simulation result 42 of the logic circuit to be verified, and uses the logic simulation result 42 to indicate the property information indicating the signal state of the terminal of the circuit included in the extracted logic cone. 51 is extracted.

The multi-cycle verification circuit creation unit 14 creates a multi-cycle path verification circuit by adding a flip-flop to the logic cone including the multi-cycle path candidate among the extracted logic cones, and outputs the multi-cycle verification circuit as a netlist 52.

The multi-cycle pass passability determination unit 15 inputs a netlist 50 indicating a circuit included in the extracted logic cone, a netlist 52 indicating a verification circuit to which a flip-flop is added, and property information 51 indicating the extracted property. To do. Then, the multi-cycle pass passability determination unit 15 gives properties to the circuits shown in the netlists 50 and 52, executes equivalence verification, and sets the multi-cycle path candidates determined to be equivalent as true multi-cycle paths. Extract.

The timing constraint output unit 16 outputs a multi-cycle timing constraint 53, which is a true multi-cycle path timing constraint determined by the multi-cycle pass passability determination unit 15. From the above, the timing constraint extraction device 10 can automatically extract the true multi-cycle path.

FIG. 2 is a circuit diagram showing an example of a logic circuit used for explaining the operation of the timing constraint extraction device 10 of FIG. The logic circuit shown in FIG. 2 is a part of the semiconductor integrated circuit to be verified.

Each flip-flop FF1, FF1_b, FF1_z, FF2, FF2_b, FF3 has a data input terminal D, a clock input terminal CK, a reset input terminal RB, and a data output terminal Q. Hereinafter, the flip-flop FF is also simply referred to as FF. Further, when the flip-flops FF1, FF1_b, FF1_z, FF2, FF2_b, and FF3 are described without distinction, they are also referred to as flip-flops FF or simply FF.

The flip-flop FF is reset while receiving the reset signal of the assert level at the reset input terminal RB, and outputs the reset level from the data output terminal Q. The flip flop FF takes in the data input to the data input terminal D in synchronization with the clock received by the clock input terminal CK while receiving the negate level reset signal at the reset input terminal RB, and stores the data until then. Is output from the data output terminal Q.

In the example shown in FIG. 2, the two-input oragate OR1 connects the two inputs to the outputs of FF1 and FF1_b, respectively, and connects the outputs to one input of the two-input and-gate AND1. Andgate AND1 connects the other input to the output of FF1_z and connects the output to the data input terminal D of FF2. Hereinafter, the or-gate OR1 and the and-gate AND1 are also simply referred to as OR1 and AND1.

From a timing point of view, one timing path is considered from a certain FF to an FF connected via a logic gate (combination circuit). In this example, the shaded FF1 to FF2 are considered as one timing path, and this path is used as a multi-cycle path candidate which is a candidate for the multi-cycle path to be discussed in the future.

3 and 4 are timing diagrams showing examples of signal waveforms of the input / output terminals of FF1 and FF2, which are the multi-cycle path candidates shown in FIG. FIG. 3 is an example of the most basic single cycle path. In the figure, FF1 / Q indicates the data output terminal Q of FF1, FF2 / D indicates the data input terminal D of FF2, and FF2 / Q indicates the data output terminal Q of FF2. The same notation is used for the timing diagrams shown below.

In the example shown in FIG. 3, the signal waveform of FF1 / Q transitions from logic 0 to logic 1 at the timing of the clock cycle (3) (FIG. 3 (a)). Then, the transition of the signal waveform of FF1 / Q from logic 0 to logic 1 propagates to FF2 / D during the clock cycle (3) (FIG. 3 (b)). Therefore, in the timing example shown in FIG. 3, the FF2 can take in the logic 1 supplied to the data input terminal D and output the logic 1 from the data output terminal Q at the timing of the clock cycle (4) (FIG. 3 (FIG. 3). c)). As described above, when the number of clock cycles required from the signal transition of FF1 / Q to the signal transition of FF2 / Q is "1", the path is called a single cycle path.

On the other hand, FIG. 4 shows an example of a multi-cycle path. The timing at which the signal waveform of FF1 / Q transitions from logic 0 to logic 1 is the clock cycle (3), as in FIG. 3 (FIG. 4 (a)). However, in FIG. 4, the transition of the signal waveform of FF1 / Q from logic 0 to logic 1 is propagated to FF2 / D after the start of the clock cycle (4) (FIG. 4 (b)). Therefore, the FF2 cannot capture the logic 1 supplied to the data input terminal D at the timing of the clock cycle (4), but captures it at the timing of the clock cycle (5) and outputs it from the data output terminal Q (FIG. 4 (FIG. 4). c)). In this way, when the number of clock cycles required from the signal transition of the data output terminal Q of FF1 to the signal transition of the data output terminal Q of FF2 is "2" or more, the path is called a multi-cycle path, and the number of cycles is ". The case of 2 "is called multi-cycle 2.

FIG. 5 is a block diagram showing an example of the multi-cycle path candidate determination unit 11 of FIG. The multi-cycle path candidate determination unit 11 includes a timing report file input unit 11a, a timing violation information extraction unit 11b, a cycle number calculation unit 11c, and a multi-cycle constraint determination unit 11d.

FIG. 6 is an explanatory diagram showing an example of the timing report file 41 of FIG. The timing report file 41 includes information such as the hierarchical instance name and terminal name of a pair of FFs that are the starting point and the ending point of the timing path, the cycle of one clock cycle, and the like. Further, the timing report file 41 shows information indicating whether the timing is satisfied in one clock cycle (MET) or whether the timing is broken (VIOLATED), and the margin of timing (slack) at that time. Information etc. are included.

In the example of FIG. 6, it is shown that the period of one clock cycle is 2 ns, the timing is broken, and the timing margin (slack) is -1.302 ns. Since the timing report file 41 is an existing file generated by the existing timing analysis device 31, detailed description thereof will be omitted. Timing satisfaction (MET) and cracking (VIOLATED) will be described with reference to FIGS. 7-9.

7, 8 and 9 are timing diagrams illustrating examples of timing satisfaction (MET) / cracking (VIOLATED) and margin (slack). 7 to 9 show an example in which the starting point of the timing path is FF1 and the ending point of the timing path is FF2.

FIG. 7 shows an example in which the timing is satisfied within one specified clock cycle (MET) and the timing margin (slack) is positive. Here, timing satisfaction (MET) indicates that a signal can be transmitted from FF1 / Q at the starting point to FF2 / D at the ending point within a specified clock cycle.

FIG. 8 shows an example in which the timing is broken within one specified clock cycle (VIOLATED) and the timing margin (slack) is negative. FIG. 8 shows an example corresponding to the timing report file 41 shown in FIG. Here, the timing break (VIOLATED) indicates that the signal cannot be transmitted from the starting point FF1 / Q to the ending point FF2 / D within one specified clock cycle.

FIG. 9 shows that when the timing of FIG. 8 is considered in two clock cycles, the timing is satisfied (MET) and the timing margin (slack) becomes positive. "Set_multicycle_path 2-from FF1 / CK -to FF2 / D" in FIG. 9 shows an example of a command indicating a constraint (multicycle constraint) of a multicycle path candidate determined by the multicycle constraint determination unit 11d. The command indicating the multi-cycle constraint is output from the multi-cycle constraint determination unit 11d.

Returning to FIG. 5, the timing report file input unit 11a acquires the information contained in the timing report file 41 (FIG. 6), and outputs the acquired information to the timing violation information extraction unit 11b. The timing violation information extraction unit 11b analyzes the information of the received timing report file 41 and outputs the information of the path where the timing is broken (VIOLATED) to the cycle number calculation unit 11c.

The cycle number calculation unit 11c acquires the information of the timing report file 41 of FIG. 6, for example, the cycle of one clock cycle is 2 ns, the timing is broken (VIOLATED), and the timing margin (slack) is -1.302 ns. To do. That is, the information indicating the timing relationship shown in FIG. 8 is acquired. Then, the cycle number calculation unit 11c executes the calculation, and as shown in FIG. 9, if there are two clock cycles, the timing margin (slack) becomes plus 0.698ns, and the timing can be satisfied (MET). judge. The cycle number calculation unit 11c outputs the determination result obtained by the calculation (MET is performed in the case of two clock cycles) to the multi-cycle constraint determination unit 11d.

The multi-cycle constraint determination unit 11d determines the constraint of the multi-cycle path candidate based on the determination result by the cycle number calculation unit 11c. In the timing report file 41 shown in FIG. 6, the hierarchical instance name of the flip-flop that is the starting point of the timing path is FF1 and the terminal name is CK, and the hierarchical instance name of the flip-flop that is the ending point is FF2 and the terminal name is D. Is.

The multi-cycle constraint determination unit 11d issues a command indicating the multi-cycle constraint "set_multicycle_path 2-from FF1 / CK -to FF2 / D" from the information in the timing report file 41 and the information calculated by the cycle number calculation unit 11c. create. Here, the information calculated by the cycle number calculation unit 11c is a determination result that "MET is performed if there are two clock cycles".

For example, the command "set_multicycle_path" is an SDC (Synopsys Design Constraints) command and is a general format used when specifying timing constraints, so the explanation is omitted. Note that "set_multicycle_path n" (n is an integer of 2 or more) indicates multicycle n, and the above-mentioned multicycle constraint "set_multicycle_path 2 -from FF1 / CK -to FF2 / D" indicates multicycle 2.

Information such as commands indicating multi-cycle constraints is not limited to SDC, and may be other commands or formats. In this way, the multi-cycle path candidate determination unit 11 can automatically determine the multi-cycle path candidate from the input timing report file 41, and can output the determined multi-cycle path candidate as a multi-cycle constraint. it can. Therefore, as compared with the case where the designer or the like manually generates the multi-cycle path candidate, the man-hours for creation can be reduced, and the occurrence of creation error and description error can be prevented.

FIG. 10 is a block diagram showing an example of the peripheral logic cone circuit extraction unit 12 of FIG. The peripheral logic cone circuit extraction unit 12 includes a netlist input unit 12a, a logic cone 1 extraction unit 12b, a logic cone 2 extraction unit 12c, a logic cone 3 extraction unit 12d, and a netlist output unit 12e. The logic cone 1 extraction unit 12b is an example of the first extraction means, the logic cone 2 extraction unit 12c is an example of the second extraction means, and the logic cone 3 extraction unit 12d is an example of the third extraction means. This is an example. Before explaining the function of the peripheral logic cone circuit extraction unit 12, the logic cone will be described.

FIG. 11 is an explanatory diagram showing an example of a logic cone extracted from the logic circuit of FIG. A logic cone is a concept used in a CAD (Computer Aided Design) tool that supports the design of semiconductor integrated circuits, and indicates a set of combinational circuits.

For example, when the logical value of the signal output from the data output terminal Q of one FF (starting point) of interest in the circuit changes, the change in the logical value is sequentially propagated through the logical cell on the subsequent stage side. The signal is distributed. As the signal is distributed, the influence of the change in the logical value of the data output terminal Q of interest spreads to the subsequent gate circuit, and is transmitted to the data input terminals D of a predetermined number of FFs (end points) in the next stage. Here, a virtual conical logical structure including a combinational circuit between the start point FF and a predetermined number of end point FFs is called a logic cone. Further, a virtual conical logical structure including a circuit on the path that has the data input terminal D of the FF of interest as the apex and goes back toward the FF on the previous stage side is also called a logic cone.

In the example shown in FIG. 11, attention is paid to FF2 at the end point in the multi-cycle path candidates from FF1 at the start point to FF2 at the end point. Then, the logic cone 1 is formed by the logic circuit included in the path when the circuit is traced back from the data input terminal D of FF2 toward the data output terminals Q of FF1, FF1_b, ..., FF1_z in the previous stage. To.

Further, the logic cone 2 is formed by the logic circuit included in the path from the data output terminal Q of FF2 to the data input terminal D of the next FF3, FF3_b, ..., FF3_z located on the rear stage side. The logic cone 1 is an example of a first logic cone, and the logic cone 2 is an example of a second logic cone.

Further, as another logic cone related to FF2, the path when the circuit is traced back from the data input terminal D of FF3 to the data input terminal D of FF2_b, ..., FF2 located one stage before. The logic cone 3 is formed by the included logic circuit. The logic cone 3 is an example of a third logic cone. Since the technology for extracting the logic circuit included in the logic cone is an existing technology used in timing analysis tools, equivalence verification tools, etc., the explanation of the specific extraction method is omitted.

Returning to FIG. 10, the netlist input unit 12a inputs the netlist 40 showing the information of the entire logic circuit to be verified. The netlist 40 is an example of connection information of a logic circuit, and a storage device such as a hard disk device in which the netlist 40 is stored is an example of a connection information storage unit. The logic cone 1 extraction unit 12b, the logic cone 2 extraction unit 12c, and the logic cone 3 extraction unit 12d are based on the netlist 40 and the FFs of the start points and end points of the multi-cycle path candidates determined by the multi-cycle constraint determination unit 11d. , Works as follows.

For example, the logic cone 1 extraction unit 12b pays attention to the end point FF2 of the multi-cycle path candidate, starts from the data input terminal D of the end point FF2, and traces back until the circuit reaches the start point FF1. The circuit included in 1 is extracted. The logic cone 2 extraction unit 12c traces the circuit from the data output terminal Q of the end point FF2 until it reaches the subsequent FF3, FF3_b, ..., FF3_z, and extracts the circuit included in the logic cone 2 of FIG. ..

The logic cone 3 extraction unit 12d traces back from the data input terminal D of FF3, which is one of the FFs reached by the logic cone 2 extraction unit 12c, to the FF in the previous stage, and goes back to the logic of FIG. The circuit contained in the cone 3 is extracted. Although not shown in FIG. 11 in consideration of the legibility of the figure, the logic cone 3 extraction unit 12d is used not only for FF3 but also for all FFs such as FF3_b and FF3_z reached by the logic cone 2 extraction unit 12c. And perform the same extraction. Therefore, a plurality of logic cones 3 are actually extracted.

Then, the netlist output unit 12e of FIG. 10 outputs the circuit group extracted by the logic cone 1 extraction unit 12b, the logic cone 2 extraction unit 12c, and the logic cone 3 extraction unit 12d as the netlist 50. In this way, the peripheral logic cone circuit extraction unit 12 extracts the circuits included in the logic cone 1, the logic cone 2, and the plurality of logic cones 3, and regards this as a circuit related to the multi-cycle path candidate in the netlist. Generate 50. The netlist 50 is an example of connection information of circuits included in the logic cone 1, the logic cone 2, and the plurality of logic cones 3, and a storage device such as a hard disk device in which the netlist 50 is stored is a logic cone storage unit. This is an example.

FIG. 12 is a block diagram showing an example of the peripheral logic cone property extraction unit 13 of FIG. The peripheral logic cone property extraction unit 13 has a logic simulation (SIM) result input unit 13a and a multi-cycle path transition timing identification unit 13b. Further, the peripheral logic cone property extraction unit 13 includes a logic cone 1 input terminal property extraction unit 13c, a logic cone 3 input terminal property extraction unit 13d, and a property information output unit 13e.

Properties generally mean attributes, but here they are used to mean design specifications. The property is an example of the signal state of the terminal of the logic circuit to be verified. For example, when the node A on the circuit is logic 1, the node B is logic 0. A storage device such as a hard disk device in which the property information 51 is stored is an example of a signal state storage unit.

The SIM result input unit 13a inputs the SIM result 42 of the logic simulation device 32 (FIG. 1). The SIM result 42 may be any one in which the output waveform of each flip-flop of the entire circuit to be verified is recorded.

The multi-cycle path transition timing specifying unit 13b searches for, for example, the output waveform of FF1 at the starting point and the output waveform of FF2 at the ending point using the multi-cycle constraint determined by the multi-cycle path candidate determining unit 11 and the SIM result 42. To do. Then, the multi-cycle path transition timing specifying unit 13b obtains the number of clock cycles (clock cycle numbers) whose logical values have changed between the starting point FF1 / Q and the ending point FF2 / Q.

FIG. 13 is an explanatory diagram showing an example of extracting the property of the logic cone 1 of FIG. The upper waveform (A) of FIG. 13 shows an example in which the timing is MET in one clock cycle, and the lower waveform (B) in FIG. 13 shows an example in which the timing is MET in two clock cycles.

Whether the operating waveform becomes the waveform (A) or the waveform (B) is determined by the propagation delay time and the wiring delay of each element of the actual logic circuit. However, the RTL simulation does not have information on the cells in the timing path and the delay time of each cell. Therefore, the waveform showing the SIM result 42 of the logic simulation executed by the logic simulation device 32 of FIG. 1 using the RTL description 21 and the test pattern 22 is the waveform (A). Since the waveform (A) is recorded in the SIM result 42, the FF1 / Q transitions from logic 0 to logic 1 in synchronization with the clock cycle (3), and the FF2 / Q synchronizes with the clock cycle (4). It can be obtained from the waveform search result that the transition from logic 0 to logic 1 is performed.

The multi-cycle path transition timing specifying unit 13b shown in FIG. 12 includes a clock cycle (2) before the starting point FF1 / Q value changes and two clock cycles (3) after the FF1 / Q value changes. ) And (4) are specified as clock cycles of interest. For example, the multi-cycle path transition timing specifying unit 13b notifies the logic cone 1 input terminal property extraction unit 13c and the logic cone 3 input terminal property extraction unit 13d of the specified clock cycle separately for the logic cones 1 and 3.

The logic cone 1 input terminal property extraction unit 13c uses the netlist 50 to extract the values at each clock cycle (2), (3), and (4) of the terminals of the circuit included in the logic cone 1. White circle in FIG. 13). For example, the terminals of the circuit included in the logic cone 1 are FF1 / Q, FF1_b / Q, FF1_z / Q, and the like. The difference between the waveforms (A) and (B) in FIG. 13 is the timing (clock cycle (3) or clock cycle (4)) at which FF2 / D transitions from logic 0 to logic 1, and each clock cycle (2). , (3), (4) have the same properties extracted in the waveforms (A) and (B).

The difference in propagation time to FF2 / D also affects the waveform of FF2 / Q. That is, in the waveform (A), the value of FF2 / Q becomes logic 1 during the two clock cycles of the clock cycles (4) and (5) (FIG. 13 (a)). In the waveform (B), the value of FF2 / Q becomes logic 1 for only one clock cycle of the clock cycle (5) (FIG. 13 (b)). As described above, in the multi-cycle 2, either the waveform (A) or the waveform (B) is obtained depending on the difference in the propagation delay time of the signal until the input of the FF2 at the end point. If the logic circuit operates normally regardless of the waveforms (A) and (B), the timing path can be set to multicycle 2.

FIG. 14 is an explanatory diagram showing an example of extracting the property of the logic cone 3 of FIG. The upper waveform (A) of FIG. 14 shows the subsequent operation when the timing is MET in one clock cycle in the waveform (A) of FIG. The lower waveform (B) of FIG. 14 shows the subsequent operation when the timing is MET in two clock cycles in the waveform (B) of FIG.

The logic cone 3 input terminal property extraction unit 13d of FIG. 12 uses the netlist 50 to extract each terminal of the logic cone 3 (FIG. 11), that is, a logical value such as FF2_b / Q (white circle in FIG. 14). .. As described above, the logic cone 3 is not limited to the one shown in FIG. Therefore, the logic cone 3 input terminal property extraction unit 13d extracts the values of the terminals of the circuits included in all the logic cones 3 not shown in FIG.

Further, the clock cycles of interest are clock cycles (3), (4), and (5) that are one cycle ahead of the case of the logic cone 1 input terminal property extraction unit 13c. This is because the logic cone 3 is a circuit one clock cycle later than the logic cone 1.

By the operation of the logic cone 1 input terminal property extraction unit 13c and the logic cone 3 input terminal property extraction unit 13d, the properties of the predetermined clock cycles of all the terminals of the circuit obtained by the peripheral logic cone circuit extraction unit 12 could be extracted. It will be. Then, the property information output unit 13e of FIG. 12 outputs the property information 51 including the extracted plurality of properties. The format of the property information 51 is not limited as long as it includes property information such as which terminal has what logical value in which clock cycle. For example, the property information 51 may be created by using a language (for example, System Verilog Assertion) supported by the equivalence verification device 15a (FIG. 16) used by the multi-cycle pass passability determination unit 15.

In this way, the peripheral logic cone property extraction unit 13 can extract the logic values of all the terminals of the logic cone 1 and the logic cone 3 in the predetermined clock cycle as properties from the SIM result 42.

FIG. 15 is an explanatory diagram showing an example of determining whether or not the circuit operates normally in the multi-cycle path. The waveform shown in FIG. 15 is the same as the waveform shown in FIG.

When determining whether the circuit operates normally in the multi-cycle path, first pay attention to the waveform of FF3 / Q, which is one output terminal of the logic cone 2 shown in FIG. Then, the waveforms (A) of the clock cycles (4), (5), and (6) that are affected by the clock cycles (3), (4), and (5) extracted by the logic cone 3 input terminal property extraction unit 13d. Compare with waveform (B). In FIG. 15, although the waveform (A) and the waveform (B) of the FF2 / Q at the end point of the multi-cycle path are different, in the subsequent FF3 / Q, the waveform (A) and the waveform (B) are different. The logic indicated by the black circles is all the same. That is, the logic circuit to be verified operates normally regardless of whether it is MET in one clock cycle or MET in two clock cycles.

In other words, when the circuit operates normally in the multi-cycle path, the difference is absorbed in the latter stage of the circuit regardless of whether it is multi-cycle 2 (when MET is performed in 1 cycle) or multi-cycle 2 (when MET is performed in 2 cycles). Will have the same waveform. Therefore, by proving that the waveforms (logical values) in the subsequent stage of the circuit are the same, it can be determined that the circuit operates normally in the multi-cycle path, and the true multi-cycle path can be extracted.

Here, the timing constraint extraction device 10 proves that the circuit operates normally in the multi-cycle path by using the equivalence verification technique instead of the logic simulation. For example, the equivalence verification device 15a described with reference to FIG. 16 has an equivalence between a circuit that operates with the waveform (A) reproduced from the netlist 50 and a circuit that operates with the waveform (B) reproduced from the netlist 52. Perform verification. Here, as described above, the netlist 50 is created by the peripheral logic cone circuit extraction unit 12, and the netlist 52 is created by the multi-cycle verification circuit creation unit 14 described with reference to FIG.

FIG. 16 is a block diagram showing an example of the multi-cycle verification circuit creation unit 14 and the multi-cycle pass availability determination unit 15 of FIG. The multi-cycle verification circuit creation unit 14 includes a flip-flop addition unit 14a and a netlist output unit 14b. The multi-cycle pass passability determination unit 15 includes an equivalence verification device 15a and a multi-cycle passability determination unit 15b.

The flip-flop addition unit 14a adds a predetermined number of flip-flops in order to change the path of the multi-cycle path candidate from a single-cycle path to a multi-cycle path. The number of flip-flops added by the flip-flop addition unit 14a is automatically determined from the multi-cycle constraint (number of multi-cycles) determined by the multi-cycle path candidate determination unit 11.

For example, in the case of multi-cycle 2, one flip-flop is added, and in the case of multi-cycle 3, two flip-flops are added. That is, in multicycle n (n is an integer of 2 or more), n-1 flip-flops are added. The netlist output unit 14b outputs the netlist 52 to which a predetermined number of flip-flops have been added by the flip-flop addition unit 14a. The netlist 52 to which a predetermined number of flip-flops are added by the flip-flop addition unit 14a is an example of connection information of a circuit for verifying a multi-cycle path. A storage device such as a hard disk device in which the netlist 52 is stored is an example of a verification circuit storage unit.

FIG. 17 is an explanatory diagram showing an example in which a flip-flop is added by the flip-flop addition unit 14a of FIG. In the circuit shown in FIG. 17, the original circuit before adding the flip-flop FF1_add is a circuit including the multi-cycle path candidate of the multi-cycle 2 shown in FIG.

As shown in FIG. 17, the flip-flop addition unit 14a adds one FF1_add to the output of FF1 which is the starting point of the multi-cycle path candidate. By adding one FF1_add, two clock cycles are required to propagate the signal from FF1 to FF2. That is, by adding FF1_add, a circuit capable of simulating the waveform (B) shown in FIGS. 13 and 14 has been created. In this way, the multi-cycle verification circuit creation unit 14 simulates the timing at the time of multi-cycle by adding a circuit in which a number of FFs one less than the assumed number of multi-cycles is added immediately after the FF as the starting point. It can be created as a circuit that reproduces.

Returning to FIG. 16, the equivalence verification device 15a of the multi-cycle pass passability determination unit 15 uses the netlist 52 of the circuit to which the flip-flop is added and the netlist 50 of the circuit corresponding to the single pass. Perform equivalence verification of two circuits. At this time, the property information 51 created by the peripheral logic cone property extraction unit 13 is used as a constraint given to the input terminals of the two circuits.

For example, the equivalence verification device 15a may be a commercially available sequential equivalence verification tool. There are two types of equivalence verification tools: one that targets a combinational circuit divided by a flip-flop, and one called sequential equivalence verification that can verify not only the combinational circuit but also the sequential circuit. Here, the combinational circuit is a circuit composed of logic cells such as OR gates and AND gates to which clocks are not supplied, and the sequential circuit is a circuit composed of logic cells such as flip-flops to which clocks are supplied. ..

FIG. 18 is an explanatory diagram showing an example of equivalence verification by the equivalence verification device 15a of FIG. Since the two circuits verified by the equivalence verification device 15a differ in the number of flip-flop stages, it is necessary to perform sequential equivalence verification that can be verified including the flip-flops.

The equivalence verification device 15a applies the same constraint to the input terminals of the two verification circuits shown in the netlists 50 and 52 by using the property information 51, and sets an output value which is a logical value of the signal output from the output terminal. Compare. Then, the equivalence verification device 15a outputs a report indicating that the two circuits are equivalent when the logic of the output value is always the same, and when there is a difference in the logic of the output value, the equivalence verification device 15a is unequal. Output a report showing. That is, the equivalence verification device 15a regards the circuits included in the logic cone 1 and the logic cone 3 as circuits related to the candidates of the multi-cycle path and uses them in the equivalence verification.

Here, by creating a circuit in which the number of flip-flops corresponding to the number of multi-cycles indicated by the multi-cycle constraint determined by the multi-cycle constraint determination unit 11d is added, the feasibility of the multi-cycle path is determined by the equivalence verification technique. be able to. Since equivalence verification can be performed by a static method without using a test pattern, the verification time can be shortened as compared with a logical simulation in which verification is dynamically executed using a test pattern.

Further, the netlists 50 and 52 used by the equivalence verification device 15a for verification show the connection of the circuits included in the logic cone shown in FIG. 11, that is, the connection of the circuits related to the multi-cycle. By extracting the circuits related to the multi-cycle path and executing the equivalence verification, the verification time can be shortened as compared with the case of executing the equivalence verification including the circuits not related to the multi-cycle path.

When the comparison result shown in the report output from the equivalence verification device 15a shows equivalence, the multi-cycle possibility determination unit 15b shown in FIG. 16 sets the multi-cycle path candidate to be verified as a true multi-cycle. to decide. Further, the multi-cycle possibility determination unit 15b determines that the multi-cycle path candidate to be verified is a single path when the comparison result shown in the report output from the equivalence verification device 15a shows inequality. Then, the multi-cycle possibility determination unit 15b outputs information indicating a timing path determined to be a true multi-cycle path among the multi-cycle path candidates to the timing constraint output unit 16 shown in FIG.

The timing constraint output unit 16 outputs the multi-cycle constraint determined by the multi-cycle constraint determination unit 11d as the multi-cycle timing constraint 53 only for the timing path determined by the multi-cycle possibility determination unit 15b as the multi-cycle path. Then, the operation of automatically extracting the multi-timing path by the timing constraint extraction device 10 is completed. The multi-cycle timing constraint 53 is an example of timing constraint information indicating a true multi-cycle path timing constraint.

FIG. 19 is a block diagram showing an example of the hardware configuration of the information processing apparatus 100 of FIG. The information processing device 100 includes a CPU 101, a ROM (Read Only Memory) 102, a RAM (Random Access Memory) 103, and an external storage device 104. Further, the information processing device 100 has an input interface unit 105, an output interface unit 106, an input / output interface unit 107, and a communication interface unit 108. For example, the CPU 101, the ROM 102, the RAM 103, the external storage device 104, the input interface unit 105, the output interface unit 106, the input / output interface unit 107, and the communication interface unit 108 are connected to each other via the bus BUS.

The CPU 101 executes various programs such as an OS and an application, and controls the overall operation of the information processing apparatus 100. The ROM 102 holds a basic program, various parameters, and the like for enabling the CPU 101 to execute various programs. The RAM 103 stores various programs executed by the CPU 101 and data used in the programs.

The external storage device 104 is an HDD (Hard Disk Drive), an SSD (Solid State Drive), or the like, and stores various programs to be expanded in the RAM 103. The various programs include a timing constraint extraction program.

An input device 110 such as a keyboard, mouse, or tablet that receives input from an operator or the like operating the information processing device 100 is connected to the input interface unit 105. An output device 120 such as a display device or a printer that displays a display screen or the like generated by various programs executed by the CPU 101 is connected to the output interface unit 106.

A recording medium 130 such as a USB (Universal Serial Bus) memory is connected to the input / output interface unit 107. For example, various programs such as a timing constraint extraction program may be stored in the recording medium 130. In this case, the program is transferred from the recording medium 130 to the RAM 103 via the input / output interface unit 107. The recording medium 130 may be a CD-ROM, a DVD (Digital Versatile Disc: registered trademark), or the like. In this case, the input / output interface unit 107 has an interface corresponding to the recording medium 130 to be connected. The communication interface unit 108 connects the information processing device 100 to, for example, a network. The recording medium 130 may be connected to the bus via the input / output interface.

As described above, in this embodiment, the timing constraint extraction device 10 can automatically extract the true multi-cycle path. As a result, the man-hours required for determining the multi-cycle path can be reduced, and the occurrence of a determination error can be prevented.

For example, the multi-cycle path candidate determination unit 11 can automatically determine the multi-cycle path candidate from the input timing report file 41, and can output the determined multi-cycle path candidate as a multi-cycle constraint. Therefore, as compared with the case where the designer or the like manually generates the multi-cycle path candidate, the man-hours for creation can be reduced, and the occurrence of creation error and description error can be prevented.

The peripheral logic cone property extraction unit 13 can extract the logic values of all the terminals of the logic cone 1 and the logic cone 3 in a predetermined clock cycle as properties from the SIM result 42. The multi-cycle verification circuit creation unit 14 is a circuit that simulates the timing of multi-cycles by adding one less FF than the assumed number of multi-cycles immediately after the FF that is the starting point. Can be created as.

By creating a circuit in which the number of flip-flops corresponding to the number of multi-cycles indicated by the multi-cycle constraint determined by the multi-cycle constraint determination unit 11d is added, it is possible to judge whether or not the multi-cycle pass is possible by the equivalence verification technique. .. Since equivalence verification can be performed by a static method without using a test pattern, the verification time can be shortened as compared with a logical simulation in which verification is dynamically executed using a test pattern.

Further, the netlists 50 and 52 used by the equivalence verification device 15a for verification show the connection of the circuits included in the logic cone shown in FIG. 11, that is, the connection of the circuits related to the multi-cycle. By extracting the circuits related to the multi-cycle path and executing the equivalence verification, the verification time can be shortened as compared with the case of executing the equivalence verification including the circuits not related to the multi-cycle path.

In the above-described embodiment, an example of automatically extracting a multi-timing path for a relatively simple logic circuit shown in FIG. 2 has been described in consideration of ease of understanding. However, in reality, true multi-timing paths are comprehensively extracted for all logic circuits mounted on semiconductor integrated circuits.

Although the present invention has been described above based on each embodiment, the present invention is not limited to the requirements shown in the above embodiments. With respect to these points, the gist of the present invention can be changed without impairing the gist of the present invention, and can be appropriately determined according to the application form thereof.

10 Timing constraint extraction device 11 Multi-cycle path candidate determination unit 11a Timing report file input unit 11b Timing biolation information extraction unit 11c Cycle number calculation unit 11d Multi-cycle constraint determination unit 12 Peripheral logic cone circuit extraction unit 12a Netlist input unit 12b Logic Cone 1 extraction unit 12c Logic cone 2 extraction unit 12d Logic cone 3 extraction unit 12e Netlist output unit 13 Peripheral logic cone property extraction unit 13a SIM result input unit 13b Multi-cycle path transition timing specification unit 13c Logic cone 1 input terminal property extraction unit 13d Logic cone 3 Input terminal Property extraction unit 13e Property information output unit 14 Multi-cycle verification circuit creation unit 14a Flip flop addition unit 14b Netlist output unit 15 Multi-cycle pass passability judgment unit 15a Equivalence verification device 15b Multi-cycle passability judgment unit 16 Timing constraint output unit 20 Clock information 21 RTL description 22 Test pattern 30 Logic synthesizer 31 Timing analyzer 32 Logic simulation device 40 Netlist 41 Timing report file 42 Logic simulation result 50 Netlist 51 Property information 52 Netlist 53 Multi-cycle timing Constraint 100 Information processing device

Japanese Patent No. 5040758

Claims (5)

It is a timing constraint extraction device that extracts the timing constraints of logic circuits mounted on semiconductor integrated circuits.
In the logic circuit to be verified, timing information indicating the timing of signals input / output between a pair of flip-flops connected via a combination circuit is input from the timing information storage unit, and multi is performed based on the input timing information. Multi-cycle path candidate determination means for determining cycle path candidates,
The connection information of the logic circuit to be verified is input from the connection information storage unit, and the logic cone connected to the flip-flop at the end point of the candidate of the multicycle path is extracted based on the input connection information, and the extracted logic is extracted. A cone extraction means that stores the connection information of the circuit contained in the cone in the logic cone storage unit,
The logic simulation result of the logic circuit to be verified is input from the simulation result storage unit, and the input logic simulation result is used to extract the signal state of the terminal of the circuit included in the logic cone extracted by the cone extraction means. Then, a signal state extraction means for storing the extracted signal state in the signal state storage unit, and
Of the extracted logic cones, a flip-flop is added to the logic cone containing the candidate for the multi-cycle path to create a multi-cycle path verification circuit, and the connection information of the created verification circuit is stored in the verification circuit storage. Verification circuit creation means stored in the section,
The connection information of the circuit included in the extracted logic cone, the connection information of the verification circuit, and the extracted signal state are obtained from the logic cone storage unit, the verification circuit storage unit, and the signal state storage unit, respectively. The input is input, the extracted signal state is given to the connection information of the input circuit, the equivalence verification is executed, and the equivalent multi-cycle path candidate is determined to be a true multi-cycle path.
An output means for outputting timing constraint information indicating the timing constraint of the true multi-cycle path determined by the determination means, and an output means for outputting the timing constraint information.
A timing constraint extraction device characterized by having. The corn extraction means
A first extraction means for extracting a first logic cone including a circuit when the circuit is traced back from the flip-flop at the end point to the flip-flop at the start point.
A second extraction means for extracting a second logic cone including a circuit to the next flip-flop located on the rear side of the end point flip-flop, and a second extraction means.
A third logic cone that includes a circuit that traces back from the next flip-flop located on the rear stage side to the flip-flop located one stage before, and extracts a third logic cone connected to the flip-flop at the end point. Has an extraction means,
The signal state extracting means extracts the signal state of the terminals of the circuit included in the first logic cone and the third logic cone, and extracts the signal state.
The first aspect of the present invention is described in claim 1, wherein the first logic cone and the third logic cone are regarded as circuits related to the candidate of the multi-cycle path and used in the equivalence verification. Timing constraint extractor. The verification circuit creating means outputs a flip-flop at the start point of the multi-cycle path candidate by one less than the number of multi-cycles of the multi-cycle path candidate determined by the multi-cycle path candidate determining means. The timing constraint extraction device according to claim 1 or 2, wherein the verification circuit is created by adding a flip-flop. It is a timing constraint extraction method executed by a timing constraint extraction device that extracts timing constraints of logic circuits mounted on semiconductor integrated circuits.
In the logic circuit to be verified, timing information indicating the timing of signals input / output between a pair of flip-flops connected via a combinational circuit is input from the timing information storage unit, and multi is performed based on the input timing information. Determine cycle path candidates and
The connection information of the logic circuit to be verified is input from the connection information storage unit, and the logic cone connected to the flip-flop at the end point of the candidate of the multicycle path is extracted based on the input connection information, and the extracted logic is extracted. The connection information of the circuit included in the cone is stored in the logic cone storage,
The logic simulation result of the logic circuit to be verified is input from the simulation result storage unit, and the signal state of the terminal of the circuit included in the extracted logic cone is extracted and extracted by using the input logic simulation result. The signal state is stored in the signal state storage unit,
Of the extracted logic cones, a flip-flop is added to the logic cone containing the candidate for the multi-cycle path to create a multi-cycle path verification circuit, and the connection information of the created verification circuit is stored in the verification circuit memory. Store in the department,
The connection information of the circuit included in the extracted logic cone, the connection information of the verification circuit, and the extracted signal state are obtained from the logic cone storage unit, the verification circuit storage unit, and the signal state storage unit, respectively. The input is input, the extracted signal state is given to the connection information of the input circuit, the equivalence verification is performed, and the equivalent multi-cycle path candidate is determined to be a true multi-cycle path.
A timing constraint extraction method characterized by outputting timing constraint information indicating the determined timing constraint of the true multi-cycle path. A timing constraint extraction program executed by a timing constraint extraction device that extracts timing constraints of logic circuits mounted on semiconductor integrated circuits.
In the logic circuit to be verified, timing information indicating the timing of signals input / output between a pair of flip-flops connected via a combinational circuit is input from the timing information storage unit, and multi is performed based on the input timing information. Determine cycle path candidates and
The connection information of the logic circuit to be verified is input from the connection information storage unit, and the logic cone connected to the flip-flop at the end point of the candidate of the multicycle path is extracted based on the input connection information, and the extracted logic is extracted. The connection information of the circuit included in the cone is stored in the logic cone storage,
The logic simulation result of the logic circuit to be verified is input from the simulation result storage unit, and the signal state of the terminal of the circuit included in the extracted logic cone is extracted and extracted by using the input logic simulation result. The signal state is stored in the signal state storage unit,
Of the extracted logic cones, a flip-flop is added to the logic cone containing the candidate for the multi-cycle path to create a multi-cycle path verification circuit, and the connection information of the created verification circuit is stored in the verification circuit memory. Store in the department,
The connection information of the circuit included in the extracted logic cone, the connection information of the verification circuit, and the extracted signal state are obtained from the logic cone storage unit, the verification circuit storage unit, and the signal state storage unit, respectively. The input is input, the extracted signal state is given to the connection information of the input circuit, the equivalence verification is performed, and the equivalent multi-cycle path candidate is determined to be a true multi-cycle path.
A timing constraint extraction program characterized by outputting timing constraint information indicating the determined timing constraint of the true multi-cycle path.

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