JP2021068968A - Transmission system, transmission device, and clock synchronization method - Google Patents

Abstract

To provide a transmission system, a transmission device, and a clock synchronization method, with which it is possible to enhance performance of clock frequency synchronization between transmission devices.SOLUTION: A transmission system comprises: a first transmission device that generates a packet from a data signal and sends the packet; and a second transmission device that reproduces the data signal from the packet. The first transmission device extracts an input data clock signal from the data signal, counts a first count value in synchronization with the input data clock signal, measures a first frequency of the input data clock signal by counting a second count value in synchronization with a first device clock signal, and gives, to the packet, the first count value and the second count value for use when the packet is sent. The second transmission device outputs the data signal reproduced from the packet in synchronization with an output data clock signal, and controls a frequency of the output data clock signal on the basis of the first count value and the second count value.SELECTED DRAWING: Figure 8

Description

This case relates to a transmission system, a transmission device, and a clock synchronization method.

For example, data signals such as audio and video that are streamed are packetized and transmitted between each node on the route at a constant transmission speed. If the frequencies of the clock signals for transmitting the data signals are not synchronized between the transmission devices of the transmitting side node and the receiving side nodes, the data signal is delayed and the output is stopped, and the quality of the streaming distribution service deteriorates. There is a risk.

For this reason, for example, in the case of a synchronous network such as a dedicated line, a high-precision reference clock used for signal transmission is supplied to the transmission device of each node, but the dedicated line is relatively inexpensive in recent years due to its high cost. Asynchronous networks such as versatile Ethernet lines are used. In the case of an asynchronous network, the transmission device of each node is provided with means such as PTP (Precision Time Protocol) and Sync-E, or GPS (Global Positioning System) clock and cesium clock for each node or base to achieve high accuracy. You can get synchronization to the reference clock.

However, even when an asynchronous network is used, the cost of the network and the device increases if a high-precision reference clock is used. Therefore, the transmission device of each node performs phase synchronization control using, for example, the count value of the clock signal extracted from the data signal without using the reference clock (see, for example, Patent Document 1). According to the phase synchronization control, even if the delay time of the data signal fluctuates according to the state of the transmission line, the frequency of the clock signal can follow the fluctuation.

Japanese Unexamined Patent Publication No. 2000-174742

However, the frequency of the clock signal may change significantly depending on the state of the data signal input source device. In this case, an error occurs in the frequency of the clock signal in each transmission device of the transmitting side node and the receiving side node, and it is difficult to quickly converge the frequency error by the phase synchronization control and synchronize the frequency of the clock signal. Therefore, an error occurs between the input rate of the data signal to the transmission device of the transmitting side node and the output rate of the data signal from the transmitting device of the receiving side node.

On the other hand, the transmission device of each node may be provided with a buffer for storing a packet amount sufficient to absorb the rate difference, but as the buffer amount increases, the residence time of the packets in the transmission device increases. Therefore, the delay time of the data signal may increase.

An object of the present invention is to provide a transmission system, a transmission device, and a clock synchronization method capable of improving the synchronization performance of clock frequencies between transmission devices.

In one aspect, the transmission system comprises a first transmission device that generates and transmits a packet from a data signal and a second transmission device that receives the packet and reproduces the data signal from the packet. The first transmission device generates an extraction unit that extracts an input data clock signal from the data signal, a first counter that counts a first count value in synchronization with the input data clock signal, and a first device clock signal. The packet is transmitted to the first generation unit, the first measurement unit that measures the first frequency of the input data clock signal by counting the second count value in synchronization with the first device clock signal, and the first measurement unit. The second transmission device acquires the first count value and the second count value from the packet, which has a first count value and a granting unit that gives the second count value to the packet. An acquisition unit, a second generation unit that generates an output data clock signal, an output unit that outputs the data signal reproduced from the packet in synchronization with the output data clock signal, the first count value, and the first It has a control unit that controls the frequency of the output data clock signal based on the two count values.

In one embodiment, the transmission device is an extraction unit that extracts an input data clock signal from the data signal in a transmission device that generates a packet from the data signal and transmits the packet to another transmission device that reproduces the data signal. The counter that counts the first count value in synchronization with the input data clock signal, the generator that generates the device clock signal, and the frequency of the input data clock signal are synchronized with the first device clock signal. It has a measuring unit that measures by counting a second count value, and an imparting unit that assigns the first count value and the second count value when the packet is transmitted to the packet.

In one embodiment, the clock synchronization method is a clock between a first transmission device that generates and transmits a packet from a data signal and a second transmission device that receives the packet and reproduces the data signal from the packet. In the synchronization method, the first transmission device extracts an input data clock signal from the data signal, counts a first count value in synchronization with the input data clock signal, generates a first device clock signal, and then generates the first device clock signal. The first frequency of the input data clock signal is measured by counting the second count value in synchronization with the first device clock signal, and the first count value and the second count when the packet is transmitted are measured. A value is given to the packet, the second transmission device acquires the first count value and the second count value from the packet, generates an output data clock signal, and the data signal reproduced from the packet. Is a method of controlling the frequency of the output data clock signal based on the first count value and the second count value.

As one aspect, it is possible to improve the synchronization performance of the clock frequency between the transmission devices.

It is a block diagram which shows an example of an asynchronous network. It is a block diagram which shows an example of a transmission system. It is a time chart which shows an example of the process of giving a time stamp to a packet. It is a time chart which shows an example of the control which brings the frequency of an output data clock signal close to a target value. It is a flowchart which shows an example of a packet transmission process. It is a flowchart which shows an example of the frequency control processing of an output data clock signal. It is a flowchart which shows an example of the determination process of a target value. It is a figure which shows the example of the change with respect to time of each frequency of an input data clock signal and an output data clock signal.

FIG. 1 is a configuration diagram showing an example of an asynchronous network. Asynchronous networks are used, for example, for data transmission services. As equipment for the data transmission service, for example, a transmission station 90 and a reception station 91 are provided.

Each of the transmission station 90 and the reception station 91 is provided with one or more transmission devices 1. The transmission device 1 accommodates digital data in a data signal and transmits the data. In the transmission line between the transmission station 90 and the reception station 91, the data signal is packetized and transmitted.

The data signal is transmitted from the transmitting station 90 to the receiving station 91, and is transmitted to a device (not shown) connected to the output side of the receiving station 91.

The asynchronous network is not provided with a common reference clock facility supplied to the transmission device 1. Therefore, frequency synchronization of the clock signal for transmitting the data signal is established between the transmission device 1 of the transmission station 90 and the reception station 91.

When frequency synchronization is not established, for example, when the frequency of the clock signal of the transmission device 1 of the transmission station 90 is higher than the frequency of the clock signal of the transmission device 1 of the reception station 91, the data signal is input to the transmission device 1 of the transmission station 90. Since the rate is higher than the output rate from the transmission device 1 of the reception station 91, a data signal loss occurs in the transmission device 1 of the reception station 91. Further, when the frequency of the clock signal of the transmission device 1 of the transmission station 90 is lower than the frequency of the clock signal of the transmission device 1 of the reception station 91, the input rate of the data signal to the transmission device 1 of the transmission station 90 is the transmission of the reception station 91. Since the output rate is lower than the output rate from the device 1, the output of the data signal is interrupted.

On the other hand, it is also possible to provide a buffer in the transmission device 1 for storing a packet amount sufficient to absorb the rate difference. However, as the amount of buffer increases, the residence time of the packet in the transmission device 1 increases, so that the delay time of the data signal may increase. Especially in the case of streaming distribution, the service quality may deteriorate due to the increase in the delay time of the data signal.

Therefore, the transmission device 1 of the transmission station 90 assigns each count value indicating the phase and frequency of the clock signal extracted from the input data signal to each packet and transmits the count value to the transmission device 1 of the reception station 91. The transmission device 1 of the receiving station 91 controls the frequency of the clock signal for outputting the data signal based on each count value. By using the frequency synchronization together, the frequency synchronization performance of the clock signal between the transmission device 1 of the transmission station 90 and the transmission device 1 of the reception station 91 is improved as compared with the case where only the phase synchronization control is performed.

FIG. 2 is a configuration diagram showing an example of a transmission system. The transmission system includes a transmission unit 2 and a reception unit 3 connected to each other via a transmission line 9 such as a LAN (Local Area Network) cable or an optical fiber. The transmission unit 2 is an example of the first transmission device, and is provided in the transmission device 1 of the transmission station 90. The receiving unit 3 is an example of the second transmission device, and is provided in the transmission device 1 of the receiving station 91. The transmission device 1 may be appropriately provided with units other than the transmission unit 2 and the reception unit 3.

The transmission unit 2 extracts the input data clock signals CLKs from the input data signal S. The transmission unit 2 generates a time stamp TS # 1 as a count value related to the phase of the input data clock signal CLKs, and generates a time stamp TS # 2 as a count value related to the frequency of the input data clock signal CLKs. The transmission unit 2 generates a packet (PKT) from the data signal S, and adds time stamps TS # 1 and TS # 2 to the packet when the packet is transmitted.

The receiving unit 3 receives the packet from the transmitting unit 2, acquires the time stamps TS # 1 and TS # 2 from the packet, and sets the frequency Fr of the output data clock signal CLKr based on the time stamps TS # 1 and TS # 2. Control. The receiving unit 3 reproduces the data signal S from the packet and outputs it in synchronization with the output data clock signal CLKr. The configurations of the transmission unit 2 and the reception unit 3 will be described below.

The transmission unit 2 includes a data writing unit 20, a buffer (BUFF) 21, a transmitting unit 22, a clock (CLK) extraction unit 23, a time stamp (TS) imparting unit 24, a phase time stamp generation unit 25, and a frequency time stamp generation unit 26. , And a transmitter clock source 27. The data writing unit 20, the transmitting unit 22, the CLK extraction unit 23, the TS adding unit 24, the phase time stamp generating unit 25, and the frequency time stamp generating unit 26 are formed by circuits such as FPGA and ASIC.

The data signal S is input to the data writing unit 20 and the CLK extraction unit 23 from another device (not shown). The data signal S is a continuous digital signal and contains audio data, video data, and the like.

The data writing unit 20 writes the data signal S to the buffer 21. The buffer 21 is, for example, a storage space for video data and audio data allocated to the memory.

For example, when the data for the payload of one packet is accumulated in the buffer 21, the transmission unit 22 reads the data from the buffer 21 and adds a header to generate a packet PKT and outputs the packet PKT to the transmission line 9. Examples of the packet PKT include, but are not limited to, IP (Internet Protocol) packets.

The transmission unit 22 may include, for example, a light source and an optical modulator for converting an electric signal of a packet PKT into an optical signal. The electric signal and the optical signal are input to the receiving unit 3 from the transmission line 9.

The CLK extraction unit 23 extracts the input data clock signals CLKs from the data signal S. The CLK extraction unit 23 includes, for example, a PLL (Phase Locked Loop) circuit or the like. The CLK extraction unit 23 outputs the input data clock signals CLKs to the phase time stamp generation unit 25 and the frequency time stamp generation unit 26.

The phase time stamp generation unit 25 includes a multiplication circuit 250 and a clock (CLK) counter 251. The multiplication circuit 250 is an example of a multiplication unit, and generates a multiplication clock signal CLKsa by multiplying the input data clock signal CLKs. The multiplication circuit 250 outputs the multiplication clock signal CLKsa to the CLK counter 251.

The CLK counter 251 is an example of the first counter, and counts the count value Na in synchronization with the input data clock signal CLKs. For example, the CLK counter 251 increments the count value Na by one each time a pulse of the multiplication clock signal CLKsa is input. As a result, the CLK counter 251 can detect the phase of the input data clock signal CLKs with the count value Na in units of the period of the multiplied clock signal CLKsa.

The count value Na is used as the time stamp TS # 1 indicating the phase of the input data clock signal CLKs. The CLK counter 251 outputs the count value Na to the TS giving unit 24.

The frequency time stamp generation unit 26 includes a frequency dividing circuit 260 and a frequency measuring unit 261. The frequency dividing circuit 260 is an example of a frequency dividing unit, and generates a frequency dividing clock signal CLKsb by dividing the input data clock signal CLKs by n (n: an integer of 2 or more). The frequency dividing circuit 260 outputs the frequency dividing clock signal CLKsb to the frequency measuring unit 261.

The frequency measuring unit 261 is an example of the first measuring unit, and measures the frequency Fs of the input data clock signal CLKs by counting the count value Nb in synchronization with the transmitting device clock signal CLK1d.

The transmission device clock source 27 is an example of the first generation unit, and generates the transmission device clock signal CLK1d and outputs it to the frequency measurement unit 261. Examples of the transmitter clock source 27 include a crystal oscillator having a fixed oscillation frequency. The frequency Fs of the input data clock signal CLKs is an example of the first frequency, and the transmitter clock signal CLK1d is an example of the first device clock signal.

The frequency measuring unit 261 measures the frequency Fs of the input data clock signal CLKs by counting the period of the divided clock signal CLKsb as the count value Nb. Therefore, the frequency measuring unit 261 can measure the frequency Fs with higher accuracy than when counting the period of the input data clock signal CLKs.

The frequency measuring unit 261 is, for example, a counter circuit, and counts the count value Nb in synchronization with the transmission device clock signal CLK1d. The frequency measuring unit 261 holds the count value Nb for each cycle of the divided clock signal CLKsb, and outputs the count value Nb indicating the length of one cycle of the divided clock signal CLKsb to the TS giving unit 24.

The TS granting unit 24 is an example of a granting unit, and assigns count values Na and Nb when a packet is transmitted from the transmitting unit 22 to the packet as time stamps TS # 1 and TS # 2, respectively. The transmission unit 22 outputs transmission pulse signals PLs indicating the timing of transmitting the packet to the TS imparting unit 24. That is, the transmission unit 22 notifies the TS granting unit 24 of the timing of packet transmission.

The TS imparting unit 24 outputs the count values Na and Nb at the time of input of the transmission pulse signal PLs to the transmission unit 22 as time stamps TS # 1 and TS # 2, respectively. The transmission unit 22 inserts the time stamps TS # 1 and TS # 2 into the header of the packet.

FIG. 3 is a time chart showing an example of processing for adding time stamps TS # 1 and TS # 2 to a packet.

Reference numeral Ga indicates a process of assigning the time stamp TS # 1. The CLK counter 251 increments the count value Na by 1 each time a pulse of the multiplication clock signal CLKsa is input. The count value Na is output to the TS giving unit 24.

Further, the transmission unit 22 outputs, for example, transmission pulse signals PLs indicating the start positions of the packets PKT # 1 and # 2 to be transmitted to the TS imparting unit 24. The position indicated by the transmission pulse signal PLs is not limited. For example, the transmission pulse signal PLs may indicate the end of packets PKT # 1 and PKT # 2.

When the transmission pulse signal PLs is input at the time t2, the TS imparting unit 24 assigns the count value Na = 9 at the time t2 to the packet PKT # 1 as the time stamp TS # 1. Further, when the transmission pulse signal PLs is input at the time t4, the TS imparting unit 24 assigns the count value Na = 902 at the time t4 to the packet PKT # 2 as the time stamp TS # 1.

As described above, since the time stamp TS # 1 indicates the count value Na of the multiplied clock signal CLKsa when the packets PKT # 1 and PKT # 2 are transmitted, the time when the packets PKT # 1 and PKT # 2 are transmitted. It corresponds to the phase of the input data clock signal CLKs with respect to t2 and t4.

Reference numeral Gb indicates a process of assigning the time stamp TS # 2. The frequency measuring unit 261 increases the count value Nb by 1 each time the pulse of the transmission device clock signal CLK1d is input. The frequency measuring unit 261 holds the count value Nb for each cycle of the divided clock signal CLKsb and resets it to 1. When the transmission pulse signal PLs is input, the frequency measuring unit 261 outputs the held count value Nb (holding value) to the TS giving unit 24.

When the falling edge of the divided clock signal CLKsb is input at time t1, the frequency measuring unit 261 holds the count value Nb = 103 at the time of input and then resets the count value Nb to 1. When the transmission pulse signal PLs is input at the time t2 (> t1), the TS assigning unit 24 assigns the count value Nb = 103 (holding value) at the time t2 to the packet PKT # 1 as the time stamp TS # 2.

Further, when the falling edge of the divided clock signal CLKsb is input at time t3, the frequency measuring unit 261 holds the count value Nb = 102 at the time of input and then resets the count value Nb to 1. When the transmission pulse signal PLs is input at the time t4 (> t3), the TS assigning unit 24 assigns the count value Nb = 102 (holding value) at the time t4 to the packet PKT # 2 as the time stamp TS # 2.

As described above, since the time stamp TS # 2 indicates the counter value Nb for one cycle of the divided clock signal CLKsb when the packets PKT # 1 and PKT # 2 are transmitted, the packets PKT # 1 and PKT # 2 Corresponds to the frequency Fs of the input data clock signal CLKs based on the time t2 and t4 when is transmitted.

Referring to FIG. 2 again, the packets with the time stamps TS # 1 and TS # 2 are input from the transmission line 9 to the receiving unit 3.

The receiving unit 3 includes a receiving unit 30, a buffer (BUFF) 31, a signal reproducing unit 32, a phase control unit 33, a frequency comparing unit 34, and a receiving device clock source 35. The receiving unit 30, the signal reproducing unit 32, the phase control unit 33, and the frequency comparing unit 34 are formed by circuits such as FPGA and ASIC.

The receiving unit 30 receives the packet input from the transmission line 9. The receiving unit 30 may have, for example, a light source and a demodulator for converting an optical signal into an electric signal and reproducing a packet.

The receiving unit 30 removes the header from the packet, extracts data from the payload of the packet, and stores it in the buffer 31. The buffer 31 is, for example, a storage space for video data and audio data allocated to the memory. The capacity of the buffer 31 is set based on, for example, the amount of variation in the delay time of the packet in the transmission line 9 and the phase difference between the input data clock signal CLKs and the output data clock signal CLKr.

The signal reproduction unit 32 is an example of an output unit, and outputs the data signal S reproduced from the packet to another unit (not shown) in synchronization with the output data clock signal CLKr. The signal reproduction unit 32 reproduces the data signal S by reading data from the buffer 31 according to the output data clock signal CLKr. The data signal S is output at a rate according to the frequency Fr of the output data clock signal CLKr.

Further, the receiving unit 30 is an example of an acquisition unit, and acquires the time stamps TS # 1 and TS # 2 from the header of the packet. That is, the receiving unit 30 acquires the count values Na and Nb when each packet is transmitted. The receiving unit 30 outputs the time stamp TS # 1 together with the received pulse signal PLr to the phase control unit 33, and outputs the time stamp TS # 2 to the frequency comparison unit 34.

The phase control unit 33 includes a phase difference calculation unit 330, a smoothing processing unit 331, a target value setting unit 332, a voltage control unit 333, a VCO (Voltage-Controlled Oscillator) 334, and a clock (CLK) counter 335. Note that some of these processes may be realized by software processing in which the CPU (Central Processing Unit) reads the program from the memory instead of the hardware.

The VCO 334 is an example of the second generation unit, and generates an output data clock signal CLKr having a frequency Fr corresponding to the voltage Vc controlled by the voltage control unit 333. The frequency Fr of the output data clock signal CLKr is a numerical value obtained by adding the error Δf of the phase control by the phase control unit 33 to the frequency Fs of the input data clock signal CLKs. The output data clock signal CLKr is input to the CLK counter 335, the signal reproduction unit 32, and the frequency comparison unit 34.

The CLK counter 335 is an example of the second counter, and counts the count value Nr in synchronization with the output data clock signal CLKr. The count value Nr corresponds to the phase of the output data clock signal CLKr based on the time when the packet is received. The CLK counter 335 outputs the count value Nr to the phase difference calculation unit 330.

The phase difference calculation unit 330 compares the count value Na of the time stamp TS # 1 with the count value Nr of the CLK counter 335 according to the input of the received pulse signal PLr. That is, the phase difference calculation unit 330 compares the count value Na with the count value Nr when the packet is received. The received pulse signal PLr indicates the start position of the packet, but is not limited to this, and may indicate the end, for example.

The phase difference calculation unit 330 calculates the difference ΔN between the count values Na and Nr. The difference ΔN between the count values Na and Nr indicates the phase difference between the input data clock signal CLKs and the output data clock signal CLKr. The difference ΔN is output to the smoothing processing unit 331.

The smoothing processing unit 331 smoothes the difference ΔN. As a result, the influence of the fluctuation of the delay time of the packet in the transmission line 9 on the control of the frequency Fr of the output data clock signal CLKr is suppressed. The smoothing processing unit 331 calculates the smoothing difference ΔNm from, for example, the time average of the difference ΔN or the average for each predetermined number of packets. The smoothing difference ΔNm is output to the target value setting unit 332.

The target value setting unit 332 sets the target value Fo according to the comparison result of the count values Na and Nr. For example, the target value setting unit 332 sets the target value Fo of the frequency Fr of the output data clock signal CLKr based on the smoothing difference ΔNm. The target value Fo is input to the voltage control unit 333.

The voltage control unit 333 controls the voltage Vc of the VCO 334 according to the target value Fo. As a result, the target value setting unit 332 and the voltage control unit 333 control the frequency Fr of the output data clock signal CLKr so as to approach the target value Fo.

FIG. 4 is a time chart showing an example of control for bringing the frequency Fr of the output data clock signal CLKr closer to the target value Fo. In this example, it is assumed that the difference ΔN is the same value as the smoothing difference ΔNm.

Further, the CLK counter 335 counts the count value Nr in synchronization with the output data clock signal CLKr. For example, the CLK counter 335 increments the count value Nr by one each time a pulse of the output data clock signal CLKr is input.

The phase difference calculation unit 330 acquires the time stamp TS # 1 from the header of the packet in response to the input of the received pulse signal PLr. For example, the phase difference calculation unit 330 acquires the time stamp TS # 1 indicating the count value Na = 9 at the time t5 when the received pulse signal PLr is input. The phase difference calculation unit 330 calculates the difference ΔN = -3 (= 9-12) between the count value Nr = 12 at time t5 and the count value Na = 9 of the time stamp TS # 1.

The target value setting unit 332 determines that the count value Nr is ahead of the count value Na based on the difference ΔN = -3, and sets the target value Fo of the frequency Fr of the output data clock signal CLKr to a value lower than the predetermined reference value. Set. The voltage control unit 333 applies a voltage Vc corresponding to the target value Fo to the VCO 334.

Further, the phase difference calculation unit 330 acquires the time stamp TS # 1 indicating the count value Na = 902 at the time t6 when the received pulse signal PLr is input. The phase difference calculation unit 330 calculates the difference ΔN = -1 (= 902-903) between the count value Nr = 903 at time t6 and the count value Na = 902 of the time stamp TS # 1.

The target value setting unit 332 determines that the progress of the count value Nr with respect to the count value Na has decreased based on the difference ΔN = -1, and sets the target value Fo of the frequency Fr of the output data clock signal CLKr to the previous control value (for example,). Set to a value higher than -30) (for example, -10). The voltage control unit 333 applies a voltage Vc corresponding to the target value Fo to the VCO 334.

For example, the target value setting unit 332 calculates a value obtained by subtracting the previous smoothing difference ΔNm from the new smoothing difference ΔNm as the control amount of the frequency Fr. The voltage control unit 333 controls the voltage Vc so that the frequency Fr changes by the controlled amount.

Further, the target value setting unit 332 may calculate the control amount of the frequency Fr by PID (Proportional-Integral-Differential) control. In this case, the target value setting unit 332 sets the difference of the frequency Fr used for the P term (proportional term), the phase error of the frequency Fr used for the I term (integral term), and the D term from the average value of the plurality of differences ΔN. The rate of change of the frequency Fr used in (differential term) is calculated.

The target value setting unit 332 calculates the sum of the products of the P term, the I term, and the D term and their respective coefficients as the control amount of the frequency Fr. The voltage control unit 333 controls the voltage Vc so that the control amount of the frequency Fr becomes zero. As a result, the frequency Fr of the output data clock signal CLKr follows the target value Fo more smoothly than in the above case.

In this way, the phase control unit 33 controls the frequency Fr of the output data clock signal CLKr so as to approach the target value Fo according to the comparison result of the count values Na and Nr. Therefore, the phase control unit 33 can make the phase of the output data clock signal CLKr follow the phase fluctuation of the input data clock signal CLKs.

However, when the delay time of the packet in the transmission path 9 fluctuates, or when the frequency Fs of the input data clock signal CLKs changes significantly, the error between the frequency Fs of the input data clock signal CLKs and the frequency Fr of the output data clock signal CLKr. Since the phase control error Δf increases, the difference between the input rate of the data signal S to the transmission unit 2 and the output rate from the reception unit 3 also increases.

On the other hand, the receiving unit 3 may be provided with a buffer for storing a packet amount sufficient to absorb the rate difference, but as the buffer amount increases, the residence time of the packets in the receiving unit 3 increases. , The delay time of the data signal S may increase.

Therefore, the target value setting unit 332 and the voltage control unit 333 shown in FIG. 2 control the frequency Fr of the output data clock signal CLKr based on the count values Na and Nb indicated by the time stamps TS # 1 and # 2. Therefore, the frequency Fr of the output data clock signal CLKr is controlled from the phase of the input data clock signal CLKs indicated by the count value Na and the measured value of the frequency Fs of the input data clock signal CLKs indicated by the count value Nb.

Here, since the count value Nb is counted by the transmission device clock signal CLK1d of the transmission unit 2, the measured value of the frequency Fs is not affected by the fluctuation of the delay time of the packet in the transmission line 9. Therefore, even when the frequency Fs of the input data clock signal CLKs changes significantly, in addition to the phase control of the output data clock signal CLKr based on the count value Na, the rapid control of the frequency Fr of the output data clock signal CLKr by the count value Nb Is possible.

Therefore, the synchronization performance of the clock frequency between the transmission unit 2 and the reception unit 3 is improved. The target value setting unit 332 and the voltage control unit 333 are examples of the control unit.

The target value setting unit 332 limits the range of the target value Fo based on the frequency difference Δfd input from the frequency comparison unit 34. The frequency comparison unit 34 detects the frequency difference Δfd between the input data clock signal CLKs and the output data clock signal CLKr based on the time stamp TS # 2. The frequency difference Δfd is a value obtained by estimating the phase control error Δf, which is an error between the frequency Fs of the input data clock signal CLKs and the frequency Fr of the output data clock signal CLKr. The frequency difference Δfd includes measurement errors due to the respective accuracy of the transmission device clock signal CLK1d of the transmission unit 2 and the reception device clock signal CLK2d of the reception unit 3.

The frequency comparison unit 34 includes a frequency estimation unit 340, an error detection unit 341, and a frequency measurement unit 342. Note that some of these processes may be realized by software processes in which the CPU reads the program from the memory instead of the hardware.

The frequency estimation unit 340 estimates the frequency Fs of the input data clock signal CLKs from the time stamp TS # 2.

Nb = T × F1d ・ ・ ・ Equation (1)
T≈n / Fs ... Equation (2)
Fs = n × F1d / Nbm ・ ・ ・ Equation (3)

The count value Nb indicated by the time stamp TS # 2 is represented by the above equation (1) from the period T of the frequency division clock signal CLKsb and the frequency F1d of the transmission device clock signal CLK1d. Here, the period T is a value including the quantization error, and is expressed by the above equation (2) from the frequency division number n of the frequency division clock signal CLKsb and the frequency Fs of the input data clock signal CLKs. .. That is, the period T of the frequency-divided clock signal CLKsb is n times the period (1 / Fs) of the input data clock signal CLKs.

Therefore, the frequency Fs of the input data clock signal CLKs can be calculated from the equations (1) and (2) to the equation (3). Here, Nbm is an average value of the count value Nb at regular intervals. For example, when the time stamp TS # 2 indicating the count values Nb = 103 and 102 is obtained from two packets received within a certain period of time, the average value Nbm is 102.5 (= (103 + 102) / 2). It becomes.

The frequency estimation unit 340 estimates the frequency Fs of the input data clock signal CLKs by the equation (3). In this way, the frequency Fs is obtained from the count value Nb of the time stamp TS # 2.

The measurement error of the frequency Fs generated by the frequency measuring unit 261 does not depend on the fluctuation of the delay time of the packet in the transmission line 9, but it depends on the accuracy ΔFosc (> 0) of the frequency F1d of the transmitting device clock signal CLK1d of the transmitting unit 2. Almost match. The frequency estimation unit 340 notifies the error detection unit 341 of the frequency Fs.

Further, the frequency measuring unit 342 is an example of the second measuring unit, and measures the frequency Fr of the output data clock signal CLKr based on the receiving device clock signal CLK2d. The receiver clock signal CLK2d is input to the frequency measurement unit 342 from the receiver clock source 35, and the output data clock signal CLKr is input from the VCO 334.

The receiving device clock source 35 is an example of the third generation unit, and generates the receiving device clock signal CLK2d. Examples of the receiver clock source 35 include a crystal oscillator having a fixed oscillation frequency. The receiving device clock signal CLK2d is an example of the second device clock signal.

The frequency measuring unit 342 counts the period of the output data clock signal CLKr by the receiving device clock signal CLK2d by the same method as the frequency measuring unit 342 of the transmission unit 2, for example. For example, the frequency measuring unit 342 holds a count value corresponding to a cycle for each falling edge of the output data clock signal CLKr, and calculates the frequency Fr (= 1 / cycle) of the output data clock signal CLKr from the count value.

The measurement error of the frequency Fr generated by the frequency measuring unit 342 does not depend on the fluctuation of the delay time of the packet in the transmission line 9, but substantially matches the accuracy ΔFosc of the frequency F2d of the receiving device clock signal CLK2d. In this example, the accuracy ΔFosc of the frequency F1d of the transmission device clock signal CLK1d and the frequency F2d of the reception device clock signal CLK2d is the same, but may be different.

The frequency measurement unit 342 notifies the voltage control unit 333 and the error detection unit 341 of the frequency Fr. The voltage control unit 333 applies a voltage Vc corresponding to the difference between the target value Fo and the frequency Fr to the VCO 334.

The error detection unit 341 calculates the frequency difference Δfd (= Fr−Fs) as the difference between the frequency Fs of the input data clock signal CLKs and the frequency Fr of the output data clock signal CLKr. The error detection unit 341 notifies the target value setting unit 332 of the frequency difference Δfd.

The target value setting unit 332 limits the range of the target value Fo based on the frequency difference Δfd. As a result, the target value setting unit 332 can suppress the fluctuation of the target value Fo so that the error Δf of the phase control does not increase.

Δfd = Δf ± 2 × ΔFosc ・ ・ ・ Equation (4)

The frequency difference Δfd includes not only the phase control error Δf of the phase control unit 33 but also each measurement error ΔFosc of the frequency measurement units 261 and 342, and the total error is 2 × ΔFosc. Therefore, the frequency difference Δfd is expressed by the above equation (4).

For example, when the accuracy ΔFosc of the transmitter clock signal CLK1d and the receiver clock signal CLK2d is ± 10 (ppm), the total of the measurement errors ΔFosc of the frequency measuring units 261 and 342 is approximately ± 20 (ppm) (= 2 ×). 10). Therefore, the phase control error Δf may be 0 when the frequency difference Δfd is in the range of -20 to +20 (ppm), but the frequency difference Δfd is in the range of -20 to +20 (ppm). If it is outside, it will be greater than 0.

Therefore, when the frequency difference Δfd exceeds the measurement error range (-2 × ΔFosc to +2 × ΔFosc) based on the respective accuracy ΔFosc of the transmitting device clock signal CLK1d and the receiving device clock signal CLK2d, the target value setting unit 332 sets the target value. Limit the range of Fo. Therefore, when the error Δf of the phase control exists, that is, when the error Δf is not 0, the target value setting unit 332 can appropriately suppress the increase of the error Δf by limiting the range of the target value Fo. it can.

Here, since the frequency difference Δfd may be a positive value or a negative value, the range of the suppressed error Δf is twice the range of the above error. That is, the range of the error Δf is defined in the range of -4 × ΔFosc to +4 × ΔFosc. For example, when each accuracy ΔFosc of the transmitting device clock signal CLK1d and the receiving device clock signal CLK2d is ± 10 (ppm), the range of the error Δf is -40 to +40 (ppm). By defining the error Δf in this way, the design of the transmission system becomes easy.

For example, the target value setting unit 332 excludes the range in which the measurement error based on each accuracy ΔFosc of the transmission device clock signal CLK1d and the reception device clock signal CLK2d is an abnormal value from the range of the target value Fo. Therefore, the frequency Fs of the input data clock signal CLKs and the frequency Fr of the output data clock signal CLKr can be synchronized with high accuracy.

Next, each process of the transmission unit 2 and the reception unit 3 will be described.

FIG. 5 is a flowchart showing an example of packet transmission processing. First, the data signal S is input to the data writing unit 20 (step St1).

The data writing unit 20 stores the data of the data signal S in the buffer 21 (step St2). The transmission unit 22 compares the amount of data stored in the buffer 21 with the predetermined amount M (step St3). The predetermined amount M is, for example, the amount of data that can be accommodated in the payload of the packet.

When the stored amount is less than the predetermined amount M (No in step St3), the transmission unit 22 executes the process of step St2 again. Further, when the stored amount is the predetermined amount M or more (Yes in step St3), the transmission unit 22 reads data from the buffer 21 and generates a packet (step St4). After generating the packet, the transmission unit 22 outputs the transmission pulse signal PLs to the TS imparting unit 24.

The TS imparting unit 24 acquires count values Na and Nb from the CLK counter 251 and the frequency measuring unit 261 according to the transmission pulse signal PLs (step St5). The TS assigning unit 24 assigns time stamps TS # 1 and TS # 2 indicating the count values Na and Nb to the header of the packet (step St6).

The transmission unit 22 transmits a packet (step St7). In this way, the packet transmission process is executed.

FIG. 6 is a flowchart showing an example of control processing of the frequency Fr of the output data clock signal CLKr. First, the receiving unit 30 receives the packet from the transmitting unit 2 (step St11). The receiving unit 30 outputs the received pulse signal PLr in response to the reception of the packet. Next, the receiving unit 30 acquires the time stamps TS # 1 and TS # 2 from the packet (step St12). Subsequent steps St13 and St14 and steps St15 to 17 may be executed in parallel.

The phase difference calculation unit 330 sets the difference ΔN between the count value Na indicated by the time stamp TS # 1 and the count value Nr synchronized with the output data clock signal CLKr as the input data clock signal in response to the input of the received pulse signal PLr. Calculated as the phase difference between CLKs and the output data clock signal CLKr (step St13). The smoothing processing unit 331 calculates the smoothing difference ΔNm from the difference ΔN for a plurality of packets, for example (step St14).

Further, the frequency estimation unit 340 estimates the frequency Fs of the input data clock signal CLKs from the count value Nb indicated by the time stamp TS # 2 (step St15). The frequency measuring unit 342 measures the frequency Fr of the output data clock signal CLKr (step St16). The error detection unit 341 calculates the frequency difference Δfd between the frequency Fs of the input data clock signal CLKs and the frequency Fr of the output data clock signal CLKr (step St17).

The target value setting unit 332 determines the target value Fo of the frequency Fr (step St18). The process of determining the target value Fo will be described later.

The voltage control unit 333 applies a voltage Vc corresponding to the target value Fo to the VCO 334 (step St19). In this way, the control process of the frequency Fr of the output data clock signal CLKr is executed.

FIG. 7 is a flowchart showing an example of the determination process of the target value Fo. This process is executed in step St18 described above.

The target value setting unit 332 compares the absolute value of the frequency difference Δfd with the total error (2 × ΔFosc) (step St31).

When the absolute value of the frequency difference Δfd is 2 × ΔFosc or less (No in step St31), the target value setting unit 332 determines that the frequency difference Δfd is a normal value, and determines, for example, the previous target value Fo'and the smoothing difference ΔNm. A new target value Fo is determined from the amount of change per unit time of (step St36). The initial value of the target value Fo'may be, for example, 0 or another value. After that, the target value setting unit 332 ends the process with the previous target value Fo'as a new target value Fo (step St34).

Further, when the absolute value of the frequency difference Δfd is larger than 2 × ΔFosc (Yes in step St31), the target value setting unit 332 determines that the frequency difference Δfd is an abnormal value. Then, it is determined whether or not the frequency difference Δfd determined to be an abnormal value is larger than 0, that is, whether it is a positive value or a negative value (step St32). The target value setting unit 332 calculates the target value Fo according to whether the frequency difference Δfd is a positive value or a negative value.

Fo = Fo'-(Δfd-2 × ΔFosc) ・ ・ ・ Equation (5)

When the frequency difference Δfd is a positive value (Yes in step St32), the target value setting unit 332 sets the frequency difference Δfd and the total error (Yes) from the previous target value Fo'so that the frequency difference Δfd is in the normal range. A new target value Fo is calculated by subtracting the difference (Δfd-2 × ΔFosc) of 2 × ΔFosc) (step St33). At this time, the target value setting unit 332 calculates the target value Fo from the above equation (5), for example.

As a result, the target value Fo is reduced from the previous target value Fo'by a value obtained by subtracting the total error (2 × ΔFosc) from the frequency difference Δfd. That is, when the frequency difference Δfd is a positive value exceeding 2 × ΔFosc, the target value setting unit 332 reduces the target value Fo from the previous target value Fo'so that the frequency difference Δfd is in the normal range. ..

For example, when the frequency difference Δfd = 30 (ppm) and the accuracy ΔFosc = 10 (ppm), the target value setting unit 332 makes the frequency difference Δfd abnormal because the frequency difference Δfd> 20 (ppm) is established in step St31. Judge as a value. Since the frequency difference Δfd is a positive value, the target value setting unit 332 calculates the target value Fo as Fo'-10 (ppm) (= 30-2 × 10) in step St33. As a result, the frequency difference Δfd is reduced by 10 (ppm) from 30 (ppm) to 20 (ppm) (= 30-10), and is therefore controlled within the normal value range.

Fo = Fo'+ (−Δfd-2 × ΔFosc) ・ ・ ・ Equation (6)

When the frequency difference Δfd is a negative value (No in step St32), the target value setting unit 332 has a total error with (−Δfd) so that the frequency difference Δfd is within the normal range at the previous target value Fo'. A new target value Fo is calculated by adding the difference (−Δfd-2 × ΔFosc) of (2 × ΔFosc) (step St35). At this time, the target value setting unit 332 calculates the target value Fo from the above equation (6), for example.

As a result, the target value Fo increases from the previous target value Fo'by a value obtained by subtracting 2 × ΔFosc for the total error from the frequency difference Δfd. That is, when the frequency difference Δfd is a negative value exceeding 2 × ΔFosc, the target value setting unit 332 increases the target value Fo from the previous target value Fo'so that the frequency difference Δfd is in the normal range. ..

For example, when the frequency difference Δfd = -30 (ppm) and the accuracy ΔFosc = 10 (ppm), the target value setting unit 332 establishes the frequency difference Δfd <-20 (ppm) in step St31, so that the frequency difference Δfd Is judged to be an abnormal value. Since the frequency difference Δfd is a negative value, the target value setting unit 332 calculates the target value Fo as Fo'+10 (ppm) (= − (-30) -2 × 10) in step St35. As a result, the frequency difference Δfd increases by 10 (ppm) from -30 (ppm) to -20 (ppm) (= -30 + 10), and is therefore controlled within the normal value range.

As described above, the target value setting unit 332 has an error based on each accuracy ΔFosc of the transmitter clock signal CLK1d and the receiver clock signal CLK2d, excluding the range in which the frequency difference Δfd is determined to be abnormal from the range of the target value Fo. It is limited to the range of (-4 × ΔFosc to +4 × ΔFosc). As a result, an increase in the error Δf can be suppressed, and the worst value of the error Δf can be defined without depending on the delay fluctuation of the transmission line.

Next, the reduction of the delay time according to this embodiment will be described.

FIG. 8 is a diagram showing an example of changes in the input data clock signals CLKs and the output data clock signals CLKr with respect to the time of each frequency Fs and Fr.

The reference numeral Gc indicates the relative changes in frequencies Fs and Fr in the comparative example. In the comparative example, the target value setting unit 332 does not limit the target value Fo based on the frequency difference Δfd. That is, the phase control unit 33 does not use the time stamp TS # 2 for controlling the frequency Fr.

The frequency Fs of the input data clock signal CLKs increases by ΔFs (> 0) at time Ta. The frequency Fr of the output data clock signal CLKr is the same as the frequency Fs at the time before the time Ta, but the difference from the frequency Fs is ΔFs at the time Ta.

However, the frequency Fr of the output data clock signal CLKr follows the frequency Fs by the phase control of the phase control unit 33, and coincides with the frequency Fs at the time Tb after the period K from the time Ta.

The reference numeral Gd indicates the relative changes in frequencies Fs and Fr in the examples. Also in this example, the frequency Fs of the input data clock signal CLKs increases by ΔFs (> 0) at the time Ta. At this time, the time required to follow the frequency Fs of the frequency Fr is K, assuming that the phase control of the phase control unit 33 is the same as that of the comparative example.

However, unlike the comparative example, the target value setting unit 332 limits the target value Fo of the frequency Fr based on the frequency difference Δfd, so that the frequency Fr is instantaneously set to a range in which the frequency difference Δfd is not determined to be abnormal at the time Ta. Increase to. As a result, the error Δf becomes 4 × ΔFosc at the maximum based on the measurement error of the frequencies Fs and Fr.

Here, the shaded areas Sa and Sb correspond to the storage amount of the buffer 31 required to prevent packet loss during the period K until the tracking of the frequency Fr is completed in the comparative examples and the examples. A separate storage amount corresponding to the fluctuation of the delay time of the packet in the transmission line 9 is required.

As an example, assuming that ΔFs = 200 (ppm), K = 300 (sec), and ΔFosc = 10 (ppm), the stored amount in the case of the comparative example corresponds to 30 (ms) (= 200 × 300/2). The amount is the amount, and the stored amount in the case of the embodiment is an amount corresponding to 6 (ms) (= 40 × 300/2). Therefore, in the case of the embodiment, the packet delay time is reduced as compared with the case of the comparative example due to the limitation of the target value Fo.

The embodiments described above are examples of preferred embodiments of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention.

The following additional notes will be further disclosed with respect to the above description.
(Appendix 1) A first transmission device that generates and transmits packets from data signals,
It has a second transmission device that receives the packet and reproduces the data signal from the packet.
The first transmission device is
An extraction unit that extracts the input data clock signal from the data signal,
A first counter that counts the first count value in synchronization with the input data clock signal, and
First device A first generator that generates a clock signal and
A first measuring unit that measures the first frequency of the input data clock signal by counting a second count value in synchronization with the first device clock signal.
It has a first count value when the packet is transmitted and a granting unit that gives the second count value to the packet.
The second transmission device is
An acquisition unit that acquires the first count value and the second count value from the packet, and
The second generator that generates the output data clock signal and
An output unit that outputs the data signal reproduced from the packet in synchronization with the output data clock signal, and an output unit.
A transmission system including a control unit that controls the frequency of the output data clock signal based on the first count value and the second count value.
(Appendix 2) The second transmission device is
A second counter that counts the third count value in synchronization with the output data clock signal, and
The third generator that generates the second device clock signal, and
It has a second measuring unit that measures the second frequency of the output data clock signal based on the second device clock signal.
The control unit
The second frequency is controlled so as to approach the target value according to the comparison result between the first count value and the third count value when the packet is received.
The transmission system according to Appendix 1, wherein the range of the target value is limited based on the difference between the first frequency obtained from the second count value and the second frequency.
(Appendix 3) When the difference between the first frequency and the second frequency exceeds the range of measurement error based on the accuracy of the first device clock signal and the second device clock signal, the control unit determines the target. The transmission system according to Appendix 2, wherein the range of values is limited.
(Appendix 4) The control unit is characterized by excluding a range in which measurement errors based on the respective accuracy of the first device clock signal and the second device clock signal are determined to be abnormal from the range of the target value. The transmission system according to Appendix 3.
(Appendix 5) The first transmission device has a frequency dividing unit that generates a frequency dividing clock signal by dividing the input data clock signal.
The transmission system according to any one of Supplementary note 1 to 4, wherein the first measuring unit measures the first frequency by counting the period of the divided clock signal as the second count value.
(Appendix 6) The first transmission device has a multiplication unit that generates a multiplication clock signal by multiplying the input data clock signal.
The transmission system according to any one of Supplementary note 1 to 5, wherein the first counter counts the first count value in synchronization with the multiplication clock signal.
(Appendix 7) In a transmission device that generates a packet from a data signal and transmits the packet to another transmission device that reproduces the data signal.
An extraction unit that extracts the input data clock signal from the data signal,
A counter that counts the first count value in synchronization with the input data clock signal,
A generator that generates the device clock signal and
A measuring unit that measures the frequency of the input data clock signal by counting the second count value in synchronization with the device clock signal.
A transmission device including a first count value when the packet is transmitted and a granting unit that assigns the second count value to the packet.
(Appendix 8) It has a frequency dividing portion that generates a frequency dividing clock signal by dividing the input data clock signal.
The transmission device according to Appendix 7, wherein the measuring unit measures the first frequency by counting the period of the divided clock signal as the second count value.
(Appendix 9) It has a multiplication unit that generates a multiplication clock signal by multiplying the input data clock signal.
The transmission device according to Appendix 7 or 8, wherein the counter counts the first count value in synchronization with the multiplication clock signal.
(Appendix 10) In a clock synchronization method between a first transmission device that generates and transmits a packet from a data signal and a second transmission device that receives the packet and reproduces the data signal from the packet.
The first transmission device is
The input data clock signal is extracted from the data signal,
The first count value is counted in synchronization with the input data clock signal,
Generates the first device clock signal and
The first frequency of the input data clock signal is measured by counting the second count value in synchronization with the first device clock signal.
The first count value and the second count value when the packet is transmitted are given to the packet.
The second transmission device is
The first count value and the second count value are acquired from the packet, and the first count value and the second count value are acquired.
Generates an output data clock signal
The data signal reproduced from the packet is output in synchronization with the output data clock signal.
A clock synchronization method characterized in that the frequency of the output data clock signal is controlled based on the first count value and the second count value.
(Appendix 11) The second transmission device is
The third count value is counted in synchronization with the output data clock signal,
Generates the second device clock signal and
The second frequency of the output data clock signal is measured based on the second device clock signal, and the second frequency is measured.
The second frequency is controlled so as to approach the target value according to the comparison result between the first count value and the third count value when the packet is received.
The clock synchronization method according to Appendix 10, wherein the range of the target value is limited based on the difference between the first frequency obtained from the second count value and the second frequency.
(Appendix 12) In the second transmission device, when the difference between the first frequency and the second frequency exceeds the range of measurement error based on the respective accuracy of the first device clock signal and the second device clock signal. The clock synchronization method according to Appendix 11, wherein the range of the target value is limited.
(Appendix 13) The second transmission device is characterized by excluding a range in which measurement errors based on the respective accuracy of the first device clock signal and the second device clock signal are determined to be abnormal from the range of the target value. The clock synchronization method according to Appendix 12.
(Appendix 14) The first transmission device generates a frequency-divided clock signal by dividing the input data clock signal, and counts the period of the frequency-divided clock signal as the second count value. The clock synchronization method according to any one of Supplementary note 10 to 13, wherein one frequency is measured.
(Supplementary note 15) The first transmission device is characterized in that a multiplied clock signal is generated by multiplying the input data clock signal and the first count value is counted in synchronization with the multiplied clock signal. The clock synchronization method according to any one of 10 to 14.

1 Transmission device 2 Transmission unit 3 Reception unit 22 Transmission unit 23 Clock extraction unit 24 Time stamping unit 27 Transmission device Clock source 30 Reception unit 32 Signal reproduction unit 35 Receiver device Clock source 250 Multiplying circuit 251,335 Clock counter 260 frequency division circuit 261 and 342 Frequency measurement unit 332 Target value setting unit 333 Voltage control unit 334 VCO

Claims (8)

The first transmission device that generates and transmits packets from data signals,
It has a second transmission device that receives the packet and reproduces the data signal from the packet.
The first transmission device is
An extraction unit that extracts the input data clock signal from the data signal,
A first counter that counts the first count value in synchronization with the input data clock signal, and
First device A first generator that generates a clock signal and
A first measuring unit that measures the first frequency of the input data clock signal by counting a second count value in synchronization with the first device clock signal.
It has a first count value when the packet is transmitted and a granting unit that gives the second count value to the packet.
The second transmission device is
An acquisition unit that acquires the first count value and the second count value from the packet, and
The second generator that generates the output data clock signal and
An output unit that outputs the data signal reproduced from the packet in synchronization with the output data clock signal, and an output unit.
A transmission system including a control unit that controls the frequency of the output data clock signal based on the first count value and the second count value. The second transmission device is
A second counter that counts the third count value in synchronization with the output data clock signal, and
The third generator that generates the second device clock signal, and
It has a second measuring unit that measures the second frequency of the output data clock signal based on the second device clock signal.
The control unit
The second frequency is controlled so as to approach the target value according to the comparison result between the first count value and the third count value when the packet is received.
The transmission system according to claim 1, wherein the range of the target value is limited based on the difference between the first frequency obtained from the second count value and the second frequency. When the difference between the first frequency and the second frequency exceeds the range of measurement error based on the accuracy of the first device clock signal and the second device clock signal, the control unit sets the range of the target value. The transmission system according to claim 2, wherein the transmission system is restricted. The third aspect of the present invention is characterized in that the control unit excludes from the range of the target value a range in which a measurement error based on each accuracy of the first device clock signal and the second device clock signal is determined to be abnormal. Described transmission system. The first transmission device has a frequency dividing portion that generates a frequency dividing clock signal by dividing the input data clock signal.
The transmission system according to any one of claims 1 to 4, wherein the first measuring unit measures the first frequency by counting the period of the divided clock signal as the second count value. .. The first transmission device has a multiplication unit that generates a multiplication clock signal by multiplying the input data clock signal.
The transmission system according to any one of claims 1 to 5, wherein the first counter counts the first count value in synchronization with the multiplication clock signal. In a transmission device that generates a packet from a data signal and transmits the packet to another transmission device that reproduces the data signal.
An extraction unit that extracts the input data clock signal from the data signal,
A counter that counts the first count value in synchronization with the input data clock signal,
A generator that generates the device clock signal and
A measuring unit that measures the frequency of the input data clock signal by counting the second count value in synchronization with the device clock signal.
A transmission device including a first count value when the packet is transmitted and a granting unit that assigns the second count value to the packet. In a clock synchronization method between a first transmission device that generates and transmits a packet from a data signal and a second transmission device that receives the packet and reproduces the data signal from the packet.
The first transmission device is
The input data clock signal is extracted from the data signal,
The first count value is counted in synchronization with the input data clock signal,
Generates the first device clock signal and
The first frequency of the input data clock signal is measured by counting the second count value in synchronization with the first device clock signal.
The first count value and the second count value when the packet is transmitted are given to the packet.
The second transmission device is
The first count value and the second count value are acquired from the packet, and the first count value and the second count value are acquired.
Generates an output data clock signal
The data signal reproduced from the packet is output in synchronization with the output data clock signal.
A clock synchronization method characterized in that the frequency of the output data clock signal is controlled based on the first count value and the second count value.

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