JP2021053474A - Game machine - Google Patents

Abstract

To provide a game machine capable of increasing a free space of a ROM of a main control circuit by reducing a capacity of a processing program, a table, and the like managed by the main control circuit and capable of increasing amusement by utilizing the free space of a ROM having the increased capacity.SOLUTION: Control means can execute plural kinds of instructions for designating a value of a high-order side one byte of a two-byte address of second storage means by using an expansion register, and internal lottery means calculates determination data by executing an addition instruction for adding a setting value storage area by using the expansion register when holding a lottery of a combination having a different lottery probability depending on a setting value within lottery processing, and acquires a lottery value for holding a lottery of an internal winning pattern combination on the basis of the calculated determination data.SELECTED DRAWING: Figure 94

Description

The present invention relates to a game machine.

Conventionally, a game called pachislot, which is provided with a plurality of reels having a plurality of symbols provided on their respective surfaces, a start switch, a stop switch, a stepping motor provided corresponding to each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player (hereinafter, also referred to as "start operation") after the game medium such as a medal or coin is inserted into the game machine, and the rotation of all reels is rotated. Outputs a signal requesting a start. The stop switch detects that the stop button provided corresponding to each reel is pressed by the player (hereinafter, also referred to as "stop operation"), and outputs a signal requesting that the rotation of the corresponding reel be stopped. To do. The stepping motor transmits its driving force to the corresponding reels. Further, the control unit controls the operation of the stepping motor based on the signals output by the start switch and the stop switch, and performs the rotation operation and the stop operation of each reel.

In such a game machine, when a start operation is detected, a lottery process using random numbers (hereinafter referred to as "internal lottery process") is performed on the program, and the result of the lottery (hereinafter, "internal winning combination") is performed. The rotation of the reel is stopped based on the timing of the stop operation. Then, when the rotation of all the reels is stopped and the combination of symbols (display combination) related to the establishment of the winning is displayed, the player is given a privilege corresponding to the combination of the symbols. As an example of the privilege given to the player, the payout of the game medium (medals, etc.) and the operation of the re-game (hereinafter, also referred to as "replay") in which the internal lottery process is performed again without consuming the game medium. , The operation of a bonus game that increases the chances of paying out game media, etc. can be mentioned.

Further, as another example of the privilege given to the player in such a game machine, a stop operation advantageous to the player for establishing a specific role (small role related to payout of the game medium, etc.) is performed. The function of activating the state in which the procedure is notified, that is, the operation of the assist time (hereinafter, referred to as "AT"), and the function of activating the gaming state in which the winning probability of the replay is higher than the normal time, that is, the replay time (hereinafter, "AT") The operation of "RT") or the function of simultaneously operating AT and RT, that is, the operation of the assist replay time (hereinafter referred to as "ART") and the like can be mentioned. In addition, these benefits may be given not only by the internal winning combination but also by the result of other lottery processing.

In addition, such a game machine is usually equipped with a circuit (main control circuit) that controls the main game operation of the game machine, such as determination of an internal winning combination, rotation and stop of each reel, and determination of presence / absence of winning. It is provided with a main control board and a sub control board on which a circuit (sub control circuit) for controlling an effect operation such as displaying an image is mounted. The game operation is controlled by a CPU (Central Processing Unit) mounted on the main control circuit. At this time, under the control of the CPU, the program stored in the ROM (Read Only Memory) of the main control circuit, various table data, etc. are expanded in the RAM (Random Access Memory) of the main control circuit, and processing related to various game operations is executed. Will be done.

In recent years, in the gaming machine having the above-described configuration, a gaming machine equipped with a main control device that processes numerical data by using a stack pointer as an operation command has been proposed (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2005-237737

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above problems by reducing the capacity of processing programs and tables managed by the main control circuit to increase the free capacity of the ROM of the main control circuit, and by the increased capacity. It is an object of the present invention to provide a gaming machine capable of enhancing game playability by utilizing the free area of the ROM of the above.

In order to solve the above problems, the present invention provides a gaming machine having the following configuration.

A control means for controlling the game operation (for example, the main CPU 101) and
A first storage means (for example, main ROM 102) in which a process for executing control by the control means is stored, and
A second storage means (for example, main RAM 103) for storing information for the control means to execute control is provided.
The control means
A general-purpose register that stores data when arithmetic processing is executed,
A 1-byte extension register that specifies a part of the memory space address that can be specified by the data stored at the time of execution of the arithmetic processing, and
Has an internal lottery means to determine the internal winning combination,
The first storage means includes a game storage area in which a program for controlling the progress of the game is stored, and a non-game storage area in which a program other than the program for controlling the progress of the game is stored. ,
The second storage means includes a game work area for the program stored in the game storage area to work, and a non-game work area for the program stored in the non-game storage area to work. ,
A set value storage area for storing a set value for adjusting the expected value of the winning of the internal winning combination is provided in the second storage means.
The control means can execute a plurality of types of instructions that specify the value of the upper 1-byte value of the 2-byte address of the second storage means by using the extension register.
In the lottery process, the internal lottery means executes an addition instruction to add the set value storage area using the expansion register when a combination having a different lottery probability differs depending on the set value is executed to obtain determination data. A gaming machine that is calculated and obtains a lottery value for drawing the internal winning combination based on the calculated determination data.

According to the gaming machine of the present invention having the above configuration, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the increased capacity is increased. It is possible to improve the playability by using the free area of the ROM of the minute.

It is a figure for demonstrating the functional flow of the game machine in one Embodiment of this invention. It is a perspective view which shows the appearance structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the schematic structure of the various display screens displayed on the sub-display device of one Embodiment of this invention. It is a figure which shows the transition example of the display screen of the sub-display device in one Embodiment of this invention. It is a block diagram which shows the whole structure of the circuit provided in the gaming machine of one Embodiment of this invention. It is a block diagram which shows the internal structure of the main control circuit in one Embodiment of this invention. It is a block diagram which shows the internal structure of the microprocessor in one Embodiment of this invention. It is a block diagram which shows the internal structure of the sub-control circuit in one Embodiment of this invention. It is a block diagram of various registers which a main CPU has in one Embodiment of this invention. It is a figure which shows the memory map of the main control circuit in one Embodiment of this invention. It is a figure which shows the transition flow of the gaming state between the bonus state and the non-bonus state of pachislot in one Embodiment of this invention. It is a figure which shows the transition flow of the gaming state between the ART gaming state, the non-ART gaming state, and the bonus state of pachislot in one Embodiment of this invention. It is a figure which shows an example of the symbol arrangement table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows the correspondence relationship between the internal winning combination and the stop symbol combination in one Embodiment of this invention. It is a figure which shows the correspondence relationship between the internal winning combination and the stop symbol combination in one Embodiment of this invention. It is a figure which shows an example of the reel stop initial setting table in one Embodiment of this invention. It is a figure which shows an example of the pull-in priority table in one Embodiment of this invention. It is a figure which shows the structure (the 1) of the hit request flag storage area and the winning operation flag storage area in one Embodiment of this invention. It is a figure which shows the structure (the 2) of the hit request flag storage area and the winning operation flag storage area in one Embodiment of this invention. It is a figure which shows (the 3) of the hit request flag storage area and the winning operation flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the carry-over combination storage area in one Embodiment of this invention. It is a figure which shows the structure of the game state flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the operation stop button storage area in one Embodiment of this invention. It is a figure which shows the structure of the pressing order storage area in one Embodiment of this invention. It is a figure which shows the structure of the symbol code storage area in one Embodiment of this invention. It is a figure which shows the correspondence table (the 1) of the internal winning combination and a sub-flag in one Embodiment of this invention. It is a figure which shows the correspondence table (the 2) of the internal winning combination and a sub-flag in one Embodiment of this invention. It is a figure for demonstrating the notification operation at the time of winning subflag EX "triple chili lip" or "reach eye lip" in the gaming machine of one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the general game state in one Embodiment of this invention. It is a figure which shows an example of the ordinary medium-high probability lottery table in one Embodiment of this invention. It is a figure which shows an example of the CZ lottery table in one Embodiment of this invention. It is a figure which shows an example of the mode-up lottery table in CZ1 in one Embodiment of this invention. It is a figure which shows an example of the point lottery table in CZ2 in one Embodiment of this invention. It is a figure which shows an example of ART lottery table (for CZ1, CZ2) in CZ in one Embodiment of this invention. It is a figure which shows an example of ART lottery table (for CZ3) in CZ in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in a normal ART in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table in ART in one Embodiment of this invention. It is a figure which shows an example of the ART level determination table in one Embodiment of this invention. It is a figure which shows an example of the normal ART medium-high probability lottery table in one Embodiment of this invention. It is a figure which shows an example of the CT lottery table in ART in one Embodiment of this invention. It is a figure which shows an example of the addition lottery table in ordinary ART in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the CT state in one Embodiment of this invention. It is a figure which shows an example of the table lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the addition lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the lottery table which added the number of sets in CT in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the bonus state in one Embodiment of this invention. It is a figure which shows an example of the bonus type lottery table in one Embodiment of this invention. It is a figure which shows an example of the lottery table which added the number of ART games in the bonus in one Embodiment of this invention. It is a figure which shows an example of the CT lottery table at the end of a bonus in one Embodiment of this invention. It is a figure for demonstrating the flow of the game (other) in a general game state in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table in non-ART in one Embodiment of this invention. It is a figure which shows the correspondence relationship between the main side navigation data and the sub side navigation data in one Embodiment of this invention. It is a flowchart which shows an example of the power-on (reset interrupt) processing executed by the main control circuit of a game machine in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the power-on processing in one Embodiment of this invention. It is a flowchart which shows the example of the game return processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the game return processing in one Embodiment of this invention. It is a flowchart which shows the example of the setting change confirmation processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the setting change confirmation process in one Embodiment of this invention. It is a flowchart which shows the example of the setting change command generation storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the setting change command generation storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the communication data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data pointer update process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the communication data pointer update process in one Embodiment of this invention. It is a flowchart which shows the example of the (external) processing at the time of power failure in one Embodiment of this invention. It is a flowchart which shows the example of the checksum generation process (non-standard) in one Embodiment of this invention. An example of a source program for executing various processes in the flowchart of the checksum generation process according to the embodiment of the present invention, a stack pointer update operation executed in the checksum generation process, and a data read operation to a register. It is a figure which shows the state of. It is a flowchart which shows the example of the sum check process (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the sum check process (non-standard) in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the checksum process in one Embodiment of this invention. It is a flowchart which shows the example of the main processing (main operation processing) executed by the main control circuit of a game machine in one Embodiment of this invention. It is a flowchart which shows the example of the medal acceptance / start check process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the medal acceptance / start check processing in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the medal insertion process in one Embodiment of this invention. It is a flowchart which shows the example of the combination monitor display switching processing in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion check process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the medal insertion check process in one Embodiment of this invention. It is a flowchart which shows the example of the error processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the error table which is actually referred to on the source program of error processing in one Embodiment of this invention. It is a flowchart which shows the example of the random number acquisition processing in one Embodiment of this invention. It is a flowchart which shows the example of the internal lottery processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the internal lottery processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the internal lottery table (for general game) which is actually referred to on the source program of the internal lottery processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the lottery value selection table by RT state which is actually referred to on the source program of the internal lottery processing in one Embodiment of this invention. Internal lottery value table selection table, 1-byte internal lottery value table, 2-byte internal lottery value table, 1-byte internal lottery value by setting, which is actually referred to on the source program of the internal lottery processing according to the embodiment of the present invention. It is a figure which shows an example of the structure of the table and the internal lottery value table for each 2-byte setting. It is a flowchart which shows the example of the symbol setting process in one Embodiment of this invention. It is a figure which shows the correspondence between the special prize (bonus) winning number and small winning combination winning number, and internal winning combination in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the symbol setting processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the hit request flag table which is actually referred to on the source program of the symbol setting process in one Embodiment of this invention. It is a flowchart which shows the example of the compressed data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the 2nd interface board control processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the 2nd interface board output processing in one Embodiment of this invention. It is a flowchart which shows the example of the control processing by state in one Embodiment of this invention. It is a flowchart which shows the example of the sub-flag conversion process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the sub-flag conversion process in one Embodiment of this invention. It is a figure which shows an example of the structure of the sub-flag conversion table which is actually referred to on the source program of the sub-flag conversion process in one Embodiment of this invention. It is a flowchart which shows the example of the navigation set processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of navigation set processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the navigation data table which is actually referred to on the source program of the navigation set processing in one Embodiment of this invention. It is a flowchart which shows the example of the flag conversion process in one Embodiment of this invention. It is a flowchart which shows the example of the normal middle start processing in one Embodiment of this invention. It is a flowchart which shows the example of the process at the start in CZ in one Embodiment of this invention. It is a flowchart which shows the example of the processing in CZ1 (CZ2) in one Embodiment of this invention. It is a flowchart which shows the example of the processing in CZ1 (CZ2) in one Embodiment of this invention. It is a flowchart which shows the example of the processing in CZ3 in one Embodiment of this invention. It is a flowchart which shows the example of the processing at the time of a start in a normal ART in one Embodiment of this invention. It is a flowchart which shows the example of the start processing during CT in one Embodiment of this invention. It is a flowchart which shows the example of CT lottery processing in CT in one Embodiment of this invention. It is a flowchart which shows the example of the table data acquisition processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the table data acquisition processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the CT lottery table in CT which is actually referred to on the source program of the table data acquisition processing in one Embodiment of this invention. It is a flowchart which shows the example of 1 byte lottery processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of 1-byte lottery processing in one Embodiment of this invention. It is a flowchart which shows the example of the process at the start in BB in one Embodiment of this invention. It is a flowchart which shows the example of the pull-in priority order storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the pull-in priority order storage process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol code acquisition processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the symbol code acquisition process in one Embodiment of this invention. On the source program of the symbol code acquisition process in one embodiment of the present invention, the first cylinder (left reel) symbol arrangement table actually referred to and the symbol correspondence referred to when the first cylinder symbol arrangement table is set. It is a figure which shows an example of the structure of the winning operation table. On the source program of the symbol code acquisition process in one embodiment of the present invention, the second cylinder (middle reel) symbol arrangement table actually referred to and the symbol correspondence referred to when the second cylinder symbol arrangement table is set. It is a figure which shows an example of the structure of the winning operation table. On the source program of the symbol code acquisition process in one embodiment of the present invention, the third cylinder (right reel) symbol arrangement table actually referred to and the symbol correspondence referred to when the third cylinder symbol arrangement table is set. It is a figure which shows an example of the structure of the winning operation table. It is a flowchart which shows the example of the logical product operation processing in one Embodiment of this invention. It is a flowchart which shows the example of the pull-in priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the pull-in priority order acquisition process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the pull-in priority order acquisition process in one Embodiment of this invention. It is a figure which shows an example of the structure of the pull-in priority order table which is actually referred to on the source program of the pull-in priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop control processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the reel stop control processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the reel stop control processing in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop possible signal OFF processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop possible signal ON processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the non-standard port output processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the non-standard port output processing in one Embodiment of this invention. It is a flowchart which shows the example of the winning search process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the prize search process in one Embodiment of this invention. It is a figure which shows an example of the structure of the payout number data table which is actually referred to on the source program of the prize search process in one Embodiment of this invention. It is a flowchart which shows the example of the illegal hit check process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the illegal hit check processing in one Embodiment of this invention. It is a flowchart which shows the example of the winning check, medal payout processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the prize check / medal payout process in one Embodiment of this invention. It is a flowchart which shows the example of the medal payout number check process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the medal payout number check process in one Embodiment of this invention. It is a flowchart which shows the example of the combination monitor aggregation processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of advantageous section aggregation processing in one Embodiment of this invention. It is a flowchart which shows the example of the ratio calculation data setting processing in one Embodiment of this invention. It is a flowchart which shows the example of the ratio calculation process (approximate value formula) in one Embodiment of this invention. It is a flowchart which shows the example of the ratio calculation process (approximate value formula) in one Embodiment of this invention. It is a flowchart which shows the example of the ratio calculation process (loop type) in one Embodiment of this invention. It is a flowchart which shows the example of the payout number totaling process in one Embodiment of this invention. It is a flowchart which shows the example of the medium time aggregation processing in one Embodiment of this invention. It is a flowchart which shows the example of the BB check process in one Embodiment of this invention. It is a flowchart which shows the example of RT check processing in one Embodiment of this invention. It is a flowchart which shows the example of RT check processing in one Embodiment of this invention. It is a flowchart which shows the example of the CZ / ART end processing in one Embodiment of this invention. It is a flowchart which shows the example of the interrupt process executed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the 7-segment LED drive processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of 7-segment LED drive processing in one Embodiment of this invention. It is a flowchart which shows the example of the 7-segment display data generation processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of 7-segment display data generation processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the 7-segment cathode table which is actually referred to on the source program of the 7-segment display data generation processing in one Embodiment of this invention. It is a flowchart which shows the example of the timer update process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the timer update process in one Embodiment of this invention. It is a flowchart which shows the example of the test firing test signal control processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the rotation cylinder braking signal generation processing in one Embodiment of this invention. It is a flowchart which shows the example of the prize signal control processing in one Embodiment of this invention. It is a flowchart which shows the example of the condition device signal control processing in one Embodiment of this invention. It is a flowchart which shows the example of the condition device signal control processing in one Embodiment of this invention. It is a flowchart which shows the example of the combination monitor display management processing in one Embodiment of this invention. It is a flowchart which shows the example of the combination monitor display management processing in one Embodiment of this invention. It is a flowchart which shows the example of the sub-side navigation control processing executed by the sub-control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the player registration process in one Embodiment of this invention. It is a flowchart which shows the example of the history management processing in one Embodiment of this invention. It is a figure which shows the flow of the game in the CT omen in the modification 1 of this invention. It is a figure which shows the correspondence relationship between the internal winning combination and the stop symbol combination in the modification 2 of this invention. It is a figure which shows the correspondence relationship between the main side navigation data and the sub side navigation data in the modification 3 of this invention. It is a figure which shows the correspondence relationship between the pushing order and the locked state in the modification 5 of this invention.

Hereinafter, a pachi-slot machine will be taken as an example of a gaming machine according to an embodiment of the present invention, and its configuration and operation will be described with reference to the drawings. In this embodiment, a pachi-slot machine having a bonus operation function and an ART function will be described.

<Function flow>
First, the functional flow of the pachislot machine will be described with reference to FIG. In the pachislot machine of the present embodiment, a medal is used as a game medium for playing a game. In addition to medals, coins, game balls, game point data, tokens, and the like can also be applied as the game medium.

When a medal is inserted into the pachislot machine by the player and the start lever is operated, one value (hereinafter referred to as a random number value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

The internal lottery means draws a lot based on the extracted random number value, and determines the internal winning combination. This internal lottery means is one of various processing means (processing functions) included in the main control circuit described later. By determining the internal winning combination, the combination of symbols that are allowed to be displayed along the valid line (winning determination line) described later is determined. The types of symbol combinations are those related to "winning" in which benefits such as medal payout, replay operation, bonus operation, etc. are given to the player, and other so-called "missing". Such things are provided. In the following, the role related to the payout of medals will be referred to as a "small role", and the role related to the operation of the replay (replay) will be referred to as a "replay role". In addition, the role related to the operation of the bonus (bonus game) is also referred to as a "bonus role".

Further, when the start lever is operated, a plurality of reels are rotated. After that, when the stop button corresponding to the predetermined reel is pressed by the player, the reel stop control means controls to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do. This reel stop control means is one of various processing means (processing functions) included in the main control circuit described later.

In pachislot, basically, control is performed to stop the rotation of the corresponding reel within a specified time (190 msec) from the time when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within this specified time is referred to as the "number of sliding pieces". Then, in the present embodiment, when the specified period is 190 msec, the maximum number of sliding pieces (maximum number of sliding pieces) is set for four symbols.

When the internal winning combination that allows the combination display of the symbols related to the winning is determined, the reel stop control means usually sets the combination of the symbols to the effective line within the specified time of 190 msec (for 4 symbols). Stop the rotation of the reel so that it is displayed as much as possible along the line. Further, the reel stop control means uses a predetermined time to stop the rotation of the reel so that the combination of symbols whose display is not permitted by the internal winning combination is not displayed along the effective line.

In this way, when all the rotations of the plurality of reels are stopped, the winning determination means determines whether or not the combination of symbols displayed along the effective line is related to winning. This winning determination means is also one of various processing means (processing functions) included in the main control circuit described later. Then, when it is determined by the winning determination means that the combination of the displayed symbols is related to the winning, a privilege such as a medal payout is given to the player. In pachislot, the above series of flows is performed as one game (unit game).

Further, in pachislot, in the flow of the above-mentioned series of game operations, various effects are produced by displaying an image by a display device, outputting light by various lamps, outputting sound by a speaker, or a combination of these. Is done.

Specifically, when the start lever is operated, a random value for production is extracted in addition to the random value used for determining the internal winning combination described above. When the random value for the effect is extracted, the effect content determining means determines the effect to be executed this time from a plurality of types of effect contents associated with the internal winning combination by lottery. This effect content determining means is one of various processing means (processing functions) provided in the sub-control circuit described later.

Next, when the effect content is determined by the effect content determining means, the effect execution means responds in conjunction with each opportunity such as when the reel starts rotating, when each reel stops rotating, and when it is determined whether or not there is a prize. To execute. In this way, in pachislot, for example, by executing the production content associated with the internal winning combination, the opportunity to know or anticipate the determined internal winning combination (in other words, the combination of symbols to be aimed at) is a game. It is provided to the player and can improve the interest of the player.

<Structure of pachislot>
Next, the structure of the pachislot machine according to the embodiment of the present invention will be described with reference to FIGS. 2 to 4.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachislot machine 1.

As shown in FIG. 2, the pachislot machine 1 includes an exterior body (game machine main body) 2. The exterior body 2 has a cabinet 2a for accommodating a reel, a circuit board, and the like, and a front door 2b to which an opening of the cabinet 2a can be opened and closed.

Inside the cabinet 2a, three reels 3L, 3C, 3R (variable display means, display row) are provided side by side in a horizontal row. Hereinafter, each reel 3L, 3C, 3R (main reel) is also referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each reel 3L, 3C, 3R has a reel body formed in a cylindrical shape and a translucent sheet material mounted on the peripheral surface of the reel body. A plurality of (for example, 20) symbols are drawn on the surface of the sheet material at predetermined intervals along the circumferential direction (rotation direction of the reel).

The front door 2b includes a lock 5, a door body 9, a front panel 10, a lumbar panel 12, and a pedestal 13. The door body 9 is attached to the cabinet 2a so as to be openable and closable by using a hinge (not shown). The hinge is provided at the left side end of the door body 9 when viewed from the front side (player side) of the pachislot machine 1. Further, the door body 9 is locked (locked) by using the lock 5 (that is, the front door 2b is maintained in the closed state and is restricted from being opened). The lock 5 is provided at the right side end of the door body 9 when viewed from the front side (player side) of the pachislot machine 1, and the front door is unlocked by using a door key (not shown). 2b is set to the open state. As the locking mechanism (locking device) of the front door 2b, another locking mechanism (for example, a locking device by electronic authentication) can be adopted.

The front panel 10 is provided on the upper part of the door body 9. The front panel 10 is composed of a frame-shaped member having an opening 10a. The opening 10a of the front panel 10 is closed by the display device cover 30, and the display device cover 30 is arranged to face the display device 11 which will be described later and is arranged inside the cabinet 2a.

The display device cover 30 is made of a black translucent synthetic resin. Therefore, the player can visually recognize the image (image) displayed by the display device 11 described later through the display device cover 30. Further, in the present embodiment, by forming the display device cover 30 with a black translucent synthetic resin, the entry of external light into the cabinet 2a is suppressed, and the image (image) displayed by the display device 11 is suppressed. Is clearly visible.

A lamp group 21 is provided on the front panel 10. The lamp group 21 includes, for example, the lamps 21a and 21b provided on the upper part of the front panel 10 when viewed from the player side. Each lamp constituting the lamp group 21 is composed of an LED (Light Emitting Diode) or the like (see LED group 85 in FIG. 7 described later), and lights are turned on and off in a pattern corresponding to the effect content.

The waist panel 12 is provided at a substantially central portion of the door body 9. The waist panel 12 has a decorative panel on which an arbitrary image is drawn, and a light source (LED included in the LED group 85 described later) that emits light for illuminating the decorative panel from the back side.

The pedestal portion 13 is provided between the front panel 10 and the lumbar panel 12. The pedestal portion 13 has a symbol display area 4, various devices to be operated by the player (medal insertion slot 14, MAX bet button 15a, 1 bet button 15b, start lever 16, 3 stop buttons 17L, 17C, 17R, settlement button (not shown), etc.) are provided.

The symbol display area 4 is an area that overlaps the three reels 3L, 3C, 3R when viewed from the front, and is arranged at a position on the player side of the three reels 3L, 3C, 3R, and the three reels. It has a size that makes 3L, 3C, and 3R visible. The symbol display area 4 functions as a display window, and has a configuration in which the reels 3L, 3C, and 3R provided behind the symbol display area 4 can be visually recognized. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

The reel display window 4 is arranged continuously among a plurality of symbols provided on the peripheral surface of each reel when the rotation of the three reels 3L, 3C, 3R provided behind the reel display window 4 is stopped. It is configured so that one symbol is displayed in the frame. That is, when the rotation of the three reels 3L, 3C, and 3R is stopped, one symbol is provided in each of the upper, middle, and lower regions for each reel in the frame of the reel display window 4 (three in total). ) Is displayed (in the frame of the reel display window 4, the design is displayed in the form of 3 rows × 3 columns). Then, in the present embodiment, in the frame of the reel display window 4, a pseudo line (center line) connecting the middle stage region of the left reel 3L, the middle stage region of the middle reel 3C, and the middle stage region of the right reel 3R is formed. It is defined as an effective line for judging whether or not a prize has been won.

The reel display window 4 is formed by the opening of the frame member 31 provided in the pedestal portion 13. Further, a pedestal region having a substantially horizontal plane is provided below the frame member 31 that defines the reel display window 4. When viewed from the player side, the medal insertion slot 14 is provided on the right side of the pedestal area, and the MAX bet button 15a and the 1-bet button 15b are provided on the left side.

The medal slot 14 is provided to receive medals dropped on the pachislot machine 1 from the outside by the player. The medals received from the medal slot 14 are used in one game up to a preset predetermined number (for example, 3), and the number of medals exceeding the predetermined number is deposited inside the pachislot machine 1. (So-called credit function (game medium storage means)).

The MAX bet button 15a and the 1-bet button 15b are provided to determine the number of medals to be used for one game from the medals deposited inside the cabinet 2a. Inside the MAX bet button 15a, a bet button LED (not shown) that lights up when a medal can be inserted is provided. In addition, the settlement button is provided to pull out (discharge) the medals deposited inside the pachislot machine 1 to the outside.

When the player presses the MAX bet button 15a, medals for the number of bets (3) in the unit game are inserted and the effective line is activated. On the other hand, one medal is inserted each time the 1-bet button 15b is pressed once. When the 1-bet button 15b is operated three times, medals for the number of bets (3) in the unit game are inserted and the effective line is activated.

In the following, the operation of the MAX bet button 15a, the operation of the 1-bet button 15b, and the operation of inserting medals into the medal insertion slot 14 (operations of inserting medals to perform a game) are all referred to as "insertion operations".

The start lever 16 is provided to start the rotation of all reels (3L, 3C, 3R). The stop buttons 17L, 17C, and 17R are provided corresponding to the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, and 17R are also referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R, respectively.

Further, an information display 6 is provided at substantially the center of the pedestal region on the substantially horizontal plane below the reel display window 4. The information display 6 is covered with a transparent window cover (not shown).

The information display 6 is a 2-digit 7-segment LED for digitally displaying (notifying) information on the number of medals to be paid out to the player (hereinafter referred to as "the number of medals to be paid out") as a privilege. For digitally displaying (notifying) information such as (hereinafter referred to as "7-segment LED") and the number of medals deposited inside the pachislot 1 (hereinafter referred to as "credit number") to the player. A 2-digit 7-segment LED is provided. In the present embodiment, the 2-digit 7-segment LED for displaying the number of medals to be paid out is a 2-digit 7-segment LED for digitally displaying (notifying) information on the occurrence of an error and the error type to the player. Is also used. Therefore, when an error occurs, the display mode of the 2-digit 7-segment LED for displaying the number of medals to be paid out is switched from the display mode of the number of medals to be paid out to the display mode of the error type information.

Further, the information display 6 is provided with an instruction monitor (not shown) for notifying information on the stop operation necessary for displaying the symbol combination according to the winning combination determined as the internal winning combination along the effective line. ing. The instruction monitor (instruction display) is composed of, for example, a 2-digit 7-segment LED. Then, the instruction monitor notifies the player of the necessary stop operation information by turning on, blinking, or turning off the two-digit 7-segment LED in a manner that uniquely corresponds to the stop operation information to be notified. To do.

The mode that uniquely corresponds to the information of the stop operation to be notified here is, for example, in the case of notifying the push order "1st (performing the first stop operation on the left reel 3L)". When the numerical value "1" is displayed on the instruction monitor and the push order "2nd (perform the first stop operation on the middle reel 3C)" is notified, the numerical value "2" is displayed on the instruction monitor and the push order is displayed. When notifying "3rd (performing the first stop operation on the right reel 3R)", the numerical value "3" is displayed on the instruction monitor. The mode of notifying the information of the stop operation on the instruction monitor (navigation data determined on the main side described later) will be described in detail later with reference to FIG. 63 described later.

As shown in FIG. 7 described later, the information display 6 is electrically connected to the main control board 71 via the door relay terminal board 68 and the game operation display board 81, and the display operation of the information display 6 is mainly performed. It is controlled by the main control circuit 90 described later in the control board 71. Further, the control method of the various 7-segment LEDs described above is dynamic lighting control.

In the pachi-slot machine 1 of the present embodiment, in addition to the instruction monitor controlled by the main control board 71, another means controlled by the sub-control board 72 is used to notify the information of the stop operation. Specifically, the information on the stop operation is notified by the display device 11 described later, which is composed of the projector mechanism 211 and the display unit 212 (see FIGS. 3 and 7 described later) described later.

When such a configuration is applied, the mode of notification in the instruction monitor and the mode of notification in other means controlled by the sub-control board 72 may be different from each other. That is, in the instruction monitor, the information of the stop operation to be notified may be notified in a manner uniquely corresponding to the information of the stop operation, and it is not always necessary to directly notify the information of the stop operation (for example, the numerical value "1" in the instruction monitor. Even if is displayed, it may not be possible to specify the content of the notification depending on the player, so it cannot be said that the notification is direct). On the other hand, in the notification on the sub side (sub control board side) by other means such as the display device 11 described later, the information of the stop operation may be directly notified. For example, when the push order "1st" is notified, the instruction monitor displays a numerical value "1" that uniquely corresponds to the push order to be notified, but other means (for example, the display device 11 or the like) display the left reel 3L. The instruction information for performing the first stop operation may be directly notified to the user.

In the pachi-slot machine 1 having such a configuration, it is possible to notify the information of the necessary stop operation according to the internal winning combination not only by the control of the sub control board 72 but also by the control of the main control board 71. Further, the presence / absence of notification of such stop operation information may be controlled according to the gaming state. For example, the stop operation information may be notified in the ART game state (see FIG. 14 described later) without notifying the stop operation information in the general game state (non-ART game state) described later.

Further, a sub display device 18 is provided on the left side of the reel display window 4 when viewed from the player side. As shown in FIG. 2, the sub-display device 18 is provided so as to stand substantially perpendicular to the pedestal region of the pedestal portion 13 in a substantially horizontal plane in the front portion of the door body 9. The sub-display device 18 is composed of a liquid crystal display and an organic EL (Electro-Luminescence) display, and displays various information.

Further, a touch sensor 19 is provided on the display surface of the sub display device 18 (see FIG. 7 described later). The touch sensor 19 operates according to a predetermined operating principle such as a capacitance method, and when it receives an operation of a player, it outputs a signal corresponding to the operation as touch input information. The pachi-slot machine 1 of the present embodiment has a function of enabling the display of the sub-display device 18 to be switched according to the player's operation (touch input information output from the touch sensor 19) received via the touch sensor 19. Has. The sub display device 18 is controlled by the sub control board 72 (see FIG. 7 described later) based on the touch input information output from the touch sensor 19.

At the lower part of the door body 9, a medal payout outlet 24, a medal tray 25, two speaker holes 20L, 20R, and the like are provided. The medal payout outlet 24 guides the medals discharged by driving the medal payout device 51, which will be described later, to the outside. The medal tray 25 stores medals discharged from the medal payout outlet 24. Further, sound effects such as sound effects and music corresponding to the contents of the production are output from the two speaker holes 20L and 20R.

[Internal structure]
Next, the internal structure of the pachislot machine 1 will be described with reference to FIGS. 3 and 4. FIG. 3 is a diagram showing the internal structure of the cabinet 2a, and FIG. 4 is a diagram showing the internal structure of the front door 2b on the back surface side.

As shown in FIG. 3, the cabinet 2a has a top plate 27a, a bottom plate 27b, left and right side plates 27c and 27d, and a back plate 27e. A display device 11 is arranged in the upper part of the cabinet 2a.

The display device 11 has a projector mechanism 211 and a box-shaped projected member 212a on which the image light projected from the projector mechanism 211 is projected, and displays an image by projection mapping. Specifically, the display device 11 generates image light based on the position (projection distance, angle, etc.) and shape of the projected member 212a, which is a three-dimensional object, and the image light is emitted by the projector mechanism 211 to the projected member. It is projected on the surface of 212a. By providing such an effect function, it is possible to perform an advanced and powerful effect. Further, although not shown in FIG. 3, another projected member having a curved display surface is provided on the back side of the box-shaped projected member 212a, and one of the projected members is provided depending on the gaming state. , Used as a screen on which video light is projected. Therefore, the inside of the cabinet 2a is also provided with a function (not shown) for switching the projected member according to the gaming state.

A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are arranged in the lower part of the cabinet 2a.

The hopper device 51 is attached to the central portion of the bottom plate 27b in the cabinet 2a. The hopper device 51 has a structure capable of accommodating a large number of medals and ejecting them one by one. The hopper device 51 pays out medals when the number of stored medals exceeds, for example, 50, or when the settlement button is pressed and the settlement of medals is executed. Then, the medals paid out by the hopper device 51 are discharged from the medal payout outlet 24 (see FIG. 2).

The medal auxiliary storage 52 stores medals overflowing from the hopper device 51. The medal auxiliary storage 52 is arranged on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. Further, the medal auxiliary storage 52 is detachably attached to the bottom plate 27b of the cabinet 2a.

The power supply device 53 includes a power supply switch 53a and a power supply board 53b (power supply means) (see FIG. 7 described later). The power supply device 53 is arranged on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side plate 27c. The power supply device 53 converts the AC voltage 100V power supplied from the sub power supply device (not shown) into the DC voltage power required by each part, and supplies the converted power to each part.

Further, above the power supply device 53 in the cabinet 2a, a sub-control board case 57 for accommodating the sub-control board 72 (see FIG. 7 described later) is arranged. A sub-control circuit 200 (see FIG. 10 to be described later) described later is mounted on the sub-control board 72 housed in the sub-control board case 57. The sub-control circuit 200 is a circuit that controls the execution of an effect by displaying an image or the like. The specific configuration of the sub-control circuit 200 will be described later.

The sub-relay board 61 is arranged above the sub-control board case 57 in the cabinet 2a. The sub-relay board 61 is a relay board on which wiring for connecting the sub-control board 72 and the main control board 71, which will be described later, is mounted. Further, the sub-relay board 61 is a relay board on which wiring for connecting the sub-control board 72 and the boards arranged around the sub-control board 72, various device units (units), and the like is mounted.

Further, although not shown in FIG. 3, a cabinet-side relay board 44 (see FIG. 7 described later) is arranged in the cabinet 2a. The cabinet-side relay board 44 includes a main control board 71 (see FIG. 7 described later), a hopper device 51, a game medal auxiliary storage switch 75 (see FIG. 7 described later), and a medal payout count switch (not shown). It is a relay board on which wiring for connecting to and is mounted.

As shown in FIG. 4, a middle door 41 is arranged at the center of the front door 2b on the back surface side, and the reel display window 4 (see FIG. 2) is attached so as to be openable and closable from the back side. Although not shown in FIG. 4, three reels 3L, 3C, and 3R are attached to the reel display window 4 side of the middle door 41, and the main control is on the side opposite to the reel display window 4 side of the middle door 41. A main control board case 55 in which the board 71 (see FIG. 7 described later) is housed is attached. A stepping motor (not shown) is connected to the three reels 3L, 3C, and 3R via gears having a predetermined reduction ratio. Further, the main control board case 55 is made of a transparent member, and when the front door 2b is in the open state, predetermined ratio information displayed by the role ratio monitor 95 (ratio display means) described later can be visually recognized. It is configured to be.

The main control board 71 housed in the main control board case 55 has a main control circuit 90 (see FIG. 9 described later) described later. The main control circuit 90 (main control means) is a circuit that controls the main flow of the game in the pachislot machine 1, such as determining the internal winning combination, rotating and stopping the reels 3L, 3C, and 3R, and determining whether or not there is a prize. .. Further, in the present embodiment, for example, control such as lottery processing of presence / absence of ART determination, display processing of navigation information on the instruction monitor, transmission processing of various test signals, display processing of ratio information on the role ratio monitor 95, and the like is also performed. This is done by the main control circuit 90. The specific configuration of the main control circuit 90 will be described later.

Speakers 65L and 65R are arranged below the middle door 41 on the back surface side of the front door 2b. The speakers 65L and 65R are arranged at positions facing the speaker holes 20L and 20R (see FIG. 2), respectively.

A selector 66 and a door open / close monitoring switch 67 are arranged above the speaker 65L. The selector 66 is a device for selecting whether or not the material, shape, and the like of medals are appropriate, and guides the appropriate medals inserted into the medal insertion slot 14 to the hopper device 51. A medal sensor (game medium detecting means: not shown) for detecting that a proper medal has passed is provided on the path through which the medal passes in the selector 66.

The door open / close monitoring switch 67 is arranged diagonally to the lower left of the selector 66 when the front door 2b is viewed from the back surface side. The door open / close monitoring switch 67 outputs a security signal for notifying the open / close of the front door 2b to the outside of the pachislot machine 1.

Further, although not shown in FIG. 4, a door relay terminal plate 68 is arranged on the back surface of the front door 2b, which is a region opened and closed by the middle door 41 and below the reel display window 4 (FIG. 4 described later). 7). The door relay terminal board 68 includes a main control board 71 in the main control board case 55, various buttons and switches, a sub relay board 61, a selector 66, a game operation display board 81, a first interface board 301 for a testing machine, and the like. This is a relay board on which wiring for connecting each of the second interface boards 302 for a testing machine is mounted. Examples of the various buttons and switches include the MAX bet button 15a, the 1-bet button 15b, the door open / close monitoring switch 67, the BET switch 77 described later, the start switch 79, and the like.

<Display example of sub display device>
Here, various display screens displayed on the sub-display device 18 will be described with reference to FIGS. 5A to 5E. 5A is a diagram showing a top screen 221 displayed on the sub display device 18, and FIG. 5B is a diagram showing a menu screen 222 displayed on the sub display device 18. 5C to 5E are diagrams showing game information screens 223, 224, and 225 displayed on the sub display device 18.

Various display screens are displayed on the sub-display device 18 by a player's touch operation, and as shown in FIGS. 5A to 5E, various display screens including a top screen 221 and a menu screen 222 and a game information screen 223, 224, 225 are included. The display screen is displayed. These display screens are switched based on the player's operation signal received via the touch sensor 19.

The top screen 221 is an initial screen of the display screens displayed on the sub display device 18, and the top screen 221 displays the “MENU” button 221a and the outline game history 221b. The "MENU" button 221a is an operation button for calling the menu screen 222 shown in FIG. 5B, and when a predetermined operation (for example, tap) by the player is performed on the "MENU" button 221a, the menu screen 222 is called. Is done. Further, on the top screen 221, a part of the game history (summary game history) of the pachislot machine 1 is displayed as the summary game history 221b. In the present embodiment, for example, the number of bonuses, the number of ARTs, and the number of games (number of games) are displayed as the outline game history 221b.

The menu screen 222 is a screen for displaying a menu that can be displayed on the sub display device 18, and on the menu screen 222, a “back” button 222a, a “registration” button 222b, an “explanation” button 222c, and an “array dividend” button 222d , The "reach eye" button 222e, the "WEB site" button 222f, and the "volume" button 222g are displayed. The "back" button 222a is an operation button for calling the top screen 221. When the player operates the "back" button 222a, the top screen 221 is called. Further, the "register" button 222b to the "volume" button 222g are operation buttons for calling the display screen of the corresponding menu content, and when the player operates each button, the corresponding menu content is displayed. The display screen is called.

For example, when the "register" button 222b is operated by the player on the menu screen 222, a registration screen (not shown) for registering the player during the game is called on the display screen of the sub display device 18. In recent pachislot machines, a service is widely provided in which a player is registered for each model and various information such as the achievement status of a predetermined mission is managed from the past game history of the player. The registration screen called by the "registration" button 222b is a display screen for registering a player when receiving the provision of this service.

Further, for example, when the "explanation" button 222c is operated by the player on the menu screen 222, the explanation screen (not shown) of the pachislot machine 1 is called to the display screen of the sub display device 18. The information displayed on the explanation screen includes, for example, an explanation about the specifications of the pachislot machine 1 such as a bonus winning probability and an ART winning probability for each set value, and an introduction explanation of a character appearing in the production of the pachislot machine 1.

Further, for example, when the "array payout" button 222d is operated by the player on the menu screen 222, the array payout screen (not shown) of the pachislot machine 1 is called on the display screen of the sub display device 18. On the array payout screen, for example, the correspondence between the combination of symbols judged to be winning in Pachislot 1 and the privilege when it is judged to be winning (dividend table) and drawn on each reel 3L, 3C, 3R. The symbol sequence (reel arrangement) and the like are displayed.

Further, for example, when the "reach eye" button 222e is operated by the player on the menu screen 222, the reach eye screen (not shown) of the pachislot machine 1 is called on the display screen of the sub display device 18. On the reach-eye screen, information on a symbol combination called "reach-eye" set in the pachi-slot machine 1 is displayed. The symbol combination referred to as "reach eyes" is a symbol combination to which a special privilege is given by displaying the symbol combination along the effective line. In the pachislot machine 1 of the present embodiment, the figure described later The symbol combination corresponding to the abbreviation "reach eye lip" shown in the content column of the winning operation flag storage area of FIGS. 28 to 30 is applicable. Then, in the present embodiment, when the symbol combination related to the "reach eye lip" is displayed along the effective line, a state advantageous to the player (for example, a bonus state, a normal ART or CT (FIG. 14 described later)) is thereafter. It is confirmed that the transition to)) will be made.

Further, for example, when the "WEB site" button 222f is operated by the player on the menu screen 222, the WEB introduction screen (not shown) of the pachislot machine 1 is called on the display screen of the sub display device 18. On the WEB introduction screen, for example, a two-dimensional code (for example, QR code (registered trademark)) indicating the URL of an arbitrary WEB site such as a special WEB site provided for each model of pachislot 1 or a WEB site of a pachislot 1 manufacturer). Is displayed. The player can access the corresponding WEB site by reading the two-dimensional code displayed on the WEB introduction screen with a mobile phone or the like.

Further, for example, when the "volume" button 222g is operated by the player on the menu screen 222, a volume adjustment screen (not shown) capable of adjusting the volume of the sound output from the speakers 65L and 65R is a sub display device. Called to the display screen of 18. The player can adjust the volume of the effect sound of the pachi-slot machine 1 via the volume adjustment screen.

Since the sub-display device 18 is provided separately from the above-mentioned display device 11 (projector mechanism 211 and display unit 212), it can be controlled separately from the display device 11. Therefore, in the pachi-slot machine 1 of the present embodiment, the display screen of the sub-display device 18 can be switched by the operation of the player even during the game (during the execution of the effect by the display device 11). As a result, for example, when the player wants to know the character appearing in the production of the display device 11, the player operates the "explanation" button 222c to call the explanation screen, and the inter-characters. Information such as the relationship between the two can be grasped during the game. Also, for example, when the player wants to grasp the symbol that should be used as a guide for winning the rare role during the reel rotation when the so-called "rare role" is won during the game, the player may ask. By operating the "arrangement payout" button 222d to call the arrangement payout screen, the reel arrangement can be grasped.

The game information screens 223, 224, and 225 are display screens that display detailed game history information including an outline game history to be displayed on the top screen 221 of the game history of the pachislot machine 1.

On the game information screen 223, a "back" button 223a, a "MENU" button 223b, a "previous" button 223c, a "next" button 223d, and a game history 223e are displayed. The "back" button 223a and the "MENU" button 223b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively, and are supported by the player operating each button. The display screen is called. Further, the "previous" button 223c and the "next" button 223d are operation buttons for switching the game information screen in a predetermined order, and when the "previous" button 223c is operated by the player, the display screen is displayed. Is switched from the game information screen 223 to the game information screen 225, and when the "Next" button 223d is operated by the player, the display screen is switched from the game information screen 223 to the game information screen 224. Further, as the game history 223e, as shown in FIG. 5C, the number of games (number of games), the number of bonuses, the number of ARTs, and the number of CZs (chance zones) are displayed.

On the game information screen 224, a "back" button 224a, a "MENU" button 224b, a "previous" button 224c, a "next" button 224d, and a game history 214e are displayed. The "back" button 224a and the "MENU" button 224b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively, and are supported by the player operating each button. The display screen is called. Further, the "previous" button 224c and the "next" button 224d are operation buttons for switching the game information screen in a predetermined order, and when the "previous" button 224c is operated by the player, the display screen is displayed for the game. When the information screen 224 is switched to the game information screen 223 and the "Next" button 224d is operated by the player, the display screen is switched from the game information screen 224 to the game information screen 225. Further, as the game history 224e, the number of times of entry and the number of successes of CZ (chance zone) described later are displayed. As will be described later, in the present embodiment, three types of CZs, CZ1, CZ2, and CZ3, are provided as CZs. Therefore, as the game history 224e, as shown in FIG. 5D, the number of rushes and the number of successes of each of CZ1 to CZ3 are displayed.

On the game information screen 225, a "back" button 225a, a "MENU" button 225b, a "previous" button 225c, a "next" button 225d, and a game history 225e are displayed. The "back" button 225a and the "MENU" button 225b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively, and are supported by the player operating each button. The display screen is called. Further, the "previous" button 225c and the "next" button 225d are operation buttons for switching the game information screens in a predetermined order, and when the "previous" button 225c is operated by the player, the display screen is displayed. Is switched from the game information screen 225 to the game information screen 224, and when the "Next" button 225d is operated by the player, the display screen is switched from the game information screen 225 to the game information screen 223. Further, as the game history 225e, as shown in FIG. 5E, the number of winnings of the small winning combination and the winning probability (fraction of the numerator of 1) are displayed.

As a display screen switching method displayed on the sub-display device 18, for example, a method of switching based on a tap operation on an operation button displayed on each display screen may be adopted, or, for example, A method of switching based on a swipe operation on the display screen may be adopted.

<Various switching functions of the display screen of the sub display device>
Next, various switching functions of the display screen of the sub-display device 18 in the pachi-slot machine 1 of the present embodiment will be described.

[Example of transition of display screen of sub display device]
First, a transition example (switching mode) of the display screen of the sub-display device 18 in the pachi-slot machine 1 of the present embodiment will be described with reference to FIGS. 6A and 6B. Note that FIG. 6A is a diagram showing a transition example of the display screen of the sub-display device 18 in a situation where the player registration state is not set, and FIG. 6B is a diagram showing a sub-display in a situation where the player registration state is set. It is a figure which shows the transition example of the display screen of the apparatus 18.

In the situation where the player registration state is not set, as shown in FIG. 6A, the display screen of the sub display device 18 transitions between the top screen 221 and the menu screen 222, and from the menu screen 222 and the menu screen 222. Transitions are possible only to and from various possible display screens, and the transitions between these display screens are controlled by the sub-control board 72 (sub-CPU 201 described later). For example, the sub-control board 72 is placed between the top screen 221 and the menu screen 222 based on a touch operation (for example, a tap operation for a predetermined button or a swipe operation on the display screen) acquired via the touch sensor 19. Switch the display screen. However, in the situation where the player registration state is not set, the sub-control board 72 controls so that the game information screens 223, 224, and 225 cannot be displayed. That is, in the situation where the player registration state is not set, the player cannot display the game information screens 223, 224, and 225 on the sub display device 18.

On the other hand, in the situation where the player registration state is set, as shown in FIG. 6B, the display screen of the sub display device 18 is between the top screen 221 and the menu screen 222, and the menu screen 222 and the menu screen 222. In addition to the transition between the various display screens that can be transitioned from, the transition between the menu screen 222 and the game information screens 223, 224, 225 is also possible, and the transition between these display screens is the sub-control board 72 (subs described later). It is controlled by CPU201). That is, the sub-control board 72 is not only between the top screen 221 and the menu screen 222, but also between the top screen 221 and the menu screen 222 and the game information screen based on the touch operation acquired via the touch sensor 19. The display screen can also be switched between 223, 224, and 225. Therefore, in the present embodiment, when the player registration state is set, the player can display the game information screens 223, 224, and 225 on the sub display device 18.

As shown in FIG. 6B, the transition order of the display screens between the top screen 221 and the menu screen 222 and the game information screens 223, 224, and 225 is arbitrary. Therefore, for example, the top screen 221 may be configured to directly transition to the game information screens 223, 224, 225, or the top screen 221 to the game information screens 223, 224, 225 only via the menu screen 222. It may be configured so that it can be transitioned.

In the pachislot machine 1 of the present embodiment, the top screen 221 can be transitioned to the game information screen 223, 224, 225 only via the menu screen 222 (the top screen 221 cannot be directly transitioned to the game information screen 223, 224, 225). ) Is adopted. In the pachislot machine 1 of the present embodiment, on the menu screen 222, the player swipes the display screen (not the menu selection operation) to display the display screen from the menu screen 222 to the game information screens 223 and 224. , 225 can be transitioned.

In the present embodiment, the game information screens 223, 224, and 225 are display screens provided completely independently of the menu screen 222. That is, in the pachislot machine 1 of the present embodiment, the game history, which is information indicating the result of the game in which the player has a strong interest during the game, is independent as information unrelated to the result of the game such as the payout arrangement and the volume control. To display. Then, in the present embodiment, in the situation where the player registration state is set, the game information screens 223, 224, and 225 can be displayed without the player performing a menu selection operation on the menu screen 222. .. Therefore, in the present embodiment, when the player registration state is set, it is possible to easily access the emotional game history information desired by the player.

Further, in the present embodiment, in the menu selection operation for the menu screen 222, the display screen cannot be changed to the game information screens 223, 224, 225, and the swipe operation for the menu screen 222 (specified in the menu display). The display screen cannot be changed to the game information screens 223, 224, and 225 unless the operation is not performed. Therefore, in the pachi-slot machine 1 of the present embodiment, the swipe operation for transitioning the display screen to the game information screens 223, 224, 225 can be treated as a hidden command in the situation where the player registration state is set. In this case, from the player's own knowledge of pachislot 1, more detailed game history information that cannot be seen by other players with little knowledge can be seen, so that the player can see more detailed game history information than the other players. It is possible to play the game advantageously, and as a result, it can be expected that the player actively plays the game.

[Display switching function from the game information screen to the top screen]
The pachi-slot machine 1 of the present embodiment has a function of shifting the display screen of the sub-display device 18 from the game information screens 223, 224, 225 to the top screen 221 manually or automatically by the player. Specifically, in the present embodiment, when the "back" button is operated on the game information screens 223, 224, 225, the display screen transitions from the game information screen 223, 224, 225 to the top screen 221 (manual transition). function). Further, in the present embodiment, when a predetermined condition is satisfied while the game information screens 223, 224, and 225 are displayed, the display screen automatically changes to the top screen 221 regardless of the player's operation. Transition (automatic transition function).

More specifically, in the pachislot machine 1, while the game information screens 223, 224, and 225 are displayed, the insertion operation (operation to the MAX bet button 15a, operation to the 1 bet button 15b, and the medal insertion slot 14 is performed. When the operation of inserting medals) is performed, the display screen of the sub display device 18 automatically transitions to the top screen 221. In addition, in a gaming state (high lip state) in which the probability that the replay combination is determined as the internal winning combination is high, such as the ART gaming state, medals are automatically inserted due to the operation of the replay accompanying the replay combination winning. As a result, in the high lip state, the opportunity to display the game information screens 223, 224, and 225 may be limited. Therefore, in the pachi-slot machine 1 of the present embodiment, when a medal is automatically inserted by the operation of the re-game, the display screen is automatically displayed on the game information screen 223, not by the operation of inserting the medal but by the start operation. , 224, 225 transitions to the top screen 221.

That is, in the present embodiment, when the re-game is activated and the game information screens 223, 224, 225 are displayed, the display screen is automatically changed to the game information screens 223, 224, triggered by the start operation. , 225 transitions to the top screen 221. On the other hand, when the re-game operation is not performed, the display screen automatically transitions from the game information screen 223, 224, 225 to the top screen 221 triggered by the input operation.

[Display switching function from the menu content display screen to the top screen (or menu screen)]
In the pachi-slot machine 1 of the present embodiment, the display screen of the sub-display device 18 can be changed by a menu selection operation on the menu screen 222, and various menu content display screens (registration screen, explanation screen, array dividend screen, reach screen, WEB introduction). It has a function of manually or automatically transitioning from the screen (screen and volume adjustment screen) to the top screen 221 (or menu screen 222). Specifically, in the present embodiment, when a predetermined button (for example, the "return to TOP" button) is operated on the menu content display screen, the display screen transitions from the menu content display screen to the top screen 221 (). Manual transition function). Further, in the present embodiment, when a specific button (for example, a "back" button) is operated on the menu content display screen, the display screen transitions from the menu content display screen to the menu screen 222 (manual transition). function).

Further, in the present embodiment, when a predetermined time elapses while the menu content display screen is displayed, the display screen automatically changes to the top screen 221 (or menu screen 222) regardless of the operation of the player. Transition (automatic transition function). At this time, the predetermined time that triggers the automatic transition to the top screen 221 (or the menu screen 222) differs depending on the type of the menu content display screen currently displayed. For example, if the volume adjustment screen for adjusting the volume output from the pachislot machine 1 is displayed for a long time, not only the volume may be adjusted to an unintended volume due to an erroneous operation, but also another player may be affected by the erroneous operation. It may be uncomfortable. Therefore, the volume adjustment screen is set to automatically transition to the top screen 221 (or menu screen 222) in a shorter time than other menu content display screens. On the other hand, the registration screen is set to automatically transition to the top screen 221 (or menu screen 222) in a longer time than other menu content display screens in order to facilitate registration of players. ..

That is, on each menu content display screen, an elapsed time (automatic transition time) that triggers an automatic transition to the top screen 221 (or menu screen 222) is appropriately set according to the type of the menu content display screen. , The volume adjustment screen is set with an automatic transition time shorter than that of other menu content display screens, and the registration screen is set with an automatic transition time longer than that of other menu content display screens.

[Menu operation enable / disable selection function]
In the pachi-slot machine 1 of the present embodiment, the display screen of the sub-display device 18 is changed from the menu screen 222 to the registration screen, the explanation screen, the arrangement payout screen, the reach eye screen, the WEB introduction screen, and the volume adjustment screen. A person can perform various operations according to these menu content display screens, and can confirm various information. It should be noted that a function (a function for selecting whether or not the menu can be operated) may be provided so that the function that the player can select the menu can be restricted according to the setting on the game store side.

For example, the display screen may not be transitioned from the menu screen 222 to the volume control screen (for example, the "volume" button 222g is not displayed on the menu screen 222) by the setting on the game store side. In this case, it is possible to prevent the player from adjusting the volume.

<Control system provided by pachislot>
Next, the control system included in the pachi-slot machine 1 will be described with reference to FIG. 7. FIG. 7 is a circuit block diagram showing the configuration of the control system of the pachislot machine 1.

The pachi-slot machine 1 has a main control board 71 provided on the middle door 41 and a sub control board 72 provided on the front door 2b. Further, the pachi-slot machine 1 has a reel relay terminal board 74, a setting key type switch 54 (setting switch), and a cabinet-side relay board 44 connected to the main control board 71. Further, the pachi-slot machine 1 has an external centralized terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, a reset switch 76, and a power supply device 53 connected to the main control board 71 via a cabinet-side relay board 44. Since the configuration of the hopper device 51 has been described above, the description thereof will be omitted here.

The reel relay terminal plate 74 is arranged inside the reel main body of each reel 3L, 3C, 3R. The reel relay terminal plate 74 is electrically connected to a stepping motor (not shown) of each reel 3L, 3C, 3R, and relays a signal output from the main control board 71 to the stepping motor.

The setting key type switch 54 is provided on the main control board case 55. The setting key type switch 54 is used when changing the setting of the pachi-slot 1 (settings 1 to 6) or when confirming the setting of the pachi-slot 1.

The cabinet-side relay board 44 is a relay board on which wiring for connecting the main control board 71, the external centralized terminal board 47, the hopper device 51, the medal auxiliary storage switch 75, the reset switch 76, and the power supply device 53 is mounted. Is. The external centralized terminal plate 47 is provided to output signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachislot machine 1. The medal auxiliary storage switch 75 is provided in the medal auxiliary storage 52, and detects whether or not the medal auxiliary storage 52 is full of medals. The reset switch 76 is used, for example, when changing the setting of the pachislot machine 1.

The power supply device 53 includes a power supply board 53b and a power supply switch 53a connected to the power supply board 53b. The power switch 53a is pressed when supplying the necessary power to the pachi-slot machine 1. The power supply board 53b is connected to the main control board 71 via the cabinet side relay board 44, and is also connected to the sub control board 72 via the sub relay board 61.

Further, the pachi-slot machine 1 has a selector 66, a door open / close monitoring switch 67, a BET switch 77, and a settlement switch 78, which are connected to the main control board 71 via the door relay terminal plate 68 and the door relay terminal plate 68. It has a start switch 79, a stop switch board 80, a game operation display board 81, an auxiliary relay board 61, a first interface board 301 for a testing machine, and a second interface board 302 for a testing machine. Since the selector 66, the door open / close monitoring switch 67, and the sub-relay board 61 have been described above, their description will be omitted here.

The BET switch 77 (throwing operation detecting means) detects that the MAX bet button 15a or the 1-bet button 15b is pressed by the player. The settlement switch 78 detects that the settlement button (not shown) has been pressed by the player. The start switch 79 (start operation detecting means) detects that the start lever 16 has been operated by the player (start operation).

The stop switch board 80 (stop operation detecting means) includes a circuit for stopping the rotating main reel and a circuit for displaying the stoptable main reel by an LED or the like. Further, the stop switch board 80 is provided with a stop switch (not shown). The stop switch detects that each of the stop buttons 17L, 17C, 17R is pressed by the player (stop operation).

The game operation display board 81 is connected to the information display (7-segment display) 6 and the LED 82. The LED 82 has, for example, three LEDs (hereinafter, "first LED" to "1st LED") for displaying the number of inserted medals, which are lit according to the number of medals inserted in this game (hereinafter referred to as "the number of inserted medals"). An LED that lights a mark indicating that medals can be inserted, a mark indicating the start of a game, a mark for replaying a game, etc., based on a signal input from the game operation display board 81 (referred to as "third LED"). Etc. are included. In the first LED to the third LED (display means), when one medal is inserted, the first LED lights up, and when two medals are inserted, the first and second LEDs light up, and three medals (game). When the number of startable medals is turned on, the first LED to the third LED are turned on. Since the information display 6 has been described above, the description thereof will be omitted here.

Both the first interface board 301 for the testing machine and the second interface board 302 for the testing machine are relay boards used when outputting various signals related to the game to the testing machine in the certification test (test firing test) of the pachislot 1 (test firing test). Since these relay boards are not mounted on the Pachislot 1 as a release product for sale, the main control circuit 90 of the main control board 71 for sale includes the first interface board 301 for the testing machine and the testing machine. Various electronic components required for connecting to the second interface board 302 for use are also not mounted). For example, a test signal for controlling a main operation related to a game (for example, internal lottery, reel stop control, etc.) is output via a first interface board 301 for a testing machine, and is determined by, for example, a main control board 71. The test signal and the like related to the pushed order navigation are output via the second interface board 302 for the testing machine.

The sub-control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub-relay board 61. Further, the pachi-slot machine 1 has a speaker group 84, an LED group 85, a 24h door open / close monitoring unit 63, a touch sensor 19, and a display unit 212 connected to the sub-control board 72 via the sub-relay board 61. Since the touch sensor 19 has been described above, the description thereof will be omitted here.

The speaker group 84 includes speakers 65L and 65R and various speakers (not shown). The LED group 85 includes a lamp group 21 provided on the front panel 10, a light source that emits light for illuminating the decorative panel of the lumbar panel 12 from the back side, and the like. The 24h door open / close monitoring unit 63 stores the open / close history information of the middle door 41. Further, the 24h door open / close monitoring unit 63 outputs a signal for displaying an error by the display device 11 to the sub control board 72 (sub control circuit 200) when the middle door 41 is opened. The display unit 212 includes, for example, a projected member 212a constituting the display device 11 and another projected member having a curved display surface provided on the back side of the projected member 212a.

Further, the pachi-slot machine 1 has a ROM cartridge board 86 and a liquid crystal relay board 87 connected to the sub-control board 72. The ROM cartridge board 86 and the liquid crystal relay board 87 are housed in the sub-control board case 57 together with the sub-control board 72.

The ROM cartridge board 86 is a board for managing various control programs executed by the sub CPU 201, image (video) for production, audio (speaker group 84), light (LED group 85), and communication data. .. The liquid crystal relay board 87 is a board that relays the connection wiring between the sub-control board 72, the projector mechanism 211 that constitutes the display device 11, and the sub-display device 18. Since the projector mechanism 211 and the sub-display device 18 have been described above, their description will be omitted here.

<Main control circuit>
Next, the configuration of the main control circuit 90 mounted on the main control board 71 will be described with reference to FIG. FIG. 8 is a block diagram showing a configuration example of the main control circuit 90 of the pachislot machine 1.

The main control circuit 90 includes a microprocessor 91, a clock pulse generation circuit 92, a power management circuit 93, a switching regulator 94 (power supply means), and a role ratio monitor 95 (ratio display means).

The microprocessor 91 is a microprocessor with a security function for a game machine. In the microprocessor 91 of the present embodiment, as will be described later, various instruction codes specific to the microprocessor 91 that can be specified in the source program (for example, "LDQ" instruction and the like described later: hereinafter, "main CPU 101". Dedicated instruction code ") is provided. In the present embodiment, the processing efficiency and the reduction of the program capacity are realized by using the instruction code dedicated to the main CPU 101. The internal configuration of the microprocessor 91 will be described in detail with reference to FIG. 9 described later, and the instruction code dedicated to the main CPU 101 provided in the microprocessor 91 will be described in detail in various processes executed by the main control circuit described later. To do.

The clock pulse generation circuit 92 generates a clock pulse signal for operating the main CPU, and outputs the generated clock pulse signal to the microprocessor 91. The microprocessor 91 executes a control program based on the input clock pulse signal.

The power management circuit 93 manages fluctuations in the DC 12V power supply voltage supplied from the power supply board 53b (see FIG. 7). Then, the power management circuit 93 outputs a reset signal to the "XSRST" terminal of the microprocessor 91, for example, when the power is turned on (when the power supply voltage exceeds the starting voltage value (10V) from 0V). When a power failure occurs (when the power supply voltage falls below the power failure voltage value (10.5V) from 12V), the power failure detection signal is output to the "XINT" terminal of the microprocessor 91. That is, the power management circuit 93 is a means (starting means) for outputting a reset signal (starting signal) to the microprocessor 91 when the power is turned on, and a power failure detection signal (power failure signal) to the microprocessor 91 when a power failure occurs. Also serves as a means for outputting (power failure means).

The switching regulator 94 is a DC / DC conversion circuit, generates a DC drive voltage (power supply voltage of DC 5 V) of the microprocessor 91, and outputs the generated DC drive voltage to the “VCC” terminal of the microprocessor 91.

As shown in the configuration example in FIG. 8, the role ratio monitor 95 is composed of, for example, a 4-digit 7-segment LED, and is a calculation circuit described later with respect to the aggregation result related to the game information aggregated by the main CPU 101 described later. 107 performs a predetermined ratio calculation, and displays the result of the ratio calculation as ratio information. In the present embodiment, a plurality of types of ratio calculations are performed as predetermined ratio calculations (see FIGS. 155 to 162 described later), and the combination ratio monitor 95 sequentially displays a plurality of types of ratio information based on the results. (See FIGS. 180 and 181 described below).

In the upper two digits of the role ratio monitor 95, "abbreviation" which is the type information indicating the type of the ratio information is displayed, and in the lower two digits, the "ratio" which is the ratio information corresponding to the type information. Is displayed. For example, when "7" is displayed in the first digit (abbreviated 10th place) of the role ratio monitor 95 and "U" is displayed in the second digit (abbreviated 1st place) (that is, the abbreviation "7U"). (When is displayed), in the lower two digits of the combination ratio monitor 95, the ART function that occupies the predetermined total number of games (175,000 times) is activated (that is, advantageous for the player) as the ratio information. The ratio of the number of games (advantageous section ratio) of the advantageous section in which the procedure of the stop operation was notified is displayed. Specifically, when the effective section ratio is 10%, "1" is displayed in the third digit (ratio 10's place) and "0" is displayed in the fourth digit (ratio 1's place). Is displayed.

Further, for example, when "6" is displayed in the first digit (abbreviated 10th place) of the role ratio monitor 95 and "Y" is displayed in the second digit (abbreviated 1st place) (that is, abbreviation). (When "6Y" is displayed), the lower two digits of the combination ratio monitor 95 indicate the combination of the number of game media paid out during the specific total number of games (6000 times) as the ratio information. Object continuous actuating device (BB in the present embodiment. In addition, when the accessory continuous actuating device (MB) in which the second type special accessory (CB) is continuously operated is mounted, it is included. The same shall apply hereinafter. ) Is activated and the ratio of the number of game media paid out (medium-time continuous combination ratio) is displayed. Specifically, when the medium-time continuous combination ratio is 59%, "5" is displayed in the third digit (ratio 10's place) and "9" is displayed in the fourth digit (ratio 1's place). Is displayed.

Further, for example, when "7" is displayed in the first digit (abbreviated 10th place) of the role ratio monitor 95 and "Y" is displayed in the second digit (abbreviated 1st place) (that is, abbreviation). (When "7Y" is displayed), in the lower two digits of the role ratio monitor 95, as ratio information, all of the number of game media paid out during a specific total number of games (6000 times). (BB in this embodiment. In addition to the above-mentioned MB, when the above-mentioned first-class special accessory (RB) is mounted alone, the above-mentioned second-class special accessory (CB) is installed. When mounted alone, when a normal accessory (SB) is mounted, all of them are included. The same shall apply hereinafter) and the ratio of the number of game media paid out (medium time role) Object ratio) is displayed. Specifically, when the medium-time bonus ratio is 59%, "5" is displayed in the third digit (ratio 10's place) and "9" is displayed in the fourth digit (ratio 1's place). Is displayed.

Further, for example, when "6" is displayed in the first digit (abbreviated 10th place) of the role ratio monitor 95 and "A" is displayed in the second digit (abbreviated 1st place) (that is, abbreviation). (When "6A" is displayed), the lower two digits of the combination ratio monitor 95 indicate the combination of the number of game media paid out during the predetermined total number of games (175,000 times) as the ratio information. The ratio of the number of game media paid out by operating the object continuous operation device (total continuous combination ratio) is displayed. Specifically, when the total joint combination ratio is 25%, "2" is displayed in the third digit (ratio 10's place) and "5" is displayed in the fourth digit (ratio 1's place). Is displayed.

Further, for example, when "7" is displayed in the first digit (abbreviated 10th place) of the role ratio monitor 95 and "A" is displayed in the second digit (abbreviated 1st place) (that is, abbreviation). (When "7A" is displayed), in the lower two digits of the role ratio monitor 95, as ratio information, all of the number of game media paid out during the predetermined total number of games (175,000 times). The ratio of the number of game media paid out by operating the accessory (total accessory ratio) is displayed. Specifically, when the total accessory ratio is 25%, "2" is displayed in the third digit (ratio 10's place) and "5" in the fourth digit (ratio 1's place). Is displayed.

In the present embodiment, the configuration in which the main control circuit 90 directly includes the combination monitor 95 is described as an example, but the display content of the combination monitor 95 is controlled by the main control circuit 90. Further, it is sufficient if the display content can be recognized when necessary (for example, when the main control board case 55 is visually recognized), and a configuration that the main control circuit 90 does not directly provide can be adopted. For example, the combination monitor 95 may be connected to the game operation display board 81, and the main control circuit 90 may control the display contents via the game operation display board 81. Further, in this case, the combination ratio monitor 95 is also used as the information display 6, the LED 82, or the instruction monitor (instruction display), and one or more of them are used to display predetermined ratio information. You may do so.

Further, in the present embodiment, as the predetermined ratio information displayed on the role ratio monitor 95, the advantageous section ratio, the medium-time continuous combination ratio, the medium-time bonus ratio, the total continuous combination ratio, and the total bonus ratio are given as examples. However, ratio information other than these may be displayed. For example, the ratio of the number of game media paid out by operating the ART function to the number of game media paid out during the predetermined total number of games (175,000 times) (total advantageous section acquisition ratio). , The ratio of the number of game media paid out by operating the ART function to the number of game media paid out during a specific total number of games (6000 times) (medium time advantageous section acquisition ratio) , The ratio of the number of games in which the accessory continuous operation device is operated (medium-time continuous combination section ratio) to the specific total number of games (6000 times), the ratio of the specific total number of games (6000 times), The ratio of the number of games in which all the characters are activated (medium-time character section ratio), and the ratio of the number of games in which the continuous character operation device is operated (total continuous operation section) among the predetermined total number of games (175,000 times) The ratio), the ratio of the number of games in which all the bonuses are operated (total bonus section ratio), etc., among the predetermined total number of games (175,000 times) can also be displayed by performing a predetermined ratio calculation.

Further, in the present embodiment, as the parameter (denominator) of the predetermined ratio information displayed on the combination ratio monitor 95, the predetermined total number of games is set to "175,000 times" and the specific total number of games is set to "6000 times". As explained, the predetermined total number of games and the specific total number of games are not limited to this. For example, as the parameter (denominator) for calculating a part or all of the various ratios described above, the predetermined total number of games may be set to "17,500 times" and the specific total number of games may be set to "3000 times". .. However, various types of game machines are installed and operated in game stores, and the optimum number of games for ratio calculation may differ. Therefore, the number of games for calculating the above-mentioned various ratios is described above. It is not limited to the ones that have been made, but can be changed as appropriate. In this case, the number of games that can be the parameter (denominator) and the number of children (numerator) for calculating a part or all of the various ratios can be arbitrarily set on the game store side. Good.

Further, in the present embodiment, the operation of the ART function is not included in all the accessories targeted in the medium-time accessory ratio and the total accessory ratio, but the operation of the ART function is included in the accessory. It is also possible to calculate the ratio of the medium-time bonus and the total bonus ratio by regarding the operation of. In addition, it goes without saying that even if the information is other than the above, as long as it is useful information, the two values can be aggregated and the ratio calculation can be performed, and the result of the ratio calculation can be displayed as the ratio information. Absent.

<Microprocessor>
Next, the internal configuration of the microprocessor 91 will be described with reference to FIG. FIG. 9 is a block diagram showing an internal configuration of the microprocessor 91.

The microprocessor 91 includes a main CPU 101, a main ROM 102 (first storage means), a main RAM 103 (second storage means), an external bus interface 104, a clock circuit 105, a reset controller 106, an arithmetic circuit 107, and the like. It has a random number circuit 110, a parallel port 111, an interrupt controller 112, a timer circuit 113, a first serial communication circuit 114, and a second serial communication circuit 115. Each of these parts constituting the microprocessor 91 is connected to each other via a signal bus 116.

The main CPU 101 executes various control programs based on the clock pulse generated by the clock circuit 105 to perform control related to the overall game operation. Here, reel stop control will be described as an example of the control operation of the main CPU 101.

The main CPU 101 counts the number of times a pulse is output to the stepping motors of each reel 3L, 3C, 3L (main reel) after detecting the reel index. As a result, the main CPU 101 manages the rotation angle of each reel (mainly, how many symbols the reel has rotated). The reel index is information indicating that the reel has made one revolution. This reel index is, for example, an optical sensor having a light emitting portion and a light receiving portion, and a detection piece provided at a predetermined position on each reel and interposed between the light emitting portion and the light receiving portion due to rotation of each main reel. It is detected by the provided reel position detection unit (not shown).

Here, the management of the rotation angle of each reel 3L, 3C, 3L (main reel) will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 103. Then, each time the output of a predetermined number of pulses required for the rotation of one symbol is counted by the pulse counter, the symbol counter provided in the main RAM 103 is added one by one. The symbol counter is provided according to each reel. The value of the symbol counter is cleared when the reel index is detected by the reel position detection unit (not shown).

That is, in the present embodiment, by managing the symbol counter, it is possible to manage how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

The main ROM 102 stores various control programs executed by the main CPU 101, various data tables, data for transmitting various control commands (commands) to the sub control circuit 200, and the like. The main RAM 103 is provided with a storage area for storing various data such as internal winning combinations determined by executing the control program. The internal configuration (memory map) of the main ROM 102 and the main RAM 103 will be described in detail with reference to FIG. 12 described later.

The external bus interface 104 is for electrically connecting the microprocessor 91 to an external signal bus (not shown) to which various components (for example, reels and the like) provided outside the microprocessor 91 are connected. It is an interface circuit. The clock circuit 105 is configured to include, for example, a frequency divider (not shown), and a clock pulse signal for CPU operation input from the clock pulse generation circuit 92 is transmitted by another component (for example, a timer circuit 113). Convert to a clock pulse signal of the frequency used. The clock pulse signal generated by the clock circuit 105 is also output to the reset controller 106.

The reset controller 106 resets the IAT (Illegal Address Trap) and the WDT (watchdog timer) based on the reset signal input from the power supply management circuit 93. The arithmetic circuit 107 includes a multiplication circuit and a division circuit. For example, when the "MUL" instruction described later (see FIG. 94B described later) is executed on the source program, the arithmetic circuit 107 executes the multiplication process based on the "MUL" instruction.

The random number circuit 110 generates a random number in a predetermined range (for example, 0 to 65535 or 0 to 255). Although not shown, the random number circuit 110 has random number registers 0 for obtaining 2-byte hard-latch random numbers, random number registers 1 to 3 for obtaining 2-byte soft-latch random numbers, and 1-byte soft-latch random numbers. It is composed of random number registers 4 to 7 for obtaining. The main CPU 101 extracts one value from the random numbers in a predetermined range generated by the random number circuit 110, for example, as a random number value for internal lottery. The parallel port 111 is a signal port (memory map I / O) input / output between the microprocessor 91 and various circuits (for example, power management circuit 93, etc.) provided outside the microprocessor 91. .. The parallel port 111 is also connected to the random number circuit 110 and the interrupt controller 112. The start switch 79 is connected to any of the input ports of PI0 to PI4 of the parallel port 111, and when the start switch 79 is turned on (on-edge), a latch signal is sent from the parallel port 111 to the random number register 0 of the random number circuit 110. Is output. Then, in the random number circuit 110, the random number register 0 is latched by the input of the latch signal, and a 2-byte hard latch random number is acquired.

The interrupt controller 112 interrupts processing by the main CPU 101 based on a power failure detection signal input from the power management circuit 93 via the parallel port 111 or a timeout signal input from the timer circuit 113 at a cycle of 1.1172 ms. Controls the execution timing of. When a power failure detection signal is input from the power management circuit 93, or when a timeout signal is input from the timer circuit 113, the interrupt controller 112 sends an interrupt request signal indicating an interrupt processing start command to the main CPU 101. Output to. The main CPU 101 has an input port check process, a reel control process, a communication data transmission process, a 7-segment LED drive process, and a timer based on an interrupt request signal input from the interrupt controller 112 in response to a timeout signal from the timer circuit 113. Various interrupt processing such as update processing (see FIG. 167 described later) is performed.

The timer circuit 113 (PTC) operates with a clock pulse signal generated by the clock circuit 105 (a clock pulse signal having a frequency obtained by dividing the clock pulse signal for operating the main CPU by a divider (not shown)) ( Count the elapsed time). Then, the timer circuit 113 outputs a timeout signal (trigger signal) to the interrupt controller 112 at a cycle of 1.1172 msec.

The first serial communication circuit 114 is a circuit that controls a serial transmission operation when data (various control commands (commands)) are transmitted from the main control board 71 to the sub control board 72. The second serial communication circuit 115 is a circuit that controls the serial transmission operation when data is transmitted from the main control board 71 to the second interface board 302 for the testing machine.

<Secondary control circuit>
Next, the configuration of the sub-control circuit 200 (sub-control means) mounted on the sub-control board 72 will be described with reference to FIG. FIG. 10 is a block diagram showing a configuration example of the sub-control circuit 200 of the pachi-slot machine 1.

The sub-control circuit 200 is electrically connected to the main control circuit 90, and performs processing such as determination and execution of the effect content based on a command transmitted from the main control circuit 90. The sub-control circuit 200 basically includes a sub CPU 201, a sub RAM 202, a rendering processor 203, a drawing RAM 204, and a driver 205.

The sub CPU 201 is connected to the ROM cartridge board 86. The driver 205 is connected to the liquid crystal relay board 87. That is, the driver 205 is connected to the projector mechanism 211 and the sub display device 18 via the liquid crystal relay board 87.

The sub CPU 201 controls the output of video, sound, and light according to the control program stored in the ROM cartridge board 86 in response to the command transmitted from the main control circuit 90. The ROM cartridge board 86 is basically composed of a program storage area and a data storage area.

The control program executed by the sub CPU 201 is stored in the program storage area. For example, in the control program, the main board communication task for controlling the communication with the main control circuit 90 and the effect registration for extracting the random value for the effect and determining and registering the effect content (effect data). Contains various programs for executing tasks. Further, the control program includes a drawing control task that controls the display of an image by the display device 11 based on the determined effect content, a lamp control task that controls the output of light by a light source such as the LED group 85, and a sound by the speaker group 84. It also includes various programs for executing voice control tasks and the like that control the output of the LED.

The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to video creation. The data storage area also includes a storage area for storing sound data related to BGM and sound effects, a storage area for storing lamp data related to a pattern of turning on and off light, and the like.

The sub RAM 202 is provided with a storage area for registering the determined effect content and effect data, and a storage area for storing various data such as a sub flag (internal winning combination) transmitted from the main control circuit 90.

The sub CPU 201, the rendering processor 203, the drawing RAM (including the frame buffer) 204, and the driver 205 create an image according to the animation data specified by the effect content, and display the created image on the display device 11 (projector mechanism 211) and /. Alternatively, it is displayed on the sub display device 18. The display device 11 (projector mechanism 211) and the sub-display device 18 are individually controlled by the sub-control board 72.

Further, the sub CPU 201 causes the speaker group 84 to output a sound such as BGM according to the sound data specified by the effect content. Further, the sub CPU 201 controls the lighting and extinguishing of the LED group 85 according to the lamp data specified by the effect content.

<Various registers of the main CPU>
Next, various registers included in the main CPU 101 will be described with reference to FIG. Note that FIG. 11 is a schematic configuration diagram of various registers included in the main CPU 101.

As the main register, the main CPU 101 includes an accumulator A (hereinafter referred to as "A register"), a flag register F (flag register), a general-purpose register B (hereinafter referred to as "B register"), and a general-purpose register C (hereinafter referred to as "B register"). General-purpose register D (hereinafter referred to as "D register"), general-purpose register E (hereinafter referred to as "E register"), general-purpose register H (hereinafter referred to as "H register"), and general-purpose register L (hereinafter referred to as "H register"). , "L register"). Further, as sub-registers, the main CPU 101 includes an accumulator A', a flag register F', a general-purpose register B', a general-purpose register C', a general-purpose register D', a general-purpose register E', a general-purpose register H', and a general-purpose register L'. As a general-purpose register. Each register is composed of 1-byte (0 to 255) registers.

Further, in the present embodiment, the B register and the C register are used as a pair register (hereinafter, referred to as “BC register”), and the D register and the E register are used as a pair register (hereinafter, referred to as “DE register”). Further, in the present embodiment, the H register and the L register are used as a pair register (hereinafter, referred to as “HL register”). The pair register can be used as a 2-byte register (range of 0 to 65535).

As shown in FIG. 11, predetermined flag information indicating the result of arithmetic processing and the like is set in each bit of the flag registers F and F'. For example, bit 6 (D6) is set with data (zero flag) indicating whether or not the calculation result is "0" in the calculation result determination process. Specifically, when the calculation result is "0", the data "1" is set in the bit 6, and when the calculation result is not "0", the data "0" is set in the bit 6. Then, in the calculation result determination process, the main CPU 101 makes a determination (YES / NO) with reference to the bit 6 data “0” / “1”.

Further, the main CPU 101 has an expansion register Q (hereinafter, referred to as “Q register”). The Q register is composed of a 1-byte register. In this embodiment, as will be described in various processing flows described later, various main CPU 101 dedicated instruction codes for specifying an address using this Q register are provided on the source program, and this instruction code is provided. By using the above, processing efficiency is improved and the capacity of the main ROM 102 is reduced. In various main CPU 101 dedicated instruction codes that specify an address using the Q register, the address data (address value) on the upper side of the address is stored in the Q register. Immediately after the reset of the main CPU 101, "F0H" is set in the Q register as an initial value. Further, in the "LD Q, n (8-bit data)" instruction using the Q register, the value of the Q register is changed by setting arbitrary 1-byte data in "n" and executing the instruction. be able to.

Further, the main CPU 101 includes an interrupt page address register I and a memory refresh register R composed of 1-byte registers, and an index register IX and an index register IY composed of 2-byte registers. , The stack pointer SP and the program counter PC are provided as dedicated registers.

<Internal configuration of main ROM and main RAM (memory map)>
Next, the internal configurations (hereinafter referred to as “memory maps”) of the main ROM 102 and the main RAM 103 included in the main control circuit 90 (microprocessor 91) will be described with reference to FIGS. 12A to 12C. Note that FIG. 12A is a diagram showing a memory map of the entire memory, FIG. 12B is a diagram showing a memory map of the main ROM 102, and FIG. 12C is a diagram showing a memory map of the main RAM 103.

In the memory map of the entire memory included in the main control circuit 90 (microprocessor 91), as shown in FIG. 12A, from the head (0000H) side of the address, the memory area of the main ROM 102, the memory area of the main RAM 103, the built-in register area, and The XCS decoding areas are arranged at predetermined addresses in this order with an unused area in between.

In the memory map of the main ROM 102, as shown in FIG. 12B, the program area, the data area, the non-standard area, the trademark recording area, the program management area, and the security setting area are displayed from the head (0000H) side of the address of the main ROM 102. In order, they are arranged at predetermined addresses.

In the program area, control programs for various processes executed by the main CPU 101 in various control processes related to the playability of the game performed by the player are stored. In the data area, various data used by the main CPU 101 in various control processes related to the playability of the game performed by the player (for example, various data tables such as an internal lottery table, various types with respect to the sub control circuit 200). Data for transmitting control commands (commands), etc.) are stored. That is, the game ROM area (game storage area) composed of the program area and the data area is necessary for the control process (process related to the game property) related to the game playability of the game actually performed by the player at the game store. Various programs and various data are stored.

Further, in the non-standard area, control programs and data of various processes (processes that do not affect the playability) that are not directly related to the playability of the game performed by the player are stored. For example, the program and data used in the Pachislot 1 certification test (test firing test), the control program and data used in the checksum generation process when the power is cut off, the thumb check process when the power is restored, and the combination monitor display switching. Control programs and data used in processing, role ratio monitor aggregation processing, etc., as well as fraud countermeasure programs and data required for them are stored in the non-standard area.

In the memory map of the main RAM 103, as shown in FIG. 12C, the game RAM area (predetermined storage area, game temporary storage area) and the non-standard RAM area (non-standard temporary) from the head (F000H) side of the address of the main RAM 103. Storage areas) are arranged at predetermined addresses in this order.

The game RAM area is provided with a work area and a stack area for temporarily storing various data such as an internal winning combination determined by executing a control program related to the game playability performed by the player. .. Then, each of the various data is stored in the work area of a predetermined address in the game RAM area.

Further, the non-standard RAM area is provided with a non-standard work area that is a work area for various processes that are not directly related to the playability of the game performed by the player, and a non-standard stack. In the present embodiment, using this non-standard RAM area, various processes that are not directly related to the playability of the game performed by the player, such as a checksum process, are executed.

As described above, in the pachi-slot machine 1 of the present embodiment, various programs and various data (tables) used for various processes not directly related to the playability of the game performed by the player are used for the game in the main ROM 102. It is stored in a non-standard ROM area (non-standard storage area) located at an address different from the ROM area. In addition, various processes that are not directly related to the playability of the game performed by such a player are performed in the main RAM 103 using an out-of-specification RAM area arranged at an address different from the game RAM area. ..

In such a configuration of the main ROM 102, programs and data unnecessary for the game itself actually played by the player are arranged in the ROM area (non-standard ROM area) where the program or the like cannot be arranged according to the conventional rules. can do. Therefore, in the present embodiment, it is possible to avoid pressure on the capacity of the gaming ROM area.

<Transition flow of game state>
Next, various gaming states managed by the main control circuit 90 (main CPU 101) of the pachi-slot machine 1 of the present embodiment and their transition flows will be described with reference to FIGS. 13 and 14. Note that FIG. 13A is a transition flow diagram of the basic gaming state of the pachislot machine 1, and FIG. 13B is a table summarizing the transition conditions of the gaming state. Further, FIG. 14A is a transition flow diagram of a gaming state in consideration of whether or not the notification (ART) function is activated, and FIG. 14B is a table summarizing the transition conditions of the gaming state.

[Basic game state transition flow]
In the pachislot machine 1 of the present embodiment, a big bonus (hereinafter referred to as "BB") is provided as a type of bonus game. The BB is a continuous accessory actuating device for a regular bonus (hereinafter referred to as “RB”) called a first-class special accessory, and continuously operates the RB.

Therefore, in the present embodiment, the main control circuit 90 manages the gaming state based on the presence or absence of winning / operating (winning) of the bonus combination. Specifically, as shown in FIG. 13A, the main control circuit 90 is based on the presence or absence of a winning / operating (winning) of a bonus combination (internal winning combination of the names "F_BB1" and "F_BB2" described later). It manages three types of gaming states called "bonus non-winning state", "inter-flag state", and "bonus state".

The bonus non-winning state is a state in which the bonus is not winning and the bonus is not activated (winning), and the bonus state is a state in which the bonus is activated. Further, in the present embodiment, when the bonus combination is determined as the internal winning combination, the bonus combination is carried over as the internal winning combination over a plurality of games until the bonus is won. The inter-flag state is a state in which the bonus combination is carried over as an internal winning combination, that is, a state in which the bonus combination is won and the bonus is not activated.

Whether or not the bonus combination is won is determined by the data stored in the hit request flag storage area (see FIGS. 28 to 30 described later) and the carry-over combination storage area (see FIG. 31 described later) provided in the main RAM 103. It is managed based on. Further, whether or not the bonus is activated (winning) is managed based on the data stored in the game state flag storage area (see FIG. 32 described later) provided in the main RAM 103.

Further, in the present embodiment, as shown in FIG. 13A, in the gaming state in which the bonus is not activated (bonus non-winning state and inter-flag state), the types of internal winning combinations related to the replay and the winning probabilities thereof are different from each other. Six types of states from the RT0 gaming state to the RT5 gaming state (hereinafter, referred to as "RT0 state" to "RT5 state", respectively) are provided. The RT0 state, RT2 state, and RT5 state are gaming states in which the probability that the replay combination is determined as the internal winning combination is low, and the RT1 state has a medium probability that the replay combination is determined as the internal winning combination. It is a gaming state with a medium probability. Further, the RT3 state and the RT4 state are gaming states in which the probability that the replay combination is determined as the internal winning combination is high. In the present embodiment, the RT state in the bonus non-winning state is any of the RT0 state to the RT4 state, and the RT state in the inter-flag state is the RT5 state.

Therefore, in the present embodiment, the main control circuit 90 is based on the type of the internal winning combination related to the replay and the winning probability thereof in the gaming state in which the bonus is not activated (bonus non-winning state and inter-flag state). It also manages six types of states, RT1 state to RT5 state.

The RT0 state to the RT5 state are managed based on the data stored in the game state flag storage area (see FIG. 32 described later) provided in the main RAM 103. Specifically, in the pachi-slot machine 1 of the present embodiment, flags indicating five RT states of the RT1 state flag to the RT5 state flag are provided, and the RT state is managed by managing the on / off states of these flags by the main RAM 103. Is managed. Then, the main control circuit 90 specifies the RT state corresponding to the RT state flag that is in the ON state as the current RT state. When all the RT state flags are off, the main control circuit 90 identifies that the current RT state is the RT0 state.

As shown in FIGS. 13A and 13B, when the bonus combination (internal winning combination of the names "F_BB1" and "F_BB2" described later) is determined as the internal winning combination in the bonus non-winning state (when the transition condition (1) is satisfied). ), The main control circuit 90 shifts the gaming state from the bonus non-winning state to the inter-flag state. Further, when the bonus combination is won in the inter-flag state (when the transition condition (2) is satisfied), the main control circuit 90 shifts the gaming state from the inter-flag state to the bonus state.

Further, when the number of medals exceeding the specified number (216) is paid out in the bonus state and the bonus state ends (when the transition condition (3) is satisfied), the main control circuit 90 changes the gaming state from the bonus state to the RT1 state (RT1 state). Shift to the bonus non-winning state).

When 20 games have elapsed in the RT1 state (when the transition condition (4) is satisfied), the main control circuit 90 shifts the game state from the RT1 state to the RT0 state. Further, in the RT1 state, if the symbol combination related to the abbreviation "bell spilled eyes" (see FIG. 28 described later) is displayed on the valid line before 20 games have elapsed (when the transition condition (5) is satisfied). , The main control circuit 90 shifts the gaming state from the RT1 state to the RT2 state.

In the RT0 state, when the symbol combination related to the abbreviation "bell spilled eye" is displayed on the valid line (when the transition condition (5) is satisfied), the main control circuit 90 shifts the gaming state from the RT0 state to the RT2 state. Let me. In the RT2 state, when the symbol combination related to the abbreviation "RT3 transition lip" (see FIG. 28 described later) is displayed on the valid line (when the transition condition (6) is satisfied), the main control circuit 90 sets the gaming state. The RT2 state is changed to the RT3 state.

In the RT3 state, when the symbol combination related to the abbreviation "RT4 transition lip" (see FIG. 28 described later) is displayed on the valid line (when the transition condition (7) is satisfied), the main control circuit 90 sets the gaming state. The RT3 state is changed to the RT4 state. Further, in the RT3 state, when the symbol combination (see FIG. 28 described later) related to the abbreviation "bell spilled eye" or "RT2 transition lip" is displayed on the valid line (when the transition condition (8) is satisfied), the main The control circuit 90 shifts the gaming state from the RT3 state to the RT2 state. Further, in the RT4 state, when the symbol combination related to the abbreviation "bell spilled eye" or "RT2 transition lip" is displayed on the valid line (when the transition condition (8) is satisfied), the main control circuit 90 is in the gaming state. Shifts the gaming state from the RT4 state to the RT2 state.

As for the symbol combination related to the abbreviation "bell spilled eyes", the internal winning combination (small combination) related to the names "F_3 selection bell_1st", "F_3 selection bell_2nd" or "F_3 selection bell_3rd" described later is determined. Moreover, it is a combination of symbols displayed when the order of the stop operation is incorrect with respect to the push order determined for each type of the small winning combination (see FIG. 24 described later). As for the symbol combination related to the abbreviation "RT2 transition lip", the internal winning combination (replay combination) related to the names "F_maintenance lip_1st", "F_maintenance lip_2nd" or "F_maintenance lip_3rd" described later is determined, and This is a combination of symbols displayed when the order of stop operations is incorrect with respect to the push order determined for each type of replay combination.

As for the symbol combination related to the abbreviation "RT3 transition lip", the internal winning combination (replay combination) related to the names "F_RT3 lip_1st", "F_RT3 lip_213", "F_RT3 lip_231" or "F_RT3 lip_3rd" described later is determined. Moreover, it is a combination of symbols displayed when the order of the stop operation is the correct answer for the push order determined for each type of the replay combination. In addition, the symbol combination related to the abbreviation "RT4 transition lip" has an internal winning combination (replay role) related to the names "F_RT4 lip_123", "F_RT4 lip_132", "F_RT4 lip_2nd" or "F_RT4 lip_3rd" described later. It is a combination of symbols that are determined and displayed when the order of stop operations is correct for the push order determined for each type of replay combination.

[Transition flow of game state considering whether or not the notification (ART) function is activated]
In the present embodiment, the main control circuit 90 (main CPU 101) determines whether or not a function (ART function) for notifying a stop operation advantageous to the player is activated. Therefore, in the present embodiment, the activated / non-activated state of the ART function is also managed as the gaming state in the bonus non-operating state.

In the pachi-slot machine 1 of the present embodiment, as shown in FIG. 14A, the main control circuit 90 separates the "general game state" and the "ART game state" based on the presence or absence of notification (ART) in the non-bonus operating state. It is managed as the game state of. That is, in the management of the gaming state in consideration of the presence / absence of notification (ART), as shown in FIG. 14A, the main control circuit 90 is roughly classified into "bonus state", "general gaming state", and "ART gaming state". It manages three types of game states.

The general gaming state is basically a gaming state (non-ART) that does not notify information on a stop operation that is advantageous to the player, and is a gaming state that is disadvantageous to the player. Further, the general gaming state is any of the RT0 to RT4 states, and is an ART non-winning gaming state.

On the other hand, the ART gaming state is a gaming state that notifies information on a stop operation that is advantageous to the player, and is a gaming state that is advantageous to the player. Further, the ART gaming state is basically the RT4 state and the gaming state during the ART winning. In the present embodiment, when the RT state shifts to the RT4 state after winning the ART, the ART game is started.

Further, in the present embodiment, as shown in FIG. 14A, two types of states called "normal gaming state" and "CZ (chance zone)" are provided as general gaming states.

The normal game state is the most unfavorable game state for the player, but in the game in the normal game state, a lottery for transition to CZ is performed. Then, as shown in FIGS. 14A and 14B, in the game in the normal gaming state, when the transition lottery to the CZ is won (when the transition condition (A) is satisfied), the main control circuit 90 changes the gaming state to the normal gaming state. To CZ.

The CZ is a gaming state (chance zone) in which the expectation for the transition to the ART gaming state is high, and in the game during the CZ, a lottery for the transition to the ART is performed. Then, as shown in FIGS. 14A and 14B, in the game during CZ, when the lottery for transition to ART is not won (when the transition condition (B) is satisfied), the main control circuit 90 sets the game state. , CZ shifts to the normal gaming state. On the other hand, in the game during CZ, when the lottery for transition to ART is won (when the transition condition (C) is satisfied), the main control circuit 90 shifts the game state from CZ to the ART game state. At this time, although not shown in FIG. 14A, the main control circuit 90 shifts the gaming state from the CZ to the ART gaming state (normal ART or CT described later) via the ART preparation state described later.

As described above, the ART gaming state is started when the RT state shifts to the RT4 state after winning the ART. As shown in FIG. 13A, since the RT4 state shifts from the RT0 to RT2 states via the RT3 state, the ART gaming state is not started immediately even after winning the ART. Therefore, in the pachi-slot machine 1 of the present embodiment, the gaming state during the period from the winning of the ART to the transition from the RT state to the RT4 state is set as the ART preparation state. Then, in this game in the ART preparation state, information on the stop operation necessary for shifting the RT state to the RT4 state is notified.

Further, in the present embodiment, as shown in FIG. 14A, two types of ART gaming states, called "normal ART" and "CT (additional chance)", in which the playability is different from each other, are provided.

Normally, ART is a stop operation that is advantageous for the player for a predetermined number of games (for example, a stop operation for displaying a symbol combination with a large number of medals to be paid out, or a stop operation necessary for maintaining the RT4 state). Is the game state in which is notified. In addition, in a game during normal ART, a lottery for transition to CT is performed.

CT is a gaming state in which a player is notified of an advantageous stop operation and can add a normal ART duration for a specific period (a period of 8 games per set), and functions as an additional chance zone. It is a game state to play. Also, during CT, the game is usually played without digesting the duration of ART. The playability during CT will be described in detail later with reference to FIGS. 52A to 52C described later.

As shown in FIGS. 14A and 14B, in a game during normal ART, when the lottery for transition to CT is won (when the transition condition (D) is satisfied), the main control circuit 90 changes the game state from normal ART to CT. Shift the game state. Further, in the normal ART, when the duration of the normal ART ends (when the transition condition (E) is satisfied), the main control circuit 90 changes the gaming state from the normal ART to the general gaming state (normal gaming state or CZ). Migrate. In the present embodiment, the duration of normal ART is managed by the number of games, but the present invention is not limited to this, and the method of managing the duration of normal ART is arbitrary. For example, the duration of normal ART may be managed by the number of medals paid out during normal ART or the difference number, or by the number of notifications (number of navigations) that affect the payout of medals during normal ART. You may manage it.

As shown in FIGS. 14A and 14B, in the game during CT, when the duration of CT (8 games per set) ends (when the transition condition (F) is satisfied), the main control circuit 90 sets the game state to CT. To normal ART.

Further, as shown in FIG. 14A, when the bonus combination is won in the general gaming state (normal gaming state or CZ) or ART gaming state (normal ART or CT) (transition condition (2) described in FIGS. 13A and 13B). When is established), the main control circuit 90 shifts the gaming state from the general gaming state or the ART gaming state to the bonus state.

In the game in the bonus state, as described above, the lottery for transition to ART is performed, and in the game in the bonus state, if the lottery for transition to ART is non-winning (when the transition condition (G) is satisfied). , The main control circuit 90 shifts the gaming state from the bonus state to the general gaming state (normal gaming state or CZ). However, when the game has transitioned from the ART gaming state (normal ART or CT) to the bonus state, the main control circuit 90 sets the gaming state to the bonus state even if the game in the bonus state does not win the ART transition lottery. Shift from the bonus state to the ART gaming state (normal ART or CT). On the other hand, in the game in the bonus state, when the lottery for transition to ART is won (when the transition condition (H) is satisfied), the main control circuit 90 changes the gaming state from the bonus state to the ART gaming state (normal ART or CT). Migrate. As described above, at the end of the bonus state, the RT state shifts to the RT1 state. Therefore, when the gaming state shifts from the bonus state to the ART gaming state, the main control circuit 90 shifts the gaming state to the ART. It shifts to the ART game state via the preparation state.

<Structure of data table stored in main ROM>
Next, the configurations of various data tables stored in the main ROM 102 will be described with reference to FIGS. 15 to 27. The various data tables used in various lottery related to the game performance (CZ, normal ART, CT game performance) during the general game state and the ART game state will be described later together with the explanation of each game property. ..

[Design arrangement table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table is data that specifies the position of each symbol in each rotation direction of the left reel 3L, the middle reel 3C, and the right reel 3R, and the type of the symbol arranged at each position (hereinafter, symbol code (in FIG. 15). (Refer to the symbol code table of)) and stipulate the correspondence with.

In the symbol arrangement table, when the reel index is detected, the position of the symbol located in the middle region of each reel in the frame of the reel display window 4 is defined as "0". Then, in each reel, in the order of proceeding in the reel rotation direction (direction from the symbol position "19" in FIG. 15 toward the symbol position "0") with the symbol position "0" as a reference, " "0" to "19" are assigned to each symbol as the symbol position.

That is, by referring to the values of the symbol counters (“0” to “19”) and the symbol arrangement table, they are displayed in the upper region, the middle region, and the lower region of each reel in the frame of the reel display window 4. It is possible to specify the type of symbol. In this embodiment, as the symbols, "white 7", "blue 7", "chili top 1", "chili top 2", "chili bottom", "replay", "hat", "cactus 1", Ten kinds of symbols of "cactus 2" and "cactus 3" are used.

Further, in the present embodiment, as shown in the symbol code table, "00000001" is assigned as data to the symbol "white 7" (symbol code 1), and the symbol "blue 7" (symbol code 2) is assigned. "00000010" is assigned as the data. The symbol "Chile top 1" (symbol code 3) is assigned "000000111" as data, and the symbol "Chile top 2" (symbol code 4) is assigned "00000100" as data.

The symbol "Chile bottom" (symbol code 5) is assigned "000000101" as data, and the symbol "replay" (symbol code 6) is assigned "00000011" as data. The symbol "hat" (symbol code 7) is assigned "000000111" as data, and the symbol "cactus 1" (symbol code 8) is assigned "00001000" as data. Further, the symbol "cactus 2" (symbol code 9) is assigned "000001001" as data, and the symbol "cactus 3" (symbol code 10) is assigned "000001010" as data.

[Internal lottery table]
Next, the internal lottery table referred to when determining the internal winning combination will be described with reference to FIGS. 16 and 17. Note that FIG. 16 is an internal lottery table referred to in each of the RT0 state to the RT4 state. Further, FIG. 17A is an internal lottery table referred to in the RT5 state, and FIG. 17B is an internal lottery table referred to in the bonus state.

The internal lottery table is provided for each game state, and defines the correspondence between various internal winning combinations and the lottery value when each internal winning combination is determined. The lottery value is defined for each setting (settings 1 to 6) for adjusting the expected value of the internal winning such as a preset bonus combination or small combination. This setting is changed, for example, by using the reset switch 76 and the setting key type switch 54 (see FIG. 7).

In the internal lottery process of the present embodiment, first, the random number register 0 of the random number circuit 110 sets a random number value extracted from a predetermined numerical range (for example, 0 to 65535) corresponding to each internal winning combination. Add in sequence at the specified lottery value. Next, it is determined whether or not the lottery result (lottery value + random number value) exceeds 65535 (whether or not the lottery result overflows). Then, when the lottery result exceeds 65535 in the predetermined internal winning combination, it is determined that the internal winning combination has won. In the internal lottery process of the present embodiment, an example in which the lottery value is added to the extracted random number value to perform the lottery has been described, but the present invention is not limited to this, and the lottery value is subtracted from the random number value. It may be determined whether or not the subtraction result (lottery result) is less than "0" (whether or not the lottery result is underflowed), and the winning / non-winning of the internal lottery may be determined.

Therefore, in the internal lottery process of the present embodiment, the larger the numerical value defined as the lottery value, the higher the probability that the internal lottery combination will be determined. The winning probability of each internal winning combination can be expressed by "the lottery value specified in each winning number / the number of all random number values that may be extracted (random number denominator: 65536)".

In the internal lottery table referred to in each of the RT0 state to the RT4 state, as shown in FIG. 16, basically, the type and winning probability of the replay combination determined as the internal winning combination according to the type of the RT state. Changes. For example, the replay combination related to the names "F_chili lip (No. 25)" to "F_reach eye lip D (No. 31)" is not determined as an internal winning combination in the RT0 state to RT3 state, and is in the RT4 state. Only determined as an internal winning role. In the pachislot machine 1 of the present embodiment, the replay combination related to the names "F_chili lip (No. 25)" to "F_reach eye lip D (No. 31)" was determined as the internal winning combination during the RT4 state. In this case, specific control (flag conversion described later) is performed. This flag conversion will be described in detail later.

Further, as shown in FIG. 16, in the RT0 state to the RT3 state, the respective internal winning combinations of the names "F_reach eye lip A" to "F_reach eye lip D" are related to the names "F_BB1" or "F_BB2". Although it may be decided in duplicate with the bonus combination (see Nos. 3 to 6 and 15 to 18), each internal winning combination (replay) of the names "F_reach eye lip A" to "F_reach eye lip D" The role) is not determined as an internal winning role alone. Therefore, in the present embodiment, when the replay combination related to the names "F_reach eye lip A" to "F_reach eye lip D" is determined as the internal winning combination during the RT0 state to the RT3 state (name from the player's point of view). When the symbol combination corresponding to the replay combination related to "F_reach eye lip A" to "F_reach eye lip D" is displayed), the bonus combination (name "F_BB1" or "F_BB2") is determined as the internal winning combination at the same time. It will be done.

Further, the RT5 state, which is the inter-flag state, is a gaming state in which the bonus combination is carried over as the internal winning combination as described above. Therefore, as shown in FIG. 17A, in the internal lottery table referred to in the RT5 state, the carry-over bonus combination is always determined as the internal winning combination. Further, as shown in FIG. 17B, in the internal lottery table referred to in the bonus state, the internal winning combination according to any of the names "F_RB combination 1" to "F_RB combination 4" is always won ( "Out of place" won't win).

[Correspondence table between internal winning combination and symbol combination (winning combination) (symbol combination determination table)]
Next, with reference to FIGS. 18 to 23, a correspondence table (symbol combination determination table) between the internal winning combination and the symbol combination will be described. The symbol combination determination table defines the correspondence between various internal winning combinations and symbol combinations (combinations) that can be displayed on the effective line (center line) associated with each internal winning combination. That is, when the internal winning combination is determined, the type of symbol combination that can be displayed on the valid line (type of display combination that can win a prize) is uniquely determined.

The various data described in the symbol combination column in each symbol combination determination table is for identifying the symbol combination that is permitted to be displayed along the effective line set over the left reel 3L, the middle reel 3C, and the right reel 3R. It is data. The relationship between each name described in the symbol combination (display combination) column and the specific symbol combination is shown in the winning operation flag storage area of FIGS. 28 to 30 described later.

Further, the "○" mark described in the symbol combination determination table indicates a symbol combination (combination) that can be displayed on the effective line in the determined internal winning combination, that is, a display combination that can win a prize. For example, when the internal winning combination "F_chili lip" is determined, as shown in FIGS. 18 and 19, the combination names "C_maintenance lip A_01" to "C_maintenance lip G_01" and "C_chili lip A_01" to "C_chili lip" are determined. The symbol combination related to "D_01" can be stopped and displayed. It should be noted that the symbol combination determination table does not specify the case where the "internal winning combination" is "off", but this is all the symbols defined by the symbol combination tables shown in FIGS. 18 to 23. Indicates that the display of combinations is not allowed.

In the pachislot machine 1 of the present embodiment, the main control circuit 90 (main CPU 101) has different stop controls depending on the internal winning combination and the gaming state, and when a predetermined combination is determined as the internal winning combination, FIGS. The rotation stop control of the left reel 3L, the middle reel 3C, and the right reel 3R is performed so that the corresponding symbol combinations shown in FIG. 23 can be displayed. In the correspondence table shown in FIGS. 18 to 23, all the symbol combinations that can be displayed for the determined internal winning combination are listed by "○", but the symbols marked with "○" are listed. Even if it is a combination, it may not be displayed.

In the present embodiment, there is a function of making the stop control (for example, the symbol to be preferentially drawn in) different according to the combination of symbols that can be stopped and displayed and the current game state, and "○" is given because of the symbol to be preferentially drawn in. Even the marked combination of symbols may not be displayed. The correspondence between the types of internal winning combinations and the actually displayed symbol combinations will be described with reference to FIGS. 24 and 25 described later.

[Correspondence between the winning combination in the non-flag state and the symbol combination displayed as stopped]
Here, with reference to FIG. 24, the correspondence between the internal winning combination and the symbol combination displayed as stopped in the gaming state (non-flag state) excluding the flag state will be described. Note that FIG. 24 shows the correspondence between various internal winning combinations that can be determined in the non-flag state and a symbol combination (abbreviation) that is stopped and displayed when each internal winning combination is determined (some combinations are omitted). It is a figure. The name of the symbol combination described in FIG. 24 is the "abbreviation" described in the content column shown in the winning operation flag storage area of FIGS. 28 to 30 described later.

In the pachi-slot machine 1 of the present embodiment, a so-called “pushing order combination” is provided in which the symbol combinations displayed differ according to the order (pushing order) of the player's stop operations. The symbol combination associated with the "correct answer in push order" shown in FIG. 24 is a symbol combination that is advantageous for the player among the symbol combinations displayed according to the push order, and is referred to as "incorrect answer in push order". The associated symbol combination is a symbol combination that is disadvantageous to the player among the symbol combinations displayed according to the pressing order. When notifying a stop operation that is advantageous to the player, the correct push order is notified, and if the stop operation is performed according to the notification, the symbol combination associated with the "push order correct answer" is displayed. Further, even in the ART gaming state, an incorrect push order may be notified, but the details thereof will be described later.

In addition, in this embodiment, for a part of the push order combination, the push order that is the correct answer is shown at the end of the name. Specifically, the last "1st" in the name of the internal winning combination means that the correct push order is that the first stop operation (the first stop operation performed) is for the left reel 3L. The end "2nd" of the name of the internal winning combination means that the push order that is the correct answer is that the first stop operation is for the middle reel 3C, and the end "3rd" of the name of the internal winning combination is the correct answer. The push order means that the first stop operation is for the right reel 3R. In addition, the end "123" of the name of the internal winning combination means that the correct push order is "left, middle, right", and the end "132" of the name of the internal winning combination is the correct answer. Means that the push order is "left, right, middle", and the last "213" in the name of the internal winning combination means that the correct push order is "middle, left, right". The ending "231" of the name of the internal winning combination means that the correct push order is "left, right, middle".

Further, in the following, the stop operation order when the first stop operation is performed on the left reel 3L, specifically, the push order of "left, middle, right" and "left, right, middle" is changed to ". Also called "forward push". Further, in the following, the stop operation order when the first stop operation is performed on the middle reel 3C or the right reel 3R, specifically, "middle, left, right", "middle, right, left", The pressing order of "right, middle, left" and "right, left, middle" is also referred to as "irregular pressing".

In the present embodiment, as shown in FIG. 24, the internal winning combination “F_Chillilip” is a pressing order combination in which the symbol combinations displayed according to the pressing order are different, and when the pressing order is the correct answer, the abbreviation “F_Chillilip” is used. Any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to "Chillilip" (see FIG. 28 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed. When the internal winning combination "F_chililip" is determined, as shown in FIGS. 18 to 23, the combination names "C_chililip A_01", "C_chililip B_01" or "C_chililip C_01" (abbreviation "single chili lip") Alternatively, "double chili lip": corresponding to the abbreviation "chili lip (no triple)" in FIG. 28 described later) can be displayed, but the combination names "C_chili lip D_01" to "C_1 certain chili lip D_01" (abbreviation). "Triple chili lip": Corresponding to the abbreviation "chili lip (triple)" in FIG. 28, which will be described later), the symbol combination cannot be displayed. That is, the internal winning combination "F_chili lip" is a combination in which the symbol combination related to the abbreviation "triple chili lip" cannot be displayed.

In addition, both the internal winning combinations "F_certain chili lip" and "F_1 certain chili lip" are push order combinations with different symbol combinations displayed according to the push order, and if the push order is correct, the abbreviation "chili lip" is used. Any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the above (see FIG. 28 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed. When the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, the symbol combination related to the abbreviation "triple chili lip" can be displayed as shown in FIGS. 18 to 23. That is, the internal winning combinations "F_certain chili lip" and "F_1 certain chili lip" are roles that can display the symbol combination related to the abbreviation "triple chili lip".

In addition, the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" are push order combinations with different symbol combinations displayed according to the push order, and are abbreviated when the push order is correct. One of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations (see FIGS. 28 and 29 described later) related to the “reach eye lip” is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed.

In the present embodiment, the order of pressing the correct answers at the time of winning the internal winning roles "F_chili lip", "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_reach eye lip D" Is to perform the first stop operation on the left reel 3L. Therefore, for example, in a game in which the internal winning combination "F_reach eye lip A" is determined, when the player performs the first stop operation on the left reel 3L, the abbreviation is changed to "reach eye lip". The symbol combination is stopped and displayed. The present invention is not limited to this, and the internal winning combinations "F_chili lip", "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_reach eye lip D" are used at the time of winning. The order of pressing the correct answers can be set arbitrarily.

In addition, both the internal winning combinations "F_maintenance lip A" and "F_maintenance lip B" are not push order combinations, and are shown in the symbol combinations related to the abbreviation "replay" regardless of the push order (see FIG. 28 described later). Any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line.

In addition, the internal winning combinations "F_maintenance lip_1st" to "F_maintenance lip_3rd" are all push order combinations in which the symbol combinations displayed according to the push order are different, and if the push order is correct, they are abbreviated. Among the symbol combinations related to "replay" (see FIG. 28 described later), any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations (see FIG. 28 described later) related to the abbreviation "RT2 transition lip" is an effective line. It is displayed along with.

In addition, the internal winning combinations "F_RT3 rip_1st" to "F_RT3 rip_3rd" are all push order combinations in which the symbol combinations displayed according to the push order are different, and when the push order is correct, the abbreviation "RT3" is used. The symbol combination related to "Transition Lip" (see FIG. 28 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed.

In addition, the internal winning combinations "F_RT4 rip_123" to "F_RT4 rip_3rd" are all push order combinations in which the symbol combinations displayed according to the push order are different, and when the push order is correct, the abbreviation "RT4" is used. The symbol combination related to "Transition Lip" (see FIG. 28 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed.

In addition, the internal winning combinations "F_3 choice bell_1st" to "F_3 choice bell_3rd" are all push order combinations in which the symbol combinations displayed according to the push order are different, and if the push order is correct, they are abbreviated. The symbol combination related to the "bell" (see FIG. 19 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, the symbol combination related to the abbreviation "bell spilled eyes" (see FIG. 28 described later) or the symbol combination related to the abbreviation "first piece" (see FIG. 30 described later) is used. Is displayed.

Further, the internal winning combination "F_common bell" is not a pressing order combination, and can be displayed as shown in FIGS. 18 to 23 of the symbol combinations (see FIG. 29 described later) related to the abbreviation "bell" regardless of the pressing order. Any of the various symbol combinations is displayed along the effective line. Further, neither of the internal winning combinations "F_sabo 1" and "F_sabo 2" is a pushing order, and FIG. 18 of the symbol combination (see FIG. 30 described later) relating to the abbreviation "cactus" regardless of the pushing order. ~ Any of the displayable symbol combinations shown in FIG. 23 is displayed along the effective line.

Further, the internal winning combination "weak cherry" is not a pressing order, and can be displayed as shown in FIGS. 18 to 23 of the symbol combinations (see FIG. 30 described later) related to the abbreviation "weak cherry" regardless of the pressing order. Any of the various symbol combinations is displayed along the effective line. In addition, the internal winning combinations "F_strong chili 1" and "F_strong chili 2" are not push order combinations, and are among the symbol combinations related to the abbreviation "strong cherry" regardless of the push order (see FIG. 30 described later). Any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line.

[Correspondence between the winning combination in the state between flags and the symbol combination displayed as stopped]
Next, with reference to FIG. 25, the correspondence between the internal winning combination and the symbol combination displayed as stopped in the inter-flag state will be described. Note that FIG. 25 is a diagram showing the correspondence between the internal winning combination and the symbol combination displayed as stopped in the inter-flag state (some combinations are omitted), and in particular, the bonus combination (some combinations are omitted) during the inter-flag state. It is a figure which shows whether or not it is possible to display the symbol combination (combination name "C_BB1" or "C_BB2") which concerns on BB combination).

In the correspondence table of FIG. 25, the "○" mark described in the "whether or not BB is established" column indicates that the symbol combination related to the BB combination can be displayed, and the "x" mark indicates the symbol combination related to the BB combination. Indicates that is not displayable. If the symbol combination related to the BB combination cannot be displayed, the symbol combination related to the combination determined to overlap with the bonus combination as the internal winning combination is displayed. For example, when the internal winning combination "F_BB1 + F_Chillilip" is won (when the internal winning combination "F_BB1" and the internal winning combination "F_Chillilip" are duplicated), as shown in FIG. 25, the internal winning combination "F_BB1" It is possible to stop and display the symbol combination related to, and the symbol combination related to the internal winning combination "F_Chillilip" is stopped and displayed.

Further, in the inter-flag state, when the symbol combination related to the BB combination cannot be displayed and the symbol combination related to the combination determined to overlap with the bonus combination is displayed, the push described with reference to FIG. 24 Only the symbol combination at the time of correct answer may be displayed, or only the symbol combination at the time of incorrect answer may be displayed.

For example, when the internal winning combination "F_BB1 + F_3 selection bell_1st" is won, as shown in FIG. 25, the symbol combination related to the internal winning combination "F_BB1" cannot be stopped and displayed, so that the internal winning combination "F_3 selection bell_1st" cannot be stopped and displayed. The symbol combination related to "" is stopped and displayed, but at this time, only the symbol combination related to the abbreviation "bell" displayed when the push order is correct is displayed, and the abbreviation "bell spilled eye" displayed when the push order is incorrect is displayed. Alternatively, the symbol combination related to the "first piece" may not be displayed (see FIG. 24). Further, for example, when the internal winning combination "F_BB1 + F_RT3 rip_1st" is won, only the symbol combination related to the abbreviation "replay" displayed when the push order is incorrect can be displayed, and the abbreviation "RT3" displayed when the push order is correct is displayed. The symbol combination related to the "transition lip" may be made invisible (see FIG. 24).

In the inter-flag state, as shown in FIG. 25, one of the bonus combination (BB combination) and the internal winning combination "off", "F_special 1", "F_special 2" and "F_special 3" If the determinations are duplicated, the symbol combination related to the BB combination can be stopped and displayed.

[Reel stop initialization table]
Next, the reel stop initial setting table will be described with reference to FIG. The reel stop initial setting table defines the correspondence between the internal winning combination and various data used in the reel stop control process described later.

The reel stop initial setting table shown in FIG. 26 defines the correspondence between the internal winning combination (small winning combination winning number) and the attraction priority table selection table number, attraction priority table number, and stop table number. In addition, in FIG. 26, the reference game state and the name of the internal winning combination are also shown.

The pull-in priority table selection table number and the pull-in priority table number are data used in the selection process of the pull-in priority table. For example, if the pull-in priority table number corresponding to the stop table number is specified in the reel stop initial setting table, it corresponds to the pull-in priority table number specified in the pull-in priority table (see FIG. 27 described later). Data related to the priority of the display combination can be acquired. On the other hand, if the attraction priority table number corresponding to the stop table number is not specified in the reel stop initialization table, the attraction priority table selection table (not shown) is referred to and the attraction priority table selection table number is set. The corresponding pull-in priority table number is determined.

Here, the reel stop control (method for determining the stop symbol position) in the pachi-slot machine 1 of the present embodiment will be briefly described. In the present embodiment, after the stop operation is detected by the stop switch, the reel stop control is performed so that the rotation of the corresponding reel stops within 190 msec. Specifically, any one of the number of sliding pieces "0" to "4" is added to the value of the symbol counter corresponding to the corresponding reel when the stop operation is detected, and the value corresponds to the obtained value. The symbol position is determined as the symbol position at which the rotation of the reel stops (hereinafter, referred to as "scheduled stop position"). The symbol position corresponding to the value of the symbol counter corresponding to the corresponding reel when the stop operation is detected is the symbol position where the rotation of the reel is started (hereinafter, referred to as "stop start position").

That is, the number of sliding pieces is the amount of rotation of the reel from the time when the stop operation is detected by the stop switch until the rotation of the corresponding reel is stopped. In other words, it is the number of symbols that pass through the middle region of the corresponding reel of the reel display window 4 in the period from the detection of the stop operation by the stop switch to the stop of the rotation of the corresponding reel. This is grasped by the value of the symbol counter updated after the stop operation is detected by the stop switch.

With reference to a stop table (not shown), the number of sliding pieces is acquired according to the stop start position of each reel. In the present embodiment, the number of sliding pieces is acquired based on the stop table, but this is tentative, and the acquired number of sliding pieces does not immediately determine the scheduled stop position of the reel. In the present embodiment, if there is a more appropriate number of sliding pieces than the number of sliding pieces acquired based on the stop table (hereinafter referred to as “sliding piece number determination data”), the pull-in priority table (described later) will be described later. Refer to FIG. 27) to change the number of sliding pieces. Then, the sliding piece number determination data is referred to for determining the search order when comparing the priorities of each symbol from the stop start position to the symbol position four ahead, which is the maximum number of sliding pieces.

[Pull-in priority table]
Next, the pull-in priority table will be described with reference to FIG. 27. The attraction priority table is the attraction data (winning operation flag data) for each type of the winning operation flag storage area (see FIGS. 28 to 30 described later) in each of the drawing priority table numbers “00” to “05”. ) And its predetermined priority.

The pull-in priority table is used to search whether or not a more appropriate number of sliding pieces exists in addition to the number of sliding pieces obtained based on the stop table (not shown). The priority order is data that defines the order in which the symbols are preferentially stopped and displayed (pulled in) among the types of symbol combinations (winning operation flags) related to winning. Further, in FIG. 27, for convenience of explanation, the combination name of the winning operation flag is described in the column of the drawing data (winning operation flag data), but in the actual drawing priority table, each drawing data is the winning prize described later. As shown in the operation flag storage area (see FIGS. 28 to 30 described later), it is represented by 1-byte data, and a unique symbol combination (winning operation flag) is assigned to each bit in the 1-byte data. ..

In the reel stop control of the present embodiment, first, the number of sliding pieces is acquired based on the stop table (not shown). However, if there is a more appropriate number of sliding pieces in addition to the number of sliding pieces based on the priority, the number is changed to the appropriate number of sliding pieces. That is, in the present embodiment, the more appropriate number of sliding pieces is determined based on the priority of the symbol combination that allows the stop display by the internal winning combination, regardless of the number of sliding pieces acquired by the stop table.

In the present embodiment, the stop display (pull-in) of the symbol combination having the higher priority is performed with priority over the stop display of the symbol combination having the lower priority.

Further, in the present embodiment, as shown in FIG. 27, not only the priority of the symbol combination (winning operation flag) is different according to the attraction priority table number, but also the number of priority divisions is different. Specifically, when the attraction priority table number is "00", the number of priority divisions is 5, and when the attraction priority table number is "01" or "04", the priority order is set. Let the number of divisions be 4. If the pull-in priority table number is "02" or "03", the number of priority divisions is 2, and if the pull-in priority table number is "05", the number of priority divisions is set. Let be 3.

Here, the priority when the pull-in priority table number is "00" will be described, and the description of the priority in the other pull-in priority table numbers will be omitted. When the pull-in priority table number is "00", the priority "1" (highest priority) includes the combination names "C_9 sheets A_01", "C_1 certain chili lip C_01", "C_1 certain chili lip D_01" and The pull-in data corresponding to "C_RT3 lip_01" is specified.

When the pull-in priority table number is "00", the priority "2" includes the combination names "C_strong 2 sheets C_01" to "C_strong 2 sheets C_09", "C_weak 2 sheets B_01" to "C_weak". Corresponds to "2 sheets B_03", "C_3 sheets E_01", "C_3 sheets E_02", "C_9 sheets F_01" to "C_9 sheets F_03", "C_1 certain chili lip B_01", "C_chili lip D_01" and "C_chili lip C_01". The pull-in data is specified.

When the pull-in priority table number is "00", the priority "3" includes the combination names "C_1 sure chili lip A_01", "C_chili lip A_01", "C_chili lip B_01" and "C_maintenance lip E_01" to "C_maintenance lip E_01". The pull-in data corresponding to "C_maintenance lip E_04" is specified.

When the pull-in priority table number is "00", the priority "4" includes the combination names "C_SP1_01", "C_SP2_01", "C_reach eye lip P_01", "C_reach eye lip P_02", and "C_reach". Eye Lip O_01 "," C_Reach Eye Lip O_02 "," C_Reach Eye Lip N_01 "," C_Reach Eye Lip N_02 "," C_Reach Eye Lip M_01 "," C_Reach Eye Lip M_02 "," C_Reach Eye Lip N_02 " L_01 "to" C_reach eye lip L_03 "," C_reach eye lip K_01 "to" C_reach eye lip K_03 "," C_reach eye lip J_01 "," C_reach eye lip I_01 "to" C_reach eye lip I_09 " , "C_reach eye lip H_01" to "C_reach eye lip H_03", "C_reach eye lip G_01", "C_reach eye lip F_01", "C_reach eye lip F_02", "C_reach eye lip E_01", " C_reach eye lip D_01 "," C_reach eye lip D_02 "," C_reach eye lip C_01 "to" C_reach eye lip C_03 "," C_reach eye lip B_01 "," C_reach eye lip B_02 "," C_reach Eye Lip A_01 "," C_Maintenance Lip F_01 "," C_Maintenance Lip F_02 "," C_Maintenance Lip D_01 "to" C_Maintenance Lip D_04 "," C_Maintenance Lip C_01 "to" C_Maintenance Lip C_03 "," C_Maintenance Lip C_03 " The pull-in data corresponding to "Rip B_01", "C_Maintenance Lip B_02" and "C_Maintenance Lip A_01" is specified.

Further, the attraction data corresponding to the combination names "C_BB1" and "C_BB2" is defined in the priority "5" (lowest priority) when the attraction priority table number is "00".

<Structure of storage area provided in main RAM>
Next, the configurations of various storage areas provided in the main RAM 103 will be described with reference to FIGS. 28 to 35.

[Hit request flag storage area and winning operation flag storage area]
First, the configuration of the winning request flag storage area (internal winning combination storage area) and the winning operation flag storage area (display combination storage area) will be described with reference to FIGS. 28 to 30. In the present embodiment, the hit request flag storage area (flag data storage area, winning flag data storage area) and the winning operation flag storage area (winning flag data storage area) have the same configuration.

In the present embodiment, the hit request flag storage area is composed of the hit request storage areas 0 to 11 each represented by 1 byte of data, and the winning operation flag storage area is each represented by 1 byte of data. It is composed of storage areas 0 to 11. The data stored in each storage area of the hit request flag storage area and the winning operation flag storage area is only the 1-byte data in the "data" column in FIGS. 28 to 30, but in FIGS. 28 to 30, , For convenience of explanation, the symbol combination of each reel associated with the bit of each storage area (in the figure, the symbol of the left reel 3L, the symbol of the middle reel 3C, and the symbol of the right reel 3R are described in this order). The name (combination name) and abbreviation, as well as the number of medals to be paid out are also described.

When "1" is stored in a predetermined bit in each of the hit request flag storage areas 0 to 11, it indicates that the internal winning combination corresponding to the predetermined bit has won the internal winning. Further, when "1" is stored in a predetermined bit in each of the winning operation storage areas 0 to 11, it indicates that the display combination (winning operation flag) corresponding to the predetermined bit has won a prize. That is, when "1" is stored in the predetermined bit, it indicates that various symbol combinations of the internal winning combinations corresponding to the predetermined bit are displayed on the effective line.

Further, in the hit request flag storage area and the winning operation flag storage area, as shown in FIGS. 28 to 30, a plurality of symbol combinations (combinations) are assigned to one bit (flag) in each storage area. Some are. That is, for such a flag, it means that there are a plurality of symbol combinations (combinations that can win a prize) that can be stopped and displayed.

For example, the winning request storage area 5 and the winning operation storage area 5 have a symbol combination "cactus 2"-"white 7"-"hat" (combination name "C_maintenance lip C_01") and a symbol combination "cactus 2". -"Chile Top 1"-"Hat" (combination name "C_maintenance lip C_02") and symbol combination "cactus 2-"-"cactus 2-"-"hat" (combination name "C_maintenance lip C_03") Three symbol combinations are assigned. Therefore, when "1" is stored in bit 5 of the hit request storage area 5, it indicates that the combination of these three symbols can be stopped and displayed on the effective line. Further, when "1" is stored in bit 5 of the winning operation storage area 5, it indicates that any one of these three symbol combinations is displayed on the valid line.

[Carryover storage area]
Next, the configuration of the carry-over combination storage area will be described with reference to FIG. 31. In the present embodiment, the carry-over combination storage area is composed of a 1-byte data storage area.

When the internal winning combination "F_BB1" or "F_BB2" is determined as a result of the internal lottery, the internal winning combination (BB combination) is stored in the carry-over combination storage area as a carry-over combination. The carry-over combination stored in the carry-over combination storage area is retained without being cleared until the corresponding symbol combination is displayed on the valid line. Further, while the carry-over combination is stored in the carry-over combination storage area, the carry-over combination is stored in the winning request storage area in addition to the internal winning combination determined by the internal lottery.

[Game status flag storage area]
Next, the configuration of the game state flag storage area will be described with reference to FIG. 32. The game state flag storage area is composed of a 1-byte data storage area. In the present embodiment, as shown in FIG. 32, a unique bonus type or RT type is assigned to each bit in the game state flag storage area.

When "1" is stored in a predetermined bit in the game state flag storage area, it indicates that the bonus game or RT corresponding to the predetermined bit is being operated. For example, when "1" is stored in bit 0 of the game state flag storage area, the big bonus "BB" is being operated, indicating that the game state is the BB game state. Further, for example, when "1" is stored in bit 3 of the game state flag storage area, it indicates that the game state is the RT3 state.

[Operation stop button storage area]
Next, the configuration of the operation stop button storage area will be described with reference to FIG. 33. The operation stop button storage area is composed of a 1-byte data storage area, and stores an operation stop button flag consisting of 1 byte. In the operation stop button flag, the operation state of the stop button is assigned to each bit.

For example, when the left stop button 17L is the stop button pressed this time, that is, the operation stop button, "1" is stored in bit 0 of the operation stop button storage area. Further, for example, when the left stop button 17L is a stop button that has not yet been pressed, that is, an effective stop button, "1" is stored in bit 4. The main CPU 101 distinguishes between the stop button pressed this time and the stop button that has not yet been pressed, based on the data stored in the operation stop button storage area.

[Press order storage area]
Next, the configuration of the pressing order storage area will be described with reference to FIG. 34. The press order storage area is composed of a 1-byte data storage area, and stores a press order flag consisting of 1 byte.

In the pressing order flag, each bit is assigned the type of pressing order of the stop button. For example, when the pressing order of the stop buttons is "left, middle, right", "1" is stored in bit 0 of the pressing order storage area.

[Design code storage area]
Next, the configuration of the symbol code storage area will be described with reference to FIG. 35. In the present embodiment, each of the symbol code storage areas is composed of symbol code storage areas 0 to 11 represented by 1 byte of data. The symbol code storage area has the same configuration as the hit request flag storage area and the winning operation flag storage area (see FIGS. 28 to 30).

In the symbol code storage area, "1" is stored in the bit corresponding to the symbol combination that can be stopped on the effective line. After all the reels are stopped, the symbol code corresponding to the display combination (winning operation flag) is stored in the symbol code storage areas 0 to 11.

[Relationship between internal winning combination and various sub-flags]
In the general game state and the ART game state, various data tables are referred to in various lottery by the main control circuit 90, but as a parameter used at this time, in this embodiment, not only the internal winning combination but also the internal winning combination is supported. Various parameters having different names (hereinafter, referred to as "sub-flag (first sub-flag)", "sub-flag EX (second sub-flag)", and "sub-flag D") are also used. Therefore, in the present embodiment, the main control circuit 90 performs a process of converting the internal winning combination into various sub-flags (see the sub-flag conversion process, the flag conversion process, and the sub-flag compression process in FIG. 104, which will be described later). In the present embodiment, a sub flag is set in the start command as information (communication parameter) regarding the internal winning combination, and is transmitted from the main control circuit 90 to the sub control circuit 200.

Here, with reference to FIGS. 36 and 37, the correspondence between the internal winning combination and various sub-flags will be described. FIG. 36 is a diagram showing the correspondence relationship between the internal winning combination (small winning combination winning number) and various sub-flags, and FIG. 37 is a diagram showing the correspondence relationship between the internal winning combination (special prize winning number) and the sub-flags.

In the flag conversion process of the present embodiment, first, a plurality of internal winning combinations belonging to the same type are combined into one sub-flag. In the present embodiment, as shown in FIG. 36, by this flag conversion process, 32 types of internal winning combinations (small winning combination winning numbers) related to the small winning combination and the replay winning combination are converted into 18 types of sub-flags (“01” to “18”. : Flag data) is converted. For example, the internal winning combination "F_maintenance rip_1st (10: small winning combination number)" to "F_maintenance rip_3rd (12)" are grouped into the sub-flag "pushing order rip 1 (09: flag data)". The sub-flag "Loss (00)" is assigned to the internal winning combination "Loss".

Further, in the flag conversion process of the present embodiment, as shown in FIG. 36, 19 types of sub-flags ("00" to "18") including the sub-flag "loss (00)" are replaced with 9 types of sub-flag EX ("00"). "-" 08 ": flag data). Therefore, in this conversion process, the sub-flag data can be further compressed. At this time, in the present embodiment, the sub flag is converted into the sub flag EX by lottery (flag conversion lottery). Specifically, it is converted as follows.

The sub-flag "Loss (00)" is converted to the sub-flag EX "Loss (00)" regardless of the result of the flag conversion lottery, and the sub-flag "Double chili lip (01)" is converted to the sub-flag "Double chili lip (01)" regardless of the result of the flag conversion lottery. It is converted to the sub flag EX "replay (01)".

When the sub-flag "triple chili lip A (02)" and the sub-flag "triple chili lip B (03)" are won in the flag conversion lottery (in the case of "with conversion" described later), the sub-flag EX "fixed combination (06)" Alternatively, it is converted to "triple chili lip (07)", and if the flag conversion lottery is not won (in the case of "no conversion" described later), it is converted to the sub-flag EX "replay (01)".

The sub-flags "reach-eye lip 1 (04)" to "reach-eye lip 4 (07)" are converted to the sub-flag EX "fixed combination (06)" or "reach-eye lip (08)" when the flag conversion lottery is won. If the flag conversion lottery is not won, it is converted to the sub-flag EX "replay (01)".

The sub-flags "replay (08)" and "push order rip 1 (09)" to "push order rip 3 (11)" are converted to the sub-flag EX "replay (01)" regardless of the result of the flag conversion lottery. The sub-flags "push order bell (12)" and "common bell (13)" are converted to the sub-flag EX "bell (02)" regardless of the result of the flag conversion lottery.

The sub-flags "cactus (14)", "weak cherry (15)" and "strong cherry (16)" are the sub-flags EX "cactus (03)" and "weak cherry (04)" regardless of the result of the flag conversion lottery, respectively. "And" strong cherry (05) ". Further, the sub-flags "reach eye 1 (17)" and "reach eye 2 (18)" are converted into the sub-flag EX "miss (00)" regardless of the result of the flag conversion lottery.

As described above, in the present embodiment, the sub-flags "triple chili lip A (02)", "triple chili lip B (03)" and "reach eye lip 1 (04)" to "reach eye lip 4 (07)" are substantially used. ) ”Is the target of the flag conversion lottery. The lottery table used for the above-mentioned flag conversion lottery will be described in detail later.

Further, in the flag conversion process of the present embodiment, as shown in FIG. 36, nine types of sub-flags EX (“00” to “08”) are converted into seven types of sub-flags D (“00” to “06”). The flag. Therefore, in this conversion process, the sub-flag data can be further compressed. In this conversion process, lottery is not performed, and the sub-flag EX and the sub-flag D are associated with each other for conversion as follows.

The sub-flag EX "loss (00)", "replay (01)" and "bell (02)" are converted into the sub-flag D "loss (00)". The sub-flag EX "cactus (03)" is converted to the sub-flag D "cactus (01)", the sub-flag EX "weak cherry (04)" is converted to the sub-flag D "weak cherry (02)", and the sub-flag EX "strong". "Cherry (05)" is converted to subflag D "strong cherry (03)".

Further, the sub flag EX "fixed combination (06)" is converted to the sub flag D "fixed combination (04)", and the sub flag EX "triple chili lip (07)" is converted to the sub flag D "triple chili lip (05)". Then, the sub flag EX "reach eye lip (08)" is converted into the sub flag D "reach eye lip (06)".

Further, in the flag conversion process of the present embodiment, as shown in FIG. 37, both the internal winning combination "F_BB1 (01: special prize winning number)" and "F_BB2 (02)" are converted into the sub-flag "BB". ..

[Gameability at the time of sub-flag EX conversion]
Here, an example of the process of converting the above-mentioned internal winning combination into the sub-flag and the sub-flag EX and the playability at the time of sub-flag EX conversion will be described with reference to FIGS. 38A and 38B. FIG. 38A is a diagram showing a flag conversion process when the internal winning combination “F_certain chili lip” or “F_1 certain chili lip” is determined, and FIG. 38B is a diagram showing the internal winning combination “F_reach eye lip A” to “F_”. It is a figure which shows the flag conversion process when any of "reach eyes lip D" is determined.

In the pachislot machine 1 of the present embodiment, any one of the internal winning combinations "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_reach eye lip D" is independent during the RT4 game state. If it is determined as an internal winning combination, a flag conversion lottery will be performed. Then, in the present embodiment, when the flag conversion lottery is won, a special privilege (for example, addition of the number of ART games or CT winning) is given.

For example, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, as shown in FIG. 38A, the internal winning combination "F_certain chili lip" and "F_1 certain chili lip" are each sub-flag "3 consecutive". It is converted into "chili lip A (02)" and "triple chili lip B (03)".

Next, the sub-flags "triple chili lip A (02)" and "triple chili lip B (03)" become the sub-flag EX "triple chili lip (07)" or "fixed combination (06)" when the flag conversion lottery is won. Will be converted. On the other hand, if the flag conversion lottery is not won, both the sub-flags "triple chili lip A (02)" and "triple chili lip B (03)" are converted to the sub-flag EX "replay (01)". ..

As described in FIG. 24, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won, the symbol combination related to the abbreviation "triple chili lip" is displayed when the push order is correct, and the push order is irregular. When the answer is correct, the symbol combination related to the abbreviation "Replay" is displayed. Therefore, in the present embodiment, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined and the flag conversion lottery is won, the internal winning combination "F_certain chili lip" and "F_1 certain chili lip" Are all treated as the combination of the sub-flag EX "triple chili lip (07)" or "fixed combination (06)".

Then, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is converted into the sub-flag EX "triple chili lip (07)" or "fixed combination (06)" by this flag conversion process, the abbreviation "triple chili lip" is abbreviated. Information for displaying the symbol combination related to "Chile Lip" is notified (for example, information to the player to aim at the Chile symbol by pushing forward is notified). On the other hand, in this flag conversion process, when the flag conversion lottery becomes non-winning and the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is converted to the sub-flag EX "replay (01)", the abbreviation is changed to "replay". Information for displaying the symbol combination is notified (for example, a pressing order other than forward pressing (irregular pressing) is notified).

Further, for example, when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is determined, as shown in FIG. 38B, the internal winning combinations “F_reach eye lip A” to “F_reach eye lip A” to “ "F_reach eye lip D" is converted into subflags "reach eye lip 1 (04)" to "reach eye lip 4 (07)", respectively.

Next, the sub-flags "reach-eye lip 1 (04)" to "reach-eye lip 4 (07)" become the sub-flag EX "reach-eye lip (08)" or "fixed combination (06)" when the flag conversion lottery is won. Will be converted. On the other hand, when the flag conversion lottery is not won, the sub-flags "reach-eye lip 1 (04)" to "reach-eye lip 4 (07)" are converted into the sub-flag EX "replay (01)".

As described in FIG. 24, when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is won, the symbol combination related to the abbreviation "reach eye lip" is used when the push order is correct. Is displayed, and when the push order is incorrect, the symbol combination related to the abbreviation "replay" is displayed. Therefore, in the present embodiment, when any one of the internal winning combination "F_reach eye lip A" to "F_reach eye lip D" is determined and the flag conversion lottery is won, the internal winning combination "F_reach eye" is determined. All of "Rip A" to "F_reach eye lip D" are treated as the combination of the sub-flag EX "reach eye lip (08)" or "fixed combination (06)".

Then, when the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" are converted into, for example, the sub-flag EX "reach eye lip (08)" or "fixed combination (06)" by this flag conversion process. , Information for displaying the symbol combination related to the abbreviation "reach eye lip" is notified (for example, information to the player to aim at the symbol "white 7" by pushing forward is notified). On the other hand, in this flag conversion process, when the flag conversion lottery becomes non-winning and the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" are converted into the sub-flag EX "replay (01)", it is abbreviated. Information for displaying the symbol combination related to "replay" is notified (for example, a pressing order other than forward pressing (irregular pressing) is notified).

Further, in the present embodiment, in the flag conversion process shown in FIG. 38A or 38B, when the player wins the flag conversion lottery and performs the stop operation according to the notification, it relates to the abbreviation "triple chili lip" or "reach eye lip". The symbol combination is stopped and displayed on the valid line, and a special privilege is given. In this granting process, a special privilege is given to the player according to the fact that the pachislot 1 wins the flag conversion lottery, but the abbreviation "3" is given to the player. By displaying the symbol combination related to "Ren Chiri Lip", it is possible to feel that a special privilege has been given.

In order to enhance the playability of pachislot, it may be preferable that the appearance frequency of the symbol combination to which the privilege is given is different depending on the state rather than being constant. Since the stop control (displayed symbol combination) differs depending on the type of internal winning combination, as a method of changing the appearance frequency of the symbol combination to which the privilege is given depending on the state, the winning probability of the internal winning combination is changed. A method is also conceivable (in pachislot 1, the winning probability of the internal winning combination can be different depending on the presence or absence of the bonus operation and the RT state. Therefore, for example, as the RT state corresponding to the ART game state, only the RT4 state is considered. Instead, a method of providing another RT state such as an RT6 state or an RT7 state is also conceivable). However, since the opportunity to make the winning probability of the internal winning combination different (the opportunity to shift to the RT state) is limited, this method lacks flexibility from the viewpoint of improving playability (interestingness).

On the other hand, in the pachislot machine 1 of the present embodiment, in addition to the internal lottery for determining the internal winning combination, the flag conversion lottery and the notification based on the lottery result are performed without changing the winning probability of the internal winning combination. , The appearance frequency of the symbol combination to which the privilege is given can be flexibly changed according to the state. That is, in a state where it is easy to win the flag conversion lottery, the appearance frequency of the symbol combination to which the privilege is given can be increased, and conversely, in a state where it is difficult to win the flag conversion lottery, the appearance of the symbol combination to which the privilege is given appears. The frequency can be reduced.

<Gameability during general game state>
Next, the flow of the game during the general game state will be described with reference to FIGS. 39A to 39C. In the pachislot machine 1 of the present embodiment, the gaming state shifts from the normal gaming state to the CZ during the general gaming state, and then the gaming state shifts from the CZ to the ART gaming state, whereby the general gaming state (non-ART gaming state) ) To the ART gaming state (see FIGS. 14A and 14B).

FIG. 39A is a diagram showing a flow of a game when the game state shifts from the normal game state to the CZ in the general game state. As shown in FIG. 39A, the normal gaming state has a low probability state and a high probability state as a lottery state of CZ. The low-probability state and the high-probability state are states in which the expectations for winning the CZ lottery performed during the normal gaming state are different from each other, the low-probability state is the state in which it is difficult to win the CZ lottery, and the high-probability state is the CZ. It is in a state where it is easy to win a lottery. Then, when the CZ lottery performed in the game during the normal game state is won, the game state shifts from the normal game state to the CZ.

In the pachislot machine 1 of the present embodiment, a plurality of chance zones of "CZ1", "CZ2" and "CZ3" are provided as CZs (chance zones). CZ1 to CZ3 are chance zones in which the expectation of winning an ART lottery performed in a game during CZ is different from each other, CZ3 is a chance zone in which an ART lottery is always won, and CZ1 and CZ2 have a predetermined probability. This is a chance zone to win the ART lottery. In the CZ lottery performed in the game during the normal game state, not only the winning / non-winning of the CZ but also the type of CZ (any of CZ1 to CZ3) to be transferred at the time of winning is determined (see FIG. 41 described later).

FIG. 39B is a diagram showing a game flow when the game state shifts from the general game state CZ1 and CZ2 to the ART game state. Both CZ1 and CZ2 are composed of a first half portion and a second half portion. The first half is a period for promoting the rank of the expectation of winning the ART lottery performed in the game during CZ, and the second half is a predetermined production of the lottery result of the ART lottery based on the rank (in this embodiment, the character). It is a period to be notified by (battle production by).

In CZ1, six modes (modes 1 to 6) are prepared as ranks, and the higher the mode, the higher the expectation of winning the ART lottery. In the first half of CZ1, the game is continuously played for the period of the first predetermined number of games (for example, 12 games at the maximum), and the mode promotion lottery is performed based on the internal winning combination. Then, in the first game of the latter half of CZ1, ART lottery is performed based on the mode promoted in the first half (the mode at the end of the first half).

In addition, in CZ2, points of 10 levels are prepared as ranks, and the higher the points, the higher the expectation of winning the ART lottery. In the first half of CZ2, games are continuously played for a period of a second predetermined number of games (for example, a maximum of 15 games), and points are promoted by lottery based on the internal winning combination. Then, in the first game of the second half of CZ2, the ART lottery is performed based on the points promoted in the first half (points at the end of the first half).

In the latter half of CZ1, a battle effect in which the ally character and the enemy character A play against each other is performed, and in the latter half of CZ2, a battle effect in which the ally character and the enemy character B play against each other is performed. This battle effect is performed over a period of a third predetermined number of games (for example, a maximum of 4 games). In addition, the victory or defeat of the battle production is managed (determined) based on the result of the ART lottery, and if the ART lottery is won, the ally character wins in the battle production, and if it is not the ART lottery, the battle The enemy character wins in the production.

Further, in each latter half of CZ1 and CZ2 (during the battle production), ART lottery is performed every game based on the internal winning combination. Then, when the ART lottery is won, the result of the battle effect is rewritten. For example, if a so-called "rare" role is determined as an internal winning role during a battle production, an ART lottery is performed, and the result of the battle production is rewritten based on the result.

In CZ1 and CZ2, if the ART is not won, the player is defeated in the battle effect in the latter half, and basically, the game state shifts to the normal game state after that. On the other hand, in CZ1 and CZ2, when the ART is won, the battle effect in the latter half is won, and then the game state shifts from the CZ to the normal ART via the ART preparation state. In addition, in this embodiment, a freeze may occur in the game of the first half of CZ1 and CZ2, and in that case, the game state is changed from CZ via the ART preparation state, and CT (additional addition) instead of normal ART is performed. Move to the chance zone).

FIG. 39C is a diagram showing a game flow when the game state shifts from the general game state CZ3 to the ART game state. The CZ3 is continuously played for a period of a fourth predetermined number of games (for example, 17 games at the maximum). Then, in CZ3, ART lottery is performed every game based on the internal winning combination.

The CZ3 ends when the ART lottery is won, and after the next game, the game state shifts from the CZ3 to the CT (additional chance zone) via the ART preparation state. Further, in CZ3, a freeze may occur, and even in that case, the game state shifts from CZ3 to CT (additional chance zone) via the ART preparation state after the next game. On the other hand, in CZ3, when the game period (fourth predetermined number of games) of CZ3 elapses without winning the ART lottery, the game state shifts from CZ3 to normal ART via the ART preparation state. That is, in the present embodiment, CZ3 is a chance zone in which the transition to the ART gaming state is confirmed.

<Various data tables used during the general game state>
Subsequently, with reference to FIGS. 40 to 45, various data tables used in the lottery process relating to the playability performed during the general game state will be described. The various data tables described below are stored in the main ROM 102.

Further, in the various data tables shown below, information on the lottery value is conceptually shown. "0" in the data table means that the lottery value corresponding to the winning probability "0%" is specified, and "extremely low" means the lottery corresponding to the winning probability "0% to less than 1%". It means that the value is specified, and "extremely low" means that the lottery value corresponding to the winning probability "1% to less than 10%" is specified. In addition, "low" in the data table means that a lottery value corresponding to a winning probability of "10% to less than 30%" is specified, and "medium" means a winning probability of "30% to less than 60%". It means that the lottery value corresponding to "" is specified, and "high" means that the lottery value corresponding to the winning probability "60% to less than 80%" is specified. Further, "extremely high" in the data table means that a lottery value corresponding to a winning probability of "80% to less than 99%" is defined, and "extremely high" means a winning probability of "99% to less than 99%". It means that the lottery value corresponding to "less than%" is specified, and "confirmed" means that the lottery value corresponding to the winning probability "100%" is specified.

Then, in the various data tables shown below, the random number register 1 of the random number circuit 110 sequentially subtracts the lottery random number values extracted from the predetermined numerical value range (0 to 65535) by the specified lottery values. , Internal lottery is performed by determining whether or not the result of subtraction is negative (whether or not so-called "digits" have occurred). In the present embodiment, an example in which the lottery value is subtracted from the lottery random value to determine the winning / non-winning in the lottery process related to the playability performed during the general game state has been described, but the present invention is limited to this. Instead, the lottery value is added to the extracted random number value for lottery, and it is determined whether or not the addition result exceeds 65536 (whether or not a so-called "digit overflow" has occurred), and the winning / non-winning is determined. May be good.

[Normal medium and high probability lottery table]
First, with reference to FIGS. 40A and 40B, a normal medium-high probability lottery table used in the transition lottery of the lottery state (low probability and high probability) of CZ will be described. In the pachislot machine 1 of the present embodiment, not only the transition lottery of the lottery state of the CZ is performed based on the internal winning combination in each game, but also at the end of the bonus, the end of the CZ, the end of the ART, etc. Transition of lottery state A lottery is performed. FIG. 40A is a configuration diagram of a normal middle-high probability lottery table that is referred to every game during the normal game state, and FIG. 40B is a normal middle-high that is referred to at the time of setting change, bonus end, CZ, ART end, etc. It is a block diagram of the probability lottery table. The name of the internal winning combination shown in FIG. 40A corresponds to the name of the sub-flag described above.

The normal medium-high probability lottery table shown in FIG. 40A shows each combination of the current CZ lottery state and the internal winning combination, the lottery result (low probability / high probability) of the CZ lottery state after the transition, and each lottery result. The correspondence with the associated lottery value information is specified.

As is clear from the normal medium-high probability lottery table shown in FIG. 40A, when the current lottery state of CZ is low probability, when the internal winning combination is the combination corresponding to the sub-flag "weak cherry", the CZ The lottery state is likely to shift to a high probability. On the other hand, when the current CZ lottery state has a high probability, when the internal winning combination is a combination corresponding to any of the subflags "common bell", "cactus", "weak cherry" and "strong cherry". In addition, the lottery state of CZ is maintained with high probability.

In the normal medium-high probability lottery table shown in FIG. 40B, each situation when referring to the table, the lottery result (low probability / high probability) of the lottery state of CZ after the transition, and the lottery associated with each lottery result. Define the correspondence with the value information. As is clear from the normal medium-high probability lottery table shown in FIG. 40B, the lottery state of CZ always shifts to a high probability at the end of the bonus.

[CZ lottery table]
Next, the CZ lottery table used in the CZ lottery will be described with reference to FIGS. 41A and 41B. FIG. 41A is a configuration diagram of a CZ lottery table used when performing a CZ lottery based on an internal winning combination during a normal game state, and FIG. 41B shows a CZ pullback at the time of CZ failure or ART end, for example. It is a block diagram of the CZ lottery table used when performing the CZ lottery whether or not to perform. The name of the internal winning combination shown in FIG. 41A corresponds to the name of the sub-flag described above.

The CZ lottery table shown in FIG. 41A shows each combination of the current CZ lottery state and the internal winning combination, the winning / non-winning (lottery result) of CZ1, CZ2, and CZ3, and the lottery associated with each lottery result. Specify the correspondence with the value information. As is clear from the CZ lottery table shown in FIG. 41A, when the current CZ lottery state is in the high probability, the CZ lottery is won more than in the case where the current CZ lottery state is in the low probability. The probability is high.

In the CZ lottery table shown in FIG. 41B, the correspondence between the winning / non-winning (lottery result) of CZ1, CZ2, and CZ3 at the time of CZ failure or the end of ART and the information of the lottery value associated with each lottery result. To specify. At the time of CZ failure (when the ART lottery in CZ1 and CZ2 is not won) or at the end of the ART game state, the CZ pullback lottery is performed using this CZ lottery table.

[CZ1 medium mode up lottery table]
Next, with reference to FIG. 42, the CZ1 medium mode-up lottery table used in the CZ1 mode-up lottery performed in the first half of CZ1 will be described. FIG. 42 is a configuration diagram of a mode-up lottery table in CZ1. The name of the internal winning combination shown in FIG. 42 corresponds to the name of the sub-flag described above.

The CZ1 medium mode-up lottery table has a correspondence relationship between each combination of the current mode and the internal winning combination, the mode-up lottery result (winning / non-winning), and the lottery value information associated with each lottery result. To specify. As shown in FIG. 44A described later, in CZ1, the higher the mode (the higher the value of the mode), the higher the probability of winning the ART lottery, and when the mode goes up to the mode 6, the ART lottery is always won.

The lottery result "mode 1 UP" in FIG. 42 means that the mode of CZ1 is raised by one step, and the lottery result "mode 2 UP" means that the mode of CZ1 is raised by two steps. Therefore, for example, in a situation where the current mode is mode 2, if the lottery result "mode 2 UP" is won, the mode of CZ1 goes up from mode 2 to mode 4. Further, for example, when the lottery result "mode 6UP_freeze occurrence" is won, the freeze occurs, and the winning of the ART lottery and the granting of CT are determined.

[CZ2 middle point lottery table]
Next, the CZ2 middle point lottery table used in the CZ2 point-up lottery performed in the first half of the CZ2 will be described with reference to FIG. 43. FIG. 43 is a configuration diagram of a point lottery table in CZ2. The name of the internal winning combination shown in FIG. 43 corresponds to the name of the sub-flag described above.

The CZ2 middle point lottery table shows the correspondence between each combination of the current points and the internal winning combination, the result of the point-up lottery (winning / non-winning), and the lottery value information associated with each lottery result. Prescribe. As shown in FIG. 44B described later, in CZ2, the higher the points, the higher the probability of winning the ART lottery, and when the points rise to "point 10", the ART lottery is always won. The lottery result "point 2 UP" in FIG. 43 means that "2" is added to the points of the current CZ2. For example, in a situation where the current point is "2", the lottery result "point 2 UP" If you win "Point 2 UP", the points of CZ2 will increase from "2" to "4". Further, for example, when the lottery result "point 10UP_freeze occurrence" is won, the freeze occurs, and the winning of the ART lottery and the granting of CT are determined.

[ART lottery table in CZ]
Next, the ART lottery table in CZ used in the ART lottery performed during CZ will be described with reference to FIGS. 44A-44C and 45. Note that FIG. 44A is a configuration diagram of an ART lottery table in CZ (for CZ1) used in the first game of the latter half of CZ1, and FIG. 44B is an ART in CZ used in the first game of the latter half of CZ2. It is a block diagram of the lottery table (for CZ2), and FIG. 44C is a block diagram of the ART lottery table in CZ (common to CZ1, CZ2 for the latter half of the battle) used in the latter half of CZ1 and CZ2. Further, FIG. 45 is a configuration diagram of an ART lottery table (for CZ3) in CZ used in the ART lottery executed in CZ3. The names of the internal winning combinations shown in FIGS. 44C and 45 correspond to the names of the sub-flags described above.

The ART lottery table in CZ (for CZ1) shown in FIG. 44A defines the correspondence between the current mode, the result of the ART lottery (presence or absence of winning), and the information of the lottery value associated with each lottery result. .. Further, the ART lottery table (for CZ2) in CZ shown in FIG. 44B shows the correspondence between the current points, the result of the ART lottery (presence or absence of winning), and the information of the lottery value associated with each lottery result. Prescribe.

As is clear from the ART lottery table in CZ (for CZ1) and the ART lottery table in CZ (for CZ2), in CZ1 and CZ2, the higher the rank (mode or point) of the first half, the easier it is to win the ART lottery.

The ART lottery table in CZ (common to CZ1 and CZ2 for the latter half of the battle) shown in FIG. 44C includes the internal winning combination, the result of the ART lottery (presence or absence of winning), and the lottery value information associated with each lottery result. Prescribe the correspondence of. As is clear from the ART lottery table in CZ (common to CZ1 and CZ2 for the latter half of the battle), in the latter half of CZ1 and CZ2, the role corresponding to the rare role (sub-flags "weak cherry", "cactus" or "strong cherry". ) Is determined as the internal winning combination, and the ART lottery is won with a predetermined probability.

The ART lottery table (for CZ3) in CZ shown in FIG. 45 shows each combination of the number of digestion games of CZ3 and the internal winning combination, the result of ART lottery (presence or absence of winning), and the lottery associated with each lottery result. Define the correspondence with the value information. As is clear from the ART lottery table in CZ (for CZ3), in the present embodiment, when the ART lottery is won in CZ3, the CT is always won.

<Playability during normal ART>
Next, the flow of the game during the game ART will be described with reference to FIGS. 46A and 46B. In the pachi-slot machine 1 of the present embodiment, as described above, normally ART and CT are provided as ART gaming states (see FIGS. 14A and 14B), and the inside of CT is used as an additional chance zone. Therefore, in the present embodiment, the player usually plays a game during ART with the aim of shifting to CT.

[Mode of transition from normal ART to CT]
FIG. 46A is a diagram showing a mode of transition of the gaming state from normal ART to CT. In the pachislot machine 1 of the present embodiment, as shown in FIG. 46A, when the CT lottery performed during the normal ART is won, the gaming state shifts from the normal ART to the CT. As shown in FIG. 46A, the pachislot machine 1 of the present embodiment is provided with an ART level and a CT lottery state as parameters that affect various lottery normally performed during ART.

As the ART level, four levels of levels 1 to 4 are provided, and this ART level is controlled (determined) mainly based on the number of continuous (digestion) games during normal ART. Then, the ART level affects the determination of the CT lottery state, the flag conversion lottery during the normal ART, which will be described later, and the like.

The CT lottery state is provided with four stages of low probability, normal, high probability, and ultra-high probability, and the CT lottery state is controlled mainly based on the ART level and the internal winning combination during normal ART ( It is determined. Then, the CT lottery state affects the CT lottery performed during the normal ART, the flag conversion lottery during the normal ART described later, and the like.

[Flag conversion during normal ART]
As described above, in the pachislot machine 1 of the present embodiment, during the RT4 state, that is, during the ART gaming state, the internal winning combinations "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_" When any one of "Reach Eye Lip D" is independently determined as an internal winning combination, a flag conversion lottery is performed, and a special privilege (for example, an addition of the number of ART games or a CT winning) is given according to the lottery result. .. FIG. 46B is a diagram showing an outline of a method of flag conversion lottery usually performed during ART.

In the present embodiment, as shown in FIG. 46B, the flag conversion lottery is performed in the normal ART with reference to the ART level and the CT lottery state. As a result, when the flag conversion lottery is won, a special privilege is given, and the symbol combination related to the abbreviation "triple chili lip" and the symbol combination related to the abbreviation "reach eye lip" are stopped and displayed on the effective line. Navigation (for example, notification of information to aim at a predetermined symbol by pushing forward) is performed. On the other hand, if the flag conversion lottery is not won, navigation (for example, notification of a push order other than forward push) is performed to stop and display the symbol combination related to the abbreviation "replay" on the effective line.

Then, when the player performs a stop operation according to this notification (navigation), the symbol combination according to the notification content is stopped and displayed on the effective line. Specifically, when the flag conversion lottery is won, the symbol combination related to the abbreviation "triple chili lip" and the symbol combination related to the abbreviation "reach eye lip" are stopped and displayed on the effective line, and are not displayed in the flag conversion lottery. In the case of winning, the symbol combination related to the abbreviation "replay" is stopped and displayed on the effective line.

<Various data tables normally used during ART>
Next, with reference to FIGS. 47 to 51, various data tables normally used in the lottery process during ART will be described. The various data tables described below are stored in the main ROM 102.

[Flag conversion lottery table during ART]
FIGS. 47A and 47B are configuration diagrams of a flag conversion lottery table during ART used in a flag conversion lottery normally performed during ART.

In the pachi-slot machine 1 according to the present embodiment, the flag conversion lottery during normal ART is performed in two stages. Specifically, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won, the first stage flag conversion lottery is first performed, and if the first stage flag conversion lottery is won, then The second stage flag conversion lottery is performed. Then, when the second-stage flag conversion lottery is won, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is converted into the sub-flag EX "triple chili lip". On the other hand, if the first-stage flag conversion lottery or the second-stage flag conversion lottery is non-winning, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is converted to the sub-flag EX "replay". (Treat as a normal replay role). If any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is won, only the second stage flag conversion lottery is performed.

FIG. 47A is a configuration diagram of the flag conversion lottery table during ART used in the first stage flag conversion lottery, and FIG. 47B is a configuration diagram of the flag conversion lottery table during ART used in the flag conversion lottery of the second stage. is there.

The flag conversion lottery table during ART shown in FIG. 47A has an internal winning combination (“F_certain chili lip” or “F_1 certain chili lip”) and a lottery result of the first stage flag conversion lottery (no conversion / with conversion (provisional)). And the correspondence relationship with the lottery value information associated with each lottery result is defined.

The flag conversion lottery table during ART shown in FIG. 47B shows each combination of the internal winning combination, the ART level, and the CT lottery state, the lottery result of the second stage flag conversion lottery (without conversion / with conversion), and each lottery result. The correspondence with the lottery value information associated with is specified. In the game until the CT is won once in the normal ART, the table in the "First time (until the CT is won once)" column of the item "ART level" in FIG. 47B is referred to.

In the present embodiment, as shown in FIGS. 47A and 47B, in the first-stage and second-stage flag conversion lottery using each of the flag conversion lottery tables during ART, a random number value (0 to 0) having a probability denominator of "256". A lottery is performed using 255). Therefore, in the present embodiment, the above-mentioned two-step flag conversion lottery can be regarded as substantially the same lottery as the case where one lottery is performed using a random number value whose probability denominator is "65536".

In recent pachislot machines, the lottery (ART lottery, etc.) related to ball ejection, which was conventionally performed on the sub control board 72 side (hereinafter referred to as "sub side"), is performed on the main control board 71 side (hereinafter referred to as "main side"). It is required to do. However, since the capacity of the storage means (main ROM 102) on the main side is limited to a small capacity, there is a demand for a mechanism that enables lottery without impairing game playability while suppressing an increase in processing capacity.

Regarding this point, in the pachi-slot machine 1 of the present embodiment, the lottery having the probability denominator of "256" can be performed in two stages, so that the lottery having the probability denominator of "65536" can be performed. The increase in capacity on the side can be suppressed. Further, in the second stage lottery, since the ART level, the CT lottery state, etc. are referred to, not only the internal winning combination but also the flag conversion lottery according to the current state can be performed, and as a result, various playability can be achieved. You can perform a flag conversion lottery with you.

[ART level determination table]
FIGS. 48A and 48B are block diagrams of an ART level determination table used when determining an ART level. The ART level determination process is performed at the time of winning the ART when the transition to the ART gaming state is decided, and during the normal ART. FIG. 48A is a configuration diagram of an ART level determination table used at the time of winning ART, and FIG. 48B is a configuration diagram of an ART level determination table normally used during ART.

The ART level determination table shown in FIG. 48A defines the correspondence between the ART levels 1 to 4 (lottery results) and the lottery value information associated with each ART level. In the present embodiment, if a freeze occurs at the time of winning the ART, the ART level 2 is determined as the ART level.

The ART level determination table shown in FIG. 48B is a lottery associated with each combination of the current ART level and the number of elapsed (digested) games of the normal ART, various ART levels of the migration destination, and each ART level of the migration destination. Specify the correspondence with the value information. Further, the ART level determination table shown in FIG. 48B corresponds to each combination of the current ART level and the number of elapsed games of the normal ART at the time of CT entry, various ART levels of the migration destination, and each ART level of the migration destination. The correspondence with the information of the lottery value obtained is specified. That is, during normal ART, not only the ART level can be shifted when the number of elapsed (digested) games of normal ART reaches a predetermined number of games, but also the ART level can be changed at the timing of entering CT during normal ART. It becomes possible to migrate.

[Normal ART medium and high probability lottery table]
FIG. 49 is a block diagram of a normal ART medium-high probability lottery table used when determining a CT lottery state during normal ART.

The normal ART medium-high probability lottery table has a correspondence relationship between each combination of the current CT lottery state and the internal winning combination, various CT lottery states of the migration destination, and lottery value information associated with each CT lottery state. Prescribe. The name of the internal winning combination shown in FIG. 49 corresponds to the name of the sub-flag described above.

As is clear from the normal ART medium and high probability lottery table, the internal winning combination corresponding to the sub-flag "triple chili lip (triple chili lip A and triple chili lip B)" and the sub-flag "reach eye lip (reach eye lip 1-4)". If you win, the CT lottery state is likely to shift (fall) to a "low probability". However, as shown in FIG. 50 described later, when the internal winning combination corresponding to the sub-flags "triple chili lip" and "reach eye lip" is won, even if the CT lottery state falls, CT The structure is such that the lottery is always won.

[CT lottery table during ART]
FIG. 50 is a block diagram of a CT lottery table during ART used in a CT lottery normally performed during ART.

The CT lottery table during ART shows each combination of the current CT lottery state and the internal winning combination, various lottery results (non-winning / normal CT / high probability CT) of the CT lottery, and a lottery associated with each lottery result. Define the correspondence with the value information. The name of the internal winning combination shown in FIG. 50 corresponds to the name of the sub-flag described above.

In the present embodiment, the sub-flags "cactus", "weak cherry", "strong cherry", "triple chili lip (triple chili lip A and triple chili lip B)", and "reach eye lip (reach eye lip)" are used as internal winning roles. When the combination corresponding to "1 to 4)" or "BB" is determined, in the CT lottery processing using the CT lottery table during ART, the CT lottery using the random value in the range where the probability denominator is "256" Is done. In addition, if an internal winning combination other than these roles (for example, a combination corresponding to the sub-flags "replay", "common bell", "pushing order bell", etc.) is determined as the internal winning combination, CT during ART In the CT lottery process using the lottery table, CT lottery using random values in the range where the probability denominator is "65536" is performed.

In the pachislot machine 1 of the present embodiment, two types of CTs called "normal CT" and "high probability CT" are provided as CTs. Normal CT and high-probability CT have different expectations for the number of ART games added during CT (addition chance zone), and high-probability CT is a CT in which a larger number of ART games are more likely to be added than normal CT. (See FIG. 55 below).

[Normal ART extra lottery table]
FIG. 51 is a configuration diagram of an additional lottery table during normal ART, which is used in an additional lottery for the number of ART games performed during normal ART. The name of the internal winning combination shown in FIG. 51 corresponds to the name of the sub-flag described above.

Normally, the additional lottery table during ART defines the correspondence between the internal winning combination, various lottery results (non-winning / additional 10G to 300G) of the additional lottery, and the lottery value information associated with each lottery result.

<Playability during CT>
Next, the flow of the game during CT will be described with reference to FIGS. 52A to 52C. It should be noted that FIGS. 52A and 52B are mainly diagrams showing an outline of the game flow during CT at the time of winning the sub-flag EX "triple chili lip", and FIG. 52C shows an outline of the flag conversion process performed during CT. It is a figure.

[Game content during CT]
In the pachislot machine 1 of the present embodiment, in CT, one set of eight games (8 games) is played. During the CT period, an additional lottery for the number of ART games is performed based on the internal winning combination for each game. Then, when the additional lottery is won, the unit game number (game number) of the CT game is not subtracted, while when the additional lottery is non-winning, the unit game number (game number) of the CT game is not subtracted. Number) is subtracted. Therefore, during the CT period, the CT does not end in the game in which the number of ART games is added, and the CT ends when the game in which the number of ART games is not added is performed eight times in the same set. ..

Further, in the present embodiment, as shown in FIGS. 52A and 52B, when the sub-flag EX "triple chili lip" is won during the CT period, that is, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won. However, if the flag conversion lottery is won, the CT games 8 times per set are reset (stocked). Then, the set of the reset (stocked) CT game is started after the set of the CT game is completed.

For example, in the same set, after the unit game that is not a winning lottery is played 7 times in the lottery for adding the number of ART games, the CT ends when the CT game in which the number of ART games is not added is played once. If the sub-flag EX "Triple Chili Lip" is won, the CT game is reset. As a result, after the CT game is reset, the CT will not end until the unit game, which is a non-winning unit game, is performed eight times in the additional lottery for the number of ART games. Therefore, the game period of CT becomes long enough to win the sub-flag EX "triple chili lip".

[Flag conversion during CT]
Next, with reference to FIG. 52C, a method of flag conversion lottery performed during CT will be described. As described above, in the present embodiment, when the sub-flag EX "triple chili lip" is won during the CT period (internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won, and the flag conversion lottery is won. Then, CT is reset (stocked). Further, as shown in the CT flag conversion lottery table of FIG. 54 described later, if the internal winning combination “F_certain chili lip” or “F_1 certain chili lip” is won during CT, the flag conversion lottery is always won (sub-flag EX “sub-flag EX”. It will always be converted to "triple chili lip"). That is, in the present embodiment, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won during CT, the CT is always reset.

Further, in the flag conversion lottery when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is won, the flags are based on three types of flag conversion tables (tables 0 to 2). The winning probability of the conversion lottery is controlled. Specifically, as shown in FIG. 52C, table 0 is a flag conversion table having the lowest probability of being converted to the sub-flag EX "reach eye lip", and table 1 is converted to the sub-flag EX "reach eye lip". It is a flag conversion table having the next lowest probability, and table 2 is a flag conversion table having the highest probability of being converted to the sub-flag EX “reach eye lip”. If the sub-flag EX "reach eye lip" is won during CT, CT is newly added as shown in the lottery table for adding the number of sets in CT described later in FIG. 56.

Further, in the present embodiment, in normal CT, as shown in FIG. 52C, the flag conversion table is determined based on the ART level. On the other hand, in high-probability CT, table 0 is always determined as the flag conversion table regardless of the ART level.

<Various data tables used during CT>
Next, various data tables used in the lottery process performed during CT will be described with reference to FIGS. 53 to 56. The various data tables described below are stored in the main ROM 102.

[Table during CT lottery table]
FIG. 53 is a configuration diagram of a CT table lottery table used when determining a table to be used for the flag conversion lottery from the three-stage flag conversion tables (tables 0 to 2).

The lottery table during CT shows the correspondence between each state such as the ART level and the type of CT to be executed, the type of the flag conversion table (tables 0 to 2), and the lottery value information associated with each type. Prescribe. The table lottery table during CT is referred to when it is decided to win the CT lottery and shift to CT, or at the start of CT.

[Cut flag conversion lottery table]
FIG. 54 is a configuration diagram of a flag conversion lottery table during CT used in a flag conversion lottery performed during CT.

The flag conversion lottery table during CT includes an internal winning combination (one of "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_reach eye lip D") and each flag conversion table ( The correspondence between the lottery result (without conversion / with conversion) of the flag conversion lottery in Tables 0 to 2) and the lottery value information associated with each lottery result is defined. As is clear from the flag conversion lottery table during CT, if the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won during CT, the flag conversion lottery is always won (sub-flag EX "triple chili lip" is always won). Will be converted).

[Additional lottery table during CT]
FIG. 55 is a configuration diagram of an additional lottery table during CT used in an additional lottery for the number of ART games performed during CT.

The additional lottery table during CT is associated with each combination of the current CT state and the internal winning combination, various lottery results of the additional lottery (non-winning / additional 10 games / ... / additional 300 games), and each lottery result. The correspondence with the lottery value information is specified. The name of the internal winning combination shown in FIG. 55 corresponds to the name of the sub-flag described above, and when a combination other than the internal winning combination (sub-flag) shown in FIG. 55 is internally won, the additional lottery during CT is won. There is nothing to do.

Further, in the additional lottery during the normal CT of the present embodiment, the form of giving the number of additional games changes according to the number of wins of the sub-flag "triple chili lip" (internal winning combination "F_certain chili lip" or "F_1 certain chili lip"). To do.

Specifically, when the number of times the sub-flag "triple chili lip" is won in the same CT set is 1 to 8, it is given by the lottery results "addition_10G" and "addition_20G" shown in FIG. 55. The number of additional games will be 10 games and 20 games, respectively. Therefore, in this case, 10 games can be easily determined as the number of additional games of ART. Further, when the number of winnings of the sub-flag "triple chili lip" in the same CT set is 9 to 16 times, the additional game given by the lottery results "addition_10G" and "addition_20G" shown in FIG. 55. Both numbers will be 20 games. That is, the number of additional games (lottery result) corresponding to the lottery value "extremely high" of the sub-flag "triple chili lip" in FIG. 55 is promoted to 20 games. Therefore, in this case, 20 games can be easily determined as the number of additional games for ART.

Further, when the number of winnings of the sub-flag "triple chili lip" in the same CT set is 17 to 24 times, the additional game given by the lottery results "addition_10G" and "addition_20G" shown in FIG. 55. Both numbers will be 30 games. That is, the number of additional games (lottery result) corresponding to the lottery values "extremely high" and "extremely low" of the sub-flag "triple chili lip" in FIG. 55 is promoted to 30 games. Therefore, in this case, "30 games" can be easily determined as the number of additional games for ART. Further, when the number of winnings of the sub-flag "triple chili lip" in the same CT set is 25 times or more, the number of additional games given by the lottery results "addition_10G" and "addition_20G" shown in FIG. 55. Will both be 50 games. That is, the number of additional games (lottery result) corresponding to the lottery values "extremely high" and "extremely low" of the sub-flag "triple chili lip" in FIG. 55 is promoted to 50 games. Therefore, in this case, "50 games" can be easily determined as the number of additional games for ART.

As described above, in the pachislot machine 1 of the present embodiment, it is possible to increase the number of ART games that can be added by one additional lottery according to the number of times the sub-flag "triple chili lip" is won during CT. Further, as described above, in the present embodiment, as long as the number of ART games is added, the CT does not end, and when the sub-flag EX "triple chili lip" is applied, the CT is reset (stock). Is done. Therefore, in the present embodiment, the player can be expected to increase the additional amount per game as the CT continues, and the interest during the CT can be improved. In addition, the number of winnings of the sub-flag "Triple Chili Lip", which is an opportunity to increase the amount of addition per game, is more than the basic number of games (8 times) for one set of CT (9 times or more). It is possible to prevent an excessive profit from being given to the game, and it is possible to balance the profit between the player and the game store.

In the present embodiment, the number of winnings of the above-mentioned sub-flag "triple chili lip" (internal winning combination "F_certain chili lip" or "F_1 certain chili lip") is the number of times counted in the same CT set. The present invention is not limited to this. For example, a new CT given when a lottery for adding the number of sets performed during CT is won may be included in "in the same CT set".

[Lottery table with additional sets during CT]
FIG. 56 is a configuration diagram of an additional lottery table for the number of sets in CT used in the additional lottery for CT sets performed during CT.

The lottery table for adding the number of sets during CT is a combination of the current CT state and the internal winning combination (sub-flag "reach-eye rip (reach-eye rips 1 to 4)"), and various lottery results of the additional lottery (non-winning / normal). The correspondence between the CT winning / high-probability CT winning) and the lottery value information associated with each lottery result is defined.

As is clear from the additional lottery table for the number of sets during CT, if you win any of the internal winning roles "F_reach eye lip A" to "F_reach eye lip D" during CT, you will definitely win the additional lottery for the CT set. (The CT set is always stocked). The stocked CT set is started after the currently operating CT set is completed.

<Playability in bonus state>
Next, the flow of the game in the bonus state will be described with reference to FIGS. 57A to 57C. FIG. 57A is a diagram showing the flow of the game when the gaming state shifts to the bonus state during the general gaming state (ART non-winning), and FIG. 57B shows the case where the gaming state shifts to the bonus state during normal ART. FIG. 57C is a diagram showing the flow of the game in the above, and FIG. 57C is a diagram showing the flow of the game when the game state shifts to the bonus state during CT.

In the pachislot machine 1 of the present embodiment, as shown in FIGS. 57A to 57C, a normal BB and a special BB are provided as bonus types in terms of playability, and the type of this bonus is determined at the time of transition to the bonus state. Will be done. At this time, if the special BB is determined, the gaming state shifts to CT via the ART preparation state after the end of the bonus state. On the other hand, when the normal BB is determined, the game state of the transition destination differs depending on the state before the transition to the bonus state.

When the gaming state shifts from the general gaming state to the normal BB, as shown in FIG. 57A, in the game during the normal BB, the ART lottery is performed based on the internal winning combination. Then, when the ART lottery is won, the game state shifts to the normal ART via the ART preparation state after the end of the bonus state. In this case, in the game in the bonus state after winning the ART lottery, the number of ART games is added to the lottery.

When the gaming state shifts from the normal ART to the normal BB, as shown in FIG. 57B, a CT lottery is performed at the end of the normal BB. The winning probability of this CT lottery is 50%, and when the winning is done, the gaming state shifts to CT via the ART preparation state after the end of the bonus state. On the other hand, when the CT lottery is not won, the game state shifts to the normal ART via the ART preparation state after the end of the bonus state. In addition, in the game in the bonus state that has been transferred from the normal ART, an additional lottery for the number of ART games is also performed.

When the gaming state shifts from CT to normal BB or special BB, as shown in FIG. 57C, the gaming state shifts to CT via the ART preparation state after the end of the bonus state. In addition, in the game in the bonus state transferred from CT, an additional lottery for the number of ART games is also performed.

<Various data tables used in games in the bonus state>
Subsequently, with reference to FIGS. 58 to 60, various data tables used in the lottery process performed in the game in the bonus state will be described. The various data tables described below are stored in the main ROM 102.

[Bonus type lottery table]
FIG. 58 is a configuration diagram of a bonus type lottery table used when determining a bonus type (normal BB, special BB).

The bonus type lottery table shows each game state (CT and others) before the transition to the bonus state, various lottery results (bonus type: normal BB / special BB), and a lottery value associated with each lottery result. Define the correspondence with information. The bonus type determination process with reference to the bonus type lottery table is performed at the start of the bonus state.

[Lottery table with the number of ART games added during the bonus]
FIG. 59 is a configuration diagram of a lottery table for adding the number of ART games in the bonus used in the ART lottery and the lottery for adding the number of ART games performed in the game in the bonus state.

The lottery table for adding the number of ART games in the bonus is associated with each combination of the current bonus type and the internal winning combination, various lottery results of the additional lottery (non-winning / 5 games / ... / 300 games), and each lottery result. The correspondence with the information of the lottery value obtained is specified.

In the present embodiment, in the ART non-winning state (the state until the ART lottery is won in the normal BB shifted from the general game state), the lottery table for adding the number of ART games during the bonus is used for the ART lottery. Specifically, in the ART non-winning state, when the number of additional games of one or more games (50 or more in the example shown in FIG. 59) is determined by the lottery using the lottery table for adding the number of ART games during the bonus, the ART Along with winning the lottery, the corresponding number of games is given as the number of ART games. On the other hand, in the state after winning the ART, the lottery table for adding the number of ART games during the bonus is used only for the lottery for adding the number of ART games.

[CT lottery table at the end of bonus]
FIG. 60 is a configuration diagram of a CT lottery table at the end of the bonus used in the CT lottery performed at the end of the bonus state.

The CT lottery table at the end of the bonus shows each combination of the bonus type (normal BB, special BB) and the game state (during normal CT, high probability CT) before shifting to the bonus state, and various lottery results of the CT lottery (during normal CT, high probability CT). The correspondence between the non-winning / normal CT winning / high-probability CT winning) and the lottery value information associated with each lottery result is defined. As is clear from the CT lottery table at the end of the bonus, for example, if a normal BB is performed during a normal ART, there is a 50% chance of winning the CT at the end of the bonus state.

<Exceptional playability during general game state>
Next, with reference to FIG. 61, an exceptional game flow during the general game state will be described.

In the basic flow of the gaming state in the pachislot machine 1 of the present embodiment, the gaming state shifts from the normal gaming state to the CZ during the general gaming state, and the gaming state shifts to the ART gaming state by winning the ART lottery in the CZ. To do. Then, in the present embodiment, the ART gaming state is realized by notifying in the RT4 state. Further, in the present embodiment, as shown in FIG. 61, the transition control of the RT state is performed according to the symbol combination displayed as stopped.

It should be noted that the symbol combination for shifting the RT state is a stop display according to the player's stop operation order (push order) (see FIG. 24), so that the notification may not be performed. By chance, the RT state may shift to the RT4 state. Further, in the RT4 state, one of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" may be determined, so that even during the general gaming state (non-ART), It is possible to display a reach eye (a symbol combination related to the abbreviation "reach eye lip") to which a special privilege is given.

Therefore, in the pachislot machine 1 of the present embodiment, as shown in FIG. 61, the RT state accidentally shifts to the RT4 state during the general gaming state (non-ART), and the symbol combination related to the abbreviation "reach eye lip" can be displayed. In such a state, the gaming state can be shifted to the ART gaming state (normal ART) without going through the CZ.

More specifically, when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is determined in the general game state and in the RT4 state, a flag conversion lottery is performed. When this flag conversion lottery is won, notification (navigation) for displaying the symbol combination related to the abbreviation "reach eye lip" is performed, and the right of ART is granted. On the other hand, when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is determined in the general game state and in the RT4 state, the flag conversion lottery is not won. Notification is performed to display the symbol combination related to the abbreviation "replay", and control is performed so that the symbol combination related to the abbreviation "reach eye lip" is not displayed.

<Various data tables used for exceptional game control during the general game state>
Next, with reference to FIG. 62, a data table used in the lottery process performed in the exceptional game control in the general game state described above will be described. The data table described below is stored in the main ROM 102.

[Non-ART flag conversion lottery table]
FIG. 62 is a configuration diagram of a non-ART flag conversion lottery table used in a flag conversion lottery performed in a game in the general game state and in the RT4 state.

The non-ART flag conversion lottery table has an internal winning combination ("F_reach eye lip A" to "F_reach eye lip D"), a lottery result of the flag conversion lottery (without conversion / with conversion), and each lottery result. The correspondence with the associated lottery value information is specified.

<Notification function controlled by the main side>
In the conventional pachislot machine, information (navigation) of reel stop operation information (pushing order, etc.) is performed by controlling the sub (sub-control board 72) side during ART. However, since the presence or absence of this notification affects the profit of the player (so-called ball ejection), in recent years, it has been required to perform the notification on the main (main control board 71) side that manages the profit of the player. There is. Therefore, in the pachi-slot machine 1 of the present embodiment, as described above, the information display 6 controlled on the main side is provided with an instruction monitor (not shown) for notifying the information of the stop operation, and is controlled by the main side. A function for notifying information on the reel stop operation is provided.

Here, FIGS. 63A to 63D show the correspondence between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in the pachislot machine 1 of the present embodiment. Note that FIG. 63A is a diagram showing a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in the ART preparation state, and FIG. 63B is a diagram during ART (normal ART or CT). It is a figure which shows the correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side. Further, FIG. 63C is a diagram showing a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the RT5 state (between the BB1 flags), and FIG. 63D is a diagram showing the correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side. It is a figure which shows the correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in (between BB2 flags).

In the present embodiment, as shown in FIGS. 63A to 63D, on the main (main control board 71) side, the information of the reel stop operation is notified by displaying the numerical values of "1" to "11" on the instruction monitor. To do. The numerical values "1" to "11" displayed on the instruction monitor uniquely correspond to the contents of the stop operation notified by each.

Specifically, the numerical values "1" to "3" indicate the types of reels that perform the first stop operation, and the numerical values "1" mean that the first stop operation is performed on the left reel 3L. Then, the numerical value "2" means that the first stop operation is performed on the middle reel 3C, and the numerical value "3" means that the first stop operation is performed on the right reel 3R.

Further, the numerical values "4" to "9" indicate the push order to be notified, and the numerical value "4" means that the push order is "left, middle, right", and the numerical value "5". Means that the push order is "left, right, middle", the numerical value "6" means that the push order is "middle, left, right", and the numerical value "7" is the push order. The order is "middle, right, left", the numerical value "8" means that the pushing order is "right, left, middle", and the numerical value "9" is the pushing order. It means that the order is "right, middle, left".

In addition, the numerical values "10" and "11" respectively notify the bonus combination, and the numerical value "10" is a symbol combination related to the combination name "C_BB1" (design "white 7" -design "white 7"-. The symbol "white 7") is meant, and the numerical value "11" means a symbol combination (symbol "blue 7" -symbol "blue 7" -symbol "blue 7") related to the combination name "C_BB2".

Although the numerical values "1" to "11" notified on the main side (instruction monitor) uniquely correspond to the content of the stop operation to be notified, all players are clear based on the numerical values. It is not always possible to grasp the content of the notification. For example, it may not be possible for some players to grasp the content of the notification simply by displaying the numerical value "6" on the instruction monitor on the main side.

Therefore, in the pachi-slot machine 1 of the present embodiment, the information related to the stop operation of the stop button is notified on the sub side as well as the notification on the main side. Specifically, the display device 11 (projector mechanism 211 and display unit 212) controlled on the sub side is used to notify the information related to the stop operation under the control of the sub side.

For example, when notifying the push order in which the first stop operation is performed on the left reel 3L, the numerical value "1" is displayed on the instruction monitor on the main side, and the left reel in the display screen of the display device 11 is displayed on the sub side. A numerical value "1" is displayed above the 3L to notify that the left reel 3L is the target of the first stop operation. Further, when notifying the push order "middle, left, right", the numerical value "6" is displayed on the instruction monitor on the main side, and the numerical value is displayed above the middle reel 3C in the display screen of the display device 11 on the sub side. "1" is displayed, the numerical value "2" is displayed above the left reel 3L, and the numerical value "3" is displayed above the right reel 3R. Notify that Further, when the internal winning combination "F_BB1" is determined, the numerical value "10" is displayed on the instruction monitor on the main side, and "white 7"-"white 7" is displayed on the display screen of the display device 11 on the sub side. -Displays information about the symbol combination of "White 7" and informs the player of the symbol to be aimed at.

The timing of notification on the main side can be set to any timing as long as it is at least the period of one game in which notification is performed. For example, the main side may be notified at the timing when the player's start operation is detected (accepted), the main side may be notified at the start of reel rotation, and the first stop operation to the third stop operation may be performed. The main side may be notified at the timing when any of the stop operations is detected. On the other hand, the timing of performing the notification on the sub side is preferably at least a timing before the first stop operation. Therefore, in the pachi-slot machine 1 of the present embodiment, notification (navigation) is performed on both the main side and the sub side at the timing when the start operation is detected or the timing when the rotation of the reel starts. As a result, before the player performs the stop operation, the stop operation information is notified on both the instruction monitor on the main side and the display device 11 on the sub side.

In the ART preparation state, as shown in FIG. 63A, notifications (navigation) called "bell navigation", "maintenance lip navigation", "RT3 transition lip navigation" and "RT4 transition lip navigation" are performed by the control of the main side. In "Bell Navi", when the internal winning combination "F_3 choice bell_1st" to "F_3 choice bell_3rd" is decided, the symbol combination (see FIG. 29) related to the abbreviation "bell" is stopped and displayed on the effective line. The push order of is notified. In "Maintenance Lip Navi", when the internal winning combination "F_Maintenance Lip_1st" to "F_Maintenance Lip_3rd" is determined, the symbol combination (see FIG. 28) related to the abbreviation "Replay" is stopped and displayed on the effective line. The push order for is notified. In the "RT3 transition lip navigation", when the internal winning combinations "F_RT3 transition lip_1st" to "F_RT3 transition lip_3rd" are determined, the symbol combination (see FIG. 28) related to the abbreviation "RT3 transition lip" is placed on the effective line. The push order for displaying the stop is notified. Further, in the "RT4 transition lip navigation", when the internal winning combinations "F_RT4 transition lip_123" to "F_RT4 transition lip_3rd" are determined, the symbol combination (see FIG. 28) related to the abbreviation "RT4 transition lip" is effective. The push order for displaying the stop display on the top is notified.

Further, in the ART gaming state (normal ART or CT), as shown in FIG. 63B, the notifications referred to as "Bell Navi", "Maintenance Lip Navi", "RT3 Transition Lip Navi" and "RT4 Transition Lip Navi" are controlled by the main side. (Navigation) is performed. In the game in the ART game state (RT4 state), a flag conversion lottery is performed, and based on the lottery result, a symbol combination related to the abbreviations "triple chili lip", "reach eye lip" or "replay" is displayed. The push order is notified, but this notification is performed only on the sub side, not on the main side.

As mentioned above, since the symbol combination related to the abbreviation "triple chili lip" or "reach eye lip" is related to the granting of special benefits, the presence or absence of notification affects the player's profit (ball output). Although it seems to be given, in reality, in the pachislot machine 1 of the present embodiment, the special privilege is given based on the lottery result of the flag conversion lottery, so that the displayed symbol combination is the given privilege. It does not affect it. Therefore, for example, in the state of winning the flag conversion lottery, even if the symbol combination related to the abbreviation "replay" is stopped and displayed, a special privilege is given. On the other hand, even if the symbol combination related to the abbreviation "triple chili lip" or "reach eye lip" can be stopped and displayed in the state where the flag conversion lottery is not won, no special privilege is given. In the pachislot machine 1 of the present embodiment, when the symbol combination displayed in this way does not affect the profit (ball output) of the player, it is controlled on the sub side without notifying the instruction monitor on the main side. The notification is performed only on the display device 11.

Further, in the RT5 state (inter-flag state), as shown in FIGS. 63C and 63D, information is notified to the player to aim at the symbol combination related to the bonus combination carried over as the internal winning combination. For example, when the internal winning combination "F_BB1" is carried over, as shown in FIG. 63C, a notification (navigation) called "white 7 navigation" is performed by the control of the main side, and the internal winning combination "F_BB2" is performed. "Is carried over, as shown in FIG. 63D, a notification (navigation) called" blue 7 navigation "is performed by the control of the main side.

In "White 7 Navi", the symbol combination corresponding to the internal winning combination "F_BB1", that is, the symbol combination related to the combination name "C_BB1" ("White 7"-"White 7"-"White 7": see FIG. 28). Information on the stop operation for displaying the stop on the valid line is notified. Further, in "Blue 7 Navi", the symbol combination corresponding to the internal winning combination "F_BB2", that is, the symbol combination related to the combination name "C_BB2" ("Blue 7"-"Blue 7"-"Blue 7": FIG. 28 Information on the stop operation for displaying the stop display on the valid line (see) is notified.

In the inter-flag state, when the bonus combination and any of the internal winning combinations "off", "F_special 1", "F_special 2" and "F_special 3" are determined, as described in FIG. 24. , The symbol combination related to the bonus combination (BB combination) can be stopped and displayed on the effective line. However, if the internal winning combination other than the internal winning combination "missing", "F_special 1", "F_special 2" and "F_special 3" and the bonus combination are winning, the symbol combination related to the bonus combination Cannot be stopped and displayed on the valid line. Therefore, in the present embodiment, as shown in FIGS. 63C and 63D, the carried-over bonus combination and the internal winning combination “missing”, “F_special role 1”, “F_special role 2” and “F_special role” Only when any of "3" is the winning, the notification called "white 7 navigation" or "blue 7 navigation" is performed by the control of the main side. Therefore, in the present embodiment, the notification (navigation) called "white 7 navigation" or "blue 7 navigation" controlled by the main side can be performed at an appropriate timing in which the bonus combination can be won.

The pachi-slot machine 1 of the present embodiment is also provided with a function of notifying a bonus by displaying a bonus confirmation screen or turning on a bonus confirmation lamp, for example. Therefore, on the main side, the navigation called "white 7 navigation" or "blue 7 navigation" may be performed only after announcing (bonus notification) that the bonus combination has been determined as the internal winning combination.

As a bonus notification, for example, an effect that is performed over a plurality of game periods (so-called continuous effect) is generally performed, and a bonus confirmation screen is displayed according to the result of this continuous effect. There is. If "White 7 Navi" or the like is performed on the main side during such a continuous production, the result of the continuous production will be known in the middle, which may spoil the interest. Therefore, in the present embodiment, after the bonus notification is made, the main control board 71 is notified (navigation) called "white 7 navigation" or "blue 7 navigation" by the control of the main side.

The method of making it possible for the main side to grasp the timing of the bonus announcement is arbitrary. As one of the methods, when the bonus combination is determined as the internal winning combination, the main control board 71 determines the number of games required until the end of the bonus notification, and after digesting the games of this number of games, "White 7 Navi" or A method of performing notification (navigation) called "blue 7 navigation" can be considered. More specifically, when the main control board 71 determines the number of games required until the end of the bonus notification, the main control board 71 notifies the sub control board 72 of the number of games. The sub-control board 72 controls the production according to the number of games, and displays the bonus confirmation screen at the timing when the games of the number of games are exhausted, so that the timing when the bonus notification is made on the main side can be grasped. Can be done. That is, the main control board 71 counts the number of unit games since the bonus combination is determined as the internal winning combination in a state where the bonus combination has not been carried over, and after the counting result reaches a predetermined number of times, the bonus combination And, when any of the internal winning combination "missing", "F_special role 1", "F_special role 2" and "F_special role 3" is determined as the internal winning combination, "white 7 navigation" or "white 7 navigation" or " Perform "Blue 7 Navi".

Further, as another method, a method of controlling the bonus notification on the main side instead of the sub side can be considered. More specifically, when the main control board 71 determines the bonus combination as the internal winning combination in the state where the bonus combination is not carried over, the main control board 71 determines the effect (at least the number of games required for the effect) to be executed by the display device 11. Notify the sub-control board 72. By executing the effect notified by the sub-control board 72 and displaying the bonus confirmation screen, it is possible to grasp the timing at which the bonus notification is made on the main side.

It should be noted that the main side may be configured to be able to grasp the timing at which the bonus notification is made by a method other than the above two methods. In this case, since the main control board 71 cannot receive the signal from the sub control board 72 or the like, it is necessary to grasp the timing at which the bonus notification is made based on the signal that the main control board 71 can accept. For example, since the main control board 71 can accept the signal associated with the stop operation, when a predetermined stop operation (for example, other than forward pressing) is performed while the bonus combination is determined as the internal winning combination. In addition, a method of notifying a bonus is also conceivable. Specifically, the sub-control board 72 acquires information on the internal winning combination and information on the stop operation from the main control board 71, and gives a bonus notification when the combination of these information is a predetermined combination. By adopting such a bonus notification method, the trigger of the bonus notification can also be grasped by the main control board 71, so that the timing at which the bonus notification is made can be grasped on the main side.

<Explanation of operation of main control circuit>
Next, with reference to FIGS. 64 to 181, the contents of various processes executed by the main CPU 101 of the main control circuit 90 by using the program will be described.

[Processing when power is turned on (reset interrupt)]
First, the power-on (reset interrupt) processing of the pachi-slot machine 1 performed under the control of the main CPU 101 will be described with reference to FIGS. 64 and 65. FIG. 64 is a flowchart showing the procedure at the time of power-on (reset interrupt), and FIGS. 65A to 65C are sources for executing the processes of S2, S7, S8, and S13 in the flowchart, respectively. It is a figure which shows an example of a program. In the power-on (reset interrupt) processing shown in FIG. 64, when the power management circuit 93 detects that the supply of the power supply voltage to the microprocessor 91 has started, the reset signal is sent to the microprocessor 91. It is output to the "XSRST" terminal, and is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

First, the main CPU 101 determines whether or not the power supply monitoring port (power supply monitoring means) is in the ON state (S1).

In S1, when the main CPU 101 determines that the power supply monitoring port is in the ON state (when the determination in S1 is YES), the main CPU 101 repeats the process of S1. The state in which the power supply monitoring port is on is a state in which the power supply voltage (DC + 5V) supplied to the main CPU 101 is not stable.

On the other hand, when the main CPU 101 determines in S1 that the power supply monitoring port is not in the ON state (when the determination in S1 is NO), the main CPU 101 performs an initialization process of the timer circuit 113 (PTC) (S2). In this process, the main CPU 101 initially sets the timer circuit 113. Specifically, the main CPU 101 sets the frequency division ratio in the timer prescaler register (not shown), sets the timer control register (not shown) to interrupt enable, etc., and sets the timer counter (not shown). Set the initial count value.

Next, the main CPU 101 performs initialization processing of the first serial communication circuit 114 (SCU1) between the main control circuit 90 and the sub-control circuit 200, and the second serial communication circuit 115 (SCU2) for the second interface board. Initialization processing is performed (S3). Next, the main CPU 101 performs initialization processing of the random number circuit 110 (RDG) (S4). Next, the main CPU 101 performs a write test of the main RAM 103 (S5).

Next, the main CPU 101 determines whether or not the writing to the main RAM 103 has been normally performed as a result of the writing test (S6).

In S6, when the main CPU 101 determines that the writing to the main RAM 103 has not been performed normally (when the determination in S6 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, in S6, when the main CPU 101 determines that the writing to the main RAM 103 has been normally performed (when the determination in S6 is YES), the main CPU 101 is in the state of the timer control register (not shown) of the timer circuit 113. (S7).

Next, the main CPU 101 determines whether or not the current state is the occurrence timing of the interrupt process based on the acquired state of the timer control register (S8). Specifically, the main CPU 101 determines whether or not 1.1172 ms has elapsed from the start of the timer count based on the acquired state of the timer control register.

In the present embodiment, when the timer time 1.1172 ms is set by the initialization process of the timer circuit 113 in S2, the count process of the CPU built-in timer is started. After that, the status of the timer circuit 113 can be acquired by reading the information of the timer control register (not shown). Then, in the present embodiment, a bit (discrimination bit) capable of discriminating (seeing) whether or not the current state is the occurrence timing of the interrupt process (whether or not it is the timer interrupt state) in the timer control register. ) Is provided.

Therefore, in the process of S7, the main CPU 101 reads the information of the timer control register (not shown), and in the process of S8, the main CPU 101 is in the ON / OFF state of the discrimination bit in the timer control register (not shown). By referring to "1" / "0"), it is determined whether or not the current state is the timing at which the interrupt process occurs. When 1.1172 ms has elapsed from the start of counting by the timer circuit 113 (if the count value of the timer circuit 113 is 0), the discrimination bit is turned on.

In S8, when the main CPU 101 determines that the current state is not the timing at which the interrupt process occurs (when the determination in S8 is NO), the main CPU 101 returns the process to the process of S7 and repeats the processes after S7.

On the other hand, in S8, when the main CPU 101 determines that the current state is the occurrence timing of the interrupt process (when the determination in S8 is YES), the main CPU 101 performs a thumb check process (non-standard) (S9). .. In this process, the main CPU 101 performs a thumb check process of the main RAM 103, and this process is performed in an unspecified work area (see FIG. 12C) in the main RAM 103. Further, the program used in this thumb check process is stored in the non-standard area in the main ROM 102 (see FIG. 12B). The details of the thumb check process will be described later with reference to FIGS. 79 and 80 described later.

Further, in S8, when the main CPU 101 determines that the current state is the occurrence timing of the interrupt process (when the determination in S8 is YES), the main CPU 101 performs the interrupt process described later before the process in S9. The interrupt process (see FIG. 167 described later) is executed. Then, by this interrupt process, a no-operation command is transmitted from the main control circuit 90 (main control board 71) to the sub control circuit 200 (sub control board 72).

After the process of S9, the main CPU 101 determines whether or not the setting key type switch 54 is in the ON state (S10).

In S10, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (when the determination in S10 is YES), the main CPU 101 performs the process of S15 described later. On the other hand, in S10, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (when the determination in S10 is NO), the main CPU 101 determines the thumb check based on the result of the thumb check process in S9. It is determined whether or not the result is normal (S11).

In S11, when the main CPU 101 determines that the thumb check determination result is not normal (when the determination in S11 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, in S11, when the main CPU 101 determines that the thumb check determination result is normal (when the determination in S11 is YES), the main CPU 101 performs the game return process (S12). In this process, the main CPU 101 performs a process of returning the game state to the state before the power failure detection. The details of the game return process will be described later with reference to FIG. 66 described later.

When the determination in S6 or S11 is NO, the main CPU 101 displays the character string "rr" indicating the occurrence of an error on the information display 6 (7-segment LED display) (S13). After that, the main CPU 101 repeats the WDT clearing process (S14).

Here, returning to the process of S10 again, if S10 is a YES determination, the main CPU 101 performs a setting change confirmation process (S15). In this process, the main CPU 101 mainly performs a setting change command generation / storage process at the start of the setting change. The details of the setting change confirmation process will be described later with reference to FIG. 68 described later.

Next, the main CPU 101 performs a RAM initialization process (S16). In this process, the main CPU 101 sets the address "at the time of RAM abnormality or at the start of setting change" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game starts from the start address. Erase (clear) the information up to the final address of the RAM area for use. Then, after the processing of S16, the main CPU 101 starts the main processing described later (see FIG. 82 described later).

In the present embodiment, the power-on (reset interrupt) processing is performed as described above. Then, the processing of S2 during the power-on (reset interrupt) processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 65A.

In the source program of FIG. 65A, 10 MHz (supply clock is 20 MHz) is set as the CPU clock, 228 is set as the prescaler register set value, and 49 is set as the initial count value. As a result, 1.1172 ms (= 1 / (10 MHz / 288) × 49) is calculated as the timer time (execution cycle) of the interrupt process.

Further, the processes of S7 and S8 during the above-mentioned power-on (reset interrupt) process are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 65B. Specifically, the process of acquiring the state of the timer control register in S7 is executed by the "LD" instruction in FIG. 65B, and the determination process in S8 is executed by the "JBIT" instruction in FIG. 65B. Then, the "LD" command in FIG. 65B and the "JBIT" command in FIG. 65B are repeatedly executed until 1.1172 ms elapses from the start of counting by the timer circuit 113, and 1.1172 ms elapses from the start of counting by the timer circuit 113. , The interrupt request signal is output from the timer circuit 113 to the main CPU 101 via the interrupt controller 112. The main CPU 101, triggered by the input of this interrupt request signal, starts the interrupt process having the first 1.1172 ms cycle after the power is restored.

Since the command related to the game operation is not set in the first 1.1172 ms cycle interrupt process immediately after the power is restored (after the initialization when the power is turned on), the main control circuit 90 to the sub control circuit 200 No operation command is sent. By permitting the interrupt process immediately after the power is restored in this way, the no-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

Further, the data stored in the L register, the H register, the E register, the D register, and the C register are set in the communication parameters 1 to 5 constituting the non-operation command transmitted in this communication operation, respectively, when the power is restored. Will be done. Therefore, in the present embodiment, the data set in the communication parameters 1 to 5 of the non-operation command transmitted in the first interrupt process after the power is restored is made different (undefined) each time the power is restored. Can be done. That is, the sum value (BCC) of the non-operation command transmitted in the interrupt process immediately after the power is restored (after the initialization when the power is turned on) can be made different for each power restoration. In this case, fraudulent acts such as goto can be suppressed.

Further, the processing (interrupt prohibition processing) of S13 during the power-on (reset interrupt) processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 65C. .. Then, control when displaying the error code "rr" on the 2-digit 7-segment LED in the information display 6 is executed by one source code "LDW HL, 100H * cZCHRAR + cBX_PAYSEG" as shown in FIG. 65C. Then, the output operation of the 7-segment common output data and the output operation of the 7-segment cathode output data to the 2-digit 7-segment LED are performed at the same time.

That is, in the pachi-slot machine 1 of the present embodiment, the 7-segment common output data and the 7-segment cathode output data are output at the same time when the 2-digit 7-segment LED is dynamically lit and controlled. In this case, the number of instruction codes required for the dynamic lighting control of the 7-segment LED on the source program can be reduced, and the capacity of the source program (capacity used by the main ROM 102) can be reduced. Therefore, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

The "7-segment common output data" referred to here is LED drive data output to the common (common) terminal of the 7-segment LED when the 7-segment LED is dynamically controlled, and the "7-segment cathode output data" is , This is LED drive data output to each cathode terminal of the 7-segment LED when the 7-segment LED is dynamically lit and controlled.

[Game return processing]
Next, with reference to FIGS. 66 and 67, the game return process performed in S12 during the power-on (reset interrupt) process (see FIG. 64) will be described. Note that FIG. 66 is a flowchart showing the procedure of the game return process, and FIG. 67 is a diagram showing an example of a source program for executing the processes of S25 to S32 in the flowchart.

First, the main CPU 101 sets the stack pointer (SP) at the time of power failure (S21). Next, the main CPU 101 clears (offs) the on-edge data before the 10-interrupt processing of the input port and the currently set on-edge data (S22). Next, the main CPU 101 sets the backup data of the output port in the output port (S23). Next, the main CPU 101 reads the data of the input port and saves the data in the current data storage area of the input port and before the interrupt processing (S24).

Next, the main CPU 101 sets the address of the rotating cylinder control data storage area (S25). Next, the main CPU 101 sets the number of reels to be checked (“3” in this embodiment) (S26).

Next, the main CPU 101 acquires reel control management information (data related to fluctuation control of the display column when a power failure occurs) of a predetermined reel based on the address of the set rotation cylinder control data storage area (S27). The reel control management information (variation control management information in the display column) is information related to the control state (rotation status) of each reel, and is backed up and saved in the event of a power failure.

Next, the main CPU 101 determines whether or not the reel control management information is information corresponding to the rotation status during reel acceleration, constant speed waiting, or constant speed (S28).

When the main CPU 101 determines in S28 that the condition of S28 is not satisfied (when the determination in S28 is NO), the main CPU 101 performs the process of S31 described later. On the other hand, in S28, when the main CPU 101 determines that the condition of S28 is satisfied (YES in S28), the main CPU 101 clears the spinning control data (reel control management information) (S29). By this process, after returning to the game, the rotation control of the reel is started from the acceleration process. Next, the main CPU 101 sets the reel operation timing value (execution start timing “1” of the rotation cylinder control data) (S30). When "1" is set for the reel operation timing, the excitation change timing is set in the reel control process (see S903 in FIG. 167 described later), so that the main CPU 101 accelerates the reel rotation control. Start from.

After the processing of S30 or when the determination in S28 is NO, the main CPU 101 subtracts 1 from the value of the number of reels (S31). Next, the main CPU 101 determines whether or not the value of the number of reels after subtraction is "0" (S32).

In S32, when the main CPU 101 determines that the value of the number of reels after subtraction is not "0" (when the determination in S32 is NO), the main CPU 101 changes the reel to be checked and shifts the processing to the processing of S27. Return and repeat the processing after S27.

On the other hand, in S32, when the main CPU 101 determines that the value of the number of reels after subtraction is "0" (when the determination in S32 is YES), the main CPU 101 performs the RAM initialization process (S33). In this process, the main CPU 101 sets the address "at the time of power recovery" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the final address of the game RAM area is set from the start address. Delete (clear) the information up to the address.

Next, the main CPU 101 restores the data of all the registers saved at the time of power failure detection to all the registers (S34). Then, after the process of S34, the main CPU 101 ends the game return process and returns the process to the process at the time of power failure detection.

In the present embodiment, the game return process is performed as described above. In the game return processing of the present embodiment, as described above, the input / output state of each port at the time of power failure is secured at the time of power recovery, and when the reel is rotating at the time of power failure, reel control management is performed at power recovery. The processing necessary for starting the re-rotation of the reel by acquiring the information is also performed (see the processing of S25 to S32). Therefore, in the present embodiment, the reel re-rotation control can be stably performed even when the reel is recovered from the electric power failure during the rotation of the reel, and the player is not uncomfortable.

Further, the processes S25 to S32 during the game return process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 67. As described above, the microprocessor 91 with a security function for a game machine used in the pachislot machine 1 of the present embodiment is provided with various instruction codes dedicated to the main CPU 101. For example, the "LDQ" instruction (predetermined read instruction) in FIG. 67 is one of the main CPU 101 dedicated instruction codes.

For example, when the source code "LDQ HL, k" is executed on the source program, the address specified by the contents of the Q register (stored data) and the 1-byte integer k (direct value) becomes the HL register. Loaded into. At this time, the content of the Q register becomes the address value on the upper side of the designated destination address, and the integer k (direct value) becomes the address value on the lower side of the designated destination address. Therefore, when the source code "LDQ HL, .LOW.wR1_CTRL" in FIG. 67 is executed, the contents of the Q register (the address value on the upper side of the address of the rotation control data storage area) and the integer value ". The address (address of the rotating cylinder control data storage area) specified by "LOW.wR1_CTRL" (address value on the lower side of the address of the rotating cylinder control data storage area) is loaded into the HL register. Note that ".LOW." Is not an actual instruction but a pseudo instruction. In this pseudo-instruction function, only the lower address of the address of the storage area specified after ".LOW." Is enabled. Further, the pseudo instruction is not an instruction stored in the actual ROM, but an instruction for the conversion program (assembler) to refer to when converting the source file into a format for storing in the ROM.

As described above, in the present embodiment, by using the instruction code dedicated to the main CPU 101 that specifies the address using the Q register (extension register), the main ROM 102, the main RAM 103, and the memory map I / O can be set by the direct value. Can be accessed. In this case, the instruction code related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Setting change confirmation process]
Next, the setting change confirmation process performed in S15 during the power-on (reset interrupt) process (see FIG. 64) will be described with reference to FIGS. 68 and 69. Note that FIG. 68 is a flowchart showing the procedure of the setting change confirmation process, FIG. 69A is a diagram showing an example of a source program for executing the processes of S44 to S47 in the flowchart, and FIG. 69B is a diagram showing an example of the source program. It is a figure which shows an example of the source program for executing the process of S57 in the flowchart.

First, the main CPU 101 performs an initialization process of an unspecified RAM area in the main RAM 103 (S41). Next, the main CPU 101 performs one interrupt wait process (S42). In this process, the main CPU 101 waits until the process of transmitting the non-operation command to the sub-control circuit 200 by the interrupt process is completed.

Next, the main CPU 101 performs a RAM initialization process (S43). In this process, the main CPU 101 sets the address "at the time of RAM abnormality or at the start of setting change" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game starts from the start address. Erase (clear) the information up to the final address of the RAM area for use.

Next, the main CPU 101 determines whether or not the setting key type switch 54 is in the ON state (S44). The setting key (not shown) inserted into the setting key type switch 54 is an operation key for operating the setting (settings 1 to 6) of the pachislot machine 1, and when the setting key is turned on, it is for setting. The key type switch 54 is turned on.

In S44, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (when the determination in S44 is NO), the main CPU 101 ends the setting change confirmation process and turns on the power (reset interrupt). ) Move to the processing of S16 of the time processing (see FIG. 64). On the other hand, in S44, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (when the determination in S44 is YES), the main CPU 101 performs a medal acceptance prohibition process (S45). By this process, the solenoid of the selector 66 (see FIG. 7) is not driven, and the inserted medals are ejected from the medal payout outlet 24 (see FIG. 2).

Next, the main CPU 101 sets the setting change start or setting confirmation start information (005H: first value) in the L register, and performs the generation and storage process of the setting change command (setting change / setting confirmation start) (S46). .. In this process, the main CPU 101 generates setting change command data (first command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the start of the setting change process or the setting confirmation process, and generates the command data. It is stored in the communication data storage area provided in the main RAM 103. The details of the setting change command generation and storage process will be described later with reference to FIG. 70 described later. Further, the setting change command (setting change / setting confirmation start) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 167. Will be sent to.

Next, the main CPU 101 sets the error count relay to the ON state (S47). Next, the main CPU 101 determines whether the setting change or the setting confirmation has been performed (S48).

In S48, when the main CPU 101 determines that the setting has not been changed (the setting has been confirmed) (when the determination in S48 is NO), the main CPU 101 performs the process of S55 described later.

On the other hand, in S48, when the main CPU 101 determines that the setting has been changed (the setting has not been confirmed) (when the determination in S48 is YES), the main CPU 101 updates the set value (S49). ). Next, the main CPU 101 performs a 7-segment display setting process of the set value (S50). By this process, the updated set value can be displayed on the 7-segment LED in the information display 6.

Next, the main CPU 101 determines whether or not the reset switch 76 is in the ON state (S51).

When the main CPU 101 determines in S51 that the reset switch 76 is in the ON state (when the determination in S51 is YES), the main CPU 101 returns the process to the process of S49 and repeats the processes after S49. On the other hand, in S51, when the main CPU 101 determines that the reset switch 76 is not in the ON state (when the determination in S51 is NO), the main CPU 101 determines whether or not the start switch 79 is in the ON state (S52). ..

When the main CPU 101 determines in S52 that the start switch 79 is not in the ON state (when the determination in S52 is NO), the main CPU 101 returns the process to the process in S51 and repeats the processes after S51. On the other hand, in S52, when the main CPU 101 determines that the start switch 79 is in the ON state (when the determination in S52 is YES), the main CPU 101 is set in the set value storage area (not shown) provided in the main RAM 103. Store the value (S53).

Next, the main CPU 101 determines whether or not the setting key type switch 54 is in the off state (S54).

In S54, when the main CPU 101 determines that the setting key type switch 54 is not in the off state (when the determination in S54 is NO), the main CPU 101 repeats the process of S54. On the other hand, in S54, when the main CPU 101 determines that the setting key type switch 54 is in the off state (when the determination in S54 is YES), the main CPU 101 performs the process of S55 described later.

When the determination in S48 is NO or the determination in S54 is YES, the main CPU 101 determines whether the setting change or the setting confirmation has been performed (S55).

In S55, when the main CPU 101 determines that the setting has not been changed (the setting has been confirmed) (when the determination in S55 is NO), the main CPU 101 performs the process of S57 described later. On the other hand, in S55, when the main CPU 101 determines that the setting has been changed (the setting has not been confirmed) (when the determination in S55 is YES), the main CPU 101 performs the RAM initialization process (S56). .. In this process, the main CPU 101 uses the address (the address next to the setting value storage area) in the gaming RAM area of the main RAM 103 shown in FIG. 12C, which is not shown, at the end of the setting change as the start address of the initialization start. It is set and the information from the start address to the final address of the game RAM area is erased (cleared).

After processing S56 or when S55 determines NO, the main CPU 101 sets the setting change end or setting confirmation end information (004H: second value) in the L register, and sets the setting change command (setting change / setting confirmation end). ) Is generated and stored (S57). In this process, the main CPU 101 generates setting change command data (second command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the end of the setting change process or the setting confirmation process, and generates the command data. It is stored in the communication data storage area provided in the main RAM 103. The details of the setting change command generation and storage process will be described later with reference to FIG. 70 described later. Further, the setting change command (setting change / setting confirmation end) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 167. Will be sent to. Then, after the processing of S57, the main CPU 101 ends the setting change confirmation processing, and shifts the processing to the processing of S16 of the power-on (reset interrupt) processing (see FIG. 64).

In the present embodiment, the setting change confirmation process is performed as described above. The processes S44 to S47 during the above-mentioned setting change confirmation process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 69A. Among them, for example, the state determination process of the setting key of S44 is executed by the source code "BITQ 7, (.LOW. (WIBUF + 4))" in FIG. 69A, and the error count relay of S47 is set to the ON state. The process is executed by the source code "SETQ 1, (.LOW.wECRRQ)" in FIG. 69A.

Both the "BITQ" instruction and the "SETQ" instruction are instruction codes dedicated to the main CPU 101 that specify an address using a Q register (extension register).

When, for example, the source code "BITQ b, (k)" is executed on the source program, the stored data (upper address value) of the Q register and the 1-byte integer value k (direct value: lower address value) are executed. If bit b of the memory at the address specified by) is checked and "1" is stored in the bit b, "0" is set in the zero flag (bit 6: see FIG. 11) of the flag register F. If "0" is stored in the bit b, "1" is set in the zero flag (predetermined bit area) of the flag register F. Therefore, when the source code "BITQ 7, (.LOW. (WIBUF + 4)" in FIG. 69A is executed, the stored data of the Q register and the address specified by the integer value ".LOW. (WIBUF + 4)" If bit 7 of the memory is checked and "1" is stored in the bit 7, "0" is set in the zero flag of the flag register F, and if "0" is stored in the bit 7. , "1" is set to the zero flag of the flag register F.

Further, for example, when the source code "SETQ b, (k)" is executed on the source program, the stored data (upper address value) of the Q register and the 1-byte integer value k (direct value: lower side) are executed. "1" is set in the memory bit b of the address specified by (address value). Therefore, when the source code "SETQ 1, (.LOW.wECRRQ)" in FIG. 69A is executed, the stored data of the Q register and the memory of the address specified by the integer value ".LOW.wECRRQ" are stored. Bit 1 is set to "1".

That is, in the setting change confirmation process of the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extension register) as described above are used, and the direct value is obtained by using these main CPU 101 dedicated instruction codes. Then, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed. In this case, the instruction code related to the address setting can be omitted, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space of the main ROM 102 can be increased, and the processing speed can be increased.

Further, the generation / storage process of the setting change command (initialization command) performed at the start of the setting change / setting confirmation of S46 during the setting change confirmation process described above is performed by the main CPU 101 executing the "CALLF" command in FIG. 69A. The generation / storage process of the setting change command (initialization command) performed at the end of the setting change / setting confirmation of S57 described above is performed by the main CPU 101 executing the "CALLF" command in FIG. 69B. The "CALLF" instruction is also an instruction code dedicated to the main CPU 101.

For example, when the source code "CALLF mn" is executed on the source program, the value (stored data) of the current PC register (program counter PC: see FIG. 11) is specified by the stack pointer (SP). It is saved in the memory, the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address specified by "mn". However, the "CALLF" instruction is a 2-byte instruction, and the jumpable address range is in the range of 0000H to 11FFH. Therefore, for example, when the source code "CALLF SB_PCIIT_00" in FIG. 69A is executed, the current value of the PC register is saved in the memory specified by the stack pointer (SP), and the stack pointer is updated by -2. , The address of "SB_PCIIT_00" is stored in the PC register, and the process jumps to the address specified by "SB_PCIIT_00".

In the present embodiment, an instruction code called a "CALL" instruction is also prepared as an instruction code of the same type as the "CALLF" instruction. Then, for example, when the source code "CALL mn" is executed on the source program, the value (stored data) of the current PC register (program counter PC: see FIG. 11) is changed as in the "CALLF" instruction. It is saved in the memory specified by the stack pointer (SP), the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address specified by "mn". However, the "CALL" instruction is a 3-byte instruction, and the jumpable address range is different from that of the "CALLF" instruction, and the jumpable address range is in the range of 0000H to FFFFH. Since the "CALLF" instruction is an instruction code having a smaller number of bytes than the "CALL" instruction, the capacity of the source program (the capacity used by the main ROM 102) can be reduced and the processing efficiency can be improved. be able to.

Further, in the setting change confirmation process of the present embodiment, as shown in FIGS. 69A and 69B, the jump destination address “SB_PCIT_00” specified by the “CALLF” instruction in S46 is the jump destination specified by the “CALLF” instruction in S57. It is the same as the address of. That is, in the present embodiment, the setting change command (initialization command) to be transmitted to the sub-control circuit 200 at the time of setting change (when the game machine is started), at the start of setting confirmation (during normal operation), and at the end of setting confirmation is generated and stored. The source programs for executing the above are the same as each other, and the source programs for the setting change command generation and storage processing used in both the processes of S46 and S57 are shared (modularized).

In this case, in both the processes of S46 and S57, it is not necessary to separately provide the source program for the setting change command generation and storage process, so that the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. .. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Setting change command generation and storage processing]
Next, the setting change command generation / storage process performed in S46 and S57 in the setting change confirmation process (see FIG. 68) will be described with reference to FIGS. 70 and 71. Note that FIG. 70 is a flowchart showing the procedure of the setting change command generation / storage process, and FIG. 71 is a diagram showing an example of a source program for executing the setting change command generation / storage process.

First, the main CPU 101 sets the information of the set values (1 to 6) in the E register (S61). Next, the main CPU 101 sets the RT state information in the C register (S62). Next, the main CPU 101 sets the command type information (02H) of the setting change command in the A register (S63).

Next, the main CPU 101 performs a communication data storage process (S64). In this process, the main CPU 101 has the information set in each register in S61 to S63 and the information set in the D register in S46 or S57 (see FIG. 68) (setting change start / setting change end / setting status). Setting change command data is generated by using (setting confirmation start / setting confirmation end), and the generated command data is saved in the communication data storage area. The details of the communication data storage process will be described later with reference to FIG. 72 described later.

After the process of S64, the main CPU 101 ends the setting change command generation and storage process. When the setting change command generation and storage process performed in S46 during the setting change confirmation process (see FIG. 68) is terminated, the main CPU 101 performs the process after the process of S64 in the setting change confirmation process (see FIG. 68). Move to the process of S47. Further, when ending the setting change command generation and storage process performed in S57 during the setting change confirmation process (see FIG. 68), the main CPU 101 ends the setting change command generation and storage process after the process of S64, and also sets the settings. The change confirmation process (see FIG. 68) is also completed.

In the present embodiment, the setting change command generation / storage process is performed as described above. The above-mentioned setting change command generation / storage process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 71.

As described above, in the setting change command generation and storage process, the setting status is stored in the D register as communication parameter 4 immediately before the setting change command generation and storage process is executed, and the set value is set during the execution of the setting change command generation and storage process. Is stored in the E register as the communication parameter 3, and the RT information is stored in the C register as the communication parameter 5. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), the communication parameters 3 to 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side, and these are used. New information is set in the communication parameters. On the other hand, the other communication parameters 1 and 2 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side, and are for communication parameters 1 and 2. Therefore, the values currently stored in the L register and the H register are set. Therefore, the values of the communication parameters 1 and 2 at the time of transmitting the setting change command (initialization command) are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[Communication data storage process]
Next, with reference to FIGS. 72 and 73, for example, the communication data storage process performed in S64 during the setting change command generation / storage process (see FIG. 70) will be described. The communication data storage process is executed not only when the setting change command is generated but also when other commands are generated. FIG. 72 is a flowchart showing the procedure of the communication data storage process, and FIG. 73 is a diagram showing an example of a source program for executing the processes of S71 to S76 during the communication data storage process.

First, the main CPU 101 stores the data set in the A register as communication command type data in the communication data temporary storage area (not shown) in the main RAM 103 (S71). Next, the main CPU 101 stores the data set in the H register and the L register in the communication data temporary storage area (predetermined storage area) in the main RAM 103 as parameters 1 and 2 of the communication command, respectively (S72). ..

Next, the main CPU 101 stores the data set in the D register and the E register as the parameters 3 and 4 of the communication command in the communication data temporary storage area in the main RAM 103 (S73). Next, the main CPU 101 stores the data set in the B register and the C register as the data of the parameter 5 of the communication command and the RT state, respectively, in the communication data temporary storage area in the main RAM 103 (S74).

Next, the main CPU 101 generates BCC data (sum value) of the communication command from the data values set in the A register to the L register (S75). Next, the main CPU 101 stores the generated BCC data in the communication data temporary storage area in the main RAM 103 (S76).

After the processing of S76, the main CPU 101 determines whether or not there is a free space in the communication data storage area in the main RAM 103 (S77). In this embodiment, a maximum of nine command data can be stored in the communication data storage area (see FIG. 75B described later).

When the main CPU 101 determines in S77 that there is no free space in the communication data storage area (when the determination in S77 is NO), the main CPU 101 ends the communication data storage process and, for example, sets change command generation and storage process (when the communication data storage area is determined to be NO). (See FIG. 70) also ends.

On the other hand, in S77, when the main CPU 101 determines that there is a vacancy in the communication data storage area (when the determination in S77 is YES), the main CPU 101 is stored in the communication data temporary storage area by the above-mentioned processes S71 to S76. The communication data is stored in the communication data storage area as communication command data (S78).

Next, the main CPU 101 performs the communication data pointer update process (S79). In this process, the main CPU 101 mainly updates the communication data pointer indicating the storage address of the communication data in the communication data storage area. The details of the communication data pointer update process will be described later with reference to FIG. 74 described later.

Then, after the process of S79, the main CPU 101 ends the communication data storage process and, for example, the setting change command generation and storage process (see FIG. 70).

In the present embodiment, the communication data storage process is performed as described above. The processes S71 to S76 during the above-mentioned communication data storage process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 73. Then, in this series of processing, the storage processing of the communication command type data, various communication parameters, the game state flag data, and the BCC data included in the command data is as shown in FIG. 73, in the Q register on the source program. It is executed by using the "LDQ" instruction, which is an instruction code dedicated to the main CPU 101 that specifies an address using (extension register).

Specifically, by executing the source code "LDQ (.LOW. (WPDT_TMP + 0)), A", the type data of the communication command stored in the A register becomes 1 with the stored data (upper address value) in the Q register. It is stored in the communication data temporary storage area of the address specified by the integer value ".LOW. (WPDT_TMP + 0)" (lower address value) of the byte. Further, by executing the source code "LDQ (.LOW. (WPDT_TPP + 1)), HL", the communication parameter 1 stored in the L register is changed to the stored data in the Q register and the 1-byte integer value ".LOW. (WPDT_TMP + 1)). The communication parameter 2 stored in the communication data temporary storage area of the address specified by "" and stored in the H register is stored in the communication data temporary storage area of the next address. Further, by executing the source code "LDQ (.LOW. (WPDT_TPP + 3)), DE", the communication parameter 3 stored in the E register is changed to the stored data in the Q register and the 1-byte integer value ".LOW. (WPDT_TPP + 3)". The communication parameter 4 stored in the communication data temporary storage area of the address specified by "" and stored in the D register is stored in the communication data temporary storage area of the next address. Then, by executing the source code "LDQ (.LOW. (WPDT_TPP + 5)), BC", the communication parameter 5 stored in the C register is changed to the stored data in the Q register and the 1-byte integer value ".LOW. (WPDT_TPP + 5)". The game state flag data stored in the communication data temporary storage area of the address specified by "" and stored in the B register is stored in the communication data temporary storage area of the next address.

Further, the BCC data which is the sum value of the command data set in the communication data storage process is calculated by executing a series of source codes "ADD (additional instruction code) A, H" to "ADD A, B", and A. Stored in a register. Then, by executing the source code "LDQ (.LOW. (WPDT_TPP + 7)), A", the BCC data stored in the A register becomes the stored data in the Q register and the 1-byte integer value ".LOW. (WPDT_TPP + 7)". It is stored in the communication data temporary storage area of the address specified in.

As described above, in the present embodiment, when creating one packet (8 bytes) of communication data (command data), various parameters are transferred from the register and stored in the communication data temporary storage area (communication buffer). In such a command data creation method, the data stored in each register at the time of command generation is stored as it is in the communication data temporary storage area as various parameters of the command data. Therefore, when command data including unused parameters is created, the value of the unused parameters becomes an indefinite value each time it is created. In this case, even if there is command data of the same type and the values of the parameters used are the same, the sum value (BCC data) of the command data can be changed each time the command is created. Further, in the present embodiment, the calculation of the sum value, which is one of the error codes, is calculated by ADD (addition instruction code), but instead of the addition instruction code, SUB (subtraction instruction code) and XOR (exclusive OR) are used. The same effect can be obtained even if the error code is calculated by the instruction code). Further, the same effect can be obtained by calculating the error code using the MUL (multiplication instruction code) or DIV (division instruction code), which is an instruction dedicated to the main CPU 101.

Therefore, in the present embodiment, by setting the unused parameter to an indefinite value, it is possible to make it difficult to analyze the communication data and suppress fraudulent acts such as goto, and it is necessary to add unnecessary goto countermeasure processing. Therefore, it is possible to suppress the pressure on the program capacity of the main control circuit 90 due to the addition of the anti-goto processing.

[Communication data pointer update process]
Next, the communication data pointer update process performed in S79 during the communication data storage process (see FIG. 72) will be described with reference to FIGS. 74 and 75. 74 is a flowchart showing the procedure of the communication data pointer update process, FIG. 75A is a diagram showing an example of a source program for executing the communication data pointer update process, and FIG. 75B is a diagram showing an example of a source program for executing the communication data pointer update process. It is a figure which shows the structure of the communication data storage area which is actually set on the source program of an update process.

First, the main CPU 101 acquires the value of the currently set communication data pointer (S81).

Next, the main CPU 101 adds and updates the value of the communication data pointer by one packet (8 bytes) (S82). In this process, when the value of the updated communication data pointer is equal to or larger than the upper limit size of the communication data storage area (see FIG. 75B), the main CPU 101 sets the value of the updated communication data pointer to "0". ", This invalidates all command data stored in the communication data storage area (makes it the same state as the discarded state).

In the present embodiment, the amount of data (1 packet) transmitted in one transmission operation is 8 bytes. That is, in the present embodiment, one command data can be transmitted by one transmission operation. Further, in the present embodiment, since a maximum of 9 command data can be stored in the communication data storage area (see FIG. 75B), the upper limit size of the communication data storage area is 72 bytes (= 8 bytes × 9). .. Therefore, in the present embodiment, the range of the communication data pointer is set to "0" to "71", and in the process of S82, the value of the communication data pointer after the update (when the communication data pointer is updated by +8) is "71 (when the communication data pointer is updated by +8). If the value exceeds "upper limit value)", set the updated communication data pointer value to "0" (return the communication data storage destination address to the start address) and store the communication data. Disable all command data stored in the area (make it the same as the discarded state). If the value of the communication data pointer is set to "0", the next time the command data is stored in the communication data storage area, it is stored from the start address of the communication data storage area, so it is stored before that. The command data will be overwritten with new command data. Therefore, in the present embodiment, it is not necessary to initialize (clear) the communication data storage area when the value of the communication data pointer exceeds "71 (upper limit value)".

Then, after the process of S82, the main CPU 101 ends the communication data pointer update process and also ends the communication data storage process (see FIG. 72).

In the present embodiment, the communication data pointer update process is performed as described above. Then, the communication data pointer update process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 75A. Among them, the update process of the communication data pointer in S82 is executed by the "ADD" instruction and the "ICPLD" instruction (predetermined update instruction) in FIG. 75A, and this "ICPLD" instruction is also dedicated to the main CPU 101. It is an instruction code.

For example, when the source code "ICPLD A, n" is executed on the source program, the contents (stored data) of the A register and the integer n are compared, and when the contents of the A register are less than the integer n, the contents of the A register are compared. , "1" is added to the contents of the A register, and when the contents of the A register are an integer n or more, "0" is set in the A register.

Therefore, when the communication data pointer update process of S82 is executed, the source code "ADD A, 7" is first executed on the source program of FIG. 75A, and the contents of the A register (the communication data pointer before the update) are executed. "7" is added to the value), and the addition result is stored in the A register. Next, the source code "ICPLD A, 71" is executed, the contents of the A register (the value of the communication data pointer after adding 7) are compared with the integer "71", and the contents of the A register are less than the integer "71". If there is, "1" is added to the contents of the A register, and if the contents of the A register are an integer "71" or more, "0" is set in the A register. That is, in the process of S82, when the value of the communication data pointer is updated by +7, if the value of the updated communication data pointer exceeds the upper limit value "71", the process of clearing the communication data pointer to zero (communication). The process of returning the data storage address to the start address of the communication data storage area) is performed. On the other hand, if the updated communication data pointer value does not exceed the upper limit value "71", the communication data pointer value is totaled by adding "1" to the communication data pointer with the "ICPLD" instruction. Update +8.

As described above, in the present embodiment, in the communication data pointer update process, communication data is used by one "ICPLD" instruction code (an instruction code in which the upper limit determination instruction of the transmission buffer and the determination branch instruction are integrated). It is possible to collectively execute the pointer update (1 addition) process, the communication data pointer determination check process after the update, and the communication data pointer clear process. In this case, it is not necessary to provide an instruction code for executing each process separately. For example, the branch instruction code for determining whether or not the updated communication data pointer value exceeds the upper limit value "71" can be omitted.

Therefore, the capacity of the source program (the capacity used by the main ROM 102) can be reduced by using the "ICPLD" instruction code dedicated to the main CPU 101 in the communication data pointer update process or the like. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Processing at the time of power failure (external)]
Next, the power failure (external) processing of the pachi-slot machine 1 performed under the control of the main CPU 101 will be described with reference to FIG. 76. FIG. 76 is a flowchart showing a procedure of (external) processing at the time of power failure. In the power interruption (external) process shown in FIG. 76, when the power supply management circuit 93 detects a decrease in the power supply voltage (power interruption) supplied to the microprocessor 91, the power interruption detection signal is transmitted to the microprocessor 91. Is output to the "XINT" terminal of the above, and is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

First, the main CPU 101 saves the data set in all the registers (S91). Next, the main CPU 101 reads the data set in the power failure detection port (S92).

Next, the main CPU 101 determines whether or not the power failure detection port is in the ON state (S93).

In S93, when the main CPU 101 determines that the power interruption detection port is not in the ON state (when the determination in S93 is NO), the main CPU 101 sets the interrupt processing permission (S94). Then, after the processing of S94, the main CPU 101 ends the (external) processing at the time of power failure. It should be noted that these processes performed when S93 is a NO determination correspond to the process of countermeasures against momentary power failure that occurs when the power management circuit 93 momentarily detects a power failure or the like.

On the other hand, in S93, when the main CPU 101 determines that the power failure detection port is in the ON state (when the determination in S93 is YES), the main CPU 101 sets that the medal cannot be inserted and sets the stop of the hopper device 51. (S95).

Next, the main CPU 101 saves the currently set value of the stack pointer (SP) in the stack area of the game RAM area in the main RAM 103 (S96).

Next, the main CPU 101 performs a checksum generation process of the main RAM 103 (S97). This process is performed in the non-standard work area (see FIG. 12C) in the main RAM 103. Further, the program used in this checksum generation process is stored in the non-standard area in the main ROM 102 (see FIG. 12B). The details of the checksum generation process will be described later with reference to FIG. 77 described later.

Next, the main CPU 101 sets access prohibition to the main RAM 103 (S98). Then, after the processing of S98, the infinite loop processing is performed until the power supply is stopped (until the power supply voltage reaches a voltage at which the main CPU 101 cannot operate).

[Checksum generation process (non-standard)]
Next, the checksum generation process performed in S97 during the power failure (external) process (see FIG. 76) will be described with reference to FIGS. 77 and 78. 77 is a flowchart showing the procedure of the checksum generation process, FIG. 78A is a diagram showing an example of a source program for executing the checksum generation process, and FIG. 78B is a checksum generation process. It is a figure which shows the state of the update operation of the stack pointer and the operation of reading data from a main RAM 103 to a register which are executed.

First, the main CPU 101 saves the current stack pointer (SP) value (the address in use of the stack area of the game RAM area) in the non-standard stack area of the non-standard RAM area of the main RAM 103 (S101). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (S102). Next, the main CPU 101 sets the address value (F0H) on the upper side of the RAM address (address of the non-standard stack area) in the Q register (S103). Next, the main CPU 101 sets the power failure occurrence flag (S104).

Next, the main CPU 101 sets the stack pointer with the calculation start address of the sum value in the game RAM area, and sets the sum calculation counter with the value obtained by dividing the number of bytes of the sum value calculation target storage area by "2". Set (S105). The sum calculation counter is a counter for determining the end trigger of the sum value calculation, and is provided in the main RAM 103. Then, when the sum calculation counter set in S105 becomes "0", the sum value calculation process of the game RAM area of the main RAM 103 is terminated.

Next, the main CPU 101 clears the HL register to 0 (sets the value “0”) (S106). By this process, the initial value "0" of the sum value is set.

Next, the main CPU 101 executes an instruction code (source code "POP DE" shown in FIG. 78A) called an "POP instruction" (specific instruction), and stores the main RAM 103 set in the stack pointer (SP). The data (stored value) of the area for 2 bytes is read from the address of the area to the DE register (S107).

When the "POP" instruction is executed, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the lower register of the pair register and specified by the stack pointer. The data (memory contents) stored in the 1-byte area of the address where the updated address is updated by 1 is loaded into the register on the upper side of the pair register. Further, when the "POP" instruction is executed, an address update process for 2 bytes (a process of adding "2" to the address) is performed on the address set in the stack pointer (SP).

Therefore, in the process of S107, the data (memory contents) stored at the address specified by the stack pointer is loaded into the E register and saved at the address specified by the stack pointer plus "1". The data (memory contents) is loaded into the D register.

FIG. 78B shows a state of reading data to the DE register and updating the address set in the stack pointer when the “POP” instruction is executed. If the address set in the stack pointer (SP) is "F010h" at the start of calculation of the sum value, the data (memory contents) stored in the address "F010h" is loaded into the E register and the address. The data (memory contents) stored in "F011h" is loaded into the D register. Further, at this time, an update process of adding 2 to the address set in the stack pointer (SP) is performed, and the address set in the stack pointer (SP) is changed from "F010h" to "F012h". Then, when the "POP" instruction is executed again, the data (memory contents) stored in the address "F012h" is loaded into the E register, and the data (memory contents) stored in the address "F013h" is loaded. It is loaded into the D register. At this time, the address set in the stack pointer (SP) is updated, and the address set in the stack pointer (SP) is changed from "F012h" to "F014h". After that, every time the "POP" instruction is executed, the above-mentioned operation of reading data to the DE register and the operation of updating the address set in the stack Ponter are repeated.

After the process of S107, the main CPU 101 performs a sum value calculation process (S108). Specifically, the main CPU 101 adds the value stored in the DE register to the value stored in the HL register, and stores the added value as a sum value in the HL register.

Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S109). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S110).

In S110, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S110 is NO), the main CPU 101 returns the process to the process of S107 and repeats the processes after S107. That is, the processes of S107 to S110 are repeated until the sum value calculation process of the game RAM area of the main RAM 103 is completed.

On the other hand, in S110, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S110 is YES), the main CPU 101 sets the DE register in the non-standard RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-standard sum count value is set in the sum calculation counter (S111). The non-standard sum count value is the number of bytes in the non-standard storage area. Therefore, when the sum calculation counter set in S111 becomes "0", the sum value calculation process of the non-standard RAM area of the main RAM 103, that is, the sum value calculation process of the entire main RAM 103 is completed.

Next, the main CPU 101 reads the data (stored value) of one byte from the address of the non-standard RAM area set in the DE register into the A register (S112).

Next, the main CPU 101 performs a sum value calculation process (S113). Specifically, the main CPU 101 adds the value stored in the A register to the value stored in the HL register, and stores the added value as a sum value in the HL register.

Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S114). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S115).

In S115, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S115 is NO), the main CPU 101 returns the processing to the processing in S112 and repeats the processing after S112. That is, the processes of S112 to S115 are repeated until the process of adding the sum value of the non-standard RAM area of the main RAM 103 to the sum value of the game RAM area is completed.

On the other hand, in S115, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S115 is YES), the main CPU 101 sets the value stored in the HL register when a power failure occurs. As the sum value of, it is stored in the sum value storage area (not shown) in the main RAM 103 (S116). Next, the main CPU 101 sets the value of the stack pointer (SP) saved in the non-standard stack area in S101 in the stack pointer (S117). Then, after the processing of S117, the main CPU 101 ends the checksum generation processing, and shifts the processing to the processing of S98 at the time of power failure (external) processing (see FIG. 76).

In the present embodiment, the checksum generation process is performed as described above. Then, the checksum generation process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 78A. As described above, in the present embodiment, the checksum of the main RAM 103 when a power failure occurs is calculated by an addition formula. At this time, in the calculation of the sum value of the game RAM area, addition processing is performed in 2-byte units (see the source code "ADD HL, DE" in FIG. 78A), and in the non-standard RAM area, addition processing is performed in 1-byte units. (See the source code "ADDWB HL, A" in FIG. 78A).

[Sum check processing (non-standard)]
Next, the thumb check process performed in S9 during the power-on processing (see FIG. 64) will be described with reference to FIGS. 79 to 81. 79 and 80 are flowcharts showing the procedure of the thumb check process, and FIG. 81 is a diagram showing an example of a source program for executing the processes of S122 to S132 during the checksum check process.

First, the main CPU 101 saves the current stack pointer (SP) value in the non-standard stack area (S121). Next, the main CPU 101 sets the address of the sum value storage area in the stack pointer, and sets the value obtained by dividing the number of bytes of the sum value calculation target storage area by "2" in the sum calculation counter (S122). The sum calculation counter set here is a counter for determining the end trigger of the sum value calculation (sum value subtraction process), and is provided in the main RAM 103. Next, the main CPU 101 acquires a sum value (checksum) from the sum value storage area (S123). By this process, the checksum (initial value before subtraction) generated when the power failure occurs is stored in the HL register.

Next, the main CPU 101 executes the "POP" instruction and reads the data (stored value) of the area of 2 bytes from the address of the storage area of the main RAM 103 set in the stack pointer (SP) into the DE register (S124). .. At this time, by executing the "POP" instruction, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the E register, and the address specified by the stack pointer is used. The data (memory contents) stored in the 1-byte area of the updated address is loaded into the D register (see FIG. 78B). Further, when the "POP" instruction is executed, an address update process for 2 bytes (a process of adding 2 addresses) is performed on the address set in the stack pointer (SP).

Next, the main CPU 101 performs a sum value calculation (subtraction) process (S125). Specifically, the main CPU 101 subtracts the value stored in the DE register from the value stored in the HL register (initial value of the sum value or the sum value after the previous subtraction process), and the subtraction is performed. Store the value as a sum value in the HL register.

Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S126). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S127).

In S127, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S127 is NO), the main CPU 101 returns the processing to the processing of S124, and repeats the processing after S124. That is, the processes of S124 to S127 are repeated until the subtraction process of the sum value is completed over the entire area of the game RAM area of the main RAM 103.

On the other hand, in S127, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S127 is YES), the main CPU 101 sets the DE register in the non-standard RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-standard sum count value is set in the sum calculation counter (S128). The non-standard sum count value is the number of bytes in the non-standard RAM area.

Next, the main CPU 101 reads the data (stored value) of one byte from the address of the non-standard RAM area set in the DE register into the A register (S129).

Next, the main CPU 101 performs a sum value calculation (subtraction) process (S130). Specifically, the main CPU 101 subtracts the value stored in the A register from the value stored in the HL register, and stores the subtracted value as a sum value in the HL register.

Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S131). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S132).

In S132, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S132 is NO), the main CPU 101 returns the processing to the processing of S129, and repeats the processing after S129. That is, the processes of S129 to S132 are repeated until the subtraction process of the sum value is completed over the entire area of the non-standard RAM area of the main RAM 103.

On the other hand, in S132, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S132 is YES), the main CPU 101 sets "sum error" in the determination result of the thumb check process. (S133). Next, the main CPU 101 determines whether or not the calculated sum value is “0” (S134).

In this process, the main CPU 101 refers to the state (1/0) of the zero flag (bit 6) of the flag register F to determine whether or not the sum value is “0”. In the present embodiment, the sum value becomes "0" when the value of the sum calculation counter set in S128 becomes "0", that is, when the subtraction process of the sum value is completed over the entire area of the main RAM 103. If, the zero flag in the flag register F is set to "1", and if the sum value is not "0", the zero flag in the flag register F is set to "0". Therefore, if "1 (on state)" is set in the zero flag of the flag register F at the time of processing S134, the main CPU 101 determines that the sum value is "0".

In S134, when the main CPU 101 determines that the calculated sum value is not "0" (when the determination in S134 is NO), the main CPU 101 performs the process of S139 described later. On the other hand, in S134, when the main CPU 101 determines that the calculated sum value is "0" (when the determination in S134 is YES), the main CPU 101 sets "power failure" in the determination result (S135). ).

Next, the main CPU 101 acquires the power failure occurrence flag (S136). Next, the main CPU 101 determines whether or not the power failure generation flag is in the state without power failure (off state) (S137).

In S137, when the main CPU 101 determines that the power interruption occurrence flag is in the state of no power interruption (when the determination in S137 is YES), the main CPU 101 performs the process of S139 described later. On the other hand, in S137, when the main CPU 101 determines that the power interruption occurrence flag is not in the state without power interruption (when the determination in S137 is NO), the main CPU 101 sets "normal" in the determination result (S138).

After the processing of S138, if S134 is a NO determination or S137 is a YES determination, the main CPU 101 saves the determination result in the thumb check determination result and clears (offs) the power failure occurrence flag (S139). Next, the main CPU 101 sets the value of the stack pointer (SP) saved in the non-standard stack area in S121 to the stack pointer (S140). Then, after the processing of S140, the main CPU 101 ends the thumb check processing, and shifts the processing to the processing of S10 of the power-on processing (see FIG. 64).

In this embodiment, the sum check process is performed as described above. Then, the processes S122 to S132 during the above-mentioned checksum check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 81.

As described above, in the thumbchock determination process of the main RAM 103 in the present embodiment, first, the value of the checksum generated when the power failure occurs is sequentially subtracted from the data stored in the main RAM 103 when the power is restored. At this time, in the game RAM area, subtraction processing is performed in 2-byte units (see the source code "SUB HL, DE" in FIG. 81), and in the non-standard RAM area, subtraction processing is performed in 1-byte units (in FIG. 81). Source code "SUBWB HL, A") is performed. Next, it is determined whether or not an abnormality has occurred based on whether or not the final subtraction result is "0" (whether or not the zero flag is in the ON state). Then, when the subtraction result is "0" (when the zero flag is in the on state), it is determined to be normal, and when the subtraction result is not "0" (when the zero flag is in the off state), it is regarded as abnormal. It is judged.

That is, in the present embodiment, the checksum generation process when a power failure occurs is performed by an addition method, and the checksum determination process when the power is restored is performed by a subtractive method. Then, normal / abnormal determination is performed based on the final subtraction result of the checksum. When such a checksum generation process and determination process are performed, it is not necessary to generate a checksum again when the power is restored and to collate the checksum with the checksum when a power failure occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, it is possible to secure a free space corresponding to the omitted portion of the collation instruction code in the main ROM 102, and it is possible to improve the game playability by utilizing the increased free space. The "POP" instruction executed in the above-mentioned checksum generation process when a power failure occurs and the checksum determination process when the power is restored is a stack pointer (SP) operation-only instruction, and the source code ". In addition to "POP DE", there are source codes "POP HL", "POP AF" and the like.

[Main processing of pachislot under the control of the main CPU]
Next, with reference to FIG. 82, the main process (main operation process) of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described. Note that FIG. 82 is a flowchart (hereinafter referred to as a main flow) showing the procedure of the main process.

First, the main CPU 101 performs a RAM initialization process (S201). In this process, the main CPU 101 sets the address "at the end of one game" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and from the start address, the game RAM area Delete (clear) the information up to the final address. The storage area in this range is, for example, a storage area in which data needs to be erased for each unit game (game) such as an internal winning combination storage area and a display combination storage area.

Next, the main CPU 101 performs medal acceptance / start check processing (S202). In this process, the main CPU 101 performs an input check process such as a medal sensor (not shown) and a start switch 79. The details of the medal reception / start check process will be described later with reference to FIG. 83 described later.

Next, the main CPU 101 performs a random number acquisition process (S203). In this process, the main CPU 101 uses a random number value for internal winning combination lottery (0 to 65535: a value of the random number register 0 of the random number circuit 110 that becomes a hard latch random number) and a random number value for production used in various ART-related lottery (0 to 65535). 0 to 65535: each value of the random number registers 1 to 3 of the random number circuit 110 to be a soft latch random number, 0 to 255: each value of the random number registers 4 to 7 of the random number circuit 110 to be a soft latch random number), etc. The extracted various random number values are stored in a random number value storage area (not shown) provided in the main RAM 103. The details of the random number acquisition process will be described later with reference to FIG. 91 described later.

Next, the main CPU 101 performs an internal lottery process (S204). In this process, the main CPU 101 performs an internal winning combination determination process by lottery based on the random number value (hard latch random number) extracted in S203. The details of the internal lottery process will be described later with reference to FIG. 93 described later.

Next, the main CPU 101 performs a symbol setting process (S205). In this process, the main CPU 101, for example, generates an internal winning combination from the hit request flag status (flag status information), expands the hit request flag data, and stores the hit request flag data in the hit request flag storage area. And so on. The details of the symbol setting process will be described later with reference to FIG. 98 described later.

Next, the main CPU 101 performs a start command generation / storage process (S206). In this process, the main CPU 101 generates start command data to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. The start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 167. The start command is configured to include parameters (sub-flags, etc.) that specify the internal winning combination and the like.

Next, the main CPU 101 performs the second interface board control process (S207). The second interface board control process is executed in the non-standard work area in the main RAM 103. The details of the second interface board control process will be described later with reference to FIG. 103 described later.

Next, the main CPU 101 performs a state-specific control process (S208). In this process, the main CPU 101 mainly performs a game start process (start process) according to the game state. The details of the state-specific control processing will be described later with reference to FIG. 105 described later.

Next, the main CPU 101 performs a reel stop initial setting process (S209). In this process, the main CPU 101 refers to the reel stop initial setting table (see FIG. 26), and sets the pull-in priority table selection table number, the pull-in priority table number, and the stop table number based on the internal winning combination and the game state. The process of acquiring and the process of storing "3" in the stop button non-operation counter are performed.

Next, the main CPU 101 performs a reel rotation start process (S210). In this process, the main CPU 101 requests the start of rotation of all reels. Then, when the start of rotation of all reels is requested, three stepping motors (not shown) are driven by an interrupt process (see FIG. 167 described later) executed at a constant cycle (1.1172 msec). Controlled, the rotation of the left reel 3L, the middle reel 3C and the right reel 3R is started. Each reel is then accelerated and controlled until its rotational speed reaches a constant speed, after which it is controlled to maintain that constant speed.

Next, the main CPU 101 performs a reel rotation start command generation / storage process (S211). In this process, the main CPU 101 generates data for a reel rotation start command to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. The reel rotation start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 167. The reel rotation start command is configured to include a parameter indicating that the reel rotation start operation has been started.

Next, the main CPU 101 performs a pull-in priority storage process (S212). In this process, the main CPU 101 acquires the attraction priority data and stores it in the attraction priority data storage area. The details of the pull-in priority storage process will be described later with reference to FIG. 127, which will be described later.

Next, the main CPU 101 performs a reel stop control process (S213). In this process, the main CPU 101 controls the rotation of the corresponding reel based on the timing at which the left stop button 17L, the middle stop button 17C, and the right stop button 17R are pressed and the internal winning combination. The details of the reel stop control process will be described later with reference to FIG. 139 described later.

Next, the main CPU 101 performs a winning search process (S214). In this process, the main CPU 101 stores the data in the symbol code storage area (see FIG. 35) in the winning operation flag storage area (see FIGS. 28 to 30). Further, in this process, the main CPU 101 determines whether or not the display combination is displayed on the effective line, and sets the number of medals to be paid out based on the determination result. The details of the winning search process will be described later with reference to FIG. 146, which will be described later.

Next, the main CPU 101 performs an illegal hit check process (S215). In this process, the main CPU 101 synthesizes a hit request flag (internal winning combination) and a winning operation flag (display combination), and determines whether or not there is an illegal hit error based on the combination result. The details of the illegal hit check process will be described later with reference to FIG. 149 described later.

Next, the main CPU 101 performs a winning check / medal payout process (S216). In this process, the main CPU 101 performs a process of generating a winning operation command. Further, in this process, the main CPU 101 drives the hopper device 51 and updates the number of credits based on the number of payouts of the display combination determined in S214, and performs the medal payout process. The details of the winning check / medal payout process will be described later with reference to FIG. 151 described later.

Next, the main CPU 101 performs the combination monitor aggregation process (S217). The combination monitor aggregation process is stored in the non-standard area in the main ROM 102, and the non-standard work area in the main RAM 103 is used as the work area. In this process, the main CPU 101 aggregates various game information, and when a specific ratio calculation condition is satisfied, performs a predetermined ratio calculation and stores the ratio information. The details of the combination monitor aggregation process will be described later with reference to FIG. 155, which will be described later.

Next, the main CPU 101 performs a BB check process (S218). In this process, the main CPU 101 controls the operation and termination of the bonus state. The details of the BB check process will be described later with reference to FIG. 163 described later.

Next, the main CPU 101 performs an RT check process (S219). In this process, the main CPU 101 performs RT state transition control based on the symbol combination stopped and displayed on the effective line. The details of the RT check process will be described later with reference to FIGS. 164 and 165 described later.

Next, the main CPU 101 performs CZ / ART end processing (S220). In this process, the main CPU 101 mainly performs a pullback lottery process for CZ. The details of the processing at the end of CZ / ART will be described later with reference to FIG. 166 described later. Then, after the processing of S219 (after the end of one game), the main CPU 101 returns the processing to the processing of S201.

[Medal reception / start check processing]
Next, the medal acceptance / start check process performed in S202 in the main flow (see FIG. 82) will be described with reference to FIGS. 83 and 84. FIG. 83 is a flowchart showing the procedure of the medal acceptance / start check process, and FIG. 84 is a diagram showing an example of a source program for executing the processes of S232 to S234 during the medal acceptance / start check process. is there.

First, the main CPU 101 determines whether or not the value of the automatic insertion medal counter is "0" (whether or not there is an automatic insertion request) (S221). In this process, when the automatic insertion medal counter is "1" or more, the main CPU 101 determines that there is an automatic insertion request. Further, the automatic insertion medal counter is data for identifying whether or not the display combination related to the replay is established in the previous unit game. When the display combination related to the re-game is established, the number of medals inserted in the previous unit game is automatically inserted into the automatic insertion medal counter.

In S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is "0" (when the determination in S221 is YES), the main CPU 101 performs the process of S225 described later.

On the other hand, in S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is not "0" (when the determination in S221 is NO), the main CPU 101 performs the medal insertion process (S222). In this process, the main CPU 101 performs a medal insertion command generation / storage process, an LED lighting control process for the number of medals inserted, and the like. The details of the medal insertion process will be described later with reference to FIG. 85 described later.

Next, the main CPU 101 subtracts 1 from the value of the automatic insertion medal counter (S223). Next, it is determined whether or not the value of the automatically inserted medal counter after subtraction is "0" (S224).

In S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is not "0" (when the determination in S224 is NO), the main CPU 101 returns the process to the process of S222 and repeats the processes after S222.

On the other hand, in S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is "0" (when S224 is a YES determination), or when S221 is a YES determination, the main CPU 101 is used for medal auxiliary storage. The storage switch check process is performed (S225). In this process, the main CPU 101 detects whether or not the medal auxiliary storage 52 is full of medals based on the on / off state of the medal auxiliary storage switch 75.

Next, the main CPU 101 performs a combination monitor display switching process (S226). The combination monitor display switching process is stored in the non-standard area in the main ROM 102, and the non-standard work area of the main RAM 103 is used as the work area. In this process, the main CPU 101 performs a process of switching the display / non-display of the ratio information on the combination ratio monitor 95 based on whether or not the combination ratio non-display condition described later is satisfied. The details of the combination monitor display switching process will be described later with reference to FIG. 87 described later.

Next, the main CPU 101 performs a medal insertion state check process (S227). Next, the main CPU 101 determines whether or not the medal can be inserted based on the result of the medal insertion state check process (S228).

When the main CPU 101 determines in S228 that the medal cannot be inserted (when the determination in S228 is NO), the main CPU 101 performs the process of S232 described later.

On the other hand, in S228, when the main CPU 101 determines that the medal insertion is possible (when the determination in S228 is YES), the main CPU 101 performs the medal insertion check process (S229). In this process, the main CPU 101 credits the medal, for example, based on the medal sensor input state, a process of determining whether or not the medal has passed normally, and when the number of medals inserted exceeds a specified number. Perform processing and so on. The details of the medal insertion check process will be described later with reference to FIG. 88 described later.

Next, the main CPU 101 determines whether or not the medal insertion or credit is possible based on the result of the medal insertion check process (S230).

When the main CPU 101 determines in S230 that the medal can be inserted or credited (when the determination in S230 is YES), the main CPU 101 performs the process of S232 described later. On the other hand, when the main CPU 101 determines in S230 that the medal cannot be inserted or credited (when the determination in S230 is NO), the main CPU 101 performs a medal acceptance prohibition process (S231). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medals are ejected from the medal payout outlet 24.

After the processing of S231, if S228 is a NO determination or S230 is a YES determination, the main CPU 101 determines whether or not the current number of inserted medals is the playable start number (S232). In this embodiment, the number of games that can be started is three (see FIGS. 28 to 30).

In S232, when the main CPU 101 determines that the current number of inserted medals is the number of playable start numbers (when the determination in S232 is YES), the main CPU 101 performs the process of S235 described later. On the other hand, in S232, when the main CPU 101 determines that the current number of inserted medals is not the playable start number (when the determination in S232 is NO), the main CPU 101 determines whether or not there is a medal inserted (S233). ).

In S233, when the main CPU 101 determines that a medal has been inserted (when the determination in S233 is YES), the main CPU 101 returns the process to S226 and repeats the processes after S226. On the other hand, when the main CPU 101 determines in S233 that no medal has been inserted (NO in S233), the main CPU 101 performs the setting change confirmation process described with reference to FIG. 68 (S234). In this process, the main CPU 101 performs a setting change command generation / storage process at the start of setting confirmation.

After the processing of S234 or when the determination in S232 is YES, the main CPU 101 determines whether or not the start switch 79 is in the ON state (S235).

When the main CPU 101 determines in S235 that the start switch 79 is not in the ON state (when the determination in S235 is NO), the main CPU 101 returns the process to S226 and repeats the processes after S226.

On the other hand, in S235, when the main CPU 101 determines that the start switch 79 is in the ON state (when the determination in S235 is YES), the main CPU 101 performs a medal acceptance prohibition process (S236). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medals are ejected from the medal payout outlet 24. Then, after the processing of S236, the main CPU 101 ends the medal acceptance / start check processing, and shifts the processing to S203 of the main flow (see FIG. 82).

In the present embodiment, the medal reception / start check process is performed as described above. Then, the processes of S232 to S234 during the above-mentioned medal acceptance / start check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 84. Among them, in the process of S234, the process is jumped to the address "SB_WVSC_00" of the execution program of the setting change confirmation process by the "CALLF" instruction which is the instruction code dedicated to the main CPU 101, and the setting change confirmation described with reference to FIGS. 68 and 69. Perform processing.

Then, the process of S234 during the above-mentioned medal acceptance / start check process, that is, the setting change confirmation process, is executed regardless of the game state. Therefore, in the present embodiment, regardless of the game state, that is, even if the game state is a bonus state (special prize operation state), the set value and the hall menu (various history data (error, power failure history, etc.)) are displayed. It can be confirmed, and fraudulent acts such as goto can be suppressed.

[Medal insertion process]
Next, with reference to FIGS. 85 and 86, the medal insertion process performed in S222 during the medal acceptance / start check process (see FIG. 83) will be described. FIG. 85 is a flowchart showing the procedure of the medal insertion process, and FIG. 86 is a diagram showing an example of a source program for executing the medal insertion process.

First, the main CPU 101 adds "1" to the value of the medal counter (S241). The medal counter is a counter for counting the number of inserted medals, and is provided in the main RAM 103.

Next, the main CPU 101 performs a medal insertion command generation / storage process (S242). In this process, the main CPU 101 generates data of a medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 167. That is, the medal insertion command is transmitted from the main control circuit 90 to the sub control circuit 200 each time one medal is inserted. The medal insertion command is configured to include parameters for specifying the number of inserted medals and the like.

Next, the main CPU 101 turns off the first to third LEDs for displaying the number of inserted medals included in the LED 82 (see FIG. 7) (S243). Next, the main CPU 101 calculates LED lighting data (lighting control data) corresponding to the number of inserted medals based on the number of inserted medals (value of the medal counter) (S244). In this process, for example, when the number of inserted medals is one, the LED lighting data for lighting only the first LED for displaying the number of inserted medals is calculated, and for example, when the number of inserted medals is three. LED lighting data for lighting all of the first to third LEDs for displaying the number of inserted medals is calculated. The method for calculating the LED lighting data will be described in detail later.

Next, the main CPU 101 uses the calculated LED lighting data to light the corresponding LED for displaying the number of inserted medals (S245). Then, after the processing of S245, the main CPU 101 ends the medal insertion processing, and shifts the processing to S223 of the medal acceptance / start check processing (see FIG. 83).

In the present embodiment, the medal insertion process is performed as described above. The medal insertion process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 86. Among them, in the process of S244, the LED lighting data for displaying the number of inserted medals is generated not by the loop process referring to the table but by the arithmetic process. This arithmetic processing is performed by sequentially executing the source codes "LD A, L" to "OR L" in the source program shown in FIG. 86 by the main CPU 101.

In this arithmetic processing, first, by executing the source code "LDA, L", the data of the number of inserted medals stored in the L register is stored in the A register. For example, when the number of inserted medals is 3, "00000011B" (decimal number "3") is stored in the A register. In the present embodiment, the 1-byte data is described as "***** B", but the last character "B" is "0" or "1" indicated before the character "B". Means that it is bit data.

Next, by executing the source code "ADD A, A", the data stored in the A register is added to the data stored in the A register, and the addition result is stored in the A register. For example, when the data stored in the A register before the execution of this "ADD" instruction is "00000011B" (when the number of inserted medals is 3), this "ADD" instruction causes the addition result. "00000011B" is stored in the A register.

Next, by executing the source code "DEC A", the data stored in the A register is subtracted by 1, and the subtraction result is stored in the A register. For example, if the data stored in the A register before the execution of the "DEC" instruction is "0000001110B", the subtraction result "000000101B" is stored in the A register by this "DEC" instruction. ..

Next, by executing the source code "OR L", a logical sum operation is performed between the data stored in the L register (the number of medals inserted) and the data stored in the A register, and the calculation result is stored in the A register. Stored. For example, when the data stored in the A register is "000000101B" and the data stored in the L register is "00000011B" before the execution of this "OR" instruction (the number of medals inserted is three). In this case, the "OR" instruction stores "000000111B", which is the result of the OR operation of both data, in the A register. Then, the data stored in the A register by executing the "OR" command becomes the LED lighting data for displaying the number of inserted medals (data indicating the lighting state of the inserted medal LED).

For example, when the number of inserted medals is 3, as described above, the final calculation result "000000111B" is for displaying the number of inserted medals by the calculation process of the LED lighting data for displaying the number of inserted medals in S244. It becomes LED lighting data. Then, in the present embodiment, "1/0" of bit 0 of the finally calculated LED lighting data is "on / off" of the output port to the LED (first LED) for displaying the number of inserted medals of the first piece. Corresponding to the "1/0" state of bit 1, corresponds to the "on / off" state of the output port to the LED (second LED) for displaying the number of inserted medals of the second piece, and "1" of bit 2. "/ 0" corresponds to the "on / off" state of the output port to the LED (third LED) for displaying the number of inserted medals. Therefore, when the number of inserted medals is 3, as described above, "000000111B" is generated as the LED lighting data, so that all the output ports of the first to third LEDs for displaying the number of inserted medals are displayed. It is set to the on state, and all the first to third LEDs for displaying the number of inserted medals are turned on.

When the LED lighting data for displaying the number of inserted medals is generated by arithmetic processing as described above, the table data referred to when generating the LED lighting data for displaying the number of inserted medals is not required, so that the table area of the main ROM 102 It is possible to increase the free space of the program and minimize the increase in the capacity of the program. That is, in the above-mentioned medal insertion process of the present embodiment, the process of displaying the medal insertion LED can be made more efficient, the free space of the main ROM 102 is secured (increased), and the increased free area is utilized. It becomes possible to enhance the playability.

[Ratio monitor display switching process]
Next, with reference to FIG. 87, the combination monitor display switching process performed in S226 during the medal reception / start check process (see FIG. 83) will be described. FIG. 87 is a flowchart showing the procedure of the combination monitor display switching process. It should be noted that this process is configured as a process that is stored in the non-standard area in the main ROM 102 and uses the non-standard work area in the main RAM 103 as the work area.

First, the main CPU 101 determines whether or not the combination display mode is waiting for the end (waiting for the end of display) (S2001). The combination display mode is identification information for controlling the display state of the combination monitor 95, and is one of display (display on), non-display (display off), and end waiting (display end waiting). The information is stored in the main RAM 103. As a result, the switching control of the display state of the combination monitor 95 is performed.

In S2001, when the main CPU 101 determines that the combination display mode is waiting for the end (waiting for the end of display) (when the determination in S2001 is YES), the main CPU 101 performs the process of S2004 described later. On the other hand, in S2001, when the main CPU 101 determines that the combination ratio display mode is not waiting for the end (waiting for the end of display) (when the determination in S2001 is NO), the main CPU 101 determines whether or not the combination non-display condition is satisfied. (S2002). The combination ratio non-display condition is a condition set to hide (display off) the display state of the combination ratio monitor 95, and is set when the settlement switch 78 is in the on state in the present embodiment. This is established when the key type switch 54 (setting switch) is in the ON state, when a medal is inserted (see FIG. 85), and when an error occurs (see FIG. 90 described later). However, it is possible not to set the combination non-display condition, and it is also possible to adopt only one or more of these conditions.

In S2002, when the main CPU 101 determines that the combination non-display condition is satisfied (when the determination in S2002 is YES), the main CPU 101 performs the process of S2004 described later. On the other hand, in S2002, when the main CPU 101 determines that the combination non-display condition is not satisfied (NO in S2002), the main CPU 101 determines whether or not the door open / close monitoring switch 67 is on. (S2003). Here, when the door open / close monitoring switch 67 is on, it means that the front door 2b is in the open state, and when the door open / close monitoring switch 67 is off, it means that the front door 2b is in the closed state.

In S2003, when the main CPU 101 determines that the door open / close monitoring switch 67 is not on (off) (when the determination in S2003 is NO), the main CPU 101 sets the display off to the combination display mode (S2004). .. Then, after the processing of S2004, the main CPU 101 ends the combination monitor display switching processing, and shifts the processing to S227 of the medal reception / start check processing (see FIG. 83).

On the other hand, in S2003, when the main CPU 101 determines that the door open / close monitoring switch 67 is ON (when the determination in S2003 is YES), the main CPU 101 sets the display on to the combination ratio display mode (S2005). Then, after the processing of S2005, the main CPU 101 ends the combination monitor display switching processing, and shifts the processing to S227 of the medal reception / start check processing (see FIG. 83).

In the present embodiment, the combination monitor display switching process is performed as described above. That is, when the above-mentioned combination ratio non-display condition is satisfied, or when the front door 2b is in the closed state, the display state of the combination ratio monitor 95 is switched to non-display (display off), and the above-mentioned combination is displayed. When the ratio non-display condition is not satisfied and the front door 2b is in the open state, the display state of the combination ratio monitor 95 is switched to display (display on). Therefore, the control load related to the ratio display can be reduced, and the life of the device for displaying the ratio (role ratio monitor 95) can be extended. Further, since the owner of the door key (not shown) (for example, a clerk of a game store, an inspector of a game machine, etc.) can perform the unlocking operation for the lock 5 of the front door 2b in principle. Since the display of the combination ratio monitor 95 cannot be visually recognized by anyone other than the holder of the door key (not shown), the safety regarding the display of the ratio can be improved.

[Medal insertion check process]
Next, the medal insertion check process performed in S229 during the medal acceptance / start check process (see FIG. 83) will be described with reference to FIGS. 88 and 89. Note that FIG. 88 is a flowchart showing the procedure of the medal insertion check process, and FIG. 89 is a diagram showing an example of a source program for executing the processes of S255 to S258 during the medal insertion check process.

First, the main CPU 101 determines whether or not the game is being replayed (S251).

When the main CPU 101 determines in S251 that the game is being replayed (when the determination in S251 is YES), the main CPU 101 ends the medal insertion check process and performs the medal acceptance / start check process (see FIG. 83). Transfer to S230.

On the other hand, in S251, when the main CPU 101 determines that the replay is not in progress (when the determination in S251 is NO), the main CPU 101 permits medal acceptance (S252). In this process, the solenoid of the selector 66 (see FIG. 4) is driven, and medals inserted from the medal insertion slot 14 are accepted. The accepted medals are counted and then guided to the hopper device 51.

Next, the main CPU 101 performs a bet button check process (S253). In this process, the main CPU 101 determines whether or not the bet button (MAX bet button 15a or 1-bet button 15b) has been operated based on the ON / OFF state of the BET switch 77. Next, the main CPU 101 determines whether or not the betting operation is completed based on the result of the betting button check processing in S253 (S254).

When the main CPU 101 determines in S254 that the betting operation has been completed (when the determination in S254 is YES), the main CPU 101 ends the medal insertion check process and performs the medal acceptance / start check process (see FIG. 83). Transfer to S230.

On the other hand, in S254, when the main CPU 101 determines that the betting operation has not been completed (when the determination in S254 is NO), the main CPU 101 determines that the medal sensor input state (game medium reception state) at the time of the current processing. Acquires the medal sensor input state at the time of the previous processing (S255). The medal sensor input state is information indicating the passing status of the medal received in the medal insertion slot 14 in the selector 66, and is the detection result of each medal sensor (not shown) provided at the entrance and the exit of the selector 66. Is generated by.

In the present embodiment, the medal sensor input state is represented by 1 byte (8 bits) of data, and the upstream first medal sensor (not shown) provided at the exit of the selector 66 side by side in the medal passing direction. The detection result corresponds to the bit 0 information ("0" or "1"), and the detection result of the second medal sensor (not shown) on the downstream side corresponds to the bit 1 information ("0" or "1"). To do. When the passage of the medal is detected by the first medal sensor, "1" is set in bit 0, and when the passage of the medal is detected by the second medal sensor, "1" is set in bit 1. Will be done. Therefore, the medal sensor input state "0000000000B" indicates the state before or after passing the medal (at the time of passing), and the medal sensor input state "00000001B" indicates the state at the start of passing the medal, and the medal sensor input state "0000000000B". "00000011B" indicates a state in which the medal is passing, and "00000010B" in the medal sensor input state indicates a state immediately before the completion of passing the medal.

Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current processing has changed from the medal sensor input state at the time of the previous processing (S256).

In S256, when the main CPU 101 determines that the medal sensor input state at the time of the current processing has not changed from the medal sensor input state at the time of the previous processing (when the determination in S256 is NO), the main CPU 101 is described in S261 described later. Perform processing.

On the other hand, in S256, when the main CPU 101 determines that the medal sensor input state at the time of the current processing has changed from the medal sensor input state at the time of the previous processing (when the determination in S256 is YES), the main CPU 101 is at the time of the previous processing. Based on the medal sensor input state, a normal value (normal change value) of the medal sensor input state obtained at the time of the current processing is generated by arithmetic processing (S257).

In this process, when the medal sensor input state at the time of the previous process is "0000000000B" (when both the first and second medal sensors have not detected medals), it is regarded as a normal change value of the medal sensor input state. When "00000001B" (when the first medal sensor detects medals and the second medal sensor does not detect medals) is generated and the medal sensor input state at the time of the previous processing is "00000001B", the medal sensor "00000011B" (when both the first and second medal sensors are medal detection) is generated as a normal change value of the input state. Further, in this process, when the medal sensor input state at the time of the previous process is "00000011B", the normal change value of the medal sensor input state is "00000010B" (the first medal sensor has not detected a medal, and the second (When the medal sensor is medal detection) is generated, and when the medal sensor input state at the time of the previous processing is "00000010B", the normal change value of the medal sensor input state is "0000000000B" (first and second medals). If both sensors do not detect medals) is generated. The method of generating (calculating) the normal change value of the medal sensor input state will be described in detail later.

Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current processing is the same as the normal change value generated in S257 (S258). In this determination process, it is determined whether or not a medal retrograde error has occurred, and if the determination condition of S258 is not satisfied, the main CPU 101 determines that a medal retrograde error has occurred.

In S258, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is not the same as the normal change value generated in S257 (when the determination in S258 is NO), the main CPU 101 performs the processing of S262 described later. Do.

On the other hand, in S258, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is the same as the normal change value generated in S257 (when the determination in S258 is YES), the main CPU 101 is at the time of the current processing. It is determined whether or not the medal sensor input state of the above is the state at the time of passing the medal (“00000000B”) (S259). In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current process is the state at the time of passing the medal (when the determination in S259 is YES), the main CPU 101 performs the process of S263 described later.

In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is not the state at the time of passing the medal (when the determination in S259 is NO), the main CPU 101 sets the medal passing check timer (S260). The time set in the medal passage check timer in this process can be set to any time as long as it is possible to determine whether or not the medal has passed the selector 66. Further, the timer value set in this process may be changed according to, for example, the medal sensor input state at the time of the current process.

After the processing of S260 or when the determination of S256 is NO, whether or not the medal sensor input state at the time of the current processing is the medal passing state (“000000111B”) and the medal passing check timer is stopped. (S261). In this determination process, it is determined whether or not a medal passing error (inserted medal passing time error) has occurred, and if the determination condition of S261 is satisfied, the main CPU 101 determines that a medal passing error has occurred.

When the main CPU 101 determines in S261 that the determination condition of S261 is not satisfied (when the determination in S261 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253.

On the other hand, in S261, when the main CPU 101 determines that the determination condition of S261 is satisfied (when S261 is a YES determination), or when S258 is a NO determination, that is, a medal passing error or a medal retrograde error has occurred. If it is determined, the main CPU 101 performs error processing (S262). In this process, the main CPU 101 performs various processes when an error occurs, such as an error command generation and storage process. The details of error handling will be described later with reference to FIG. 90 described later. Then, after the processing of S262, the main CPU 101 returns the processing to the processing of S253, and repeats the processing after S253.

Here, returning to the process of S259 again, if S259 is a YES determination, the main CPU 101 determines whether or not a specified number of medals (three medals in this embodiment) have already been inserted (S263). ..

In S263, when the main CPU 101 determines that the specified number of medals have not been inserted (NO in S263), the main CPU 101 performs the medal insertion process described with reference to FIG. 85 (S264). Then, after the processing of S264, the main CPU 101 returns the processing to the processing of S253, and repeats the processing after S253.

On the other hand, in S263, when the main CPU 101 determines that a specified number of medals have already been inserted (when the determination in S263 is YES), the main CPU 101 adds "1" to the value of the credit counter (S265). ). Next, the main CPU 101 performs a medal insertion command generation / storage process (S266). In this process, the main CPU 101 generates data of a medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 167.

Next, the main CPU 101 determines whether or not the number of credits of the medal is the upper limit value (50 in the present embodiment) based on the value of the credit counter (S267).

In S267, when the main CPU 101 determines that the number of credits for medals is not the upper limit value (when the determination in S267 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253. On the other hand, in S267, when the main CPU 101 determines that the number of credits of medals is the upper limit value (when the determination in S267 is YES), the main CPU 101 ends the medal insertion check process and performs the medal acceptance / start check process. Transfer to S230 for processing (see FIG. 83).

In the present embodiment, the medal insertion check process is performed as described above. Then, the processes of S255 to S258 during the above-mentioned medal insertion check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 89. Among them, the process of generating the normal change value of the medal sensor input state of S257 is performed not by the process of referencing and acquiring the table, but by the arithmetic process. Specifically, the normal change value generation process is performed by the main CPU 101 executing the source codes "RLA" and "AND cBX_MDINSW" in the source program shown in FIG. 89 in this order.

The "RLA" instruction is an instruction code that shifts the 1-byte data stored in the A register to the left (in the direction from bit 0 to bit 7) once (by 1 bit). In the example shown in FIG. 89, the 1-byte data indicating the previous medal sensor input state stored in the A register by the source code “LDA, B” executed before the “RLA” instruction is the “RLA” instruction. Shifts to the left once. At this time, the bit data newly stored in bit 0 is determined based on the execution result of the source code "CP cBX_MDISW2" executed before the "RLA" instruction.

The "CP" instruction is an instruction code that executes a comparison operation. Further, "cBX_MDISW2" is 1 byte of data, and is "00000010B" in this embodiment. When the source code "CP cBX_MDISW2" is executed, 1-byte data indicating the previous medal sensor input state stored in the A register is compared with "cBX_MDISW2 (00000010B)".

Then, as a result of executing the source code "CP cBX_MDISW2", if the result that the 1-byte data indicating the previous medal sensor input state is less than "cBX_MDISW2 (00000010B)" is obtained, the carry flag of the flag register F is obtained. (See FIG. 11) is set to "1", and when the "RLA" instruction is executed, the carry flag "1" of the flag register F is stored in bit 0 of the A register. On the other hand, as a result of executing the source code "CP cBX_MDISW2", if the result that the 1-byte data indicating the previous medal sensor input state is "cBX_MDISW2 (00000010B)" or more is obtained, the carry flag of the flag register F is obtained. (See FIG. 11) is set to "0", and when the "RLA" instruction is executed, the carry flag "0" of the flag register F is stored in bit 0 of the A register.

Therefore, for example, if the 1-byte data indicating the previous medal sensor input state is "0000000000B (state before or after passing the medal (when passing))" (<"cBX_MDISW2"), the "RLA" command is issued. By execution, "00000001B" is generated, and if the 1-byte data indicating the previous medal sensor input state is "00000001B (state at the start of medal passage)" (<"cBX_MDISW2"), the "RLA" instruction is executed. Will generate "00000011B". On the other hand, for example, if the 1-byte data indicating the previous medal sensor input state is "000000111B (state during medal passing)" (> "cBX_MDISW2"), "00000011B" is generated by executing the "RLA" instruction. If the 1-byte data indicating the previous medal sensor input state is "00000010B (state immediately before the completion of medal passage)" (= "cBX_MDISW2"), "00000100B" is generated by executing the "RLA" command. To.

Next, when the source code "AND cBX_MDINSW" is executed, the 1-byte data (stored data in the A register) generated by executing the "RLA" instruction is logically stacked with the 1-byte data "cBX_MDINSW", and the medal sensor. The normal change value of the input state is calculated. The 1-byte data "cBX_MDISW" is "00000011B" in the present embodiment. Therefore, when the source code "AND cBX_MDINSW" is executed, only the data of bit 0 and bit 1 in the stored data of the A register is masked, and the other bit data becomes "0".

As a result, for example, if the 1-byte data indicating the previous medal sensor input state is "00000000000B (state before passing the medal)", the normal change value of the medal sensor input state is "00000001B (state at the start of passing the medal)". ) ”Is generated, and if the 1-byte data indicating the previous medal sensor input state is“ 00000001B (state at the start of medal passage) ”, the normal change value of the medal sensor input state is“ 000000111B (during medal passing). State) ”is generated. On the other hand, for example, if the 1-byte data indicating the previous medal sensor input state is "000000111B (state during medal passing)", the normal change value of the medal sensor input state is "00000010B (state immediately before the completion of medal passage)". Is generated, and if the 1-byte data indicating the previous medal sensor input state is "00000010B" (the state immediately before the completion of passing the medal), the normal change value of the medal sensor input state is "0000000000B (after passing the medal (passing)). Time) state) ”is generated.

As described above, by changing the detection process of the change mode of the medal sensor input state from the table reference process to the arithmetic process, the free space of the table storage area of the main ROM 102 can be increased and the capacity of the program can be increased. Can be minimized. Therefore, by adopting the above-mentioned method, it is possible to improve the efficiency of the detection process of the medal insertion sensor state, and it is possible to improve the playability by utilizing the increased free space in the main ROM 102.

[Error handling]
Next, with reference to FIGS. 90 and 91, for example, the error processing performed in S262 during the medal insertion check processing (see FIG. 88) will be described. FIG. 90 is a flowchart showing an error processing procedure, and FIG. 91 is a diagram showing an example of the configuration of an error table actually referred to on the error processing source program.

In the error table shown in FIG. 91, for each 1-byte data (for example, 1-byte data stored in the address “dERR_HE” in FIG. 91) indicating the on / off state of the port indicating the type of the error factor, Error display data (for example, 1-byte data stored in the addresses "dERR_HE + 1" and "dERR_HE + 2" in FIG. 91) is defined. This error display data is output to the 2-digit 7-segment LED (both for displaying the number of payouts and for displaying the error) included in the information display 6.

First, the main CPU 101 turns off the medal solenoid (S271). Specifically, the main CPU 101 stops driving the solenoid of the selector 66 (see FIG. 7). Next, the main CPU 101 saves the medal payout number display data (S272).

Next, the main CPU 101 performs an error table setting process (S273). By this process, the start address of the error table shown in FIG. 91 is set on the source program.

Next, the main CPU 101 acquires an error factor (S274). The error factor acquired in this process changes according to the process in which the error process currently being processed is read. As shown in FIG. 91, the error factors targeted in this embodiment include "hopper empty error", "hopper jam error", "inserted medal passing count error", "inserted medal passing check error", and "" "Insert medal passage check error", "Insert medal passage time error", "Insert medal retrograde error", "Insert medal auxiliary storage full error", and "Illegal hit error" are specified. For example, when the error processing is read after the processing of S258 during the medal insertion check processing, the “inserted medal retrograde error (Cr)” in FIG. 91 is acquired as an error factor in this processing. Further, for example, when the error process is read after the process of S261 during the medal insertion check process, the "inserted medal passing time error (CE)" in FIG. 91 is acquired as an error factor in this process. ..

Next, the main CPU 101 acquires error display data from the error table and the error cause (S275). For example, when the error factor is "insertion medal retrograde error (Cr)", the error shown in FIG. 91 is used as the error display data to be output to the upper digit 7-segment LED among the 2-digit 7-segment LEDs in this process. The 1-byte data "001001110B" stored in the address "dERR_CR + 1" in the table is acquired, and the 1-byte data "00000101B" stored in the address "dERR_CR + 2" is used as error display data to be output to the lower digit 7-segment LED. Is acquired. In this case, the two characters "Cr" are displayed as error information on the two-digit 7-segment LED.

Next, the main CPU 101 performs an error command (generation) generation and storage process (S276). In this process, the main CPU 101 generates data of an error command when an error occurs, which is transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. .. The error command when an error occurs stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 167. The error command when an error occurs includes a parameter indicating that an error has occurred.

Next, the main CPU 101 performs a standby process for an interrupt time (1.1172 ms) (S277). Next, the main CPU 101 determines whether or not the error has been cleared (S278).

When the main CPU 101 determines in S278 that the error has not been cleared (when the determination in S278 is NO), the main CPU 101 returns the process to the process in S277 and repeats the processes after S277.

On the other hand, in S278, when the main CPU 101 determines that the error has been cleared (when the determination in S278 is YES), the main CPU 101 performs an error factor clearing process (S279). This process is performed in a non-standard work area of the main RAM 103. Next, the main CPU 101 performs a restoration process of the payout number display data of the medals saved in S272 (S280).

Next, the main CPU 101 performs an error command (release) generation and storage process (S281). In this process, the main CPU 101 generates data of an error command at the time of error cancellation to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. .. The error command at the time of canceling the error stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 167. The error command at the time of error cancellation includes a parameter indicating error cancellation. Then, after the processing of S281, the main CPU 101 ends the error processing, and shifts the processing to, for example, S253 during the medal insertion check processing (see FIG. 88). In the error release, the generated error factor is released, and the error state is released by pressing the reset switch 76.

[Random number acquisition process]
Next, with reference to FIG. 92, the random number acquisition process performed in S203 in the main flow (see FIG. 82) will be described. Note that FIG. 92 is a flowchart showing the procedure of the random number acquisition process.

First, the main CPU 101 acquires a hard latch random number (0 to 65535) of the random number register 0 of the random number circuit, and uses the acquired random number value as a random number value for internal winning combination lottery, and uses a random number value storage area (non-standard) in the main RAM 103. It is stored in (shown) (S291).

Next, the main CPU 101 generates soft latch random numbers (0 to 65535: random numbers for production used in ART-related lottery processing, random numbers in 0 to 255: 1-byte lottery processing) of random number registers 1 to 7 of the random number circuit. The soft latch random number acquisition register is set for this purpose (S292). Next, the main CPU 101 sets the acquisition number (for example, 7) of the soft latch random numbers (S293).

Next, the main CPU 101 collectively acquires the number of acquired soft latch random numbers, and stores the acquired number of soft latch random numbers in the random number value storage area (S294). At this time, the soft latch random number (effect random number value, 2-byte random number value) acquired from the random number register 1 of the random number circuit 110 is the hardware acquired from the random number register 0 of the random number circuit in the random number value storage area. It is stored in an area different from the area in which the latch random number (random number value for the internal winning combination lottery) is stored. Then, after the processing of S294, the main CPU 101 ends the random number acquisition processing and shifts the processing to S204 of the main flow (see FIG. 82). In the present embodiment, in order to store four 2-byte random numbers and four 1-byte random numbers, a 12-byte storage area is allocated to the main RAM 103 as a random number storage area.

[Internal lottery processing]
Next, the internal lottery process performed in S204 in the main flow (see FIG. 82) will be described with reference to FIGS. 93 to 97. FIG. 93 is a flowchart showing the procedure of the internal lottery process, FIG. 94A is a diagram showing an example of a source program for executing the processes of S302 to S305 during the internal lottery process, and FIG. 94B is a diagram. It is a figure which shows an example of the source program for executing the process of S308-S309 in the internal lottery process.

Further, FIG. 95 is a diagram showing an example of the configuration of an internal lottery table (for general game) actually referred to on the source program of the internal lottery process, and FIG. 96 is a diagram showing an example of the configuration of the internal lottery table (for general game). It is a figure which shows an example of the structure of the lottery value selection table by RT state which is actually referred. Further, FIG. 97 shows an internal lottery value table selection table, a 1-byte internal lottery value table, a 2-byte internal lottery value table, a 2-byte internal lottery value table, and an internal lottery value table for each 1-byte setting that are actually referred to on the source program of the internal lottery process. It is a figure which shows an example of the structure of the internal lottery value table by 2 byte setting. In the present embodiment, an internal lottery table for RB (BB) is also provided, but here, the configuration of the internal lottery table for RB referred to on the source program of the internal lottery process is shown. Omit.

First, the main CPU 101 performs a set value / medal insertion number check process (S301). In this process, the main CPU 101 checks the set value (any of 1 to 6) of the current game and the number of inserted medals (3 in the present embodiment).

Next, the main CPU 101 sets the internal lottery table for general games and the number of lottery (53 times in this embodiment) (S302). In this process, the value (winning request flag status) of the "special prize winning number + small winning combination winning number" in the internal lottery table (for general game) shown in FIG. 95 is set in the C register, and the "lottery value selection table or The value of the lottery coefficient table (judgment data: data related to the address) is set in the A register. As shown in FIG. 95, the winning request flag status is set to the special prize winning number ("00H (off)", "01H (BB1)", "02H (BB2)": decimal number 0, 1, 2). "25H (hexadecimal number: 37 in decimal number (special prize number described later)) multiplied by the small winning combination winning number (" 00H "to" 24H ": 0 to 36 in decimal number) is added. ..

Next, the main CPU 101 determines whether or not the RB is in operation (S303). When the main CPU 101 determines in S303 that the RB is not in operation (when the determination in S303 is NO), the main CPU 101 performs the process of S305 described later.

On the other hand, when the main CPU 101 determines in S303 that the RB is in operation (when the determination in S303 is YES), the main CPU 101 sets the internal lottery table for RB and the number of lottery (5 times in this embodiment). Set (S304). In this process, the internal lottery table and the number of lottery for general games set in S302 are overwritten by the internal lottery table and the number of lottery for RB.

After the processing of S304 or when the determination in S303 is NO, the main CPU 101 acquires the determination data (data related to the address) of the lottery target combination from the set internal lottery table, and updates the lottery table address (S305).

Next, the main CPU 101 determines whether or not the determination data is RT state-specific data (S306). In this process, the main CPU 101 determines whether or not the currently acquired lottery target combination is an internal winning combination whose lottery value changes according to the RT state. Specifically, the main CPU 101 determines whether or not the address defined in the currently acquired lottery target combination determination data is the address in the lottery value selection table for each RT state shown in FIG. 96. ..

For example, in the determination data "(dRPPTR01-dRTRB_SEL) * 2 + 001H" associated with the internal winning combination "F_chililip" in the internal lottery table of FIG. 95, the internal winning in the lottery value selection table for each RT state shown in FIG. 96 Since the address "dRPPTR01" of the combination "F_chilip" is defined, the determination data associated with the internal winning combination "F_chilip" corresponds to the RT state-specific data. Therefore, when the currently acquired lottery target combination is the internal winning combination “F_Chillilip”, the main CPU 101 determines that the determination data is the RT state-specific data in the processing of S306.

In S306, when the main CPU 101 determines that the determination data is not the RT state-specific data (when the determination in S306 is NO), the main CPU 101 performs the process of S308 described later. On the other hand, in S306, when the main CPU 101 determines that the determination data is the data for each RT state (when the determination in S306 is YES), the main CPU 101 selects the RT state lottery value shown in FIG. 96 based on the determination data. Selection data is acquired from the table, and the acquired selection data is set in the determination data (S307).

After the processing of S307 or when the determination in S306 is NO, the main CPU 101 determines whether or not the determination data of the lottery target combination is the data for each setting (S308). In this process, the main CPU 101 determines whether or not the currently acquired lottery target combination is an internal winning combination whose lottery value changes according to the set value. Specifically, in the main CPU 101, the address defined in the currently acquired lottery target combination determination data is in the 1-byte setting internal lottery value table or the 2-byte setting internal lottery value table shown in FIG. 97. It is determined whether or not the address is.

For example, in the determination data "((dNMLB00F289-dPRB_DB_WV) / 06H) * 2 + 080H" associated with the internal winning combination "F_strong Chile 1" in the internal lottery table of FIG. 95, the internal by 1-byte setting shown in FIG. Since the address "dNMLB00F289" of the internal winning combination "F_strong Chile 1" in the lottery value table is specified, the judgment data associated with the internal winning combination "F_strong Chile 1" corresponds to the data for each setting. To do. Therefore, when the currently acquired lottery target combination is the internal winning combination “F_strong dust 1”, the main CPU 101 determines that the determination data is the setting-specific data in the process of S308.

In S308, when the main CPU 101 determines that the determination data is not the setting-specific data (when the determination in S308 is NO), the main CPU 101 performs the process of S310 described later. On the other hand, in S308, when the main CPU 101 determines that the determination data is the data for each setting (when the determination in S308 is YES), the main CPU 101 adds the set value data (any of 0 to 5) to the determination data. Then, the added value is set in the determination data (S309). The set value data added to the determination data in this process is the data associated with the set value, but the set value data "0" to "5" are not the values of the set value itself, but are "0" to "5", respectively. It is the data corresponding to "setting 1" to "setting 6".

After the processing of S309 or when the determination in S308 is NO, the main CPU 101 calculates the address of the area in which the lottery value of the lottery target combination is stored based on the set determination data (address data), and sets the address to the address. The stored lottery value is acquired (S310).

In the processing of S310, for example, when the lottery target combination is the internal winning combination “F_Sabo 2” whose lottery value does not depend on both the RT state and the set value, the 1-byte internal lottery value table shown in FIG. 97. The lottery value "128" stored in the address "dNM_B00F26" is acquired from. Further, for example, when the lottery target combination is the internal winning combination “F_RT3 lip_1st” whose lottery value changes depending on the RT state and the RT state is the RT2 state, the 2-byte internal lottery value table shown in FIG. 97 The lottery value "1800" stored in the address "dRT2B00F13456" is acquired from.

Further, in the processing of S310, for example, when the lottery target combination is the internal winning combination “F_strong chili 1” whose lottery value changes depending on the set value, the internal lottery value table for each 1-byte setting shown in FIG. 97. From the six types of lottery values "150 (setting 1), 150 (setting 2), 150 (setting 3), 150 (setting 4), 160 (setting 5), 170 (setting 6)" specified in The lottery value corresponding to the set value is acquired. At this time, the lottery value corresponding to the set value is acquired by adding the set value data to the determination data (processing in S309) and designating the obtained address. Therefore, for example, when the lottery target combination is "F_strong chili 1" and the set value is "6" (set value data is "5"), the lottery value "dNMLB00F289 + 5" stored in the address "dNMLB00F289 + 5" 170 "is acquired.

In the present embodiment, in the case of a combination whose lottery value depends on both the RT state and the set value, such as the internal winning combination "F_maintenance lip A", the internal lottery value table and the internal lottery by setting are used. The lottery value is obtained by referring to both of the value tables.

Next, the main CPU 101 acquires a random number value (any of 0 to 65535) for the internal winning combination lottery stored in the random number storage area (S311).

Next, the main CPU 101 performs a lottery execution process (S312). In this process, the main CPU 101 adds the random number value acquired in S311 to the lottery value acquired in S310, and sets the addition result as the lottery result (winning / non-winning of the lottery target combination). In this lottery execution process, when the sum of the lottery value and the random number value exceeds 65535 (overflow), it is determined that the lottery target combination has been won (the lottery target combination has been determined as the internal winning combination). To.

Next, the main CPU 101 stores a value obtained by adding the lottery value to the random number value (random number value after the lottery execution) as a new random number value in the random number storage area (S313). Next, the main CPU 101 determines whether or not the lottery execution process has won (whether or not an overflow has occurred) (S314).

In S314, when the main CPU 101 determines that the winning is won in the lottery execution process (when the determination in S314 is YES), the main CPU 101 refers to the internal lottery table and refers to the winning request flag status (corresponding to the winning internal winning combination). The value of "special prize winning number + small winning combination winning number") is acquired (S315). For example, in a general game, if a winning combination is won in the lottery execution process when the lottery target combination is "F_certain chili lip", in the processing of S315, the winning request flag status "(00H * 25H) + 02H" (special prize winning number =). 0, small winning combination number = 2) is acquired. Then, after the processing of S315, the main CPU 101 ends the internal lottery processing, and shifts the processing to S205 of the main flow (see FIG. 82).

On the other hand, in S314, when the main CPU 101 determines that the lottery has not been won in the lottery execution process (when the determination in S314 is NO), the main CPU 101 updates the lottery target combination to the next combination in the internal lottery table, and draws the lottery. The number of times is subtracted by 1 (S316). Next, the main CPU 101 determines whether or not the number of lottery after subtraction is "0" (S317).

In S317, when the main CPU 101 determines that the number of lottery after subtraction is not "0" (when the determination in S317 is NO), the main CPU 101 returns the process to the process of S305 and repeats the processes after S305.

On the other hand, in S317, when the main CPU 101 determines that the number of lottery after subtraction is "0" (when the determination in S317 is YES), that is, when the internal winning combination is "missing", the main CPU 101 determines. Set the loss status (S318). The "missing status" corresponds to the winning request flag status in which both the special prize winning number and the small winning combination winning number are "0". Then, after the processing of S318, the main CPU 101 ends the internal lottery processing, and shifts the processing to S205 of the main flow (see FIG. 82).

In the present embodiment, the internal lottery process is performed as described above. The processes S302 to S305 during the internal lottery process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 94A. Among them, the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 94A.

On the source program, for example, when the source code "LDIN ss, (HL)" is executed, the memory specified by the address set in the HL register (pair register) and the address obtained by adding "1" to the address. The contents (data) of are loaded into the ss (BC, DE, AC, AE or BD) pair register, and the address set in the HL register is updated by +2 (2 addition). Therefore, when the source code "LDIN AC, (HL)" in FIG. 94A is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( Data) is loaded into the AC register, and the address set in the HL register is updated by +2 (addition of 2). In the determination data acquisition process of S305, as described above, the determination data (value of "lottery value selection table or lottery coefficient table") is stored in the A register by this "LDIN" instruction (predetermined read instruction). It is stored, and the request flag status (value of "special prize winning number + small winning combination winning number") is stored in the C register.

As described above, in the determination data acquisition process of S305 during the internal lottery process, both the data load process and the address update process can be performed by one instruction code (“LDIN” instruction). In this case, the instruction code related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, the processes of S308 and S309 during the above-mentioned internal lottery process are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 94B. Among them, in the addition process of the set value data (any of 0 to 5) of S309, the main CPU 101 uses the source codes "MUL A, 6" and "ADDQ A, (.LOW.wWAVENUM)" in FIG. 94B. It is performed by executing in this order. Both the "MUL" instruction and the "ADDQ" instruction are instruction codes dedicated to the main CPU 101, and the "ADDQ" instruction is an instruction code dedicated to the main CPU 101 that specifies an address using a Q register (extension register).

When, for example, the source code "MUL A, n" is executed on the source program, the stored data in the A register is multiplied by the 1-byte integer n, and the multiplication result is stored in the A register. Therefore, in the source code "MUL A, 6" in FIG. 94B, the contents (stored data) of the A register are multiplied by a 1-byte integer 6, and the multiplication result is stored in the A register. This multiplication process is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, since the pachi-slot machine 1 of the present embodiment is provided with a dedicated calculation circuit (calculation circuit 107) for executing multiplication processing and division processing on the source program, the efficiency of multiplication processing and division processing should be improved. Can be done.

Further, for example, when the source code "ADDQ r, (k)" is executed on the source program, the stored data (upper address value) of the Q register and the 1-byte integer k (direct value: lower address value) are executed. The stored data of the r register (A, B, C, D, E, H or L register) is added to the memory contents (stored data) of the address specified by), and the addition result is stored in the r register. To. Therefore, when the source code "ADDQ A, (.LOW.wWAVENUM)" in FIG. 94B is executed, the stored data of the Q register and the memory of the address specified by the 1-byte integer value ".LOW.wWAVENUM". The contents (stored data) of the A register are added to the contents (set value data) of, and the addition result is stored in the A register.

That is, in the example shown in FIG. 94B, in the addition process of the set value in S309, the lottery target combination is obtained by multiplying the relative value for lottery table selection by the coefficient "6" and adding the set value data to the multiplied value. The address of the lottery table in which the lottery value of is stored is calculated.

As described above, in the present embodiment, the main CPU 101 dedicated instruction code (“ADDQ” instruction) using the Q register (extension register) is used in the internal lottery process, and if this instruction code is used, the direct value is used. This allows access to the main ROM 102, the main RAM 103, and the memory map I / O. Therefore, the instruction related to the address setting can be omitted on the source program of the internal lottery processing, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Design setting process]
Next, the symbol setting process performed in S205 in the main flow (see FIG. 82) will be described with reference to FIGS. 98 to 101.

FIG. 98 is a flowchart showing the procedure of the symbol setting process. FIG. 99 is a correspondence table between the special prize (bonus) winning number and the small winning combination winning number and the internal winning combination. In FIG. 99, the special prize winning number and the small winning combination winning number corresponding to "missing (00)" are not shown. Further, FIG. 100 is a diagram showing an example of a source program for executing the processes of S324 to S330 during the symbol setting process, and FIG. 101 is a hit actually referred to on the source program of the symbol setting process. It is a figure which shows an example of the structure of the request flag table (flag data table, winning flag table data).

First, the main CPU 101 extracts a special prize winning number and a small winning combination winning number based on the winning request flag status acquired by the internal lottery process, and extracts the extracted special winning winning number and the small winning combination winning number in the main RAM 103. It is stored in the winning number storage area (not shown) (S321).

In the present embodiment, as shown in FIG. 99, the special prize (bonus) winning numbers "1" and "2" are associated with the internal winning combinations "F_BB1" and "F_BB2", respectively. Further, the small winning combination "1" to "36" are associated with the internal winning combination "F_chili lip" to "F_RB combination 4", respectively. Then, as described with reference to FIG. 95, the value of the winning request flag status is obtained by multiplying the special prize winning number by the special prize number (“37 (25H in hexadecimal number)” in the present embodiment) and multiplying the value by the small winning combination winning number. It is the added value. Therefore, in the process of S321, since the special prize winning number and the small winning combination winning number are extracted from the value of the winning request flag status, in the present embodiment, the main CPU 101 sets the value of the winning request flag status to the special prize number (“37””. ) To divide. As a result, the value of the quotient generated by the division process becomes the special prize winning number (one of 0 to 2 in decimal number), and the remaining value becomes the small winning combination winning number (one of 0 to 36 in decimal number). Become.

Next, the main CPU 101 determines whether or not the small winning combination has been won based on the extracted small winning combination winning number (S322). In this process, if the small winning combination winning number is any of 1 to 36, the main CPU 101 determines that the small winning combination has won, and if the small winning combination winning number is 0, the main CPU 101 determines that the small winning combination has won. It is determined that the small role did not win.

In S322, when the main CPU 101 determines that the small winning combination has not been won (when the determination in S322 is NO), the main CPU 101 performs the process of S331 described later. On the other hand, in S322, when the main CPU 101 determines that the small winning combination has won (when the determination in S322 is YES), the main CPU 101 sets the small winning combination winning number as the initial value of the subtraction result (S323).

Next, the main CPU 101 sets the hit request flag table (see FIG. 101) (S324). Next, the main CPU 101 subtracts 1 from the subtraction result and updates the subtraction result (S325). Next, the main CPU 101 determines whether or not the subtraction result is less than "0" (S326).

In S326, when the main CPU 101 determines that the subtraction result is not less than "0" (when the determination in S326 is NO), the main CPU 101 performs the bit number calculation process (S327). In the bit number calculation process of S327, the number of blocks in the storage area of the hit request flag data corresponding to the small winning combination winning number specified in the hit request flag table is acquired.

In the present embodiment, the hit request flag storage area (internal winning combination storage area) is provided with blocks of hit request storage areas 0 to 7 and blocks of hit request storage areas 8 to 11. Therefore, the maximum value of the number of blocks in the storage area of the hit request flag data acquired by the bit number calculation process of S327 is “2”. For example, when the internal winning combination is "F_certain chili lip", as shown in the hit request flag table (see FIG. 101), the storage area 7 included in the blocks of the hit request storage areas 0 to 7 and the hit request Since the hit request flag data is defined in each of the storage areas 9 included in the blocks of the storage areas 8 to 11, the number of blocks in the storage area of the hit request flag data acquired in the bit number calculation process of S327 is "2". It becomes.

Next, the main CPU 101 performs a bit number calculation process (S328). In the bit number calculation process of S328, the number of bytes of the hit request flag data in the block unit specified in the hit request flag table (see FIG. 101) is calculated. For example, when the internal winning combination is "F_certain chili lip", 1 byte of hit request flag data is stored in both the storage area 7 and the storage area 9 as shown in the hit request flag table (see FIG. 101). Therefore, the number of bytes of the hit request flag data for each block acquired in the bit number calculation process of S328 is 1 byte. In the table shown in FIG. 101, the hit request flag data stored in the storage area 7 is described as "10000000B | 01000000B", but this is because the hit request flag data stored in the storage area 7 is described. It means that it is "10000000B" or ("|" is a symbol of the logical sum) "01000000B".

The above-mentioned processes of S325 to S328 are repeated as many times as the number of small winning combination winning numbers. For example, when the internal winning combination is "F_certain winning combination" (small winning combination number is "2"), the above-mentioned processing of S325 to S328 is repeated twice. When the processing of S325 to S328 is repeated a plurality of times, the number of blocks acquired in the bit number calculation processing of S327 and S328 and the number of bytes of the hit request flag data for each block are stored in another storage area. Will be done. Further, the number of blocks obtained by the processing of S325 to S328 described above and the number of bytes of the hit request flag data in the block unit are information (on-bit information) for designating the storage destination of the hit request flag data.

Here, returning to the processing of S326 again, when the main CPU 101 determines in S326 that the subtraction result is less than "0" (when the determination in S326 is YES), the main CPU 101 is in the hit request flag storage area ( The internal winning combination storage area) is set (S329). At this time, the main CPU 101 checks (updates) the hit request flag based on the number of blocks obtained by the above-mentioned processes of S325 to S328 and the number of bytes (on-bit information) of the hit request flag data for each block. Set only the storage area. Specifically, the address of the hit request flag storage area to be checked (updated) is stored in the DE register (see FIG. 100).

Next, the main CPU 101 performs a compressed data storage process (S330). In this process, the main CPU 101 mainly performs a process of transferring (expanding) the hit request flag data to a predetermined storage area in the hit request flag storage area to be checked (updated). The details of the compressed data storage process will be described later with reference to FIG. 102 described later.

After the processing of S330 or when the determination in S322 is NO, the main CPU 101 refers to the carry-over combination storage area (see FIG. 31) to determine whether or not there is a carry-over combination (S331). In S331, when the main CPU 101 determines that there is a carry-over combination (when the determination in S331 is YES), the main CPU 101 performs the process of S334 described later.

On the other hand, in S331, when the main CPU 101 determines that there is no carry-over combination (when the determination in S331 is NO), the main CPU 101 determines the bonus combination (BB1 or BB2) based on the special prize winning number extracted in the process of S321. ) Wins or not (S332).

In S332, when the main CPU 101 determines that the bonus combination has not been won (when the determination in S332 is NO), the main CPU 101 ends the symbol setting process and shifts the process to S206 in the main flow (see FIG. 82). Transfer.

On the other hand, in S332, when the main CPU 101 determines that the bonus combination has been won (when the determination in S332 is YES), the main CPU 101 stores the winning special prize winning number in the carry-over combination storage area (S333).

After the processing of S333 or when the determination in S331 is NO, the main CPU 101 sets the special prize winning number in the winning number storage area (not shown), sets the hit request flag data in the hit request flag storage area, and sets the RT state to RT5. Set to the state and clear (“0”) the number of RT games (the number of digestion games in the RT1 state) (S334). Then, after the processing of S334, the main CPU 101 ends the symbol setting processing and shifts the processing to S206 of the main flow (see FIG. 82).

In the present embodiment, the symbol setting process is performed as described above. The processing of S324 to S330 (compression / decompression processing of data related to winning) during the symbol setting processing described above is performed by sequentially executing each source code defined by the source program of FIG. 100 by the main CPU 101. .. Among them, the compressed data storage process of S330 is performed by the main CPU 101 executing the source code "CALLF SB_BTEP_00" in FIG. 100.

The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_BTEP_00" in FIG. 100 is executed, processing is performed at the address specified by "SB_BTEP_00". Jump and start the compressed data storage process. In the compressed data storage process of S330, as described above, the hit request flag data (compressed data) stored in the hit request flag table is expanded (copied) to the corresponding hit request flag storage area.

Further, the setting process of the address of the hit request flag storage area of S329 during the symbol setting process described above is performed by the main CPU 101 executing the source code "LDQ DE, .LOW. WWAVEBIT" in FIG. 100. That is, the processing of S329 during the symbol setting processing is performed by the "LDQ" instruction dedicated to the main CPU 101 that specifies the address using the Q register (extension register). In this case, the instruction code related to the address setting can be omitted on the source program of the symbol setting process, and the capacity of the source program of the symbol setting process (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the present embodiment, the data related to the winning is compressed / decompressed by the processing procedure described in S324 to S330 during the symbol setting process described above, and the command code dedicated to the main CPU 101 described above is used in the process. By using it, it is possible to improve the efficiency of the data compression / decompression processing related to the winning, and it is possible to effectively utilize the limited capacity of the main RAM 103.

[Compressed data storage process]
Next, with reference to FIG. 102, for example, the compressed data processing performed in S330 during the symbol setting process (see FIG. 98) will be described. FIG. 102 is a flowchart showing the procedure of the compressed data storage process.

The compressed data storage process shown in FIG. 102 is executed not only in S330 during the symbol setting process (see FIG. 98) but also in S649 during the symbol code acquisition process (see FIG. 129 described later) described later. In the compressed data storage process executed in S330 during the symbol setting process (see FIG. 98), the flag data to be processed is the hit request flag data (flag data related to the winning combination), but the symbol code acquisition process described later In the compressed data storage process executed in S649 (see FIG. 129 described later), the flag data to be processed is the winning operation flag data (flag data related to the winning combination). Then, both processes are the same except that the types of flag data to be processed are different.

Therefore, in the flowchart of FIG. 102, the flag data to be processed is referred to as “process target flag data”, and the flag table to be processed is referred to as “process target flag table”. Further, in accordance with this description, also in the following description of the compressed data storage process, the hit request flag data or the winning operation flag data is referred to as "process target flag data", and the hit request flag table (see FIG. 101) or described later. The symbol-corresponding winning operation table (see, for example, FIG. 131A described later) is referred to as a “processing target flag table”.

First, the main CPU 101 sets the storage destination check bit (S341). In this process, the storage destination check bit is stored in a register other than the A register.

The storage destination check bit is 1-byte data for designating a block that is a storage destination (transfer destination) of the processing target flag data. In the present embodiment, the hit request flag storage area and the winning operation flag storage area are both composed of two blocks (blocks of storage areas 0 to 7 and blocks of storage areas 8 to 11). Then, for example, when the internal winning combination “F_certain chili lip” is determined, the hit request flag data is stored in each of the storage area 7 and the storage area 9 as shown in the hit request flag table of FIG. 101. (Because the number of blocks in the storage destination is "2"), in the process of S341, "00000011B" is set as the storage destination check bit. The bit 0 value (1/0) of this 1-byte data corresponds to the presence or absence of a storage destination in the block of the storage areas 0 to 7, and the bit 1 value (1/0) corresponds to the storage areas 8 to 11. Corresponds to the presence or absence of the storage destination in the block of.

Next, the main CPU 101 sets the value of the transfer counter in byte units to "8" (S342). In the present embodiment, since the number of bytes of each block is "8", "8" is set as the initial value of the transfer counter.

Next, the value of the transfer instruction bit is extracted from the storage destination check bit (S343). The transfer instruction bit corresponds to the data of bit 0 in the storage destination check bit, and in the processing of S343, the storage destination check bit stored in the 1-byte register is shifted to the right once (for 1 bit). As a result, the transfer instruction bit is extracted. Specifically, when the 1-byte register (register other than the A register) in which the storage destination check bit is stored is shifted to the right once, the data stored in bits 7 to 1 are changed to bits 6 to 0, respectively. As it moves, the data of bit 0 before the shift is output. Then, the data output by this shift process becomes the value of the transfer instruction bit.

Next, the main CPU 101 determines whether or not there is a transfer instruction based on the value of the extracted transfer instruction bit (S344). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is "1". For example, when "00000011B" is set as the storage destination check bit, transfer is performed in the first (corresponding to the first block of the storage area) and second (corresponding to the second block of the storage area) determination process of S344. Although it is determined that there is an instruction, in the determination process of S344 after the third time, it is determined that there is no transfer instruction.

In S344, when the main CPU 101 determines that there is no transfer instruction (when the determination in S344 is NO), the main CPU 101 performs the process of S354 described later.

On the other hand, in S344, when the main CPU 101 determines that there is a transfer instruction (when the determination in S344 is YES), the main CPU 101 acquires byte unit storage destination designation information from the processing target flag table (S345). In this process, the transfer destination is stored at the start address of the area in which the flag data of the process target combination (winning combination or winning combination) in the processing target flag table is stored as the byte unit storage destination specification information. Byte data is retrieved. For example, when the internal winning combination is "F_certain chili lip", it is stored at the start address of the area in which the flag data of "F_certain chili lip" is stored in the hit request flag table shown in FIG. 101. The 1-byte data "10000000B" that designates the area 7 as the transfer destination is acquired as the byte unit storage destination designation information.

Next, the main CPU 101 performs an update process (a process of adding 1 to the address) of the address to be referred to in the process target flag table (S346). Further, in this process, the main CPU 101 sets as an initial address an address that specifies the head storage area of the block that is the storage (transfer) destination of the processing target flag data. For example, in the processing of the first block, the address of the storage area 0 is set as the initial address in the processing of S346, and in the processing of the second block, the address of the storage area 8 is set as the initial address in the processing of S346. ..

Next, the main CPU 101 extracts the value of the transfer instruction bit from the byte unit storage destination designation information (S347). The transfer instruction bit referred to here corresponds to bit 0 of the byte unit storage destination specification information, and in the processing of S347, the byte unit storage destination specification information stored in the 1-byte register is shifted to the right once. Extracts the value of the transfer instruction bit (outputs bit 0 data).

Next, the main CPU 101 determines whether or not there is a transfer instruction based on the value of the transfer instruction bit extracted in the process of S347 (S348). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is “1”. For example, when "00000010B" is set as the byte unit storage destination designation information, the bit 1 data "1" is processed in S347 of the second time (the storage area 1 of the first block or the storage area 9 of the second block). Is output as the value of the transfer instruction bit to determine that there is a transfer instruction, but in the first and third to eighth processes of S347, it is determined that there is no transfer instruction.

In S348, when the main CPU 101 determines that there is no transfer instruction (when the determination in S348 is NO), the main CPU 101 performs the process of S351 described later.

On the other hand, in S348, when the main CPU 101 determines that there is a transfer instruction (when the determination in S348 is YES), the main CPU 101 is the processing target flag stored in the address in the currently set processing target flag table. The data (winning request flag data or winning operation flag data) is transferred (copied) to the designated storage area (S349).

For example, when the internal winning combination is "F_certain chili lip" and the current processing is performed on the storage area (storage area 0 to 7) of the first block, the byte unit storage destination specification information is ". Since it becomes "10000000B" (data that specifies the storage area 7 as the storage destination), it is determined that there is a transfer instruction in the eighth processing of S347, and in the subsequent processing of S349, the hit request flag data "10000000B" and "01000000B" are obtained. , "00100000B" and "00010000B" are transferred (copied) to the storage area 7 of the hit request flag storage area.

Next, the main CPU 101 performs an update process (a process of adding 1 to the address) of the address to be referred to in the process target flag table (S350).

After the processing of S350 or when the determination in S348 is NO, the main CPU 101 performs an address update process (a process of adding 1 to the address) that specifies a storage area to be a storage destination of the processing target flag data (S351). Next, the main CPU 101 subtracts 1 from the value of the transfer counter (S352).

Next, the main CPU 101 determines whether or not the value of the transfer counter is "0" (S353). In S353, when the main CPU 101 determines that the value of the transfer counter is not "0" (when the determination in S353 is NO), the main CPU 101 returns the processing to the processing of S347 and repeats the processing after S347.

On the other hand, in S353, when the main CPU 101 determines that the value of the transfer counter is "0" (when the determination in S353 is YES), does the main CPU 101 have a transfer instruction target remaining in the current storage destination check bit? Whether or not it is determined (S354). In this process, the main CPU 101 determines whether or not a bit in which "1" is stored remains in the storage destination check bit at the time of the current process. Then, when the bit in which "1" is stored remains in the storage destination check bit, that is, when the block to be processed exists, the main CPU 101 gives a transfer instruction to the current storage destination check bit. Determine that the target remains.

In S354, when the main CPU 101 determines that the transfer instruction target remains in the current storage destination check bit (when the determination in S354 is YES), the main CPU 101 returns the process to the process of S342, and the process after S342. repeat. On the other hand, in S354, when the main CPU 101 determines that the transfer instruction target does not remain in the current storage destination check bit (when the determination in S354 is NO), the main CPU 101 ends the compressed data storage process and performs the process. For example, it is moved to S331 in the symbol setting process (see FIG. 98).

[Second interface board control process (non-standard)]
Next, the second interface board control process performed in S207 in the main flow (see FIG. 82) will be described with reference to FIG. 103. FIG. 103 is a flowchart showing the procedure of the second interface board control process. This process is performed in the non-standard work area (see FIG. 12C) in the main RAM 103. Further, the program used in the second interface board control process is stored in the non-standard area in the main ROM 102 (see FIG. 12B).

First, the main CPU 101 saves the address data of the stack area in the main RAM 103 set in the stack pointer (SP) (S361). Next, the main CPU 101 sets the address data of the non-standard stack area in the main RAM 103 in the stack pointer (SP) (S362).

Next, the main CPU 101 acquires navigation data (S363). Next, the main CPU 101 sets the navigation conversion table in the non-standard work area in the main RAM 103 (S364).

Next, the main CPU 101 refers to the navigation conversion table and acquires the push order number for the second interface (S365). Next, the main CPU 101 stores the acquired push order number for the second interface in the non-standard push order number storage area (not shown) provided in the non-standard work area (S366). Next, the main CPU 101 sets "0" to the value of the pressing position table selection counter provided in the non-standard work area (S367).

Next, the main CPU 101 determines whether or not the acquired navigation data is push-order navigation (navigation data for push-order small combination) (S368). In S368, when the main CPU 101 determines that the acquired navigation data is the push order navigation (when the determination in S368 is YES), the main CPU 101 performs the process of S372 described later.

On the other hand, in S368, when the main CPU 101 determines that the acquired navigation data is not the push-order navigation (when the determination in S368 is NO), the main CPU 101 determines that the acquired navigation data is the navigation data (10) for the BB1 stop operation. It is determined whether or not it is (S369).

In S369, when the main CPU 101 determines that the acquired navigation data is the navigation data for the BB1 stop operation (when the determination in S369 is YES), the main CPU 101 performs the process of S371 described later. On the other hand, in S369, when the main CPU 101 determines that the acquired navigation data is not the navigation data for the BB1 stop operation (when the determination in S369 is NO), the main CPU 101 sets the value of the pressing position table selection counter to "1". Is added (S370). In S370, the process of adding "1" to the value of the pressing position table selection counter is a process performed to acquire the pressing position of BB2 from the pressing position table (not shown).

After the processing of S370 or when the determination in S369 is YES, the main CPU 101 adds "1" to the value of the pressing position table selection counter (S371). In S371, the process of adding "1" to the value of the pressing position table selection counter is a process performed to acquire the pressing position of BB1 or BB2 from the pressing position table (not shown).

After the processing of S371 or when the determination in S368 is YES, the main CPU 101 selects the pressing position table (not shown) based on the value of the pressing position table selection counter (S372). Next, the main CPU 101 refers to the selected pressing position table and acquires pressing position data for three reels (left reel 3L, middle reel 3C, and right reel 3R) (S373). Next, the main CPU 101 stores the acquired pressing position data in the non-standard pressing position storage area (not shown) provided in the non-standard work area (S374). By the processing of S367 to S371, if the navigation data is the push order navigation, the value of the push position table selection counter becomes "0", and if the navigation data is the navigation data for the BB1 stop operation, the push position table selection counter The value is "1", and if the navigation data is the navigation data for the BB2 stop operation, the value of the pressing position table selection counter is "2". That is, the pressed position data is acquired based on the navigation data.

Next, the main CPU 101 performs the second interface board output process (S375). The details of the second interface board output process will be described later with reference to FIG. 104 described later.

Next, the main CPU 101 performs a reset process of all the registers (S376). Next, the main CPU 101 sets the address data of the stack area saved in S361 in the stack pointer (SP) (S377). Then, after the processing of S377, the main CPU 101 ends the second interface board control processing, and shifts the processing to S208 of the main flow (see FIG. 82).

[Second interface board output processing]
Next, the second interface board output process performed in S375 during the second interface board control process (see FIG. 103) will be described with reference to FIG. 104. FIG. 104 is a flowchart showing the procedure of the second interface board output processing. The second interface board output process is performed in the non-standard work area of the main RAM 103.

First, the main CPU 101 determines whether or not the transmission operation is performed via the second interface serial line (second serial communication circuit 115: SCU2) (S381). When the main CPU 101 determines in S381 that the transmission operation is being performed via the serial line for the second interface (when the determination in S381 is YES), the main CPU 101 ends the second interface board output process. The process is transferred to S376 of the second interface board control process (see FIG. 103).

On the other hand, in S381, when the main CPU 101 determines that the transmission operation is not performed via the serial line for the second interface (when the determination in S381 is NO), the main CPU 101 is provided in the non-standard work area. The loop counter value is set to "3" (the number of reels), and the serial communication sum value is set to the initial value "1" (S382). Next, the main CPU 101 transmits transmission start data via the second interface serial line (second serial communication circuit 115: SCU2) (S383).

Next, the main CPU 101 refers to the non-standard pressing position storage area of the predetermined reel (rotary reel), and acquires the pressing position data of the predetermined reel (S384). Next, the main CPU 101 updates the reference non-standard pressing position storage area to that of the next target reel (rotary reel) (S385).

Next, the main CPU 101 acquires pulse number data corresponding to the pressing position data (symbol position) based on the pulse conversion data (not shown) and the acquired pressing position data (S386). The details of the correspondence between the pressing position data (symbol position) and the pulse number data will be omitted, but for example, the acquired pressing position data (symbol position) is "3" (symbol "white 7" in the left reel 3L). ), "38" is acquired as the pulse number data, and when the pressing position data (symbol position) is "10" (symbol "replay" in the left reel 3L), "38" is acquired as the pulse number data. 155 ”is acquired. Further, for example, when the acquired pressing position data (symbol position) is "12" (symbol "blue 7" in the left reel 3L), "189" is acquired as the pulse number data, and the pressing position data (symbol) is acquired. When the position) is "15" (the symbol "replay" in the left reel 3L), "239" is acquired as the pulse number data.

Next, the main CPU 101 transmits the acquired pulse number data via the second interface serial line (second serial communication circuit 115: SCU2) (S387). Next, the main CPU 101 adds the pulse number data to the serial communication sum value (S388). Next, the main CPU 101 subtracts 1 from the value of the loop counter (S389).

Next, the main CPU 101 determines whether or not the value of the loop counter is "0" (S390). In S390, when the main CPU 101 determines that the value of the loop counter is not "0" (when the determination in S390 is NO), the main CPU 101 changes the target reel to the next reel and returns the process to S384. The processing after S384 is repeated.

On the other hand, in S390, when the main CPU 101 determines that the value of the loop counter is "0" (when the determination in S390 is YES), the main CPU 101 sets the serial communication sum value to the serial line for the second interface (the first). 2 Serial communication circuit 115: SCU2) for transmission (S391). Then, after the processing of S391, the main CPU 101 ends the second interface board output processing, and shifts the processing to S376 of the second interface board control processing (see FIG. 103).

[Control processing by state]
Next, with reference to FIG. 105, the state-specific control processing performed in S208 in the main flow (see FIG. 82) will be described. FIG. 105 is a flowchart showing the procedure of the state-specific control process.

First, the main CPU 101 performs a sub-flag conversion process (S401). In this process, the main CPU 101 performs a process of converting the internal winning combination into sub-flags (see FIGS. 36 and 37). The details of the sub-flag conversion process will be described later with reference to FIG. 106 described later.

Next, the main CPU 101 performs a navigation set process (S402). In this process, the main CPU 101 acquires navigation data based on the RT state, the game state, and the small winning combination winning number. The details of the navigation set processing will be described later with reference to FIG. 109 described later.

Next, the main CPU 101 determines whether or not the current RT state is the RT4 state (S403). In S403, when the main CPU 101 determines that the current RT state is not the RT4 state (when the determination in S403 is NO), the main CPU 101 performs the process of S406 described later.

On the other hand, in S403, when the main CPU 101 determines that the current RT state is the RT4 state (when the determination in S403 is YES), the main CPU 101 performs a flag conversion process (S404). In this process, the main CPU 101 performs a flag conversion lottery process (compression process of sub-flag data) for converting the sub-flag into the sub-flag EX (see FIG. 36). By this flag conversion process, 19 types (including loss) of sub-flags are converted (compressed) into 9 types (including loss) of sub-flag EX. The details of the flag conversion process will be described later with reference to FIG. 112 described later.

Next, the main CPU 101 performs a sub-flag compression process (S405). In this process, the main CPU 101 converts the sub-flag EX into the sub-flag D (see FIG. 36), and further compresses the sub-flag data. By this sub-flag compression process, 9 types (including loss) of sub-flag EX are converted (compressed) into 7 types (including loss) of sub-flag D.

After the processing of S405 or when the determination in S403 is NO, the main CPU 101 determines whether or not the current gaming state is the normal gaming state (S406).

In S406, when the main CPU 101 determines that the current gaming state is the normal gaming state (when the determination in S406 is YES), the main CPU 101 performs the normal middle start process (S407). The details of the normal start processing will be described later with reference to FIG. 113 described later. Then, after the processing of S407, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

On the other hand, in S406, when the main CPU 101 determines that the current gaming state is not the normal gaming state (when the determination in S406 is NO), the main CPU 101 determines whether or not the current gaming state is CZ (when the current gaming state is determined to be NO). S408).

In S408, when the main CPU 101 determines that the current gaming state is CZ (when the determination in S408 is YES), the main CPU 101 performs the CZ middle start process (S409). The details of the CZ middle start processing will be described later with reference to FIG. 114 described later. Then, after the processing of S409, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

On the other hand, in S408, when the main CPU 101 determines that the current gaming state is not CZ (when the determination in S408 is NO), the main CPU 101 determines whether or not the current gaming state is normal ART (S410). ).

In S410, when the main CPU 101 determines that the current gaming state is the normal ART (when the determination in S410 is YES), the main CPU 101 performs the normal start processing during the ART (S411). The details of the normal start processing during ART will be described later with reference to FIG. 118 described later. Then, after the processing of S411, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

On the other hand, in S410, when the main CPU 101 determines that the current gaming state is not normal ART (when the determination in S410 is NO), the main CPU 101 determines whether or not the current gaming state is CT (S412). ).

In S412, when the main CPU 101 determines that the current gaming state is CT (when the determination in S412 is YES), the main CPU 101 performs a process at the start during CT (S413). The details of the processing at the start during CT will be described later with reference to FIG. 119 described later. Then, after the processing of S413, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

On the other hand, in S412, when the main CPU 101 determines that the current gaming state is not CT (when the determination in S412 is NO), the main CPU 101 determines whether or not the current gaming state is a bonus state (S414). ).

In S414, when the main CPU 101 determines that the current gaming state is the bonus state (when the determination in S414 is YES), the main CPU 101 performs the process at the start during BB (S415). The details of the BB start processing will be described later with reference to FIG. 126 described later. Then, after the processing of S415, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

On the other hand, in S414, when the main CPU 101 determines that the current gaming state is not the bonus state (when the determination in S414 is NO), the main CPU 101 performs other processing (S416). In this process, the main CPU 101 performs a process according to a game state other than the game state targeted by the various determination processes. For example, when the current gaming state is the ART preparation state, processing corresponding to the ART preparation state is performed. Then, after the processing of S416, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

[Sub-flag conversion process]
Next, the sub-flag conversion process performed in S401 during the state-based control process (see FIG. 105) will be described with reference to FIGS. 106 to 108. FIG. 106 is a flowchart showing the procedure of the sub-flag change processing. Further, FIG. 107 is a diagram showing an example of a source program for executing the sub-flag change process, and FIG. 108 is a diagram of a sub-flag conversion table (conversion table) actually referred to on the source program of the sub-flag conversion process. It is a figure which shows an example of the structure.

First, the main CPU 101 acquires a small winning combination winning number (0 to 36) (S421). Next, the main CPU 101 determines whether or not the bonus operation is currently in progress (S422).

In S422, when the main CPU 101 determines that the bonus is currently in operation (when the determination in S422 is YES), the main CPU 101 converts the small winning combination winning number into a sub-flag in which the bonus is operating and saves it (S423). .. The process of converting the small winning combination winning number into the sub-flag during the bonus operation is performed by the main CPU 101 executing the source code "SUB (subtraction instruction) cNHT_RBST-c7HT1_FLA" in FIG. 107. Then, in the present embodiment, by executing this "SUB" instruction, the small winning combination winning number is uniformly converted into the sub-flag "cactus (14)". Then, after the processing of S423, the main CPU 101 ends the sub-flag conversion processing, and shifts the processing to S402 of the state-based control processing (see FIG. 105).

On the other hand, in S422, when it is determined that the main CPU 101 is not currently operating the bonus (when the determination in S422 is NO), the main CPU 101 sets the sub-flag conversion table shown in FIG. 108 (S424). In this process, the initial value of the sub-flag to be determined is set to "loss (00)", and the sub-flag "loss (00)" is set as the initial address of the block in the sub-flag conversion table shown in FIG. Set the address ("dSBCBVTB + 1") in which is stored.

Next, in the main CPU 101, whether the data of the small winning combination winning number defined in the block in the sub-flag conversion table currently being referred to is the data corresponding to the small winning combination winning number acquired in the current game. Whether or not it is determined (S425).

In S425, the main CPU 101 determines that the data of the small winning combination winning number defined in the block in the sub-flag conversion table to be referred to is not the data corresponding to the small winning combination winning number acquired in the current game. At this time (when the determination in S425 is NO), the main CPU 101 updates the block in the sub-flag conversion table to be referred to to the block at the next address (S426). Next, the main CPU 101 adds "1" to the value of the sub flag (S427). Then, after the processing of S427, the main CPU 101 returns the processing to the processing of S425, and repeats the processing after S425.

On the other hand, in S425, the data of the small winning combination winning number defined in the block in the sub-flag conversion table referred to by the main CPU 101 is the data corresponding to the small winning combination winning number acquired in the current game. When it is determined (when the determination in S425 is YES), the main CPU 101 refers to the sub-flag conversion table shown in FIG. 108 and refers to the sub-flag conversion control data associated with the small winning combination winning number (of the address of the small winning combination winning number). The 1-byte data stored at the next address) is acquired, and the sub-flag conversion control data is stored in the sub-flag conversion control data storage area (not shown) provided in the main RAM 103 (S428). In this process, for example, when the small winning combination winning number acquired in the current game is "03" (internal winning combination "F_3 consecutive chili lip"), the sub-flag conversion is performed with reference to the sub-flag conversion table shown in FIG. 108. The control data "00000011B" is acquired. Then, after the processing of S428, the main CPU 101 ends the sub-flag conversion processing, and shifts the processing to S402 of the state-based control processing (see FIG. 105).

In the present embodiment, the sub-flag conversion process is performed as described above. The above-mentioned sub-flag conversion process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 107. Further, in the sub-flag conversion table shown in FIG. 108, which is actually referred to on the source program of the sub-flag conversion process, sub-flag conversion control data (control status) is associated with each sub-flag. At this time, the same sub-flag conversion control data (control status) is associated with the same type of sub-flag.

For example, the sub-flag conversion control data (control status) "00000011B" is commonly assigned to the sub-flags "triple chili lip A" and "triple chili lip B". Further, for example, the sub-flag conversion control data (control status) "00000001B" is commonly assigned to the sub-flags "reach-eye lip 1" to "reach-eye lip 4". Then, in the flag conversion lottery process when converting the above-mentioned internal winning combination (sub-flag) to the sub-flag EX, the lottery is performed based on the sub-flag conversion control data (control status) stored in the sub-flag conversion control data storage area. ..

By providing common sub-flag conversion control data for the same type of internal winning combination (sub-flag) in the sub-flag conversion table for converting the flag managed on the main side (internal winning combination) to a flag manageable on the sub side. The versatility of the conversion table is increased, and changes in the conversion program due to a model change can be handled with minor changes, so that an increase in development cost can be suppressed.

[Naviset processing]
Next, with reference to FIGS. 109 to 111, the navigation set process performed in S402 during the state-based control process (see FIG. 105) will be described. FIG. 109 is a flowchart showing the procedure of the navigation set process. Further, FIG. 110 is a diagram showing an example of a source program for executing the processes of S434 to S436 described later during the navigation set processing, and FIG. 111 is actually referred to on the source program of the navigation set processing. It is a figure which shows an example of the structure of the navigation data table.

First, the main CPU 101 determines whether or not the navigation set flag is set in the sub-flag conversion control data storage area (not shown) (S431). Specifically, the main CPU 101 refers to the sub-flag conversion control data storage area, and the set sub-flag conversion control data is data corresponding to the small winning combination winning numbers (10 to 23) that generate push order navigation. Determine if it is. In S431, when the main CPU 101 determines that the navigation set flag is not set in the sub-flag conversion control data storage area (when the determination in S431 is NO), the main CPU 101 ends the navigation set processing and performs the processing according to the state. The control process (see FIG. 105) is transferred to S403.

On the other hand, in S431, when the main CPU 101 determines that the navigation set flag is set in the sub-flag conversion control data storage area (when the determination in S431 is YES), the RT state of the main CPU 101 is RT0 or RT1. Whether or not it is determined (S432). In S432, when the main CPU 101 determines that the RT state is not the RT0 or RT1 state (when the determination in S432 is NO), the main CPU 101 ends the navigation set process and controls the process according to the state (see FIG. 105). Move to S403.

On the other hand, in S432, when the main CPU 101 determines that the RT state is the RT0 or RT1 state (when the determination in S432 is YES), the main CPU 101 determines whether or not the gaming state is the general gaming state (when the RT state is determined to be YES). S433). In S433, when the main CPU 101 determines that the gaming state is the general gaming state (when the determination in S433 is YES), the main CPU 101 ends the navigation set process and controls the process according to the state (see FIG. 105). Move to S403.

On the other hand, in S433, when the main CPU 101 determines that the gaming state is not the general gaming state (when the determination in S433 is NO), the main CPU 101 acquires the small winning combination winning number (S434). Next, the main CPU 101 refers to the navigation data table shown in FIG. 111, and acquires navigation data (any of 1 to 9) based on the small winning combination winning number (S435).

Next, the main CPU 101 stores the acquired navigation data (information regarding the stop operation of the variable display of the plurality of display columns) in the navigation data storage area (stop operation instruction information storage area) (S436) in the main RAM 103. Then, after the processing of S436, the main CPU 101 ends the navigation set processing, and shifts the processing to S403 of the state-based control processing (see FIG. 105).

In this embodiment, the navigation set process is performed as described above. The processing of S434 to S436 during the navigation set processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 110. In this series of processing, as shown in FIG. 110, an "LDQ" instruction dedicated to the main CPU 101 that specifies an address using a Q register (extension register) is used on the source program.

For example, when the source code "LDQ A, (k)" is executed on the source program, the stored data in the Q register (upper address value) and the 1-byte integer k (direct value: lower address value). The contents (stored data) of the memory at the address specified in and are loaded into the A register. Therefore, for example, when the source code "LDQ A, (wHITFRT)" in FIG. 110 is executed, the stored data of the Q register and the contents of the memory of the address specified by the integer value "wHITFRT" are stored in the A register. Loaded into.

Further, for example, when the source code "LDQ (k), A" is executed on the source program, the stored data of the A register is the stored data of the Q register (upper address value) and the 1-byte integer k. It is loaded into the memory of the address specified by (direct value: lower address value). Therefore, for example, by executing the source code "LDQ (wNAVIPTN), A" in FIG. 110, the data (navigation data) stored in the A register becomes 1 byte with the stored data (upper address value) in the Q register. It is stored in the navigation data storage area of the address specified by the integer value "wNAVIPTN" (lower address value) of.

As described above, in the present embodiment, the main CPU 101 dedicated instruction code using the Q register (extension register) is used in the navigation set processing, and the main ROM 102, the main RAM 103, and the memory map I / O are accessed by direct values. can do. In this case, the instruction related to the address setting can be omitted on the source program of the navigation set processing, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Flag conversion process]
Next, with reference to FIG. 112, the flag conversion process performed in S404 during the state-based control process (see FIG. 105) will be described. Note that FIG. 112 is a flowchart showing the procedure of the flag conversion process.

First, the main CPU 101 determines whether or not it is the start of CT (S441).

When the main CPU 101 determines in S441 that it is not the start of CT (when the determination in S441 is NO), the main CPU 101 performs the process of S443 described later. On the other hand, in S441, when the main CPU 101 determines that it is the start of CT (when the determination in S441 is YES), the main CPU 101 determines the table number of the flag conversion lottery table used for the flag conversion lottery during CT by lottery. And set (S442).

After the processing of S442 or when the determination in S441 is NO, the main CPU 101 sets the flag conversion lottery table according to the current state (S443). For example, if the current state is the RT4 state during non-ART, the non-ART flag conversion lottery table (see FIG. 62) is set, and if the current state is the RT4 state during normal ART, The flag conversion lottery table during ART (see FIGS. 47A and 47B) is set, and when the current state is the RT4 state during CT, the flag conversion lottery table during CT (see FIG. 54) is set.

Next, the main CPU 101 refers to the set flag conversion lottery table, and performs the flag conversion lottery process based on the internal winning combination (S444). In fact, in this process, the main CPU 101 performs a flag conversion lottery process using the sub-flag conversion control data acquired from the sub-flag conversion control table shown in FIG. 108 based on the sub-flag corresponding to the internal winning combination.

Next, the main CPU 101 determines whether or not the flag conversion lottery of S444 has been won (S445).

In S445, when the main CPU 101 determines that the flag conversion lottery has been won (when the determination in S445 is YES), the main CPU 101 performs the sub-flag conversion process (S446). In this process, for example, when the internal winning combination is "F_1 certain chili lip", that is, when the sub flag is "triple chili lip B (03)", when the flag conversion lottery process is won, the sub flag conversion process of S446 is performed. , The sub-flag "triple chili lip B (03)" is converted to the sub-flag EX "fixed combination (06)" or the sub-flag EX "triple chili lip (07)" (see FIG. 36).

After the process of S446, the main CPU 101 determines whether or not the current gaming state is the non-ART state (S447). In S447, when the main CPU 101 determines that the current gaming state is not the non-ART state (when the determination in S447 is NO), the main CPU 101 ends the flag conversion process and controls the process according to the state (see FIG. 105). ) S405.

On the other hand, in S447, when the main CPU 101 determines that the current gaming state is the non-ART state (when the determination in S447 is YES), the main CPU 101 adds "1" to the number of ART sets (S448). Next, the main CPU 101 sets the ART preparation state in the game state of the next game (S449). Then, after the processing of S449, the main CPU 101 ends the flag conversion processing, and shifts the processing to S405 of the state-based control processing (see FIG. 105).

Here, returning to the process of S445 again, when the main CPU 101 determines in S445 that the flag conversion lottery has not been won (when the determination in S445 is NO), the main CPU 101 performs the sub-flag maintenance process (S450). .. In this process, for example, when the internal winning combination is "F_1 certain chili lip", that is, when the sub flag is "triple chili lip B (03)", and the flag conversion lottery is not winning, the sub flag of S450 is maintained. By the processing, the sub-flag "triple chili lip B (03)" is converted (maintained) into the sub-flag EX "replay (01)". Then, after the processing of S450, the main CPU 101 ends the flag conversion processing, and shifts the processing to S405 of the state-based control processing (see FIG. 105).

[Normal start processing]
Next, with reference to FIG. 113, the normal middle start process performed in S407 during the state-based control process (see FIG. 105) will be described. Note that FIG. 113 is a flowchart showing the procedure of the normal start processing.

First, the main CPU 101 refers to the CZ lottery table (see FIG. 41A), and performs the CZ lottery process based on the current CZ lottery state and the internal winning combination (sub flag) (S461). Next, the main CPU 101 determines whether or not the CZ lottery of S461 has been won (S462).

In S462, when the main CPU 101 determines that the CZ lottery has not been won (when the determination in S462 is NO), the main CPU 101 performs the process of S465 described later.

On the other hand, in S462, when the main CPU 101 determines that the CZ lottery has been won (when the determination in S462 is YES), the main CPU 101 sets the winning type CZ in the game state of the next game (S463). Next, the main CPU 101 sets the number of CZ games of the winning type in the CZ game number counter (S464). The CZ game number counter is a counter that counts the duration of CZ, and is provided in the main RAM 103. In the process of S464, for example, when CZ1 wins, the first predetermined number of games (for example, "12") is set in the CZ game number counter (first half), and CZ2 wins. Is set to a second predetermined number of games (for example, "15") in the CZ game number counter (first half), and when CZ3 wins, a fourth predetermined number of games is set in the CZ game number counter. (For example, "17") is set.

After the processing of S464 or when the determination in S462 is NO, the main CPU 101 usually refers to the medium-high probability lottery table (see FIG. 40A), and performs the transition lottery of the lottery state of CZ based on the internal winning combination (sub-flag) (S465). ). Next, the main CPU 101 updates the lottery state of CZ based on the result of the transition lottery (S466). Then, after the processing of S466, the main CPU 101 ends the normal middle start processing and also ends the state-specific control processing (see FIG. 105).

[Processing at start during CZ]
Next, with reference to FIG. 114, the CZ middle start process performed in S409 during the state-specific control process (see FIG. 105) will be described. Note that FIG. 114 is a flowchart showing the procedure of the start processing during CZ.

First, the main CPU 101 determines whether or not the current gaming state is CZ1 (S471).

In S471, when the main CPU 101 determines that the current gaming state is CZ1 (when the determination in S471 is YES), the main CPU 101 performs CZ1 (CZ2) intermediate processing (S472). The details of the processing during CZ1 (CZ2) will be described later with reference to FIGS. 115 and 116 described later. Then, after the processing of S472, the main CPU 101 ends the processing at the start during CZ, and also ends the state-specific control processing (see FIG. 105).

On the other hand, in S471, when the main CPU 101 determines that the current gaming state is not CZ1 (when the determination in S471 is NO), the main CPU 101 determines whether or not the current gaming state is CZ2 (S473). ..

In S473, when the main CPU 101 determines that the current gaming state is CZ2 (when the determination in S473 is YES), the main CPU 101 performs CZ1 (CZ2) intermediate processing (S474). Details of the processing during CZ1 (CZ2) will be described later with reference to FIGS. 115 and 116 described later. Then, after the processing of S474, the main CPU 101 ends the processing at the start during CZ, and also ends the state-specific control processing (see FIG. 105). In the present embodiment, the CZ1 intermediate processing and the CZ2 intermediate processing differ only in the rank (mode or point) indicating the degree of expectation of winning the ART lottery, and the basic processing contents are the same. Therefore, in the present embodiment, the CZ1 intermediate process and the CZ2 intermediate process will be described as one process as the CZ1 (CZ2) intermediate process.

On the other hand, in S473, when the main CPU 101 determines that the current gaming state is not CZ2 (when the determination in S473 is NO), the main CPU 101 performs CZ3 intermediate processing (S475). The details of the processing during CZ3 will be described later with reference to FIG. 117 described later. Then, after the processing of S475, the main CPU 101 ends the processing at the start during CZ, and also ends the state-specific control processing (see FIG. 105).

[Processing during CZ1 (CZ2)]
Next, with reference to FIGS. 115 and 116, the CZ1 (CZ2) intermediate processing performed in S472 or S474 during the CZ intermediate start processing (see FIG. 114) will be described. It should be noted that FIGS. 115 and 116 are flowcharts showing the procedure of processing during CZ1 (CZ2).

First, the main CPU 101 determines whether or not the current game is a game in the first half of CZ1 (or CZ2) (S481). In S481, when the main CPU 101 determines that the current game is not the game of the first half of CZ1 (or CZ2) (when the determination in S481 is NO), the main CPU 101 performs the process of S490 described later.

On the other hand, in S481, when the main CPU 101 determines that the current game is the game of the first half of CZ1 (when the determination in S481 is YES), the main CPU 101 refers to the mode-up lottery table during CZ1 (see FIG. 42). Then, the mode-up lottery process is performed based on the internal winning combination (sub flag) (S482). Further, in S481, when the main CPU 101 determines that the current game is a game in the first half of CZ2 (when the determination in S481 is YES), the main CPU 101 refers to the CZ2 middle point lottery table (see FIG. 43). , The point-up lottery is performed based on the internal winning combination (sub flag) (S482).

Next, the main CPU 101 updates the rank (mode or point) based on the lottery result of S482 (S483). Next, the main CPU 101 determines whether or not the freeze is won in the lottery of S482 (S484).

In S484, when the main CPU 101 determines that the freeze has been won (when the determination in S484 is YES), the main CPU 101 performs a freeze process for temporarily stopping the progress of the game, and the number of ART sets and the number of CT sets. Add "1" to (S485). Further, in this process, the main CPU 101 determines and sets the ART level with reference to the ART level determination table (see FIG. 48A). When a freeze occurs, "ART level 2" is determined as the ART level.

Next, the main CPU 101 sets the ART preparation state in the game state of the next game (S486). Then, after the processing of S486, the main CPU 101 ends the processing during CZ1 (CZ2), and also ends the processing at the start during CZ (see FIG. 114).

Here, returning to the processing of S484 again, when it is determined in S484 that the main CPU 101 has not won the freeze (when the determination in S484 is NO), the main CPU 101 is the value of the CZ game number counter (first half). Is subtracted by 1 (S487). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (first half) is "0" (S488).

In S488, when the main CPU 101 determines that the value of the CZ game number counter (first half) is not "0" (when the determination in S488 is NO), the main CPU 101 ends the processing during CZ1 (CZ2), and at the same time, The CZ middle start process (see FIG. 114) also ends.

On the other hand, in S488, when the main CPU 101 determines that the value of the CZ game number counter (first half) is "0" (when the determination in S488 is YES), the main CPU 101 sets the CZ1 or the game state of the next game. The latter half of CZ2 is set (S489). Then, after the processing of S489, the main CPU 101 ends the processing during CZ1 (CZ2), and also ends the processing at the start during CZ (see FIG. 114).

Here, returning to the process of S481 again, when the determination in S481 is NO, the main CPU 101 determines whether or not the current game is the first game in the latter half of CZ1 or CZ2 (S490). In S490, when the main CPU 101 determines that the current game is not the first game in the latter half of CZ1 or CZ2 (when the determination in S490 is NO), the main CPU 101 performs the process of S495 described later.

On the other hand, in S490, when the main CPU 101 determines that the current game is the first game in the latter half of CZ1 or CZ2 (when the determination in S490 is YES), the main CPU 101 uses the ART lottery table in CZ (FIGS. 44A and 44A and). (Refer to 44B), the ART lottery process is performed based on the rank (mode or point) of the first half (S491).

Next, the main CPU 101 determines whether or not the ART lottery has been won (S492). In S492, when the main CPU 101 determines that the ART lottery has not been won (when the determination in S492 is NO), the main CPU 101 performs the process of S494 described later.

On the other hand, in S492, when the main CPU 101 determines that the ART lottery has been won (when the determination in S492 is YES), the main CPU 101 adds "1" to the number of ART sets and sets the ART level determination table (see FIG. 48A). ), The ART level lottery is performed, and the lottery result is set (S493).

After the processing of S493 or when the determination in S492 is NO, the main CPU 101 sets a predetermined value in the CZ game number counter (second half) (S494). In the processing of S494, for example, when the ART lottery is won, "4" is set in the CZ game number counter (second half), and when the ART lottery is not won, the number of CZ games is set. "3" is set in the counter (second half).

After the processing of S494 or when the determination in S490 is NO, the main CPU 101 refers to the ART lottery table in CZ (see FIG. 44C) and performs the ART lottery processing based on the internal winning combination (sub flag) (S495).

Next, the main CPU 101 determines whether or not the ART lottery has been won (S496). In S496, when the main CPU 101 determines that the ART lottery has not been won (when the determination in S496 is NO), the main CPU 101 performs the process of S498 described later.

On the other hand, in S496, when the main CPU 101 determines that the ART lottery has been won (when the determination in S496 is YES), the main CPU 101 adds "1" to the number of ART sets and sets the ART level determination table (see FIG. 48A). ), The ART level lottery is performed, and the lottery result is set (S497).

After the processing of S497 or when the determination in S496 is NO, the main CPU 101 subtracts 1 from the value of the CZ game number counter (second half) (S498). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (second half) is "0" (S499).

In S499, when the main CPU 101 determines that the value of the CZ game number counter (second half) is not "0" (when the determination in S499 is NO), the main CPU 101 ends the processing during CZ1 (CZ2), and at the same time, The CZ middle start process (see FIG. 114) also ends.

On the other hand, in S499, when the main CPU 101 determines that the value of the CZ game number counter (second half) is "0" (when the determination in S499 is YES), the main CPU 101 has an ART set number of "1" or more. It is determined whether or not it is (S500).

In S500, when the main CPU 101 determines that the number of ART sets is "1" or more (when the determination in S500 is YES), the main CPU 101 sets the ART preparation state in the game state of the next game (S501). Then, after the processing of S501, the main CPU 101 ends the processing during CZ1 (CZ2), and also ends the processing at the start during CZ (see FIG. 114).

On the other hand, in S500, when the main CPU 101 determines that the number of ART sets is not "1" or more (when the determination in S500 is NO), the main CPU 101 sets the game state of the next game to the state at the time of CZ failure (when the CZ failure state is set). S502). Then, after the processing of S502, the main CPU 101 ends the processing during CZ1 (CZ2), and also ends the processing at the start during CZ (see FIG. 114).

[Processing during CZ3]
Next, with reference to FIG. 117, the CZ3 intermediate processing performed in S475 during the CZ intermediate start processing (see FIG. 114) will be described. Note that FIG. 117 is a flowchart showing the procedure of processing during CZ3.

First, the main CPU 101 refers to the ART lottery table in CZ (see FIG. 45), and performs the ART lottery process based on the internal winning combination (sub flag) (S511).

Next, the main CPU 101 determines whether or not the ART lottery has been won (S512). In S512, when the main CPU 101 determines that the ART lottery has not been won (when the determination in S512 is NO), the main CPU 101 performs the process of S518 described later.

On the other hand, in S512, when the main CPU 101 determines that the ART lottery has been won (when the determination in S512 is YES), the main CPU 101 adds "1" to the number of ART sets and adds "1" to the number of CT sets. Add (S513). Next, the main CPU 101 determines whether or not the freeze has been won in the ART lottery of S512 (S514).

In S514, when the main CPU 101 determines that the freeze has not been won (when the determination in S514 is NO), the main CPU 101 performs the process of S516 described later. On the other hand, in S514, when the main CPU 101 determines that the freeze has been won (when the determination in S514 is YES), the main CPU 101 performs a freeze process for temporarily stopping the progress of the game (S515).

After the processing of S515 or when the determination in S514 is NO, the main CPU 101 performs an ART level lottery process with reference to the ART level determination table (see FIG. 48A), and sets the lottery result (ART level) (S516). .. Next, the main CPU 101 sets the ART preparation state in the game state of the next game (S517). Then, after the processing of S517, the main CPU 101 ends the processing during CZ3 and also ends the processing at the start during CZ (see FIG. 114).

Here, returning to the process of S512 again, when the determination in S512 is NO, the main CPU 101 subtracts 1 from the value of the CZ game number counter (S518). Next, the main CPU 101 determines whether or not the value of the CZ game number counter is "0" (S519).

In S519, when the main CPU 101 determines that the value of the CZ game number counter is not "0" (when the determination in S519 is NO), the main CPU 101 ends the CZ3 middle processing and the CZ middle start processing (FIG. 114) also ends.

On the other hand, in S519, when the main CPU 101 determines that the value of the CZ game number counter is "0" (when the determination in S519 is YES), the main CPU 101 adds "1" to the number of ART sets and ARTs. An ART level lottery is performed with reference to the level determination table (see FIG. 48A), and the lottery result is set (S520). Next, the main CPU 101 sets the ART preparation state in the game state of the next game (S521). Then, after the processing of S521, the main CPU 101 ends the processing during CZ3 and also ends the processing at the start during CZ (see FIG. 114).

[Processing at start during normal ART]
Next, with reference to FIG. 118, the process at the start of normal ART performed in S411 during the state-specific control process (see FIG. 105) will be described. Note that FIG. 118 is a flowchart showing the procedure of the normal start processing during ART.

First, the main CPU 101 adds "1" to the value of the ART continuous game number counter (S531). The ART continuation game number counter is a counter that normally counts the number of games (the number of digested games) that ART has continued. Further, in the present embodiment, in addition to the ART continuous game number counter, an ART end game number counter that counts the number of games that can be normally continued by ART is also provided. Then, in the pachislot 1 of the present embodiment, the value of the ART continuous game number counter is compared with the value of the ART end game number counter, and when the value of the ART continuous game number counter reaches the value of the ART end game number counter, ART The game state ends.

Next, the main CPU 101 refers to the CT lottery table during ART (see FIG. 50), and performs the CT lottery process based on the current CT lottery state and the internal winning combination (sub flag) (S532). Next, the main CPU 101 determines whether or not the CT lottery has been won (S533). In S533, when the main CPU 101 determines that the CT lottery has not been won (when the determination in S533 is NO), the main CPU 101 performs the process of S536 described later.

On the other hand, in S533, when the main CPU 101 determines that the CT lottery has been won (when the determination in S533 is YES), the main CPU 101 adds "1" to the number of CT sets and adds "1" to the value of the CT game number counter. 8 ”is set (S534). Next, the main CPU 101 sets the winning type of CT in the game state of the next game (S535).

After the processing of S535 or when the determination in S533 is NO, the main CPU 101 refers to the ART level determination table (see FIG. 48B), draws the ART level based on the value of the ART continuous game number counter, and sets the lottery result. (S536). Next, the main CPU 101 refers to the normal ART medium-high probability lottery table (see FIG. 49), draws the CT lottery state of the migration destination based on the current CT lottery state and the internal winning combination (sub flag), and the lottery result. Is set (S537).

Next, the main CPU 101 refers to the additional lottery table during normal ART (see FIG. 51), and performs an additional lottery process for the number of ART games based on the internal winning combination (sub flag) (S538). Next, the main CPU 101 determines whether or not the additional lottery has been won (S539).

In S539, when the main CPU 101 determines that the additional lottery has not been won (when the determination in S539 is NO), the main CPU 101 performs the process of S541 described later. On the other hand, in S539, when the main CPU 101 determines that the additional lottery has been won (when the determination in S539 is YES), the main CPU 101 adds the winning result to the ART end game number counter (S540).

After the processing of S540 or when the determination in S539 is NO, the main CPU 101 determines whether or not the value of the ART continuous game number counter has reached the value of the ART end game number counter (S541). In S541, when the main CPU 101 determines that the value of the ART continuation game number counter has not reached the value of the ART end game number counter (when the determination in S541 is NO), the main CPU 101 normally processes at the start during ART. Is terminated, and the state-specific control process (see FIG. 105) is also terminated.

On the other hand, in S541, when the main CPU 101 determines that the value of the ART continuous game number counter has reached the value of the ART end game number counter (when the determination in S541 is YES), the main CPU 101 sets the number of ART sets to 1. Subtract (S542). Next, the main CPU 101 sets the state at the end of ART (S543). Then, after the processing of S543, the main CPU 101 ends the normal start processing during ART, and also ends the state-specific control processing (see FIG. 105).

[Processing at start during CT]
Next, with reference to FIG. 119, the process at the start of CT performed in S413 during the state-specific control process (see FIG. 105) will be described. Note that FIG. 119 is a flowchart showing the procedure of the start processing during CT.

First, the main CPU 101 refers to the additional lottery table during CT (see FIG. 55), and performs an additional lottery for the number of ART games based on the internal winning combination (sub flag) (S551). Next, the main CPU 101 determines whether or not the additional lottery has been won (S552).

In S552, when the main CPU 101 determines that the additional lottery has not been won (when the determination in S552 is NO), the main CPU 101 performs the process of S556 described later. On the other hand, in S552, when the main CPU 101 determines that the additional lottery has been won (when the determination in S552 is YES), the main CPU 101 adds the winning result to the ART end game number counter (S553). As described above, in the pachislot machine 1 of the present embodiment, as the number of times the sub-flag "triple chili lip (triple chili lip A or triple chili lip B)" is applied during the same CT increases, one lottery per lottery. The amount of extra is increased.

After the processing of S553, the main CPU 101 determines whether or not the internal winning combination corresponds to the sub-flag EX "triple chili lip" (or "fixed combination"), that is, the internal winning combination "F_certain chili lip" or "F_1". It is determined whether or not the flag conversion lottery process of S444 in FIG. 112 has been won (S554).

In S554, when the main CPU 101 determines that the internal winning combination does not correspond to the sub-flag EX "triple chili lip" (when the determination in S554 is NO), the main CPU 101 ends the processing at the start during CT, and at the same time, The state-specific control process (see FIG. 105) also ends.

On the other hand, in S554, when the main CPU 101 determines that the internal winning combination corresponds to the sub-flag EX "triple chili lip" (when the determination in S554 is YES), the main CPU 101 sets the value of the CT game number counter. "1" is added (S555). Then, after the processing of S555, the main CPU 101 ends the processing at the start during CT, and also ends the state-specific control processing (see FIG. 105).

Here, returning to the processing of S552 again, when the determination in S552 is NO, the main CPU 101 performs the CT lottery processing during CT (S556). In this process, the main CPU 101 mainly performs an additional lottery for the number of CT sets. The details of the CT lottery process during CT will be described later with reference to FIG. 120 described later.

Next, the main CPU 101 subtracts 1 from the value of the CT game number counter (S557). Next, the main CPU 101 determines whether or not the value of the CT game number counter is "0" (S558).

In S558, when the main CPU 101 determines that the value of the CT game number counter is not "0" (when the determination in S558 is NO), the main CPU 101 ends the CT start processing and state-specific control processing (when the CT game number counter value is not "0"). (See FIG. 105) also ends. On the other hand, in S558, when the main CPU 101 determines that the value of the CT game number counter is "0" (when the determination in S558 is YES), the main CPU 101 determines whether the number of CT sets is "1" or more. (S559).

In S559, when the main CPU 101 determines that the number of CT sets is "1" or more (when the determination in S559 is YES), the main CPU 101 subtracts 1 from the number of CT sets (S560). Next, the main CPU 101 sets the value of the CT game number counter to "8" (S561). Then, after the processing of S561, the main CPU 101 ends the processing at the start during CT, and also ends the state-specific control processing (see FIG. 105).

On the other hand, in S559, when the main CPU 101 determines that the number of CT sets is not "1" or more (when the determination in S559 is NO), the main CPU 101 sets the normal ART in the gaming state of the next game (S562). Then, after the processing of S562, the main CPU 101 ends the processing at the start during CT, and also ends the state-specific control processing (see FIG. 105).

[CT lottery processing during CT]
Next, with reference to FIG. 120, the CT lottery process during CT performed in S556 during the start process during CT (see FIG. 119) will be described. Note that FIG. 120 is a flowchart showing the procedure of CT lottery processing during CT.

First, the main CPU 101 sets the CT lottery table during CT (S571). The CT lottery table during CT set here is the lottery table with the number of sets during CT described in FIG. 56 above, but the CT lottery table during CT actually set on the source program (set during CT). The configuration of the number-added lottery table) will be described later with reference to FIG. 123 described later.

Next, the main CPU 101 performs a table data acquisition process (S572). In this process, the main CPU 101 acquires the address of the lottery table referred to in the CT lottery process during CT. The details of the table data acquisition process will be described later with reference to FIG. 121 described later.

Next, the main CPU 101 performs a 1-byte lottery process (S573). In this process, the main CPU 101 performs an additional lottery of the CT set. The details of the 1-byte lottery process will be described later with reference to FIG. 124 described later.

Next, the main CPU 101 determines whether or not the 1-byte lottery process has been won (S574). In S574, when the main CPU 101 determines that the 1-byte lottery process has not been won (when the determination in S574 is NO), the main CPU 101 ends the CT lottery process during CT and performs the process at the start of CT (FIG. Move to S557 (see 119).

On the other hand, in S574, when the main CPU 101 determines that the 1-byte lottery process has been won (when the determination in S574 is YES), the main CPU 101 adds "1" to the number of CT sets (S575). Then, after the processing of S575, the main CPU 101 ends the CT lottery processing during CT, and shifts the processing to S557 of the processing at the start during CT (see FIG. 119).

[Table data acquisition process]
Next, the table data acquisition process performed in S572 during the CT lottery process during CT (see FIG. 120) will be described with reference to FIGS. 121 to 123. FIG. 121 is a flowchart showing the procedure of the table data acquisition process. Further, FIG. 122 is a diagram showing an example of a source program for executing the table data acquisition process, and FIG. 123 is actually referred to on the source program of the CT lottery process and the table data acquisition process during CT. It is a figure which shows an example of the structure of the CT lottery table in CT (corresponding to the lottery table which added the number of sets in CT explained with FIG. 56). The specific lottery values stored in the CT lottery table during CT shown in FIG. 123 are examples.

In the present embodiment, when the lottery value referred to in the CT lottery process during CT is acquired, the lottery value is stored through the two-step address calculation process (first-step and second-step table data acquisition process). Calculate the address. First, in the first-stage table data acquisition process (processes S582 and S583 described later), a "selection value (1 byte)" associated with the internal winning combination (actually, the sub flag D) is acquired. The selected value is provided for each type of internal winning combination, it is possible to determine whether or not the internal winning combination is a lottery target, and it is possible to specify the placement destination of the lottery table associated with the internal winning combination. Value (relative value) is specified. Further, in the present embodiment, the selection value "0" is defined in advance for the internal winning combination (actually, the sub-flag D) in which the lottery result of the CT lottery processing during CT is non-winning, and the internal winning combination is set to 1. It is treated as "miss" at the time of the table data acquisition process of the stage. Then, in the second stage table data acquisition processing (processing of S585 to S587 described later), an address in which the lottery value of the internal winning combination in which the selection value other than "0" is defined is stored is calculated (lottery table). The address is calculated by adding the relative value (selected value) from the reference address (2 bytes) of.

First, the main CPU 101 refers to the CT lottery selection table during CT (not shown), and addresses the first and second stages of additional selection data for calculating the address of the CT lottery table during CT, and the CT. The number of lottery lottery (twice in this embodiment) is acquired (S581). Next, the main CPU 101 adds the address of the first-stage addition selection data to the address of the CT lottery table during CT to calculate the first-stage selection address (S582).

Next, the main CPU 101 acquires the selection value stored in the calculated first-stage selection address (S583). Next, the main CPU 101 determines whether or not the selected value is "0" (S584).

In S584, when the main CPU 101 determines that the selected value is "0" (when the determination in S584 is YES), the main CPU 101 ends the table data acquisition process and performs the CT lottery process during CT (FIG. 120). (See) to S573.

On the other hand, in S584, when the main CPU 101 determines that the selection value is not "0" (when the determination in S584 is NO), the main CPU 101 adds the selection value to the selection address to obtain the second-stage selection address. Calculate (S585). Next, the main CPU 101 adds the address of the second-stage addition selection data to the second-stage selection address to calculate the selection address (S586).

Next, the main CPU 101 acquires the selection value stored in the selection address calculated in S586, adds the selection value to the selection address, and calculates the address to be referred to in the CT lottery table during CT (S587). .. Then, after the processing of S587, the main CPU 101 ends the table data acquisition processing, and shifts the processing to S573 of the CT lottery processing (see FIG. 120) during CT.

In the present embodiment, the table data acquisition process is performed as described above. Then, the above-mentioned table data acquisition process is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 122.

Among them, in the first stage table data acquisition processing (processing of S581 to S584), the data was stored in the areas from the addresses "dCTCTSTTB" to "dCTCTS_RER-1" in the CT winning lottery table during CT shown in FIG. 123. The table (table selection relative table by winning combination) is referred to. In addition, in the table selection relative table (lottery table selection table) for each winning combination, each combination in which the CT winning is lost (sub-flag D "missing", "cactus", "weak cherry", "strong cherry", "fixed role" , "Triple chili lip"), "0" is stored as the selection value (relative value) described above. Then, in the first stage table data acquisition process (address calculation process), when the selected value is "0", the lottery result is set to "miss" (see the determination process in S584 above).

In the CT-in-CT winning lottery table having the above configuration, in the winning combination table selection relative table referred to in the first stage table data acquisition process, "loss" can be set only by the combination type, so that the lottery table can be set. It is no longer necessary to specify the lottery value for the "lost" role. Therefore, in the present embodiment, it is not necessary to store the lottery value data (“0”) of the “missing” role in the CT winning lottery table during CT, and the capacity of the table area of the main ROM 102 can be saved.

Further, in the process of S587 during the table data acquisition process (process of S585 to S587) in the second stage (when the sub flag D “reach eye lip” is acquired), the CT shown in FIG. 123 is based on the calculated lottery table address. From the medium CT winning lottery table (corresponding to the lottery table with the number of sets added during CT in FIG. 56), the lottery table (starting address "dNMCTTS_RR") used in the normal CT state or the lottery table in the high probability CT state (starting address "dSPCTTS_RR"). ) Is selected.

In the lottery table used in the high-probability CT state, as shown in FIG. 123, a "judgment bit" (judgment data) composed of 1-byte data is stored in the address area next to the start address "dSPCTCTS_RER". In the determination bit, data indicating a range of addresses in which the lottery value to be drawn is stored is stored. As in the example shown in FIG. 123, when the lottery value of the lottery target (high probability CT) is stored only in the next address of the storage area of the "judgment bit" of the lottery table in the high probability CT state, the judgment is made. In the bit storage area, 1-byte data "00000001B" in which "1" is stored only in bit 0 is stored as a determination bit. On the other hand, when the lottery value of the lottery target (high-accuracy CT and normal CT) is stored in the next address and the next address of the storage area of the determination bit as in the lottery table used in the normal CT state, FIG. 123 As shown in the above, 1-byte data “00000011B” in which “1” is stored only in bits 0 and 1 is stored as a determination bit in the determination bit storage area. When such a determination bit is provided, it is not necessary to store lottery value data that is not subject to lottery in the area of the address where the bit data is "0" in the determination bit in the lottery table.

Further, in the lottery table used in the high-probability CT state, as shown in FIG. 123, the lottery value of the high-probability CT win is stored in the address "dSPCTCTS_RER + 2" next to the "judgment bit", and is used as the lottery value of the high-probability CT win. The data specified in the address "cABS_HIT" is stored. In the present embodiment, the data defined in this address "cABS_HIT" is data indicating winning confirmation (100% winning) (hereinafter, referred to as "confirmed data"). Further, in the present embodiment, since it is not necessary to provide the lottery value data (“0”) for loss in the CT winning lottery table during CT, as shown in FIG. 123, the definite data defined in the address “cABS_HIT”. Can be specified as "0". That is, in the CT winning lottery table during CT having the above configuration, the lottery value "0" can be used as definite data.

As described in the lottery table for adding the number of sets during CT in FIG. 56, in the present embodiment, the “high probability CT winning” is always determined in the lottery for adding the number of sets during CT in the high probability CT state. Therefore, in the present embodiment, on the source program, the confirmed data can be stored as the lottery value of the high-probability CT win in the CT winning lottery table during CT shown in FIG. 123.

Like the lottery table in the second stage (when the sub-flag D “reach eye lip” is acquired) described above, the lottery target combination and the non-lottery target combination (sub flag D) of the CT lottery are determined by the value of each bit data constituting the determination bit. ) Is determined, so that it is not necessary to store the lottery value data (loss data) of the winning combination that is not subject to the lottery in the table. Further, the lottery value "0" can be used as the definite data in which the winning probability of the lottery target combination is 100%. From these facts, in this embodiment, the capacity of the CT winning lottery table during CT (the lottery table with the number of sets added during CT) can be compressed, and the free space can be secured (increased) in the main ROM 102. , It will be possible to improve the playability by utilizing the increased free space. Further, in the present embodiment, an example in which this technique is used in the CT winning process during CT has been described, but the present invention is not limited to this, and the ART lottery (see FIG. 116) and the number of ART games added lottery (see FIG. 118). ), CT lottery described later (see FIG. 163 described later), pullback lottery of CZ described later (see FIG. 166 described later), and the like.

[1 byte lottery processing]
Next, with reference to FIGS. 124 and 125, the 1-byte lottery process performed in S573 during the CT lottery process during CT (see FIG. 120) will be described. FIG. 124 is a flowchart showing the procedure of the 1-byte lottery process. Further, FIG. 125 is a diagram showing an example of a source program for executing the 1-byte lottery process.

First, the main CPU 101 sets a 1-byte random number value (0 to 255: soft latch random number of the random number register 4 of the random number circuit 110) stored in the random number storage area (not shown) in the main RAM 103 for CT lottery during CT. Set (S591). Next, the main CPU 101 obtains lottery determination data (determination bits in the lottery table defined in the second stage of FIG. 123) from the CT lottery table during CT based on the address calculated in S587 during the table data acquisition process. Acquire (S592). Further, in this process, the main CPU 101 sets the number of determination bits "8" as the initial value of the number of lottery.

Next, the main CPU 101 determines whether or not the lottery determination data is a lottery target (S593). In this determination process, the main CPU 101 refers to the bit data in the determination bit associated with the current number of lottery, and if the bit data is "1", it determines that the lottery target is selected. In the present embodiment, the bits 0 to 7 in the determination bit are associated with the number of lottery "8" to "1", respectively.

In S593, when the main CPU 101 determines that the lottery determination data is not the lottery target (when the determination in S593 is NO), the main CPU 101 performs the process of S599 described later. On the other hand, in S593, when the main CPU 101 determines that the lottery determination data is the lottery target (when the determination in S593 is YES), the main CPU 101 acquires the lottery value from the CT lottery table during CT (S594).

Next, the main CPU 101 determines whether or not the lottery value is "0" (winning confirmation data) (S595).

In S595, when the main CPU 101 determines that the lottery value is "0" (when the determination in S595 is YES), the main CPU 101 ends the 1-byte lottery process, and performs the CT lottery process during CT (FIG. 120). (See) to S574. On the other hand, in S595, when the main CPU 101 determines that the lottery value is not "0" (when the determination in S595 is NO), the main CPU 101 performs a CT lottery (additional lottery of the number of CT sets) process (S596). Specifically, the main CPU 101 subtracts a lottery value from a random number value (1 byte random value), and uses the subtraction result as a random number value.

Next, the main CPU 101 determines whether or not the CT lottery of S596 has been won (S597). In the CT lottery of S596, the main CPU 101 determines that the winning result is obtained when the subtraction result of S596 is "0" or less (when a so-called "digit shift" occurs).

In S597, when the main CPU 101 determines that the CT lottery has been won (when the determination in S597 is YES), the main CPU 101 ends the 1-byte lottery process, and the process is the CT lottery process during CT (see FIG. 120). Move to S574. On the other hand, in S597, when the main CPU 101 determines that the CT lottery has not been won (when the determination in S597 is NO), the main CPU 101 refers to the lottery value storage address (lottery address) in the CT lottery table during CT. Is updated to the next lottery address (S598).

After the processing of S598 or when the determination in S593 is NO, the main CPU 101 subtracts 1 from the number of lottery (S599). Next, the main CPU 101 determines whether or not the number of lottery is "0" (S600).

In S600, when the main CPU 101 determines that the number of lottery is not "0" (when the determination in S600 is NO), the main CPU 101 returns the process to S593 and repeats the processes after S593. On the other hand, in S600, when the main CPU 101 determines that the number of lottery is "0" (when the determination in S600 is YES), the main CPU 101 ends the 1-byte lottery process, and performs the CT lottery process during CT (CT lottery process). (See FIG. 120).

In the present embodiment, the 1-byte lottery process is performed as described above. The 1-byte lottery process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 125.

In the random number acquisition process of S591 during the 1-byte lottery process, as shown in FIG. 125, the "LDQ" instruction, which is an instruction code dedicated to the main CPU 101 that specifies an address using the Q register (extension register), is issued on the source program. Used. Therefore, in the present embodiment, even in the 1-byte lottery process, the main ROM 102, the main RAM 103, and the memory map I / O are accessed by the direct value by using the instruction code using the Q register (extension register). Therefore, the instruction code related to the address setting can be omitted, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Processing at start during BB]
Next, with reference to FIG. 126, the BB start-time processing performed in S415 during the state-specific control processing (see FIG. 105) will be described. Note that FIG. 126 is a flowchart showing the procedure of the start processing during BB.

First, the main CPU 101 refers to the bonus lottery table for adding the number of ART games (see FIG. 59), and performs the lottery process for adding the number of ART games based on the internal winning combination (S611). Next, the main CPU 101 determines whether or not the additional lottery has been won (S612).

In S612, when the main CPU 101 determines that the additional lottery has not been won (when the determination in S612 is NO), the main CPU 101 ends the BB start processing and also performs the state-specific control processing (see FIG. 105). finish. On the other hand, in S612, when the main CPU 101 determines that the additional lottery has been won (when the determination in S612 is YES), the main CPU 101 adds the winning result (the number of additional games) to the ART end game number counter (S613). ..

Next, the main CPU 101 determines whether or not the number of ART sets is "0" (S614). When the main CPU 101 determines in S614 that the number of ART sets is not "0" (when the determination in S614 is NO), the main CPU 101 ends the BB start processing and the state-specific control processing (see FIG. 105). ) Also ends.

On the other hand, in S614, when the main CPU 101 determines that the number of ART sets is "0" (when the determination in S614 is YES), the main CPU 101 adds "1" to the number of ART sets (S615). Then, after the processing of S615, the main CPU 101 ends the processing at the start during BB, and also ends the state-specific control processing (see FIG. 105).

[Pull-in priority storage process]
Next, with reference to FIGS. 127 and 128, the pull-in priority storage process performed in S212 in the main flow (see FIG. 82) will be described. FIG. 127 is a flowchart showing the procedure of the attraction priority storage process. Further, FIG. 128 is a diagram showing an example of a source program for executing the processes of S625 and S626 described later during the attraction priority storage process.

First, the main CPU 101 sets "3" to the number of search reels (S621). Next, the main CPU 101 performs a pull-in priority table selection process (S622). In this process, the pull-in priority table (see FIG. 27) is selected based on the internal winning combination and the operation stop button.

Next, the main CPU 101 performs a pull-in priority storage area selection process (S623). In this process, the pull-in priority data storage area of the reel to be searched is selected. Next, the main CPU 101 sets "20" as the number of symbol checks (number of times) (S624).

Next, the main CPU 101 performs a symbol code acquisition process (S625). In this process, the symbol code is acquired by referring to the winning operation flag storage area and the symbol code storage area corresponding to the number of symbol checks. The details of the symbol code acquisition process will be described later with reference to FIG. 129 described later.

Next, the main CPU 101 performs a logical product calculation process (S626). In this process, the main CPU 101 performs a process of generating the winning operation flag data. The details of the logical product calculation process will be described later with reference to FIG. 134 described later.

Next, the main CPU 101 performs a pull-in priority acquisition process (S627). In this process, in the main CPU 101, the bit is set to "1" in the winning operation flag (winning combination) storage area (see FIGS. 28 to 30), and the bit is set to "1" in the hit request flag storage area. With reference to the attraction priority table (see FIG. 27), the attraction priority data is acquired for the winning combination. The details of the pull-in priority acquisition process will be described later with reference to FIGS. 135 and 136 described later.

Next, the main CPU 101 stores the acquired attraction priority data in the attraction priority data storage area (not shown) in the main RAM 103 (S628). At this time, the attraction priority data is stored in the attraction priority data storage area so that the value of each priority and the bit of the storage area correspond to each other.

The pull-in priority data storage area is provided with a priority data storage area for each type of main reel. In each attraction priority data storage area, the attraction priority data determined according to each symbol position "0" to "19" of the corresponding main reel is stored. In the present embodiment, by referring to this attraction priority data storage area, it is searched whether or not a more appropriate number of sliding pieces exists in addition to the number of sliding pieces determined based on the stop table.

The content of the priority pull-in data stored in the pull-in priority data storage area differs depending on the type of the pull-in priority table number in the pull-in priority table referred to when determining the pull-in priority data. Further, the pull-in priority data indicates that the larger the value, the higher the priority. By referring to the pull-in priority data, it is possible to relatively evaluate the priority among the symbols arranged on the peripheral surface of the main reel. That is, the symbol whose highest value is determined as the attraction priority data is the symbol having the highest priority. Therefore, it can be said that the pull-in priority data indicates the order between the symbols arranged on the peripheral surface of the main reel. If there are a plurality of symbols having the same value of the pull-in priority data, one symbol is determined according to the priority order defined by the priority order table.

Next, the main CPU 101 updates the pull-in priority storage area (S629). In this process, the main CPU 101 sets a pull-in priority data storage area for the next check symbol. Next, the main CPU 101 subtracts 1 from the number of symbol checks (S630). Next, the main CPU 101 determines whether or not the number of symbol checks is "0" (S631).

In S631, when the main CPU 101 determines that the number of symbol checks is not "0" (when the determination in S631 is NO), the main CPU 101 returns the process to the process of S625 and repeats the processes after S625. On the other hand, in S631, when the main CPU 101 determines that the number of symbol checks is "0" (when the determination in S631 is YES), the main CPU 101 performs a search target reel change process (S632).

Next, the main CPU 101 subtracts 1 from the number of search reels (S633). Next, the main CPU 101 determines whether or not the number of search reels is "0", that is, whether or not the above-mentioned series of processes has been performed on all the main reels (S634).

In S634, when the main CPU 101 determines that the number of search reels is not "0" (when the determination in S634 is NO), the main CPU 101 returns the process to the process of S622 and repeats the processes after S622. On the other hand, in S634, when the main CPU 101 determines that the number of search reels is "0" (when the determination in S634 is YES), the main CPU 101 ends the attraction priority storage process and performs the process in the main flow (FIG. FIG. (Refer to 82), move to S213.

In the present embodiment, the attraction priority storage process is performed as described above. The processing of S625 and S626 during the above-described attraction priority storage processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 128.

Among them, the logical product calculation process of S626 is performed by the main CPU 101 executing the source code "CALLF SB_DAND_00" in FIG. 128. The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_DAND_00" in FIG. 128 is executed, processing is performed at the address specified by "SB_DAND_00". The jump is made and the logical product calculation process is started.

[Design code acquisition process]
Next, the symbol code acquisition process performed in S625 during the attraction priority storage process (see FIG. 127) will be described with reference to FIGS. 129 to 133. FIG. 129 is a flowchart showing the procedure of the symbol code acquisition process, and FIG. 130 is a diagram showing an example of a source program for executing the symbol code acquisition process. FIG. 131A is a diagram showing an example of the configuration of the first reel (left reel) symbol arrangement table actually referred to on the source program of the symbol code acquisition process, and FIG. 131B is a diagram showing a first reel symbol arrangement table set. It is a figure which shows an example of the structure of the symbol correspondence winning operation table which is sometimes referred to. FIG. 132A is a diagram showing an example of the configuration of the second reel (middle reel) symbol arrangement table actually referred to on the source program of the symbol code acquisition process, and FIG. 132B is a diagram of the second reel symbol arrangement table set. It is a figure which shows an example of the structure of the symbol correspondence winning operation table which is sometimes referred to. Further, FIG. 133A is a diagram showing an example of the configuration of the third reel (right reel) symbol arrangement table actually referred to on the source program of the symbol code acquisition process, and FIG. 133B is a diagram showing the third reel symbol arrangement. It is a figure which shows an example of the structure of the symbol correspondence winning operation table which is referred at the time of table setting.

First, the main CPU 101 clears the winning operation flag storage area (S641). In this process, the main CPU 101 sets "0" in all the storage areas in the winning operation flag storage area (see FIGS. 28 to 30). Next, the main CPU 101 sets the first reel symbol arrangement table (see FIG. 131A) (S642).

Next, the main CPU 101 determines whether or not the first reel (left reel 3L) is stopped (S643).

In S643, when the main CPU 101 determines that the first reel (left reel 3L) is stopped (when the determination in S643 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, in S643, when the main CPU 101 determines that the first reel (left reel 3L) is not stopped (when the determination in S643 is NO), the main CPU 101 uses the second reel symbol arrangement table (see FIG. 132A). Set (S644). In this process, the first reel symbol arrangement table set in the process of S642 is overwritten by the second reel symbol arrangement table.

Next, the main CPU 101 determines whether or not the second reel (middle reel 3C) is stopped (S645).

In S645, when the main CPU 101 determines that the second reel (middle reel 3C) is stopped (when the determination in S645 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, in S645, when the main CPU 101 determines that the second reel (middle reel 3C) is not stopped (when the determination in S645 is NO), the main CPU 101 uses the third reel symbol arrangement table (see FIG. 133A). Set (S646). In this process, the second reel symbol arrangement table set in the process of S644 is overwritten by the third reel symbol arrangement table.

After the processing of S646, or when the determination of S643 or S645 is YES, the main CPU 101 performs the symbol check processing at the time of executing the stop operation on the reel to be stopped controlled, and corresponds to the symbol corresponding to the symbol acquired by the symbol check processing. Acquire the winning operation table (S647). For example, when the first reel (left reel 3L) is stopped and the symbol located on the effective line during the stop operation is "white 7", the main CPU 101 has the address "dR1_SVN1" to the address "dR1_SVN2" in FIG. 131B. The start address of the symbol-corresponding winning operation table specified in the block in the range of -1 ”is acquired.

Next, the main CPU 101 sets the winning operation flag storage area (S648). Next, the main CPU 101 performs the compressed data storage process described with reference to FIG. 102 (S649). In this process, the main CPU 101 mainly performs a process of transferring (expanding) the winning operation flag data stored in the symbol-corresponding winning operation table to the corresponding storage area in the winning operation flag storage area.

For example, when the first reel (left reel 3L) is stopped and the symbol located on the effective line during the stop operation is "white 7", the symbol combinations (combinations) that can be won are shown in FIGS. 28 to 28 to FIG. As shown in 30, the combination names "C_2nd_A_01", "C_2nd_A_01" and "C_SP1_01" defined in the second storage area, and the combination names "C_9 sheets C_01" to "C_9 sheets C_03" defined in the third storage area, "C_9 sheets C_07" to "C_9 sheets C_09" and "C_9 sheets E_01", combination names defined in the fourth storage area "C_RB role A_01", "C_RB role A_02", "C_RB role B_01" to "C_RB role B_04" , "C_RB role C_01" and "C_RB role C_02", combination names defined in the sixth storage area "C_reach eye lip C_01" to "C_reach eye lip C_03", "C_reach eye lip D_01", "C_ Reach eye lip D_02 "and" C_reach eye lip E_01 ", and the combination name" C_BB1 "defined in the tenth storage area.

In this case, the storage destination of the first block (the 0th to 7th storage areas) of the winning operation flag data stored in the symbol-corresponding winning operation table is stored in the address "dR1_SVN1 + 1" in the table shown in FIG. 131B. It is designated by the 1-byte designated data "01011100B" (see the comment "storage area +2, +3, +4, +6" column in FIG. 131B). Further, the storage destination of the second block (8th to 11th storage areas) of the winning operation flag data stored in the symbol-corresponding winning operation table is stored in the address "dR1_SVN1 + 6" in the table shown in FIG. 131B. It is designated by the 1-byte designated data "10000000B" (see the comment "storage area +10" column in FIG. 131B).

In the present embodiment, the bits 0 to 7 of the designated data of the first block are bits for designating the 0th to 7th storage areas of the first block as storage destinations, respectively, and the designated data of the second block. Bits 0 to 3 are bits that specify the 8th to 11th storage areas of the second block as storage destinations, respectively. Then, in the 1-byte designated data of each block, "1" is stored in the bit corresponding to the storage area in the winning operation flag storage area, which is the storage destination of the winning operation flag data.

Therefore, for example, when the first reel (left reel 3L) is stopped and the symbol located on the effective line during the stop operation is "white 7", the address in the table shown in FIG. 131B in the processing of S649. The winning operation flag data "00010000B" or "00000100B" stored in "dR1_SVN1 + 2" is transferred from the symbol-corresponding winning operation table to the second storage area in the winning operation flag storage area, and stored in the address "dR1_SVN1 + 3". The winning operation flag data "00100000B" or "00000100B" is transferred from the symbol-corresponding winning operation table to the third storage area in the winning operation flag storage area. Further, in this case, in the process of S649, the winning operation flag data "10000000B", "01000000B" or "001000000B" stored in the address "dR1_SVN1 + 4" in the table shown in FIG. 131B is won from the symbol-corresponding winning operation table. The winning operation flag data "0010000B", "00010000B" or "00001000B" transferred to the fourth storage area in the operation flag storage area and stored at the address "dR1_SVN1 + 5" is stored in the winning operation flag from the symbol-corresponding winning operation table. It is transferred to the sixth storage area in the area. Further, in this case, in the process of S649, the winning operation flag data "10000000B" stored in the address "dR1_SVN1 + 8" in the table shown in FIG. 131B is the tenth in the winning operation flag storage area from the symbol-corresponding winning operation table. Transferred to storage area.

After the processing of S649, the main CPU 101 sets the winning operation flag storage area updated by the compressed data storage processing, sets the symbol code storage area, and the data length of the winning operation flag storage area (12 bytes in this embodiment). Is set (S650). Then, after the processing of S650, the main CPU 101 ends the symbol code acquisition processing, and shifts the processing to S626 of the pull-in priority storage processing (see FIG. 127).

In the present embodiment, the symbol code acquisition process is performed as described above. The symbol code acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 130. Among them, the compressed data storage process of S649 is performed by the main CPU 101 executing the source code "CALLF SB_BTEP_00" in FIG. 130.

The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_BTEP_00" in FIG. 130 is executed, processing is performed at the address specified by "SB_BTEP_00". Jump and start the compressed data storage process. Then, in this compressed data storage process, as described above, the winning operation flag data (compressed data) stored in the symbol-corresponding winning operation flag table of each reel is expanded (copied) in the winning operation flag storage area.

In this embodiment, the data related to the winning is compressed / decompressed by the processing procedure described in S647 to S649 during the symbol code acquisition process described above, and the command code dedicated to the main CPU 101 described above is performed in the process. By using the above, it is possible to improve the efficiency of the compression / decompression processing of the data related to the winning, and it is possible to effectively utilize the limited capacity of the main RAM 103.

Further, in the present embodiment, in the compressed data storage process of S649 during the symbol code acquisition process, the jump destination address “SB_BTEP_00” specified by the “CALLF” command is the compression of S330 during the symbol setting process described with reference to FIG. 98. In the data storage process, it is the same as the jump destination address specified by the "CALLF" instruction. That is, in the present embodiment, the source program for executing the compressed data storage process performed in the symbol code acquisition process is the same as the source program for executing the compressed data storage process performed in the symbol setting process, and is S649 and S330. In both processes, the source program for the compressed data storage process is shared (modularized). In this case, since it is not necessary to separately provide the source program for the compressed data storage process in both the processes S649 and S330, the capacity of the source program (capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Logical product operation processing]
Next, with reference to FIG. 134, for example, the logical product calculation process performed in S626 during the pull-in priority order storage process (see FIG. 127) will be described. FIG. 134 is a flowchart showing the procedure of the AND operation processing. The logical product calculation process shown in FIG. 134 is not only in S626 in the attraction priority storage process (see FIG. 127), but also in S687 in the attraction priority acquisition process (see FIGS. 135 and 136 described later). Is also executed.

In the logical product calculation process executed in S626 during the pull-in priority storage process (see FIG. 127), the two data to be ANDed are stored in the winning operation flag set in S650 during the symbol code acquisition process described above. It is the data of the area and the data of the symbol code storage area. The former data corresponds to the "logical product destination data" described later, and the latter data corresponds to the "logical product source data" described later. Further, in this case, the number of bytes "12" of the data length (12 bytes) set in S650 during the above-mentioned symbol code acquisition process corresponds to the "number of logical products" described later.

On the other hand, in the logical product operation process executed in S687 in the attraction priority acquisition process (see FIGS. 135 and 136 described later), the two data to be ANDed are the hit (retract) request flag storage area. Data and data of the winning operation flag storage area. The former data corresponds to the "logical product destination data" described later, and the latter data corresponds to the "logical product source data" described later. Further, in this case, the number of bytes "1" of the data length (1 byte) of the RT operation combination display flag described in FIG. 137B described later corresponds to the "logical product number" described later.

First, the main CPU 101 acquires the logical product source data (for example, the data of the symbol code storage area) (S661). Next, the main CPU 101 performs a logical product operation of the logical product source data and the logical product destination data (for example, data in the winning operation flag storage area), and saves the calculation result as the logical product destination data (S662).

Next, the main CPU 101 adds 1 to the address of the logical product source data to be acquired (S663). Next, the main CPU 101 adds 1 to the address of the logical product destination data to be referred to (S664).

Next, the main CPU 101 subtracts 1 from the number of logical products (S665). Next, the main CPU 101 determines whether or not the number of logical products is "0" (S666).

In S666, when the main CPU 101 determines that the number of logical products is not "0" (when the determination in S666 is NO), the main CPU 101 returns the process to the process of S661 and repeats the processes after S661. On the other hand, in S666, when the main CPU 101 determines that the number of logical products is "0" (when the determination in S666 is YES), the main CPU 101 ends the logical product calculation process and stores the process, for example, in the pull-in priority order. The process moves to S627 of the process (see FIG. 127).

[Pull-in priority acquisition process]
Next, the attraction priority acquisition process performed in S627 during the attraction priority storage process (see FIG. 127) will be described with reference to FIGS. 135 to 138. It should be noted that FIGS. 135 and 136 are flowcharts showing the procedure of the attraction priority acquisition process. FIG. 137A is a diagram showing an example of a source program for executing the process of S680 to S683 described later during the attraction priority acquisition process, and FIG. 137B shows the process of S686 described later during the attraction priority acquisition process. FIG. 137C is a diagram showing an example of a source program for execution, and FIG. 137C is a diagram showing an example of a source program for executing the process of S687 described later during the pull-in priority acquisition process. Further, FIG. 138 is a diagram showing an example of the configuration of the attraction priority table that is actually referred to on the source program of the attraction priority acquisition process.

First, the main CPU 101 determines whether or not it is time to check the right reel 3R (specific display column) (S671).

When the main CPU 101 determines in S671 that it is not the time to check the right reel 3R (when the determination in S671 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S671, when the main CPU 101 determines that it is time to check the right reel 3R (when the determination in S671 is YES), the main CPU 101 "ANY combination" in the symbol combination (winning combination) related to the internal winning combination. It is determined whether or not (a combination of predetermined symbols) is included (S672). The "ANY combination" here means a combination in which the winning is confirmed regardless of at least the stop symbol of the right reel 3R (at least the winning combination in which the stop symbol of the right reel 3R is an arbitrary symbol).

In S672, when the main CPU 101 determines that the symbol combination related to the internal winning combination does not include the "ANY combination" (when the determination in S672 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S672, when the main CPU 101 determines that the symbol combination related to the internal winning combination includes the "ANY combination" (when the determination in S672 is YES), the main CPU 101 determines that the "ANY combination" in the winning operation flag storage area. The storage area corresponding to the "combination" is masked (S673). Specifically, the main CPU 101 sets "1" in the bit corresponding to the "ANY combination" in the winning operation flag storage area.

After the processing of S673, or when S671 or S672 is determined to be NO, the main CPU 101 sets "1" to the address of the last storage area as the address of the winning operation flag storage area (see FIGS. 28 to 30). The added address is set, the stop prohibition data is set, and the winning operation flag data length (data length of the winning operation flag storage area: 12 bytes in this embodiment) is set (S674). Next, the main CPU 101 acquires the value of the stock button operation counter and the stop button operation state (S675). The stop button operation counter is a counter for managing the number of stop buttons for which a stop operation is detected. Further, the operation stop button operation state is acquired by referring to the operation stop button storage area (see FIG. 33).

Next, the main CPU 101 subtracts (updates -1) the address of the set winning operation flag storage area by 1 (S676). Next, the main CPU 101 generates hit request flag data from the set winning operation flag storage area and the corresponding hit request flag storage area (see FIGS. 28 to 30), and the generated hit request flag data. The prohibited winning operation position is generated based on (S677).

Next, the main CPU 101 determines whether or not the stop operation position is the prohibited winning operation position (S678).

In S678, when the main CPU 101 determines that the stop operation position is not the prohibited winning operation position (when the determination in S678 is NO), the main CPU 101 performs the process of S684 described later. On the other hand, in S678, when the main CPU 101 determines that the stop operation position is the prohibited winning operation position (when the determination in S678 is YES), the value of the stop button operation counter of the main CPU 101 is the value of the third stop. Whether or not it is determined (S679).

In S679, when the main CPU 101 determines that the value of the stop button operation counter is the value of the third stop (when the determination in S679 is YES), the main CPU 101 performs the process of S705 described later. On the other hand, in S679, when the main CPU 101 determines that the value of the stop button operation counter is not the value of the third stop (when the determination in S679 is NO), the value of the stop button operation counter of the main CPU 101 is the second stop. It is determined whether or not it is a value (S680).

In S680, when the main CPU 101 determines that the value of the stop button operation counter is not the value of the second stop (when the determination in S680 is NO), the main CPU 101 performs the process of S684 described later. On the other hand, in S680, when the main CPU 101 determines that the value of the stop button operation counter is the value of the second stop (when the determination in S680 is YES), whether or not the main CPU 101 is after the right reel 3R is stopped. (S681).

When the main CPU 101 determines in S681 that the right reel 3R has been stopped (when the determination in S681 is YES), the main CPU 101 performs the process of S684 described later. On the other hand, in S681, when the main CPU 101 determines that the right reel 3R has not been stopped (when the determination in S681 is NO), the main CPU 101 has a flag that the hit request flag may be interfered with by the "ANY combination". It is determined whether or not (whether or not "ANY combination" is not included in the symbol combination (winning combination) related to the internal winning combination) (S682).

In S682, when the main CPU 101 determines that the hit request flag is not a flag that may be interfered with by the "ANY combination" (when the determination in S682 is YES), the main CPU 101 performs the process of S684 described later. On the other hand, in S682, when the main CPU 101 determines that the hit request flag is a flag that may be interfered with by the "ANY combination" (when the determination in S682 is NO), the main CPU 101 currently checks "ANY". It is determined whether or not it is time to check the hit request flag including the "combination" (S683).

In S683, when the main CPU 101 determines that the current check is the time to check the hit request flag including the "ANY combination" (when the determination in S683 is YES), the main CPU 101 performs the process of S705 described later.

On the other hand, in S683, when the main CPU 101 determines that the current check is not at the time of checking the hit request flag including "ANY combination" (when S683 is NO determination), when S678 or S680 is NO determination, or S681. Alternatively, when the determination in S682 is YES, the main CPU 101 subtracts 1 from the winning operation flag data length (S684). Next, the main CPU 101 determines whether or not the winning operation flag data length is “0” (S685).

In S685, when the main CPU 101 determines that the winning operation flag data length is not "0" (when the determination in S685 is NO), the main CPU 101 returns the processing to the processing of S676 and repeats the processing after S676.

On the other hand, in S685, when the main CPU 101 determines that the winning operation flag data length is "0" (when the determination in S685 is YES), the main CPU 101 performs a stop control pull-in request flag setting process (S686). .. This process is performed by sequentially executing each process specified in the source program of FIG. 137B by the main CPU 101. Therefore, in this process, the AND operation process described with reference to FIG. 134 is performed. In the logical product operation process executed in the process of S686, as described above, the data of the hit (pull-in) request flag storage area is set in the "logical product destination data", and the data of the winning operation flag storage area is set. It is set in the "logical product source data", and the number of bytes "1" of the data length (1 byte) of the RT operation combination display flag is set in the "logical product count". The RT operation combination display flag is a storage area in which the symbol combination related to the RT transition is defined in the winning operation flag storage area, and in the present embodiment, only the storage area 11 is defined as shown in FIGS. 28 to 30. Become.

Next, the main CPU 101 refers to the pull-in priority table address storage area and acquires the pull-in priority table (S687). This process is performed by sequentially executing each process specified in the source program of FIG. 137C by the main CPU 101. Therefore, in this process, the initial value "1 (001H)" of the pull-in priority data is set to the currently set address, and the start address shown in FIG. 138 is "dPLVLTB00" to "dPLVLTB05". The pull-in priority table stored in one of the blocks is acquired. The pull-in priority tables stored in the blocks whose start addresses are "dPLVLTB00" to "dPLVLTB05" shown in FIG. 138 are the pull-in priority table numbers "00" to "05" shown in FIG. 27, respectively. Corresponds to the pull-in priority table.

Next, the main CPU 101 determines whether or not the data in the pull-in priority table stored at the currently set address is the end code (000H) (S688).

In S688, when the main CPU 101 determines that the data in the pull-in priority table stored at the currently set address is the end code (when the determination in S688 is YES), the main CPU 101 uses S705, which will be described later. Process. On the other hand, in S688, when the main CPU 101 determines that the data in the pull-in priority table stored at the currently set address is not the end code (when the determination in S688 is NO), the main CPU 101 operates the winning operation. The flag storage area is set (S689).

Next, the main CPU 101 acquires the attraction priority data from the attraction priority table based on the currently set address (S690). Next, the main CPU 101 sets the block counter of the pull-in priority table (S691). In the present embodiment, in this process, the main CPU 101 sets "2" to the value of the block counter in the pull-in priority table.

Next, the main CPU 101 sets the number of checks of the attraction priority table, and adds 1 (+1 update) to the address of the attraction priority table to be referred to (S692). In the present embodiment, in this process, the main CPU 101 sets the number of checks in the pull-in priority table to "8" (the number of bits of check data defined in the pull-in priority table shown in FIG. 138).

Next, the main CPU 101 acquires check data (see FIG. 138) based on the updated address of the pull-in priority table, and extracts check bits from the check data (S693). In the present embodiment, the check bit extracted here corresponds to bit 0 of the check data. For example, in the processing of S690, when the attraction priority data "03EH" is acquired from the attraction priority table defined in the block whose start address is "dPLVLTB00", in the processing of S693, "10001000B" is used as the check data. It is acquired and "0" is extracted as the value of the check bit.

Next, the main CPU 101 determines whether or not the value of the extracted check bit is “1” (S694).

In S694, when the main CPU 101 determines that the value of the extracted check bit is not "1" (when the determination in S694 is NO), the main CPU 101 performs the process of S699 described later. On the other hand, in S694, when the main CPU 101 determines that the value of the extracted check bit is "1" (when the determination in S694 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referred to. (+1 update), and based on the updated address, the determination data (“flag determination data” in FIG. 138) is acquired from the pull-in priority table (S695).

Next, the main CPU 101 determines whether or not the currently acquired winning operation flag data is the determination target based on the determination data acquired in S695 (S696). In this process, the main CPU 101 compares the currently acquired winning operation flag data with the determination data, determines whether or not the former corresponds to the latter, and the former corresponds to the latter. In that case, it is determined that the currently acquired winning operation flag data is the determination target.

In S696, when the main CPU 101 determines that the winning operation flag data is not the determination target (when the determination in S696 is NO), the main CPU 101 performs the process of S699 described later. On the other hand, in S696, when the main CPU 101 determines that the winning operation flag data is the determination target (when the determination in S696 is YES), the main CPU 101 updates the attraction priority data (S697). In this process, the main CPU 101 updates (overwrites) the currently set attraction priority data with the attraction priority data associated with the determination data acquired in S697.

Next, the main CPU 101 updates the check data (S698). In this process, the main CPU 101 shifts the check data by one bit to the right (direction from bit 7 to bit 0). In this process, "0" is set in the bit 7 of the check data after the shift.

After the processing of S698, or when S694 or S696 is determined to be NO, the main CPU 101 determines whether or not there is a bit to be checked (a bit in which "1" is set) in the check data (S699).

In S699, when the main CPU 101 determines that there is no bit to be checked in the check data (when the determination in S699 is NO), the main CPU 101 performs the process of S702 described later. On the other hand, in S699, when the main CPU 101 determines that the check data has a bit to be checked (when the determination in S699 is YES), the main CPU 101 adds 1 to the address of the winning operation flag storage area to be checked (+1 update). ), And the number of checks is subtracted by 1 (S700).

Next, the main CPU 101 determines whether or not the number of checks is "0" (S701). When the main CPU 101 determines in S701 that the number of checks is not "0" (when the determination in S701 is NO), the main CPU 101 returns the process to the process of S698 and repeats the processes after S698.

On the other hand, in S701, when the main CPU 101 determines that the number of checks is "0" (when the determination in S701 is YES), the main CPU 101 sets the number of checks to the address of the winning operation flag storage area currently referred to. The initial value "8" is added to update the address of the winning operation flag storage area, and the value of the block counter is subtracted by 1 (S702). Next, the main CPU 101 determines whether or not the value of the block counter is "0" (S703).

In S703, when the main CPU 101 determines that the value of the block counter is not "0" (when the determination in S703 is NO), the main CPU 101 returns the process to the process of S692 and repeats the processes after S692.

On the other hand, in S703, when the main CPU 101 determines that the value of the block counter is "0" (when the determination in S703 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referred to (+1 update). ) (S704). For example, when the currently referenced pull-in priority table is the pull-in priority table specified in the block whose start address is "dPLVLTB00", this process causes the refer-in pull-in priority table to have a start address of "dPLVLTB00". It is changed to the pull-in priority table specified in the block which is "dPLVLTB01". Then, after the processing of S704, the main CPU 101 returns the processing to the processing of S688, and repeats the processing after S688.

Here, returning to the processing of S679, S683 or S688 again, if S679, S683 or S688 is a YES determination, the main CPU 101 uses the attraction order data set at this time as the final attraction priority data. Set (S705). If S679 or S683 is YES, the main CPU 101 sets "0 (00H)" as the final pull-in priority data. In this case, since the end code is assigned to the pull-in priority data "0 (00H)", no pull-in data (stop prohibition) is set. Then, after the processing of S705, the main CPU 101 ends the attraction priority acquisition process, and shifts the process to S628 of the attraction priority storage process (see FIG. 127).

In the present embodiment, the attraction priority acquisition process is performed as described above. The pull-in priority handling process of the “ANY combination” of S680 to S683 during the above-mentioned pull-in priority acquisition process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 137A. Be told. Among them, for example, the determination process of S683 is executed by a "JCP" instruction (predetermined determination instruction) on the source program. The "JCP" instruction is an instruction that executes an operation equivalent to a comparison instruction, and is an instruction code dedicated to the main CPU 101.

When, for example, the source code "JCP cc, A, n, e" is executed on the source program, the contents (stored data) of the A register are compared with the integer n, and the comparison result is the condition of cc. If so, the process is jumped to the address specified by e. In the "cc condition" of the "JCP" instruction, one of the carry flag state and the zero flag state in the flag register F is specified (see FIG. 11). For example, if "C" is specified for cc, the condition of cc means that the carry flag is "1" (on state), and if "NC" is specified for cc, the condition of cc. Means that the carry flag is "0" (off state). Further, for example, if "Z" is specified for cc, the condition of cc means that the zero flag is "1" (on state), and if "NZ" is specified for cc, the condition of cc is The condition means that the zero flag is "0" (off state).

As shown in FIG. 137A, when the "JCP" instruction is used on the source program of the pull-in priority correspondence process of the "ANY combination", the instruction related to the address setting can be omitted (the instruction related to the address setting is separately provided). Therefore, it is possible to improve the processing efficiency of the pull-in priority handling process of the "ANY combination" and reduce the capacity of the source program (the capacity used by the main ROM 102).

Further, the stop control pull-in request flag setting process of S686 during the above-mentioned pull-in priority acquisition process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 137B. In the stop control pull-in request flag setting process of S686, as shown in FIG. 137B, the "LDQ" instruction and the "CALLF" that specify the address using the Q register (extension register), which is the instruction code dedicated to the main CPU 101. The instruction is used.

Therefore, by using the "LDQ" instruction using the Q register (extension register) in the stop control pull-in request flag setting process of S686, the main ROM 102, the main RAM 103, and the memory map I / O are accessed by the direct value. can do. In this case, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced. Further, the "CALLF" instruction is a 2-byte instruction code as described above. Therefore, by using these main CPU 101 dedicated instruction codes in the stop control pull-in request flag setting process, the efficiency of the process can be improved and the limited capacity of the main RAM 103 can be effectively utilized. ..

Further, in the present embodiment, in the stop control pull-in request flag setting process of S686 during the priority pull-in order acquisition process, the jump destination logical product operation address “SB_DAND_00” specified by the “CALLF” instruction is the above-mentioned FIG. 127. It is the same as the jump destination address specified by the "CALLF" instruction in the logical product operation processing of S626 during the attraction priority storage processing described in (see FIG. 128). That is, in the present embodiment, the source program for executing the AND operation processing performed in the stop control pull-in request flag setting process of S686 during the priority pull-in order acquisition process is the logic performed in S626 during the pull-in priority storage process. It is the same as the source program for executing the AND operation, and the source program for the AND operation is shared (modularized) in both the S686 and S626 processes. In this case, in both the processes of S686 and S626, it is not necessary to separately provide the source program for the AND operation processing, so that the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the acquisition process of the attraction priority table (see FIG. 138) of S687 during the above-mentioned attraction priority acquisition process, the main CPU 101 sequentially executes each source code defined by the source program of FIG. 137C. Will be done. Then, in the acquisition process of the pull-in priority table in S687, as shown in FIG. 137C, the "LDQ" instruction that specifies the address using the Q register (extension register), which is the instruction code dedicated to the main CPU 101, is used.

Therefore, even in the acquisition process of the pull-in priority table of S687, the instruction related to the address setting can be omitted on the source program by using the "LDQ" instruction. As a result, the efficiency of the acquisition process of the pull-in priority table can be improved, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced.

As described above, in the various processes during the priority attraction order acquisition process of the present embodiment, the various instruction codes dedicated to the main CPU 101 described above are appropriately used to improve the efficiency of the corresponding processes and reduce the capacity of the source program. doing. As a result, in the present embodiment, it is possible to improve the efficiency of the program processing speed of the main control circuit 90 and reduce the capacity, and it is possible to improve the playability by utilizing the free area corresponding to the reduced capacity. It becomes.

[Reel stop control process]
Next, the reel stop control process performed in S213 in the main flow (see FIG. 82) will be described with reference to FIGS. 139 to 141. Note that FIG. 139 is a flowchart showing the procedure of the reel stop control process. FIG. 140 is a diagram showing an example of a source program for executing the processes of S711 to S716 described later during the reel stop control process, and FIG. 141 is a diagram showing the process of S726 described later during the reel stop control process. It is a figure which shows an example of the source program for this.

First, the main CPU 101 performs a reel stop enable signal OFF process (S711). In this process, the main CPU 101 mainly performs the port output process of the reel stop enable signal OFF data. Further, this process is performed using the non-standard work area of the main RAM 103. The details of the reel stop enable signal OFF process will be described later with reference to FIG. 142 described later.

Next, the main CPU 101 determines whether or not the rotation speeds of all the reels have reached a predetermined constant speed (whether or not the speed has reached a "constant speed") (S712). In S712, when the main CPU 101 determines that the rotation speeds of all reels are not "constant speed" (when the determination in S712 is NO), the main CPU 101 repeats the process of S712.

On the other hand, in S712, when the main CPU 101 determines that the rotation speeds of all the reels have reached "constant speed" (when the determination in S712 is YES), the main CPU 101 performs a reel stop enable signal ON process (S713). In this process, the main CPU 101 mainly performs the port output process of the reel stop enable signal ON data. Further, this process is performed using the non-standard work area of the main RAM 103. The details of the reel stop enable signal ON processing will be described later with reference to FIG. 143, which will be described later.

Next, the main CPU 101 determines whether or not a valid stop button has been pressed (S714).

When the main CPU 101 determines in S714 that the valid stop button is not pressed (when the determination in S714 is NO), the main CPU 101 returns the process to the process of S713 and repeats the processes after S713. On the other hand, in S714, when the main CPU 101 determines that a valid stop button has been pressed (when the determination in S714 is YES), the main CPU 101 updates the operation stop button storage area (see FIG. 33), and the stop button is not yet pressed. The value of the operation counter is subtracted by 1 (S715).

Next, the main CPU 101 determines the search target reel from the operation stop button (S716). Further, in this process, the address (start address) set process of the reel control data storage area in which the reel control management information of the search target reel is stored is also performed (source code "LDQ IX, wR1_CTRL- (wR2_CTRL)" in FIG. 140. -WR1_CTRL) ").

Next, the main CPU 101 performs a reel stop enable signal OFF process (S717). Similar to S711, this process is performed using the non-standard work area of the main RAM 103. The details of the reel stop enable signal OFF process will be described later with reference to FIG. 142 described later. Next, the main CPU 101 stores the stop start position in the main RAM 103 based on the value of the symbol counter (S718).

Next, the main CPU 101 performs a reel stop selection process (S719). Although detailed description is omitted, in this process, the main CPU 101 performs a process of selecting the number of sliding pieces.

Next, the main CPU 101 determines a scheduled stop position based on the stop start position and the number of sliding pieces determined in S719, and stores the determined stop scheduled position in the main RAM 103 (S720). In this process, the main CPU 101 adds the number of sliding pieces to the stop start position, and sets the addition result as the stop scheduled position.

Next, the main CPU 101 executes the symbol code storage process (S721). In this process, the symbol code corresponding to the scheduled stop position is stored in the symbol code storage area. Next, the main CPU 101 determines whether or not the reel to be controlled is the reel of the final stop (third stop) (S722). In this process, the main CPU 101 determines whether or not the reel to be controlled is the reel of the final stop (third stop) based on the value of the stop button non-operation counter, and the value of the stop button non-operation counter is set. When it is "0", it is determined that the reel to be controlled is the reel at the final stop.

In S722, when the main CPU 101 determines that the reel to be controlled is not the reel of the final stop (when the determination in S722 is NO), the main CPU 101 performs the control change process (S723). In this process, the stop information group used for stopping the reel is updated when the reel is at a specific stop position. Next, the main CPU 101 performs the pull-in priority storage process described with reference to FIG. 127 (S724).

Next, the main CPU 101 performs a stop interval remaining time standby process (S725). In this process, the main CPU 101 performs a standby process until a preset predetermined reel stop interval time elapses. Then, after the processing of S725, the main CPU 101 returns the processing to the processing of S711, and repeats the processing after S711.

Here, returning to the process of S722 again, when the main CPU 101 determines in S722 that the reel to be controlled is the reel of the final stop (when the determination in S722 is YES), the main CPU 101 excites all the reels. Determines whether or not is in the stopped state (S726). In S726, when the main CPU 101 determines that the excitation of all reels is not in the stopped state (when the determination in S726 is NO), the main CPU 101 repeats the process of S726.

On the other hand, in S726, when the main CPU 101 determines that the excitation of all reels is in the stopped state (when the determination in S726 is YES), the main CPU 101 keeps the stop button operated for the third stop in the ON state. It is determined whether or not (the stop button is not released) (S727). In S727, when the main CPU 101 determines that the stop button operated by the third stop operation remains in the ON state (when the determination in S727 is YES), the main CPU 101 repeats the process of S727. On the other hand, in S727, when the main CPU 101 determines that the stop button operated by the third stop operation is not in the ON state (when the determination in S727 is NO), the main CPU 101 ends the reel stop control process and performs the process. Move to S214 of the main flow (see FIG. 82).

In the present embodiment, the reel stop control process is performed as described above. The processing of S711 to S716 during the reel stop control processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 140. As shown in FIG. 140, in the source program of the reel stop control process of the present embodiment, an instruction code dedicated to the main CPU 101, for example, an "LDQ" instruction for specifying an address using a Q register (extension register) or "LDQ" instruction " The "CALLF" instruction is used.

Therefore, by using such a main CPU 101 dedicated instruction code in the reel stop control process, the capacity of the source program of the reel control process can be reduced and the processing efficiency of the reel stop control process can be improved. it can. That is, in the present embodiment, it is possible to improve the efficiency of the program processing speed and reduce the capacity of the main control circuit 90, and utilize the free area of the main ROM 102 increased according to the reduced capacity for playability. Can be increased.

Further, the determination process of S726 during the reel stop control process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 141. As shown in FIG. 141, this process is executed by using the "LDQ" instruction and the "ORQ" instruction (predetermined OR operation instruction) on the source code.

The "ORQ" instruction is an instruction code that performs a logical sum operation, and is an instruction code dedicated to the main CPU 101 that specifies an address using a Q register (extension register). Then, for example, when the source code "ORQ (k)" is executed on the source program, the stored data (upper address value) of the Q register and the 1-byte integer k (direct value: lower address value) are used. A logical sum operation is performed between the contents of the memory (stored data) at the specified address and the contents (stored data) of the A register, and the calculation result is stored in the A register.

Therefore, in the determination process of S726 during the reel stop control process, when the source code "LDQ A, (.LOW.wR1_TIM)" in FIG. 141 is first executed, the stored data of the Q register and the integer value ". The contents of the memory (excitation timer value of the first reel) at the address specified by ".LOW.wR1_TIM" are loaded into the A register. In the present embodiment, the address of the area in the main RAM 103 where the excitation timer value of the first reel is stored is "F032h". Then, in the determination process of S726 described above, the upper address value "F0h" of the address "wR1_TIM (F032h)" is set in the Q register in advance when the LDQ instruction is executed, and the lower side is set to the k value (direct value). The address value (".LOW.wR2_TIM" = 32h) is substituted.

Next, when the source code "ORQ (.LOW.wR2_TIM)" in FIG. 141 is executed, the address "wR2_TIM" of the area in which the stored data (F0h) of the Q register and the excitation timer value of the second reel are stored is executed. The logical sum operation of the memory contents (excitation timer value of the second reel) of the address specified by the lower address value (3Dh) of "F03Dh)" and the contents of the A register (excitation timer value of the first reel) is performed. The calculation result (combined result of the excitation timer value of the first reel and the excitation timer value of the second reel) is stored in the A register. Next, when the source code "ORQ (.LOW.wR3_TIM)" in FIG. 141 is executed, the address "wR3_TIM" of the area in which the stored data (F0h) of the Q register and the excitation timer value of the third reel are stored is executed. The contents of the memory of the address specified by the lower address value (48h) of "F048h)" (excitation timer value of the third reel) and the contents of the A register (excitation timer value of the first reel and the excitation timer of the second reel). A logical sum operation with the value (combination result with the value) is performed, and the operation result (combination result of the excitation timer values of the first to third reels) is stored in the A register.

As described above, in the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extension register) are used in the check process of the stopped state of the reel (rotary cylinder). Therefore, by using these main CPU 101 dedicated instruction codes, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values, and the instruction related to the address setting is omitted on the source program. Therefore, the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

As described above, in the various processes during the reel stop control process of the present embodiment, the various instruction codes dedicated to the main CPU 101 described above are appropriately used to improve the efficiency of the corresponding processes and reduce the capacity of the source program. ing. As a result, in the present embodiment, it is possible to improve the efficiency of the program processing speed of the main control circuit 90 and reduce the capacity, and it is possible to improve the playability by utilizing the free area corresponding to the reduced capacity. It becomes.

[Reel stoptable signal OFF processing]
Next, with reference to FIG. 142, the reel stop enable signal OFF process performed in S711 or S717 during the reel stop control process (see FIG. 139) will be described. Note that FIG. 142 is a flowchart showing a procedure for turning off the reel stop enable signal.

First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S731). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S732).

Next, the main CPU 101 saves the data set in all the registers (S733). Next, the main CPU 101 performs a set process of the reel stop enable signal OFF data (S734).

Next, the main CPU 101 performs non-standard port output processing (S735). In this process, the main CPU 101 generates and outputs OFF output data (output off mode data), which will be described later, based on the reel stop enable signal OFF data. This process is performed using the non-standard work area of the main RAM 103. Details of the non-standard port output processing will be described later with reference to FIG. 144 described later.

Next, the main CPU 101 restores the data of all the registers saved in S733 (S736). Next, the main CPU 101 sets the address of the stack area saved in S731 in the stack pointer (SP) (S737).

Then, after the processing of S737, the main CPU 101 ends the reel stop enable signal OFF processing. At this time, if the executed reel stop enable signal OFF process is the process of S711 in the reel stop control process (see FIG. 139), the main CPU 101 shifts the process to the process of S712 in the reel stop control process. On the other hand, when the executed reel stop enable signal OFF process is the process of S717 in the reel stop control process (see FIG. 139), the main CPU 101 shifts the process to the process of S718 in the reel stop control process.

[Reel stoptable signal ON processing]
Next, with reference to FIG. 143, the reel stop enable signal ON process performed in S713 during the reel stop control process (see FIG. 139) will be described. Note that FIG. 143 is a flowchart showing the procedure of the reel stop enable signal ON processing.

First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S741). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S742).

Next, the main CPU 101 saves the data set in all the registers (S743). Next, the main CPU 101 refers to the operation stop button storage area (see FIG. 33) and acquires the stop button state (S744). Next, the main CPU 101 performs a set process of the reel stop enable signal ON data (S745).

Next, the main CPU 101 performs non-standard port output processing (S746). In this process, the main CPU 101 generates and outputs ON output data (output on mode data), which will be described later, based on the reel stop enable signal ON data. This process is performed using the non-standard work area of the main RAM 103. Details of the non-standard port output processing will be described later with reference to FIG. 144 described later.

Next, the main CPU 101 restores the data of all the registers saved in S743 (S747). Next, the main CPU 101 sets the address of the stack area saved in S741 in the stack pointer (SP) (S748). Then, after the processing of S748, the main CPU 101 ends the reel stop enable signal ON processing, and shifts the processing to the processing of S714 in the reel stop control processing (see FIG. 139).

[Non-standard port output processing]
Next, with reference to FIGS. 144 and 145, regarding the non-standard port output processing performed in S735 during the reel stoptable signal OFF processing (see FIG. 142) and S746 during the reel stoptable signal ON processing (see FIG. 143). explain. Note that FIG. 144 is a flowchart showing the procedure of the non-standard port output process. Further, FIG. 145 is a diagram showing an example of a source program for executing the non-standard port output process.

First, the main CPU 101 determines whether or not the port output setting is the ON output mode (S751). In this process, the main CPU 101 determines that the port output setting is the ON output mode when the reel stop enable signal ON data is set, and when the reel stop enable signal OFF data is set, the main CPU 101 determines. , Judge that the port output setting is not ON output mode.

In S751, when the main CPU 101 determines that the port output setting is the ON output mode (when the determination in S751 is YES), the main CPU 101 performs the process of S753 described later. On the other hand, in S751, when the main CPU 101 determines that the port output setting is not the ON output mode (when the determination in S751 is NO), the main CPU 101 performs an OFF output data (output off mode data) generation process (S752). ). In this process, among the ports (bits) that are currently in the output on state, the port (bit) that you want to turn off is turned off, and the port (bit) that is currently in the output off state is turned off. OFF output data for maintaining the state is generated.

After the processing of S752 or when the determination in S751 is NO, the main CPU 101 performs an ON output data (output on mode data) generation process (S753). In this process, among the ports (bits) that are currently in the output off state, the port (bit) that you want to turn on is turned on, and the port (bit) that is currently in the output on state is turned on. ON output data for maintaining the state is generated. Next, the main CPU 101 outputs the generated output data from the designated port (S754).

Then, after the processing of S754, the main CPU 101 ends the non-standard port output processing. At this time, if the executed non-standard port output process is the process of S735 during the reel stop enable signal OFF process (see FIG. 142), the main CPU 101 processes the process of S736 during the reel stop enable signal OFF process. Move to. On the other hand, when the executed non-standard port output process is the process of S746 during the reel stop enable signal ON process (see FIG. 143), the main CPU 101 shifts the process to the process of S747 during the reel stop enable signal ON process. Transfer.

In the present embodiment, the non-standard port output process is performed as described above. Then, the above-mentioned non-standard port output processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 145.

Among them, in the process of generating the OFF output data of S752 during the above-mentioned non-standard port output process, the source codes "XOR (HL)" and "AND (HL)" in FIG. 145 are executed in this order. Will be done. Further, the process of generating the ON output data of S753 during the above-mentioned non-standard port output process is performed by executing the source code "OR (HL)" in FIG. 145.

By performing such output data generation processing on the source program, the OFF output data generated in S752 is generated even if the ON output data generation processing of S753 is performed after the OFF output data generation processing of S752. Does not change.

For example, the port output setting is the OFF output mode, and the output data indicating the non-standard port to be turned off in this process is "00010111" ("1" is the bit to be turned off), and the non-standard port is currently set. When the output data (backup data) output to is "0100011" ("1" is the bit currently on), the data of bit 0, bit 1 and bit 5 of the backup data is changed from "1" to "1". OFF output data for setting to "0" is generated. In this case, first, when the source code "XOR (HL)" in FIG. 145 is executed, an exclusive OR operation is performed between the output data "00010111" and the backup data "0101011", and the operation result is " 01000100 ”is obtained. Next, when the source code "AND (HL)" in FIG. 145 is executed, a logical product operation of the calculation result "010000100" and the backup data "01000111" is performed, and the calculation result "01000000" is used as OFF output data. Generated.

After that, when the ON output data generation process of S753 (source code “OR (HL)” in FIG. 145) is executed, the calculation result “01000000” (OFF output data) is turned on in this process. A logical sum operation is performed with the output data "00000000000" indicating the non-standard port to be desired (since the port output setting is the OFF output mode, "0" is set for each bit of the output data), and the calculation result is “01000000” is obtained, and the OFF output data does not change. Qualitatively, when the port output setting is the OFF output mode, in the ON output data generation process of S753, the output for keeping the port (bit) that is in the output ON state in the OFF output data in the ON state. Since the data is generated, the OFF output data generated in S752 does not change even if the ON output data generation process of S753 is performed after the OFF output data generation process of S752.

[Prize search process]
Next, the winning search process performed in S214 in the main flow (see FIG. 82) will be described with reference to FIGS. 146 to 148. Note that FIG. 146 is a flowchart showing the procedure of the winning search process. FIG. 147 is a diagram showing an example of a source program for executing the winning search process. Further, FIG. 148 is a diagram showing an example of the configuration of the payout number data table that is actually referred to on the source program of the winning search process.

First, the main CPU 101 transfers and stores the data of each storage area stored in the symbol code storage area (see FIG. 35) to the corresponding storage area of the winning operation flag storage area (see FIGS. 28 to 30). (S761). Then, at the end of this processing, the address at the end of the winning operation flag storage area is set in the DE register.

Next, the main CPU 101 sets the address of the payout number data table (the start address “dPAYNUMTB” of the payout number data table shown in FIG. 148) in the HL register (S762). Next, the main CPU 101 sets the number of payout number tables (“5” in this embodiment) as the initial value of the winning search counter, and sets the initial value in the B register (S763).

Next, the main CPU 101 sets the data of the number of medals to be paid out (in this embodiment, any one of 1, 2, 3, and 9) in the C register based on the address set in the HL register. , The determination target data is set in the A register, and "2" is added (+2 update) to the address set in the HL register (S764). In the payout number data table shown in FIG. 148, the data of the payout number of medals is "payout number (1, 2, 3 or 9) * 2 + 0", and the determination target data is next to the payout number data. It is 1-byte data (for example, "11111000B" or the like) stored in the address. Further, in the following, the data "0" in the data "number of medals to be paid out (1, 2, 3 or 9) * 2 + 0" set in the C register will be referred to as a "judgment bit". This determination bit is information indicating whether or not the block is the determination target block of the winning search.

Next, the main CPU 101 extracts the value of the determination bit from the data of the number of medals to be paid out set in the C register (S765). Next, the main CPU 101 determines whether or not the block is a determination target block based on the value of the extracted determination bit (S766). In this process, the main CPU 101 determines that the block is a determination target block when the value of the extracted determination bit is "1". In this embodiment, as shown in FIG. 148, the value of the determination bit is always "0" regardless of the number of medals to be paid out, so that the processing of S766 is always a NO determination.

In S766, when the main CPU 101 determines that the block is not the determination target block (when the determination in S766 is NO), the main CPU 101 performs the process of S768 described later. On the other hand, in S766, when the main CPU 101 determines that the block is the determination target block (when the determination in S766 is YES), the main CPU 101 subtracts 1 from the address of the winning operation flag storage area set in the DE register (-). 1 update) (S767).

After the processing of S767 or when the determination in S766 is NO, the main CPU 101 extracts the data of the storage area specified by the address of the winning operation flag storage area set in the DE register as the determination data (S768).

Next, the main CPU 101 determines whether or not the determination result is a prize based on the determination target data set in the A register in S764 and the determination data extracted in S768 (S769). In this process, if the determination target data set in the A register in S764 is the same as the determination data extracted in S768, the main CPU 101 determines that the determination result is a prize.

In S769, when the main CPU 101 determines that the result of the determination is not a prize (when the determination in S769 is NO), the main CPU 101 performs the process of S776 described later. On the other hand, in S769, when the main CPU 101 determines that the result of the determination is a winning result (when the determination in S769 is YES), the main CPU 101 has three current games (a game in which the number of medals bet is three). ) (S770).

In S770, when the main CPU 101 determines that the current game is a three-card game (when the determination in S770 is YES), the main CPU 101 performs the process of S772 described later. On the other hand, in S770, when the main CPU 101 determines that the current game is not a three-card game (when the determination in S770 is NO), the main CPU 101 pays out a two-card game (a game in which the number of medals bet is two). The number of sheets (2 sheets) is set in the C register (S771).

After the processing of S771 or when the determination in S770 is YES, the main CPU 101 updates the number of payouts (S772). Specifically, the main CPU 101 adds the number of medals to be paid out set in the C register to the current value of the winning number counter, and sets the added value to the number of payouts.

Next, the main CPU 101 determines whether or not the value of the number of payouts is less than the maximum number of payouts "10" (S773).

In S773, when the main CPU 101 determines that the value of the number of payouts is less than the maximum number of payouts "10" (when the determination in S773 is YES), the main CPU 101 performs the process of S775 described later. On the other hand, in S773, when the main CPU 101 determines that the value of the payout number is not less than the maximum payout number "10" (when the determination in S773 is NO), the main CPU 101 sets the maximum payout number "10" to the payout number. (S774).

After the processing of S774 or when the determination in S773 is YES, the main CPU 101 stores the payout number in the winning number counter (S775).

After the processing of S775 or when the determination in S769 is NO, the main CPU 101 determines whether or not there is another prize (S776). In S776, when the main CPU 101 determines that there is another prize (when the determination in S776 is YES), the main CPU 101 returns the process to the process of S769 and repeats the processes after S769.

On the other hand, in S7776, when the main CPU 101 determines that there is no other prize (when the determination in S776 is NO), the main CPU 101 subtracts 1 (updates -1) the value of the prize search counter (S777). In addition, as in the present embodiment, when there is only one effective line, since a plurality of small winning combinations are not duplicated and won a prize, the determination process of S776 is always a NO determination.

Next, the main CPU 101 determines whether or not the value of the winning search counter is "0" (S778).

In S778, when the main CPU 101 determines that the value of the winning search counter is not "0" (when the determination in S778 is NO), the main CPU 101 returns the processing to the processing of S764 and repeats the processing after S764. On the other hand, in S778, when the main CPU 101 determines that the value of the winning search counter is "0" (when the determination in S778 is YES), the main CPU 101 ends the winning search process and performs the process in the main flow (FIG. FIG. (Refer to 82), the process proceeds to S215.

In the present embodiment, the winning search process is performed as described above. Then, the above-mentioned winning search process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 147. Among them, the set processing of the number of payouts and the data to be determined in S764 is performed by the main CPU 101 executing the source code "LDIN AC, (HL)".

When, for example, the source code "LDIN ss, (HL)" is executed on the source program, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( Data) is loaded into the ss (BC, DE, AC, AE or BD) pair register, and the address set in the HL register is updated by +2 (2 additions). Therefore, when the source code "LDIN AC, (HL)" in FIG. 147 is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( The number of payouts and the data to be determined) are loaded into the AC register, and the address set in the HL register is updated by +2 (2 additions). In the process of S764, by this "LDIN" instruction, the data of the number of payouts is stored in the A register, the determination target data is stored in the C register, and the address set in the HL register is updated by +2.

As described above, in the winning search process of the present embodiment, both the data load process and the address update process can be performed by one "LDIN" command. In this case, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, the acquisition process of the value of the medal counter referred to in the determination process of S770 during the above-mentioned winning search process, the acquisition process of the value of the winning number counter referred to in the processing of S772, and the winning number counter performed in the processing of S775. As shown in FIG. 147, all the save (update) processes are executed by the "LDQ" instruction (instruction code dedicated to the main CPU 101) that specifies the address using the Q register (extension register). Therefore, in the winning search process of the present embodiment, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by the direct value by using the "LDQ" instruction. The instruction related to the setting can be omitted (it is not necessary to separately provide the instruction related to the address setting), and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, as shown in FIG. 147, the determination process of S769 during the winning search process described above is executed by the "JSLAA" instruction (predetermined determination instruction) on the source program. The "JSLAA" instruction is an instruction that executes an operation equivalent to a left shift (SLA) instruction.

For example, when the source code "JSLAA cc, e" is executed on the source program, if the condition of cc is satisfied, the process is jumped to the address specified by e. The state of the carry flag in the flag register F is specified in the "cc condition" specified by the "JSLAA" instruction. For example, if "C" is specified for cc, the condition of cc means that the carry flag is "1" (on state), and if "NC" is specified for cc, the condition of cc. Means that the carry flag is "0" (off state). Therefore, in the source code "JSLAA NC, MN_CKLN_06" in FIG. 147, if the carry flag is "0" (off state), the process jumps to the address specified by "MN_CKLN_06".

Further, the determination process of S770 and S773 during the above-mentioned winning search process is executed by the "JCP" instruction on the source program as shown in FIG. 147. As described above, the "JCP" instruction is an instruction that executes an operation equivalent to a comparison instruction, and is an instruction code dedicated to the main CPU 101.

Therefore, when the above-mentioned "JSLAA" command and "JCP" command are used on the source program of the winning search process, the command related to the address setting can be omitted (it is necessary to separately provide the command related to the address setting). The capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Illegal hit check processing]
Next, the illegal hit check process performed in S215 in the main flow (see FIG. 82) will be described with reference to FIGS. 149 and 150. Note that FIG. 149 is a flowchart showing the procedure of the illegal hit check process. Further, FIG. 150 is a diagram showing an example of a source program for executing the illegal hit check process. An illegal hit is a BB winning number and a small winning combination (internal winning combination) that are drawn by the internal lottery process (see FIG. 93) and stored in the winning number storage area by the symbol setting process (see FIG. 98). Based on this, it is a term indicating that the left reel 3L, the middle reel 3C, and the right reel 3R are stopped on the effective line with a combination of symbols that cannot be established (symbol combination is not established).

First, the main CPU 101 sets the address of the winning operation flag storage area (see FIGS. 28 to 30) (S781). Next, the main CPU 101 sets the size of the winning operation flag storage area (the number of bytes, “12” in this embodiment) to the value of the check counter (S782).

Next, the main CPU 101 is based on the address of the winning operation flag storage area currently set, and the internal winning combination stored in the storage area in the hit request flag storage area (internal winning combination storage area) corresponding to the address. Data (hit request flag data) is acquired (S783). Next, the main CPU 101 synthesizes the winning combination data (winning operation flag data) stored in the address of the currently set winning operation flag storage area and the internal winning combination data (winning request flag data) ( S784).

In this synthesis process, the main CPU 101 first obtains the exclusive OR of the winning combination data (winning operation flag data) and the internal winning combination data (winning request flag data) (source program shown in FIG. 150). Source code inside "XOR (HL)"). Next, the main CPU 101 obtains the logical product of the calculated exclusive-OR calculation result and the winning combination data (winning operation flag data) (source code "AND (HL)" in the source program shown in FIG. 150. ), The calculation result of the logical product is used as the synthesis result. If no illegal hit error has occurred, the value of this synthesis result will be "0".

Next, the main CPU 101 determines whether or not an illegal hit error has occurred based on the result of the synthesis process of S784 (S785).

In S785, when the main CPU 101 determines that an illegal hit error has not occurred (NO in S785), the main CPU 101 updates the address of the winning operation flag storage area to be referred to by +1 (S786). Next, the main CPU 101 subtracts 1 from the value of the check counter (S787). Next, the main CPU 101 determines whether or not the value of the check counter is "0" (S788).

In S788, when the main CPU 101 determines that the value of the check counter is not "0" (when the determination in S788 is NO), the main CPU 101 returns the process to the process of S783 and repeats the processes after S783. On the other hand, in S788, when the main CPU 101 determines that the value of the check counter is "0" (when the determination in S788 is YES), the main CPU 101 ends the illegal hit check process and performs the process in the main flow (FIG. FIG. (Refer to 82), the process proceeds to S216.

Here, returning to the processing of S785 again, when the main CPU 101 determines in S785 that an illegal hit error has occurred (when the determination in S785 is YES), the main CPU 101 performs the error processing described with reference to FIG. 90. (S789). By this process, the two-digit 7-segment LED (both for displaying the number of payouts and for displaying the error) included in the information display 6 is used to display the two characters "EE" indicating the occurrence of an illegal hit error as error information. Error display data is output. The state in which the illegal hit error occurs (error state) is released by pressing the reset switch 76 (see FIG. 7).

Next, the main CPU 101 clears the value of the winning number counter and the data of the hit request flag storage area (S790). Then, after the processing of S790, the main CPU 101 ends the illegal hit check processing, and shifts the processing to the processing of S216 in the main flow (see FIG. 82).

In the present embodiment, the illegal hit check process is performed as described above. Then, the above-mentioned illegal hit check process is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 150.

In this embodiment, as shown in FIGS. 28 to 30, the configuration of the winning operation flag storage area (display combination storage area) is the same as that of the hit request flag storage area (internal winning combination storage area). The winning request flag storage area and the winning operation flag storage area arranged in the main RAM 103 at the time of combining the winning combination of the winning operation flag storage area and the internal winning combination can have the same configuration. Therefore, the calculation result of S784 in the illegal hit check process of the present embodiment (the result of synthesizing the data of the winning combination and the data of the internal winning combination) is the data of the winning combination and the internal on the source program as described above. It is obtained by simply logically producting the winning combination data (executed with the "AND" instruction). As a result, in the present embodiment, the illegal hit check process can be made more efficient and simplified, the free space of the main control program can be secured (increased), and the increased free space can be used for playability. It becomes possible to increase.

[Prize check / medal payout process]
Next, the winning check / medal payout process performed in S216 in the main flow (see FIG. 82) will be described with reference to FIGS. 151 and 152. Note that FIG. 151 is a flowchart showing the procedure of winning check / medal payout processing. Further, FIG. 152 is a diagram showing an example of a source program for executing the processes of S804 to S808 described later during the winning check / medal payout process.

First, the main CPU 101 performs a winning operation command generation process (S801). In this process, the main CPU 101 generates type data and various communication parameters included in the winning operation command transmitted to the sub-control circuit 200. The winning operation command is configured to include a parameter for specifying a winning operation flag (display combination) and the like.

Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 72 (S802). By this process, the winning operation command data is stored in the communication data storage area (see FIG. 75B) provided in the main RAM 103. The winning operation command is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 167.

Next, the main CPU 101 determines whether or not the value of the winning number counter is "0" (S803). In S803, when the main CPU 101 determines that the value of the winning number counter is "0" (when the determination in S803 is YES), the main CPU 101 ends the winning check / medal payout process, and performs the process in the main flow (when the winning check / medal payout process is completed). (Refer to FIG. 82), the process proceeds to S217.

On the other hand, in S803, when the main CPU 101 determines that the value of the winning number counter is not "0" (when the determination in S803 is NO), the main CPU 101 has the maximum number of medals credited (stored). In the embodiment, it is determined whether or not the number is 50 or more (S804).

In S804, when the main CPU 101 determines that the number of credits for medals is not equal to or greater than the upper limit (when the determination in S804 is NO), the main CPU 101 adds "1" to the value of the credit counter (updates +1) (upgrading +1). S805). The added value of the credit counter is displayed by a 2-digit 7-segment LED (not shown) for displaying the number of stored sheets included in the information display 6. Next, the main CPU 101 performs a medal payout number check process (S806). The details of the medal payout number check process will be described later with reference to FIG. 153, which will be described later.

Next, the main CPU 101 determines whether or not the payout of medals has been completed (S807). In S807, when the main CPU 101 determines that the medal payout has been completed (when the determination in S807 is YES), the main CPU 101 ends the winning check / medal payout process, and the process is in the main flow (see FIG. 82). Move to the processing of S217.

On the other hand, in S807, when the main CPU 101 determines that the payout of medals has not been completed (when the determination in S807 is NO), the main CPU 101 performs a payout interval standby process (S808). In this process, the main CPU 101 waits until the preset medal payout interval time (60.33 msec in this embodiment: 54 cycles of the interrupt process (1.1172 msec cycle) described later with reference to FIG. 167) elapses. Wait. Then, after the processing of S808, the main CPU 101 returns the processing to the processing of S803, and repeats the processing after S803.

Here, returning to the process of S804 again, when the main CPU 101 determines in S804 that the number of credits for medals is equal to or greater than the upper limit (50) (when the determination in S804 is YES), the main CPU 101 determines. The medal payout process is performed (S809). By this process, one medal is paid out. Then, after the processing of S809, the main CPU 101 ends the winning check / medal payout processing, and shifts the processing to the processing of S217 in the main flow (see FIG. 82).

In the present embodiment, the winning check and the medal payout process are performed as described above. The processes S804 to S808 during the winning check / medal payout process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 152.

In the present embodiment, when the payout operation is continued after the credit counter is updated (+1), the main CPU 101 performs a wait (payout interval wait) process for 60.33 ms in the process of S808. On the source program, the main CPU 101 is realized by executing the source codes "LD BC, cTM_PAYC" and "RST SB_W1BC_00" in this order. In this way, in the winning check / medal payout process, if a wait (waiting for payout interval) of 60.33 ms is performed when the payout operation is continued after updating the credit counter (+1), useless waiting time is reduced. It is possible to reduce the mental burden on the player.

[Check process for paying out medals]
Next, with reference to FIGS. 153 and 154, the medal payout number check process performed in S806 during the winning check / medal payout process (see FIG. 151) will be described. Note that FIG. 153 is a flowchart showing the procedure of the medal payout number check process. Further, FIG. 154A is a diagram showing an example of a source program for executing the processes of S811 to S814 described later during the medal payout number check process, and FIG. 154B shows S816 and S816 described later during the medal payout number check process. It is a figure which shows an example of the source program for executing the process of S817.

First, the main CPU 101 adds (+1 update) to the value of the medal OUT counter (S811). The medal OUT counter is a counter for counting the number of times the medal is paid out. Next, the main CPU 101 adds (+1 update) to the value of the payout number counter (S812). The payout number counter is a counter for counting the payout number of medals.

Next, the main CPU 101 performs a payout number 7SEG display process (S813). In this process, the main CPU 101 performs a control process of displaying the value of the payout number counter by a 2-digit 7-segment LED (not shown) for displaying the payout number included in the information display 6.

Next, the main CPU 101 performs an update process of the winning combination end number counter (S814). The winning combination end number counter is a counter for counting the remaining number of medals to be paid out corresponding to the winning combination. In this process, the main CPU 101 compares the value of the combination end number counter with the lower limit value “0”, and if the value of the combination end number counter is larger than the lower limit value “0”, the combination end number counter. The value of the counter is subtracted by 1 (updated by -1), and when the value of the winning combination end number counter is equal to or less than the lower limit value "0", the value of the winning combination ending number counter is held at "0".

Next, the main CPU 101 subtracts 1 (updates -1) the value of the winning number counter (S815).

Next, the main CPU 101 performs a credit information command generation process (S816). In this process, the main CPU 101 generates type data and various communication parameters included in the credit information command transmitted to the sub-control circuit 200. The credit information command is configured to include a parameter for specifying the number of credits for medals.

Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 72 (S817). By this process, the credit information command data is stored in the communication data storage area (see FIG. 75B) provided in the main RAM 103. The credit information command is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 167. Then, after the process of S817, the main CPU 101 ends the medal payout number check process, and shifts the process to the process of S807 during the winning check / medal payout process (see FIG. 151).

In the present embodiment, the medal payout number check process is performed as described above. The processes of S811 to S814 during the above-mentioned medal payout number check process are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 154A. Among them, the update process of the winning combination end number counter in S814 is executed by the "DCPLD" instruction (predetermined update instruction) in FIG. 154A. The "DCPLD" instruction is an instruction code dedicated to the main CPU 101.

When, for example, the source code "DCPLD (HL), n" is executed on the source program, the memory contents (stored data) of the address specified by the HL register are compared with the integer n, and the memory contents are changed. If it is larger than the integer n, the contents of the memory are subtracted by 1, and if the contents of the memory are not more than the integer n, the integer n is stored in the memory at the address specified by the HL register. Therefore, when the source code "DCPLD (HL), 0" in FIG. 154A is executed, the contents of the memory at the address specified by the HL register (value of the winning combination end number counter) and an integer 0 (lower limit value). If the memory content (value of the winning combination end number counter) is greater than an integer 0, the memory content is subtracted by 1, and if the memory content is an integer 0 or less, the memory content is subtracted. "0" is set in (value of the number counter for the end of the winning combination). That is, if the value of the current combination end number counter is larger than "0", the combination end number counter is updated, and if the current combination end number counter value is "0" or less. , The process of holding the value of the winning combination end number counter at "0" is performed.

As described above, in the process of S814 during the medal payout number check process, one "DCPLD" command (a command in which the lower limit judgment command of the number management counter and the judgment branch command are integrated) is used to complete the winning combination. Both the counter update (subtraction) process and the process of holding the value of the continuous end number counter at "0" can be executed. In this case, it is not necessary to provide an instruction code for executing both processes separately. For example, the determination branch instruction code for determining whether or not the value of the continuous end number counter is "0" can be omitted. Therefore, in the medal payout number check process of the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, and the free space can be secured (increased) in the main ROM 102, resulting in an increase. It is possible to improve the playability by utilizing the free space.

Further, the processes of S816 and S817 during the above-mentioned medal payout number check process are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 154B.

Among them, in the process of S816, as shown in FIG. 154B, the value of the payout counter is set in the communication parameter 1 of the credit information command via the L register, and the credit is set in the communication parameter 5 via the C register. The value of the counter is set. However, the other communication parameters 2 to 4 constituting the credit information command are set with values (indefinite values) currently stored in the H register, the E register, and the D register, respectively. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[Ratio monitor aggregation processing (non-regulation)]
Next, with reference to FIG. 155, the combination monitor aggregation process performed in S217 in the main flow (see FIG. 82) will be described. FIG. 155 is a flowchart showing the procedure of the combination monitor aggregation process. In this process, the non-standard work area (see FIG. 12C) in the main RAM 103 is used as the work area, and the program used in this process is stored in the non-standard area in the main ROM 102 (see FIG. 12B). ..

First, the main CPU 101 performs advantageous section aggregation processing (S2011). In this process, the main CPU 101 aggregates the necessary game information and calculates the above-mentioned advantageous section ratio based on the aggregated result. The details of the advantageous section aggregation process will be described later with reference to FIG. 156, which will be described later.

Next, the main CPU 101 performs a payout number counting process (S2012). In this process, the main CPU 101 aggregates the necessary game information, and calculates the total consecutive combination ratio and the total accessory ratio described above based on the aggregation result. The details of the payout number counting process will be described later with reference to FIG. 161 described later.

Next, the main CPU 101 performs a medium-time aggregation process (S2013). In this process, the main CPU 101 calculates the medium-time continuous combination ratio and the medium-time bonus ratio described above based on the game information aggregated by the payout number counting process (see S2012). The details of the medium-time aggregation process will be described later with reference to FIG. 162 described later. Then, after the processing of S2013, the main CPU 101 ends the combination monitor aggregation processing, and shifts the processing to the processing of S218 in the main flow (see FIG. 82).

[Advantageous section aggregation processing]
Next, with reference to FIG. 156, the advantageous section aggregation process performed in S2011 during the combination monitor aggregation process (see FIG. 155) will be described. Note that FIG. 156 is a flowchart showing the procedure of the advantageous section aggregation processing.

First, the main CPU 101 determines whether or not the combination ratio monitoring state is the state where the total number of games has reached the upper limit (S2021). In the present embodiment, the upper limit of the total number of games that can be totaled is set to "16777215" (3 bytes), and in this process, it is determined whether or not the total number of games that have been totaled has reached the upper limit. The upper limit of the total number of games that can be totaled can be changed as appropriate. For example, the upper limit of the total number of games that can be totaled may be set to "42949677295" (4 bytes). Further, for example, a predetermined value within the range of 3 bytes (for example, "175000") may be set.

In S2021, when the main CPU 101 determines that the combination monitor state is the state where the upper limit of the total number of games has been reached (when the determination in S2021 is YES), the main CPU 101 ends the advantageous section aggregation process and performs the process in the combination monitor. The process proceeds to S2012 during the aggregation process (see FIG. 155).

On the other hand, in S2021, when the main CPU 101 determines that the combination ratio monitoring state is not the state in which the upper limit of the total number of games has been reached (when the determination in S2021 is NO), the main CPU 101 performs the game number addition process (S2022). In this game number addition process, if the ART function is operating (that is, during the advantageous section), the data of the advantageous section storage area (not shown) which is composed of 3 bytes and totals the number of games in the advantageous section is added by 1. At the same time, the data of the total number of games storage area (not shown) which is composed of 3 bytes and totals the total number of games is added by 1. Further, when the ART function is not operating (that is, during a normal section that is not in an advantageous section), only the data in the total number of games storage area described above is added by 1.

Next, the main CPU 101 determines whether or not the addition result to the total number of games storage area exceeds the total number of games upper limit (or whether or not the total number of games has reached the upper limit) (S2023). In S2023, when the main CPU 101 determines that the addition result to the total game number storage area exceeds the total game number upper limit (when the determination in S2023 is YES), the main CPU 101 is in the combination ratio monitor state and the total game number upper limit. The arrival state is set (S2024). Then, after the processing of S2024, the main CPU 101 ends the advantageous section aggregation processing, and shifts the processing to the processing of S2012 in the combination monitor aggregation processing (see FIG. 155).

On the other hand, in S2023, when the main CPU 101 determines that the addition result to the total game number storage area does not exceed the total game number upper limit (when the determination in S2023 is NO), the main CPU 101 is in the total game number storage area. The lower 2 bytes of data are acquired (S2025). Next, the main CPU 101 determines whether or not the total number of games has reached the "6000" game (S2026).

In S2026, when the main CPU 101 determines that the total number of games has reached the "6000" game based on the data of the lower two bytes of the total number of games storage area (when the determination in S2026 is YES), the main CPU 101 determines that the total number of games has reached "6000". A state in which the total number of games reaches 6000 G is set in the role ratio monitor state (S2027). Then, after the processing of S2027, the main CPU 101 shifts to the processing of S2032 described later.

On the other hand, in S2026, when the main CPU 101 determines that the total number of games has not reached the "6000" game based on the data of the lower two bytes of the total number of games storage area (when the determination in S2026 is NO), the main The CPU 101 determines whether or not the total number of games has reached the "175000" game (S2028). Specifically, the main CPU 101 determines whether or not the data of the lower 2 bytes of the total number of games storage area is "0AB98H".

In S2028, when the main CPU 101 determines that the total number of games has not reached the "175000" game based on the data of the lower two bytes of the total number of games storage area (when the determination in S2028 is NO), the main CPU 101 determines. , S2032, which will be described later. On the other hand, in S2028, when the main CPU 101 determines that the total number of games has reached the "175000" game based on the data of the lower two bytes of the total number of games storage area (when the determination in S2028 is YES), the main CPU 101 Acquires the data of the upper 1 byte of the total number of games storage area (S2029).

Next, the main CPU 101 determines whether or not the total number of games has reached the "175000" game (S2030). Specifically, the main CPU 101 determines whether or not the data of the upper 1 byte of the total number of games storage area is "02H". In S2030, when the main CPU 101 determines that the total number of games has not reached the "175000" game based on the data of the upper 1 byte of the total number of games storage area (when the determination in S2030 is NO), the main CPU 101 , S2032, which will be described later.

On the other hand, in S2030, when the main CPU 101 determines that the total number of games has reached the "175000" game based on the data of the upper 1 byte of the total number of games storage area (when the determination in S2030 is YES), the main CPU 101 Sets the total number of games reaching 175000G in the role ratio monitor state (S2031).

After the processing of S2027, when S2028 determines NO, when S2030 determines NO, and after processing S2031, the main CPU 101 sets the advantageous section ratio calculation table (S2032). In the present embodiment, the advantageous section ratio calculation table (calculation data table for calculating the advantageous section ratio) is in the order of the advantageous section storage area, the total number of games storage area, the advantageous section ratio display data storage area, and the end code. A table with specified addresses.

Next, the main CPU 101 performs the ratio calculation data setting process (S2033). In this process, the main CPU 101 calculates the effective period ratio based on the data of the advantageous section storage area and the data of the total number of games storage area, and stores the calculation result in the advantageous section ratio display data storage area. The details of the ratio calculation data setting process will be described later with reference to FIG. 157, which will be described later. Then, after the processing of S2033, the main CPU 101 ends the advantageous section aggregation processing, and shifts the processing to the processing of S2012 in the combination monitor aggregation processing (see FIG. 155).

[Ratio calculation data setting process]
Next, with reference to FIG. 157, S2033 in the advantageous section totaling process (see FIG. 156), S2118 in the payout number totaling process (see FIG. 161 described later), and the medium-time totaling process described later (described later). The ratio calculation data setting process performed in S2127 in (see FIG. 162) will be described. Note that FIG. 157 is a flowchart showing the procedure of the ratio calculation data setting process.

First, the main CPU 101 determines whether or not the address of the calculation data table is an end code (S2041). That is, when the advantageous section ratio calculation table, the accessory and the combination ratio calculation table 1 described later, or the accessory and the combination ratio calculation table 2 described later are set in the main CPU 101, the current address is the end code. It is determined whether or not it is (00H).

In S2041, when the main CPU 101 determines that the address of the calculation data table is the end code (when the determination in S2041 is YES), the main CPU 101 ends the ratio calculation data setting process and performs the advantageous section aggregation process (FIG. 156). In the case of S2033 in (see), this advantageous period totaling process is also completed and the process is moved to S2012 of the combination monitor totaling process (see FIG. 155), and the payout number totaling process described later (see FIG. 161 described later) is in progress. In the case of S2118, the payout number totaling process is also completed and the process is moved to S2013 of the combination monitor totaling process (see FIG. 155), and S2127 in the medium-time totaling process (see FIG. 162 described later) described later. In that case, the process is transferred to S2128 during the medium-time aggregation process.

On the other hand, in S2041, when the main CPU 101 determines that the address of the calculation data table is not an end code (when the determination in S2041 is NO), the main CPU 101 uses the calculation data table address as the calculation work address 1 (molecule). Transfer to the calculation work address 2 (denominator) (S2042). In this process, for example, when the advantageous section ratio calculation table is set, the address of the advantageous section storage area is transferred to the calculation work address 1 (molecule), and the address of the total number of games storage area is the calculation work. Transferred to address 2 (denominator).

Further, in this process, for example, when the accessory and the consecutive combination ratio calculation table 1 described later are set, the address of the total consecutive combination payout number storage area described later is transferred to the calculation work address 1 (numerator). , The address of the total payout number storage area, which will be described later, is transferred to the calculation work address 2 (denominator). Alternatively, the address of the total payout number storage area described later is transferred to the calculation work address 1 (numerator), and the address of the total payout number storage area described later is transferred to the calculation work address 2 (denominator).

Further, in this process, for example, when the accessory and the continuous combination ratio calculation table 2 described later are set, the address of the medium-time continuous combination payout number storage area described later becomes the calculation work address 1 (numerator). It is transferred, and the address of the medium-time payout number storage area, which will be described later, is transferred to the calculation work address 2 (denominator). Alternatively, the address of the medium-time payout number storage area described later is transferred to the calculation work address 1 (numerator), and the address of the medium-time payout number storage area described later is transferred to the calculation work address 2 (denominator). ..

Next, the main CPU 101 performs a ratio calculation process (S2043). In this process, the ratio information is calculated based on the game information transferred to the calculation work address 1 (numerator) and the calculation work address 2 (denominator). The details of the ratio calculation process will be described later with reference to FIGS. 158 to 160 described later.

Next, the main CPU 101 acquires the address of the display data storage area from the calculation data table (S2044). In this process, for example, when the advantageous section ratio calculation table is set, the address of the advantageous section ratio display data storage area is acquired, and when the accessory and the consecutive combination ratio calculation table 1 described later are set. When the address of the total combination ratio display data storage area or the total combination ratio display data storage area, which will be described later, is acquired, and the accessory and the combination ratio calculation table 2 described later is set in, the medium time The address of the continuous combination ratio display data storage area or the medium-time bonus ratio display data storage area is acquired.

Next, the main CPU 101 updates the address of the calculation data table by +1 (S2045). Next, the main CPU 101 stores the ratio calculated by the ratio calculation process (see S2043) as display data (ratio information) in the corresponding display data storage area of the calculation data table (S2046). Then, after the processing of S2046, the main CPU 101 returns the processing to the processing of S2041.

[Ratio calculation processing (approximate value formula)]
Next, with reference to FIGS. 158 and 159, the first aspect (approximate value formula) of the ratio calculation process performed in S2043 of the ratio calculation data setting process (see FIG. 157) will be described. Note that FIGS. 158 and 159 are flowcharts showing the procedure of the ratio calculation process (approximate value formula).

First, the main CPU 101 determines whether or not the value of the calculation work address 2 (denominator) is 0 (S2051). In S2051, when the main CPU 101 determines that the value of the work address 2 (denominator) for calculation is 0 (when the determination in S2051 is YES), the main CPU 101 ends the ratio calculation process (approximate value formula). The process is transferred to the process of S2044 in the ratio calculation data setting process (see FIG. 157).

On the other hand, in S2051, when the main CPU 101 determines that the value of the calculation work address 2 (denominator) is not 0 (when the determination in S2051 is NO), the main CPU 101 inputs the data of the calculation work address 1 (numerator). Transfer to the calculation work 1 (S2052). As described above, the value transferred to the calculation work address 1 (molecule) is within the range of 3 bytes, but as will be described later, the value of the calculation work 1 is multiplied by 100. , Calculation work 1 (molecule) is composed of 4 bytes (however, since the 32nd bit is always 0, the effective bit is 31 bits). However, the calculation work address 1 (numerator) may also be composed of 4 bytes as in the calculation work 1 (numerator).

Next, the main CPU 101 transfers the data of the calculation work address 2 (denominator) to the calculation work 2 (S2053). As described above, as the calculation work 1 (numerator) is composed of 4 bytes, the calculation work 2 (denominator) is also 4 bytes (however, like the calculation work 1 (numerator), the effective bit is 31 bits). Consists of. However, the calculation work address 2 (denominator) may also be configured with 4 bytes as in the calculation work 2 (denominator).

Next, the main CPU 101 multiplies the data of the calculation work 1 (numerator) by 100 (S2054). In this ratio calculation process, as will be described later, the 100% (percentage) is calculated by dividing the data of the calculation work 1 (molecule) by the data of the calculation work 2 (denominator). Therefore, in this process, the numerator is multiplied by 100 in advance so that the quotient calculated at that time becomes an integer. The data of the calculation work 1 (numerator) may be divided by the data of the calculation work 2 (denominator) and then multiplied by 100 to calculate the quotient. Further, when the ratio information is displayed on the combination ratio monitor 95, the value multiplied by 100 may be displayed. Further, it is possible to appropriately change how many times the data of the calculation work 1 (numerator) is multiplied according to the ratio information to be calculated.

Next, the main CPU 101 sets the highest address (that is, the 4th byte) of the calculation work 1 (numerator) and sets the highest address (that is, the 4th byte) of the calculation work 2 (denominator) (S2055). ). Next, the main CPU 101 sets 2 in the search counter and 0 in the shift counter (S2056).

Next, the main CPU 101 performs a logical sum operation of 1 byte of data of the calculation work 1 (numerator) and 1 byte of data of the calculation work 2 (denominator) (S2057). Next, the main CPU 101 determines whether or not the value of the OR operation is 0 (S2058). That is, the main CPU 101 determines whether or not the data for one byte of the search target stored in the calculation work 1 (numerator) and the calculation work 2 (denominator) are both 0.

In S2058, when the main CPU 101 determines that the value of the OR operation is not 0 (when the determination in S2058 is NO), the main CPU 101 shifts the process to the process of S2062. On the other hand, in S2058, when the main CPU 101 determines that the value of the OR operation is 0 (when the determination in S2058 is YES), the main CPU 101 updates the address of the calculation work 1 (numerator) by -1 and at the same time. The address of the calculation work 2 (denominator) is updated by -1 (S2059).

Next, the main CPU 101 subtracts 1 from the search counter set (S2060). That is, the main CPU 101 subtracts 1 from the value of the search counter. Next, the main CPU 101 determines whether or not the search counter is 0 (S2061). In S2061, when the main CPU 101 determines that the search counter is not 0 (when the determination in S2061 is NO), the main CPU 101 returns the process to the process in S2057. On the other hand, in S2061, when the main CPU 101 determines that the search counter is 0 (when the determination in S2061 is YES), the main CPU 101 shifts the processing to the processing of S2065 described later.

In S2058, when the main CPU 101 determines that the value of the OR operation is not 0 (when the determination in S2058 is NO), the main CPU 101 shifts the value of the OR operation to the right (S2062). Next, the main CPU 101 determines whether or not the value of the least significant bit is 1 as a result of the processing of S2062 (S2063). That is, the main CPU 101 searches for a bit string that is 1 at the highest level within the range of the maximum value to be aggregated (for example, "175000" of the total number of games) according to the result of the OR operation.

In S2063, when the main CPU 101 determines that the value of the least significant bit is 1 (when the determination in S2063 is YES), the main CPU 101 shifts the process to the process of S2065 described later. On the other hand, in S2063, when the main CPU 101 determines that the value of the least significant bit is not 1 (when the determination in S2063 is NO), the main CPU 101 adds 1 to the shift counter (S2064). After the processing of S2064, the main CPU 101 returns the processing to the processing of S2062.

When S2061 is a YES determination and S2063 is a YES determination, the main CPU 101 determines whether or not the value of the shift counter is 0 (S2065). In S2065, when the main CPU 101 determines that the value of the shift counter is not 0 (when the determination in S2065 is NO), the main CPU 101 performs the calculation work 1 (numerator) for 2-byte calculation based on the value of the shift counter. In addition to the shift processing, the calculation work 2 (denominator) is shifted for 2-byte calculation (S206). That is, the main CPU 101 has data for 2 bytes from the bit string that is 1 at the highest level within the range of the maximum value to be aggregated (for example, "175000" of the total number of games) according to the result of the OR calculation. Is extracted by each of the calculation work 1 (numerator) and the calculation work 2 (denominator) and stored in the lower 2 bytes.

On the other hand, in S2065, when the main CPU 101 determines that the value of the shift counter is 0 (when the determination in S2065 is YES), and after the processing of S2066, the main CPU 101 performs the calculation work 1 (numerator) and the calculation work 2 Two bytes (lower two bytes) of data (numerator and denominator) are acquired from (denominator) (S2067).

Next, the main CPU 101 divides the acquired numerator by the acquired denominator to calculate the quotient (S2068). Next, the main CPU 101 multiplies the value of the original calculation work 2 (denominator) by the calculated quotient (S2069). Next, the main CPU 101 compares the multiplication result of S2069 with the value after multiplying the value of the original calculation work 1 (numerator) by 100 (S2070).

Next, the main CPU 101 corrects the value of the quotient (ratio) based on the comparison result of S2070 (S2071). Specifically, the main CPU 101 performs a correction process of subtracting 1 from the quotient (ratio) value when the multiplication result of S2069 is larger than the value after multiplying the value of the original calculation work 1 (numerator) by 100. I do. In this process, an appropriate correction process may be performed so that the value of the quotient (ratio) calculated as an approximate value is less likely to cause an error with the true value. Therefore, the correction process may be performed by setting the comparison target of S2070 to another numerical value and performing another calculation. That is, in this correction process, all operations for making it difficult for an error to occur between the calculated approximate value and the true value can be adopted.

Next, the main CPU 101 determines whether or not the quotient (ratio) is 100 or more (S2072). Normally, the quotient (ratio) does not exceed 100, so in this process, it may be determined whether or not the quotient (ratio) is 100. Further, in this case, if it is determined that the number exceeds 100, this may be used as an error factor and error processing (see FIG. 90) may be performed.

In S2072, when the main CPU 101 determines that the quotient (ratio) is 100 or more (when the determination in S2072 is YES), the main CPU 101 subtracts 1 from the quotient (ratio) (S2073). This is because, in the present embodiment, as described above, the combination ratio monitor 95 can display only numerical values up to two digits. Then, after the processing of S2073, the main CPU 101 ends the ratio calculation processing (approximate value formula), and shifts the processing to the processing of S2044 in the ratio calculation data setting processing (see FIG. 157). On the other hand, in S2072, when the main CPU 101 determines that the quotient (ratio) is not 100 or more (when the determination in S2072 is NO), the main CPU 101 ends the ratio calculation process (approximate value formula) and calculates the ratio. The process is transferred to S2044 during the data setting process (see FIG. 157).

[Ratio calculation process (loop type)]
Next, with reference to FIG. 160, a second aspect (loop type) of the ratio calculation process that can be performed in S2043 of the ratio calculation data setting process (see FIG. 157) will be described. Note that FIG. 160 is a flowchart showing the procedure of the ratio calculation process (loop type).

First, the main CPU 101 determines whether or not the value of the calculation work address 2 (denominator) is 0 (S2081). In S2081, when the main CPU 101 determines that the value of the calculation work address 2 (denominator) is 0 (when the determination in S2081 is YES), the main CPU 101 ends the ratio calculation process (loop type) and processes it. Is moved to the process of S2044 in the ratio calculation data setting process (see FIG. 157).

On the other hand, in S2081, when the main CPU 101 determines that the value of the calculation work address 2 (denominator) is not 0 (when the determination in S2081 is NO), the main CPU 101 inputs the data of the calculation work address 1 (numerator). Transfer to the calculation work 1 (S2082). Since the configurations of the calculation work address 1 (molecule) and the calculation work 1 (molecule) are the same as those in the first aspect, the description thereof is omitted here.

Next, the main CPU 101 transfers the data of the calculation work address 2 (denominator) to the calculation work 2 (S2083). Since the configuration of the calculation work address 2 (denominator) and the calculation work 2 (denominator) is the same as that in the first aspect, the description thereof is omitted here.

Next, the main CPU 101 sets the number of display digit loops to 2 (S2084). The number of display digit loops is the loop processing described later (S2087 described later) in order to calculate the values displayed in the 10th place (see FIG. 8) and the 1st place (see FIG. 8) of the ratio monitor 95, respectively. ~ S2092) is defined as the number of times to be repeated. Next, the main CPU 101 multiplies the data of the calculation work 1 (numerator) by 100 (S2085).

Next, the main CPU 101 sets the number of subtraction loops to 0 (S2086). The number of subtraction loops counts the number of times the loop processing described later (S2087 to S2092 described later) is repeated, and the counting result is the ratio 10th place (see FIG. 8) and the ratio 1 of the combination monitor 95. It is the value displayed in the place of (see FIG. 8). That is, the main CPU 101 sets the initial value of the number of subtraction loops in this process.

Next, the main CPU 101 determines whether or not the value stored in the calculation work 1 (numerator) is smaller than the value stored in the calculation work 2 (denominator) (S2087). In S2087, when the main CPU 101 determines that the value stored in the calculation work 1 (numerator) is smaller than the value stored in the calculation work 2 (denominator) (when the determination in S2087 is YES). ), The main CPU 101 shifts the processing to S2093, which will be described later. That is, the main CPU 101 ends the loop processing.

On the other hand, in S2087, when the main CPU 101 determines that the value stored in the calculation work 1 (numerator) is larger than the value stored in the calculation work 2 (denominator) (S2087 determines NO). In the case of), the main CPU 101 sets the calculation work 1 (numerator) and the calculation work 2 (denominator) (S2088).

Next, the main CPU 101 subtracts the value of the lower 2 bytes of the calculation work 2 (denominator) from the value of the lower 2 bytes of the calculation work 1 (numerator), and converts the subtraction result into the lower 2 bytes of the calculation work 1 (numerator). Store (S2089). Next, the main CPU 101 subtracts the value of the upper 2 bytes of the calculation work 2 (denominator) from the value of the upper 2 bytes of the calculation work 1 (molecule), further subtracts the upper digit (borrows the digit), and subtracts the value. The result is stored in the upper 2 bytes of the calculation work 1 (molecule) (S2090).

Next, the main CPU 101 adds 1 to the number of subtraction loops (S2091). Next, the main CPU 101 determines whether or not the number of subtraction loops is 9 or more (S2092). In S2092, when the main CPU 101 determines that the number of subtraction loops is 9 or more (when the determination in S2092 is YES), the main CPU 101 shifts the processing to S2093 described later. That is, the main CPU 101 ends the loop processing. On the other hand, in S2092, when the main CPU 101 determines that the number of subtraction loops is not 9 or more (when the determination in S2092 is NO), the main CPU 101 returns the process to the process of S2087. That is, the main CPU 101 continues (loops) the loop processing.

In S2087, when the main CPU 101 determines that the value stored in the calculation work 1 (numerator) is smaller than the value stored in the calculation work 2 (denominator) (when the determination in S2087 is YES). ), And in S2092, when the main CPU 101 determines that the number of subtraction loops is 9 or more (when the determination in S2092 is YES), the main CPU 101 saves the calculation result (the number of subtraction loops) (S2093). By this process, one digit of the ratio information displayed on the combination ratio monitor 95 is saved.

Next, the main CPU 101 subtracts 1 from the number of display digit loops (S2094). Next, the main CPU 101 determines whether or not the number of display digit loops is 0 (S2095). In S2095, when the main CPU 101 determines that the number of display digit loops is not 0 (when the determination in S2095 is NO), the main CPU 101 returns the process to the process of S2086.

On the other hand, in S2095, when the main CPU 101 determines that the number of display digit loops is 0 (when the determination in S2095 is YES), the main CPU 101 determines the display data (ratio) from the stored calculation result (number of subtraction loops). Information) is calculated (S2096). That is, the main CPU 101 calculates the values displayed in the ratio 10's place (see FIG. 8) and the ratio 1's place (see FIG. 8) of the combination monitor 95 based on the number of stored subtraction loops. .. Then, after the processing of S2063, the main CPU 101 ends the ratio calculation processing (loop type), and shifts the processing to the processing of S2044 in the ratio calculation data setting processing (see FIG. 157). The processing of S2087 to S2092 of this ratio calculation processing (loop type) is a general method for constructing a program for calculating a value of 3 bytes or more in an 8-bit CPU.

As described above, in the present embodiment, the first aspect (approximate value formula) and the second aspect (loop formula) have been described as modes of the ratio calculation process. Here, in the first aspect (approximate value expression), as compared with the second aspect (loop expression), the processing load related to the ratio calculation is less because the above-mentioned loop processing is not performed, and the stability of the game operation is stable. There is an advantage that can be secured.

Therefore, in the present embodiment, as a general rule, the ratio calculation process performed in S2043 in the ratio calculation data setting process (see FIG. 157) adopts the first aspect (approximate value formula). This makes it possible to derive desired ratio information without imposing an excessive burden on the main control circuit 90 mounted on the pachislot machine 1. However, the second aspect (loop type) of the ratio calculation process can be adopted depending on the content of the ratio calculation and the circuit configuration of the main control circuit 90, and the first aspect (approximate) of the ratio calculation process. It is also possible to properly use the value formula) and the second aspect (loop formula) of the ratio calculation process.

Further, in the present embodiment, in the first aspect (approximate value formula) of the ratio calculation process, an appropriate correction process is performed on the calculated ratio information. This makes it possible to prevent an error from occurring between the true value and the ratio information even when the ratio information is calculated based on the approximate value.

[Aggregation of the number of payouts]
Next, with reference to FIG. 161, the payout number totaling process performed in S2012 of the combination monitor totaling process (see FIG. 155) will be described. Note that FIG. 161 is a flowchart showing a procedure for counting the number of payouts.

First, the main CPU 101 determines whether or not the number of payouts is 0 (S2101). That is, the main CPU 101 determines whether or not the medal has been paid out in this game. In this process, it may be determined whether or not the number of payouts is 0 without considering the number of inserts, or whether or not the number of payouts is 0 is determined in consideration of the number of inserts. You may try to do it. For example, when three medals are inserted and three medals are paid out in this game, the number of medals to be paid out is 3 in the former, but the number of medals to be paid out is 0 in the latter case. In short, in the payout number totaling process, the payout number may be simply totaled, or the net increase number may be totaled.

In S2101, when the main CPU 101 determines that the number of payouts is 0 (when the determination in S2101 is YES), the main CPU 101 ends the payout number totaling process and performs the process in the role ratio monitor totaling process (see FIG. 155). Move to the processing of S2013 inside. On the other hand, in S2101, when the main CPU 101 determines that the number of payouts is not 0 (when the determination in S2101 is NO), the main CPU 101 is composed of 3 bytes (may be 2 bytes) and has a predetermined game period (may be 2 bytes). A 3-byte addition process is performed in which the current payout number is added to the data (6000G payout number) stored in the medium-time payout number storage area for totaling the payout number in (6000 times) (S2102). The detailed description of the 3-byte addition process will be omitted (the same applies hereinafter).

Next, the main CPU 101 determines whether or not the combination monitor state is the state where the total payout number upper limit is reached (S2103). In the present embodiment, the upper limit of the total number of payouts that can be totaled is set to "16777215" (3 bytes), and in this process, it is determined whether or not the total number of payouts that can be totaled has reached the upper limit. The upper limit of the total number of payouts that can be totaled can be changed as appropriate. For example, the upper limit of the total number of games that can be totaled may be set to "42949677295" (4 bytes). Further, for example, a predetermined value within the range of 3 bytes (for example, "210000") may be set.

In S2103, when the main CPU 101 determines that the combination ratio monitoring state is the state in which the upper limit of the total number of payouts has been reached (when the determination in S2103 is YES), the main CPU 101 shifts the processing to the processing of S2107 described later. On the other hand, in S2103, when the main CPU 101 determines that the winning combination monitor state is not the state where the upper limit of the total number of payouts has been reached (when the determination in S2103 is NO), the main CPU 101 is composed of 3 bytes and totals the total number of payouts. A 3-byte addition process is performed in which the current payout number is added to the data (total payout number) stored in the payout number storage area (S2104).

Next, the main CPU 101 determines whether or not the data stored in the total payout number storage area has reached the upper limit (S2105). In S2105, when the main CPU 101 determines that the data stored in the total payout number storage area has not reached the upper limit (when the determination in S2105 is NO), the main CPU 101 shifts the processing to the processing of S2107 described later. Transfer. On the other hand, in S2105, when the main CPU 101 determines that the data stored in the total payout number storage area has reached the upper limit (when the determination in S2105 is YES), the main CPU 101 is in the role ratio monitor state and the total payout number is reached. The upper limit reached state is set (S2106).

In S2103, when the main CPU 101 determines that the combination monitor state is the state where the total payout number upper limit is reached (when the determination in S2103 is YES), in S2105, the main CPU 101 is stored in the total payout number storage area. When it is determined that the data has not reached the upper limit (when the determination in S2105 is NO), and after the processing in S2106, the main CPU 101 acquires a special prize signal (see FIG. 177 described later) described later (S2107).

Next, the main CPU 101 outputs a special prize signal indicating the operation of SB (ordinary accessory), CB (type 2 special accessory), or RB (type 1 special accessory) with respect to the acquired special prize signal. It is determined whether or not it is (generated) (S2108). That is, in this process, the main CPU 101 determines whether or not any of the installed bonuses (special bonuses) is in operation. In addition, in this embodiment, SB (ordinary accessory) and CB (type 2 special accessory) are not mounted, and RB (type 1 special accessory) is always in the BB (accessory continuous operation device). Things) are supposed to work.

In S2108, the main CPU 101 does not output (generate) a special prize signal indicating the operation of SB (ordinary accessory), CB (type 2 special accessory), or RB (type 1 special accessory). When it is determined (when the determination in S2108 is NO), the main CPU 101 shifts the processing to the processing in S2116 described later. On the other hand, in S2108, the main CPU 101 outputs (generates) a special prize signal indicating the operation of either SB (ordinary accessory), CB (type 2 special accessory), or RB (type 1 special accessory). When it is determined that the signal has been output (when the determination in S2108 is YES), the main CPU 101 determines whether or not the special prize signal being output (generated) is RB (Type 1 special accessory) (S2109). ..

In S2109, when the main CPU 101 determines that the special prize signal being output (generated) is not an RB (type 1 special accessory) (when the determination in S2109 is NO), the main CPU 101 performs processing in S2113 described later. Move to processing. On the other hand, when the main CPU 101 determines that the special prize signal being output (generated) is RB (type 1 special accessory) (when the determination in S2109 is YES), the main CPU 101 has 3 bytes (2 bytes). Data (6000G continuous combination of payout buffer) stored in the medium-time continuous combination payout number storage area, which is composed of (may be) and aggregates the number of payouts due to the operation of BB (RB) in a predetermined game period (6000 times). A 3-byte addition process is performed in which the number of items to be paid out this time is added to the number of items to be paid out (S2110).

Next, the main CPU 101 determines whether or not the combination monitor state is the state where the total payout number upper limit is reached (S2111). In S2111, when the main CPU 101 determines that the winning combination monitor state is not the total payout number upper limit reached state (when the determination in S2111 is NO), the main CPU 101 is composed of 3 bytes and the total payout is performed by the operation of the BB (RB). A 3-byte addition process that updates (adds) the data (total number of consecutive payouts) stored in the total number of consecutive payouts storage area, based on the update (addition) result of the medium-time consecutive payout number storage area. (S2112). In S2112, the main CPU 101 may perform a process of adding the current payout number to the data stored in the total consecutive payout number storage area, as in the process of S2110 described above.

When the main CPU 101 determines in S2109 that the special prize signal being output (generated) is not RB (type 1 special accessory) (when the determination in S2109 is NO), in S2111, the main CPU 101 monitors the role ratio. When it is determined that the total payout number upper limit has been reached (when the determination in S2111 is YES), and after the processing in S2112, the main CPU 101 is composed of 3 bytes (may be 2 bytes) and is a predetermined game. Add the number of payouts this time to the data (the number of payouts of the 6000G payout buffer) stored in the medium-time payout number storage area, which aggregates the number of payouts due to the operation of all the payouts during the period (6000 times). A 3-byte addition process is performed (S2113).

Next, the main CPU 101 determines whether or not the combination monitor state is the state where the total payout number upper limit is reached (S2114). In S2114, when the main CPU 101 determines that the combination monitor state is the total payout number upper limit reached state (when the determination in S2114 is YES), the main CPU 101 ends the payout number counting process and performs the process in the combination monitor. The process proceeds to S2013 during the aggregation process (see FIG. 155).

On the other hand, in S2114, when the main CPU 101 determines that the combination ratio monitoring state is not the total payout number upper limit reached state (when the determination in S2114 is NO), the main CPU 101 is composed of 3 bytes and depends on the operation of all the accessories. The data (total number of payouts) stored in the total number of payouts storage area for totaling the total number of payouts is updated (added) based on the update (addition) result of the medium-time payout number storage area. A 3-byte addition process is performed (S2115). In S2115, the main CPU 101 may perform a process of adding the current payout number to the data stored in the total bonus payout number storage area, as in the process of S2113 described above.

In S2108, the main CPU 101 does not output (generate) a special prize signal indicating the operation of SB (ordinary accessory), CB (type 2 special accessory), or RB (type 1 special accessory). When it is determined (when S2108 is NO determination), and after the processing of S2115, the main CPU 101 determines whether or not the combination ratio monitoring state is the total payout number upper limit reached state (S2116). In S2116, when the main CPU 101 determines that the combination monitor state is the total payout number upper limit reached state (when the determination in S2116 is YES), the main CPU 101 ends the payout number counting process and performs the process in the combination monitor. The process proceeds to S2013 during the aggregation process (see FIG. 155).

On the other hand, in S2116, when the main CPU 101 determines that the combination ratio monitoring state is not the total payout number upper limit reached state (NO determination in S2116), the main CPU 101 sets the accessory and the consecutive combination ratio calculation table 1. (S2117). In this embodiment, the accessory and joint combination ratio calculation table 1 (calculation data table for calculating the total consecutive combination ratio and the total combination ratio) is a total consecutive combination payout number storage area, a total payout number storage area, and a total ream. It is a table in which addresses are specified in the order of a combination ratio display data storage area, a total bonus number payout number storage area, a total payout number storage area, a total bonus ratio display data storage area, and an end code.

Next, the main CPU 101 performs a ratio calculation data setting process (see FIG. 157) (S2118). The ratio calculation data setting process is as described above, and the description thereof is omitted here. Then, after the process of S2118, the main CPU 101 ends the payout number counting process, and shifts the process to the process of S2013 in the combination monitor totaling process (see FIG. 155).

[Medium-time aggregation processing]
Next, with reference to FIG. 162, the medium-time aggregation process performed in S2013 of the combination monitor aggregation process (see FIG. 155) will be described. Note that FIG. 162 is a flowchart showing the procedure of the medium-time aggregation process.

First, the main CPU 101 determines whether or not the 3000G management counter is less than 3000 (S2121). The 3000G management counter is a counter that counts the number of games after a predetermined initialization condition is satisfied (for example, a setting change has been made) for display control of the combination monitor 95, and will be described later. In addition, the medium-time continuous combination ratio and the medium-time bonus ratio are not calculated until the 3000G management counter reaches 3000.

In S2121, when the main CPU 101 determines that the 3000G management counter is less than 3000 (when the determination in S2121 is YES), the main CPU 101 adds 1 to the 3000G management counter (S2122). Then, after the processing of S2122, the main CPU 101 ends the medium-time aggregation processing, also ends the combination monitor aggregation processing (see FIG. 155), and shifts the processing to the processing of S218 in the main flow (see FIG. 82).

On the other hand, in S2121, when the main CPU 101 determines that the 3000G management counter is not less than 3000 (when the determination in S2121 is YES), the main CPU 101 calculates the 6000G payout buffer address from the buffer selection pointer (S21223). That is, the main CPU 101 calculates the address of an area such as a medium-time bonus payout number storage area as a buffer area. The buffer selection pointer is identification information for designating the position (address) of the buffer area.

Next, the main CPU 101 determines whether or not the combination monitor state is the 6000 G reaching state (see FIG. 156) (S2124). In S2124, when the main CPU 101 determines that the winning ratio monitor state is not the 6000G reaching state (when the determination in S2124 is NO), the main CPU 101 shifts the process to S2126 described later. When the main CPU 101 determines in S2124 that the combination monitor state is not the 6000G reached state (NO determination in S2124), the main CPU 101 ends the medium-time aggregation process and performs the combination monitor aggregation process (FIG. FIG. (Refer to 155) may also be completed, and the processing may be transferred to the processing of S218 in the main flow (see FIG. 82).

On the other hand, in S2124, when the main CPU 101 determines that the combination monitor state has reached 6000G (when the determination in S2124 is YES), the main CPU 101 uses the data stored in the calculated 6000G payout buffer. It is transferred to the medium-time payout number storage area of the object and the continuous combination ratio calculation table 2 (S2125).

In S2124, when the main CPU 101 determines that the combination monitor state is not the 6000G reached state (when the determination in S2124 is NO), and after the processing of S2125, the main CPU 101 sets the accessory and the consecutive combination ratio calculation table 2. (S2126). In the present embodiment, the accessory and consecutive combination ratio calculation table 2 (calculation data table for calculating the medium-time consecutive combination ratio and the medium-time consecutive combination ratio) is a medium-time continuous combination payout number storage area and medium-time. Addresses were specified in the order of payout number storage area, medium-time consecutive combination ratio display data storage area, medium-time bonus payout number storage area, medium-time payout number storage area, medium-time bonus ratio display data storage area, and end code. It's a table.

Next, the main CPU 101 performs a ratio calculation data setting process (see FIG. 157) (S2127). The ratio calculation data setting process is as described above, and the description thereof is omitted here. Next, the main CPU 101 clears the 6000G payout buffer from the buffer selection pointer (S2128). Next, the main CPU 101 adds 1 to the buffer selection pointer (S2129). In the process of S2129, when the buffer selection pointer becomes 2, the buffer selection pointer is cleared to 0. Then, after the processing of S2129, the main CPU 101 ends the medium-time aggregation processing, also ends the combination monitor aggregation processing (see FIG. 155), and shifts the processing to the processing of S218 in the main flow (see FIG. 82).

[BB check process]
Next, the BB check process performed in S218 in the main flow (see FIG. 82) will be described with reference to FIG. 163. Note that FIG. 163 is a flowchart showing the procedure of the BB check process.

First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S821). In S821, when the main CPU 101 determines that the current gaming state is not the bonus state (when the determination in S821 is NO), the main CPU 101 performs the process of S832 described later.

On the other hand, in S821, when the main CPU 101 determines that the current gaming state is the bonus state (when the determination in S821 is YES), the main CPU 101 is for counting the number of medals that can be paid out during the bonus state. The number of medals paid out in the winning check / medal payout process is subtracted from the value of the BB payout number counter (S822).

Next, the main CPU 101 determines whether or not the value of the BB payout number counter is less than "0" (S823). In S823, when the main CPU 101 determines that the value of the payout number counter in BB is not less than "0" (when the determination in S823 is NO), the main CPU 101 ends the BB check process and performs the process in the main flow (FIG. (Refer to 82), the process proceeds to S219.

On the other hand, in S823, when the main CPU 101 determines that the value of the payout number counter in BB is less than "0" (when the determination in S823 is YES), the main CPU 101 performs the bonus end processing (S824). In this process, the main CPU 101 clears various information in the bonus state and sets the RT1 state flag to the on state.

Next, the main CPU 101 refers to the CT lottery table at the end of the bonus (see FIG. 60) and performs the CT lottery at the end of the bonus (S825). Next, the main CPU 101 determines whether or not the CT lottery at the end of the bonus has been won (S826).

In S826, when the main CPU 101 determines that the CT lottery has not been won (when the determination in S826 is NO), the main CPU 101 performs the process of S828 described later. On the other hand, in S826, when the main CPU 101 determines that the CT lottery has been won (when the determination in S826 is YES), the main CPU 101 adds "1" to the number of CT sets (S827). If the CT lottery is won when the number of ART sets is "0", "1" is added to the number of CT sets and "1" is also added to the number of ART sets in the processing of S827. ..

After the processing of S827 or when the determination in S826 is NO, the main CPU 101 determines whether or not the number of ART sets or the number of CT sets is "1" or more (S828).

In S828, when the main CPU 101 determines that the number of ART sets or the number of CT sets is "1" or more (when the determination in S828 is YES), the main CPU 101 sets the ART preparation state in the game state of the next game. (S829). Then, after the processing of S829, the main CPU 101 ends the BB check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

On the other hand, in S828, when the main CPU 101 determines that the number of ART sets or the number of CT sets is not "1" or more (when the determination in S828 is NO), the main CPU 101 sets the normal game state to the game state of the next game. (S830). Next, the main CPU 101 draws the lottery state of CZ with reference to the normal medium-high probability lottery table (see FIG. 40B), and sets the lottery result (S831). Then, after the processing of S831, the main CPU 101 ends the BB check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

Here, returning to the process of S821 again, when the determination in S821 is NO, the main CPU 101 determines whether or not the symbol combination related to the BB combination (the symbol combination of the combination "C_BB1" or "C_BB2") is displayed. (S832). In S832, when the main CPU 101 determines that the symbol combination related to the BB combination is not displayed (when the determination in S832 is NO), the main CPU 101 ends the BB check process and performs the process in the main flow (see FIG. 82). Move to the processing of S219 inside.

On the other hand, in S832, when the main CPU 101 determines that the symbol combination related to the BB combination is displayed (when the determination in S832 is YES), the main CPU 101 refers to the bonus type lottery table (see FIG. 58) and gives a bonus. The type is drawn and the lottery result is set (S833). Next, the main CPU 101 sets a predetermined value (the number of payouts that triggers the end of the bonus: "216" in the present embodiment) to the value of the payout number counter during BB (S834).

Next, the main CPU 101 performs a bonus start processing (S835). In this process, the main CPU 101 performs various processes necessary for starting the operation of the bonus, such as setting a bonus state in the game state of the next game. Then, after the processing of S835, the main CPU 101 ends the BB check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

[RT check processing]
Next, the RT check process performed in S219 in the main flow (see FIG. 82) will be described with reference to FIGS. 164 and 165. Note that FIGS. 164 and 165 are flowcharts showing the procedure of RT check processing.

First, the main CPU 101 determines whether or not the RT state is the RT5 state (S841). In S841, when the main CPU 101 determines that the RT state is the RT5 state (when the determination in S841 is YES), the main CPU 101 ends the RT check process and performs the process in S220 in the main flow (see FIG. 82). Move to the processing of.

On the other hand, in S841, when the main CPU 101 determines that the RT state is not the RT5 state (when the determination in S841 is NO), the main CPU 101 determines whether or not the RT state is the RT0 state (S842). In S842, when the main CPU 101 determines that the RT state is not the RT0 state (when the determination in S842 is NO), the main CPU 101 performs the process of S845 described later.

On the other hand, in S842, when the main CPU 101 determines that the RT state is the RT0 state (when the determination in S842 is YES), the main CPU 101 displays the symbol combination of the abbreviation "bell spilled eyes" (see FIG. 28). It is determined whether or not it is (S843). In S843, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" is not displayed (when the determination in S843 is NO), the main CPU 101 ends the RT check process and performs the process in the main flow (FIG. (Refer to 82), the process proceeds to S220.

On the other hand, in S843, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" is displayed (when the determination in S843 is YES), the main CPU 101 sets the RT2 state flag to the ON state (S844). .. By this process, the RT state shifts from the RT0 state to the RT2 state. Then, after the processing of S844, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S220 in the main flow (see FIG. 82).

Here, returning to the process of S842 again, when the determination in S842 is NO, the main CPU 101 determines whether or not the RT state is the RT1 state (S845). In S845, when the main CPU 101 determines that the RT state is not the RT1 state (when the determination in S845 is NO), the main CPU 101 performs the process of S850 described later.

On the other hand, in S845, when the main CPU 101 determines that the RT state is the RT1 state (when the determination in S845 is YES), the main CPU 101 determines whether or not the symbol combination of the abbreviation "bell spilled eye" is displayed. (S846).

In S846, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eye" is displayed (when the determination in S846 is YES), the main CPU 101 sets the RT1 state flag to the off state and sets the RT2 state flag. Is set to the on state (S847). By this process, the RT state shifts from the RT1 state to the RT2 state. Then, after the processing of S847, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S220 in the main flow (see FIG. 82).

On the other hand, in S846, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" is not displayed (when the determination in S846 is NO), the main CPU 101 determines whether or not 20 games have passed in the RT1 state. (S848).

In S848, when the main CPU 101 determines that 20 games in the RT1 state have not elapsed (NO in S848), the main CPU 101 ends the RT check process and performs the process in the main flow (see FIG. 82). ) Move to the processing of S220. On the other hand, in S848, when the main CPU 101 determines that 20 games have passed in the RT1 state (when the determination in S848 is YES), the main CPU 101 sets the RT1 state flag to the off state (S849). By this process, the RT state shifts from the RT1 state to the RT0 state. Then, after the processing of S849, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S220 in the main flow (see FIG. 82).

Here, returning to the process of S845 again, when S845 is a NO determination, the main CPU 101 determines whether or not the RT state is the RT2 state (S850). In S850, when the main CPU 101 determines that the RT state is not the RT2 state (when the determination in S850 is NO), the main CPU 101 performs the process of S853 described later.

On the other hand, in S850, when the main CPU 101 determines that the RT state is the RT2 state (when the determination in S850 is YES), the main CPU 101 displays the symbol combination (see FIG. 28) of the abbreviation "RT3 transition lip". It is determined whether or not it is present (S851). In S851, when the main CPU 101 determines that the symbol combination of the abbreviation "RT3 transition lip" is not displayed (when the determination in S851 is NO), the main CPU 101 ends the RT check process and performs the process in the main flow (FIG. (Refer to 82), the process proceeds to S220.

On the other hand, in S851, when the main CPU 101 determines that the symbol combination of the abbreviation "RT3 transition lip" is displayed (when the determination in S851 is YES), the main CPU 101 sets the RT2 state flag to the off state and RT3. The state flag is set to the on state (S852). By this process, the RT state shifts from the RT2 state to the RT3 state. Then, after the processing of S852, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S220 in the main flow (see FIG. 82).

Here, returning to the process of S850 again, when the determination in S850 is NO, the main CPU 101 determines whether or not the RT state is the RT3 state (S853). In S853, when the main CPU 101 determines that the RT state is not the RT3 state (when the determination in S853 is NO), the main CPU 101 performs the process of S862 described later.

On the other hand, in S853, when the main CPU 101 determines that the RT state is the RT3 state (when the determination in S853 is YES), the main CPU 101 displays the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip". It is determined whether or not it has been done (S854).

In S854, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is displayed (when the determination in S854 is YES), the main CPU 101 sets the RT3 state flag to the off state. At the same time, the RT2 state flag is set to the on state (S855). By this process, the RT state shifts from the RT3 state to the RT2 state. Then, after the processing of S855, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S220 in the main flow (see FIG. 82).

On the other hand, in S854, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is not displayed (when S854 is NO determination), the main CPU 101 is abbreviated as "RT4 transition". It is determined whether or not the symbol combination (see FIG. 28) of "Rip" is displayed (S856).

In S856, when the main CPU 101 determines that the symbol combination of the abbreviation "RT4 transition lip" is not displayed (when the determination in S856 is NO), the main CPU 101 ends the RT check process and performs the process in the main flow (when it is determined as NO). (Refer to FIG. 82), the process proceeds to S220. On the other hand, in S856, when the main CPU 101 determines that the symbol combination of the abbreviation "RT4 transition lip" is displayed (when the determination in S856 is YES), the main CPU 101 sets the RT3 state flag to the off state and RT4. The state flag is set to the on state (S857). By this process, the RT state shifts from the RT3 state to the RT4 state.

After the process of S857, the main CPU 101 determines whether or not the game state is the ART preparation state (S858). In S858, when the main CPU 101 determines that the gaming state is not the ART preparation state (when the determination in S858 is NO), the main CPU 101 ends the RT check process and performs the process in the main flow (see FIG. 82) S220. Move to the processing of.

On the other hand, in S858, when the main CPU 101 determines that the gaming state is the ART preparation state (when the determination in S858 is YES), the main CPU 101 determines whether or not the number of CT sets is "1" or more. (S859).

In S859, when the main CPU 101 determines that the number of CT sets is "1" or more (when the determination in S859 is YES), the main CPU 101 sets CT in the game state of the next game and sets the CT game number counter. Set "8" (S860). Then, after the processing of S860, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S220 in the main flow (see FIG. 82).

On the other hand, in S859, when the main CPU 101 determines that the number of CT sets is not "1" or more (when the determination in S859 is NO), the main CPU 101 sets the normal ART in the game state of the next game, and the ART end game. A predetermined value is set in the number counter (S861). Then, after the processing of S861, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S220 in the main flow (see FIG. 82).

Here, returning to the process of S853 again, when the determination in S853 is NO, the main CPU 101 determines whether or not the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is displayed (S862). In S862, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is not displayed (when the determination in S862 is NO), the main CPU 101 ends the RT check process. , The process is transferred to the process of S220 in the main flow (see FIG. 82).

On the other hand, in S862, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is displayed (when the determination in S862 is YES), the main CPU 101 turns off the RT4 state flag. At the same time, the RT2 state flag is set to the on state (S863). By this process, the RT state shifts from the RT4 state to the RT2 state. Then, after the processing of S863, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S220 in the main flow (see FIG. 82).

[Processing at the end of CZ / ART]
Next, with reference to FIG. 166, the processing at the end of CZ / ART performed in S220 in the main flow (see FIG. 82) will be described. Note that FIG. 166 is a flowchart showing a procedure for processing at the end of CZ / ART.

First, the main CPU 101 determines whether or not the current gaming state is at the time of CZ failure or at the end of ART (S871). In S871, when the main CPU 101 determines that the current gaming state is neither at the time of CZ failure nor at the end of ART (when the determination of S871 is NO), the main CPU 101 ends the processing at the end of CZ / ART. The process is transferred to the process of S201 in the main flow (see FIG. 82).

On the other hand, in S871, when the main CPU 101 determines that the current gaming state is either when the CZ fails or when the ART ends (when the determination in S871 is YES), the main CPU 101 uses the CZ lottery table (see FIG. 41B). ), The pullback lottery of CZ is performed (S872). Next, the main CPU 101 determines whether or not the CZ pullback lottery has been won (S873).

In S873, when the main CPU 101 determines that the CZ pullback lottery has been won (when the determination in S873 is YES), the main CPU 101 sets the winning type CZ in the game state of the next game (S874). Next, the main CPU 101 sets a value corresponding to the winning type of CZ in the CZ game number counter (S875). Then, after the processing of S875, the main CPU 101 ends the processing at the end of CZ / ART, and shifts the processing to the processing of S201 in the main flow (see FIG. 82).

On the other hand, in S873, when the main CPU 101 determines that the CZ pullback lottery has not been won (when the determination in S873 is NO), the main CPU 101 sets the normal game state to the game state of the next game (S876). Next, the main CPU 101 draws the lottery state of CZ with reference to the normal medium-high probability lottery table (see FIG. 40B), and sets the lottery result (S877). Then, after the processing of S877, the main CPU 101 ends the processing at the end of CZ / ART, and shifts the processing to the processing of S201 in the main flow (see FIG. 82).

[Interrupt processing controlled by the main CPU (1.1172 msec)]
Next, with reference to FIG. 167, the interrupt processing performed by the main CPU 101 at a cycle of 1.1172 msec will be described. Note that FIG. 167 is a flowchart showing the procedure of the interrupt process. The interrupt process repeatedly executed at a cycle of 1.1172 msec is generated based on the output timing of the timeout signal of the timer circuit 113 set in the initialization process of the timer circuit 113 (PTC) (see S2 in FIG. 64). This is a process executed when the interrupt request signal from the interrupt controller 112 is input to the main CPU 101.

First, the main CPU 101 performs a register save process (S901). Next, the main CPU 101 performs an input port check process (S902). In this process, signals input from various switches such as a stop switch are checked.

Next, the main CPU 101 performs a reel control process (S903). In this process, the main CPU 101 starts rotating the left reel 3L, the middle reel 3C, and the right reel 3R when all the reels are requested to start rotating, and then each reel rotates at a constant speed. Drive and control three stepping motors. When the number of sliding pieces is determined, the main CPU 101 updates the symbol counter of the corresponding reel by the number of sliding pieces. Then, the main CPU 101 waits for the updated symbol counter to match the value corresponding to the scheduled stop position (the symbol at the scheduled stop position reaches the area on the effective line of the display window) of the corresponding reel. The corresponding stepping motor is driven and controlled so that the rotation is decelerated and stopped.

Next, the main CPU 101 performs a communication data transmission process (S904). In this process, various commands stored in the communication data storage area are mainly transmitted to the sub-control circuit 200 via the first serial communication circuit 114 (see FIG. 9) of the main control circuit 90. After transmitting a command to the sub-control circuit 200, the main CPU 101 subtracts and updates the communication data pointer by one packet (not shown), and clears the transmitted command data in the communication data storage area. When a plurality of command data are stored in the communication data storage area, the command data is transmitted to the sub-control circuit 200 in the order of the oldest stored command data. Further, when the command data is not stored in the communication data storage area, that is, when the value of the communication data pointer is "0", a non-operation command is generated and transmitted to the sub-control circuit 200. Next, the main CPU 101 performs a insertion medal passage check process (S905). In this process, the main CPU 101 checks whether or not the inserted medal has passed the selector 66 based on the detection result (medal sensor input state) of the medal sensor (not shown). Next, the main CPU 101 performs the WDT restart process (S906).

Next, the main CPU 101 performs a 7-segment LED drive process (S907). In this process, the main CPU 101 drives and controls various 7-segment LEDs included in the information display 6, and displays, for example, the number of medals paid out, the number of credits, the stop button pressing order data, and the like. The details of the 7-segment LED drive process will be described later with reference to FIG. 168 described later.

Next, the main CPU 101 performs a timer update process (S908). In this process, the main CPU 101 performs a count (subtraction) process of various set timers. The details of the timer update process will be described later with reference to FIG. 173, which will be described later.

Next, the main CPU 101 performs an error detection process (S909). Next, the main CPU 101 performs a door open / close check process (S910). In the door open / close check process, the main CPU 101 checks the open / closed state of the front door 2b (see FIG. 2) by checking the on (door open) / off (door closed) state of the door open / close monitoring switch 67.

Next, the main CPU 101 performs a test firing test signal control process (S911). In this process, control process is performed when various test signals are output to the testing machine via the second interface boat or the like. Further, this process is executed using the non-standard work area (see FIG. 12C) of the main RAM 103. In the present embodiment, this process is also performed at a time other than the test firing test (after the pachislot machine 1 is installed in the game store), but at this time, the main control board 71 passes through the second interface boat or the like. Since it is not connected to the testing machine, various test signals are generated but not output. The details of the test firing test signal control process will be described later with reference to FIG. 175 described later.

Next, the main CPU 101 performs a register reset process (S912). Then, after the processing of S912, the main CPU 101 ends the interrupt processing.

[7-segment LED drive processing]
Next, the 7-segment LED drive process performed in S907 during the interrupt process (see FIG. 167) will be described with reference to FIGS. 168 and 169. Note that FIG. 168 is a flowchart showing the procedure of the 7-segment LED drive process. Further, FIG. 169A is a diagram showing an example of a source program for executing the processes of S923 to S925 described later during the 7-segment LED drive process, and FIG. 169B is a diagram showing S931 to be described later during the 7-segment LED drive process. It is a figure which shows an example of the source program for executing the process of S936.

First, the main CPU 101 adds (+1 update) to the value of the interrupt counter (S921). Next, the main CPU 101 determines whether or not the value of the interrupt counter is an odd number (S922).

In S922, when the main CPU 101 determines that the value of the interrupt counter is not an odd number (when the determination in S922 is NO), the main CPU 101 ends the 7-segment LED drive process and interrupts the process (see FIG. 167). ) Moves to the processing of S908. That is, in the present embodiment, the 7-segment LED drive process is performed every two interruption cycles. In the present embodiment, an example of executing the 7-segment LED drive process when the value of the interrupt counter is an even number has been described, but the present invention is not limited to this, and the 7-segment LED drive process is not limited to this when the value of the interrupt counter is an odd number. The LED drive process may be executed, or the execution timing of the 7-segment LED drive process may be determined by using the quotient or the remainder when the value of the interrupt counter is divided by an arbitrary integer.

On the other hand, in S922, when the main CPU 101 determines that the value of the interrupt counter is an odd number (when the determination in S922 is YES), the main CPU 101 acquires navigation data from the navigation data storage area (S923). Next, the main CPU 101 sets the address of the push order display data storage area for storing the push order display data output to each cathode of the 7-segment LED (S924).

Next, the main CPU 101 performs a 7-segment display data generation process (S925). In this process, the main CPU 101 creates push order display data (7-segment display data) based on the navigation data, and stores the generated push order display data in the push order display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 170 described later.

Next, the main CPU 101 acquires the value of the credit counter (S926). Next, the main CPU 101 sets the address of the credit display data storage area for storing the credit display data output to each cathode of the 7-segment LED (S927).

Next, the main CPU 101 performs a 7-segment display data generation process (S928). In this process, the main CPU 101 generates credit display data (7-segment display data) based on the value of the credit counter, and stores the generated credit display data in the credit display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 170 described later.

Next, the main CPU 101 sets the address of the 7-segment common counter storage area for storing the value of the 7-segment common counter described later (S929). Next, the main CPU 101 adds (+1 update) to the value of the 7-segment common counter (S930). In this process, when the updated 7-segment common counter value becomes "8", the main CPU 101 sets the 7-segment common counter value to "0". In the present embodiment, since the 7-segment LED is dynamically controlled, the value of the 7-segment common counter is updated every 8 times.

Next, the main CPU 101 creates common selection data based on the value of the 7-segment common counter, and addresses the target cathode data storage area (push order display data storage area or target storage area in the credit display data storage area). Is set (S931). Next, the main CPU 101 outputs clear data to the cathode of the 7-segment LED (S932). This process is performed in order to eliminate the influence of the afterimage by temporarily turning off the 7-segment LED.

Next, the main CPU 101 acquires and sets 7-segment cathode output data from the target cathode data storage area (S933). Next, the main CPU 101 generates 7-segment common output data from the 7-segment common backup data and the common selection data (S934).

Next, the main CPU 101 stores the 7-segment common output data and the 7-segment cathode output data in the 7-segment common backup data and the 7-segment cathode backup data, respectively (S935). Next, the main CPU 101 outputs 7-segment cathode output data and 7-segment common output data (S936). Then, after the processing of S936, the main CPU 101 ends the 7-segment LED drive processing, and shifts the processing to the processing of S908 in the interrupt processing (see FIG. 167).

In this embodiment, the 7-segment LED drive process is performed as described above. The processing of S923 to S925 during the above-mentioned 7-segment LED drive processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 169A. Further, the processes of S931 to S936 during the above-mentioned 7-segment LED drive process are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 169B.

Among them, the output processing of each 7-segment output data of S936 is executed by one source code "LD (cPA_SEGCOM), BC" as shown in FIG. 169B. Therefore, in the 7-segment LED drive process of the present embodiment, the 7-segment common output (selection) data and the 7-segment cathode output data are output at the same time when the 2-digit 7-segment LED is dynamically lit and controlled. That is, in the dynamic lighting control of the 7-segment LED when performing push order navigation on the instruction monitor, and the 7-segment common output (7-segment common output) in the dynamic lighting control of the 7-segment LED when displaying credit information with the 2-digit 7-segment LED. (Selection) data and 7-segment cathode output data are output at the same time.

In this case, the number of instruction codes required for the dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, it becomes possible to improve the playability. Further, in the present embodiment, an example in which a 7-segment drive circuit (not shown) that performs a 7-segment LED drive process is configured by a cathode common circuit and controlled by the cathode has been described, but the present invention is not limited to this, and 7 The seg drive circuit may be composed of an anode common circuit, and the 7-segment LED may be controlled by the anode.

Further, as shown in FIG. 169A, the Q register (extension register) is used for both the acquisition process of the navigation data of S923 and the address set process of the push display data storage area of S924 during the 7-segment LED drive process described above. It is executed by the "LDQ" instruction (instruction code dedicated to the main CPU 101) that specifies the address. Therefore, in the 7-segment LED drive process of the present embodiment, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by the direct value by using the "LDQ" instruction, so that the source program can be used. , The instruction related to the address setting can be omitted (it is not necessary to separately provide the instruction related to the address setting), and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[7-segment display data generation process]
Next, the 7-segment display data generation process performed in S925 and S928 in the 7-segment LED drive process (see FIG. 167) will be described with reference to FIGS. 170 to 172. Note that FIG. 170 is a flowchart showing the procedure of the 7-segment display data generation process. FIG. 171 is a diagram showing an example of a source program for executing the 7-segment display data generation process. Further, FIG. 172 is a diagram showing an example of the configuration of the 7-segment cathode table that is actually referred to on the source program of the 7-segment display data generation process.

The "display data" described later generated by the 7-segment display data generation process performed in S925 during the 7-segment LED drive process (see FIG. 168) corresponds to the push-order display data, and the 7-segment LED drive process (FIG. 168). The "display data" described later generated in the 7-segment display data generation process performed in S928 in (see 168) corresponds to the credit display data.

First, the main CPU 101 divides the display data set in the cathode data storage area by "10", acquires the quotient value of the division result as the display data of the upper digit of the 2-digit 7-segment LED, and divides the data. The remaining value of the result is acquired as the display data of the lower digit (S941). Next, the main CPU 101 determines whether or not to display the upper digit based on the acquired display data of the upper digit (S942).

When the main CPU 101 determines in S942 that the upper digit display is to be performed (when the determination in S942 is YES), the main CPU 101 performs the process of S944 described later. On the other hand, in S942, when the main CPU 101 determines that the upper digit is not displayed (NO in S942), the main CPU 101 sets no upper digit display (S943).

After the processing of S943 or when the determination in S942 is YES, the main CPU 101 refers to the 7-segment cathode table (see FIG. 172) and acquires the display data of the upper digit (S944). Next, the main CPU 101 saves the acquired high-order digit display data in the high-order digit display data storage area (not shown) (S945).

Next, the main CPU 101 refers to the 7-segment cathode table (see FIG. 172) and acquires the display data of the lower digits (S946). Next, the main CPU 101 saves the acquired low-order digit display data in the low-order digit display data storage area (not shown) (S947).

Then, after the processing of S947, the main CPU 101 ends the 7-segment display data generation processing. At this time, if the executed 7-segment display data generation process is the process of S925 in the 7-segment LED drive process (see FIG. 168), the main CPU 101 changes the process to the process of S926 during the 7-segment LED drive process. Transfer. On the other hand, when the executed 7-segment display data generation process is the process of S928 in the 7-segment LED drive process (see FIG. 168), the main CPU 101 shifts the process to the process of S929 in the 7-segment LED drive process. ..

In the present embodiment, the 7-segment display data generation process is performed as described above. The 7-segment display data generation process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 171.

[Timer update process]
Next, the timer update process performed in S908 during the interrupt process (see FIG. 167) will be described with reference to FIGS. 173 and 174. Note that FIG. 173 is a flowchart showing the procedure of the timer update process. Further, FIG. 174 is a diagram showing an example of a source program for executing the processes of S951 to S954 described later during the timer update process.

First, the main CPU 101 sets the update start address of the 2-byte timer storage area (not shown) in the HL register, and sets the number of 2-byte timers in the B register (S951).

Next, the main CPU 101 compares the number of 2-byte timers with the lower limit value "0", and if the number of 2-byte timers is larger than the lower limit value "0", subtracts 1 from the number of 2-byte timers (updates -1). When the number of 2-byte timers is equal to or less than the lower limit value "0", the number of 2-byte timers is held at "0" (S952). Further, in the process of S952, the main CPU 101 subtracts 2 (-2 updates) the update start address of the 2-byte timer storage area set in the HL register.

Next, the main CPU 101 subtracts (updates -1) the number of 2-byte timers set in the B register by 1 (S953). Next, the main CPU 101 determines whether or not the number of 2-byte timers set in the B register is "0" (S954).

In S954, when the main CPU 101 determines that the number of 2-byte timers set in the B register is not "0" (when the determination in S954 is NO), the main CPU 101 returns the processing to the processing of S952, and after S952. Repeat the process.

On the other hand, in S954, when the main CPU 101 determines that the number of 2-byte timers set in the B register is "0" (when the determination in S954 is YES), the main CPU 101 stores the 1-byte timer in the HL register. The update start address of is set, and the number of 1-byte timers is set in the B register (S955).

Next, the main CPU 101 compares the number of 1-byte timers with the lower limit value "0", and if the number of 1-byte timers is larger than the lower limit value "0", the number of 1-byte timers is subtracted by 1 (-1 update). However, when the number of 1-byte timers is equal to or less than the lower limit value "0", the number of 1-byte timers is held at "0" (S956). Further, in the process of S956, the main CPU 101 subtracts 1 (-1 update) the update start address of the 1-byte timer storage area set in the HL register.

Next, the main CPU 101 subtracts (updates -1) the number of 1-byte timers set in the B register by 1 (S957). Next, the main CPU 101 determines whether or not the number of 1-byte timers set in the B register is "0" (S958).

In S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is not "0" (when the determination in S958 is NO), the main CPU 101 returns the processing to the processing of S956, and after S956. Repeat the process.

On the other hand, in S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is "0" (when the determination in S958 is YES), the main CPU 101 performs an electromagnetic counter control process (S959). ). In this process, an output control process is performed when a signal indicating IN / OUT of the medal is output to the external centralized terminal plate 47. Then, after the processing of S959, the main CPU 101 ends the timer update processing, and shifts the processing to the processing of S909 in the interrupt processing (see FIG. 167).

In the present embodiment, the timer update process is performed as described above. The processing of S951 to S954 (update processing of the 2-byte timer) during the timer update processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 174.

Among them, the process of S952 (update process of the 2-byte timer) is executed by the "DCPWLD" instruction (predetermined update instruction) in FIG. 174. The "DCPWLD" instruction is an instruction code dedicated to the main CPU 101.

When, for example, the source code "DCPWLD (HL), n" is executed on the source program, the contents (stored data) of the memory for 2 bytes from the address specified in the HL register are compared with the integer n. If the contents of the memory for 2 bytes are larger than the integer n, the contents of the memory for 2 bytes are subtracted by 1, and if the contents of the memory for 2 bytes are not more than the integer n, they are specified in the HL register. The integer n is stored in the memory for 2 bytes from the address.

Therefore, in the source code "DCPWLD (HL), 0" in FIG. 174, the contents of the memory for 2 bytes (the number of 2-byte timers) and the integer "0" (lower limit value) from the address specified by the HL register are used. When the contents of the memory for 2 bytes are larger than the integer "0", the contents of the memory for 2 bytes are subtracted by 1, and the contents of the memory for 2 bytes are equal to or less than the integer "0". Is set to "0" in the contents of the memory for 2 bytes. That is, if the current number of 2-byte timers is larger than "0", the 2-byte timer update process is performed, and if the current number of 2-byte timers is "0" or less, the number of 2-byte timers is "0". Is held in.

As described above, in the timer update process of the present embodiment, both the process of updating (subtracting) the number of timers and the process of holding the number of timers at "0" are executed by the "DCPWLD" instruction which is the instruction code dedicated to the main CPU 101. can do. In this case, it is not necessary to provide an instruction code for executing both processes separately. Further, the determination branch instruction code for determining whether or not the number of timers is "0" can be omitted. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, it becomes possible to improve the playability. In the present embodiment, an example in which the "DCPWLD" instruction is used only in the update process of the 2-byte timer has been described, but the present invention is not limited to this, and the "DCWPLD" instruction is also used in the update process of the 1-byte timer. You may use it.

[Test firing test signal control processing (non-standard)]
Next, with reference to FIG. 175, the test firing test signal control process performed in S911 during the interrupt process (see FIG. 167) will be described. Note that FIG. 175 is a flowchart showing the procedure of the test firing test signal control process.

First, the main CPU 101 saves the address of the stack area of the main RAM 103 (S961). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S962). Next, the main CPU 101 saves the data of all the registers (S963).

Next, the main CPU 101 performs a rotating cylinder braking signal generation process (S964). In this process, the main CPU 101 generates and outputs a rotation control signal (drive signal) for each reel, which is output to the testing machine via the second interface boat or the like. The details of the rotating cylinder braking signal generation process will be described later with reference to FIG. 176, which will be described later.

Next, the main CPU 101 performs a special prize signal control process (S965). In this process, the main CPU 101 performs an output process of a bonus (special prize) ON / OFF signal (test signal) output to the testing machine. The details of the prize signal control process will be described later with reference to FIG. 177 described later.

Next, the main CPU 101 performs the condition device signal control process (S966). In this process, the main CPU 101 performs a control signal output process corresponding to the state of the condition device signal control flag. The details of the condition device signal control process will be described later with reference to FIGS. 178 and 179 described later.

Next, the main CPU 101 performs a combination monitor display management process (S967). In this process, the main CPU 101 controls the display content of the combination monitor 95 according to the result of the aggregation and the ratio calculation by the combination monitor aggregation process (see FIG. 155). The details of the combination monitor display management process will be described later with reference to FIGS. 180 and 181 described later.

Next, the main CPU 101 performs a restoration process of the data of all the registers saved in the process of S963 (S968). Next, the main CPU 101 sets the address of the stack area saved in the process of S961 in the stack pointer (SP) (S969). Then, after the processing of S969, the main CPU 101 ends the test firing test signal control processing, and shifts the processing to the processing of S912 in the interrupt processing (see FIG. 167).

[Rotating cylinder braking signal generation processing]
Next, with reference to FIG. 176, the rotating cylinder braking signal generation process performed in S964 during the test firing test signal control process (see FIG. 175) will be described. Note that FIG. 176 is a flowchart showing the procedure of the rotating cylinder braking signal generation processing.

First, the main CPU 101 sets a rotation cylinder control data storage area (not shown) in the non-standard work area (S971). Next, the main CPU 101 sets the number of reels to "3" and clears the rotation cylinder control signal and its generation state (1 byte data) (S972).

Next, the main CPU 101 determines whether or not the rotation control data is “less than stopped” data (S973). The "less than stopped" rotation control data here is rotation control data other than the rotation control data for stopping the reel, that is, rotation control data for rotationally driving the reel (acceleration). It is one of the states of preparation, acceleration, constant speed waiting, constant speed, and waiting for the stop start position).

In S973, when the main CPU 101 determines that the rotation control data is "less than stopped" data (when the determination in S973 is YES), the main CPU 101 performs the process of S975 described later. On the other hand, in S973, when the main CPU 101 determines that the rotation control data is not "less than stopped" data (when the determination in S973 is NO), the main CPU 101 determines that the rotation control data is "statically indeterminate hold control end". It is determined whether or not the data is (S974). The rotating cylinder control data of "statically indeterminate hold control end" referred to here is rotation cylinder control data indicating a state in which all phases and all phases of the reel are stopped.

In S974, when the main CPU 101 determines that the rotation control data is "statically indeterminate hold control end" data (when the determination in S974 is YES), the main CPU 101 performs the process of S976 described later. On the other hand, in S974, when the main CPU 101 determines that the rotation control data is not "statically indeterminate hold control end" data (when S974 is a NO determination), or when S973 is a YES determination, the main CPU 101 determines. Bit 3 of the rotation control signal generation state (1 byte data) is turned on (“1”) (S975).

After the processing of S975 or when the determination in S974 is NO, the main CPU 101 shifts the data of each bit in the generated state by one bit to the right (in the direction from bit 7 to bit 0) (S976). Next, the main CPU 101 updates the address of the rotating cylinder control data storage area to the address of the next reel to be controlled (S977).

Next, the main CPU 101 subtracts 1 from the number of reels (S978). Next, the main CPU 101 determines whether or not the number of reels is "0" (S979).

In S979, when the main CPU 101 determines that the number of reels is not "0" (when the determination in S979 is NO), the main CPU 101 returns the processing to the processing of S973 and repeats the processing after S973.

On the other hand, in S979, when the main CPU 101 determines that the number of reels is "0" (when the determination in S979 is YES), the main CPU 101 outputs the data in the generated state via the rotating cylinder braking signal output port. Output to the first interface board 301 (see FIG. 7) for use (S980). Then, after the processing of S980, the main CPU 101 ends the rotation cylinder braking signal generation processing, and shifts the processing to the processing of S965 in the test firing test signal control processing (see FIG. 175).

[Special prize signal control processing]
Next, with reference to FIG. 177, the special prize signal control process performed in S965 during the test firing test signal control process (see FIG. 175) will be described. Note that FIG. 177 is a flowchart showing the procedure of the special prize signal control process.

First, the main CPU 101 acquires the game state flag by referring to the game state flag storage area (see FIG. 32) (S991). Next, the main CPU 101 determines whether or not the gaming state is the RB gaming state (S992).

In S992, when the main CPU 101 determines that the gaming state is the RB gaming state (when the determination in S992 is YES), the main CPU 101 sends an ON signal from the RB medium signal port for the test signal to the first interface for the test machine. Output to board 301 (see FIG. 7) (S993). On the other hand, in S992, when the main CPU 101 determines that the gaming state is not the RB gaming state (when the determination in S992 is NO), the main CPU 101 sends an OFF signal from the RB medium signal port for the test signal to the first test machine. Output to the interface board 301 (see FIG. 7) (S994).

After the processing of S993 or S994, the main CPU 101 refers to the game state flag storage area (see FIG. 32) and determines whether or not the game state is the BB game state (S995).

In S995, when the main CPU 101 determines that the gaming state is the BB gaming state (when the determination in S995 is YES), the main CPU 101 sends an ON signal from the BB medium signal port for the test signal to the first interface for the test machine. Output to board 301 (see FIG. 7) (S996). On the other hand, in S995, when the main CPU 101 determines that the gaming state is not the BB gaming state (when the determination in S995 is NO), the main CPU 101 sends an OFF signal from the BB medium signal port for the test signal to the first test machine. Output to the interface board 301 (see FIG. 7) (S997).

Then, after the processing of S996 or S997, the main CPU 101 ends the special prize signal control processing, and shifts the processing to the processing of S966 in the test firing test signal control processing (see FIG. 175).

In the present embodiment, when the CB game state, the MB game state, or the SB game state is further provided, the same processing as described above is performed in the CB game state, the MB game state, or the SB game state. You may do it.

Specifically, after the processing of S998, when the main CPU 101 determines whether or not the gaming state is the CB gaming state, and the main CPU 101 determines that the gaming state is the CB gaming state, the test signal is used. While the ON signal is output from the CB medium signal port to the first interface board 301 for the tester (see FIG. 7), when it is determined that the gaming state is not the CB gaming state, the OFF signal is output from the CB medium signal port for the test signal. The output may be made to the first interface board 301 for the testing machine (see FIG. 7).

Further, after the processing, the main CPU 101 determines whether or not the gaming state is the MB gaming state, and when the main CPU 101 determines that the gaming state is the MB gaming state, the MB signal port for the test signal. While outputting the ON signal to the first interface board 301 for the tester (see FIG. 7), when it is determined that the gaming state is not the MB gaming state, the OFF signal is output from the MB medium signal port for the test signal to the tester. 1 Output to the interface board 301 (see FIG. 7) may be performed.

Further, after the processing, the main CPU 101 determines whether or not the gaming state is the SB gaming state, and when the main CPU 101 determines that the gaming state is the SB gaming state, the SB signal port for the test signal. While outputting the ON signal to the first interface board 301 for the tester (see FIG. 7), when it is determined that the gaming state is not the SB gaming state, the OFF signal is sent from the SB signal port for the test signal to the tester. 1 Output to the interface board 301 (see FIG. 7) may be performed.

[Condition device signal control processing]
Next, the condition device signal control process performed in S966 during the test firing test signal control process (see FIG. 175) will be described with reference to FIGS. 178 and 179. Note that FIGS. 178 and 179 are flowcharts showing the procedure of the condition device signal control process.

First, the main CPU 101 determines whether or not the condition device signal control flag is in the initial state (S1001). In S1001, when the main CPU 101 determines that the condition device signal control flag is in the initial state (when the determination in S1001 is YES), the main CPU 101 ends the condition device signal control process and performs the test firing test signal control process. (See FIG. 175) The process proceeds to S967.

On the other hand, in S1001, when the main CPU 101 determines that the condition device signal control flag is not in the initial state (when the determination in S1001 is NO), the main CPU 101 sets the condition device signal control flag to the ON state of the replay state identification signal. It is determined whether or not it is indicated (S1002).

In S1002, when the main CPU 101 determines that the condition device signal control flag indicates the ON state of the replay state identification signal (when the determination in S1002 is YES), the main CPU 101 serves the condition device signal control state. The ON state of the physical condition device signal is set (S1003). Next, the main CPU 101 outputs the RT state information from the condition devices 1 to 6 signal ports to the first interface board 301 for the testing machine (see FIG. 7) (S1004). Then, after the processing of S1004, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 175).

On the other hand, in S1002, when the main CPU 101 determines that the condition device signal control flag does not indicate the ON state of the replay state identification signal (when the determination in S1002 is NO), the condition device signal control flag is set in the main CPU 101. It is determined whether or not the re-game state identification signal indicates an off state (S1005).

In S1005, when the main CPU 101 determines that the condition device signal control flag indicates the off state of the replay state identification signal (when the determination in S1005 is YES), the main CPU 101 uses the condition devices 1 to 8 signal ports. Outputs the OFF signal from the first interface board 301 for the testing machine (see FIG. 7) (S1006). Then, after the processing of S1006, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 175).

On the other hand, in S1005, when the main CPU 101 determines that the condition device signal control flag does not indicate the off state of the replay state identification signal (when the determination in S1005 is NO), the main CPU 101 has the condition device signal control state. It is determined whether or not the accessory condition device signal is on (S1007).

In S1007, when the main CPU 101 determines that the condition device signal control state is the ON state of the accessory condition device signal (when the determination in S1007 is YES), the main CPU 101 wins a special prize from the condition devices 1 to 8 signal ports. The number information is output to the first interface board 301 for the testing machine (see FIG. 7), and at this time, the ON signal is output from the condition device 8 signal port to the first interface board 301 for the testing machine (see FIG. 7) (see FIG. 7). S1008). Next, the main CPU 101 sets a predetermined waiting time (24.58 ms in this embodiment) in the condition device signal output waiting timer (S1009). Next, the main CPU 101 sets the condition device signal control state to the state of waiting for the condition device signal output (S1010). Then, after the processing of S1010, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 175).

On the other hand, in S1007, when the main CPU 101 determines that the condition device signal control state is not the ON state of the accessory condition device signal (when the determination in S1007 is NO), the main CPU 101 has the condition device signal control state as the condition device signal. It is determined whether or not the output is waiting (S1011).

In S1011, when the main CPU 101 determines that the condition device signal control state is the state of waiting for the condition device signal output (when the determination of YES in S1011), the value of the condition device signal output wait timer of the main CPU 101 is "0". It is determined whether or not it is (S1012).

In S1012, when the main CPU 101 determines that the value of the condition device signal output waiting timer is not "0" (when the determination in S1012 is NO), the main CPU 101 ends the condition device signal control process and tests the process. The process shifts to the processing of S967 in the signal control processing (see FIG. 175). On the other hand, in S1012, when the main CPU 101 determines that the value of the condition device signal output waiting timer is "0" (when the determination in S1012 is YES), the main CPU 101 is in the condition device signal control state. The on state of the signal or the off state of the condition device signal is set (S1013). Then, after the processing of S1013, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 175).

Here, returning to the processing of S1011 again, when the main CPU 101 determines in S1011 that the condition device signal control state is not the state of waiting for the condition device signal output (when the determination in S1011 is NO), the main CPU 101 determines the condition. It is determined whether or not the device signal control state is the on state of the small combination condition device signal (S1014).

In S1014, when the main CPU 101 determines that the condition device signal control state is the on state of the small combination condition device signal (when the determination in S1014 is YES), the main CPU 101 has a small combination from the condition devices 1 to 8 signal ports. The winning number information is output to the first interface board 301 for the testing machine (see FIG. 7), and at this time, the ON signal is output from the condition device 7 signal port to the first interface board 301 for the testing machine (see FIG. 7). (S1015). Next, a predetermined waiting time (24.58 ms in this embodiment) is set in the condition device signal output waiting timer (S1016). Next, the main CPU 101 sets the condition device signal control state to the state of waiting for the condition device signal output (S1017). Then, after the processing of S1017, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 175).

On the other hand, in S1014, when the main CPU 101 determines that the condition device signal control state is not the ON state of the small winning combination condition device signal (when the determination in S1014 is NO), the main CPU 101 is turned off from the condition devices 1 to 8 signal ports. The signal is output to the first interface board 301 for the testing machine (see FIG. 7) (S1018). Then, after the processing of S1018, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 175).

[Ratio monitor display management process]
Next, the combination monitor display management process performed in S967 during the test firing test signal control process (see FIG. 175) will be described with reference to FIGS. 180 and 181. Note that FIGS. 180 and 181 are flowcharts showing the procedure of the combination monitor display management process.

First, the main CPU 101 determines whether or not the combination display mode is display (display on) (S2141). In S2141, when the main CPU 101 determines that the combination display mode is not display (display on) (non-display (display off)) (when S2141 is NO determination), the main CPU 101 initializes the display channel. (S2142).

Next, the main CPU 101 sets an initial value (timer value with a change interval of about 5 seconds) in the display update timer, and sets an initial value (timer value with about 0.6 seconds) in the blinking management timer (S2143). The display update timer is a timer that manages switching of display contents (type information and ratio information) on the role ratio monitor 95, and the blinking management timer is a timer that manages blinking of the display on the combination ratio monitor 95. Then, after the process of S2143, the main CPU 101 ends the combination monitor display management process, and shifts the process to the process of S968 in the test firing test signal control process (see FIG. 175).

On the other hand, in S2141, when the main CPU 101 determines that the combination ratio display mode is display (display on) (when the determination in S2141 is YES), the main CPU 101 determines whether or not the combination ratio non-display condition is satisfied. Is determined (S2144). In S2144, when the main CPU 101 determines that the combination non-display condition is not satisfied (NO in S2144), the main CPU 101 determines whether or not the door open / close monitoring switch 67 is on (when the combination ratio non-display condition is not satisfied). S2145).

When the main CPU 101 determines in S2144 that the combination non-display condition is satisfied (when the determination in S2144 is YES), and when the main CPU 101 determines in S2145 that the door open / close monitoring switch 67 is not on. (When the determination in S2145 is NO), the main CPU 101 sets the display end wait (end wait) in the combination display mode (S2146).

On the other hand, in S2145, when the main CPU 101 determines that the door open / close monitoring switch 67 is ON (when the determination in S2145 is YES), and after the processing of S2146, the main CPU 101 sets the turn-off timing (S2147). Next, the main CPU 101 subtracts 1 from the blinking management timer (S2148). Next, the main CPU 101 determines whether or not the value of the blinking management timer is larger than the initial value / 2 (S2149).

In S2149, when the main CPU 101 determines that the value of the blinking management timer is larger than the initial value / 2 (when the determination in S2149 is YES), the main CPU 101 sets the lighting timing (S2150). That is, the main CPU 101 lights the display of the combination ratio monitor 95 when the value of the blinking management timer is within the predetermined range, and displays the combination ratio monitor 95 when the value of the blinking management timer is outside the predetermined range. By turning off the light, the display of the role ratio monitor 95 is blinked.

On the other hand, in S2149, when the main CPU 101 determines that the value of the blinking management timer is equal to or less than the initial value / 2 (when the determination in S2149 is NO), and after the processing of S2150, the main CPU 101 sets the display update timer to 1. Subtract (S2151). Next, the main CPU 101 determines whether or not the display update timer has timed up (S2152). That is, the main CPU 101 determines whether or not the period corresponding to the initial value of the set display update timer has elapsed.

In S2152, when the main CPU 101 determines that the display update timer has timed up (when the determination in S2152 is YES), the main CPU 101 adds 1 to the display selection value (S2153). In this process, the main CPU 101 sets the display selection value to 0 when the display selection value is 4. On the other hand, in S2152, when the main CPU 101 determines that the display update timer has not timed up (when the determination in S2152 is NO), and after the processing of S2152, the main CPU 101 manages the role ratio monitor display from the display selection value. The display target address of the table (not shown) is calculated (S2154).

Here, the display selection value is a value for selecting the display content of the combination ratio monitor 95. For example, the display selection value 0 corresponds to the type information of "7U" (advantageous section ratio). The display selection value 1 corresponds to the type information "6Y" (medium time consecutive combination ratio), and the display selection value 2 corresponds to the type information "7Y" (medium time accessory ratio). The display selection value 3 corresponds to the type information "6A" (total winning combination ratio), and the display selection value 4 corresponds to the type information "7A" (total winning combination ratio).

Next, the main CPU 101 determines whether or not the combination monitor state has reached the specified number of games of the display target block (S2155). That is, the main CPU 101 determines from the combination ratio monitor state whether it is time to display the ratio information related to the type information corresponding to the display selection value. In S2155, when the main CPU 101 determines that the combination monitor state has not reached the specified number of games of the display target block (when the determination in S2155 is NO), the main CPU 101 shifts to the process of S2159 described later. ..

On the other hand, in S2155, when the main CPU 101 determines that the combination monitor state has reached the specified number of games of the display target block (when the determination in S2155 is YES), the main CPU 101 is set to the display selection value. Correspondingly, the type character string and the ratio blinking determination value are acquired (S2156). The type character string is data for selecting the display mode of the type information, and the ratio blinking determination value is data for selecting the display mode of the ratio information.

Next, the main CPU 101 determines whether or not it is the lighting timing (S2157). When the main CPU 101 determines in S2157 that it is the lighting timing (when the determination in S2157 is YES), the main CPU 101 shifts the process to S2159 described later. On the other hand, in S2157, when the main CPU 101 determines that it is not the lighting timing (when the determination in S2157 is NO), the main CPU 101 sets the light off (S2158).

In S2155, when the main CPU 101 determines that the combination monitor state has not reached the specified number of games of the display target block (when the determination in S2155 is NO), in S2157, the main CPU 101 is the lighting timing. When it is determined (S2157 is YES determination), and after the processing of S2158, the main CPU 101 saves the acquired type character string in the abbreviation area (not shown) (S2159).

Next, the main CPU 101 acquires display data from the target display data storage area (S2160). In this process, the main CPU 101 stores, for example, an advantageous section ratio display data storage area, a total consecutive combination ratio display data storage area, a total accessory ratio display data storage area, and a medium-time continuous combination ratio display data according to a display selection value. Acquires the display data stored in the display data storage area of either the area or the medium-time accessory ratio display data storage area.

Next, the main CPU 101 determines whether or not the acquired ratio blinking determination value is 0 (S2161). In S2161, when the main CPU 101 determines that the acquired ratio blinking determination value is 0 (when the determination in S2161 is YES), the main CPU 101 is in the display area (that is, the display data displayed as the ratio information). Is set to "---" (S2162). That is, when the ratio blinking determination value is 0, the specific ratio information is not displayed. Then, after the process of S2162, the main CPU 101 ends the combination monitor display management process, and shifts the process to the process of S968 in the test firing test signal control process (see FIG. 175).

On the other hand, in S2161, when the main CPU 101 determines that the acquired ratio blinking determination value is not 0 (when the determination in S2161 is NO), the main CPU 101 determines whether the display data is within the blinking range or at the lighting timing. Whether or not it is determined (S2163). That is, the main CPU 101 determines whether or not it is time to display the display data.

In S2163, when the main CPU 101 determines that the display data is within the blinking range or is not the lighting timing (when the determination in S2163 is NO), the main CPU 101 clears the display area (S2164). Then, after the processing of S2164, the main CPU 101 ends the combination monitor display management processing, and shifts the processing to the processing of S968 in the test firing test signal control processing (see FIG. 175).

On the other hand, in S2163, when the main CPU 101 determines that the display data is within the blinking range or the lighting timing (when the determination in S2163 is YES), the main CPU 101 sets the display area for the display data (S2165). Then, after the processing of S2165, the main CPU 101 ends the combination monitor display management processing, and shifts the processing to the processing of S968 in the test firing test signal control processing (see FIG. 175).

<Explanation of operation of sub-control circuit>
Next, with reference to FIGS. 182 to 184, the contents of various processes executed by the sub CPU 201 of the sub control circuit 200 by using the program will be described.

[Sub-side navigation control processing]
First, the sub-side navigation control process will be described with reference to FIG. 182. Note that FIG. 182 is a flowchart showing the procedure of the sub-side navigation control process.

First, the sub CPU 201 determines whether or not the navigation data has been acquired (S1101). The sub CPU 201 acquires the navigation data determined by the main control board 71 from the start command data received from the main control board 71. Therefore, in the process of S1101, the sub CPU 201 determines whether or not the received start command data includes the navigation data.

When the sub CPU 201 determines in S1101 that the navigation data has been acquired (when the determination in S1101 is YES), the sub CPU 201 sets the sub-side navigation data according to the navigation data (S1102). For example, when the sub CPU 201 acquires the navigation data "4", as shown in FIG. 63, the navigation data for notifying the push order "left, middle, right" is set as the sub side navigation data in this process. To. As a result, the content of the stop operation can be notified on both the main side and the sub side. Then, after the processing of S1102, the sub CPU 201 ends the sub-side navigation control processing.

On the other hand, in S1101, when the sub CPU 201 determines that the navigation data has not been acquired (when the determination in S1101 is NO), the sub CPU 201 determines whether or not navigation (notification of stop operation) is necessary. (S1103). In the present embodiment, the sub CPU 201 needs to be navigated, for example, when a flag conversion lottery is performed on the main control board 71 or when a predetermined combination is determined as an internal winning combination on the main control board 71. Is determined. The result of the flag conversion lottery and the type of the internal winning combination are included in the start command data. Therefore, in the process of S1103, the sub CPU 201 determines whether or not navigation is necessary based on these various pieces of information included in the start command data.

When the sub CPU 201 determines in S1103 that navigation is not necessary (NO in S1103), the sub CPU 201 ends the sub-side navigation control process.

On the other hand, in S1103, when the sub CPU 201 determines that navigation is necessary (when the determination in S1103 is YES), the sub CPU 201 sets the sub-side navigation data according to various lottery results (S1104). For example, when the internal winning combination "F_certain chili lip" is determined and the flag conversion lottery is won, the sub CPU 201 is a navigation system for displaying the symbol combination related to the abbreviation "triple chili lip" in this process. Set the data (for example, navigation data that aims at the Chilean pattern by pushing forward). Further, for example, when the internal winning combination "F_certain chili lip" is determined and the flag conversion lottery is not winning, the sub CPU 201 is for displaying the symbol combination related to the abbreviation "replay" in this process. Set navigation data (for example, navigation data indicating a push order other than forward push). By these processes, even if the main side does not notify the content of the stop operation, the sub side alone can notify the content of the stop operation. Then, after the processing of S1104, the sub CPU 201 ends the sub-side navigation control processing.

[Player registration process]
Next, the player registration process will be described with reference to FIG. 183. Note that FIG. 183 is a flowchart showing the procedure of the player registration process.

First, the sub CPU 201 determines whether or not the registration operation has been accepted (S1111). For example, when the operation of the registration button 222b is accepted on the menu screen 222 (see FIG. 5B) of the sub display device 18, and the predetermined operation is accepted on the registration screen (not shown) displayed in that case, the sub CPU 201 performs the registration operation. Is determined to have been accepted.

When the sub CPU 201 determines in S1111 that the registration operation has been accepted (when the determination in S1111 is YES), the sub CPU 201 sets the player registration state (S1112). In the situation where the player registration state is set, the sub CPU 201 can display the game information screens 223, 224, 225 (see FIGS. 5C to 5E) on the sub display device 18. Control the display screen. Then, after the process of S1112, the sub CPU 201 ends the player registration process.

On the other hand, when it is determined in S1111 that the sub CPU 201 has not accepted the registration operation (when the determination in S1111 is NO), the sub CPU 201 determines whether or not the registration deletion operation has been accepted (S1113). For example, when a specific operation is accepted on the registration screen of the sub display device 18, the sub CPU 201 determines that the registration deletion operation has been accepted.

When the sub CPU 201 determines in S1113 that the registration deletion operation is not accepted (when the determination in S1113 is NO), the sub CPU 201 ends the player registration process.

On the other hand, in S1113, when it is determined that the sub CPU 201 has accepted the registration deletion operation (when the determination in S1113 is YES), the sub CPU 201 clears the player registration state (S1114). In the situation where the player registration state is cleared, the sub CPU 201 makes it impossible to display the game information screens 223, 224, 225 (see FIGS. 5C to 5E) on the sub display device 18. Control the display screen of. Then, after the process of S1114, the sub CPU 201 ends the player registration process.

[History management process]
Next, the history management process will be described with reference to FIG. 184. Note that FIG. 184 is a flowchart showing the procedure of the history management process.

First, the sub CPU 201 acquires the game result from various command data received from the main control board 71 (S1121). For example, in this process, the sub CPU 201 can grasp the type of the winning combination determined as the internal winning combination from the start command data. Further, for example, in this process, the sub CPU 201 can grasp the symbol combination displayed from the winning operation command data (that is, the presence or absence of winning of the winning combination determined as the internal winning combination). Further, for example, in this process, the sub CPU 201 can grasp the current gaming state and the transition status of the gaming state from the start command data and the like.

Next, the sub CPU 201 performs a game history update process based on the acquired game result (S1122). By this process, the sub CPU 201 is based on the game results acquired from various command data, for example, the number of bonuses, the number of ARTs, the number of games (number of games), the number of CZs, the number of CZ successes, the number of winnings of each combination and the winnings. It is possible to manage various game histories such as probabilities. Then, after the process of S1122, the sub CPU 201 ends the history management process.

<Various effects>
In the pachislot machine 1 of the present embodiment, the following various effects can be obtained in terms of playability.

[Management of duration during CT]
In the pachislot machine 1 of the present embodiment, a CT is provided as an additional chance zone in which the duration of the normal ART can be extended, and the number of ART games is added based on the internal winning combination (sub-flag) in the CT. In CT, eight games are played in one set, but if the number of ART games can be added during CT, the number of games is not subtracted, and the number of games is increased only when the number of games cannot be added. Subtract. Therefore, the player does not know how long the CT will last, and the CT will not end as long as the addition is performed, so that the interest of the game during the CT can be enhanced.

Further, in the present embodiment, when the sub-flag EX "triple chili lip" is won (winned in the sub-flag conversion lottery) and added during CT, the CT game 8 times per set is also reset (stock). Will be done. In this case, for example, even if the CT game period is just before the end, when the sub-flag EX "triple chili lip" is won, the addition is performed and the CT is restarted from the beginning. You will have a strong interest in it, and you will be able to continue the game without getting bored, and you will be able to enhance the interest of the game during CT.

In addition, the addition of the sub-flag EX "triple chili lip" at the time of winning is performed only when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined as the internal winning combination and the flag conversion lottery is won. .. Therefore, it is possible to prevent giving an excessive profit to the player, and it is possible to balance the profit between the player and the game store. In the above embodiment, an example (see FIG. 54) in which the flag conversion lottery is always won when the internal winning combination “F_certain chili lip” or “F_1 certain chili lip” is determined during CT has been described. The present invention is not limited to this, and the winning probability of the flag conversion lottery can be appropriately set according to the balance of profits between the player and the game store.

[Number of additional games at the time of winning the "triple chili lip" during CT]
In the pachislot machine 1 of the above embodiment, when the sub-flag "triple chili lip" is won during CT and the number of additions based on the sub-flag "triple chili lip" exceeds a predetermined number of times, one additional lottery is performed. The number of additional games for winning ART will increase (see FIG. 55). Further, as described above, as long as the number of ART games is added, the CT does not end, and when the sub-flag EX "triple chili lip" is won, the CT is reset. Therefore, from the player's point of view, it is possible to expect that the additional amount per one time (one game) will increase as the CT continues, and the interest during the CT will improve. Furthermore, since the number of times (9 times or more) that triggers the increase in the amount of addition per game (1 game) is larger than the basic number of games (8 times) for one set of CT, the player is asked. It is possible to prevent excessive profits from being given, and to balance (keep good) the profits between the player and the game store.

[Bonus notification performed on the main side]
In the pachi-slot machine 1 of the above embodiment, the numerical value "10" is uniquely associated with the information of the stop operation for displaying the symbol combination related to the bonus combination (BB combination) on the instruction monitor (not shown) of the information display 6. "(Or" 11 ") is displayed to notify the bonus on the main side (see FIG. 63). However, in pachislot, the priority of the symbol to be drawn (stopped and displayed) on the effective line is usually set, and when the bonus combination and other combinations are determined as the internal winning combination, the priority is set. Depending on the situation, the combination of symbols related to the bonus combination may or may not be drawn.

For example, in the pachislot machine 1 of the present embodiment, the bonus combination and any one of the internal winning combination "missing", "F_special role 1", "F_special role 2", and "F_special role 3" are determined in duplicate. If so, the symbol combination related to the bonus combination can be drawn in, but the bonus combination and the internal winning combination "off", "F_special role 1", "F_special role 2" and "F_special role 3" If a combination other than the winning combination is determined in duplicate, the symbol combination related to the bonus combination cannot be drawn in. Therefore, in the present embodiment, the bonus combination and any one of the internal winning combination "missing", "F_special role 1", "F_special role 2", and "F_special role 3" are determined in duplicate. Only in this case, the numerical value "10" (or "11") is displayed on the instruction monitor. In this case, the navigation (bonus notification) on the main side can be performed at an appropriate timing in which the bonus combination can be won.

Further, in the pachislot machine 1 of the present embodiment, the bonus combination and any one of the internal winning combination "missing", "F_special role 1", "F_special role 2" and "F_special role 3" are determined in duplicate. Even so, the numerical value "10" (or "11") is not displayed (without navigation) on the instruction monitor until the predetermined number of games have passed since the bonus combination was first won, and the predetermined number of games have been played. The numerical value "10" (or "11") is displayed on the instruction monitor on condition that the game has passed.

In addition, for example, when an effect (so-called continuous effect) performed over a plurality of games is performed with the winning of the bonus role as an opportunity, the numerical value "10" (or "or" 10 ") is displayed on the instruction monitor during this continuous effect. If 11 ") is displayed, the meaning of the continuous production is diminished, and there is a possibility that the interest is spoiled. Therefore, in the pachi-slot machine 1 of the present embodiment, the display is not performed by the instruction monitor until the predetermined number of games have elapsed, and the display is performed by the instruction monitor after the predetermined number of games have elapsed. As a result, the bonus notification on the main side can be performed without impairing the effect of the effect.

[Notification performed on both the main side and sub side and notification performed on the sub side alone]
In the pachi-slot machine 1 of the present embodiment, a plurality of types of combinations having different symbol combinations displayed according to the mode (pushing order) of the stop operation are provided (see FIG. 24), and the displayed symbols are provided for these plurality of types of combinations. A combination in which different benefits are given depending on the combination and a combination in which the same privilege is given even if the displayed symbol combinations are different are included.

For example, the number of medals to be paid out differs depending on whether the symbol combination related to the abbreviation "bell" is displayed or the symbol combination related to the abbreviation "bell spilled eye" is displayed, and these combinations are displayed symbols. It is a role in which different benefits are given depending on the combination. In addition, whether or not the RT state is transferred in addition to the operation of the replay between the case where the symbol combination related to the abbreviation "Replay" is displayed and the case where the symbol combination related to the abbreviation "RT2 transition lip" is displayed. Therefore, the internal winning combinations "F_3 selection bell_1st" and "F_maintenance lip_1st" are also roles in which different benefits are given depending on the displayed symbol combination.

On the other hand, in both the case where the symbol combination related to the abbreviation "triple chili lip" is displayed and the case where the symbol combination related to the abbreviation "replay" is displayed, the replay operation is only performed. Therefore, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is a role in which the same privilege is given even if the displayed symbol combinations are different. As described above, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" has different benefits depending on the result of the flag conversion lottery, but the benefits given by the displayed symbol combination. It is not a role that affects.

In the pachislot machine 1 of the present embodiment, the winning combination to which different benefits are given depending on the displayed symbol combination is notified on both the main side and the sub side, but the same even if the displayed symbol combinations are different. The combination to which the privilege is given is not notified by the instruction monitor on the main side, but is notified only by the display device 11 on the sub side. By providing such a notification function, notifications that affect the benefits are appropriately performed by the instruction monitor on the main side that manages the benefits, while notifications that do not affect the benefits are diverse on the display device 11 on the sub side. It can be done with the navigation.

[Game history display function]
In the pachi-slot machine 1 of the present embodiment, a sub-display device 18 is provided separately from the display device 11 (projector mechanism 211 and display unit 212), and the sub-display device 18 displays various information useful to the player. For example, as shown in FIGS. 5A to 5E, a top screen 221 showing the outline game history, a menu screen 222 capable of performing various operations on the pachislot machine 1, and a game information screen 223, 224, 225 showing the detailed game history are sub-display devices. It can be displayed at 18.

Further, the pachi-slot machine 1 of the present embodiment has a function of enabling registration of a player who plays a game via a sub-display device 18, and a function of providing a unique service to the registered player. For example, in the present embodiment, when the registration of the player is not accepted, the game information screens 223, 224, and 225 showing the detailed game history cannot be displayed on the sub display device 18, but the registration of the player is performed. If accepted, the game information screens 223, 224, and 225 showing the detailed game history can be displayed on the sub display device 18. Since making it possible to confirm a more detailed game history leads to an improvement in the convenience of the player, in the present embodiment, the convenience can be improved when the registration of the player is accepted.

Further, in the pachi-slot machine 1 of the present embodiment, the sub-display device 18 is provided separately from the display device 11 that performs the effect. The sub display device 18 is controlled by the sub control board 72 (sub CPU 201) via the liquid crystal relay board 87. Further, the display unit 212 constituting the display device 11 is controlled by the sub control board 72 (sub CPU 201) via the accessory relay board (not shown). Therefore, in the present embodiment, the sub-display device 18 can be controlled separately from the display device 11. Specifically, the display screen of the sub-display device 18 can be switched even during the game (that is, during the execution of the effect by the display device 11). Therefore, even during the game, the player can acquire various information by switching the display of the sub-display device 18 without disturbing the effect executed by the display device 11.

Further, in the display device 11 of the pachi-slot machine 1 of the present embodiment, a flat image display is used by switching a plurality of screen mechanisms (display unit 212) for displaying an image by irradiating the irradiation light from the projector mechanism 211. When performing an effect, an effect using an image display with a sense of depth (three-dimensional effect), and an effect using a curved image display, the effect can be significantly enhanced. However, such a display form of information is not suitable for displaying information unrelated to the production such as a game history during the production. Therefore, in the pachi-slot machine 1 of the present embodiment, information unrelated to the effect can be displayed on the sub-display device 18 provided separately from the display device 11, so that the effect of the effect is not impaired and the game is played. Various information such as history can be displayed appropriately.

By the way, in a general pachislot machine, a medal insertion slot 14 is provided on the right side of the pedestal portion 13 when viewed from the player side, and bet buttons 15a and 15b and a start lever 16 are provided on the left side of the pedestal portion 13. Therefore, normally, when advancing the game, the player operates the operation unit on the right side or the left side (side) of the pedestal portion 13.

On the other hand, in the pachi-slot machine 1 of the present embodiment, the sub-display device 18 is provided on the side (left side) of the surface that stands substantially vertically from the pedestal portion 13, and the sub-display device 18 is provided on the screen of the sub-display device 18. A touch sensor 19 for switching the display screen of is provided. Therefore, in the present embodiment, the sub-display device 18 and the input device (touch sensor 19) for controlling the display are provided at the place where the player's hand is located during the game, so that the player's operability Can be improved. In particular, when the sub display device 18 with the touch sensor 19 is provided on the surface of the pedestal portion 13 that stands upright from the horizontal plane as in the present embodiment, the player puts his / her hand on the pedestal portion 13. However, the sub display device 18 can be operated. In this case, not only the operability of the player is improved, but also the fatigue of the player due to the operation can be reduced, and as a result, the operating rate can be expected to be improved.

[Non-standard ROM area and non-standard RAM area]
In the pachislot machine 1 of the present embodiment, as shown in FIG. 12B, various programs and various types used for various processes (various processes that do not affect the playability) that are not directly related to the playability of the game performed by the player The data (table) is stored in the main ROM 102 in a non-standard ROM area arranged at an address different from the game ROM area.

In such a configuration of the main ROM 102, programs and data unnecessary for the game itself actually played by the player are arranged in a ROM area (non-standard ROM area) where programs and the like cannot be arranged under the conventional rules. can do. Therefore, in the present embodiment, it is possible to avoid pressure on the capacity of the game ROM area in the main ROM 102 of the main control board 71, and to enhance the expandability of the program and the table in the main ROM 102.

[Effects obtained by processing when the power is turned on (reset interrupt)]
In the power-on (reset interrupt) processing of the pachi-slot machine 1 of the present embodiment, as shown in FIG. 64, the first 1.1172 ms cycle interrupt processing is performed immediately after the power is restored (before the thumb check) (S7 and S8). ), A non-operation command is transmitted from the main control circuit 90 to the sub control circuit 200. By permitting the interrupt process immediately after the power is restored in this way, the no-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

Further, the communication parameters 1 to 5 constituting the non-operation command transmitted immediately after the power is restored are set with the data stored in the L register, the H register, the E register, the D register and the C register, respectively, when the power is restored. Will be done. Therefore, in the present embodiment, the sum value (BCC) of the non-operation command transmitted in the interrupt process immediately after the power is restored can be made different every time the power is restored, and fraudulent acts such as goto can be suppressed. it can.

Further, the control for displaying the error code "rr" on the 2-digit 7-segment LED in the information display 6 performed in the processing of S13 during the power-on (reset interrupt) processing is one "LDW". It is executed by an instruction (predetermined read instruction), and the output operation of the 7-segment common output (selection) data to the 2-digit 7-segment LED and the output operation of the 7-segment cathode output data are performed at the same time (see FIG. 65C). That is, in the pachi-slot machine 1 of the present embodiment, when the 2-digit 7-segment LED is dynamically lit and controlled in the power-on (reset interrupt) processing, the 7-segment common output (selection) data and the 7-segment cathode output data are displayed. It is output at the same time.

In this case, the number of instruction codes required for the dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, the playability can be enhanced.

[Effects obtained by game return processing]
In the game return processing of the pachislot machine 1 of the present embodiment, as shown in FIG. 66, the input / output state of each port at the time of power failure is secured at the time of power recovery, and when the reel is rotating at the time of power failure, When the power is restored, the reel control management information is acquired and the processing necessary for starting the reel rotation is also performed (see S25 to S32). Therefore, in the present embodiment, it is possible to stably control the re-rotation of the reel even when recovering from the electric power failure during the rotation of the reel, and the player is not discomforted.

Further, as described above, the pachi-slot machine 1 of the present embodiment includes a microprocessor 91 with a security function for a game machine. The microprocessor 91 is provided with various instruction codes (instruction codes dedicated to the main CPU 101) specific to the microprocessor 91 that can be specified on the source program, and the instruction codes dedicated to the main CPU 101 are used in various processes. This makes it possible to improve processing efficiency and reduce program capacity.

For example, in the game return process, as shown in FIG. 67, the "LDQ" instruction, which is one of the instruction codes dedicated to the main CPU 101, is used on the source program. The "LDQ" instruction is an instruction code that specifies an address using a Q register (extension register), and as described above, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed with direct values. In this case, the instruction code related to the address setting can be omitted, and the capacity of the source program for the game return processing (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by setting change confirmation processing]
In the setting change confirmation process of the pachi-slot machine 1 of the present embodiment, as shown in FIG. 69A, the "BITQ" instruction and the "SETQ" instruction (predetermined instruction), which are instruction codes dedicated to the main CPU 101, are used on the source program. .. Both the "BITQ" instruction and the "SETQ" instruction are instruction codes for specifying an address using a Q register (extension register), and when these instruction codes are used, as described above, the main RAM 103 is a direct value. And memory map I / O can be accessed. In this case, the instruction code related to the address setting can be omitted, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space of the main ROM 102 can be increased, and the processing speed can be increased.

Further, the generation and storage processing of the setting change command (initialization command) performed at the time of setting change / setting confirmation start of S46 and at the end of setting change / setting confirmation of S57 during the setting change confirmation processing is as shown in FIGS. 69A and 69B. In addition, it is executed by the "CALLF" command, which is a command code dedicated to the main CPU 101, on the source program. The jump destination address specified by the "CALLF" instruction in S46 is the same as the jump destination address specified by the "CALLF" instruction in S57. That is, in the present embodiment, the setting change command (initialization command) to be transmitted to the sub-control circuit 200 at the time of setting change (when the game machine is started), at the start of setting confirmation (during normal operation), and at the end of setting confirmation is generated and stored. The source programs for executing the above are the same as each other, and the source programs are shared (modularized) in both the processes of S46 and S57.

In this case, in both the processes of S46 and S57, it is not necessary to separately provide the source program for the generation and storage process of the setting change command, so that the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. it can. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by setting change command generation and storage processing]
In the setting change command generation and storage process of the pachislot machine 1 of the present embodiment, as shown in FIG. 70, the set value is stored in the E register as the communication parameter 3, and the RT information is stored in the C register as the communication parameter 5. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), the communication parameters 3 and 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side, and these are used. New information is set in the communication parameters. On the other hand, the other communication parameters 1, 2 and 4 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side, and are communication parameters 1, 2 and 4. For and 4, the values currently stored in the L register, H register, and D register are set. Therefore, the values of the communication parameters 1, 2 and 4 at the time of transmitting the setting change command (initialization command) are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[Effects obtained by communication data storage processing]
In the communication data storage process of the pachislot 1 of the present embodiment, as shown in FIG. 72, the data stored in the A register is set as the type data of the communication command, and the L register, the H register, the E register, the D register and the C register are set. The data stored in the registers are set as communication parameters 1 to 5 of the communication command, respectively, and the data stored in the B register is set as the game state flag data of the communication command. That is, in the present embodiment, when creating one packet (8 bytes) of communication data (command data), various parameters are transferred from the register and stored in the communication data temporary storage area (communication buffer).

In this case, when command data including unused parameters is created, the value of the unused parameters becomes an indefinite value each time it is created. That is, in the command data including unused parameters, even if there is command data of the same type and the values of the used parameters are the same, the sum value (BCC data) of the command data can be changed for each command creation. .. Therefore, in the present embodiment, by setting the unused parameter to an indefinite value, it is possible to make it difficult to analyze the communication data and suppress fraudulent acts such as goto, and it is necessary to add unnecessary goto countermeasure processing. Therefore, it is possible to suppress the pressure on the program capacity of the main control circuit 90 due to the addition of the anti-goto processing.

[Effects obtained by updating the communication data pointer]
In the communication data pointer update process of the pachislot machine 1 of the present embodiment, as shown in FIG. 75A, the "ICPLD" instruction, which is an instruction code dedicated to the main CPU 101, is used on the source program.

In the communication data pointer update process, the "ICPLD" instruction is an instruction code in which the upper limit determination instruction of the transmission buffer and the determination branch instruction are integrated. There is no need to provide it. Therefore, by using the "ICPLD" instruction, the capacity of the source program for the communication data pointer update process (the capacity used by the main ROM 102) can be reduced. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by checksum generation process and checksum check process]
In the checksum generation process (non-standard) performed at the time of power failure in the pachi-slot machine 1 of the present embodiment, the checksum is calculated by sequentially adding the data of the main RAM 103 as shown in FIG. 77. On the other hand, in the thumb check process (non-standard) performed when the power is turned on (when the power is restored), the value of the checksum generated when the power is cut off is stored in the main RAM 103 when the power is restored, as shown in FIG. 79. The data is sequentially subtracted, and the presence or absence of an abnormality is determined based on whether or not the final subtraction result is "0". That is, in the present embodiment, the checksum generation process when a power failure occurs is performed by an addition method, and the checksum determination process when the power is restored is performed by a subtractive method.

When such a checksum generation process and determination process are adopted, it is not necessary to generate a checksum again when the power is restored and to collate the checksum with the checksum when a power failure occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, in the main ROM 102, it is possible to secure (increase) the free space corresponding to the omission of the collation instruction code, and it is possible to utilize the increased free space to improve the playability. Become.

[Effects obtained by medal reception / start check processing]
In the medal acceptance / start check process of the pachislot machine 1 of the present embodiment, as shown in FIG. 83, the setting change confirmation process (process of S234) is performed, and this process is executed regardless of the gaming state. Therefore, in the present embodiment, even if the game state is a bonus state (special prize operating state), the set value and the hall menu (various history data (error, power failure history, etc.)) can be confirmed, and the game can be checked. It is possible to suppress fraudulent activities.

[Effects obtained by inserting medals]
In the medal insertion process of the pachislot machine 1 of the present embodiment, as shown in FIG. 85, in the process of S244, the LED lighting data for displaying the number of inserted medals is generated by arithmetic processing instead of loop processing with reference to the table. .. Specifically, a series of source codes "LD A, L" to "OR L" in the source program shown in FIG. 86 are sequentially executed to generate LED lighting data for displaying the number of inserted medals.

When the LED lighting data for displaying the number of inserted medals is generated by arithmetic processing, the free space of the table area of the main ROM 102 can be increased, and the increase in the capacity of the program can be minimized. That is, in the medal insertion process of the present embodiment, the process of displaying the medal insertion LED can be made more efficient, the free space of the main ROM 102 is secured (increased), and the increased free area is utilized to improve the playability. Can be enhanced.

[Effects obtained by medal insertion check processing]
In the medal insertion check process (see FIG. 88) of the pachi-slot machine 1 of the present embodiment, the process of generating the normal change value of the medal sensor input state of S257 is performed by an arithmetic process, not a process of acquiring by referring to the table. Specifically, the medal sensor input state normal change value is calculated by sequentially executing the source codes "RLA" and "AND cBX_MDINSW" in the source program shown in FIG. 89.

By changing the detection process of the change mode of the medal sensor input state from the table reference process to the arithmetic process, the free space of the table storage area of the main ROM 102 can be increased and the increase in the program capacity can be minimized. it can. Therefore, by adopting the above-mentioned processing method, it is possible to improve the efficiency of the detection processing of the change mode of the medal insertion sensor state, and to utilize the increased free space in the main ROM 102 to improve the playability. it can.

[Effects obtained by internal lottery processing]
In the internal lottery process of the pachi-slot machine 1 of the present embodiment (see FIG. 93), the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 94A. By executing this "LDIN" instruction, in the processing of S305, the determination data (the value of the "lottery value selection table or lottery counting table") is stored in the A register, and the request flag status ("special prize winning number") hits the C register. + Value of "small winning combination winning number") is stored. Further, by executing the "LDIN" instruction, the address set in the HL register is updated by +2 (addition of 2).

That is, in the determination data acquisition process of S305 during the internal lottery process, both the data load process and the address update process can be performed by one instruction code (“LDIN” instruction). In this case, the instruction code related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the addition processing of the set value data (any of 0 to 5) of S309 of the internal lottery processing, the main CPU 101 uses the source codes “MUL A, 6” and “ADDQ A, (.LOW.wWAVENUM” in FIG. 94B. ) ”Is executed in this order.

The "MUL" instruction is an instruction code for multiplication processing dedicated to the main CPU 101, and the execution of this instruction is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, since the pachi-slot machine 1 of the present embodiment is provided with a dedicated calculation circuit (calculation circuit 107) for executing multiplication processing and division processing on the source program, the efficiency of multiplication processing and division processing should be improved. Can be done.

Further, the "ADDQ" instruction (predetermined addition instruction) is an instruction code dedicated to the main CPU 101, and is an instruction code for specifying an address using a Q register (extension register). Then, by using this "ADDQ" instruction, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by the direct value. Therefore, by using the "ADDQ" instruction, the instruction related to the address setting can be omitted on the source program of the internal lottery processing, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. Can be done. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by design setting process]
In the symbol setting process (see FIG. 98) of the pachi-slot machine 1 of the present embodiment, the compressed data storage process of S330 is performed by the main CPU 101 executing the source code "CALLF SB_BTEP_00" in FIG. 100. The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_BTEP_00" in FIG. 100 is executed, processing is performed at the address specified by "SB_BTEP_00". Jump and start the compressed data storage process.

Further, the setting process of the address of the hit request flag storage area of S329 during the symbol setting process is performed by the main CPU 101 executing the source code "LDQ DE, .LOW. WWAVEBIT" in FIG. 100. That is, the processing of S329 is performed by the "LDQ" instruction dedicated to the main CPU 101 using the Q register (extension register). In this case, the instruction code related to the address setting can be omitted on the source program of the symbol setting process, and the capacity of the source program of the symbol setting process (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the present embodiment, the data related to the winning is compressed / decompressed by the processing procedure described in S324 to S330 during the symbol setting process described above, and the command code dedicated to the main CPU 101 described above is used in the process. By using it, it is possible to improve the efficiency of the compression / decompression processing of the data related to the winning, and it is possible to effectively utilize the limited capacity of the main RAM 103.

[Effects obtained by sub-flag conversion processing]
In the sub-flag conversion table shown in FIG. 108, which is actually referred to on the source program of the sub-flag conversion process in the pachi-slot machine 1 of the present embodiment, the sub-flag conversion control data (control status) is associated with each sub-flag. .. At this time, the same sub-flag conversion control data (control status) is associated with the same type of sub-flag.

For example, the sub-flag conversion control data (control status) "00000011B" is commonly assigned to the sub-flags "triple chili lip A" and "triple chili lip B". Then, in the flag conversion lottery process when converting the internal winning combination (sub-flag) to the sub-flag EX, the lottery is performed based on the sub-flag conversion control data (control status) associated with the sub-flag.

In this way, in the sub-flag conversion table managed on the main side, by providing common sub-flag conversion control data for the same type of internal winning combination (sub-flag), the versatility of the conversion table is increased, and the conversion table is changed. Since changes in the conversion program can be handled with minor changes, it is possible to suppress an increase in development costs.

[Effects obtained by navigation set processing]
In the navigation set processing of the pachislot machine 1 of the present embodiment, as shown in FIG. 110, the "LDQ" instruction (instruction code dedicated to the main CPU 101) that specifies the address using the Q register (extension register) is used in the source program. Be done.

Therefore, in the navigation set processing of the present embodiment, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by table data acquisition processing]
In the table data acquisition process of the pachislot machine 1 of the present embodiment (see FIG. 121), in the table data acquisition process of the first stage of S581 to S584, the table selection by winning combination in the CT winning lottery table during CT (see FIG. 123) is selected. Relative table is referenced. Then, in the table selection relative table for each winning combination referred to in the table data acquisition process of the first stage, the "loss" of the CT lottery is set by the selection value provided for each type of the internal winning combination (sub flag D). Therefore, it is not necessary to specify the lottery value of the "missing" role in the lottery table. Therefore, in the present embodiment, it is not necessary to store the lottery value data of the “missing” role in the CT winning lottery table during CT, and the capacity of the table area of the main ROM 102 can be saved.

Further, in the lottery table of the second stage (when subflag D "reach eye lip" is acquired) in the CT winning lottery table during CT, the lottery target combination or the non-lottery target combination is determined by the value of each bit constituting the determination bit. This eliminates the need to store lottery value data (loss data) in a table for a combination that is not subject to lottery. Further, in the CT winning lottery table during CT, the lottery value "0" can be used as the definite data in which the winning probability of the winning combination of the lottery target combination is 100%. From these facts, in this embodiment, the capacity of the CT winning lottery table during CT (the lottery table with the number of sets added during CT) can be compressed, and the free space can be secured (increased) in the main ROM 102. , You can improve the playability by utilizing the increased free space.

[Effects obtained by design code acquisition processing]
In the symbol code acquisition process (see FIG. 129) of the pachi-slot machine 1 of the present embodiment, the data related to the winning is compressed / decompressed by the processing procedure described in S647 to S649, and the main CPU 101 dedicated command in the processing is performed. By using a code (such as a "CALLF" command), it is possible to improve the efficiency of the data compression / decompression processing related to the winning, and it is possible to effectively utilize the limited capacity of the main RAM 103.

Further, in the present embodiment, in the compressed data storage process of S649 during the symbol code acquisition process, the jump destination address specified by the "CALLF" command is the compressed data storage process of S330 during the symbol setting process (see FIG. 98). Is the same as the jump destination address specified by the "CALLF" instruction. That is, in the present embodiment, the source program for executing the compressed data storage process is shared (modularized) in both the symbol code acquisition process and the symbol setting process. In this case, since it is not necessary to separately provide the source program for the compressed data storage process in each process, the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by pull-in priority acquisition processing]
In the pull-in priority order acquisition process of the pachi-slot machine 1 of the present embodiment (see FIGS. 135 and 136), the determination process of S683 during the pull-in priority correspondence process of the “ANY combination” is performed by the main CPU 101 dedicated instruction code on the source program. It is executed by a certain "JCP" instruction (comparison instruction) (see FIG. 137A).

When the "JCP" command is used in the source program of the "ANY role" pull-in priority processing, the command related to the address setting can be omitted as described above, so the "ANY role" pull-in priority support The processing efficiency of the processing can be increased, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced.

Further, in the stop control pull-in request flag setting process of S686 during the pull-in priority acquisition process, as shown in FIG. 137B, the Q register (extension register), which is the instruction code dedicated to the main CPU 101, is used on the source program. The "LDQ" instruction and the "CALLF" instruction for specifying an address are used.

Therefore, in the stop control pull-in request flag setting process of S686, by using the "LDQ" instruction, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (use of the main ROM 102). Capacity) can be reduced. Further, the "CALLF" instruction is a 2-byte instruction code as described above. Therefore, by using these main CPU 101 dedicated instruction codes in the stop control pull-in request flag setting process, the efficiency of the process can be improved and the limited capacity of the main RAM 103 can be effectively utilized. ..

Further, in the present embodiment, in the stop control pull-in request flag setting process of S686 during the priority pull-in order acquisition process, the address of the jump destination logical product operation process specified by the "CALLF" instruction is the pull-in priority order storage process ( It is the same as the jump destination address specified by the "CALLF" instruction in the logical product operation processing of S626 in (see FIG. 127) (see FIG. 128). That is, in the present embodiment, the source program for executing the AND operation processing is shared (modularized) in both the priority attraction order acquisition process and the attraction priority order storage process.

In this case, since it is not necessary to separately provide the source program for the logical product operation processing in both the priority attraction order acquisition process and the attraction priority order storage process, the capacity of the source program (the capacity used by the main ROM 102) is increased accordingly. Can be reduced. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the acquisition process of the attraction priority table (see FIG. 138) of S687 during the attraction priority acquisition process, as shown in FIG. 137C, the "LDQ" instruction (instruction code dedicated to the main CPU 101) is used. Therefore, even in the acquisition process of the pull-in priority table in S687, the instruction related to the address setting can be omitted on the source program. As a result, the efficiency of the acquisition process of the pull-in priority table can be improved, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced.

[Effects obtained by reel stop control processing]
In the reel stop control process of the pachi-slot machine 1 of the present embodiment (see FIG. 139), in the processes of S711 to S715, as shown in FIG. 140, the address is specified by using the Q register (extension register) on the source program. The "LDQ" instruction and the "CALLF" instruction are used.

Therefore, in the present embodiment, by using these main CPU 101 dedicated instruction codes, the capacity of the source program for the reel control processing can be reduced, and the processing efficiency of the reel stop control processing can be improved. That is, in the present embodiment, it is possible to improve the efficiency of the program processing speed and reduce the capacity of the main control circuit 90, and utilize the free area of the main ROM 102 increased according to the reduced capacity to improve the playability. Can be enhanced.

Further, in the determination process of S726 during the reel stop control process (check process of the stop state of the reel (rotary cylinder)), as shown in FIG. 141, the "LDQ" instruction and the "ORQ" instruction (Q) on the source program. A main CPU 101 dedicated instruction code) that specifies an address using a register (extension register) is used.

Therefore, in the present embodiment, the instruction related to the address setting can be omitted on the source program of the reel stop control process, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. .. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by winning search processing]
In the winning search process of the pachislot machine 1 of the present embodiment (see FIG. 146), in the set process of the number of payouts and the determination target data in S764, as shown in FIG. 147, the "LDIN" command is used on the source program.

Therefore, in the winning search process of the present embodiment, both the data load process and the address update process can be performed by one "LDIN" command. In this case, the instruction related to the address setting can be omitted on the source program of the winning search process, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, the acquisition process of the value of the medal counter referred to in the determination process of S770 during the winning search process, the acquisition process of the value of the winning number counter referred to in the processing of S772, and the saving of the winning number counter performed in the processing of S775 ( In each of the update) processes, as shown in FIG. 147, the "LDQ" instruction for specifying the address using the Q register (extension register) is used. Therefore, in the winning search process of the present embodiment, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the determination process of S769 during the winning search process, as shown in FIG. 147, the "JSLAA" instruction is used on the source program, and in the determination process of S770 and S773, the "JCP" instruction is used. When the "JSLAA" command and the "JCP" command are used on the source program of the winning search process, the command related to the address setting can be omitted as described above, and the capacity of the source program (main ROM 102) can be omitted accordingly. (Capacity used) can be reduced. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by illegal hit check processing]
In the present embodiment, as shown in FIGS. 28 to 30, the configuration of the winning operation flag storage area (display combination storage area) is the same as that of the hit request flag storage area (internal winning combination storage area). Therefore, in the arithmetic processing of S784 in the illegal hit check processing of the present embodiment, the data of the winning combination and the data of the internal winning combination are simply ANDed on the source program (see FIG. 150) by a logical product (“AND” instruction). You can get the result of combining the winning combination data and the internal winning combination data just by executing).

Therefore, in the present embodiment, the illegal hit check process can be made more efficient and simplified, and as a result, the free space of the main control program can be secured, and the free space can be used to enhance the playability. be able to.

[Effects obtained by winning check / medal payout processing]
In the winning check / medal payout process of the pachislot machine 1 of the present embodiment (see FIG. 151), when the payout operation is continued after the credit counter is updated (+1), the wait (payout interval) of 60.33 ms is performed in the process of S808. Wait) Processing is performed. In this case, unnecessary waiting time can be reduced, and the mental burden on the player can be reduced.

[Effects obtained by checking the number of medals paid out]
In the update process of the winning combination end number counter of S814 during the medal payout number check process (see FIG. 153) of the pachislot machine 1 of the present embodiment, as shown in FIG. 154A, it is an instruction code dedicated to the main CPU 101 on the source program. The "DCPLD" instruction is used.

In the processing of S814, the "DCPLD" instruction is an instruction code in which the lower limit determination instruction of the number management counter and the determination branch instruction are integrated. Both processes of holding the counter value at "0" can be executed. In this case, it is not necessary to provide an instruction code for executing both processes separately. Therefore, in the medal payout number check process of the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, and the free space can be secured (increased) in the main ROM 102, resulting in an increase. It is possible to improve the playability by utilizing the free space.

Further, in the process of S816 during the medal payout number check process, as shown in FIG. 154B, the value of the payout counter is set in the communication parameter 1 of the credit information command, and the value of the credit counter is set in the communication parameter 5. Will be done. However, the values stored in the H register, the E register, and the D register at the present time are set in the other communication parameters 2 to 4 (unused parameters) constituting the credit information command. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[Effects obtained by 7-segment LED drive processing]
As shown in FIG. 169B, the output processing of the 7-segment common output (selection) data and the 7-segment cathode output data performed in S936 in the 7-segment LED drive processing (see FIG. 168) of the pachislot machine 1 of the present embodiment is one source. It is executed by the code "LD (cPA_SEGCOM), BC". That is, in the present embodiment, in the 7-segment LED drive process, when the 2-digit 7-segment LED is dynamically lit and controlled, the 7-segment common output data and the 7-segment cathode output data are output at the same time. This output control is also performed when the push order display data is displayed on the instruction monitor in the information display 6.

In this case, the number of instruction codes required for the dynamic lighting control of the 7-segment LED can be reduced on the source program of the 7-segment LED drive process. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, the playability can be enhanced.

[Effects obtained by timer update processing]
In the process of S952 (update process of the 2-byte timer) in the timer update process of the pachislot machine 1 of the present embodiment (see FIG. 173), as shown in FIG. The "DCPWLD" command is used.

When the "DCPWLD" instruction is executed in the timer update process, both the process of updating (subtracting) the number of timers (the number of 2-byte timers) and the process of holding the number of timers at "0" are executed as described above. Can be done. In this case, it is not necessary to provide an instruction code for executing both processes separately. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, the playability can be enhanced.

[Effects obtained by ratio calculation processing (approximate value formula)]
In the ratio calculation process (approximate value formula) of the pachislot 1 of the present embodiment (see FIGS. 158 and 159), a predetermined ratio calculation (100) using the data of each storage area composed of a capacity of 3 bytes or more as the molecule and denominator. When performing fractional calculation), the data in each storage area is subjected to predetermined arithmetic processing to calculate the data for 2 bytes, and the approximate value is calculated based on the calculated data for 2 bytes. , I try to calculate the ratio information. Therefore, in the present embodiment, desired ratio information can be derived without imposing an excessive load on the main control circuit 90 mounted on the pachislot machine 1.

Further, in the ratio calculation process (approximate value formula) of the pachislot machine 1 of the present embodiment (see FIGS. 158 and 159), an appropriate correction process is performed on the calculated ratio information. Therefore, even when the ratio information is calculated based on the approximate value, it is possible to prevent an error from occurring with the true value.

In the pachi-slot machine 1 of the present embodiment, a case where the main CPU 101 has a function of calculating data of at least 2 bytes and each storage area is composed of 3 bytes or more will be described as an example. However, this is not limited to cases where the ratio calculation process (approximate value formula) (see FIGS. 158 and 159) can be applied. For example, the main CPU 101 has a function of performing a 4-byte data calculation, and can be applied even when each storage area is composed of 5 bytes or more, and the main CPU 101 performs a 1-byte data calculation. It has a function to perform, and can be applied even when each storage area is composed of 2 bytes or more. That is, it can be appropriately modified and applied according to the specifications on the main CPU 101 (control means) side.

[Effects obtained by the role ratio monitor display switching process and the role ratio monitor display management process]
In the combination monitor display switching process (see FIG. 87) and the combination monitor display management process (see FIGS. 180 and 181) of the pachislot 1 of the present embodiment, the above-mentioned combination non-display condition is satisfied, or When the front door 2b is in the closed state, the display state of the combination monitor 95 is switched to non-display (display off), the above-mentioned combination non-display condition is not satisfied, and the front door 2b is in the open state. In the case of, the display state of the combination monitor 95 is switched to display (display on). Therefore, the control load related to the ratio display can be reduced, and the life of the device for displaying the ratio (role ratio monitor 95) can be extended. Further, since the owner of the door key (not shown) (for example, a clerk of a game store, an inspector of a game machine, etc.) can perform the unlocking operation for the lock 5 of the front door 2b in principle. Since the display of the combination ratio monitor 95 cannot be visually recognized by anyone other than the holder of the door key (not shown), the safety regarding the display of the ratio can be improved.

<Various deformation examples>
The configuration and operation of the gaming machine according to the present invention have been described above, including their effects. However, the present invention is not limited to the above-described embodiments, and includes various other embodiments and modifications as long as it does not deviate from the gist of the present invention described in the claims.

[Modification example 1: CT precursor game and notification lottery during normal ART]
In the pachislot machine 1 of the above embodiment, in order to facilitate understanding, an example in which the gaming state is shifted from the next game (next game) to an advantageous state when the player wins a favorable state (for example, CT). However, the present invention is not limited to this. For example, when performing game control in an advantageous state for a player, the game control in the advantageous state may be performed after performing a predetermined number of games, which is called a so-called "precursor game". ..

Here, with reference to FIGS. 185A and 185B, as an example thereof, an example in which the gaming state shifts from the normal ART to the CT via a predetermined number of precursor games will be described. Note that FIG. 185A is a diagram showing a game flow at the time of winning the CT lottery in the first modification, and FIG. 185B is a configuration diagram of a flag conversion lottery table used in the flag conversion lottery performed during the precursory game.

In the game during the normal ART of this example, first, as shown in FIG. 185A, the CT lottery table during the ART (see FIG. 50) is used as in the above embodiment, and the CT lottery is based on the internal winning combination (sub flag). I do. When the CT lottery is won, it is determined that the gaming state shifts to a state advantageous for the player called CT (additional chance zone). Therefore, various lottery for the CT lottery during the period until the CT is won. Is performed on the main side (main control board 71). For example, the main control board 71 (main CPU101) performs an internal lottery for determining the internal winning combination, and also as the internal winning combination, the internal winning combination “F_certain chili lip”, “F_1 certain chili lip”, and “F_reach eye lip A”. When any of "F_reach eye lip D" is determined, the flag conversion lottery is performed using the flag conversion lottery table during ART (see FIGS. 47A and 47B).

Next, when a CT lottery is won in a game during normal ART, in this example, a precursory game (CT precursory game) for a predetermined period is performed before the transition to CT. In this example, in the CT precursor game, for example, a privilege for a player such as a CT lottery based on a sub-flag EX ("triple chili lip", "reach eye lip", "replay", etc.) determined by a flag conversion lottery. The lottery that grants the above will not be performed. However, in this example, in the CT precursor game, for example, the flag conversion lottery using the flag conversion lottery table shown in FIG. 185B is performed on the sub side (sub-control board 72 side), and the flag conversion lottery performed on this sub side is performed. Based on the result, the content of the notification performed on the sub side is controlled (determined). For example, when the flag conversion lottery performed on the sub side is won, the display device 11 (projector mechanism 211 and display unit 212) notifies the information for displaying the symbol combination related to the abbreviation "reach eye lip". When the flag conversion lottery is not won, the display device 11 notifies the information for displaying the symbol combination related to the abbreviation "replay".

As described above, in recent pachislot machines, it is required that the main side perform a lottery that affects the profit (ball output) of the player, but in the pachislot machine 1 of this example, the lottery result of the flag conversion lottery is the game. A period (period of CT precursor game) that does not affect the interests of the person is provided, and the flag conversion lottery is performed on the sub side only during this period. Therefore, in this example, for example, in a situation where the privilege of being in the CT omen is decided, it is possible to increase the chance of displaying a special symbol combination such as the symbol combination related to the abbreviation "reach eye lip". At the same time, it is possible to increase the variation of how to show the combination of symbols. As a result, according to the configuration of this example, it is possible to further improve the playability.

The lottery table shown in FIG. 185B is a flag conversion lottery table in the CT precursor used for the flag conversion lottery performed on the sub side, and is stored in the ROM cartridge substrate 86. The flag conversion lottery table in the CT omen includes the internal winning roles "F_reach eye lip A" to "F_reach eye lip D", the lottery result (non-winning / winning) of the flag conversion lottery performed on the sub side, and each lottery. The correspondence with the lottery value information associated with the result is specified.

As is clear from the flag conversion lottery table shown in FIG. 185B, in this example, in the CT precursor game, the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" have a very high probability of sub-flag EX ". It is converted to "reach eye lip" (wins the flag conversion lottery). That is, in the CT precursor game, when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is determined, the symbol combination of the abbreviation "reach eye lip" is stopped and displayed with high probability. Therefore, it is possible to suggest to the player that the current game is in the CT precursor game. At this time, as described above, when the flag conversion lottery performed on the sub side in the CT precursor game is won, the notification for displaying the symbol combination related to the abbreviation "reach eye lip" is performed, but the privilege is given. There is no.

In this example, the flag conversion lottery during the CT precursor game may be performed on the main side. However, as in the example described with reference to FIGS. 185A and 185B, the data capacity and processing load on the main side can be reduced by performing the lottery on the sub side during a period that does not affect the profit of the player.

[Modification example 2: Another example of push order for triple chili lip display]
In the pachislot machine 1 of the above embodiment, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, if the stop button pressing order is correct, the symbol combination related to the abbreviation "triple chili lip" is used. An example has been described in which a symbol combination related to the abbreviation "replay" is displayed when the display is displayed and the pressing order is incorrect (see FIG. 24). Further, in the above-described embodiment, an example has been described in which the correct push order associated with the internal winning combinations “F_certain chili lip” and “F_1 certain chili lip” is “forward push”. However, the present invention is not limited to this.

For example, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, the types of symbol combinations displayed when the pressing order is incorrect are increased, and the internal winning combination "F_certain chili lip" is increased. The correct push order when "" is determined may be different from that when the internal winning combination "F_1 certainty lip" is determined. An example thereof (modification example 2) will be described with reference to FIGS. 186A and 186B. Note that FIG. 186A is a diagram showing a correspondence relationship between the internal winning combination and the symbol combination (stop symbol (abbreviation)) displayed as a stop in the modified example 2, and FIG. It is a figure which shows the correspondence relationship between the result of the flag conversion lottery of, and the navigation type performed on the sub side.

In this example, as shown in FIG. 186A, when the internal winning combination "F_certain chili lip" is determined, the correct push order is "forward push (left reel 3L is the first stop)", and the wrong answer is pushed. The order is "first stop of the middle reel 3C (hereinafter referred to as" middle push ") or first stop of the right reel 3R (hereinafter referred to as" reverse push ")", that is, "irregular push". Then, in this example, when the internal winning combination "F_certain chili lip" is determined, the symbol combination related to the abbreviation "triple chili lip" is displayed when pressed forward, and the abbreviation "replay" is displayed when pressed in the middle. The symbol combination related to is displayed, and when it is pushed backward, the symbol combination related to the abbreviation "double chili lip" is displayed.

Further, in this example, when the internal winning combination "F_1 certainty lip" is determined, the correct answer is pushed in the reverse order, and the incorrect answer is pushed in the forward and middle push orders. Then, in this example, when the internal winning combination "F_1 certain chili lip" is determined, when it is pressed backward, the symbol combination related to the abbreviation "triple chili lip" is displayed, and when it is pressed in the middle, the abbreviation "replay" is displayed. The symbol combination according to is displayed, and when it is pushed forward, the symbol combination related to the abbreviation "double chili lip" is displayed.

In the pachislot machine 1 of this example, when either the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, if the player presses forward, the abbreviation "triple chili lip" or the abbreviation "triple chili lip" or The symbol combination related to "double chili lip" is displayed. In addition, when either the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined and pressed backward, the abbreviation "triple chili lip" or "double chili lip" is used depending on the type of internal winning combination. The symbol combination related to "" is displayed. Further, in this example, when either of the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, if the player presses the button in the middle, the symbol combination related to the abbreviation "replay" is performed regardless of the type of the internal winning combination. Is displayed.

When the correspondence between the internal winning combination and the symbol combination displayed as stopped (stop symbol (abbreviation)) is set to the relationship shown in FIG. 186A, for example, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined. In that case, it becomes possible to carry out various navigations (notifications) for the player to aim at the Chilean pattern.

For example, both "navigation that aims at the chili symbol by pushing forward" and "navigation that aims at the chili symbol by pushing backward" can be performed. In addition, when the internal winning role "F_certain chili lip" is decided, "navigation that aims at the chili symbol by pushing forward" becomes a navigation for displaying the symbol combination related to the abbreviation "triple chili lip", and " "Navi that aims at the chili symbol by reverse pressing" is a navigation for not displaying the symbol combination related to the abbreviation "triple chili lip" (navigation that displays the symbol combination related to the abbreviation "double chili lip"). On the other hand, when the internal winning combination "F_1 certain chili lip" is decided, "navigation that aims at the chili symbol by pushing forward" is a navigation for not displaying the symbol combination related to the abbreviation "triple chili lip" (abbreviation "navigation"). The navigation that displays the symbol combination related to "double chili lip"), and the "navigation that aims at the chili symbol by reverse pressing" is the navigation for displaying the symbol combination related to the abbreviation "triple chili lip".

In this example, the decision as to whether or not to perform the above-mentioned navigation is managed by the flag conversion lottery performed on the main side, and the navigation is executed by the control of the sub side based on the result of the flag conversion lottery on the main side. .. At this time, the correspondence between the lottery result of the flag conversion lottery normally performed on the main side during ART and the navigation type controlled on the sub side is the correspondence relationship shown in FIG. 186B.

Also in this example, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined in the game during normal ART, the main control board 71 (main CPU 101) performs a two-step flag conversion lottery ( See FIG. 47). On the other hand, on the sub side, the result of the two-step flag conversion lottery is acquired from the start command data, and the navigation to be performed by the display device 11 is determined based on the result of the two-step flag conversion lottery.

Therefore, in this example, when the lottery result is non-winning at the time of the first stage flag conversion lottery, the sub control board 72 (sub CPU201) is referred to as "replay navigation" as shown in FIG. 186B. Perform the so-called navigation. In the "replay navigation", information instructing the player to press the button is notified. In this example, as shown in FIG. 186A, regardless of whether the internal winning combination is "F_certain chili lip" or "F_1 certain chili lip", the symbol combination related to the abbreviation "replay" is displayed at the time of middle pressing. ..

Further, in this example, when the first stage flag conversion lottery is won and the lottery result of the second stage flag conversion lottery is non-winning, the sub control board 72 (sub CPU201) is shown in FIG. 186B. As shown in, the navigation called "Chililip fan navigation" is performed. In addition, in the "Chile Lip Fan Navi", when the internal winning combination "F_certain Chile Lip" is determined, the player is notified of the instruction information to aim the Chile symbol by pushing back. On the other hand, in the "Chile Lip Fan Navi", when the internal winning combination "F_1 Definite Chile Lip" is determined, the player is notified of the instruction information to aim the Chile symbol by pushing forward. Then, in such a "chili lip fan navigation", as shown in FIG. 186A, when the internal winning is "F_certain chili lip", the symbol combination related to the abbreviation "double chili lip" is displayed at the time of reverse pressing. When the internal winning combination is "F_1 certain chili lip", the symbol combination related to the abbreviation "double chili lip" is displayed at the time of forward pressing.

Further, in this example, when both the first stage and the second stage flag conversion lottery are won, the sub control board 72 (sub CPU201) is referred to as a "chili lip aligned navigation" as shown in FIG. 186B. Navigating. In addition, in the "Chile Lip Matching Navi", when the internal winning combination "F_certain Chile Lip" is determined, the player is notified of the instruction information to aim the Chile symbol by pushing forward. On the other hand, in the "Chile Lip Matching Navi", when the internal winning combination "F_1 Definite Chile Lip" is determined, the player is notified of the instruction information to aim the Chile symbol by pushing back. Then, in such a "chili lip matching navigation", as shown in FIG. 186A, when the internal winning is "F_certain chili lip", the symbol combination related to the abbreviation "triple chili lip" is displayed at the time of forward pressing. When the internal winning combination is "F_1 certain chili lip", the symbol combination related to the abbreviation "triple chili lip" is displayed at the time of reverse pressing.

In this example, the notification based on the lottery result of the flag conversion lottery described above does not affect the profit (the flag conversion lottery itself affects the profit, but the symbol combination displayed as a result affects the profit. Therefore, the above notification operation of this example is not performed on the main side (instruction monitor), but is performed only on the sub side (display device 11). Further, in this example, as described above, by performing not only the "chili lip matching navigation" but also the "chili lip fanning navigation", the navigation that does not affect the profit can be controlled by the sub side in various modes. .. As a result, the interest of the game can be improved.

[Modification 3: Another example of the bell navigation mode between flags and between non-flags]
In the pachi-slot machine 1 of the above embodiment, as described above, the main side is notified by displaying the numerical value uniquely corresponding to the information of the reel stop operation on the instruction monitor (not shown). At this time, the correspondence relationship of the navigation data described with reference to FIGS. 63A to 63D is referred to. Then, in the above-described embodiment, an example in which "white 7 navigation" and "blue 7 navigation" are performed during the BB flag state (RT5 state) but "bell navigation" is not performed has been described. Not limited. In the state between BB flags (RT5), "Bell Navi" may be performed in addition to "White 7 Navi" and "Blue 7 Navi".

In this case, the numerical values displayed on the instruction monitor may be different from each other in the state between the BB flags and the state between the non-BB flags. Here, FIGS. 187A and 187B show the correspondence between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the state between the BB flags in the modified example 3. Note that FIG. 187A is a diagram showing the correspondence between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the RT5 state (between the BB1 flags), and FIG. It is a figure which shows the correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in (between BB2 flags).

Further, in this example, the correspondence between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the non-BB flag state is the same as that of the above embodiment (see FIGS. 63A and 63B). .. Therefore, when "Bell Navi" is performed in the non-BB flag state, numerical values "1" to "3" (pushing order second instruction information) are displayed on the instruction monitor.

In this example, as shown in FIGS. 187A and 187B, when "Bell Navi" is performed in the state between the BB flags, the numerical values "12" to "14" (pushing order first instruction information) are displayed on the instruction monitor. The flag. The present invention is not limited to this, and the numerical value displayed on the instruction monitor can be appropriately changed when "Bell Navi" is performed in the state between the BB flags. In this example, the navigation on the sub side performed by using the display device 11 may be provided in common in both the BB flag inter-flag state and the non-BB flag inter-flag state.

[Modification 4: Another example of granting benefits]
In the pachi-slot machine 1 of the above embodiment, since the notification content is controlled based on the result of the flag conversion lottery performed on the main side, the symbol combination displayed is different when the stop operation is performed according to the notification. That is, in the above embodiment, an example in which whether or not to grant the privilege is determined based on the result of the flag conversion lottery performed on the main side has been described, but the present invention is not limited to this. For example, on the main side (main control board 71), the privilege may be given based on the actually displayed symbol combination.

In this case, the main control board 71 (main CPU 101) gives a privilege when a predetermined symbol combination is displayed according to the notification performed according to the result of the flag conversion lottery, and when the notification is not followed, the main control board 71 (main CPU 101) gives a privilege. , Even if a predetermined symbol combination is displayed, the privilege may not be given. In the pachislot machine 1 of the above embodiment, the symbol combinations displayed according to the pressing order are different, but even when the player ignores the notification and performs the stop operation, the symbol combinations related to the abbreviation "triple chili lip" are used. There is a possibility that a special symbol combination such as, etc. will be displayed. Therefore, in this example, even if the notification is ignored and a special symbol combination is displayed, the privilege is given only when the special symbol combination is displayed according to the notification without giving the privilege. You may.

[Modification 5: Another example of notification control that does not affect profits (privileges)]
In the pachislot machine 1 of the above modification 1 (see FIGS. 185A and 185B), whether or not to perform the notification that affects the profit is determined by the notification lottery (flag conversion lottery) on the main side and does not affect the profit. An example in which whether or not to perform notification is determined by a notification lottery on the sub side has been described. Then, as an example of the notification that does not affect the profit, an example of displaying the symbol combination related to the abbreviation "reach eye lip" during the precursory game has been described, but the notification that does not affect the profit is described. , Not limited to this example.

In recent pachislot machines, the game may be changed to a state in which it is easy (difficult) to lock the game according to the order of stop operations. For example, transitioning to a state where it is easy to lock the game when the pressing order is "left, middle, right", and transitioning to a state where it is difficult to lock the game when the pressing order is "right, middle, left". There is. In such a pachislot machine, it is possible to shift to a state in which it is easy (difficult) to lock the game by notifying the pushing order. However, if whether or not to lock the game affects the profit, it is necessary to control this notification on the main side. If whether or not to lock the game does not affect the profit, this notification may be controlled on the sub side.

Further, as a case where whether or not to perform the game lock affects the profit, for example, it is conceivable that the game lock is performed to win the ART lottery. On the other hand, when whether or not to perform the game lock does not affect the profit, it is the case where the game lock is performed as an effect. For example, by frequently performing the game lock during the precursory game in which it is decided to give a profit (privilege), it becomes possible to show in the production that the profit will be given in the subsequent game. ..

Here, with reference to FIGS. 188A and 188B, a configuration example in which the push order and the locked state are associated with each other in the modified example 5 will be described. Note that FIG. 188A is a diagram showing the correspondence relationship between the push order and the locked state, and FIG. 188B is a diagram showing the relationship between the presence or absence of the influence of the game lock on the profit and the notification mode.

In the example shown in FIG. 188A, when the internal winning combination “F_maintenance lip A” is determined and the stop operation is performed in the pressing order of “left, middle, right”, the lock state is “0” (a state in which it is difficult to lock). ) To "1" (easy to lock), and when the stop operation is performed in the pressing order of "left, right, middle", "middle, left, right" or "middle, right, left", the current When the locked state of is maintained and the stop operation is performed in the pressing order of "right, left, middle" or "right, middle, left", the locked state changes from "1" to "0". In addition, when the internal winning combination "F_maintenance lip B" is determined, if the stop operation is performed in the pressing order of "middle, left, right", the lock state changes from "0" (a state in which it is difficult to lock) to "1". "(Easy to lock state), and when the stop operation is performed in any other pressing order, the current locked state is maintained.

In the example shown in FIG. 188A, in order to simplify the explanation, an example in which the lock state is set to two stages of "0 (difficult to lock state)" and "1 (easy to lock)" will be described. The present invention is not limited to this. For example, a locked state of three or more stages may be provided. Further, in this case, the lock state may not be changed step by step, but may be changed in multiple steps at one time.

Then, in this example, as shown in FIG. 188B, when the game lock affects the profit, the notification lottery for whether or not to perform the notification is performed on the main (main control board 71) side, and the lottery result is performed. The predetermined push order is notified on both the main side and the sub side based on. On the other hand, when the game lock does not affect the profit, a notification lottery for whether or not to perform notification is performed on the sub (sub-control board 72) side, and a predetermined push order is performed on the sub side based on the lottery result. Is notified.

As pachislot, there are pachislots in which the game lock affects the profit for the entire period of the game, and there are pachislots in which the game lock does not affect the profit for the entire period of the game. Further, as a pachislot, there is a pachislot in which the game lock affects the profit during a predetermined period of the game, but the game lock does not affect the profit during a specific period of the game. Therefore, during the period when the game lock affects the profit, the main side performs a notification lottery as to whether or not to notify, and based on the lottery result, both the main side and the sub side notify the predetermined push order. On the other hand, during the period when the game lock does not affect the profit, the sub side may perform a notification lottery as to whether or not to notify, and the sub side may notify the predetermined push order based on the lottery result. Good.

Since the game lock is normally controlled on the main side (main control board 71), the main control board 71 is provided with a function of transitioning the locked state according to the pressing order shown in FIG. 188A. That is, the main control board 71 draws lots for whether or not to lock the game with a probability according to the lock state setting means for setting the lock state based on the order of the detected stop operations and the lock state set by the lock state setting means. It also functions as a game lock determination means determined by the above, and a lock execution means for temporarily stopping the progress of the game when it is determined that the game lock determination means performs the game lock. Further, when the lock state setting means sets the lock state in which the game lock is easy (difficult), the main control board 71 and / or the sub control board 72 is notified by lottery as to whether or not to notify the push order. It also functions as a lottery means and a notification means for notifying a predetermined push order based on the lottery result of the notification lottery means.

[Modification example 6: Another example of termination conditions for normal ART and CT]
Normally, the termination conditions for ART and CT are not limited to the examples described in the above embodiments, and any termination conditions can be adopted. For example, the number of medals awarded during normal ART or CT, the number of times a unit game is digested during normal ART or CT, the number of times information is notified that is advantageous to the player during normal ART or CT, When the predetermined number of games (for example, 50 games) is set as one set, the end condition such as the number of sets and the continuation rate at the end of one set can be adopted.

Further, as a method for counting the number of medals given during normal ART or CT, for example, a method for counting the number of medals paid out in a unit game may be adopted, or a method of counting the number of medals paid out in a unit game may be adopted. A method of counting the difference number (net increase number) obtained by subtracting the number of bets (multiplications) of the medals used in the unit game from the number of medals played may be adopted. Further, as a method for counting the number of medals given during normal ART or CT, a method of calculating based on the actually increased medals (calculation based on the actual value) may be adopted, or has the number actually increased? Regardless of whether or not, a method of calculating based on the number of medals scheduled to increase when following the notification (calculation based on an ideal value) may be adopted.

Further, depending on the type of internal winning combination, a configuration in which the number of medals granted is not increased, that is, a configuration in which the number of medals that is the end condition of the number of medals granted or the difference is not counted may be adopted. .. For example, even if a part of the winning combination (rare role) with a low probability of being determined as the internal winning combination or a combination in which the display / non-display of the symbol combination is switched according to the timing of the stop operation is determined as the internal winning combination. , The number of medals granted may not be increased or decreased (counted).

[Modification 7: Other]
The content of the notification normally performed during ART or CT is not limited to the above-mentioned example, and is arbitrary. For example, the order of stop operations (pushing order) in which a special symbol combination that is advantageous to the player is displayed may be notified, or the timing of the stop operation required for displaying the symbol combination ( The symbol to be aimed at) may be notified.

As an advantageous state for the player, the winning probability of the internal winning combination related to the re-game does not change (or changes within a range that does not affect the game playability), but the mode of the stop operation that is advantageous for the player. It may be in a gaming state in which the notification function, that is, the AT function is activated. Further, as an advantageous state for the player, a re-game high probability state (replay time) in which the winning probability of the internal winning combination related to the re-game is high is activated, and a mode of the stop operation advantageous for the player is notified. It may be in a gaming state in which the function is activated, that is, the ART function is activated.

Further, in the pachi-slot machine 1 of the above embodiment, an example of displaying various display screens on the sub-display device 18 provided on the left side of the reel display window 4 when viewed from the player side has been described, but the present invention is not limited thereto. .. For example, another sub-display device may be provided on the right side of the reel display window 4 when viewed from the player side, and various display screens may be displayed on this sub-display device as well. In this case, a touch sensor is provided on the display surface of the sub display device provided on the right side of the reel display window 4, and the display screen of the sub display device is switched based on the touch input information output from the touch sensor. It may be.

Further, in the above-described embodiment and various modifications, the pachi-slot machine has been described as an example, but the present invention is not limited thereto. Features other than the features peculiar to pachislot 1, such as the features related to reel control and the features related to setting change and confirmation of the present invention, can be applied to a gaming machine called "pachinko", and the same effect can be obtained. For example, checksum generation and determination processing, various processing using the main CPU 101 dedicated instruction code (address specification processing using the Q register, soft timer update processing, 7-segment LED drive processing, communication data generation and storage processing, etc. ), Various processes using the non-standard ROM area and the non-standard RAM area, and the like can also be applied to "pachinko".

<Various functions of the main control board and sub control board>
The embodiments and various modifications of the pachi-slot machine 1 according to the present invention have been described above. Here, various functions possessed by the main control board 71 (main control circuit 90, main CPU 101) and the sub control board 72 (sub control circuit 200, sub CPU 201) of the pachislot machine 1 according to the present invention will be collectively described.

The main control board 71 is connected to the start switch 79 and the stop switch board 80, and controls the progress of the game shown in FIG. Therefore, the main control board 71 functions as a start operation detecting means, a symbol changing means, an internal winning combination determining means, a stop operation detecting means, a reel stop control means (stop control means), and a winning determination means.

Further, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined during normal ART, the main control board 71 performs a flag conversion lottery, and the result of this flag conversion lottery or other internal winning combination. When a CT lottery based on the above is won, CT that normally extends the duration of ART is started. Therefore, the main control board 71 also functions as a conversion lottery means and an additional game starting means.

Further, the main control board 71 adds (extends) the number of ART games indicating the duration of normal ART during CT according to the internal winning combination. Specifically, when the internal winning combination corresponding to the sub-flags "cactus", "weak cherry" or "strong cherry" is determined, the main control board 71 adds a predetermined amount of the number of ART games of normal ART. When the internal winning combination corresponding to the sub-flag "triple chili lip A or triple chili lip B" is determined, the number of ART games of normal ART is added by a specific amount. Further, when the number of times the number of ART games based on the sub-flag "triple chili lip" is added to the main control board 71 exceeds 8 times, which is the basic number of games in one set of CT, 9 times or more, the addition 1 Increase the amount added per round. Therefore, the main control board 71 also functions as an additional control means.

Further, the main control board 71 counts the number of games in which the number of ART games is not added during CT by using the CT game number counter, and when the CT game number counter counts “8”, CT ends. At this time, when the sub-flag EX "triple chili lip" is won (that is, the flag conversion lottery is won), the main control board 71 resets the CT game 8 times (8 games) per set (CT game number counter). Returns the value to the initial value). Therefore, the main control board 71 also functions as a counting means and an additional game ending means.

Further, when the bonus combination (internal winning combination "F_BB1", "F_BB2") is determined as the internal winning combination, the main control board 71 shifts the game state to the BB flag state (RT5 state) and also shifts the BB flag. In the interim state, the bonus role is carried over as an internal winning role until the bonus is activated (until the bonus role is won). Therefore, the main control board 71 also functions as a bonus carry-over means. Further, when the bonus combination is won in the state between the BB flags, the main control board 71 activates the bonus and shifts the gaming state to the bonus state. Therefore, the main control board 71 also functions as a bonus starting means and an advantageous gaming means.

Further, as shown in FIG. 25, in the main control board 71, the bonus combination and the predetermined internal winning combination (“off”, “F_special 1” to “F_special 3”) overlap in the state between the BB flags. If it is decided, stop control is performed so that the symbol combination (“C_BB1”, “C_BB2”) related to the bonus combination can be displayed, and the bonus combination and the internal winning combination other than the predetermined internal winning combination are performed. If is determined in duplicate, stop control is performed so that the symbol combination related to the bonus combination cannot be displayed. Then, when the symbol combination related to the bonus combination can be displayed during the state between the BB flags, the main control board 71 controls the instruction monitor (not shown) of the information display 6 to win the bonus combination. The bonus instruction information is notified by displaying the numerical value "10" or "11" that uniquely indicates the mode of the stop operation. On the other hand, when the symbol combination related to the bonus combination cannot be displayed during the state between the BB flags, the main control board 71 does not display (notify) the numerical values "10" and "11" on the instruction monitor. Therefore, the instruction monitor of the main control board 71 and the information display 6 functions as an instruction information notification means.

Further, at this time, the main control board 71 notifies the numerical value "10" or "11" via the instruction monitor only after the bonus notification is given. Specifically, when the main control board 71 determines the bonus combination as the internal winning combination without carrying over the bonus combination, the number of subsequent games is counted, and the bonus is given after the counting result reaches the predetermined number of times. When the combination and the predetermined internal winning combination (“missing”, “F_special 1” to “F_special 3”) are determined in duplicate, the numerical value “10” or “11” is notified via the instruction monitor. .. Therefore, the main control board 71 also functions as a counting means for counting the number of unit games after the bonus combination is determined as the internal winning combination.

The sub-control board 72 manages the game history based on various command data received from the main control board 71, and when the registration operation from the player is accepted, the sub-control board 72 accepts the registration of the player who plays the game. Therefore, the sub-control board 72 functions as a history management means and a registration receiving means.

Further, the pachi-slot machine 1 according to the present invention is provided separately from the display device 11 and the display device 11 that produce an effect according to the progress of the game, and includes a top screen 221 and a game information screen 223, 224, 225 and the like. The sub-display device 18 for displaying the display screen of the above and the touch sensor 19 provided on the display unit of the sub-display device 18, and the sub-control board 72 controls the operations of the display device 11 and the sub-display device 18. To do. Specifically, the sub-control board 72 controls the sub-display device 18 so that the game information screens 223, 224, and 225 can be displayed on the sub-display device 18 when the registration of the player is accepted. When the registration of the player is not accepted, the sub-display device 18 is controlled so that the game information screens 223, 224, and 225 cannot be displayed. Therefore, the sub-control board 72 also functions as a control means.

Further, since the main control board 71 grants various benefits according to the result of the game, it also functions as a privilege granting means. Specifically, the main control board 71 gives a privilege according to the symbol combination displayed along the effective line.

For example, in a game in which the internal winning combination "F_3 choice bell_1st" is determined, when the symbol combination related to the abbreviation "bell" is displayed on the effective line, the main control board 71 grants nine medals. When the symbol combination related to the abbreviation "bell spilled eyes" is displayed on the effective line, the main control board 71 gives 0 medals. Further, for example, in a game in which the internal winning combination "F_certain chili lip" is determined, when the symbol combination related to the abbreviation "triple chili lip" or the abbreviation "replay" is displayed on the effective line, the main control board 71 The same privilege of operating the re-game is given. Further, the main control board 71 grants a privilege based on the result of the flag conversion lottery instead of the symbol combination displayed along the effective line. For example, the main control board 71 performs a flag conversion lottery when the internal winning combination “F_certain chili lip” is determined, and when the flag conversion lottery is won, a privilege such as winning the CT lottery is given.

Further, the sub-control board 72 executes an effect according to the mode of the stop operation via the display device 11. Therefore, the sub-control board 72 and the display device 11 also function as effect executing means. At this time, if the privilege to be given differs depending on the symbol combination displayed along the effective line, the main control board 71 uniquely indicates the mode of the stop operation advantageous to the player via the instruction monitor. If the benefits given by the symbol combination displayed along the valid line are the same, the mode of the stop operation advantageous to the player is not notified. On the other hand, the sub-control board 72 executes an effect indicating the order of the stop operations regardless of whether the benefits given by the displayed symbol combinations are the same / different.

Further, the main control board 71 performs a CT lottery as to whether or not to start CT, and if the CT lottery is won, the CT is started after, for example, a predetermined number of precursory games are performed after the winning. Therefore, the main control board 71 also functions as an advantageous state lottery means and an advantageous state starting means. Further, at this time, if the internal winning combination “F_certain chili lip” or “F_1 certain chili lip” is determined during the CT precursor game, the sub-control board 72 performs a flag conversion lottery on the sub side. Therefore, the sub-control board 72 also functions as a notification lottery means.

Further, in the pachi-slot machine 1 according to the present invention, the main control board 71 is given a privilege based on the result of the flag conversion lottery, and the main control board 71 and the sub control board 72 are provided via the instruction monitor and the display device 11. Notify the push order. Therefore, the main control board 71 also functions as a privilege giving means. Further, the main control board 71, the sub control board 72, the instruction monitor and the display device 11 also function as notification means.

Further, in the pachi-slot machine 1 according to the present invention, the main control board 71 (main control circuit 90, main CPU 101) performs various control processes over the entire game operation. Therefore, the main control board 71 also functions as an arithmetic control means. Further, in the pachi-slot machine 1 according to the present invention, the main control board 71 (main control circuit 90, main CPU 101) also functions as means for executing various processes shown below.

The main control board 71 (main control circuit 90, main CPU 101) performs a checksum generation process (see FIG. 77) when a power failure occurs and a checksum check process (see FIGS. 79 and 80) when the power is restored. Therefore, the main control board 71 also functions as a sum value calculating means, a sum value subtracting means, and a sum value determining means.

The main control board 71 (main control circuit 90, main CPU 101) performs a winning search process (see FIG. 146). Therefore, the main control board 71 also functions as a privilege granting determination means and a winning combination determining means.

The main control board 71 (main control circuit 90, main CPU 101) performs communication data transmission processing (S904 during interrupt processing in FIG. 167). Therefore, the main control board 71 also functions as a data transmission means.

The main control board 71 (main control circuit 90, main CPU 101) performs a setting change confirmation process (see FIG. 68). Therefore, the main control board 71 also functions as a setting change confirmation means, a start command generation means, and an end command generation means.

The main control board 71 (main control circuit 90, main CPU 101) performs communication data storage processing (see FIG. 72) and communication data pointer update processing (see FIG. 74). Therefore, the main control board 71 also functions as a communication data generation means and a communication data generation storage means.

The main control board 71 (main control circuit 90, main CPU 101) performs a 7-segment LED drive process (see FIG. 168). Therefore, the main control board 71 also functions as a 7-segment LED drive means and an LED drive control means.

The main control board 71 (main control circuit 90, main CPU 101) performs a game return process (see FIG. 68). Therefore, the main control board 71 also functions as a game return means.

The main control board 71 (main control circuit 90, main CPU 101) performs medal acceptance / start check processing (see FIG. 83). Therefore, the main control board 71 also functions as a game start determination means and a setting confirmation means (S234).

The main control board 71 (main control circuit 90, main CPU 101) performs a medal insertion check process (see FIG. 88). Therefore, the main control board 71 also functions as a game medium reception state determination means (S255 to S258).

The main control board 71 (main control circuit 90, main CPU 101) repeatedly executes the interrupt process (see FIG. 167) at a cycle of 1.1172 msec. Therefore, the main control board 71 also functions as an interrupt processing execution means and a constant cycle processing means.

The main control board 71 (main control circuit 90, main CPU 101) performs power-on processing (see FIG. 64). Therefore, the main control board 71 also functions as a power recovery processing execution means.

The main control board 71 (main control circuit 90, main CPU 101) performs an internal lottery process (see FIG. 93). Therefore, the main control board 71 also functions as an internal lottery means.

The main control board 71 (main control circuit 90, main CPU 101) performs a symbol setting process (see FIG. 98). Therefore, the main control board 71 includes an internal winning combination generating means (S321), a flag table expanding means, a winning flag table expanding means (S324), a flag storage area designating means, a winning flag storage area designating means (S329), and flag data. It also functions as a storage means and a winning flag data storage means (S330).

The main control board 71 (main control circuit 90, main CPU 101) performs a symbol code acquisition process (see FIG. 129). Therefore, the main control board 71 also functions as a winning flag storage area designating means (S648) and a symbol code storage area setting means (S650).

The main control board 71 (main control circuit 90, main CPU 101) performs reel stop control processing (see FIG. 139). Therefore, the main control board 71 also functions as a stop operation detection result acquisition means (S714) and a stop control data storage area setting means (source code “LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)” in FIG. 140). ..

The main control board 71 (main control circuit 90, main CPU 101) performs a pull-in priority acquisition process (see FIGS. 135 and 136). Therefore, the main control board 71 includes a priority stop symbol determination means, an arbitrary combination processing means (S680 to S683), a winning flag storage area designation means (S686), a winning flag storage area designation means (S686), and a logical product calculation means. (S686) and also functions as a priority data table acquisition means (S687).

The main control board 71 (main control circuit 90, main CPU 101) performs an illegal hit check process (see FIG. 149). Therefore, the main control board 71 also functions as an error detecting means, an error processing means, a winning flag storage area designating means (S781), a logical product calculation means (S784), and an error determining means (S785).

The main control board 71 (main control circuit 90, main CPU 101) performs a winning check / medal payout process (see FIG. 151). Therefore, the main control board 71 also functions as a game medium payout means, a game medium addition means (S805), a payout end determination means (S807), and a weight generation means (S808).

The main control board 71 (main control circuit 90, main CPU 101) performs a CT lottery process during CT (see FIG. 120). Therefore, the main control board 71 also functions as a privilege granting determination means.

The main control board 71 (main control circuit 90, main CPU 101) performs a sub-flag conversion process (see FIG. 106). Therefore, the main control board 71 also functions as a first sub-flag conversion means.

Further, the main control board 71 (main control circuit 90, main CPU 101) performs a flag conversion process (see FIG. 112). Therefore, the main control board 71 also functions as a second sub-flag conversion means.

The main control board 71 (main control circuit 90, main CPU 101) performs a combination monitor aggregation process (see FIG. 155). Therefore, the main control board 71 also functions as an aggregation means.

Further, the main control board 71 (main control circuit 90, main CPU 101) performs a ratio calculation data setting process (see FIG. 157) and a ratio calculation process (approximate value formula) (FIGS. 158 and 159). Therefore, the main control board 71 also functions as a ratio calculation means.

Further, the role ratio monitor 95 controlled by the main control board 71 (main control circuit 90, main CPU 101) displays ratio information (ratio calculation result). Therefore, the combination ratio monitor 95 functions as a ratio display means.

<Supplementary note (summary of the present invention)>
[First game machine]
Conventionally, in the game machine having the above-described configuration, there is known a game machine that obtains a checksum of data stored in a RAM at the time of power failure and performs a checksum determination process obtained at the time of power failure when the power is restored (. For example, see Japanese Patent Application Laid-Open No. 2009-011375). In the gaming machine of JP-A-2009-011375, in the checksum determination process at the time of power restoration, an error notification is performed when the checksum obtained at the time of power restoration does not match the checksum obtained at the time of power failure.

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been compressed due to the complexity of the game playability, and there is a demand for reducing the capacity of processing programs and tables other than the game playability managed by the main control circuit.

The present invention has been made to solve the above-mentioned first problem, and the first object of the present invention is to reduce the capacity of processing programs, tables, etc. other than playability managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM of the main control circuit and enhancing the game playability by utilizing the free space of the ROM corresponding to the increased capacity.

In order to solve the first problem, the present invention provides a first gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A power supply means for supplying a power supply voltage (for example, a power supply board 53b and a switching regulator 94) and
When the power supply voltage exceeds a predetermined start-up voltage value (for example, 10 V), a start-up means for outputting a start-up signal to the arithmetic processing means (for example, output processing of a reset signal of the power management circuit 93).
Output of a power failure detection signal of a power management circuit 93 (for example, output of a power failure detection signal) that outputs a power failure signal to the arithmetic processing means when the power supply voltage falls below a predetermined power failure voltage value (for example, 10.5 V). Processing), and equipped with
The arithmetic processing means
A flag register (for example, flag register F) that stores data corresponding to the result of arithmetic processing, and
When the power failure means outputs the power failure signal, all the information stored in the predetermined storage area (for example, the game RAM area) in the second storage means is cumulatively added to calculate the sum value. Sum value calculation means (for example, checksum generation processing),
A sum value that sequentially subtracts information stored in the predetermined storage area from the sum value generated by the sum value calculating means when the latest power failure occurs when the activation means outputs the activation signal. Subtraction means (for example, S122 to S131 during the thumb check process) and
When the subtraction process by the checksum value subtracting means is completed for all the information stored in the predetermined storage area, the subtraction result set in the predetermined bit area (for example, zero flag) in the flag register is set. A gaming machine comprising: a sum value determining means (for example, S134 during a thumb check process) for determining the presence or absence of an abnormality based on the corresponding data.

Further, in the first gaming machine of the present invention, the sum value calculating means executes a specific instruction (for example, a POP instruction) when adding information stored in the predetermined storage area. The information of 2 bytes stored continuously is acquired and added, and the information of the read start address of the information is updated by 2 bytes.
The sum value subtracting means continuously stores the sum value by executing the specific command when subtracting the information stored in the predetermined storage area from the sum value generated when the power failure occurs. The information for bytes may be acquired and subtracted, and the information at the read start address of the information may be updated for 2 bytes.

Further, in the first gaming machine of the present invention, the arithmetic processing means has a stack pointer capable of setting the address of the predetermined storage area of the second storage means.
Even if the specific instruction executed when the sum value calculating means adds the information stored in the predetermined storage area is a dedicated instruction (for example, a POP instruction) for operating the stack pointer. Good.

According to the first gaming machine of the present invention having the above configuration, the capacity of processing programs and tables other than game playability is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the capacity is increased. The playability can be improved by using the free area of the ROM corresponding to the capacity.

[2nd to 5th game machines]
Conventionally, in a gaming machine having the above-described configuration, a gaming machine equipped with a main control device that processes numerical data by using a stack pointer as an operation command has been proposed (see, for example, Japanese Patent Application Laid-Open No. 2005-237737). ).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above-mentioned second problem, and a second object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the second problem, the present invention provides a second gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
A dedicated register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an expansion register (for example, a Q register) capable of designating a part of an address in the first storage means or the second storage means by the stored data. ) And,
The arithmetic processing means executes a predetermined instruction (for example, "BITQ" instruction, "SETQ" instruction, "LDQ" instruction, etc.) capable of designating an address in the second storage means by using the expansion register. A game machine characterized by being possible.

Further, in the second gaming machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

Further, in order to solve the second problem, the present invention provides a third gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the stop operation of the display column by the stop control means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
A dedicated register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an expansion register (for example, a Q register) capable of designating a part of an address in the first storage means or the second storage means by the stored data. ) And,
The arithmetic processing means
In the process of checking the stopped state of the display column,
The predetermined read instruction (for example, the "LDQ" instruction) that can specify the address in the second storage means is executed by using the expansion register, and the predetermined read instruction stored in the second storage means is executed. Read the information indicating the variable display status of the display column,
Next, a predetermined OR operation instruction (for example, an "ORQ" instruction) capable of designating an address in the second storage means is executed using the expansion register, and the instruction is stored in the second storage means. While reading out the information indicating the state of the variable display of the other display column, the OR operation is performed between the information and the information indicating the state of the variable display of the predetermined display column.
After that, the execution of the predetermined OR operation instruction is repeated, and the OR operation of the result of the OR operation and the information indicating the variable display state of each of the remaining display columns is repeated, and the OR is performed on all the display columns. A gaming machine characterized in that it is determined whether or not all display columns are in a stopped state based on the result of an OR operation obtained when the operation is completed.

Further, in the third gaming machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

Further, in order to solve the second problem, the present invention provides a fourth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the determination operation of the internal winning combination by the internal winning combination determining means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
A dedicated register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an expansion register (for example, a Q register) capable of designating a part of an address in the first storage means or the second storage means by the stored data. ) And,
For the internal winning combination determined by the internal winning combination determining means, the winning probability changes according to the set value for adjusting the expected value for determining the internal winning combination related to the privilege grant. Is provided,
The arithmetic processing means
In the process of determining the internal winning combination,
By executing a predetermined addition instruction (for example, "ADDQ" instruction) capable of specifying an address in the second storage means using the expansion register, the setting of the internal winning combination according to the setting to be the lottery target. The current set value is added to the start address of the area where the lottery value for each value is stored, and the address where the lottery value of the internal winning combination for each setting associated with the current set value is stored is specified. A game machine characterized by acquiring the lottery value.

Further, in the fourth gaming machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

Further, in order to solve the second problem, the present invention provides a fifth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
When the variable display of the plurality of display columns is stopped by the stop control means, a symbol corresponding to the internal winning combination related to the payout of the game medium is placed on the determination line set across the plurality of display columns. A privilege grant determination means (for example, a prize search process) for determining whether or not the combination of is stopped and displayed, and
An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the determination operation by the privilege grant determination means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
It has a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means.
The arithmetic processing means
In the process of determining whether or not the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line.
The game that can be given when a predetermined read command (for example, "LDIN" command) is executed and a combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line. The feature is that the data of the number of payouts of the medium and the judgment data corresponding to the data of the number of payouts indicating the type of the combination of the symbols corresponding to the internal winning combination related to the payout of the game medium are simultaneously acquired. A game machine to play.

Further, in the fifth gaming machine of the present invention, the arithmetic processing means is
In the process of determining whether or not the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line.
The inside related to the payout of the game medium by executing a predetermined judgment command (for example, "JSLAA" command) that can execute the judgment command, the process jump destination address designation command, and the process jump operation command with one command. It may be determined whether or not the combination of symbols corresponding to the winning combination is stopped and displayed.

According to the second to fifth gaming machines of the present invention having the above configuration, the capacity of processing programs and tables managed by the main control circuit is reduced to reduce the free capacity of the ROM (first storage means) of the main control circuit. It is possible to increase the number and improve the playability by utilizing the free area of the ROM corresponding to the increased capacity.

[6th and 7th game machines]
Conventionally, in the game machine having the above-described configuration, when an abnormality occurs in the data stored in the RAM of the main control unit, the RAM abnormality error state is controlled, the progress of the game is disabled, and the setting change mode is performed. When a new setting value is selected / set based on the setting change operation, a game machine has been proposed that cancels the state in which the game progress is disabled and makes the game progressable (the game machine is proposed). For example, see Japanese Patent Application Laid-Open No. 2007-209810).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above-mentioned third problem, and a third object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the third problem, the present invention provides a sixth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
A data transmission means for transmitting command data related to the game operation (for example, S904 (communication data transmission process) during interrupt processing) and
Setting change confirmation means (for example, setting change confirmation processing) that can execute the setting value change processing and the setting value confirmation processing for adjusting the expected value for which the internal winning combination related to the privilege grant is determined,
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a setting value change operation or confirmation operation by the setting change confirmation means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
At the start of the set value change process or the set value confirmation process, the start command generation means for generating the first command data (for example, S43 during the setting change confirmation process) and
At the end of the set value change process or the set value confirmation process, the command generation means at the end of generating the second command data (for example, S57 during the setting change confirmation process) is provided.
The first command data generation process executed by the start command generation means and the second command data generation process executed by the end command generation means are shared. A featured game machine.

Further, in the sixth gaming machine of the present invention, the arithmetic processing means has a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means.
The arithmetic processing means
When generating the first command data, a first value (for example, "005H") is set in a predetermined register (for example, L register) of the general-purpose register, and the generation process is executed.
When generating the second command data, a second value (for example, "004H") may be set in a predetermined register of the general-purpose register to execute the generation process.

Further, in order to solve the above-mentioned third problem, the present invention provides a seventh gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
A data transmission means for transmitting command data related to the game operation (for example, S904 (communication data transmission process) during interrupt processing) and
Communication data generation means for creating the command data (for example, setting change command generation / storage process and communication data storage process),
Setting change confirmation means (for example, setting change confirmation processing) that can execute the setting value change processing and the setting value confirmation processing for adjusting the expected value for which the internal winning combination related to the privilege grant is determined,
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a command data generation operation by the communication data generation means and a setting value change operation or confirmation operation by the setting change confirmation means.
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
At the start of the set value change process or the set value confirmation process, the start command generation means for generating the start command data (for example, S43 during the setting change confirmation process) and
At the end of the set value change process or the set value confirmation process, it has an end command generation means (for example, S57 during the setting change confirmation process) that generates end command data.
The start-time command data generation process executed by the start-time command generation means and the end-time command data generation process executed by the end-time command generation means are shared.
The arithmetic processing means has a plurality of general-purpose registers in which a plurality of types of data are stored when the arithmetic processing is executed by the arithmetic processing means.
The arithmetic processing means
In the command data generation process
The communication parameter used among the plurality of types of communication parameters constituting the command data is set in the corresponding general-purpose register among the plurality of general-purpose registers.
The used communication parameters set in the general-purpose register are stored in a predetermined storage area (for example, a communication data temporary storage area) in the second storage means.
When there is an unused communication parameter among the plurality of types of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter at the time of generating the command data is used as the communication parameter. Store in the storage area of
A gaming machine characterized in that a sum value of the command data is generated based on the data stored in the general-purpose register associated with a communication parameter.

Further, in the seventh game machine of the present invention, in the command data generation process, the value stored in the general-purpose register associated with the communication parameter is added to the value stored in the accumulator of the general-purpose register. By doing so, the sum value of the command data may be generated, and the generated sum value may be stored in the predetermined storage area.

According to the sixth and seventh gaming machines of the present invention having the above configuration, the capacity of the processing program and the table managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the increased capacity is increased. The playability can be improved by using the free area of the ROM of the minute.

[8th and 9th game machines]
Conventionally, in the game machine having the above-described configuration, a game machine that transmits a command from the game control board (main control circuit) to the effect control board (sub control circuit) is known (for example, see JP-A-2002-360766). ).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above-mentioned fourth problem, and a fourth object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the fourth problem, the present invention provides an eighth game machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
Data transmission means for transmitting communication data related to the game operation (for example, S904 (communication data transmission processing) during interrupt processing) and
Communication data generation and storage means (for example, communication data storage processing and communication) that creates the communication data and stores the generated communication data in a communication data storage area provided in a predetermined address range in the second storage means. Data pointer update process)
The communication data generation / storage means is
When the communication data is sequentially stored in the communication data storage area from the storage area of the start address of the predetermined address range toward the storage area of the last address, an update instruction, an upper limit determination instruction, and a determination branch instruction are issued. By executing a predetermined update instruction (for example, "ICPLD" instruction) that can be executed by one instruction, the current value of the communication data pointer, which is a parameter related to address specification in the communication data storage area, and the last address. When the current communication data pointer is less than the upper limit value, the communication data pointer is added and updated, and the current communication data pointer is the upper limit value. If the above is the case, the gaming machine is characterized by changing the communication data pointer to the lower limit value of the communication data pointer corresponding to the start address.

Further, in the eighth game machine of the present invention, when the communication data generation and storage means changes the communication data pointer to the lower limit value of the communication data pointer corresponding to the start address, the communication data storage area The communication data stored in may be invalidated.

Further, in order to solve the fourth problem, the present invention provides a ninth game machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
In the counting process (for example, the medal payout number check process) of the value of predetermined data related to the progress of the game operation,
When updating the value of the predetermined data, the current update instruction (for example, "DCPLD" instruction) that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction is executed. The value of the predetermined data is compared with the lower limit of the value of the predetermined data, and if the current value of the predetermined data is larger than the lower limit of the value of the predetermined data, the value of the predetermined data Is subtracted and updated, and if the current value of the predetermined data is equal to or less than the lower limit of the value of the predetermined data, the value of the predetermined data is held at the lower limit.

Further, in the ninth game machine of the present invention, the predetermined data may be the number of payouts of the game medium.

According to the eighth and ninth gaming machines of the present invention having the above configuration, the capacity of processing programs and tables managed by the main control circuit is reduced to reduce the free capacity of the ROM (first storage means) of the main control circuit. It is possible to increase the number and improve the playability by utilizing the free area of the ROM corresponding to the increased capacity.

[10th game machine]
Conventionally, in the game machine having the above-described configuration, a game machine controlled by a timer subtraction process by software is known (see, for example, Japanese Patent Application Laid-Open No. 2004-041261).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above-mentioned fifth problem, and a fifth object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the fifth problem, the present invention provides a tenth gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
In the counting process of the number of timers of the soft timer (for example, timer update process)
By executing a predetermined update instruction (for example, "DCPWLD" instruction) that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction, the current number of timers of the soft timer and the lower limit of the number of timers. While comparing with the value, if the current number of timers of the soft timer is larger than the lower limit value, the number of timers of the soft timer is subtracted and updated, and if the current number of timers of the soft timer is equal to or less than the lower limit value. , A gaming machine characterized in that the number of timers of the soft timer is held at the lower limit value.

In the tenth gaming machine of the present invention, the soft timer may be a 2-byte soft timer.

Further, in the tenth gaming machine of the present invention, the arithmetic processing means has a fixed cycle processing means (for example, an interrupt process repeatedly executed at a cycle of 1.1172 msec) that performs processing at a fixed cycle.
The counting process of the number of timers by the soft timer is executed by the fixed cycle processing means.
The elapsed time of the soft timer may be determined based on the cycle of processing by the fixed cycle processing means and the number of timers.

Further, in the tenth gaming machine of the present invention, the processing by the fixed cycle processing means is executed based on the interrupt signal generated by the timer function (for example, the timer circuit 113) built in the arithmetic processing means. You may do so.

According to the tenth gaming machine of the present invention having the above configuration, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit. It is possible to provide a gaming machine capable of enhancing game playability by utilizing the free area of the ROM corresponding to the increased capacity.

[11th and 12th game machines]
Conventionally, in the game machine having the above-described configuration, there is known a game machine that displays the internal lottery result with a 7-segment LED by controlling the main control circuit (see, for example, Japanese Patent Application Laid-Open No. 2008-237337).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above-mentioned sixth problem, and a sixth object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the sixth problem, the present invention provides an eleventh gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
Multiple 7-segment LEDs that broadcast specific information about the game,
A 7-segment LED driving means for driving the plurality of 7-segment LEDs (for example, a 7-segment LED driving process) and
An LED drive control means that controls the drive operation of the plurality of 7-segment LEDs by the 7-segment LED drive means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The LED drive control means
Dynamic drive control is performed on the plurality of 7-segment LEDs, a predetermined read instruction (for example, "LDW" instruction) is executed, and common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs. A game machine characterized by doing.

Further, in the eleventh gaming machine of the present invention, the arithmetic processing means has a fixed cycle processing means (for example, an interrupt process repeatedly executed at a cycle of 1.1172 msec) that performs processing at a fixed cycle.
The fixed-cycle processing means counts the number of times the processing is executed by the fixed-cycle processing means.
When the counted value is an even number, the control process by the LED drive control means may be executed.

Further, in order to solve the sixth problem, the present invention provides a twelfth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
An instruction display (for example, an instruction monitor) including a plurality of 7-segment LEDs for notifying information regarding a stop operation of the variable display of the plurality of display columns, and an instruction display (for example, an instruction monitor).
A 7-segment LED driving means for driving the plurality of 7-segment LEDs (for example, a 7-segment LED driving process) and
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling the driving operation of the plurality of 7-segment LEDs by the 7-segment LED driving means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
Dynamic drive control is performed on the plurality of 7-segment LEDs, a predetermined read instruction (for example, "LDW" instruction) is executed, and common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs. A game machine characterized by doing.

Further, in the twelfth gaming machine of the present invention, the arithmetic processing means is
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and the stored data has an expansion register (for example, a Q register) capable of designating a part of an address in the second storage means.
The arithmetic processing means in the second storage means by executing a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means using the expansion register. The address of the stop operation instruction information storage area (for example, the navigation data storage area) that is arranged in and stores the information related to the stop operation of the variation display of the plurality of display columns is specified, and the variation display of the plurality of display columns is displayed. Information about the stop operation may be stored in the stop operation instruction information storage area.

According to the eleventh and twelfth gaming machines of the present invention having the above configuration, the capacity of processing programs and tables managed by the main control circuit is reduced to reduce the free capacity of the ROM (first storage means) of the main control circuit. It is possible to increase the number and improve the playability by utilizing the free area of the ROM corresponding to the increased capacity.

[13th game machine]
Conventionally, in a game machine having the above-described configuration, a game machine in which a game control board (main control board) controls a reel unit is known (see, for example, Japanese Patent Application Laid-Open No. 2012-034914).

By the way, in the rotation control of the reel (rotating cylinder), the lack of stability of the rotation operation of the reel causes discomfort to the player (especially a skilled person), and there is a possibility that the discomfort may reduce the interest of the game. There is. In this case, the game store may be disadvantaged and the sales of the game machine itself may be affected.

The present invention has been made to solve the above-mentioned seventh problem, and a seventh object of the present invention is to suppress a lack of stability in the rotation operation of the reel and not to give a player discomfort. It is to provide a gaming machine that can be used.

In order to solve the seventh problem, the present invention provides a thirteenth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A setting switch (for example, a setting key type switch 54) for initializing a predetermined area of the second storage means is provided.
The arithmetic processing means
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
When the power is restored, the input state of the input port and the output state of the output port at the time of power failure are set, and if the display column is fluctuating at the time of power failure, it is stored in the second storage means. A game return in which the fluctuation control management information (for example, reel control management information) of the display row when a power failure occurs is cleared, and information instructing the fluctuation start of the display row is set in the fluctuation control management information of the display row. A gaming machine comprising means (for example, game return processing).

Further, in the thirteenth gaming machine of the present invention, the arithmetic processing means is
When the setting switch is in the off state, the process by the game return means is executed, and the process is executed.
When the setting switch is in the ON state, a predetermined area of the second storage means may be initialized without executing the process by the game return means.

According to the thirteenth gaming machine of the present invention having the above configuration, it is possible to suppress the lack of stability of the reel rotation operation (variation display operation of the display row) so as not to give the player discomfort. ..

[14th game machine]
Conventionally, in a game machine having the above-described configuration, a game machine capable of displaying a set value (1 to 6) by operating a setting change switch is known (for example, Japanese Patent Application Laid-Open No. 2008-245704 and Japanese Patent Application Laid-Open No. 2008-245704). 2013-042870 (see).

By the way, conventionally, while a game is being played in a game state advantageous to the player, such as during a bonus game or an ART game, a game machine whose set value cannot be confirmed is the mainstream. In such a game machine, if a bonus game or an ART game is started immediately after a cheating called "goto", the cheating cannot be confirmed, which may be disadvantageous to the game store. is there.

The present invention has been made to solve the above-mentioned eighth problem, and an eighth object of the present invention is to play a game even while the game is being played in a gaming state which is advantageous to the player. It is to provide a game machine capable of confirming information such as set values and deterring fraudulent acts such as goto.

In order to solve the eighth problem, the present invention provides a fourteenth gaming machine having the following configuration.

A setting switch located at a predetermined position inside the game machine body,
Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
An advantageous game means (for example, a bonus game described later) that executes a game state advantageous to the player based on the internal winning combination determined by the internal winning combination determining means.
A setting change confirmation means (for example, S233 during the medal reception / start check process) that can change or confirm the setting value related to the probability that the internal winning combination is determined according to the operation of the setting switch, and
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
It is equipped with a game start determination means (for example, medal reception / start check processing) for determining whether or not the game can be started.
The setting change confirmation means can change the setting value related to the probability that the internal winning combination is determined according to the operation of the setting switch when the power is turned on.
When it is determined by the game start determination means that the game can be started and the setting switch is operated, the setting change confirmation is performed by checking the setting value related to the probability that the internal winning combination is determined regardless of the game state. A gaming machine characterized in that it can be confirmed by processing by means.

Further, in the fourteenth game machine of the present invention, when the power is turned on to the game machine while the setting switch is operated, the setting change confirmation means has a predetermined storage area of the second storage means. May be initialized, the set value may be changed, and the changed set value may be stored in the second storage means.

According to the fourteenth gaming machine of the present invention having the above configuration, even during a game being played in a gaming state advantageous to the player, such as during a bonus game or an ART game, the set value and the like can be set. Information can be confirmed, and fraudulent acts such as goto can be deterred.

[15th and 16th game machines]
Conventionally, in the game machine having the above-described configuration, a game machine provided with a display device for displaying the number of inserted medals is known (see, for example, Japanese Patent Application Laid-Open No. 1999-197883).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above-mentioned ninth problem, and a ninth object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the ninth problem, the present invention provides a fifteenth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
A game medium detecting means (for example, a medal sensor) that detects a reception state (for example, a medal sensor input state) of the game medium, and
Whether or not the current change mode of the reception state of the game medium detected by the game medium detection means is normal is determined by arithmetic processing based on the reception state of the game medium detected in the previous process. A game machine including a game medium reception state determination means (for example, S255 to S258 during a medal insertion check process).

In the fifteenth game machine of the present invention, the game medium reception state determining means is a normal value of the reception state of the game medium that can be detected in the current process based on the reception state of the game medium detected in the previous process. May be calculated by a logical operation, and the normal value may be compared with the current reception state of the game medium to determine whether or not the change mode of the reception state of the game medium is normal. ..

Further, in the fifteenth game machine of the present invention, the game medium reception state determination means determines whether or not the change mode of the reception state of the game medium is normal by two bits in the 1-byte information. You may do so.

In order to solve the ninth problem, the present invention provides a sixteenth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
Display means (for example, first LED to third LED) that notifies information indicating the number of input of the game medium in a display mode corresponding to the number of input of the game medium.
An arithmetic processing means (for example, main CPU 101, medal insertion processing) that performs arithmetic processing for controlling the notification operation by the display means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
It is characterized in that lighting control data for notifying information indicating the number of input of the game medium in a display mode corresponding to the number of input of the game medium is generated by a logical operation process based on the number of input of the game medium. A game machine to play.

Further, in the sixteenth game machine of the present invention, in the logical operation process, the lighting control data of the game medium may be generated from three-bit data of information within one byte.

According to the fifteenth and sixteenth gaming machines of the present invention having the above configuration, the capacity of the processing program and the table managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the increased capacity is increased. The playability can be improved by using the free area of the ROM of the minute.

[17th and 18th game machines]
Conventionally, in a game machine having the above-described configuration, a game machine in which a main board (main control board) and a sub board (sub control board) are connected by communication and a command is transmitted from the main board to the sub board is known. (See, for example, Japanese Patent No. 5725590).

By the way, conventionally, the communication between the main control board that controls the game and the sub-control board that controls the effect is one-way communication from the main control board to the sub-control board, and when the power is turned on. There is a large gap between the start-up time of the main control board and that of the sub-control board. Therefore, the communication connection between the main control board and the sub control board at the time of turning on the power may become unstable.

The present invention has been made to solve the tenth problem, and a tenth object of the present invention is a main control board (main control means) and a sub control board (sub control means) at the time of turning on the power. The purpose of the present invention is to provide a game machine capable of stably operating communication between the two.

In order to solve the tenth problem, the present invention provides a seventeenth gaming machine having the following configuration.

A main control means (for example, a main control circuit 90) for transmitting communication data related to a game operation is provided.
The main control means
During the control process by the main control means, the interrupt process is executed at a predetermined cycle, and when the interrupt process is executed, if there is no communication data related to the game operation, the interrupt process execution means (for example,) that transmits a non-operation command. , Interrupt processing),
It has a power recovery processing execution means (for example, power-on processing) that executes a predetermined power recovery processing when the power is restored.
After the power restoration process is started, the power restoration processing executing means waits until the interrupt processing can be executed by the interrupt processing executing means (for example, S7 and S8 during the power-on processing). Do,
The interrupt processing execution means is a gaming machine characterized in that, at the end of the standby by the power recovery processing execution means, the interrupt processing is executed and the non-operation command is transmitted to the sub control means.

Further, in the seventeenth gaming machine of the present invention, the main control means is
A timer circuit (for example, timer circuit 113) that measures the predetermined cycle, and
It has an interrupt circuit (for example, an interrupt controller 112) that generates an interrupt signal for executing the interrupt process based on the timeout signal of the timer circuit.
The power recovery processing execution means is
After setting the initial setting for generating the timeout signal in the timer circuit at the predetermined cycle, a process of waiting until the interrupt process can be executed by the interrupt process executing means is performed.
The end of the standby may be determined based on the presence or absence of the occurrence of the timeout signal in the timer circuit.

Further, in order to solve the tenth problem, the present invention provides an eighteenth gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
Communication data generation means for creating command data related to game operations (for example, setting change command generation and storage processing and communication data storage processing),
During the control process by the arithmetic processing means, the interrupt processing is executed at a predetermined cycle, and when the interrupt processing is executed, if there is no command data related to the game operation, the interrupt processing execution means (for example,) that transmits a non-operation command , Interrupt processing),
Power restoration processing execution means (for example, power-on processing) that executes a predetermined power restoration processing when the power is restored, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
After the power restoration process is started, the power restoration processing executing means waits until the interrupt processing can be executed by the interrupt processing executing means (for example, S7 and S8 during the power-on processing). Do,
The interrupt processing execution means executes the interrupt processing and transmits the no-operation command at the end of the standby by the power recovery processing execution means.
The arithmetic processing means
It has a plurality of general-purpose registers in which a plurality of types of data are stored when the arithmetic processing is executed by the arithmetic processing means.
The command data is composed of a command type, a plurality of communication parameters, and a sum value.
The plurality of communication parameters are each assigned to the plurality of general-purpose registers.
The communication data generation means is
After setting the communication parameter in the general-purpose register assigned to the communication parameter according to the command type of the command data, the communication parameter set in the general-purpose register is stored in a predetermined storage in the second storage means. Store in an area (for example, communication data temporary storage area),
Even if there is a communication parameter that is not used based on the command type of the command data among the plurality of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter is used as the communication parameter. Stored in the predetermined storage area as
A gaming machine characterized in that a sum value of the command data is generated based on the command type and the data stored in the general-purpose register assigned to the communication parameter.

Further, the eighteenth gaming machine of the present invention includes a power supply monitoring means (for example, a power supply monitoring port) for monitoring the state of the power supply voltage.
The arithmetic processing means
If the power supply voltage state is not stable, wait until the power supply voltage state stabilizes, and then wait until the power supply voltage state stabilizes.
After initializing the timer circuit, serial communication circuit, and random number circuit of the arithmetic processing means on the condition that the state of the power supply voltage is stable, the predetermined area of the second storage means is used. 2 Check if the storage means are normal and check
The no-operation command may be transmitted on condition that the second storage means is normal.

According to the 17th and 18th gaming machines of the present invention having the above configuration, it is possible to stably operate the communication between the main control board and the sub control board when the power is turned on.

[19th and 20th game machines]
Conventionally, in the game machine having the above-described configuration, for example, a game machine that executes a control called pull-in control of the winning symbol of the reel and a control called kicking control of the winning symbol of the reel is known based on the lottery result. (See, for example, Japanese Patent Application Laid-Open No. 2002-219213).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Furthermore, in recent years, as the playability has become complicated and the pattern combination pattern of the winning combination (winning combination) has increased, the RAM capacity of the main control circuit has been squeezed, and the efficiency of the processing executed by the main control circuit has been improved. , Development of technology that can effectively utilize the limited RAM capacity of the main control circuit is required.

The present invention has been made to solve the eleventh problem, and the eleventh object of the present invention is to improve the efficiency of processing executed by the main control circuit and to make the RAM capacity of the main control circuit effective. It is to provide a game machine that can be utilized.

In order to solve the eleventh problem, the present invention provides a nineteenth gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
Internal lottery means (for example, internal lottery processing) that determines flag status information (for example, winning request flag status) regarding the internal winning combination with a predetermined probability, and
An internal winning combination generating means (for example, S321 during the symbol setting process) that generates an internal winning combination from the flag status information acquired by the internal lottery means, and
A flag that defines the correspondence between the internal winning combination, the flag data corresponding to the internal winning combination, and the storage destination data that specifies the storage destination of the flag data in the second storage means, and is stored in the first storage means. A flag table expanding means (for example, S324 during the symbol setting process) that expands a data table (for example, a hit request flag table) in the second storage means, and
With the flag storage area specifying means (for example, S329 during the symbol setting process) that is arranged in the second storage means and specifies the address of the flag data storage area (for example, the hit request flag storage area) that stores the flag data. ,
Flag data that transfers and stores the flag data corresponding to the internal winning combination generated by the internal winning combination generating means from the flag table into the flag data storage area based on the corresponding storage destination data. A gaming machine comprising a storage means (for example, S330 during a symbol setting process).

Further, in the nineteenth game machine of the present invention, the arithmetic processing means calculates on-bit information indicating the storage destination data of the flag data table and sets it as the on-bit information to be transferred. The flag data may be transferred to the flag data storage area.

Further, in order to solve the eleventh problem, the present invention provides a twentieth game machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an expansion register (for example, a Q register) capable of designating a part of an address in the first storage means or the second storage means by the stored data. )When,
Internal lottery means (for example, internal lottery processing) that determines flag status information (for example, winning request flag status) regarding the internal winning combination with a predetermined probability, and
An internal winning combination generating means (for example, S321 during the symbol setting process) that generates an internal winning combination from the flag status information acquired by the internal lottery means, and
A winning flag data table (for example, a winning request) that defines the correspondence between the internal winning combination, the corresponding winning flag data, and the storage destination data that specifies the storage destination of the winning flag data in the second storage means. The winning flag table expanding means (for example, S324 during the symbol setting process) that expands the flag table) in the second storage means, and
By executing a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means using the expansion register, the second storage means is arranged and the winning is achieved. Winning flag storage area designating means (for example, S329 during symbol setting processing) that specifies the address of the winning flag data storage area (for example, hit request flag storage area) for storing flag data, and
The winning flag data corresponding to the internal winning combination generated by the internal winning combination generating means is transferred from the winning flag table to the winning flag data storage area based on the corresponding storage destination data and stored. Winning flag data storage means (for example, S330 during symbol setting processing) and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal lottery means and the detection of the stop operation by the stop operation detection means.
When the variable display of the plurality of display columns is stopped by the stop control means, the combination of symbols corresponding to the internal winning combination is stopped and displayed on the determination line set across the plurality of display columns. A means for determining a winning combination (for example, a winning search process) for determining whether or not a winning combination has been made.
A winning flag data storage area (for example,) for storing winning flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line by executing the predetermined reading command (for example, The winning flag storage area designation means (for example, S648 during the symbol code acquisition process) that specifies the address of the winning operation flag storage area), and
By executing the predetermined read command, the address of the symbol code storage area for storing the symbol code data corresponding to the combination of the symbols arranged in the second storage means and stopped and displayed on the determination line is designated. A gaming machine characterized by having a symbol code storage area setting means (for example, S650 during a symbol code acquisition process).

Further, in the twentieth game machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

According to the 19th and 20th gaming machines of the present invention having the above configuration, it is possible to improve the efficiency of the processing executed by the main control circuit and effectively utilize the RAM (second storage means) capacity of the main control circuit. ..

[21st and 22nd game machines]
Conventionally, in the game machine having the above-described configuration, the stop control of the variable display of the reel symbol is performed based on the internal winning combination and the stop operation of the player, the winning judgment is made by the combination of the symbols, and the hopper is determined based on the result of the winning judgment. A gaming machine that controls (medal payout device) to control medal payout is known (see, for example, Japanese Patent Application Laid-Open No. 2008-119498).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the twelfth problem, and a twelfth object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the twelfth problem, the present invention provides a twenty-first gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the stop operation of the display column by the stop control means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
An expansion register (for example, a Q register) in which data is stored when the arithmetic processing is executed by the arithmetic processing means and a part of an address in the second storage means can be specified by the stored data.
By executing a predetermined read instruction (for example, "LDQ" instruction) capable of specifying an address in the second storage means using the expansion register, the detection result of the stop operation by the stop operation detection means can be obtained. The stop operation detection result acquisition means to be acquired (for example, S714 during the reel stop control process) and
When the player's stop operation with respect to the predetermined display row is detected by the stop operation detecting means, by executing the predetermined read command, the player is arranged in the second storage means and the predetermined display row is displayed. A stop control data storage area setting means for designating the address of the stop control data storage area for storing the stop control data of the fluctuation display (for example, the source code "LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)" in FIG. 140) and A game machine characterized by having.

Further, in the 21st gaming machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

Further, in order to solve the twelfth problem, the present invention provides a 22nd gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, the combination of a plurality of types of symbols corresponding to the plurality of types of internal winning combinations is set across the plurality of display columns. Priority stop symbol determination means (for example, pull-in priority acquisition process) for determining a combination of symbols to be preferentially stopped and displayed on the determined determination line,
An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the stop operation of the display column by the stop control means and the determination operation of the combination of symbols to be stopped and displayed by the priority stop symbol determination means.
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
An expansion register (for example, a Q register) in which data is stored when the arithmetic processing is executed by the arithmetic processing means and a part of an address in the second storage means can be specified by the stored data.
By executing a predetermined read instruction (for example, "LDQ" instruction) capable of specifying an address in the second storage means using the expansion register, the detection result of the stop operation by the stop operation detection means can be obtained. The stop operation detection result acquisition means to be acquired (for example, S714 during the reel stop control process) and
When the player's stop operation for a predetermined display row is detected by the stop operation detecting means, by executing the predetermined read command, the player is arranged in the second storage means and the predetermined display row is displayed. A stop control data storage area setting means for designating the address of the stop control data storage area for storing the stop control data of the fluctuation display (for example, the source code "LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)" in FIG. 140) and
In the process of preferentially determining the combination of symbols to be stopped and displayed on the determination line by the priority stop symbol determining means, one comparison determination instruction, a process jump destination address designation instruction, and a process jump operation instruction. By executing a predetermined determination command (for example, "JCP" instruction) that can be executed by the command, a specific display column (for example, "JCP" command) currently being determined is combined with the combination of symbols corresponding to the internal winning combination to be determined. , Right reel 3R), it is determined whether or not a predetermined combination of symbols (for example, "ANY" combination) in which the stop symbol on the determination line is arbitrary is included, and the internal winning combination to be determined is used. When it is determined that the combination of the corresponding symbols includes the combination of the predetermined symbols, the optional combination handling processing means for prohibiting the stop display of the combination of the symbols corresponding to the internal winning combination to be determined (for example, A gaming machine characterized by having S683) in the process of acquiring a pull-in priority.

Further, in the 22nd gaming machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

According to the 21st and 22nd gaming machines of the present invention having the above configuration, the capacity of the processing program and the table managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the increased capacity is increased. The playability can be improved by using the free area of the ROM of the minute.

[23rd to 25th game machines]
Conventionally, in the game machine having the above-described configuration, there is known a game machine that controls the stop of a symbol by using a pull-in priority table at the time of stop control of a symbol (see, for example, Japanese Patent Application Laid-Open No. 2007-175450).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the thirteenth problem, and the thirteenth object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the thirteenth problem, the present invention provides a twenty-third gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, the combination of a plurality of types of symbols corresponding to the plurality of types of internal winning combinations is set across the plurality of display columns. Priority stop symbol determination means (for example, pull-in priority acquisition process) for determining a combination of symbols to be preferentially stopped and displayed on the determined determination line,
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a determination operation of a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
It has an extension register (for example, a Q register) in which data is stored when the arithmetic processing is executed by the arithmetic processing means and a part of an address in the second storage means can be specified by the stored data. ,
In the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means.
The arithmetic processing means
By executing a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means using the expansion register, the second storage means is arranged and inside the second storage means. The winning flag storage area specifying means (for example, S686 during the pull-in priority acquisition process) that specifies the address of the winning flag data storage area (for example, the winning request flag storage area) that stores the winning flag data corresponding to the winning combination, and
A winning flag data storage area (for example,) for storing winning flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line by executing the predetermined reading command (for example, The winning flag storage area specifying means (for example, S686 during the attraction priority acquisition process) that specifies the address of the winning operation flag storage area), and
A gaming machine characterized by having a logical product calculation means (for example, S686 during a pull-in priority acquisition process) that performs a logical product calculation of the winning flag data and the corresponding winning flag data.

Further, in the 23rd game machine of the present invention, in the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, the combination of symbols corresponding to the internal winning combination to be determined. Includes a combination of predetermined symbols (for example, "ANY" combination) in which the stop symbol on the determination line in the specific display column (for example, the right reel 3R) currently being determined is arbitrary.
The arithmetic processing means includes address designation processing of the winning flag data storage area by the winning flag storage area designating means, address designation processing of the winning flag data storage area by the winning flag storage area designating means, and AND operation. The logical product operation processing by the means may not be executed.

Further, in order to solve the thirteenth problem, the present invention provides a twenty-fourth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, the combination of a plurality of types of symbols corresponding to the plurality of types of internal winning combinations is set across the plurality of display columns. Priority stop symbol determination means (for example, pull-in priority acquisition process) for determining a combination of symbols to be preferentially stopped and displayed on the determined determination line,
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a determination operation of a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
Data is stored when the arithmetic processing is executed by the arithmetic processing means, and an expansion register (for example, a Q register) capable of designating a part of an address in the first storage means or the second storage means by the stored data. ) And,
In the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means.
The arithmetic processing means
By executing a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means using the expansion register, the second storage means is arranged and inside the second storage means. The winning flag storage area specifying means (for example, S686 during the pull-in priority acquisition process) that specifies the address of the winning flag data storage area (for example, the winning request flag storage area) that stores the winning flag data corresponding to the winning combination, and
A winning flag data storage area (for example,) for storing winning flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line by executing the predetermined reading command (for example, The winning flag storage area specifying means (for example, S686 during the attraction priority acquisition process) that specifies the address of the winning operation flag storage area), and
A logical product calculation means (for example, S686 during the attraction priority acquisition process) that performs a logical product operation of the winning flag data and the corresponding winning flag data, and
Priority data table acquisition means (for example, pull-in priority) for acquiring a data table that defines the priority of the combination of symbols to be stopped and displayed among the combinations of the plurality of types of symbols by executing the predetermined read command. A gaming machine comprising S687) during acquisition processing.

Further, in the 24th game machine of the present invention, in the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, the combination of symbols corresponding to the internal winning combination to be determined. Includes a combination of predetermined symbols (for example, "ANY" combination) in which the stop symbol on the determination line in the specific display column (for example, the right reel 3R) currently being determined is arbitrary.
The arithmetic processing means includes address designation processing of the winning flag data storage area by the winning flag storage area designating means, address designation processing of the winning flag data storage area by the winning flag storage area designating means, and AND operation. The logical product operation processing by the means may not be executed.

Further, in order to solve the thirteenth problem, the present invention provides a twenty-fifth gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
Error detection means (for example, illegal hit check processing) that determines whether or not an illegal hit error has occurred, and
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a determination operation by the error detecting means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
A general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
It has an extension register (for example, a Q register) in which data is stored when the arithmetic processing is executed by the arithmetic processing means and a part of an address in the second storage means can be specified by the stored data. ,
In the process of determining whether or not an illegal hit error has occurred by the error detecting means,
The arithmetic processing means
By executing a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means using the expansion register, the second storage means is arranged and the plurality. Winning flag that specifies the address of the winning flag data storage area (for example, the winning operation flag storage area) that stores the winning flag data corresponding to the combination of symbols that are stopped and displayed on the judgment line set across the display column of Storage area designation means (for example, S781 during illegal hit check processing) and
A logical product calculation means (for example, S784 during illegal hit check processing) that performs a logical product operation of the winning flag data stored in the winning flag data storage area and the winning flag data indicating the corresponding internal winning combination. When,
It has an error determining means (for example, S785 during the illegal hit check process) for determining whether or not an illegal hit error has occurred based on the calculation result of the AND calculation means.
A gaming machine characterized in that the configuration of the winning flag data storage area (for example, the winning request flag storage area) in which the winning flag data is stored is the same as the configuration of the winning flag data storage area.

Further, in the 25th gaming machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

Further, in the 25th gaming machine of the present invention, the arithmetic processing means has an error processing means for performing error processing when it is determined by the error detecting means that there is an illegal hit error.
The error processing means may visually notify the illegal hit error and stop the game until the illegal hit error is cleared.

According to the 23rd to 25th gaming machines of the present invention having the above configuration, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the increased capacity is increased. The playability can be improved by using the free area of the ROM of the minute.

[26th game machine]
Conventionally, in a game machine having the above-described configuration, a game machine that transmits command data from a game control board (main control board) to an effect control board (sub-control board) is known (for example, Japanese Patent Application Laid-Open No. 2013-027655). And Japanese Patent Application Laid-Open No. 2014-033751).

By the way, in recent years, with the diversification of playability, there is a tendency that the processing related to playability increases in the effect control by the sub-control circuit. Therefore, a fraudulent act called "goto" that falsifies the communication data transmitted from the main control circuit to the sub control circuit has occurred, causing damage to the amusement store. On the other hand, conventionally, as proposed in Japanese Patent Application Laid-Open No. 2014-033751 and the like, measures have been taken to prevent the transmission data from being squeezed in the main control circuit. However, the addition of such anti-goto processing causes a problem that the program capacity of the main control circuit is squeezed.

The present invention has been made to solve the above-mentioned fourteenth problem, and the fourteenth object of the present invention is to suppress fraudulent acts without performing fraud prevention processing on transmitted data, and at the same time. It is to provide a gaming machine capable of eliminating the pressure on the program capacity of the main control circuit due to fraud prevention processing.

In order to solve the 14th problem, the present invention provides a 26th gaming machine having the following configuration.

A data transmission means (for example, a main control circuit 90) for transmitting communication data related to the game operation, and
A communication data generation means (for example, communication data storage process) for creating the communication data, and
An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a communication data generation operation by the communication data generation means, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The arithmetic processing means
It has a plurality of general-purpose registers in which a plurality of types of data are stored when the arithmetic processing is executed by the arithmetic processing means.
The arithmetic processing means
In the communication data generation process by the communication data generation means.
A plurality of types of communication parameters constituting the communication data are assigned to the plurality of general-purpose registers, respectively.
Among the plurality of types of communication parameters constituting the communication data, the communication parameter is set in the corresponding general-purpose register among the plurality of general-purpose registers based on the type of the communication data.
The communication parameters set in the general-purpose register are stored in a predetermined storage area (communication data temporary storage area) in the second storage means.
Among the plurality of types of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter at the time of generating the communication data is stored as the communication parameter in the predetermined storage area.
A gaming machine characterized in that a sum value of the communication data is generated based on data set in the plurality of general-purpose registers according to the plurality of types of communication parameters.

Further, in the 26th gaming machine of the present invention, the communication data generating means is set in the plurality of general-purpose registers when there is no space in a predetermined storage area in the second storage means. The communication data generation process may be terminated without storing the parameters in the predetermined storage area in the second storage means.

According to the 26th gaming machine of the present invention having the above configuration, fraudulent activity can be suppressed without performing fraud prevention processing on the transmitted data (communication data), and the program capacity of the main control circuit by the fraud prevention processing. The pressure on the device can be eliminated.

[27th game machine]
Conventionally, in the game machine having the above-described configuration, a game machine having a function of updating the number of credits according to the number of medals paid out by the control of the main control circuit is known (for example, Japanese Patent Application Laid-Open No. 2009- 077977 (see).

By the way, conventionally, in games during ART or bonus, medals are paid out more frequently, but at this time, the payout interval for each medal is often controlled uniformly (constantly). In this case, a wasteful waiting time occurs during the medal payout period. Therefore, for example, in a long-time game such as ART, the game period becomes unnecessarily long, which may be a mental burden on the player.

The present invention has been made to solve the above fifteenth problem, and the fifteenth object of the present invention is to reduce unnecessary waiting time and reduce the mental burden on the player during the medal payout period. It is to provide a game machine capable of being able to do so.

In order to solve the fifteenth problem, the present invention provides a 27th gaming machine having the following configuration.

Insertion operation detection means (for example, BET switch 77) for detecting the insertion operation of the game medium, and
A start operation detecting means (for example, a start switch 79) that detects a start operation by the player after the throwing operation is detected by the throwing operation detecting means,
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A variable display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display columns and variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means.
A stop operation detection means (for example, a stop switch board 80) that detects a stop operation by the player, and
A stop control means (for example, a reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determining means and the detection of the stop operation by the stop operation detecting means.
When the variable display of the plurality of display columns is stopped by the stop control means, a symbol corresponding to the internal winning combination related to the payout of the game medium is placed on the determination line set across the plurality of display columns. A privilege grant determination means (for example, a prize search process) for determining whether or not the combination of is stopped and displayed, and
When it is determined by the privilege grant determination means that the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line, the game medium payout means (for example, the game medium payout means) for paying out the game medium. , Winning check, medal payout processing),
A game medium storage means (for example, a credit function) for storing the game medium, and
A calculation processing means (for example, main CPU 101) that performs calculation processing for controlling the payout operation of the game medium by the game medium payout means is provided.
The arithmetic processing means
It is determined by the privilege grant determination means that the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line, and the game medium stored in the game medium storage means. When the number of stored games is less than the upper limit, the game medium adding means (for example, S805 during the winning check / medal payout process) that adds 1 to the number of stored game media is used.
The game medium is given when the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed after the game medium is added to the stored number of the game media by the game medium adding means. A payout end determination means (for example, S807 during the winning check / medal payout process) for determining whether or not the total number of payouts of the game medium has been paid out, and
When it is determined by the payout end determination means that the payout of the total number of payouts of the game medium has not been completed, the weight generation means (for example, a winning check) that generates a weight that invalidates the operation related to the game for a predetermined period. A gaming machine characterized by having S808) in the process of paying out medals.

Further, in the 27th gaming machine of the present invention, the arithmetic processing means has an interrupt processing executing means for executing an interrupt processing at a predetermined cycle.
In the wait in which the operation related to the game by the wait generating means is invalid, the interrupt processing by the interrupt processing executing means may be executed a predetermined number of times.

According to the 27th gaming machine of the present invention having the above configuration, it is possible to reduce unnecessary waiting time and reduce the mental burden on the player during the medal (game medium) payout period.

[28th and 29th game machines]
Conventionally, in the game machine having the above-described configuration, there is known a game machine in which a lottery table for determining an internal winning combination or an AT game is stored in a ROM (see, for example, Japanese Patent Application Laid-Open No. 2009-125459).

By the way, in the game machine described in JP-A-2009-125459, the lottery table and the lottery processing program of AT games are stored in a ROM provided on a sub-control board having a sufficient storage capacity. However, for reasons peculiar to the game machine industry in recent years, it is necessary to store the table and the program related to the lottery of the AT game in the ROM provided on the main control board. Therefore, the ROM capacity of the main control board, which is limited to a small capacity, is compressed.

The present invention has been made to solve the above 16th problem, and the 16th object of the present invention is to reduce the amount of data used in the processing of the main control circuit and to free the ROM of the main control circuit. It is to provide a game machine capable of increasing the capacity.

In order to solve the 16th problem, the present invention provides a 28th gaming machine having the following configuration.

A start operation detecting means (for example, a start switch 79) for detecting a start operation by a player, and
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
Based on the internal winning combination determined by the internal winning combination determining means, the privilege granting determining means (for example, CT lottery processing during CT) determines by lottery whether or not to grant a gaming state advantageous to the player as a privilege. When,
A lottery table referred to by the privilege granting determination means (for example, a CT winning lottery table during CT) is provided.
At the lottery table
Judgment data (for example, determination bit) that specifies the type of the internal winning combination to be the lottery target and the lottery value of the internal winning combination to be the lottery target specified by the determination data are defined.
The lottery value of the internal winning combination that is not subject to lottery is not specified.
A value other than 0 is specified for the lottery value of the internal winning combination of the lottery target having a winning probability of less than 100%, and 0 is specified for the lottery value of the internal winning combination of the lottery target having a winning probability of 100%. A game machine characterized by being.

Further, in the 28th game machine of the present invention, the privilege granting determination means is
Obtain a 1-byte random number value from a soft latch random number and obtain it.
By drawing using the acquired random number value and the lottery value, it may be determined whether or not to give a gaming state advantageous to the player as a privilege.

In order to solve the 16th problem, the present invention provides a 29th gaming machine having the following configuration.

A start operation detecting means (for example, a start switch 79) for detecting a start operation by a player, and
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
Based on the internal winning combination determined by the internal winning combination determining means, the privilege granting determining means (for example, CT lottery processing during CT) determines by lottery whether or not to grant a gaming state advantageous to the player as a privilege. When,
A lottery table (for example, a CT winning lottery table during CT), which is referred to by the privilege granting determining means and is provided for each type of the internal winning combination,
A lottery table selection table for selecting the lottery table associated with the currently determined internal winning combination (for example, a table selection relative table for each winning combination) is provided.
In the lottery table selection table,
For each type of the internal winning combination, it is possible to determine whether or not the internal winning combination of the type is a lottery target, and it is possible to specify the placement destination of the lottery table associated with the internal winning combination of the type. The selection value is specified,
The selection value of the internal winning combination that is not subject to lottery is defined as 0, which treats the lottery result by the privilege granting determination means as a loss.
A gaming machine characterized in that data other than 0 is defined in the selected value of the internal winning combination to be a lottery target.

Further, in the 29th game machine of the present invention, the selection value of the lottery table selection table is a relative value up to the lottery table to be selected, and even if the relative value is a value of 1 byte. Good.

According to the 28th and 29th gaming machines of the present invention having the above configuration, the amount of data used in the processing of the main control circuit can be reduced, and the free space of the ROM of the main control circuit can be increased.

[30th game machine]
Conventionally, in the gaming machine having the above-described configuration, the program and the table are arranged in a fixed area in the ROM mounted on the main control board (see, for example, Japanese Patent Application Laid-Open No. 2012-110635).

By the way, the programs and tables that can be arranged in the ROM of the main control board like the game machine described in JP2012-110635A are limited by the rules of the game machine industry, and the ROM of the main control board. The extensibility of programs and tables within is extremely poor.

The present invention has been made to solve the above-mentioned seventeenth problem, and the seventeenth object of the present invention is a gaming machine capable of enhancing the expandability of a program and a table in a ROM of a main control board. Is to provide.

In order to solve the 17th problem, the present invention provides a 30th gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and
A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means is provided.
The first storage means includes a game storage area (for example, a game ROM area) in which information necessary for executing a process related to the game playability of the game performed by the player is stored, and the game memory. An out-of-specification storage area (for example, an out-of-specification ROM area) that is arranged in an area different from the area and stores information necessary for executing a process that is not related to the playability of the game performed by the player is provided. A game machine characterized by being.

Further, in the thirtieth gaming machine of the present invention, the second storage means is for gaming in which information necessary for executing a process related to the playability of the game performed by the player is temporarily stored. The game playability of the game, which is arranged in an area different from the game temporary storage area (for example, the game RAM area) including the work area and the game stack area and the game temporary storage area, and is performed by the player. A non-standard work area for temporarily storing information necessary for executing processing that is not related to the non-standard and a non-standard temporary storage area (for example, a non-standard RAM area) including a non-standard stack area are provided. May be good.

Further, in the thirtieth gaming machine of the present invention, the arithmetic processing means has a stack pointer as a dedicated register.
The arithmetic processing means
When executing a program stored in the non-standard storage area of the first storage means, the address of the non-standard stack area of the second storage means is set in the stack pointer.
When terminating the program stored in the non-standard storage area of the first storage means, the game of the second storage means saved when executing the program stored in the non-standard storage area. The address of the stack area may be set in the stack pointer to return to the program stored in the game storage area of the first storage area.

According to the thirtieth gaming machine of the present invention having the above configuration, the expandability of the program and the table in the ROM of the main control board can be enhanced.

[31st game machine]
Conventionally, in the gaming machine having the above-described configuration, in order to use the information of the internal winning combination determined by the main control circuit in the production control of the sub-control circuit, the internal winning combination is converted into a sub-flag that summarizes the types in group units. A gaming machine having a function is known (see, for example, Japanese Patent Application Laid-Open No. 2010-051471).

In the gaming machine described in JP-A-2010-051471, the conversion table and the conversion processing program for converting the internal winning combination into sub-flags are stored in a ROM provided on the sub-control board having a sufficient storage capacity. Has been done. However, for reasons peculiar to the amusement machine industry in recent years, the information of the internal winning combination determined by the main control circuit cannot be transmitted to the sub control circuit, and a conversion table and a conversion processing program related to the sub flag are also provided on the main control board. It is necessary to store it in the ROM. In this case, these tables and programs put pressure on the ROM capacity of the main control board, which is limited to a small capacity. Therefore, it is required to develop a technology that can suppress the pressure on the ROM capacity of the main control board by the conversion table and conversion processing program related to the sub-flag, and can efficiently respond to changes in the model, planning, specifications, etc. of the game machine. ing.

The present invention has been made to solve the above-mentioned eighteenth problem, and the eighteenth object of the present invention is to suppress pressure on the ROM capacity of the main control board, and to obtain a model, plan, and specification of a game machine. It is to provide a game machine capable of efficiently responding to such changes.

In order to solve the 18th problem, the present invention provides a 31st gaming machine having the following configuration.

A start operation detecting means (for example, a start switch 79) for detecting a start operation by a player, and
An internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means.
A first sub-flag conversion means (for example, sub-flag conversion process) that converts the internal winning combination determined by the internal winning combination determining means into a first sub-flag (for example, a sub-flag) with reference to a conversion table.
The first sub-flag obtained by the conversion process by the first sub-flag conversion means is converted into a second sub-flag (for example, sub-flag EX) by lottery with reference to a lottery table (for example, various flag conversion lottery tables). A second sub-flag conversion means (for example, flag conversion processing) is provided.
In the conversion table, the correspondence between the internal winning combination, the control status data associated with the internal winning combination, and the first sub-flag is defined, and the correspondence between the first sub-flag of the same type is defined. The control status data with the same value is assigned and
A gaming machine characterized in that the lottery by the second sub-flag conversion means is performed based on the control status data.

Further, the gaming machine of the present invention includes a data transmitting means for transmitting command data related to the gaming operation.
The data transmitting means may transmit the first sub-flag as a communication parameter of command data when the start operation detecting means detects a start operation.

According to the 31st gaming machine of the present invention having the above configuration, it is possible to suppress the pressure on the ROM capacity of the main control board and efficiently respond to changes in the model, planning, specifications, etc. of the gaming machine.

[32nd to 37th game machines]

In recent years, in a game machine having the above-described configuration, from the viewpoint of monitoring fraudulent activities, etc., by aggregating game information such as the number of payouts of game media, ratio information such as the payout rate and the bonus ratio has been derived. (For example, see Japanese Patent Application Laid-Open No. 2016-0872335).

By the way, in such a game machine, a so-called 8-bit CPU is generally mounted as the CPU of the main control circuit. In an 8-bit CPU, the data that can be calculated at one time is limited to a numerical range of 2 bytes (that is, 0 to 65535). Therefore, when the numerical range exceeds 65536 (that is, 3 bytes or more), it is a digit. Special arithmetic processing such as raising and lowering is required.

Here, for example, in the gaming machine shown in JP-A-2016-0872335, if the target to be aggregated by the CPU of the main control circuit is within a 2-byte numerical range, it is special in deriving the ratio information. No arithmetic processing is required, but if the numerical value exceeds 2 bytes, special arithmetic processing is required to derive the ratio information.

Therefore, in the gaming machine shown in JP-A-2016-0872335, it is necessary to limit the target to be aggregated within a 2-byte numerical range, or to incorporate a complicated program or the like for performing special arithmetic processing. Will occur. In this case, there is a problem that the desired ratio information cannot be derived, or the CPU of the main control circuit is heavily loaded, which may interfere with the control of the original game operation.

The present invention has been made to solve the 19th problem, and is capable of deriving desired ratio information without imposing an excessive burden on the main control circuit mounted on the game machine. The purpose is to provide.

In order to solve the 19th problem, the present invention provides a 32nd gaming machine having the following configuration.

A control means for controlling the game operation (for example, the main CPU 101) and
A first storage means (main ROM 102) in which a process for the control means to execute control is stored, and
A second storage means (main RAM 103) in which information for the control means to execute control is stored, and
Aggregation means (for example, combination monitor aggregation processing by the main CPU 101) that aggregates a plurality of information related to the game, and
A ratio calculation means (for example, a ratio calculation data setting process and a ratio calculation process by the main CPU 101) that performs a ratio calculation based on the aggregation result by the aggregation means, and
A ratio display means (for example, a combination ratio monitor 95) for displaying a ratio calculation result by the ratio calculation means is provided.
The control means has a function of performing an operation of at least N (for example, an integer of 1 or more) bytes.
The second storage means
A plurality of aggregation result storage areas (for example, a numerator data storage area and a denominator data storage area in each calculation data table) composed of N + 1 bytes or more for storing the aggregation results by the aggregation means, and
It has a plurality of ratio result storage areas (for example, display data storage areas in each calculation data table) for storing ratio calculation results by the ratio calculation means.
The ratio calculation means
The denominator and numerator corresponding to the type of ratio calculation are selected from the aggregation results stored in the plurality of aggregation result storage areas, respectively.
A valid unit is detected from the upper digit in the selected aggregation result storage area, and a 100% fraction calculation is performed using the range of N bytes from the detected valid unit (for example, a ratio calculation process (approximate value formula) is performed). A game machine characterized in that the ratio calculation result is calculated by this.

According to the 32nd gaming machine of the present invention having the above configuration, desired ratio information can be derived without imposing an excessive load on the main control circuit mounted on the gaming machine.

Further, in order to solve the 19th problem, the present invention provides a 33rd game machine having the following configuration.

A control means for controlling the game operation (for example, the main CPU 101) and
A first storage means (main ROM 102) in which a process for the control means to execute control is stored, and
A second storage means (main RAM 103) in which information for the control means to execute control is stored, and
Aggregation means (for example, combination monitor aggregation processing by the main CPU 101) that aggregates a plurality of information related to the game, and
A ratio calculation means (for example, a ratio calculation data setting process and a ratio calculation process by the main CPU 101) that performs a ratio calculation based on the aggregation result by the aggregation means, and
A ratio display means (for example, a combination ratio monitor 95) for displaying a ratio calculation result by the ratio calculation means is provided.
The control means has a function of performing an operation of at least N (for example, an integer of 1 or more) bytes.
The second storage means
A plurality of aggregation result storage areas (for example, a numerator data storage area and a denominator data storage area in each calculation data table) composed of N + 1 bytes or more for storing the aggregation results by the aggregation means, and
It has a plurality of ratio result storage areas (for example, display data storage areas in each calculation data table) for storing ratio calculation results by the ratio calculation means.
The ratio calculation means
The denominator and numerator corresponding to the type of ratio calculation are selected from the aggregation results stored in the plurality of aggregation result storage areas, respectively.
A valid unit is detected from the upper digit in the selected aggregation result storage area, and a 100% fraction calculation is performed using the range of N bytes from the detected valid unit (for example, a ratio calculation process (approximate value formula) is performed). By calculating the ratio calculation result,
If the calculated ratio calculation result should be subjected to a predetermined correction process (for example, S2071 during the ratio calculation process by the main CPU 101), the ratio calculation result is calculated after performing the predetermined correction process. Stored in the ratio result storage area according to the type,
The ratio display means is a gaming machine characterized in that the ratio stored in the plurality of ratio result storage areas is displayed based on a predetermined condition.

According to the 33rd gaming machine of the present invention having the above configuration, desired ratio information can be derived without imposing an excessive load on the main control circuit mounted on the gaming machine, and the derived ratio information can be derived. Can be displayed properly.

Further, in order to solve the 19th problem, the present invention provides a 34th gaming machine having the following configuration.

A control means for controlling the game operation (for example, the main CPU 101) and
A first storage means (main ROM 102) in which a process for the control means to execute control is stored, and
A second storage means (main RAM 103) in which information for the control means to execute control is stored, and
Aggregation means (for example, combination monitor aggregation processing by the main CPU 101) that aggregates a plurality of information related to the game, and
A ratio calculation means (for example, a ratio calculation data setting process and a ratio calculation process by the main CPU 101) that performs a ratio calculation based on the aggregation result by the aggregation means, and
A ratio display means (for example, a combination ratio monitor 95) for displaying a ratio calculation result by the ratio calculation means is provided.
The control means has a function of performing an operation of at least N (for example, an integer of 1 or more) bytes.
The second storage means
A plurality of aggregation result storage areas (for example, a numerator data storage area and a denominator data storage area in each calculation data table) composed of N + 1 bytes or more for storing the aggregation results by the aggregation means, and
It has a plurality of ratio result storage areas (for example, display data storage areas in each calculation data table) for storing ratio calculation results by the ratio calculation means.
The ratio calculation means
The denominator and numerator corresponding to the type of ratio calculation are selected from the aggregation results stored in the plurality of aggregation result storage areas, respectively.
A valid unit is detected from the upper digit in the selected aggregation result storage area, and a 100% fraction calculation is performed using the range of N bytes from the detected valid unit (for example, a ratio calculation process (approximate value formula) is performed). By calculating the ratio calculation result,
When the predetermined non-display condition is not satisfied, the ratio display means displays the ratio stored in the plurality of ratio result storage areas based on the predetermined condition, and the predetermined non-display condition is satisfied. If so, the gaming machine is characterized in that the ratios stored in the plurality of ratio result storage areas are not displayed.

According to the 34th gaming machine of the present invention having the above configuration, desired ratio information can be derived without imposing an excessive load on the main control circuit mounted on the gaming machine, and the derived ratio information can be derived. Can be displayed appropriately, the control burden related to the display of the ratio can be reduced, and the life of the device for displaying the ratio can be extended.

Further, in order to solve the 19th problem, the present invention provides a 35th gaming machine having the following configuration.

A control means for controlling the game operation (for example, the main CPU 101) and
A first storage means (main ROM 102) in which a process for the control means to execute control is stored, and
A second storage means (main RAM 103) in which information for the control means to execute control is stored, and
Aggregation means (for example, combination monitor aggregation processing by the main CPU 101) that aggregates a plurality of information related to the game, and
A ratio calculation means (for example, a ratio calculation data setting process and a ratio calculation process by the main CPU 101) that performs a ratio calculation based on the aggregation result by the aggregation means, and
A ratio display means (for example, a combination ratio monitor 95) for displaying a ratio calculation result by the ratio calculation means is provided.
The control means has a function of performing an operation of at least N (for example, an integer of 1 or more) bytes.
The second storage means
A plurality of aggregation result storage areas (for example, numerator data storage area and denominator data storage area in the calculation data table) composed of N + 1 bytes or more for storing the aggregation result by the aggregation means, and
It has a ratio result storage area (for example, a display data storage area in a calculation data table) for storing a ratio calculation result by the ratio calculation means.
The plurality of aggregation result storage areas are
A first aggregation result storage area (for example, a molecular data storage area in a calculation data table) for storing the first aggregation result by the aggregation means, and
It includes at least a second aggregation result storage area (for example, a denominator data storage area in the calculation data table) for storing the second aggregation result by the aggregation means.
The ratio calculation means
When a specific ratio calculation condition is satisfied, the numerator of the first aggregation result stored in the first aggregation result storage area is a predetermined N bytes, and the numerator is stored in the second aggregation result storage area. The ratio calculation result is calculated using the predetermined N bytes of the second aggregation result as the denominator.
When the calculated ratio calculation result should be subjected to a predetermined correction process (for example, S2071 during the ratio calculation process by the main CPU 101), the ratio calculation result is obtained as the ratio result after the predetermined correction process is performed. A gaming machine characterized in that it is stored in a storage area.

Further, in order to solve the 19th problem, the present invention provides a 36th gaming machine having the following configuration.

A control means for controlling the game operation (for example, the main CPU 101) and
A first storage means (main ROM 102) in which a process for the control means to execute control is stored, and
A second storage means (main RAM 103) in which information for the control means to execute control is stored, and
Aggregation means (for example, combination monitor aggregation processing by the main CPU 101) that aggregates a plurality of information related to the game, and
A ratio calculation means (for example, a ratio calculation data setting process and a ratio calculation process by the main CPU 101) that performs a ratio calculation based on the aggregation result by the aggregation means, and
A ratio display means (for example, a combination ratio monitor 95) for displaying a ratio calculation result by the ratio calculation means is provided.
The control means has a function of performing an operation of at least N (for example, an integer of 1 or more) bytes.
The second storage means
A plurality of aggregation result storage areas (for example, numerator data storage area and denominator data storage area in the calculation data table) composed of N + 1 bytes or more for storing the aggregation result by the aggregation means, and
It has a ratio result storage area (for example, a display data storage area in a calculation data table) for storing a ratio calculation result by the ratio calculation means.
The plurality of aggregation result storage areas are
A first aggregation result storage area (for example, a molecular data storage area in a calculation data table) for storing the first aggregation result by the aggregation means, and
It includes at least a second aggregation result storage area (for example, a denominator data storage area in the calculation data table) for storing the second aggregation result by the aggregation means.
The ratio calculation means
When a specific ratio calculation condition is satisfied, the numerator of the first aggregation result stored in the first aggregation result storage area is a predetermined N bytes, and the numerator is stored in the second aggregation result storage area. The quotient is calculated by using the predetermined N bytes of the second aggregation result as the denominator and dividing the numerator by the denominator.
Multiply the quotient by the second tabulation result to calculate the product.
The product is compared with the numerator multiplied by the predetermined value, and if the product is larger, the quotient is subtracted by 1, and the subtraction result is stored in the ratio result storage area as the ratio calculation result. A featured gaming machine.

According to the 35th and 36th gaming machines of the present invention having the above configuration, desired ratio information can be derived without imposing an excessive load on the main control circuit mounted on the gaming machine, and is approximated. Even when the ratio information is calculated based on the value, it is possible to prevent an error from occurring between the value and the true value.

Further, in order to solve the 19th problem, the present invention provides a 37th gaming machine having the following configuration.

A control means for controlling the game operation (for example, the main CPU 101) and
A first storage means (main ROM 102) in which a process for the control means to execute control is stored, and
A second storage means (main RAM 103) in which information for the control means to execute control is stored, and
Aggregation means (for example, combination monitor aggregation processing by the main CPU 101) that aggregates a plurality of information related to the game, and
A ratio calculation means (for example, a ratio calculation data setting process and a ratio calculation process by the main CPU 101) that performs a ratio calculation based on the aggregation result by the aggregation means, and
A ratio display means (for example, a combination ratio monitor 95) for displaying a ratio calculation result by the ratio calculation means is provided.
The control means has a function of performing an operation of at least N (for example, an integer of 1 or more) bytes.
The second storage means
A plurality of aggregation result storage areas (for example, numerator data storage area and denominator data storage area in the calculation data table) composed of N + 1 bytes or more for storing the aggregation result by the aggregation means, and
It has a ratio result storage area (for example, a display data storage area in a calculation data table) for storing a ratio calculation result by the ratio calculation means.
The plurality of aggregation result storage areas are
A first aggregation result storage area (for example, a molecular data storage area in a calculation data table) for storing the first aggregation result by the aggregation means, and
It includes at least a second aggregation result storage area (for example, a denominator data storage area in the calculation data table) for storing the second aggregation result by the aggregation means.
The ratio calculation means
When a specific ratio calculation condition is satisfied, the numerator of the first aggregation result stored in the first aggregation result storage area is a predetermined N bytes, and the numerator is stored in the second aggregation result storage area. The ratio calculation result is calculated using the predetermined N bytes of the second aggregation result as the denominator.
When the calculated ratio calculation result should be subjected to a predetermined correction process (for example, S2071 during the ratio calculation process by the main CPU 101), the ratio calculation result is obtained as the ratio result after the predetermined correction process is performed. Store in storage area,
When the predetermined non-display condition is not satisfied, the ratio display means displays the ratio stored in the ratio result storage area based on the predetermined condition, and the predetermined non-display condition is satisfied. In some cases, the gaming machine is characterized in that the ratio stored in the ratio result storage area is not displayed.

According to the 37th gaming machine of the present invention having the above configuration, desired ratio information can be derived without imposing an excessive load on the main control circuit mounted on the gaming machine, and the ratio is based on an approximate value. Even when calculating information, it is possible to prevent an error from occurring with the true value, reduce the control burden related to the display of the ratio, and reduce the ratio. The life of the displayed device can be extended.

1 ... Pachislot, 3L, 3C, 3R ... Reel, 4 ... Reel display window, 5 ... Lock, 6 ... Information display, 11 ... Display device, 17L, 17C, 17R ... Stop button, 18 ... Sub display device, 71 ... Main control board, 72 ... Sub control board, 90 ... Main control circuit, 91 ... Microprocessor, 95 ... Role ratio monitor, 101 ... Main CPU, 102 ... Main ROM, 103 ... Main RAM, 107 ... Arithmetic circuit, 114 ... No. 1 serial communication circuit, 115 ... second serial communication circuit, 200 ... sub control circuit, 201 ... sub CPU 201, 301 ... first interface board, 302 ... second interface board

Claims (1)

Control means to control the game operation and
A first storage means in which a process for executing control by the control means is stored, and
A second storage means for storing information for the control means to execute control is provided.
The control means
A general-purpose register that stores data when arithmetic processing is executed,
A 1-byte extension register that specifies a part of the memory space address that can be specified by the data stored at the time of execution of the arithmetic processing, and
Has an internal lottery means to determine the internal winning combination,
The first storage means includes a game storage area in which a program for controlling the progress of the game is stored, and a non-game storage area in which a program other than the program for controlling the progress of the game is stored. ,
The second storage means includes a game work area for the program stored in the game storage area to work, and a non-game work area for the program stored in the non-game storage area to work. ,
A set value storage area for storing a set value for adjusting the expected value of the winning of the internal winning combination is provided in the second storage means.
The control means can execute a plurality of types of instructions that specify the value of the upper 1-byte value of the 2-byte address of the second storage means by using the extension register.
In the lottery process, the internal lottery means executes an addition instruction to add the set value storage area using the expansion register when a combination having a different lottery probability differs depending on the set value is executed to obtain determination data. A gaming machine that is calculated and obtains a lottery value for drawing the internal winning combination based on the calculated determination data.

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