JP2021045585A - Game machine - Google Patents

Abstract

To provide a game machine capable of increasing the free capacity of a ROM of a main control circuit, and enhancing game properties by using a free area of the ROM corresponding to the increased capacity.SOLUTION: Processing for executing port output of on-data or off-data, processing for outputting on-data on a stop enabling signal when rotation of patterns reaches a constant speed, and processing for outputting off-data on the stop enabling signal when a stop operation is detected after the on-data is output are stored in an out-of-prescription storage area of a Pachinko slot machine. In the on-data and off-data output processing, port output processing is called after all values of a plurality of general purpose registers are saved, and then the values of all registers are restored to the plurality of general purpose registers. In the Pachinko slot machine, a performance stage is changed at the time of recovery from the power interruption. The performance stage is changed so that a mode coincides with the performance stage at the time of transition to an ending mode.SELECTED DRAWING: Figure 138

Description

The present invention relates to a gaming machine such as a pachislot machine.

Conventionally, when a game medium such as a medal or a coin is inserted (hereinafter referred to as "insertion operation") by a player and the start lever is operated (hereinafter referred to as "start operation"), a plurality of symbols are respectively inserted. When the rotation of the plurality of reels arranged on the surface of the is started and the stop button is operated (hereinafter referred to as "stop operation"), the rotation of the plurality of reels is stopped, and the combination of the symbols displayed as a result is obtained. There is known a game machine called a so-called pachislot machine, which is given a privilege according to the number of reels.

In such a game machine, when the start operation is detected by the start switch, a random number value is extracted and a lottery is performed (hereinafter, the result of this lottery is referred to as an "internal winning combination"), and the stepping motor is driven and controlled. When the stop operation is detected by the stop switch, the stepping motor is driven and controlled to stop the rotation of the plurality of reels based on the internal winning combination.

Conventionally, in the game machine having the above-described configuration, the stop control of the variable display of the reel symbol is performed based on the internal winning combination and the stop operation of the player, the winning judgment is made by the combination of the symbols, and the hopper is determined based on the result of the winning judgment. A gaming machine that controls (medal payout device) to control medal payout is known (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2008-119498

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve such a problem, and an object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the free space of the ROM of the main control circuit. It is an object of the present invention to provide a gaming machine capable of enhancing the game playability by increasing the number of free areas of the ROM corresponding to the increased capacity.

The gaming machine according to the present invention includes a start operation detecting means for detecting a start operation by a player and a plurality of display columns, and is provided in each display column based on the detection of the start operation by the start operation detecting means. A symbol rotating means for rotating a symbol, a stop operation detecting means for detecting a stop operation by a player, and a stop control means for stopping the rotation of the symbol based on the detection of the stop operation by the stop operation detecting means. An arithmetic processing means that performs arithmetic processing for controlling a game operation, a first storage means that stores information necessary for executing the arithmetic processing by the arithmetic processing means, and execution of the arithmetic processing by the arithmetic processing means. The arithmetic processing means includes a second storage means for storing information necessary for the operation, and the arithmetic processing means includes a plurality of general-purpose registers in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and the arithmetic processing means. Data is stored at the time of executing the arithmetic processing, and the stored data has an expansion register capable of designating a part of the address in the second storage means, and the first storage means is at least playable. The second storage means has a game storage area in which programs and data related to the game are stored, and an out-of-specification storage area in which programs and data that are not directly related to the game playability of the game are stored. The game storage area has a game storage area used by the program stored in the game storage area and a non-standard storage area used by the program stored in the non-standard storage area, and the game storage area has a predetermined value. A constant-speed rotation determining means for determining whether or not the rotation of the symbol in the display column has reached a predetermined constant speed is stored, and a port output for on-data or off-data port output is stored in the non-specified storage area. Processing, on-data output processing for outputting on-data of a stoptable signal from the port output processing when the constant-speed rotation determining means determines that the rotation of the symbol has reached the predetermined constant speed. After the on-data output process outputs on-data, the off-data output process that outputs off-data of a stoptable signal from the port output process based on the detection of the stop operation by the stop operation detection means, and the off-data output process. Is stored, and in the on-data output process and the off-data output process executed by the arithmetic processing means, the port output process is called after saving the values of all the registers of the plurality of general-purpose registers. After that, after restoring the values of all the saved registers to the plurality of general-purpose registers. Further, the effect means for shifting to the program stored in the game storage area and performing the effect using the effect stage, and the power-on detection means for detecting the power-on, the effect means. , The production stage can be shifted to another production stage according to the progress of the game, and the production stage before the power is turned off is transferred to another production stage according to the power-on detection means detecting the power-on. It is possible, and the production stage has a specific production stage and a first production stage and a second production stage different from the specific production stage, and the specific production stage is the first production stage. It is an effect stage capable of shifting from the effect stage to the second effect stage, and the effect means is from the first effect stage to the specific effect stage via the second effect stage. When it is decided to shift and a power failure occurs in the second production stage that has shifted from the first production stage, the power-on detecting means detects the power-on. The second production stage is shifted to the first production stage accordingly, but after that, it is possible to shift from the first production stage to the specific production stage without going through the second production stage. It is characterized by.

According to the present invention, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free space of the ROM of the main control circuit, and the free area of the ROM corresponding to the increased capacity is used for playability. Can be enhanced.

It is a figure for demonstrating the functional flow of the game machine in one Embodiment of this invention. It is a perspective view which shows the appearance structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the schematic structure of the various display screens displayed on the sub-display device of one Embodiment of this invention. It is a figure which shows the transition example of the display screen of the sub-display device in one Embodiment of this invention. It is a block diagram which shows the whole structure of the circuit provided in the gaming machine of one Embodiment of this invention. It is a block diagram which shows the internal structure of the main control circuit in one Embodiment of this invention. It is a block diagram which shows the internal structure of the microprocessor in one Embodiment of this invention. It is a block diagram which shows the internal structure of the sub-control circuit in one Embodiment of this invention. It is a block diagram of various registers which a main CPU has in one Embodiment of this invention. It is a figure which shows the memory map of the main control circuit in one Embodiment of this invention. It is a figure which shows the transition flow of the gaming state between the bonus state and the non-bonus state of pachislot in one Embodiment of this invention. It is a figure which shows the transition flow of the gaming state between the ART gaming state, the non-ART gaming state, and the bonus state of pachislot in one Embodiment of this invention. It is a figure which shows an example of the symbol arrangement table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination determination table in one Embodiment of this invention. It is a figure which shows the correspondence relationship between the internal winning combination and the stop symbol combination in one Embodiment of this invention. It is a figure which shows the correspondence relationship between the internal winning combination and the stop symbol combination in one Embodiment of this invention. It is a figure which shows an example of the reel stop initial setting table in one Embodiment of this invention. It is a figure which shows an example of the pull-in priority table in one Embodiment of this invention. It is a figure which shows the structure (the 1) of the hit request flag storage area and the winning operation flag storage area in one Embodiment of this invention. It is a figure which shows the structure (the 2) of the hit request flag storage area and the winning operation flag storage area in one Embodiment of this invention. It is a figure which shows (the 3) of the hit request flag storage area and the winning operation flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the carry-over combination storage area in one Embodiment of this invention. It is a figure which shows the structure of the game state flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the operation stop button storage area in one Embodiment of this invention. It is a figure which shows the structure of the pressing order storage area in one Embodiment of this invention. It is a figure which shows the structure of the symbol code storage area in one Embodiment of this invention. It is a figure which shows the correspondence table (the 1) of the internal winning combination and a sub-flag in one Embodiment of this invention. It is a figure which shows the correspondence table (the 2) of the internal winning combination and a sub-flag in one Embodiment of this invention. It is a figure for demonstrating the notification operation at the time of winning subflag EX "triple chili lip" or "reach eye lip" in the gaming machine of one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the general game state in one Embodiment of this invention. It is a figure which shows an example of the ordinary medium-high probability lottery table in one Embodiment of this invention. It is a figure which shows an example of the CZ lottery table in one Embodiment of this invention. It is a figure which shows an example of the mode-up lottery table in CZ1 in one Embodiment of this invention. It is a figure which shows an example of the point lottery table in CZ2 in one Embodiment of this invention. It is a figure which shows an example of ART lottery table (for CZ1, CZ2) in CZ in one Embodiment of this invention. It is a figure which shows an example of ART lottery table (for CZ3) in CZ in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in a normal ART in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table in ART in one Embodiment of this invention. It is a figure which shows an example of the ART level determination table in one Embodiment of this invention. It is a figure which shows an example of the normal ART medium-high probability lottery table in one Embodiment of this invention. It is a figure which shows an example of the CT lottery table in ART in one Embodiment of this invention. It is a figure which shows an example of the addition lottery table in ordinary ART in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the CT state in one Embodiment of this invention. It is a figure which shows an example of the table lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the addition lottery table in CT in one Embodiment of this invention. It is a figure which shows an example of the lottery table which added the number of sets in CT in one Embodiment of this invention. It is a figure for demonstrating the flow of the game in the bonus state in one Embodiment of this invention. It is a figure which shows an example of the bonus type lottery table in one Embodiment of this invention. It is a figure which shows an example of the lottery table which added the number of ART games in the bonus in one Embodiment of this invention. It is a figure which shows an example of the CT lottery table at the end of a bonus in one Embodiment of this invention. It is a figure for demonstrating the flow of the game (other) in a general game state in one Embodiment of this invention. It is a figure which shows an example of the flag conversion lottery table in non-ART in one Embodiment of this invention. It is a figure which shows the correspondence relationship between the main side navigation data and the sub side navigation data in one Embodiment of this invention. It is a flowchart which shows an example of the power-on (reset interrupt) processing executed by the main control circuit of a game machine in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the power-on processing in one Embodiment of this invention. It is a flowchart which shows the example of the game return processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the game return processing in one Embodiment of this invention. It is a flowchart which shows the example of the setting change confirmation processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the setting change confirmation process in one Embodiment of this invention. It is a flowchart which shows the example of the setting change command generation storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the setting change command generation storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the communication data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data pointer update process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the communication data pointer update process in one Embodiment of this invention. It is a flowchart which shows the example of the (external) processing at the time of power failure in one Embodiment of this invention. It is a flowchart which shows the example of the checksum generation process (non-standard) in one Embodiment of this invention. An example of a source program for executing various processes in the flowchart of the checksum generation process according to the embodiment of the present invention, a stack pointer update operation executed in the checksum generation process, and a data read operation to a register. It is a figure which shows the state of. It is a flowchart which shows the example of the sum check process (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the sum check process (non-standard) in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the checksum process in one Embodiment of this invention. It is a flowchart which shows the example of the main processing (main operation processing) executed by the main control circuit of a game machine in one Embodiment of this invention. It is a flowchart which shows the example of the medal acceptance / start check process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the medal acceptance / start check processing in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the medal insertion process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion check process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the medal insertion check process in one Embodiment of this invention. It is a flowchart which shows the example of the error processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the error table which is actually referred to on the source program of error processing in one Embodiment of this invention. It is a flowchart which shows the example of the random number acquisition processing in one Embodiment of this invention. It is a flowchart which shows the example of the internal lottery processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the internal lottery processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the internal lottery table (for general game) which is actually referred to on the source program of the internal lottery processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the lottery value selection table by RT state which is actually referred to on the source program of the internal lottery processing in one Embodiment of this invention. Internal lottery value table selection table, 1-byte internal lottery value table, 2-byte internal lottery value table, 1-byte internal lottery value by setting, which is actually referred to on the source program of the internal lottery processing according to the embodiment of the present invention. It is a figure which shows an example of the structure of the table and the internal lottery value table for each 2-byte setting. It is a flowchart which shows the example of the symbol setting process in one Embodiment of this invention. It is a figure which shows the correspondence between the special prize (bonus) winning number and small winning combination winning number, and internal winning combination in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the symbol setting processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the hit request flag table which is actually referred to on the source program of the symbol setting process in one Embodiment of this invention. It is a flowchart which shows the example of the compressed data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the 2nd interface board control processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the 2nd interface board output processing in one Embodiment of this invention. It is a flowchart which shows the example of the control processing by state in one Embodiment of this invention. It is a flowchart which shows the example of the sub-flag conversion process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the sub-flag conversion processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the sub-flag conversion table which is actually referred to on the source program of the sub-flag conversion process in one Embodiment of this invention. It is a flowchart which shows the example of the navigation set processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of navigation set processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the navigation data table which is actually referred to on the source program of the navigation set processing in one Embodiment of this invention. It is a flowchart which shows the example of the flag conversion process in one Embodiment of this invention. It is a flowchart which shows the example of the normal middle start processing in one Embodiment of this invention. It is a flowchart which shows the example of the process at the start in CZ in one Embodiment of this invention. It is a flowchart which shows the example of the processing in CZ1 (CZ2) in one Embodiment of this invention. It is a flowchart which shows the example of the processing in CZ1 (CZ2) in one Embodiment of this invention. It is a flowchart which shows the example of the processing in CZ3 in one Embodiment of this invention. It is a flowchart which shows the example of the processing at the time of a start in a normal ART in one Embodiment of this invention. It is a flowchart which shows the example of the start processing during CT in one Embodiment of this invention. It is a flowchart which shows the example of CT lottery processing in CT in one Embodiment of this invention. It is a flowchart which shows the example of the table data acquisition processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the table data acquisition processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the CT lottery table in CT which is actually referred to on the source program of the table data acquisition processing in one Embodiment of this invention. It is a flowchart which shows the example of 1 byte lottery processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of 1-byte lottery processing in one Embodiment of this invention. It is a flowchart which shows the example of the process at the start in BB in one Embodiment of this invention. It is a flowchart which shows the example of the pull-in priority order storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the pull-in priority order storage process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol code acquisition processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the symbol code acquisition process in one Embodiment of this invention. On the source program of the symbol code acquisition process in one embodiment of the present invention, the first cylinder (left reel) symbol arrangement table actually referred to and the symbol correspondence referred to when the first cylinder symbol arrangement table is set. It is a figure which shows an example of the structure of the winning operation table. On the source program of the symbol code acquisition process in one embodiment of the present invention, the second cylinder (middle reel) symbol arrangement table actually referred to and the symbol correspondence referred to when the second cylinder symbol arrangement table is set. It is a figure which shows an example of the structure of the winning operation table. On the source program of the symbol code acquisition process in one embodiment of the present invention, the third cylinder (right reel) symbol arrangement table actually referred to and the symbol correspondence referred to when the third cylinder symbol arrangement table is set. It is a figure which shows an example of the structure of the winning operation table. It is a flowchart which shows the example of the logical product operation processing in one Embodiment of this invention. It is a flowchart which shows the example of the pull-in priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the pull-in priority order acquisition process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the pull-in priority order acquisition process in one Embodiment of this invention. It is a figure which shows an example of the structure of the pull-in priority order table which is actually referred to on the source program of the pull-in priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop control processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the reel stop control processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the reel stop control processing in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop possible signal OFF processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop possible signal ON processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the non-standard port output processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the non-standard port output processing in one Embodiment of this invention. It is a flowchart which shows the example of the winning search process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the prize search process in one Embodiment of this invention. It is a figure which shows an example of the structure of the payout number data table which is actually referred to on the source program of the prize search process in one Embodiment of this invention. It is a flowchart which shows the example of the illegal hit check process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of the illegal hit check processing in one Embodiment of this invention. It is a flowchart which shows the example of the winning check, medal payout processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the prize check / medal payout process in one Embodiment of this invention. It is a flowchart which shows the example of the medal payout number check process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the medal payout number check process in one Embodiment of this invention. It is a flowchart which shows the example of the BB check process in one Embodiment of this invention. It is a flowchart which shows the example of RT check processing in one Embodiment of this invention. It is a flowchart which shows the example of RT check processing in one Embodiment of this invention. It is a flowchart which shows the example of the CZ / ART end processing in one Embodiment of this invention. It is a flowchart which shows the example of the interrupt process executed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the 7-segment LED drive processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of 7-segment LED drive processing in one Embodiment of this invention. It is a flowchart which shows the example of the 7-segment display data generation processing in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processing in the flowchart of 7-segment display data generation processing in one Embodiment of this invention. It is a figure which shows an example of the structure of the 7-segment cathode table which is actually referred to on the source program of the 7-segment display data generation processing in one Embodiment of this invention. It is a flowchart which shows the example of the timer update process in one Embodiment of this invention. It is a figure which shows an example of the source program for executing various processes in the flowchart of the timer update process in one Embodiment of this invention. It is a flowchart which shows the example of the test firing test signal control processing (non-standard) in one Embodiment of this invention. It is a flowchart which shows the example of the rotation cylinder braking signal generation processing in one Embodiment of this invention. It is a flowchart which shows the example of the prize signal control processing in one Embodiment of this invention. It is a flowchart which shows the example of the condition device signal control processing in one Embodiment of this invention. It is a flowchart which shows the example of the condition device signal control processing in one Embodiment of this invention. It is a flowchart which shows the example of the sub-side navigation control processing executed by the sub-control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the player registration process in one Embodiment of this invention. It is a flowchart which shows the example of the history management processing in one Embodiment of this invention. It is a figure which shows the flow of the game in the CT omen in the modification 1 of this invention. It is a figure which shows the correspondence relationship between the internal winning combination and the stop symbol combination in the modification 2 of this invention. It is a figure which shows the correspondence relationship between the main side navigation data and the sub side navigation data in the modification 3 of this invention. It is a figure which shows the correspondence relationship between the pushing order and the locked state in the modification 5 of this invention. It is a figure which shows the transition flow of the gaming state between the bonus state and the non-bonus state of the pachislot in another embodiment of this invention. It is a figure which shows an example of the symbol arrangement table in the said embodiment. It is a figure which shows an example of the internal lottery table in the said embodiment. It is a figure which shows an example of the internal lottery table in the said embodiment. It is a figure which shows an example of the symbol combination determination table in the said embodiment. It is a figure which shows an example of the symbol combination determination table in the said embodiment. It is a figure which shows an example of the symbol combination determination table in the said embodiment. It is a figure which shows an example of the symbol combination determination table in the said embodiment. It is a figure which shows an example of the symbol combination determination table in the said embodiment. It is a figure which shows an example of the symbol combination determination table in the said embodiment. It is a figure which shows an example of the symbol combination determination table in the said embodiment. It is a figure which shows an example of the symbol combination determination table in the said embodiment. It is a figure which shows an example of the symbol combination determination table in the said embodiment. It is a figure which shows an example of the symbol combination determination table in the said embodiment. It is a figure which shows an example of the symbol combination determination table in the said embodiment. It is a figure which shows an example of the symbol combination determination table in the said embodiment. It is a figure which shows the correspondence relationship between the internal winning combination and the stop symbol combination in the said embodiment. It is a figure which shows an example of the content of the symbol combination in the said embodiment. It is a figure which shows an example of the content of the symbol combination in the said embodiment. It is a figure which shows an example of the content of the symbol combination in the said embodiment. It is a figure which shows an example of the content of the symbol combination in the said embodiment. It is a figure which shows an example of the content of the symbol combination in the said embodiment. It is a figure which shows an example of the content of the symbol combination in the said embodiment. It is a figure which shows an example of the content of the symbol combination in the said embodiment. It is a figure which shows the transition flow of the gaming state between the ART gaming state, the non-ART gaming state, and the bonus state of the pachislot in the said embodiment. It is a correspondence table about the abbreviation of the internal winning combination in the said embodiment. It is a figure which shows the flow of the game in the normal game state in the said embodiment. It is a figure which shows the flow of the game in the normal game state in the said embodiment. It is a figure which shows an example of the ART lottery table at the start of a cycle in the said embodiment. It is a figure which shows an example of the periodic MAP lottery table in the said embodiment. It is a figure which shows an example of the game number lottery table in the said embodiment. It is a figure which shows an example of the ART lottery table during a cycle and ART preparation in the said embodiment. It is a figure which shows an example of the MAP transition lottery table in the said embodiment. It is a figure which shows an example of the MAP transition lottery table in the said embodiment. It is a figure which shows an example of the MAP transition lottery table in the said embodiment. It is a figure which shows an example of the MAP transition lottery table in the said embodiment. It is a figure which shows an example of the MAP transition lottery table in the said embodiment. It is a figure which shows an example of the MAP transition lottery table in the said embodiment. It is a figure which shows an example of the MAP transition lottery table in the said embodiment. It is a figure which shows an example of the MAP transition lottery table in the said embodiment. It is a figure which shows an example of the mode transition game number lottery table in the said embodiment. It is a figure which shows the transition example of the periodic MAP in the said embodiment. It is a figure which shows the transition example of the periodic MAP in the said embodiment. It is a figure which shows the mode transition example at the time of the periodic MAP transition in the said embodiment. It is a figure which shows the flow of the game in the bonus state in the said embodiment. It is a figure which shows an example of the ART lottery table at the end of BB in the said embodiment. It is a figure which shows an example of the loop mode lottery table in the said embodiment. It is a figure which shows the flow of the game in the ART game state in the said embodiment. It is a figure which shows an example of the high-accuracy map lottery table in the said embodiment. It is a figure which shows an example of the continuous lottery table in the said embodiment. It is a figure which shows an example of the EP point lottery table in the said embodiment. It is a figure which shows an example of the ART game number lottery table in the said embodiment. It is a figure which shows an example of the ART lottery table in the normal ART and the episode ART in the said embodiment, and the addition lottery table at the time of the addition winning. It is a flowchart which shows the example of the main processing (main operation processing) executed by the main control circuit of pachislot in the said embodiment. It is a flowchart which shows the example of the control process by state in the said Embodiment. It is a flowchart which shows the example of the normal middle start processing in the said embodiment. It is a flowchart which shows the example of the normal ART lottery processing in the said embodiment. It is a flowchart which shows the example of the MAP transition process in the said Embodiment. It is a flowchart which shows the example of the mode transition process in the said Embodiment. It is a flowchart which shows the example of the start processing during ART in the said embodiment. It is a flowchart which shows the example of the processing in normal ART in the said embodiment. It is a flowchart which shows the example of the processing in normal ART in the said embodiment. It is a flowchart which shows the example of the processing during episode ART in the said embodiment. It is a flowchart which shows the example of the process at the start of a bonus in the said embodiment. It is a flowchart which shows the example of the BB check process in the said Embodiment. It is a flowchart which shows the example of RT check processing in the said embodiment. It is a figure which shows the timing example of ART start in the said embodiment. It is a figure which shows the output timing example of the external signal at the end of ART in the said embodiment. It is a figure which shows the relationship of the mode of the main side and the sub side at the time of power-on in the said embodiment. It is a figure which shows the relationship of the mode of the main side and the sub side at the time of power-on in the said embodiment. It is a figure which shows the outline of the production during a normal ART in the said embodiment. It is a figure which shows an example of the distribution level lottery table in the said embodiment. It is a figure which shows an example of the winning type lottery table in the said embodiment. It is a figure which shows an example of the progress pattern lottery table in the said embodiment. It is a figure which shows an example of the tile type change lottery table and the like in the said embodiment.

Hereinafter, a pachi-slot machine will be taken as an example of a gaming machine according to an embodiment of the present invention, and its configuration and operation will be described with reference to the drawings. In this embodiment, a pachi-slot machine having a bonus operation function and an ART function will be described.

<Function flow>
First, the functional flow of the pachislot machine will be described with reference to FIG. In the pachislot machine of the present embodiment, a medal is used as a game medium for playing a game. In addition to medals, coins, game balls, game point data, tokens, and the like can also be applied as the game medium.

When a medal is inserted into the pachislot machine by the player and the start lever is operated, one value (hereinafter referred to as a random number value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

The internal lottery means draws a lot based on the extracted random number value, and determines the internal winning combination. This internal lottery means is one of various processing means (processing functions) included in the main control circuit described later. By determining the internal winning combination, the combination of symbols that are allowed to be displayed along the valid line (winning determination line) described later is determined. The types of symbol combinations are those related to "winning" in which benefits such as medal payout, replay operation, bonus operation, etc. are given to the player, and other so-called "missing". Such things are provided. In the following, the role related to the payout of medals will be referred to as a "small role", and the role related to the operation of the replay (replay) will be referred to as a "replay role". In addition, the role related to the operation of the bonus (bonus game) is also referred to as a "bonus role".

Further, when the start lever is operated, a plurality of reels are rotated. After that, when the stop button corresponding to the predetermined reel is pressed by the player, the reel stop control means controls to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do. This reel stop control means is one of various processing means (processing functions) included in the main control circuit described later.

In pachislot, basically, control is performed to stop the rotation of the corresponding reel within a specified time (190 msec) from the time when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within this specified time is referred to as the "number of sliding pieces". Then, in the present embodiment, when the specified period is 190 msec, the maximum number of sliding pieces (maximum number of sliding pieces) is set for four symbols.

When the internal winning combination that allows the combination display of the symbols related to the winning is determined, the reel stop control means usually sets the combination of the symbols to the effective line within the specified time of 190 msec (for 4 symbols). Stop the rotation of the reel so that it is displayed as much as possible along the line. Further, the reel stop control means uses a predetermined time to stop the rotation of the reel so that the combination of symbols whose display is not permitted by the internal winning combination is not displayed along the effective line.

In this way, when all the rotations of the plurality of reels are stopped, the winning determination means determines whether or not the combination of symbols displayed along the effective line is related to winning. This winning determination means is also one of various processing means (processing functions) included in the main control circuit described later. Then, when it is determined by the winning determination means that the combination of the displayed symbols is related to the winning, a privilege such as a medal payout is given to the player. In pachislot, the above series of flows is performed as one game (unit game).

Further, in pachislot, in the flow of the above-mentioned series of game operations, various effects are produced by displaying an image by a display device, outputting light by various lamps, outputting sound by a speaker, or a combination of these. Is done.

Specifically, when the start lever is operated, a random value for production is extracted in addition to the random value used for determining the internal winning combination described above. When the random value for the production is extracted, the production content determining means determines the production to be executed this time from a plurality of types of production contents associated with the internal winning combination by lottery. This effect content determining means is one of various processing means (processing functions) provided in the sub-control circuit described later.

Next, when the effect content is determined by the effect content determining means, the effect execution means responds in conjunction with each opportunity such as when the reel starts rotating, when each reel stops rotating, and when it is determined whether or not there is a prize. To execute. In this way, in pachislot, for example, by executing the production content associated with the internal winning combination, the opportunity to know or anticipate the determined internal winning combination (in other words, the combination of symbols to be aimed at) is a game. It is provided to the player and can improve the interest of the player.

<Structure of pachislot>
Next, the structure of the pachislot machine according to the embodiment of the present invention will be described with reference to FIGS. 2 to 4.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachislot machine 1.

As shown in FIG. 2, the pachislot machine 1 includes an exterior body (game machine main body) 2. The exterior body 2 has a cabinet 2a for accommodating a reel, a circuit board, and the like, and a front door 2b to which an opening of the cabinet 2a can be opened and closed.

Inside the cabinet 2a, three reels 3L, 3C, 3R (variable display means, display row) are provided side by side in a horizontal row. Hereinafter, each reel 3L, 3C, 3R (main reel) is also referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each reel 3L, 3C, 3R has a reel body formed in a cylindrical shape and a translucent sheet material mounted on the peripheral surface of the reel body. A plurality of (for example, 20) symbols are drawn on the surface of the sheet material at predetermined intervals along the circumferential direction (rotation direction of the reel).

The front door 2b includes a door body 9, a front panel 10, a lumbar panel 12, and a pedestal portion 13. The door body 9 is attached to the cabinet 2a so as to be openable and closable by using a hinge (not shown). The hinge is provided at the left side end of the door body 9 when viewed from the front side (player side) of the pachislot machine 1.

The front panel 10 is provided on the upper part of the door body 9. The front panel 10 is composed of a frame-shaped member having an opening 10a. The opening 10a of the front panel 10 is closed by the display device cover 30, and the display device cover 30 is arranged to face the display device 11 which will be described later and is arranged inside the cabinet 2a.

The display device cover 30 is made of a black translucent synthetic resin. Therefore, the player can visually recognize the image (image) displayed by the display device 11 described later through the display device cover 30. Further, in the present embodiment, by forming the display device cover 30 with a black translucent synthetic resin, the entry of external light into the cabinet 2a is suppressed, and the image (image) displayed by the display device 11 is suppressed. Is clearly visible.

A lamp group 21 is provided on the front panel 10. The lamp group 21 includes, for example, the lamps 21a and 21b provided on the upper part of the front panel 10 when viewed from the player side. Each lamp constituting the lamp group 21 is composed of an LED (Light Emitting Diode) or the like (see LED group 85 in FIG. 7 described later), and lights are turned on and off in a pattern corresponding to the effect content.

The waist panel 12 is provided at a substantially central portion of the door body 9. The waist panel 12 has a decorative panel on which an arbitrary image is drawn, and a light source (LED included in the LED group 85 described later) that emits light for illuminating the decorative panel from the back side.

The pedestal portion 13 is provided between the front panel 10 and the lumbar panel 12. The pedestal portion 13 has a symbol display area 4, various devices to be operated by the player (medal insertion slot 14, MAX bet button 15a, 1 bet button 15b, start lever 16, 3 stop buttons 17L, 17C, 17R, settlement button (not shown), etc.) are provided.

The symbol display area 4 is an area that overlaps the three reels 3L, 3C, 3R when viewed from the front, and is arranged at a position on the player side of the three reels 3L, 3C, 3R, and the three reels. It has a size that makes 3L, 3C, and 3R visible. The symbol display area 4 functions as a display window, and has a configuration in which the reels 3L, 3C, and 3R provided behind the symbol display area 4 can be visually recognized. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

The reel display window 4 is arranged continuously among a plurality of symbols provided on the peripheral surface of each reel when the rotation of the three reels 3L, 3C, 3R provided behind the reel display window 4 is stopped. It is configured so that one symbol is displayed in the frame. That is, when the rotation of the three reels 3L, 3C, and 3R is stopped, one symbol is set in each of the upper, middle, and lower regions for each reel in the frame of the reel display window 4 (three in total). ) Is displayed (in the frame of the reel display window 4, the design is displayed in the form of 3 rows × 3 columns). Then, in the present embodiment, in the frame of the reel display window 4, a pseudo line (center line) connecting the middle stage region of the left reel 3L, the middle stage region of the middle reel 3C, and the middle stage region of the right reel 3R is formed. It is defined as an effective line for determining whether or not a prize has been won.

The reel display window 4 is formed by the opening of the frame member 31 provided in the pedestal portion 13. Further, a pedestal region having a substantially horizontal plane is provided below the frame member 31 that defines the reel display window 4. When viewed from the player side, the medal insertion slot 14 is provided on the right side of the pedestal area, and the MAX bet button 15a and the 1-bet button 15b are provided on the left side.

The medal slot 14 is provided to receive medals dropped on the pachislot machine 1 from the outside by the player. The medals received from the medal slot 14 are used in one game up to a preset predetermined number (for example, 3), and the number of medals exceeding the predetermined number is deposited inside the pachislot machine 1. (So-called credit function (game medium storage means)).

The MAX bet button 15a and the 1-bet button 15b are provided to determine the number of medals to be used for one game from the medals deposited inside the cabinet 2a. Inside the MAX bet button 15a, a bet button LED (not shown) that lights up when a medal can be inserted is provided. In addition, the settlement button is provided to pull out (discharge) the medals deposited inside the pachislot machine 1 to the outside.

When the player presses the MAX bet button 15a, medals for the number of bets (3) in the unit game are inserted and the effective line is activated. On the other hand, one medal is inserted each time the 1-bet button 15b is pressed once. When the 1-bet button 15b is operated three times, medals for the number of bets (3) in the unit game are inserted and the effective line is activated.

In the following, the operation of the MAX bet button 15a, the operation of the 1-bet button 15b, and the operation of inserting medals into the medal insertion slot 14 (operations of inserting medals to perform a game) are all referred to as "insertion operations".

The start lever 16 is provided to start the rotation of all reels (3L, 3C, 3R). The stop buttons 17L, 17C, and 17R are provided corresponding to the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, and 17R are also referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R, respectively.

Further, an information display 6 is provided at substantially the center of the pedestal region on the substantially horizontal plane below the reel display window 4. The information display 6 is covered with a transparent window cover (not shown).

The information display 6 is a 2-digit 7-segment LED for digitally displaying (notifying) information on the number of medals to be paid out to the player (hereinafter referred to as "the number of medals to be paid out") as a privilege. For digitally displaying (notifying) information such as (hereinafter referred to as "7-segment LED") and the number of medals deposited inside the pachislot 1 (hereinafter referred to as "credit number") to the player. A 2-digit 7-segment LED is provided. In the present embodiment, the 2-digit 7-segment LED for displaying the number of medals to be paid out is a 2-digit 7-segment LED for digitally displaying (notifying) information on the occurrence of an error and the error type to the player. Is also used. Therefore, when an error occurs, the display mode of the 2-digit 7-segment LED for displaying the number of medals to be paid out is switched from the display mode of the number of medals to be paid out to the display mode of the error type information.

Further, the information display 6 is provided with an instruction monitor (not shown) for notifying information on the stop operation necessary for displaying the symbol combination according to the winning combination determined as the internal winning combination along the effective line. ing. The instruction monitor (instruction display) is composed of, for example, a 2-digit 7-segment LED. Then, the instruction monitor notifies the player of the necessary stop operation information by turning on, blinking, or turning off the two-digit 7-segment LED in a manner that uniquely corresponds to the stop operation information to be notified. To do.

The mode that uniquely corresponds to the information of the stop operation to be notified here is, for example, in the case of notifying the push order "1st (performing the first stop operation on the left reel 3L)". When the numerical value "1" is displayed on the instruction monitor and the push order "2nd (perform the first stop operation on the middle reel 3C)" is displayed, the numerical value "2" is displayed on the instruction monitor and the push order is displayed. When notifying "3rd (performing the first stop operation on the right reel 3R)", the numerical value "3" is displayed on the instruction monitor. The mode of notifying the information of the stop operation on the instruction monitor (navigation data determined on the main side described later) will be described in detail later with reference to FIG. 63 described later.

As shown in FIG. 7 described later, the information display 6 is electrically connected to the main control board 71 via the door relay terminal board 68 and the game operation display board 81, and the display operation of the information display 6 is mainly performed. It is controlled by the main control circuit 90 described later in the control board 71. Further, the control method of the various 7-segment LEDs described above is dynamic lighting control.

In the pachi-slot machine 1 of the present embodiment, in addition to the instruction monitor controlled by the main control board 71, another means controlled by the sub-control board 72 is used to notify the information of the stop operation. Specifically, the information on the stop operation is notified by the display device 11 described later, which is composed of the projector mechanism 211 and the display unit 212 (see FIGS. 3 and 7 described later) described later.

When such a configuration is applied, the mode of notification in the instruction monitor and the mode of notification in other means controlled by the sub-control board 72 may be different from each other. That is, in the instruction monitor, the information of the stop operation to be notified may be notified in a manner uniquely corresponding to the information of the stop operation, and it is not always necessary to directly notify the information of the stop operation (for example, the numerical value "1" in the instruction monitor. Even if is displayed, it may not be possible to specify the content of the notification depending on the player, so it cannot be said to be a direct notification). On the other hand, in the notification on the sub side (sub control board side) by other means such as the display device 11 described later, the information of the stop operation may be directly notified. For example, when the push order "1st" is notified, the instruction monitor displays a numerical value "1" that uniquely corresponds to the push order to be notified, but other means (for example, the display device 11 or the like) display the left reel 3L. The instruction information for performing the first stop operation may be directly notified to the user.

In the pachi-slot machine 1 having such a configuration, it is possible to notify the information of the necessary stop operation according to the internal winning combination not only by the control of the sub control board 72 but also by the control of the main control board 71. Further, the presence / absence of notification of such stop operation information may be controlled according to the gaming state. For example, the stop operation information may be notified in the ART game state (see FIG. 14 described later) without notifying the stop operation information in the general game state (non-ART game state) described later.

Further, a sub display device 18 is provided on the left side of the reel display window 4 when viewed from the player side. As shown in FIG. 2, the sub-display device 18 is provided so as to stand substantially perpendicular to the pedestal region of the pedestal portion 13 in a substantially horizontal plane in the front portion of the door body 9. The sub-display device 18 is composed of a liquid crystal display and an organic EL (Electro-Luminescence) display, and displays various information.

Further, a touch sensor 19 is provided on the display surface of the sub display device 18 (see FIG. 7 described later). The touch sensor 19 operates according to a predetermined operating principle such as a capacitance method, and when it receives an operation of a player, it outputs a signal corresponding to the operation as touch input information. The pachi-slot machine 1 of the present embodiment has a function of enabling the display of the sub-display device 18 to be switched according to the player's operation (touch input information output from the touch sensor 19) received via the touch sensor 19. Has. The sub display device 18 is controlled by the sub control board 72 (see FIG. 7 described later) based on the touch input information output from the touch sensor 19.

At the lower part of the door body 9, a medal payout outlet 24, a medal tray 25, two speaker holes 20L, 20R, and the like are provided. The medal payout outlet 24 guides the medals discharged by driving the medal payout device 51, which will be described later, to the outside. The medal tray 25 stores medals discharged from the medal payout outlet 24. Further, sound effects such as sound effects and music corresponding to the contents of the production are output from the two speaker holes 20L and 20R.

[Internal structure]
Next, the internal structure of the pachislot machine 1 will be described with reference to FIGS. 3 and 4. FIG. 3 is a diagram showing the internal structure of the cabinet 2a, and FIG. 4 is a diagram showing the internal structure of the front door 2b on the back surface side.

As shown in FIG. 3, the cabinet 2a has a top plate 27a, a bottom plate 27b, left and right side plates 27c and 27d, and a back plate 27e. A display device 11 is arranged in the upper part of the cabinet 2a.

The display device 11 has a projector mechanism 211 and a box-shaped projected member 212a on which the image light projected from the projector mechanism 211 is projected, and displays an image by projection mapping. Specifically, the display device 11 generates image light based on the position (projection distance, angle, etc.) and shape of the projected member 212a, which is a three-dimensional object, and the image light is emitted by the projector mechanism 211 to the projected member. It is projected on the surface of 212a. By providing such an effect function, it is possible to perform an advanced and powerful effect. Further, although not shown in FIG. 3, another projected member having a curved display surface is provided on the back side of the box-shaped projected member 212a, and one of the projected members is provided depending on the gaming state. , Used as a screen on which video light is projected. Therefore, the inside of the cabinet 2a is also provided with a function (not shown) for switching the projected member according to the gaming state.

A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are arranged in the lower part of the cabinet 2a.

The hopper device 51 is attached to the central portion of the bottom plate 27b in the cabinet 2a. The hopper device 51 has a structure capable of accommodating a large number of medals and ejecting them one by one. The hopper device 51 pays out medals when the number of stored medals exceeds, for example, 50, or when the settlement button is pressed and the settlement of medals is executed. Then, the medals paid out by the hopper device 51 are discharged from the medal payout outlet 24 (see FIG. 2).

The medal auxiliary storage 52 stores medals overflowing from the hopper device 51. The medal auxiliary storage 52 is arranged on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. Further, the medal auxiliary storage 52 is detachably attached to the bottom plate 27b of the cabinet 2a.

The power supply device 53 includes a power supply switch 53a and a power supply board 53b (power supply means) (see FIG. 7 described later). The power supply device 53 is arranged on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side plate 27c. The power supply device 53 converts the AC voltage 100V power supplied from the sub power supply device (not shown) into the DC voltage power required by each part, and supplies the converted power to each part.

Further, above the power supply device 53 in the cabinet 2a, a sub-control board case 57 for accommodating the sub-control board 72 (see FIG. 7 described later) is arranged. A sub-control circuit 200 (see FIG. 10 to be described later) described later is mounted on the sub-control board 72 housed in the sub-control board case 57. The sub-control circuit 200 is a circuit that controls the execution of an effect by displaying an image or the like. The specific configuration of the sub-control circuit 200 will be described later.

The sub-relay board 61 is arranged above the sub-control board case 57 in the cabinet 2a. The sub-relay board 61 is a relay board on which wiring for connecting the sub-control board 72 and the main control board 71, which will be described later, is mounted. Further, the sub-relay board 61 is a relay board on which wiring for connecting the sub-control board 72 and the boards arranged around the sub-control board 72, various device units (units), and the like is mounted.

Further, although not shown in FIG. 3, a cabinet-side relay board 44 (see FIG. 7 described later) is arranged in the cabinet 2a. The cabinet-side relay board 44 includes a main control board 71 (see FIG. 7 described later), a hopper device 51, a game medal auxiliary storage switch 77 (see FIG. 7 described later), and a medal payout count switch (not shown). It is a relay board on which wiring for connecting to and is mounted.

As shown in FIG. 4, a middle door 41 is arranged at the center of the front door 2b on the back surface side, and a reel display window 4 (see FIG. 2) is attached so as to be openable and closable from the back side. Although not shown in FIG. 4, three reels 3L, 3C, and 3R are attached to the reel display window 4 side of the middle door 41, and the main control is on the side opposite to the reel display window 4 side of the middle door 41. A main control board case 55 in which the board 71 (see FIG. 7 described later) is housed is attached. A stepping motor (not shown) is connected to the three reels 3L, 3C, and 3R via gears having a predetermined reduction ratio.

The main control board 71 housed in the main control board case 55 has a main control circuit 90 (see FIG. 9 described later) described later. The main control circuit 90 (main control means) is a circuit that controls the main flow of the game in the pachislot machine 1, such as determining the internal winning combination, rotating and stopping the reels 3L, 3C, and 3R, and determining whether or not there is a prize. .. Further, in the present embodiment, for example, the main control circuit 90 also controls the lottery process of whether or not the ART is determined, the display process of the navigation information on the instruction monitor, the transmission process of various test signals, and the like. The specific configuration of the main control circuit 90 will be described later.

Speakers 65L and 65R are arranged below the middle door 41 on the back surface side of the front door 2b. The speakers 65L and 65R are arranged at positions facing the speaker holes 20L and 20R (see FIG. 2), respectively.

A selector 66 and a door open / close monitoring switch 67 are arranged above the speaker 65L. The selector 66 is a device for selecting whether or not the material and shape of the medal are appropriate, and guides the appropriate medal inserted into the medal insertion slot 14 to the hopper device 51. A medal sensor (game medium detecting means: not shown) for detecting that a proper medal has passed is provided on the path through which the medal passes in the selector 66.

The door open / close monitoring switch 67 is arranged diagonally to the lower left of the selector 66 when the front door 2b is viewed from the back surface side. The door open / close monitoring switch 67 outputs a security signal for notifying the open / close of the front door 2b to the outside of the pachislot machine 1.

Further, although not shown in FIG. 4, a door relay terminal plate 68 is arranged on the back surface of the front door 2b, which is a region opened and closed by the middle door 41 and below the reel display window 4 (FIG. 4 described later). 7). The door relay terminal board 68 includes a main control board 71 in the main control board case 55, various buttons and switches, a sub relay board 61, a selector 66, a game operation display board 81, a first interface board 301 for a testing machine, and the like. This is a relay board on which wiring for connecting each of the second interface boards 302 for a testing machine is mounted. Examples of the various buttons and switches include the MAX bet button 15a, the 1-bet button 15b, the door open / close monitoring switch 67, the BET switch 77 described later, the start switch 79, and the like.

<Display example of sub display device>
Here, various display screens displayed on the sub-display device 18 will be described with reference to FIGS. 5A to 5E. 5A is a diagram showing a top screen 221 displayed on the sub display device 18, and FIG. 5B is a diagram showing a menu screen 222 displayed on the sub display device 18. 5C to 5E are diagrams showing game information screens 223, 224, and 225 displayed on the sub display device 18.

Various display screens are displayed on the sub-display device 18 by a player's touch operation, and as shown in FIGS. 5A to 5E, various display screens including a top screen 221 and a menu screen 222 and a game information screen 223, 224, 225 are included. The display screen is displayed. These display screens are switched based on the player's operation signal received via the touch sensor 19.

The top screen 221 is an initial screen of the display screens displayed on the sub display device 18, and the top screen 221 displays the “MENU” button 221a and the outline game history 221b. The "MENU" button 221a is an operation button for calling the menu screen 222 shown in FIG. 5B, and when a predetermined operation (for example, tap) by the player is performed on the "MENU" button 221a, the menu screen 222 is called. Is done. Further, on the top screen 221, a part of the game history (summary game history) of the pachislot machine 1 is displayed as the summary game history 221b. In the present embodiment, for example, the number of bonuses, the number of ARTs, and the number of games (number of games) are displayed as the outline game history 221b.

The menu screen 222 is a screen for displaying a menu that can be displayed on the sub display device 18, and on the menu screen 222, a “back” button 222a, a “registration” button 222b, an “explanation” button 222c, and an “array dividend” button 222d , The "reach eye" button 222e, the "WEB site" button 222f, and the "volume" button 222g are displayed. The "back" button 222a is an operation button for calling the top screen 221. When the player operates the "back" button 222a, the top screen 221 is called. Further, the "registration" button 222b to the "volume" button 222g are operation buttons for calling the display screen of the corresponding menu content, and when the player operates each button, the corresponding menu content is displayed. The display screen is called.

For example, when the "register" button 222b is operated by the player on the menu screen 222, a registration screen (not shown) for registering the player during the game is called on the display screen of the sub display device 18. In recent pachislot machines, a service is widely provided in which a player is registered for each model and various information such as the achievement status of a predetermined mission is managed from the past game history of the player. The registration screen called by the "registration" button 222b is a display screen for registering a player when receiving the provision of this service.

Further, for example, when the "explanation" button 222c is operated by the player on the menu screen 222, the explanation screen (not shown) of the pachislot machine 1 is called to the display screen of the sub display device 18. The information displayed on the explanation screen includes, for example, an explanation about the specifications of the pachislot machine 1 such as a bonus winning probability and an ART winning probability for each set value, and an introduction explanation of a character appearing in the production of the pachislot machine 1.

Further, for example, when the “array payout” button 222d is operated by the player on the menu screen 222, the array payout screen (not shown) of the pachislot machine 1 is called on the display screen of the sub display device 18. On the array payout screen, for example, the correspondence between the combination of symbols judged to be winning in Pachislot 1 and the privilege when it is judged to be winning (dividend table) and drawn on each reel 3L, 3C, 3R. The symbol sequence (reel arrangement) and the like are displayed.

Further, for example, when the "reach eye" button 222e is operated by the player on the menu screen 222, the reach eye screen (not shown) of the pachislot machine 1 is called on the display screen of the sub display device 18. On the reach-eye screen, information on a symbol combination called "reach-eye" set in the pachi-slot machine 1 is displayed. The symbol combination referred to as "reach eyes" is a symbol combination to which a special privilege is given by displaying the symbol combination along the effective line. In the pachislot machine 1 of the present embodiment, the figure described later The symbol combination corresponding to the abbreviation "reach eye lip" shown in the content column of the winning operation flag storage area of FIGS. 28 to 30 is applicable. Then, in the present embodiment, when the symbol combination related to the "reach eye lip" is displayed along the effective line, a state advantageous to the player (for example, a bonus state, a normal ART or CT (FIG. 14 described later)) is thereafter. It is confirmed that the transition to)) will be made.

Further, for example, when the "WEB site" button 222f is operated by the player on the menu screen 222, the WEB introduction screen (not shown) of the pachislot machine 1 is called on the display screen of the sub display device 18. On the WEB introduction screen, for example, a two-dimensional code (for example, QR code (registered trademark)) indicating the URL of an arbitrary WEB site such as a special WEB site provided for each model of pachislot 1 or a WEB site of a pachislot 1 manufacturer). Is displayed. The player can access the corresponding WEB site by reading the two-dimensional code displayed on the WEB introduction screen with a mobile phone or the like.

Further, for example, when the "volume" button 222g is operated by the player on the menu screen 222, a volume adjustment screen (not shown) capable of adjusting the volume of the sound output from the speakers 65L and 65R is a sub display device. Called to the display screen of 18. The player can adjust the volume of the effect sound of the pachi-slot machine 1 via the volume adjustment screen.

Since the sub-display device 18 is provided separately from the above-mentioned display device 11 (projector mechanism 211 and display unit 212), it can be controlled separately from the display device 11. Therefore, in the pachi-slot machine 1 of the present embodiment, the display screen of the sub-display device 18 can be switched by the operation of the player even during the game (during the execution of the effect by the display device 11). As a result, for example, when the player wants to know the character appearing in the production of the display device 11, the player operates the "explanation" button 222c to call the explanation screen, and the inter-characters. Information such as the relationship between the two can be grasped during the game. Also, for example, when the player wants to grasp the symbol that should be used as a guide for winning the rare role during the reel rotation when the so-called "rare role" is won during the game, the player may ask. By operating the "arrangement payout" button 222d to call the arrangement payout screen, the reel arrangement can be grasped.

The game information screens 223, 224, and 225 are display screens that display detailed game history information including an outline game history to be displayed on the top screen 221 of the game history of the pachislot machine 1.

On the game information screen 223, a "back" button 223a, a "MENU" button 223b, a "previous" button 223c, a "next" button 223d, and a game history 223e are displayed. The "back" button 223a and the "MENU" button 223b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively, and are supported by the player operating each button. The display screen is called. Further, the "previous" button 223c and the "next" button 223d are operation buttons for switching the game information screen in a predetermined order, and when the "previous" button 223c is operated by the player, the display screen is displayed. Is switched from the game information screen 223 to the game information screen 225, and when the "Next" button 223d is operated by the player, the display screen is switched from the game information screen 223 to the game information screen 224. Further, as the game history 223e, as shown in FIG. 5C, the number of games (number of games), the number of bonuses, the number of ARTs, and the number of CZs (chance zones) are displayed.

On the game information screen 224, a "back" button 224a, a "MENU" button 224b, a "previous" button 224c, a "next" button 224d, and a game history 214e are displayed. The "back" button 224a and the "MENU" button 224b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively, and are supported by the player operating each button. The display screen is called. Further, the "previous" button 224c and the "next" button 224d are operation buttons for switching the game information screen in a predetermined order, and when the "previous" button 224c is operated by the player, the display screen is displayed for the game. When the information screen 224 is switched to the game information screen 223 and the "Next" button 224d is operated by the player, the display screen is switched from the game information screen 224 to the game information screen 225. Further, as the game history 224e, the number of times of entry and the number of successes of CZ (chance zone) described later are displayed. As will be described later, in the present embodiment, three types of CZs, CZ1, CZ2, and CZ3, are provided as CZs. Therefore, as the game history 224e, as shown in FIG. 5D, the number of rushes and the number of successes of each of CZ1 to CZ3 are displayed.

On the game information screen 225, a "back" button 225a, a "MENU" button 225b, a "previous" button 225c, a "next" button 225d, and a game history 225e are displayed. The "back" button 225a and the "MENU" button 225b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively, and are supported by the player operating each button. The display screen is called. Further, the "previous" button 225c and the "next" button 225d are operation buttons for switching the game information screens in a predetermined order, and when the "previous" button 225c is operated by the player, the display screen is displayed. Is switched from the game information screen 225 to the game information screen 224, and when the "Next" button 225d is operated by the player, the display screen is switched from the game information screen 225 to the game information screen 223. Further, as the game history 225e, as shown in FIG. 5E, the number of winnings of the small winning combination and the winning probability (fraction of the numerator of 1) are displayed.

As a display screen switching method displayed on the sub-display device 18, for example, a method of switching based on a tap operation on an operation button displayed on each display screen may be adopted, or, for example, A method of switching based on a swipe operation on the display screen may be adopted.

<Various switching functions of the display screen of the sub display device>
Next, various switching functions of the display screen of the sub-display device 18 in the pachi-slot machine 1 of the present embodiment will be described.

[Example of transition of display screen of sub display device]
First, a transition example (switching mode) of the display screen of the sub-display device 18 in the pachi-slot machine 1 of the present embodiment will be described with reference to FIGS. 6A and 6B. Note that FIG. 6A is a diagram showing a transition example of the display screen of the sub-display device 18 in a situation where the player registration state is not set, and FIG. 6B is a diagram showing a sub-display in a situation where the player registration state is set. It is a figure which shows the transition example of the display screen of the apparatus 18.

In the situation where the player registration state is not set, as shown in FIG. 6A, the display screen of the sub display device 18 transitions between the top screen 221 and the menu screen 222, and from the menu screen 222 and the menu screen 222. Transitions are possible only to and from various possible display screens, and the transitions between these display screens are controlled by the sub-control board 72 (sub-CPU 201 described later). For example, the sub-control board 72 is placed between the top screen 221 and the menu screen 222 based on a touch operation (for example, a tap operation for a predetermined button or a swipe operation on the display screen) acquired via the touch sensor 19. Switch the display screen. However, in the situation where the player registration state is not set, the sub-control board 72 controls so that the game information screens 223, 224, and 225 cannot be displayed. That is, in the situation where the player registration state is not set, the player cannot display the game information screens 223, 224, and 225 on the sub display device 18.

On the other hand, in the situation where the player registration state is set, as shown in FIG. 6B, the display screen of the sub display device 18 is between the top screen 221 and the menu screen 222, and the menu screen 222 and the menu screen 222. In addition to the transition between the various display screens that can be transitioned from, the transition between the menu screen 222 and the game information screens 223, 224, 225 is also possible, and the transition between these display screens is the sub-control board 72 (subs described later). It is controlled by CPU201). That is, the sub-control board 72 is not only between the top screen 221 and the menu screen 222, but also between the top screen 221 and the menu screen 222 and the game information screen based on the touch operation acquired via the touch sensor 19. The display screen can also be switched between 223, 224, and 225. Therefore, in the present embodiment, when the player registration state is set, the player can display the game information screens 223, 224, and 225 on the sub display device 18.

As shown in FIG. 6B, the transition order of the display screens between the top screen 221 and the menu screen 222 and the game information screens 223, 224, and 225 is arbitrary. Therefore, for example, the top screen 221 may be configured to directly transition to the game information screens 223, 224, 225, or the top screen 221 to the game information screens 223, 224, 225 only via the menu screen 222. It may be configured so that it can be transitioned.

In the pachislot machine 1 of the present embodiment, the top screen 221 can be transitioned to the game information screen 223, 224, 225 only via the menu screen 222 (the top screen 221 cannot be directly transitioned to the game information screen 223, 224, 225). ) Is adopted. In the pachislot machine 1 of the present embodiment, on the menu screen 222, the player swipes the display screen (not the menu selection operation) to display the display screen from the menu screen 222 to the game information screens 223 and 224. , 225 can be transitioned.

In the present embodiment, the game information screens 223, 224, and 225 are display screens provided completely independently of the menu screen 222. That is, in the pachislot machine 1 of the present embodiment, the information indicating the result of the game in which the player has a strong interest during the game, which is the game history, is independent as information having nothing to do with the result of the game such as the payout arrangement and the volume control. To display. Then, in the present embodiment, in the situation where the player registration state is set, the game information screens 223, 224, and 225 can be displayed without the player performing a menu selection operation on the menu screen 222. .. Therefore, in the present embodiment, when the player registration state is set, it is possible to easily access the emotional game history information desired by the player.

Further, in the present embodiment, in the menu selection operation for the menu screen 222, the display screen cannot be changed to the game information screens 223, 224, 225, and the swipe operation for the menu screen 222 (specified in the menu display). The display screen cannot be changed to the game information screens 223, 224, and 225 unless the operation is not performed. Therefore, in the pachi-slot machine 1 of the present embodiment, the swipe operation for transitioning the display screen to the game information screens 223, 224, 225 can be treated as a hidden command in the situation where the player registration state is set. In this case, from the player's own knowledge of pachislot 1, more detailed game history information that cannot be seen by other players with little knowledge can be seen, so that the player can see more detailed game history information than the other players. It is possible to play the game advantageously, and as a result, it can be expected that the player actively plays the game.

[Display switching function from the game information screen to the top screen]
The pachi-slot machine 1 of the present embodiment has a function of shifting the display screen of the sub-display device 18 from the game information screens 223, 224, 225 to the top screen 221 manually or automatically by the player. Specifically, in the present embodiment, when the "back" button is operated on the game information screens 223, 224, 225, the display screen transitions from the game information screen 223, 224, 225 to the top screen 221 (manual transition). function). Further, in the present embodiment, when a predetermined condition is satisfied while the game information screens 223, 224, and 225 are displayed, the display screen automatically changes to the top screen 221 regardless of the player's operation. Transition (automatic transition function).

More specifically, in the pachislot machine 1, while the game information screens 223, 224, and 225 are displayed, the insertion operation (operation to the MAX bet button 15a, operation to the 1 bet button 15b, and the medal insertion slot 14 is performed. When the operation of inserting medals) is performed, the display screen of the sub display device 18 automatically transitions to the top screen 221. In addition, in a gaming state (high lip state) in which the probability that the replay combination is determined as the internal winning combination is high, such as the ART gaming state, medals are automatically inserted due to the operation of the replay accompanying the replay combination winning. As a result, in the high lip state, the opportunity to display the game information screens 223, 224, and 225 may be limited. Therefore, in the pachi-slot machine 1 of the present embodiment, when a medal is automatically inserted by the operation of the re-game, the display screen is automatically displayed on the game information screen 223, not by the operation of inserting the medal but by the start operation. , 224, 225 transitions to the top screen 221.

That is, in the present embodiment, when the re-game is activated and the game information screens 223, 224, 225 are displayed, the display screen is automatically changed to the game information screens 223, 224, triggered by the start operation. , 225 transitions to the top screen 221. On the other hand, when the re-game operation is not performed, the display screen automatically transitions from the game information screen 223, 224, 225 to the top screen 221 triggered by the input operation.

[Display switching function from the menu content display screen to the top screen (or menu screen)]
In the pachi-slot machine 1 of the present embodiment, the display screen of the sub-display device 18 can be changed by a menu selection operation on the menu screen 222, and various menu content display screens (registration screen, explanation screen, array dividend screen, reach screen, WEB introduction). It has a function of manually or automatically transitioning from the screen (screen and volume adjustment screen) to the top screen 221 (or menu screen 222). Specifically, in the present embodiment, when a predetermined button (for example, the "return to TOP" button) is operated on the menu content display screen, the display screen transitions from the menu content display screen to the top screen 221 (). Manual transition function). Further, in the present embodiment, when a specific button (for example, a "back" button) is operated on the menu content display screen, the display screen transitions from the menu content display screen to the menu screen 222 (manual transition). function).

Further, in the present embodiment, when a predetermined time elapses while the menu content display screen is displayed, the display screen automatically changes to the top screen 221 (or menu screen 222) regardless of the operation of the player. Transition (automatic transition function). At this time, the predetermined time that triggers the automatic transition to the top screen 221 (or the menu screen 222) differs depending on the type of the menu content display screen currently displayed. For example, if the volume adjustment screen for adjusting the volume output from the pachislot machine 1 is displayed for a long time, not only the volume may be adjusted to an unintended volume due to an erroneous operation, but also another player may be affected by the erroneous operation. It may be uncomfortable. Therefore, the volume adjustment screen is set to automatically transition to the top screen 221 (or menu screen 222) in a shorter time than other menu content display screens. On the other hand, the registration screen is set to automatically transition to the top screen 221 (or menu screen 222) in a longer time than other menu content display screens in order to facilitate registration of players. ..

That is, on each menu content display screen, an elapsed time (automatic transition time) that triggers an automatic transition to the top screen 221 (or menu screen 222) is appropriately set according to the type of the menu content display screen. , The volume adjustment screen is set with an automatic transition time shorter than that of other menu content display screens, and the registration screen is set with an automatic transition time longer than that of other menu content display screens.

[Menu operation enable / disable selection function]
In the pachi-slot machine 1 of the present embodiment, the display screen of the sub-display device 18 is changed from the menu screen 222 to the registration screen, the explanation screen, the arrangement payout screen, the reach eye screen, the WEB introduction screen, and the volume adjustment screen. A person can perform various operations according to these menu content display screens, and can confirm various information. It should be noted that a function (a function for selecting whether or not the menu can be operated) may be provided so that the function that the player can select the menu can be restricted according to the setting on the game store side.

For example, the display screen may be made incapable of transitioning from the menu screen 222 to the volume control screen (for example, the "volume" button 222g is not displayed on the menu screen 222) by the setting on the game store side. In this case, it is possible to prevent the player from adjusting the volume.

<Control system provided by pachislot>
Next, the control system included in the pachi-slot machine 1 will be described with reference to FIG. 7. FIG. 7 is a circuit block diagram showing the configuration of the control system of the pachislot machine 1.

The pachi-slot machine 1 has a main control board 71 provided on the middle door 41 and a sub control board 72 provided on the front door 2b. Further, the pachi-slot machine 1 has a reel relay terminal board 74, a setting key type switch 54 (setting switch), and a cabinet-side relay board 44 connected to the main control board 71. Further, the pachi-slot machine 1 has an external centralized terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, a reset switch 76, and a power supply device 53 connected to the main control board 71 via a cabinet-side relay board 44. Since the configuration of the hopper device 51 has been described above, the description thereof will be omitted here.

The reel relay terminal plate 74 is arranged inside the reel main body of each reel 3L, 3C, 3R. The reel relay terminal plate 74 is electrically connected to a stepping motor (not shown) of each reel 3L, 3C, 3R, and relays a signal output from the main control board 71 to the stepping motor.

The setting key type switch 54 is provided on the main control board case 55. The setting key type switch 54 is used when changing the setting of the pachi-slot 1 (settings 1 to 6) or when confirming the setting of the pachi-slot 1.

The cabinet-side relay board 44 is a relay board on which wiring for connecting the main control board 71, the external centralized terminal board 47, the hopper device 51, the medal auxiliary storage switch 75, the reset switch 76, and the power supply device 53 is mounted. Is. The external centralized terminal plate 47 is provided to output signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachislot machine 1. The medal auxiliary storage switch 75 is provided in the medal auxiliary storage 52, and detects whether or not the medal auxiliary storage 52 is full of medals. The reset switch 76 is used, for example, when changing the setting of the pachislot machine 1.

The power supply device 53 includes a power supply board 53b and a power supply switch 53a connected to the power supply board 53b. The power switch 53a is pressed when supplying the necessary power to the pachi-slot machine 1. The power supply board 53b is connected to the main control board 71 via the cabinet side relay board 44, and is also connected to the sub control board 72 via the sub relay board 61.

Further, the pachi-slot machine 1 has a selector 66, a door open / close monitoring switch 67, a BET switch 77, and a settlement switch 78, which are connected to the main control board 71 via the door relay terminal plate 68 and the door relay terminal plate 68. It has a start switch 79, a stop switch board 80, a game operation display board 81, an auxiliary relay board 61, a first interface board 301 for a testing machine, and a second interface board 302 for a testing machine. Since the selector 66, the door open / close monitoring switch 67, and the sub-relay board 61 have been described above, their description will be omitted here.

The BET switch 77 (throwing operation detecting means) detects that the MAX bet button 15a or the 1-bet button 15b is pressed by the player. The checkout switch 78 detects that the checkout button (not shown) has been pressed by the player. The start switch 79 (start operation detecting means) detects that the start lever 16 has been operated by the player (start operation).

The stop switch board 80 (stop operation detecting means) includes a circuit for stopping the rotating main reel and a circuit for displaying the stoptable main reel by an LED or the like. Further, the stop switch board 80 is provided with a stop switch (not shown). The stop switch detects that each of the stop buttons 17L, 17C, 17R is pressed by the player (stop operation).

The game operation display board 81 is connected to the information display (7-segment display) 6 and the LED 82. The LED 82 has, for example, three LEDs (hereinafter, "first LED" to "1st LED") for displaying the number of inserted medals, which are lit according to the number of medals inserted in this game (hereinafter referred to as "the number of inserted medals"). An LED that lights a mark indicating that medals can be inserted, a mark indicating the start of a game, a mark for replaying a game, etc., based on a signal input from the game operation display board 81 (referred to as "third LED"). Etc. are included. In the first LED to the third LED (display means), when one medal is inserted, the first LED lights up, and when two medals are inserted, the first and second LEDs light up, and three medals (game). When the number of startable medals is turned on, the first LED to the third LED are turned on. Since the information display 6 has been described above, the description thereof will be omitted here.

Both the first interface board 301 for the testing machine and the second interface board 302 for the testing machine are relay boards used when outputting various signals related to the game to the testing machine in the certification test (test firing test) of the pachislot 1 (test firing test). Since these relay boards are not mounted on the Pachislot 1 as a release product for sale, the main control circuit 90 of the main control board 71 for sale includes the first interface board 301 for the testing machine and the testing machine. Various electronic components required for connecting to the second interface board 302 for use are also not mounted). For example, a test signal for controlling a main operation related to a game (for example, internal lottery, reel stop control, etc.) is output via a first interface board 301 for a testing machine, and is determined by, for example, a main control board 71. The test signal and the like related to the pushed order navigation are output via the second interface board 302 for the testing machine.

The sub-control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub-relay board 61. Further, the pachi-slot machine 1 has a speaker group 84, an LED group 85, a 24h door open / close monitoring unit 63, a touch sensor 19, and a display unit 212 connected to the sub-control board 72 via the sub-relay board 61. Since the touch sensor 19 has been described above, the description thereof will be omitted here.

The speaker group 84 includes speakers 65L and 65R and various speakers (not shown). The LED group 85 includes a lamp group 21 provided on the front panel 10, a light source that emits light for illuminating the decorative panel of the lumbar panel 12 from the back side, and the like. The 24h door open / close monitoring unit 63 stores the open / close history information of the middle door 41. Further, the 24h door open / close monitoring unit 63 outputs a signal for displaying an error by the display device 11 to the sub control board 72 (sub control circuit 200) when the middle door 41 is opened. The display unit 212 includes, for example, a projected member 212a constituting the display device 11 and another projected member having a curved display surface provided on the back side of the projected member 212a.

Further, the pachi-slot machine 1 has a ROM cartridge board 86 and a liquid crystal relay board 87 connected to the sub-control board 72. The ROM cartridge board 86 and the liquid crystal relay board 87 are housed in the sub-control board case 57 together with the sub-control board 72.

The ROM cartridge board 86 is a board for managing various control programs executed by the sub CPU 201, image (video) for production, audio (speaker group 84), light (LED group 85), and communication data. .. The liquid crystal relay board 87 is a board that relays the connection wiring between the sub-control board 72, the projector mechanism 211 that constitutes the display device 11, and the sub-display device 18. Since the projector mechanism 211 and the sub-display device 18 have been described above, their description will be omitted here.

<Main control circuit>
Next, the configuration of the main control circuit 90 mounted on the main control board 71 will be described with reference to FIG. FIG. 8 is a block diagram showing a configuration example of the main control circuit 90 of the pachislot machine 1.

The main control circuit 90 includes a microprocessor 91, a clock pulse generation circuit 92, a power management circuit 93, and a switching regulator 94 (power supply means).

The microprocessor 91 is a microprocessor with a security function for a game machine. In the microprocessor 91 of the present embodiment, as will be described later, various instruction codes specific to the microprocessor 91 that can be specified in the source program (for example, "LDQ" instruction and the like described later: hereinafter, "main CPU 101". Dedicated instruction code ") is provided. In the present embodiment, the processing efficiency and the reduction of the program capacity are realized by using the instruction code dedicated to the main CPU 101. The internal configuration of the microprocessor 91 will be described in detail with reference to FIG. 9 described later, and the instruction code dedicated to the main CPU 101 provided in the microprocessor 91 will be described in detail in various processes executed by the main control circuit described later. To do.

The clock pulse generation circuit 92 generates a clock pulse signal for operating the main CPU, and outputs the generated clock pulse signal to the microprocessor 91. The microprocessor 91 executes a control program based on the input clock pulse signal.

The power management circuit 93 manages fluctuations in the DC 12V power supply voltage supplied from the power supply board 53b (see FIG. 7). Then, the power management circuit 93 outputs a reset signal to the "XSRST" terminal of the microprocessor 91, for example, when the power is turned on (when the power supply voltage exceeds the starting voltage value (10V) from 0V). When a power failure occurs (when the power supply voltage falls below the power failure voltage value (10.5V) from 12V), the power failure detection signal is output to the "XINT" terminal of the microprocessor 91. That is, the power management circuit 93 is a means (starting means) for outputting a reset signal (starting signal) to the microprocessor 91 when the power is turned on, and a power failure detection signal (power failure signal) to the microprocessor 91 when a power failure occurs. Also serves as a means for outputting (power failure means).

The switching regulator 94 is a DC / DC conversion circuit, generates a DC drive voltage (power supply voltage of DC 5 V) of the microprocessor 91, and outputs the generated DC drive voltage to the “VCC” terminal of the microprocessor 91.

<Microprocessor>
Next, the internal configuration of the microprocessor 91 will be described with reference to FIG. FIG. 9 is a block diagram showing an internal configuration of the microprocessor 91.

The microprocessor 91 includes a main CPU 101, a main ROM 102 (first storage means), a main RAM 103 (second storage means), an external bus interface 104, a clock circuit 105, a reset controller 106, an arithmetic circuit 107, and the like. It has a random number circuit 110, a parallel port 111, an interrupt controller 112, a timer circuit 113, a first serial communication circuit 114, and a second serial communication circuit 115. Each of these parts constituting the microprocessor 91 is connected to each other via a signal bus 116.

The main CPU 101 executes various control programs based on the clock pulse generated by the clock circuit 105 to perform control related to the overall game operation. Here, reel stop control will be described as an example of the control operation of the main CPU 101.

The main CPU 101 counts the number of times a pulse is output to the stepping motors of each reel 3L, 3C, 3L (main reel) after detecting the reel index. As a result, the main CPU 101 manages the rotation angle of each reel (mainly, how many symbols the reel has rotated). The reel index is information indicating that the reel has made one revolution. This reel index is, for example, an optical sensor having a light emitting portion and a light receiving portion, and a detection piece provided at a predetermined position on each reel and interposed between the light emitting portion and the light receiving portion due to rotation of each main reel. It is detected by the provided reel position detection unit (not shown).

Here, the management of the rotation angle of each reel 3L, 3C, 3L (main reel) will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 103. Then, each time the output of a predetermined number of pulses required for the rotation of one symbol is counted by the pulse counter, the symbol counter provided in the main RAM 103 is added one by one. The symbol counter is provided according to each reel. The value of the symbol counter is cleared when the reel index is detected by the reel position detection unit (not shown).

That is, in the present embodiment, by managing the symbol counter, it is possible to manage how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

The main ROM 102 stores various control programs executed by the main CPU 101, various data tables, data for transmitting various control commands (commands) to the sub control circuit 200, and the like. The main RAM 103 is provided with a storage area for storing various data such as internal winning combinations determined by executing the control program. The internal configuration (memory map) of the main ROM 102 and the main RAM 103 will be described in detail with reference to FIG. 12 described later.

The external bus interface 104 is for electrically connecting the microprocessor 91 to an external signal bus (not shown) to which various components (for example, reels and the like) provided outside the microprocessor 91 are connected. It is an interface circuit. The clock circuit 105 is configured to include, for example, a frequency divider (not shown), and a clock pulse signal for CPU operation input from the clock pulse generation circuit 92 is transmitted by another component (for example, a timer circuit 113). Convert to a clock pulse signal of the frequency used. The clock pulse signal generated by the clock circuit 105 is also output to the reset controller 106.

The reset controller 106 resets the IAT (Illegal Address Trap) and the WDT (watchdog timer) based on the reset signal input from the power supply management circuit 93. The arithmetic circuit 107 includes a multiplication circuit and a division circuit. For example, when the "MUL" instruction described later (see FIG. 93B described later) is executed on the source program, the arithmetic circuit 107 executes the multiplication process based on the "MUL" instruction.

The random number circuit 110 generates a random number in a predetermined range (for example, 0 to 65535 or 0 to 255). Although not shown, the random number circuit 110 has random number registers 0 for obtaining 2-byte hard-latch random numbers, random number registers 1 to 3 for obtaining 2-byte soft-latch random numbers, and 1-byte soft-latch random numbers. It is composed of random number registers 4 to 7 for obtaining. The main CPU 101 extracts one value from the random numbers in a predetermined range generated by the random number circuit 110, for example, as a random number value for internal lottery. The parallel port 111 is a signal port (memory map I / O) input / output between the microprocessor 91 and various circuits (for example, power management circuit 93, etc.) provided outside the microprocessor 91. .. The parallel port 111 is also connected to the random number circuit 110 and the interrupt controller 112. The start switch 79 is connected to any of the input ports of PI0 to PI4 of the parallel port 111, and when the start switch 79 is turned on (on-edge), a latch signal is sent from the parallel port 111 to the random number register 0 of the random number circuit 110. Is output. Then, in the random number circuit 110, the random number register 0 is latched by the input of the latch signal, and a 2-byte hard latch random number is acquired.

The interrupt controller 112 interrupts processing by the main CPU 101 based on a power failure detection signal input from the power management circuit 93 via the parallel port 111 or a timeout signal input from the timer circuit 113 at a cycle of 1.1172 ms. Controls the execution timing of. When a power failure detection signal is input from the power management circuit 93, or when a timeout signal is input from the timer circuit 113, the interrupt controller 112 sends an interrupt request signal indicating an interrupt processing start command to the main CPU 101. Output to. The main CPU 101 has an input port check process, a reel control process, a communication data transmission process, a 7-segment LED drive process, and a timer based on an interrupt request signal input from the interrupt controller 112 in response to a timeout signal from the timer circuit 113. Various interrupt processing such as update processing (see FIG. 158 described later) is performed.

The timer circuit 113 (PTC) operates with a clock pulse signal generated by the clock circuit 105 (a clock pulse signal having a frequency obtained by dividing the clock pulse signal for operating the main CPU by a divider (not shown)) ( Count the elapsed time). Then, the timer circuit 113 outputs a timeout signal (trigger signal) to the interrupt controller 112 at a cycle of 1.1172 msec.

The first serial communication circuit 114 is a circuit that controls a serial transmission operation when data (various control commands (commands)) are transmitted from the main control board 71 to the sub control board 72. The second serial communication circuit 115 is a circuit that controls the serial transmission operation when data is transmitted from the main control board 71 to the second interface board 302 for the testing machine.

<Secondary control circuit>
Next, the configuration of the sub-control circuit 200 (sub-control means) mounted on the sub-control board 72 will be described with reference to FIG. FIG. 10 is a block diagram showing a configuration example of the sub-control circuit 200 of the pachi-slot machine 1.

The sub-control circuit 200 is electrically connected to the main control circuit 90, and performs processing such as determination and execution of the effect content based on a command transmitted from the main control circuit 90. The sub-control circuit 200 basically includes a sub CPU 201, a sub RAM 202, a rendering processor 203, a drawing RAM 204, and a driver 205.

The sub CPU 201 is connected to the ROM cartridge board 86. The driver 205 is connected to the liquid crystal relay board 87. That is, the driver 205 is connected to the projector mechanism 211 and the sub display device 18 via the liquid crystal relay board 87.

The sub CPU 201 controls the output of video, sound, and light according to the control program stored in the ROM cartridge board 86 in response to the command transmitted from the main control circuit 90. The ROM cartridge board 86 is basically composed of a program storage area and a data storage area.

The control program executed by the sub CPU 201 is stored in the program storage area. For example, in the control program, the main board communication task for controlling the communication with the main control circuit 90 and the effect registration for extracting the random value for the effect and determining and registering the effect content (effect data). Contains various programs for executing tasks. Further, the control program includes a drawing control task that controls the display of the image by the display device 11 based on the determined effect content, a lamp control task that controls the light output by the light source such as the LED group 85, and a sound by the speaker group 84. It also includes various programs for executing voice control tasks and the like that control the output of the LED.

The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to video creation. The data storage area also includes a storage area for storing sound data related to BGM and sound effects, a storage area for storing lamp data related to a pattern of turning on and off light, and the like.

The sub RAM 202 is provided with a storage area for registering the determined effect content and effect data, and a storage area for storing various data such as a sub flag (internal winning combination) transmitted from the main control circuit 90.

The sub CPU 201, the rendering processor 203, the drawing RAM (including the frame buffer) 204, and the driver 205 create an image according to the animation data specified by the effect content, and display the created image on the display device 11 (projector mechanism 211) and /. Alternatively, it is displayed on the sub display device 18. The display device 11 (projector mechanism 211) and the sub-display device 18 are individually controlled by the sub-control board 72.

Further, the sub CPU 201 causes the speaker group 84 to output a sound such as BGM according to the sound data specified by the effect content. Further, the sub CPU 201 controls the lighting and extinguishing of the LED group 85 according to the lamp data specified by the effect content.

<Various registers of the main CPU>
Next, various registers included in the main CPU 101 will be described with reference to FIG. Note that FIG. 11 is a schematic configuration diagram of various registers included in the main CPU 101.

As the main register, the main CPU 101 includes an accumulator A (hereinafter referred to as "A register"), a flag register F (flag register), a general-purpose register B (hereinafter referred to as "B register"), and a general-purpose register C (hereinafter referred to as "B register"). General-purpose register D (hereinafter referred to as "D register"), general-purpose register E (hereinafter referred to as "E register"), general-purpose register H (hereinafter referred to as "H register"), and general-purpose register L (hereinafter referred to as "H register"). , "L register"). Further, as sub-registers, the main CPU 101 includes an accumulator A', a flag register F', a general-purpose register B', a general-purpose register C', a general-purpose register D', a general-purpose register E', a general-purpose register H', and a general-purpose register L'. As a general-purpose register. Each register is composed of 1-byte registers.

Further, in the present embodiment, the B register and the C register are used as a pair register (hereinafter, referred to as “BC register”), and the D register and the E register are used as a pair register (hereinafter, referred to as “DE register”). Further, in the present embodiment, the H register and the L register are used as a pair register (hereinafter, referred to as “HL register”).

As shown in FIG. 11, predetermined flag information indicating the result of arithmetic processing and the like is set in each bit of the flag registers F and F'. For example, bit 6 (D6) is set with data (zero flag) indicating whether or not the calculation result is "0" in the calculation result determination process. Specifically, when the calculation result is "0", the data "1" is set in the bit 6, and when the calculation result is not "0", the data "0" is set in the bit 6. Then, in the calculation result determination process, the main CPU 101 makes a determination (YES / NO) with reference to the bit 6 data “0” / “1”.

Further, the main CPU 101 has an expansion register Q (hereinafter, referred to as “Q register”). The Q register is composed of a 1-byte register. In this embodiment, as will be described in various processing flows described later, various main CPU 101 dedicated instruction codes for specifying an address using this Q register are provided on the source program, and this instruction code is provided. By using the above, processing efficiency is improved and the capacity of the main ROM 102 is reduced. In various main CPU 101 dedicated instruction codes that specify an address using the Q register, the address data (address value) on the upper side of the address is stored in the Q register. Immediately after the reset of the main CPU 101, "F0H" is set in the Q register as an initial value. Further, in the "LD Q, n (8-bit data)" instruction using the Q register, the value of the Q register is changed by setting arbitrary 1-byte data in "n" and executing the instruction. be able to.

Further, the main CPU 101 includes an interrupt page address register I and a memory refresh register R composed of 1-byte registers, and an index register IX and an index register IY composed of 2-byte registers. , The stack pointer SP and the program counter PC are provided as dedicated registers.

<Internal configuration of main ROM and main RAM (memory map)>
Next, the internal configurations (hereinafter referred to as “memory maps”) of the main ROM 102 and the main RAM 103 included in the main control circuit 90 (microprocessor 91) will be described with reference to FIGS. 12A to 12C. Note that FIG. 12A is a diagram showing a memory map of the entire memory, FIG. 12B is a diagram showing a memory map of the main ROM 102, and FIG. 12C is a diagram showing a memory map of the main RAM 103.

In the memory map of the entire memory included in the main control circuit 90 (microprocessor 91), as shown in FIG. 12A, from the head (0000H) side of the address, the memory area of the main ROM 102, the memory area of the main RAM 103, the built-in register area, and The XCS decoding areas are arranged at predetermined addresses in this order with an unused area in between.

In the memory map of the main ROM 102, as shown in FIG. 12B, the program area, the data area, the non-standard area, the trademark recording area, the program management area, and the security setting area are displayed from the head (0000H) side of the address of the main ROM 102. In order, they are arranged at predetermined addresses.

In the program area, control programs for various processes executed by the main CPU 101 in various control processes related to the playability of the game performed by the player are stored. In the data area, various data used by the main CPU 101 (for example, a data table such as an internal lottery table, and various sub-control circuits 42 in various control processes related to the playability of the game performed by the player). Data for transmitting control commands (commands), etc.) are stored. That is, the game ROM area (game storage area) composed of the program area and the data area is necessary for the control process (process related to the game property) related to the game playability of the game actually performed by the player at the game store. Various programs and various data are stored.

Further, in the non-standard area, control programs and data of various processes (processes that do not affect the playability) that are not directly related to the playability of the game performed by the player are stored. For example, programs and data used in the pachislot 1 certification test (test firing test), control programs and data used in checksum generation processing at the time of power failure and thumb check processing at power recovery, and fraud countermeasure programs. And the data required for it are stored in the non-standard area.

In the memory map of the main RAM 103, as shown in FIG. 12C, the game RAM area (predetermined storage area, game temporary storage area) and the non-standard RAM area (non-standard temporary) from the head (F000H) side of the address of the main RAM 103. Storage areas) are arranged at predetermined addresses in this order.

The game RAM area is provided with a work area and a stack area for temporarily storing various data such as an internal winning combination determined by executing a control program related to the game playability performed by the player. .. Then, each of the various data is stored in the work area of a predetermined address in the game RAM area.

Further, the non-standard RAM area is provided with a non-standard work area that is a work area for various processes that are not directly related to the playability of the game performed by the player, and a non-standard stack. In the present embodiment, using this non-standard RAM area, various processes that are not directly related to the playability of the game performed by the player, such as a checksum process, are executed.

As described above, in the pachi-slot machine 1 of the present embodiment, various programs and various data (tables) used for various processes not directly related to the playability of the game performed by the player are used for the game in the main ROM 102. It is stored in a non-standard ROM area (non-standard storage area) located at an address different from the ROM area. In addition, various processes that are not directly related to the playability of the game performed by such a player are performed in the main RAM 103 using an out-of-specification RAM area arranged at an address different from the game RAM area. ..

In such a configuration of the main ROM 102, programs and data unnecessary for the game itself actually played by the player are arranged in the ROM area (non-standard ROM area) where the program or the like cannot be arranged according to the conventional rules. can do. Therefore, in the present embodiment, it is possible to avoid pressure on the capacity of the gaming ROM area.

<Transition flow of game state>
Next, various gaming states managed by the main control circuit 90 (main CPU 101) of the pachislot machine 1 of the present embodiment and their transition flows will be described with reference to FIGS. 13 and 14. Note that FIG. 13A is a transition flow diagram of the basic gaming state of the pachislot machine 1, and FIG. 13B is a table summarizing the transition conditions of the gaming state. Further, FIG. 14A is a transition flow diagram of a gaming state in consideration of whether or not the notification (ART) function is activated, and FIG. 14B is a table summarizing the transition conditions of the gaming state.

[Basic game state transition flow]
In the pachislot machine 1 of the present embodiment, a big bonus (hereinafter referred to as "BB") is provided as a type of bonus game. The BB is a continuous accessory actuating device for a regular bonus (hereinafter referred to as “RB”) called a first-class special accessory, and continuously operates the RB.

Therefore, in the present embodiment, the main control circuit 90 manages the gaming state based on the presence or absence of winning / operating (winning) of the bonus combination. Specifically, as shown in FIG. 13A, the main control circuit 90 is based on the presence or absence of a winning / operating (winning) of a bonus combination (internal winning combination of the names "F_BB1" and "F_BB2" described later). It manages three types of gaming states called "bonus non-winning state", "inter-flag state", and "bonus state".

The bonus non-winning state is a state in which the bonus is not winning and the bonus is not activated (winning), and the bonus state is a state in which the bonus is activated. Further, in the present embodiment, when the bonus combination is determined as the internal winning combination, the bonus combination is carried over as the internal winning combination over a plurality of games until the bonus is won. The inter-flag state is a state in which the bonus combination is carried over as an internal winning combination, that is, a state in which the bonus combination is won and the bonus is not activated.

Whether or not the bonus combination is won is determined by the data stored in the hit request flag storage area (see FIGS. 28 to 30 described later) and the carry-over combination storage area (see FIG. 31 described later) provided in the main RAM 103. It is managed based on. Further, whether or not the bonus is activated (winning) is managed based on the data stored in the game state flag storage area (see FIG. 32 described later) provided in the main RAM 103.

Further, in the present embodiment, as shown in FIG. 13A, in the gaming state in which the bonus is not activated (bonus non-winning state and inter-flag state), the types of internal winning combinations related to the replay and the winning probabilities thereof are different from each other. Six types of states from the RT0 gaming state to the RT5 gaming state (hereinafter, referred to as "RT0 state" to "RT5 state", respectively) are provided. The RT0 state, RT2 state, and RT5 state are gaming states in which the probability that the replay combination is determined as the internal winning combination is low, and the RT1 state has a medium probability that the replay combination is determined as the internal winning combination. It is a gaming state with a medium probability. Further, the RT3 state and the RT4 state are gaming states in which the probability that the replay combination is determined as the internal winning combination is high. In the present embodiment, the RT state in the bonus non-winning state is any of the RT0 state to the RT4 state, and the RT state in the inter-flag state is the RT5 state.

Therefore, in the present embodiment, the main control circuit 90 is based on the type of the internal winning combination related to the replay and the winning probability thereof in the gaming state in which the bonus is not activated (bonus non-winning state and inter-flag state). It also manages six types of states, RT1 state to RT5 state.

The RT0 state to the RT5 state are managed based on the data stored in the game state flag storage area (see FIG. 32 described later) provided in the main RAM 103. Specifically, in the pachi-slot machine 1 of the present embodiment, flags indicating five RT states of the RT1 state flag to the RT5 state flag are provided, and the RT state is managed by managing the on / off states of these flags by the main RAM 103. Is managed. Then, the main control circuit 90 specifies the RT state corresponding to the RT state flag that is in the ON state as the current RT state. When all the RT state flags are off, the main control circuit 90 identifies that the current RT state is the RT0 state.

As shown in FIGS. 13A and 13B, when the bonus combination (internal winning combination of the names "F_BB1" and "F_BB2" described later) is determined as the internal winning combination in the bonus non-winning state (when the transition condition (1) is satisfied). ), The main control circuit 90 shifts the gaming state from the bonus non-winning state to the inter-flag state. Further, when the bonus combination is won in the inter-flag state (when the transition condition (2) is satisfied), the main control circuit 90 shifts the gaming state from the inter-flag state to the bonus state.

Further, when the number of medals exceeding the specified number (216) is paid out in the bonus state and the bonus state ends (when the transition condition (3) is satisfied), the main control circuit 90 changes the gaming state from the bonus state to the RT1 state (RT1 state). Shift to the bonus non-winning state).

When 20 games have elapsed in the RT1 state (when the transition condition (4) is satisfied), the main control circuit 90 shifts the game state from the RT1 state to the RT0 state. Further, in the RT1 state, if the symbol combination related to the abbreviation "bell spilled eyes" (see FIG. 28 described later) is displayed on the valid line before 20 games have elapsed (when the transition condition (5) is satisfied). , The main control circuit 90 shifts the gaming state from the RT1 state to the RT2 state.

In the RT0 state, when the symbol combination related to the abbreviation "bell spilled eye" is displayed on the valid line (when the transition condition (5) is satisfied), the main control circuit 90 shifts the gaming state from the RT0 state to the RT2 state. Let me. In the RT2 state, when the symbol combination related to the abbreviation "RT3 transition lip" (see FIG. 28 described later) is displayed on the valid line (when the transition condition (6) is satisfied), the main control circuit 90 sets the gaming state. The RT2 state is changed to the RT3 state.

In the RT3 state, when the symbol combination related to the abbreviation "RT4 transition lip" (see FIG. 28 described later) is displayed on the valid line (when the transition condition (7) is satisfied), the main control circuit 90 sets the gaming state. The RT3 state is changed to the RT4 state. Further, in the RT3 state, when the symbol combination (see FIG. 28 described later) related to the abbreviation "bell spilled eye" or "RT2 transition lip" is displayed on the valid line (when the transition condition (8) is satisfied), the main The control circuit 90 shifts the gaming state from the RT3 state to the RT2 state. Further, in the RT4 state, when the symbol combination related to the abbreviation "bell spilled eye" or "RT2 transition lip" is displayed on the valid line (when the transition condition (8) is satisfied), the main control circuit 90 is in the gaming state. Shifts the gaming state from the RT4 state to the RT2 state.

As for the symbol combination related to the abbreviation "bell spilled eyes", the internal winning combination (small combination) related to the names "F_3 selection bell_1st", "F_3 selection bell_2nd" or "F_3 selection bell_3rd" described later is determined. Moreover, it is a combination of symbols displayed when the order of the stop operation is incorrect with respect to the push order determined for each type of the small winning combination (see FIG. 24 described later). As for the symbol combination related to the abbreviation "RT2 transition lip", the internal winning combination (replay combination) related to the names "F_maintenance lip_1st", "F_maintenance lip_2nd" or "F_maintenance lip_3rd" described later is determined, and This is a combination of symbols displayed when the order of stop operations is incorrect with respect to the push order determined for each type of replay combination.

As for the symbol combination related to the abbreviation "RT3 transition lip", the internal winning combination (replay combination) related to the names "F_RT3 lip_1st", "F_RT3 lip_213", "F_RT3 lip_231" or "F_RT3 lip_3rd" described later is determined. Moreover, it is a combination of symbols displayed when the order of the stop operation is the correct answer for the push order determined for each type of the replay combination. In addition, the symbol combination related to the abbreviation "RT4 transition lip" has an internal winning combination (replay role) related to the names "F_RT4 lip_123", "F_RT4 lip_132", "F_RT4 lip_2nd" or "F_RT4 lip_3rd" described later. It is a combination of symbols that are determined and displayed when the order of stop operations is correct for the push order determined for each type of replay combination.

[Transition flow of game state considering whether or not the notification (ART) function is activated]
In the present embodiment, the main control circuit 90 (main CPU 101) determines whether or not a function (ART function) for notifying a stop operation advantageous to the player is activated. Therefore, in the present embodiment, the activated / non-activated state of the ART function is also managed as the gaming state in the bonus non-operating state.

In the pachi-slot machine 1 of the present embodiment, as shown in FIG. 14A, the main control circuit 90 separates the "general game state" and the "ART game state" based on the presence or absence of notification (ART) in the non-bonus operating state. It is managed as the game state of. That is, in the management of the gaming state in consideration of the presence / absence of notification (ART), as shown in FIG. 14A, the main control circuit 90 is roughly classified into "bonus state", "general gaming state", and "ART gaming state". It manages three types of game states.

The general gaming state is basically a gaming state (non-ART) that does not notify information on a stop operation that is advantageous to the player, and is a gaming state that is disadvantageous to the player. Further, the general gaming state is any of the RT0 to RT4 states, and is an ART non-winning gaming state.

On the other hand, the ART gaming state is a gaming state that notifies information on a stop operation that is advantageous to the player, and is a gaming state that is advantageous to the player. Further, the ART gaming state is basically the RT4 state and the gaming state during the ART winning. In the present embodiment, when the RT state shifts to the RT4 state after winning the ART, the ART game is started.

Further, in the present embodiment, as shown in FIG. 14A, two types of states called "normal gaming state" and "CZ (chance zone)" are provided as general gaming states.

The normal game state is the most unfavorable game state for the player, but in the game in the normal game state, a lottery for transition to CZ is performed. Then, as shown in FIGS. 14A and 14B, in the game in the normal gaming state, when the transition lottery to the CZ is won (when the transition condition (A) is satisfied), the main control circuit 90 changes the gaming state to the normal gaming state. To CZ.

The CZ is a gaming state (chance zone) in which the expectation for the transition to the ART gaming state is high, and in the game during the CZ, a lottery for the transition to the ART is performed. Then, as shown in FIGS. 14A and 14B, in the game during CZ, when the lottery for transition to ART is not won (when the transition condition (B) is satisfied), the main control circuit 90 sets the game state. , CZ shifts to the normal gaming state. On the other hand, in the game during CZ, when the lottery for transition to ART is won (when the transition condition (C) is satisfied), the main control circuit 90 shifts the game state from CZ to the ART game state. At this time, although not shown in FIG. 14A, the main control circuit 90 shifts the gaming state from the CZ to the ART gaming state (normal ART or CT described later) via the ART preparation state described later.

As described above, the ART gaming state is started when the RT state shifts to the RT4 state after winning the ART. As shown in FIG. 13A, since the RT4 state shifts from the RT0 to RT2 states via the RT3 state, the ART gaming state is not started immediately even after winning the ART. Therefore, in the pachi-slot machine 1 of the present embodiment, the gaming state during the period from the winning of the ART to the transition from the RT state to the RT4 state is set as the ART preparation state. Then, in this game in the ART preparation state, information on the stop operation necessary for shifting the RT state to the RT4 state is notified.

Further, in the present embodiment, as shown in FIG. 14A, two types of ART gaming states, called "normal ART" and "CT (additional chance)", in which the playability is different from each other, are provided.

Normally, ART is a stop operation that is advantageous for the player for a predetermined number of games (for example, a stop operation for displaying a symbol combination with a large number of medals to be paid out, or a stop operation necessary for maintaining the RT4 state). Is the game state in which is notified. In addition, in a game during normal ART, a lottery for transition to CT is performed.

CT is a gaming state in which a player is notified of an advantageous stop operation and can add a normal ART duration for a specific period (a period of 8 games per set), and functions as an additional chance zone. It is a game state to play. Also, during CT, the game is usually played without digesting the duration of ART. The playability during CT will be described in detail later with reference to FIGS. 52A to 52C described later.

As shown in FIGS. 14A and 14B, in a game during normal ART, when the lottery for transition to CT is won (when the transition condition (D) is satisfied), the main control circuit 90 changes the game state from normal ART to CT. Shift the game state. Further, in the normal ART, when the duration of the normal ART ends (when the transition condition (E) is satisfied), the main control circuit 90 changes the gaming state from the normal ART to the general gaming state (normal gaming state or CZ). Migrate. In the present embodiment, the duration of normal ART is managed by the number of games, but the present invention is not limited to this, and the method of managing the duration of normal ART is arbitrary. For example, the duration of normal ART may be managed by the number of medals paid out during normal ART or the difference number, or by the number of notifications (number of navigations) that affect the payout of medals during normal ART. You may manage it.

As shown in FIGS. 14A and 14B, in the game during CT, when the duration of CT (8 games per set) ends (when the transition condition (F) is satisfied), the main control circuit 90 sets the game state to CT. To normal ART.

Further, as shown in FIG. 14A, when the bonus combination is won in the general gaming state (normal gaming state or CZ) or ART gaming state (normal ART or CT) (transition condition (2) described in FIGS. 13A and 13B). When is established), the main control circuit 90 shifts the gaming state from the general gaming state or the ART gaming state to the bonus state.

In the game in the bonus state, as described above, the lottery for transition to ART is performed, and in the game in the bonus state, if the lottery for transition to ART is non-winning (when the transition condition (G) is satisfied). , The main control circuit 90 shifts the gaming state from the bonus state to the general gaming state (normal gaming state or CZ). However, when the game has transitioned from the ART gaming state (normal ART or CT) to the bonus state, the main control circuit 90 sets the gaming state to the bonus state even if the game in the bonus state does not win the ART transition lottery. Shift from the bonus state to the ART gaming state (normal ART or CT). On the other hand, in the game in the bonus state, when the lottery for transition to ART is won (when the transition condition (H) is satisfied), the main control circuit 90 changes the gaming state from the bonus state to the ART gaming state (normal ART or CT). Migrate. As described above, at the end of the bonus state, the RT state shifts to the RT1 state. Therefore, when the gaming state shifts from the bonus state to the ART gaming state, the main control circuit 90 shifts the gaming state to the ART. It shifts to the ART game state via the preparation state.

<Structure of data table stored in main ROM>
Next, the configurations of various data tables stored in the main ROM 102 will be described with reference to FIGS. 15 to 27. The various data tables used in various lottery related to the game performance (CZ, normal ART, CT game performance) during the general game state and the ART game state will be described later together with the explanation of each game property. ..

[Design arrangement table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table is data that specifies the position of each symbol in each rotation direction of the left reel 3L, the middle reel 3C, and the right reel 3R, and the type of the symbol arranged at each position (hereinafter, symbol code (in FIG. 15). (Refer to the symbol code table of)) and stipulate the correspondence with.

In the symbol arrangement table, when the reel index is detected, the position of the symbol located in the middle region of each reel in the frame of the reel display window 4 is defined as "0". Then, in each reel, in the order of proceeding in the reel rotation direction (direction from the symbol position "19" in FIG. 15 toward the symbol position "0") with the symbol position "0" as a reference, " "0" to "19" are assigned to each symbol as the symbol position.

That is, by referring to the values of the symbol counters (“0” to “19”) and the symbol arrangement table, they are displayed in the upper region, the middle region, and the lower region of each reel in the frame of the reel display window 4. It is possible to specify the type of symbol. In this embodiment, as the symbols, "white 7", "blue 7", "chili top 1", "chili top 2", "chili bottom", "replay", "hat", "cactus 1", Ten kinds of symbols of "cactus 2" and "cactus 3" are used.

Further, in the present embodiment, as shown in the symbol code table, "00000001" is assigned as data to the symbol "white 7" (symbol code 1), and the symbol "blue 7" (symbol code 2) is assigned. "00000010" is assigned as the data. The symbol "Chile top 1" (symbol code 3) is assigned "000000111" as data, and the symbol "Chile top 2" (symbol code 4) is assigned "00000100" as data.

The symbol "Chile bottom" (symbol code 5) is assigned "000000101" as data, and the symbol "replay" (symbol code 6) is assigned "00000011" as data. The symbol "hat" (symbol code 7) is assigned "000000111" as data, and the symbol "cactus 1" (symbol code 8) is assigned "00001000" as data. Further, the symbol "cactus 2" (symbol code 9) is assigned "000001001" as data, and the symbol "cactus 3" (symbol code 10) is assigned "000001010" as data.

[Internal lottery table]
Next, the internal lottery table referred to when determining the internal winning combination will be described with reference to FIGS. 16 and 17. Note that FIG. 16 is an internal lottery table referred to in each of the RT0 state to the RT4 state. Further, FIG. 17A is an internal lottery table referred to in the RT5 state, and FIG. 17B is an internal lottery table referred to in the bonus state.

The internal lottery table is provided for each game state, and defines the correspondence between various internal winning combinations and the lottery value when each internal winning combination is determined. The lottery value is defined for each setting (settings 1 to 6) for adjusting the expected value of the internal winning such as a preset bonus combination or small combination. This setting is changed, for example, by using the reset switch 76 and the setting key type switch 54 (see FIG. 7).

In the internal lottery process of the present embodiment, first, the random number register 0 of the random number circuit 110 sets a random number value extracted from a predetermined numerical range (for example, 0 to 65535) corresponding to each internal winning combination. Add in sequence at the specified lottery value. Next, it is determined whether or not the lottery result (lottery value + random number value) exceeds 65535 (whether or not the lottery result overflows). Then, when the lottery result exceeds 65535 in the predetermined internal winning combination, it is determined that the internal winning combination has won. In the internal lottery process of the present embodiment, an example in which the lottery value is added to the extracted random number value to perform the lottery has been described, but the present invention is not limited to this, and the lottery value is subtracted from the random number value. It may be determined whether or not the subtraction result (lottery result) is less than "0" (whether or not the lottery result is underflowed), and the winning / non-winning of the internal lottery may be determined.

Therefore, in the internal lottery process of the present embodiment, the larger the numerical value defined as the lottery value, the higher the probability that the internal lottery combination will be determined. The winning probability of each internal winning combination can be expressed by "the lottery value specified in each winning number / the number of all random number values that may be extracted (random number denominator: 65536)".

In the internal lottery table referred to in each of the RT0 state to the RT4 state, as shown in FIG. 16, basically, the type and winning probability of the replay combination determined as the internal winning combination according to the type of the RT state. Changes. For example, the replay combination related to the names "F_chili lip (No. 25)" to "F_reach eye lip D (No. 31)" is not determined as an internal winning combination in the RT0 state to RT3 state, and is in the RT4 state. Only determined as an internal winning role. In the pachislot machine 1 of the present embodiment, the replay combination related to the names "F_chili lip (No. 25)" to "F_reach eye lip D (No. 31)" was determined as the internal winning combination during the RT4 state. In this case, specific control (flag conversion described later) is performed. This flag conversion will be described in detail later.

Further, as shown in FIG. 16, in the RT0 state to the RT3 state, the respective internal winning combinations of the names "F_reach eye lip A" to "F_reach eye lip D" are related to the names "F_BB1" or "F_BB2". Although it may be decided in duplicate with the bonus combination (see Nos. 3 to 6 and 15 to 18), each internal winning combination (replay) of the names "F_reach eye lip A" to "F_reach eye lip D" The role) is not determined as an internal winning role alone. Therefore, in the present embodiment, when the replay combination related to the names "F_reach eye lip A" to "F_reach eye lip D" is determined as the internal winning combination during the RT0 state to the RT3 state (name from the player's point of view). When the symbol combination corresponding to the replay combination related to "F_reach eye lip A" to "F_reach eye lip D" is displayed), the bonus combination (name "F_BB1" or "F_BB2") is determined as the internal winning combination at the same time. It will be done.

Further, the RT5 state, which is the inter-flag state, is a gaming state in which the bonus combination is carried over as the internal winning combination as described above. Therefore, as shown in FIG. 17A, in the internal lottery table referred to in the RT5 state, the carry-over bonus combination is always determined as the internal winning combination. Further, as shown in FIG. 17B, in the internal lottery table referred to in the bonus state, the internal winning combination according to any of the names "F_RB combination 1" to "F_RB combination 4" is always won ( "Out of place" won't win).

[Correspondence table between internal winning combination and symbol combination (winning combination) (symbol combination determination table)]
Next, with reference to FIGS. 18 to 23, a correspondence table (symbol combination determination table) between the internal winning combination and the symbol combination will be described. The symbol combination determination table defines the correspondence between various internal winning combinations and symbol combinations (combinations) that can be displayed on the effective line (center line) associated with each internal winning combination. That is, when the internal winning combination is determined, the type of symbol combination that can be displayed on the valid line (type of display combination that can be won) is uniquely determined.

The various data described in the symbol combination column in each symbol combination determination table is for identifying the symbol combination that is permitted to be displayed along the effective line set over the left reel 3L, the middle reel 3C, and the right reel 3R. It is data. The relationship between each name described in the symbol combination (display combination) column and the specific symbol combination is shown in the winning operation flag storage area of FIGS. 28 to 30 described later.

Further, the "○" mark described in the symbol combination determination table indicates a symbol combination (combination) that can be displayed on the effective line in the determined internal winning combination, that is, a display combination that can win a prize. For example, when the internal winning combination "F_chili lip" is determined, as shown in FIGS. 18 and 19, the combination names "C_maintenance lip A_01" to "C_maintenance lip G_01" and "C_chili lip A_01" to "C_chili lip" are determined. The symbol combination related to "D_01" can be stopped and displayed. It should be noted that the symbol combination determination table does not specify the case where the "internal winning combination" is "off", but this is all the symbols defined by the symbol combination tables shown in FIGS. 18 to 23. Indicates that the display of combinations is not allowed.

In the pachislot machine 1 of the present embodiment, the main control circuit 90 (main CPU 101) has different stop controls depending on the internal winning combination and the gaming state, and when a predetermined combination is determined as the internal winning combination, FIGS. The rotation stop control of the left reel 3L, the middle reel 3C, and the right reel 3R is performed so that the corresponding symbol combinations shown in FIG. 23 can be displayed. In the correspondence table shown in FIGS. 18 to 23, all the symbol combinations that can be displayed for the determined internal winning combination are listed by "○", but the symbols marked with "○" are listed. Even if it is a combination, it may not be displayed.

In the present embodiment, there is a function of changing the stop control (for example, the symbol to be preferentially pulled in) according to the combination of symbols that can be stopped and displayed and the current game state, and "○" is given because of the symbol to be preferentially drawn. Even the marked combination of symbols may not be displayed. The correspondence between the types of internal winning combinations and the actually displayed symbol combinations will be described with reference to FIGS. 24 and 25 described later.

[Correspondence between the winning combination in the non-flag state and the symbol combination displayed as stopped]
Here, with reference to FIG. 24, the correspondence between the internal winning combination and the symbol combination displayed as stopped in the gaming state (non-flag state) excluding the flag state will be described. Note that FIG. 24 shows the correspondence between various internal winning combinations that can be determined in the non-flag state and a symbol combination (abbreviation) that is stopped and displayed when each internal winning combination is determined (some combinations are omitted). It is a figure. The name of the symbol combination described in FIG. 24 is the "abbreviation" described in the content column shown in the winning operation flag storage area of FIGS. 28 to 30 described later.

In the pachi-slot machine 1 of the present embodiment, a so-called “pushing order combination” is provided in which the symbol combinations displayed differ according to the order (pushing order) of the player's stop operations. The symbol combination associated with the "correct answer in push order" shown in FIG. 24 is a symbol combination that is advantageous for the player among the symbol combinations displayed according to the push order, and is referred to as "incorrect answer in push order". The associated symbol combination is a symbol combination that is disadvantageous to the player among the symbol combinations displayed according to the pressing order. When notifying a stop operation that is advantageous to the player, the correct push order is notified, and if the stop operation is performed according to the notification, the symbol combination associated with the "push order correct answer" is displayed. Further, even in the ART gaming state, an incorrect push order may be notified, but the details thereof will be described later.

In addition, in this embodiment, for a part of the push order combination, the push order that is the correct answer is shown at the end of the name. Specifically, the last "1st" in the name of the internal winning combination means that the correct push order is that the first stop operation (the first stop operation performed) is for the left reel 3L. The end "2nd" of the name of the internal winning combination means that the push order that is the correct answer is that the first stop operation is for the middle reel 3C, and the end "3rd" of the name of the internal winning combination is the correct answer. The push order means that the first stop operation is for the right reel 3R. In addition, the end "123" of the name of the internal winning combination means that the correct push order is "left, middle, right", and the end "132" of the name of the internal winning combination is the correct answer. Means that the push order is "left, right, middle", and the last "213" in the name of the internal winning combination means that the correct push order is "middle, left, right". The ending "231" of the name of the internal winning combination means that the correct push order is "left, right, middle".

Further, in the following, the stop operation order when the first stop operation is performed on the left reel 3L, specifically, the push order of "left, middle, right" and "left, right, middle" is changed to ". Also called "forward push". Further, in the following, the stop operation order when the first stop operation is performed on the middle reel 3C or the right reel 3R, specifically, "middle, left, right", "middle, right, left", The pressing order of "right, middle, left" and "right, left, middle" is also referred to as "irregular pressing".

In the present embodiment, as shown in FIG. 24, the internal winning combination “F_Chillilip” is a pressing order combination in which the symbol combinations displayed according to the pressing order are different, and when the pressing order is the correct answer, the abbreviation “F_Chillilip” is used. Any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to "Chillilip" (see FIG. 28 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed. When the internal winning combination "F_chililip" is determined, as shown in FIGS. 18 to 23, the combination names "C_chililip A_01", "C_chililip B_01" or "C_chililip C_01" (abbreviation "single chili lip") Alternatively, "double chili lip": corresponding to the abbreviation "chili lip (no triple)" in FIG. 28 described later) can be displayed, but the combination names "C_chili lip D_01" to "C_1 certain chili lip D_01" (abbreviation). "Triple chili lip": Corresponding to the abbreviation "chili lip (triple)" in FIG. 28 described later), the symbol combination cannot be displayed. That is, the internal winning combination "F_chili lip" is a combination in which the symbol combination related to the abbreviation "triple chili lip" cannot be displayed.

In addition, both the internal winning combinations "F_certain chili lip" and "F_1 certain chili lip" are push order combinations with different symbol combinations displayed according to the push order, and if the push order is correct, the abbreviation "chili lip" is used. Any of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the above (see FIG. 28 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed. When the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, the symbol combination related to the abbreviation "triple chili lip" can be displayed as shown in FIGS. 18 to 23. That is, the internal winning combinations "F_certain chili lip" and "F_1 certain chili lip" are roles that can display the symbol combination related to the abbreviation "triple chili lip".

In addition, the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" are push order combinations with different symbol combinations displayed according to the push order, and are abbreviated when the push order is correct. One of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations (see FIGS. 28 and 29 described later) related to the "reach eye lip" is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed.

In the present embodiment, the order of pressing the correct answers at the time of winning the internal winning roles "F_chili lip", "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_reach eye lip D" Is to perform the first stop operation on the left reel 3L. Therefore, for example, in a game in which the internal winning combination "F_reach eye lip A" is determined, when the player performs the first stop operation on the left reel 3L, the abbreviation is changed to "reach eye lip". The symbol combination is stopped and displayed. The present invention is not limited to this, and the internal winning combinations "F_chili lip", "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_reach eye lip D" are used at the time of winning. The order of pressing the correct answers can be set arbitrarily.

In addition, both the internal winning combinations "F_maintenance lip A" and "F_maintenance lip B" are not push order combinations, and are shown in the symbol combinations related to the abbreviation "replay" regardless of the push order (see FIG. 28 described later). Any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line.

In addition, the internal winning combinations "F_maintenance lip_1st" to "F_maintenance lip_3rd" are all push order combinations in which the symbol combinations displayed according to the push order are different, and if the push order is correct, they are abbreviated. Among the symbol combinations related to "replay" (see FIG. 28 described later), any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations (see FIG. 28 described later) related to the abbreviation "RT2 transition lip" is an effective line. It is displayed along with.

In addition, the internal winning combinations "F_RT3 rip_1st" to "F_RT3 rip_3rd" are all push order combinations in which the symbol combinations displayed according to the push order are different, and when the push order is correct, the abbreviation "RT3" is used. The symbol combination related to "Transition Lip" (see FIG. 28 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed.

In addition, the internal winning combinations "F_RT4 rip_123" to "F_RT4 rip_3rd" are all push order combinations in which the symbol combinations displayed according to the push order are different, and when the push order is correct, the abbreviation "RT4" is used. The symbol combination related to "Transition Lip" (see FIG. 28 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 18 to 23 among the symbol combinations related to the abbreviation "replay" (see FIG. 28 described later) is along the effective line. Is displayed.

In addition, the internal winning combinations "F_3 choice bell_1st" to "F_3 choice bell_3rd" are all push order combinations in which the symbol combinations displayed according to the push order are different, and if the push order is correct, they are abbreviated. The symbol combination related to the "bell" (see FIG. 19 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, the symbol combination related to the abbreviation "bell spilled eyes" (see FIG. 28 described later) or the symbol combination related to the abbreviation "first piece" (see FIG. 30 described later) is used. Is displayed.

Further, the internal winning combination "F_common bell" is not a pressing order combination, and can be displayed as shown in FIGS. 18 to 23 of the symbol combinations (see FIG. 29 described later) related to the abbreviation "bell" regardless of the pressing order. Any of the various symbol combinations is displayed along the effective line. Further, neither of the internal winning combinations "F_sabo 1" and "F_sabo 2" is a pushing order, and FIG. 18 of the symbol combination (see FIG. 30 described later) relating to the abbreviation "cactus" regardless of the pushing order. ~ Any of the displayable symbol combinations shown in FIG. 23 is displayed along the effective line.

Further, the internal winning combination "weak cherry" is not a pressing order, and can be displayed as shown in FIGS. 18 to 23 of the symbol combinations (see FIG. 30 described later) related to the abbreviation "weak cherry" regardless of the pressing order. Any of the various symbol combinations is displayed along the effective line. In addition, the internal winning combinations "F_strong chili 1" and "F_strong chili 2" are not push order combinations, and are among the symbol combinations related to the abbreviation "strong cherry" regardless of the push order (see FIG. 30 described later). Any of the displayable symbol combinations shown in FIGS. 18 to 23 is displayed along the effective line.

[Correspondence between the winning combination in the state between flags and the symbol combination displayed as stopped]
Next, with reference to FIG. 25, the correspondence between the internal winning combination and the symbol combination displayed as stopped in the inter-flag state will be described. Note that FIG. 25 is a diagram showing the correspondence between the internal winning combination and the symbol combination displayed as stopped in the inter-flag state (some combinations are omitted), and in particular, the bonus combination (some combinations are omitted) during the inter-flag state. It is a figure which shows whether or not it is possible to display the symbol combination (combination name "C_BB1" or "C_BB2") which concerns on BB combination).

In the correspondence table of FIG. 25, the "○" mark described in the "whether or not BB is established" column indicates that the symbol combination related to the BB combination can be displayed, and the "x" mark indicates the symbol combination related to the BB combination. Indicates that is not displayable. If the symbol combination related to the BB combination cannot be displayed, the symbol combination related to the combination determined to overlap with the bonus combination as the internal winning combination is displayed. For example, when the internal winning combination "F_BB1 + F_Chillilip" is won (when the internal winning combination "F_BB1" and the internal winning combination "F_Chillilip" are duplicated), as shown in FIG. 25, the internal winning combination "F_BB1" It is possible to stop and display the symbol combination related to, and the symbol combination related to the internal winning combination "F_Chillilip" is stopped and displayed.

Further, in the inter-flag state, when the symbol combination related to the BB combination cannot be displayed and the symbol combination related to the combination determined to overlap with the bonus combination is displayed, the push described with reference to FIG. 24 Only the symbol combination at the time of correct answer may be displayed, or only the symbol combination at the time of incorrect answer may be displayed.

For example, when the internal winning combination "F_BB1 + F_3 selection bell_1st" is won, as shown in FIG. 25, the symbol combination related to the internal winning combination "F_BB1" cannot be stopped and displayed, so that the internal winning combination "F_3 selection bell_1st" cannot be stopped and displayed. The symbol combination related to "" is stopped and displayed, but at this time, only the symbol combination related to the abbreviation "bell" displayed when the push order is correct is displayed, and the abbreviation "bell spilled eye" displayed when the push order is incorrect is displayed. Alternatively, the symbol combination related to the "first piece" may not be displayed (see FIG. 24). Further, for example, when the internal winning combination "F_BB1 + F_RT3 rip_1st" is won, only the symbol combination related to the abbreviation "replay" displayed when the push order is incorrect can be displayed, and the abbreviation "RT3" displayed when the push order is correct is displayed. The symbol combination related to the "transition lip" may be made invisible (see FIG. 24).

In the inter-flag state, as shown in FIG. 25, one of the bonus combination (BB combination) and the internal winning combination "off", "F_special 1", "F_special 2" and "F_special 3" If the determinations are duplicated, the symbol combination related to the BB combination can be stopped and displayed.

[Reel stop initialization table]
Next, the reel stop initial setting table will be described with reference to FIG. The reel stop initial setting table defines the correspondence between the internal winning combination and various data used in the reel stop control process described later.

The reel stop initial setting table shown in FIG. 26 defines the correspondence between the internal winning combination (small winning combination winning number) and the attraction priority table selection table number, attraction priority table number, and stop table number. In addition, in FIG. 26, the reference game state and the name of the internal winning combination are also shown.

The pull-in priority table selection table number and the pull-in priority table number are data used in the selection process of the pull-in priority table. For example, if the pull-in priority table number corresponding to the stop table number is specified in the reel stop initial setting table, it corresponds to the pull-in priority table number specified in the pull-in priority table (see FIG. 27 described later). Data related to the priority of the display combination can be acquired. On the other hand, if the attraction priority table number corresponding to the stop table number is not specified in the reel stop initialization table, the attraction priority table selection table (not shown) is referred to and the attraction priority table selection table number is set. The corresponding pull-in priority table number is determined.

Here, the reel stop control (method for determining the stop symbol position) in the pachi-slot machine 1 of the present embodiment will be briefly described. In the present embodiment, after the stop operation is detected by the stop switch, the reel stop control is performed so that the rotation of the corresponding reel stops within 190 msec. Specifically, any one of the number of sliding pieces "0" to "4" is added to the value of the symbol counter corresponding to the corresponding reel when the stop operation is detected, and the value corresponds to the obtained value. The symbol position is determined as the symbol position at which the rotation of the reel stops (hereinafter, referred to as "scheduled stop position"). The symbol position corresponding to the value of the symbol counter corresponding to the corresponding reel when the stop operation is detected is the symbol position where the rotation of the reel is started (hereinafter, referred to as "stop start position").

That is, the number of sliding pieces is the amount of rotation of the reel from the time when the stop operation is detected by the stop switch until the rotation of the corresponding reel is stopped. In other words, it is the number of symbols that pass through the middle region of the corresponding reel of the reel display window 4 in the period from the detection of the stop operation by the stop switch to the stop of the rotation of the corresponding reel. This is grasped by the value of the symbol counter updated after the stop operation is detected by the stop switch.

With reference to a stop table (not shown), the number of sliding pieces is acquired according to the stop start position of each reel. In the present embodiment, the number of sliding pieces is acquired based on the stop table, but this is tentative, and the acquired number of sliding pieces does not immediately determine the scheduled stop position of the reel. In the present embodiment, if there is a more appropriate number of sliding pieces than the number of sliding pieces acquired based on the stop table (hereinafter referred to as “sliding piece number determination data”), the pull-in priority table (described later) will be described later. Refer to FIG. 27) to change the number of sliding pieces. Then, the sliding piece number determination data is referred to for determining the search order when comparing the priorities of each symbol from the stop start position to the symbol position four ahead, which is the maximum number of sliding pieces.

[Pull-in priority table]
Next, the pull-in priority table will be described with reference to FIG. 27. The attraction priority table is the attraction data (winning operation flag data) for each type of the winning operation flag storage area (see FIGS. 28 to 30 described later) in each of the drawing priority table numbers “00” to “05”. ) And its predetermined priority.

The pull-in priority table is used to search whether or not a more appropriate number of sliding pieces exists in addition to the number of sliding pieces obtained based on the stop table (not shown). The priority order is data that defines the order in which the symbols are preferentially stopped and displayed (pulled in) among the types of symbol combinations (winning operation flags) related to winning. Further, in FIG. 27, for convenience of explanation, the combination name of the winning operation flag is described in the column of the drawing data (winning operation flag data), but in the actual drawing priority table, each drawing data is the winning prize described later. As shown in the operation flag storage area (see FIGS. 28 to 30 described later), it is represented by 1-byte data, and a unique symbol combination (winning operation flag) is assigned to each bit in the 1-byte data. ..

In the reel stop control of the present embodiment, first, the number of sliding pieces is acquired based on the stop table (not shown). However, if there is a more appropriate number of sliding pieces in addition to the number of sliding pieces based on the priority, the number is changed to the appropriate number of sliding pieces. That is, in the present embodiment, the more appropriate number of sliding pieces is determined based on the priority of the symbol combination that allows the stop display by the internal winning combination, regardless of the number of sliding pieces acquired by the stop table.

In the present embodiment, the stop display (pull-in) of the symbol combination having the higher priority is performed with priority over the stop display of the symbol combination having the lower priority.

Further, in the present embodiment, as shown in FIG. 27, not only the priority of the symbol combination (winning operation flag) is different according to the attraction priority table number, but also the number of priority divisions is different. Specifically, when the attraction priority table number is "00", the number of priority divisions is 5, and when the attraction priority table number is "01" or "04", the priority order is set. Let the number of divisions be 4. If the pull-in priority table number is "02" or "03", the number of priority divisions is 2, and if the pull-in priority table number is "05", the number of priority divisions is set. Let be 3.

Here, the priority when the pull-in priority table number is "00" will be described, and the description of the priority in the other pull-in priority table numbers will be omitted. When the pull-in priority table number is "00", the priority "1" (highest priority) includes the combination names "C_9 sheets A_01", "C_1 certain chili lip C_01", "C_1 certain chili lip D_01" and The pull-in data corresponding to "C_RT3 lip_01" is specified.

When the pull-in priority table number is "00", the priority "2" includes the combination names "C_strong 2 sheets C_01" to "C_strong 2 sheets C_09", "C_weak 2 sheets B_01" to "C_weak". Corresponds to "2 sheets B_03", "C_3 sheets E_01", "C_3 sheets E_02", "C_9 sheets F_01" to "C_9 sheets F_03", "C_1 certain chili lip B_01", "C_chili lip D_01" and "C_chili lip C_01". The pull-in data is specified.

When the pull-in priority table number is "00", the priority "3" includes the combination names "C_1 sure chili lip A_01", "C_chili lip A_01", "C_chili lip B_01" and "C_maintenance lip E_01" to "C_maintenance lip E_01". The pull-in data corresponding to "C_maintenance lip E_04" is specified.

When the pull-in priority table number is "00", the priority "4" includes the combination names "C_SP1_01", "C_SP2_01", "C_reach eye lip P_01", "C_reach eye lip P_02", and "C_reach". Eye Lip O_01 "," C_Reach Eye Lip O_02 "," C_Reach Eye Lip N_01 "," C_Reach Eye Lip N_02 "," C_Reach Eye Lip M_01 "," C_Reach Eye Lip M_02 "," C_Reach Eye Lip N_02 " L_01 "to" C_reach eye lip L_03 "," C_reach eye lip K_01 "to" C_reach eye lip K_03 "," C_reach eye lip J_01 "," C_reach eye lip I_01 "to" C_reach eye lip I_09 " , "C_reach eye lip H_01" to "C_reach eye lip H_03", "C_reach eye lip G_01", "C_reach eye lip F_01", "C_reach eye lip F_02", "C_reach eye lip E_01", " C_reach eye lip D_01 "," C_reach eye lip D_02 "," C_reach eye lip C_01 "to" C_reach eye lip C_03 "," C_reach eye lip B_01 "," C_reach eye lip B_02 "," C_reach Eye Lip A_01 "," C_Maintenance Lip F_01 "," C_Maintenance Lip F_02 "," C_Maintenance Lip D_01 "to" C_Maintenance Lip D_04 "," C_Maintenance Lip C_01 "to" C_Maintenance Lip C_03 "," C_Maintenance Lip C_03 " The pull-in data corresponding to "Rip B_01", "C_Maintenance Lip B_02" and "C_Maintenance Lip A_01" is specified.

Further, the attraction data corresponding to the combination names "C_BB1" and "C_BB2" is defined in the priority "5" (lowest priority) when the attraction priority table number is "00".

<Structure of storage area provided in main RAM>
Next, the configurations of various storage areas provided in the main RAM 103 will be described with reference to FIGS. 28 to 35.

[Hit request flag storage area and winning operation flag storage area]
First, the configuration of the winning request flag storage area (internal winning combination storage area) and the winning operation flag storage area (display combination storage area) will be described with reference to FIGS. 28 to 30. In the present embodiment, the hit request flag storage area (flag data storage area, winning flag data storage area) and the winning operation flag storage area (winning flag data storage area) have the same configuration.

In the present embodiment, the hit request flag storage area is composed of the hit request storage areas 0 to 11 each represented by 1 byte of data, and the winning operation flag storage area is each represented by 1 byte of data. It is composed of storage areas 0 to 11. The data stored in each storage area of the hit request flag storage area and the winning operation flag storage area is only the 1-byte data in the "data" column in FIGS. 28 to 30, but in FIGS. 28 to 30, , For convenience of explanation, the symbol combination of each reel associated with the bit of each storage area (in the figure, the symbol of the left reel 3L, the symbol of the middle reel 3C, and the symbol of the right reel 3R are described in this order). The name (combination name) and abbreviation, as well as the number of medals to be paid out are also described.

When "1" is stored in a predetermined bit in each of the hit request flag storage areas 0 to 11, it indicates that the internal winning combination corresponding to the predetermined bit has won the internal winning. Further, when "1" is stored in a predetermined bit in each of the winning operation storage areas 0 to 11, it indicates that the display combination (winning operation flag) corresponding to the predetermined bit has won a prize. That is, when "1" is stored in the predetermined bit, it indicates that various symbol combinations of the internal winning combinations corresponding to the predetermined bit are displayed on the effective line.

Further, in the hit request flag storage area and the winning operation flag storage area, as shown in FIGS. 28 to 30, a plurality of symbol combinations (combinations) are assigned to one bit (flag) in each storage area. Some are. That is, for such a flag, it means that there are a plurality of symbol combinations (combinations that can win a prize) that can be stopped and displayed.

For example, the winning request storage area 5 and the winning operation storage area 5 have a symbol combination "cactus 2"-"white 7"-"hat" (combination name "C_maintenance lip C_01") and a symbol combination "cactus 2". -"Chile Top 1"-"Hat" (combination name "C_maintenance lip C_02") and symbol combination "cactus 2-"-"cactus 2-"-"hat" (combination name "C_maintenance lip C_03") Three symbol combinations are assigned. Therefore, when "1" is stored in bit 5 of the hit request storage area 5, it indicates that the combination of these three symbols can be stopped and displayed on the effective line. Further, when "1" is stored in bit 5 of the winning operation storage area 5, it indicates that any one of these three symbol combinations is displayed on the valid line.

[Carryover storage area]
Next, the configuration of the carry-over combination storage area will be described with reference to FIG. 31. In the present embodiment, the carry-over combination storage area is composed of a 1-byte data storage area.

When the internal winning combination "F_BB1" or "F_BB2" is determined as a result of the internal lottery, the internal winning combination (BB combination) is stored in the carry-over combination storage area as a carry-over combination. The carry-over combination stored in the carry-over combination storage area is retained without being cleared until the corresponding symbol combination is displayed on the valid line. Further, while the carry-over combination is stored in the carry-over combination storage area, the carry-over combination is stored in the winning request storage area in addition to the internal winning combination determined by the internal lottery.

[Game status flag storage area]
Next, the configuration of the game state flag storage area will be described with reference to FIG. 32. The game state flag storage area is composed of a 1-byte data storage area. In the present embodiment, as shown in FIG. 32, a unique bonus type or RT type is assigned to each bit in the game state flag storage area.

When "1" is stored in a predetermined bit in the game state flag storage area, it indicates that the bonus game or RT corresponding to the predetermined bit is being operated. For example, when "1" is stored in bit 0 of the game state flag storage area, the big bonus "BB" is being operated, indicating that the game state is the BB game state. Further, for example, when "1" is stored in bit 3 of the game state flag storage area, it indicates that the game state is the RT3 state.

[Operation stop button storage area]
Next, the configuration of the operation stop button storage area will be described with reference to FIG. 33. The operation stop button storage area is composed of a 1-byte data storage area, and stores an operation stop button flag consisting of 1 byte. In the operation stop button flag, the operation state of the stop button is assigned to each bit.

For example, when the left stop button 17L is the stop button pressed this time, that is, the operation stop button, "1" is stored in bit 0 of the operation stop button storage area. Further, for example, when the left stop button 17L is a stop button that has not yet been pressed, that is, an effective stop button, "1" is stored in bit 4. The main CPU 101 distinguishes between the stop button pressed this time and the stop button that has not yet been pressed, based on the data stored in the operation stop button storage area.

[Press order storage area]
Next, the configuration of the pressing order storage area will be described with reference to FIG. 34. The press order storage area is composed of a 1-byte data storage area, and stores a press order flag consisting of 1 byte.

In the pressing order flag, each bit is assigned the type of pressing order of the stop button. For example, when the pressing order of the stop buttons is "left, middle, right", "1" is stored in bit 0 of the pressing order storage area.

[Design code storage area]
Next, the configuration of the symbol code storage area will be described with reference to FIG. 35. In the present embodiment, each of the symbol code storage areas is composed of symbol code storage areas 0 to 11 represented by 1 byte of data. The symbol code storage area has the same configuration as the hit request flag storage area and the winning operation flag storage area (see FIGS. 28 to 30).

In the symbol code storage area, "1" is stored in the bit corresponding to the symbol combination that can be stopped on the effective line. After all the reels are stopped, the symbol code corresponding to the display combination (winning operation flag) is stored in the symbol code storage areas 0 to 11.

[Relationship between internal winning combination and various sub-flags]
In the general game state and the ART game state, various data tables are referred to in various lottery by the main control circuit 90, but as a parameter used at this time, in this embodiment, not only the internal winning combination but also the internal winning combination is supported. Various parameters having different names (hereinafter, referred to as "sub-flag (first sub-flag)", "sub-flag EX (second sub-flag)", and "sub-flag D") are also used. Therefore, in the present embodiment, the main control circuit 90 performs a process of converting the internal winning combination into various sub-flags (see the sub-flag conversion process, the flag conversion process, and the sub-flag compression process in FIG. 104, which will be described later). In the present embodiment, a sub flag is set in the start command as information (communication parameter) regarding the internal winning combination, and is transmitted from the main control circuit 90 to the sub control circuit 200.

Here, with reference to FIGS. 36 and 37, the correspondence between the internal winning combination and various sub-flags will be described. FIG. 36 is a diagram showing the correspondence relationship between the internal winning combination (small winning combination winning number) and various sub-flags, and FIG. 37 is a diagram showing the correspondence relationship between the internal winning combination (special prize winning number) and the sub-flags.

In the flag conversion process of the present embodiment, first, a plurality of internal winning combinations belonging to the same type are combined into one sub-flag. In the present embodiment, as shown in FIG. 36, by this flag conversion process, 32 types of internal winning combinations (small winning combination winning numbers) related to the small winning combination and the replay winning combination are converted into 18 types of sub-flags (“01” to “18”. : Flag data) is converted. For example, the internal winning combination "F_maintenance rip_1st (10: small winning combination number)" to "F_maintenance rip_3rd (12)" are grouped into the sub-flag "pushing order rip 1 (09: flag data)". The sub-flag "Loss (00)" is assigned to the internal winning combination "Loss".

Further, in the flag conversion process of the present embodiment, as shown in FIG. 36, 19 types of sub-flags ("00" to "18") including the sub-flag "loss (00)" are replaced with 9 types of sub-flag EX ("00"). "-" 08 ": flag data). Therefore, in this conversion process, the sub-flag data can be further compressed. At this time, in the present embodiment, the sub flag is converted into the sub flag EX by lottery (flag conversion lottery). Specifically, it is converted as follows.

The sub-flag "Loss (00)" is converted to the sub-flag EX "Loss (00)" regardless of the result of the flag conversion lottery, and the sub-flag "Double chili lip (01)" is converted to the sub-flag "Double chili lip (01)" regardless of the result of the flag conversion lottery. It is converted to the sub flag EX "replay (01)".

When the sub-flag "triple chili lip A (02)" and the sub-flag "triple chili lip B (03)" are won in the flag conversion lottery (in the case of "with conversion" described later), the sub-flag EX "fixed combination (06)" Alternatively, it is converted to "triple chili lip (07)", and if the flag conversion lottery is not won (in the case of "no conversion" described later), it is converted to the sub-flag EX "replay (01)".

The sub-flags "reach-eye lip 1 (04)" to "reach-eye lip 4 (07)" are converted to the sub-flag EX "fixed combination (06)" or "reach-eye lip (08)" when the flag conversion lottery is won. If the flag conversion lottery is not won, it is converted to the sub-flag EX "replay (01)".

The sub-flags "replay (08)" and "push order rip 1 (09)" to "push order rip 3 (11)" are converted to the sub-flag EX "replay (01)" regardless of the result of the flag conversion lottery. The sub-flags "push order bell (12)" and "common bell (13)" are converted to the sub-flag EX "bell (02)" regardless of the result of the flag conversion lottery.

The sub-flags "cactus (14)", "weak cherry (15)" and "strong cherry (16)" are the sub-flags EX "cactus (03)" and "weak cherry (04)" regardless of the result of the flag conversion lottery, respectively. "And" strong cherry (05) ". Further, the sub-flags "reach eye 1 (17)" and "reach eye 2 (18)" are converted into the sub-flag EX "miss (00)" regardless of the result of the flag conversion lottery.

As described above, in the present embodiment, the sub-flags "triple chili lip A (02)", "triple chili lip B (03)" and "reach eye lip 1 (04)" to "reach eye lip 4 (07)" are substantially used. ) ”Is the target of the flag conversion lottery. The lottery table used for the above-mentioned flag conversion lottery will be described in detail later.

Further, in the flag conversion process of the present embodiment, as shown in FIG. 36, nine types of sub-flags EX (“00” to “08”) are converted into seven types of sub-flags D (“00” to “06”). The flag. Therefore, in this conversion process, the sub-flag data can be further compressed. In this conversion process, lottery is not performed, and the sub-flag EX and the sub-flag D are associated with each other for conversion as follows.

The sub-flag EX "loss (00)", "replay (01)" and "bell (02)" are converted into the sub-flag D "loss (00)". The sub-flag EX "cactus (03)" is converted to the sub-flag D "cactus (01)", the sub-flag EX "weak cherry (04)" is converted to the sub-flag D "weak cherry (02)", and the sub-flag EX "strong". "Cherry (05)" is converted to subflag D "strong cherry (03)".

Further, the sub flag EX "fixed combination (06)" is converted to the sub flag D "fixed combination (04)", and the sub flag EX "triple chili lip (07)" is converted to the sub flag D "triple chili lip (05)". Then, the sub flag EX "reach eye lip (08)" is converted into the sub flag D "reach eye lip (06)".

Further, in the flag conversion process of the present embodiment, as shown in FIG. 37, both the internal winning combination "F_BB1 (01: special prize winning number)" and "F_BB2 (02)" are converted into the sub-flag "BB". ..

[Gameability at the time of sub-flag EX conversion]
Here, an example of the process of converting the above-mentioned internal winning combination into the sub-flag and the sub-flag EX and the playability at the time of sub-flag EX conversion will be described with reference to FIGS. 38A and 38B. FIG. 38A is a diagram showing a flag conversion process when the internal winning combination “F_certain chili lip” or “F_1 certain chili lip” is determined, and FIG. 38B is a diagram showing the internal winning combination “F_reach eye lip A” to “F_”. It is a figure which shows the flag conversion process when any of "reach eyes lip D" is determined.

In the pachislot machine 1 of the present embodiment, any one of the internal winning combinations "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_reach eye lip D" is independent during the RT4 game state. If it is determined as an internal winning combination, a flag conversion lottery will be performed. Then, in the present embodiment, when the flag conversion lottery is won, a special privilege (for example, addition of the number of ART games or CT winning) is given.

For example, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, as shown in FIG. 38A, the internal winning combination "F_certain chili lip" and "F_1 certain chili lip" are each sub-flag "3 consecutive". It is converted into "chili lip A (02)" and "triple chili lip B (03)".

Next, the sub-flags "triple chili lip A (02)" and "triple chili lip B (03)" become the sub-flag EX "triple chili lip (07)" or "fixed combination (06)" when the flag conversion lottery is won. Will be converted. On the other hand, if the flag conversion lottery is not won, both the sub-flags "triple chili lip A (02)" and "triple chili lip B (03)" are converted to the sub-flag EX "replay (01)". ..

As described in FIG. 24, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won, the symbol combination related to the abbreviation "triple chili lip" is displayed when the push order is correct, and the push order is irregular. When the answer is correct, the symbol combination related to the abbreviation "Replay" is displayed. Therefore, in the present embodiment, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined and the flag conversion lottery is won, the internal winning combination "F_certain chili lip" and "F_1 certain chili lip" Are all treated as the combination of the sub-flag EX "triple chili lip (07)" or "fixed combination (06)".

Then, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is converted into the sub-flag EX "triple chili lip (07)" or "fixed combination (06)" by this flag conversion process, the abbreviation "triple chili lip" is abbreviated. Information for displaying the symbol combination related to "Chile Lip" is notified (for example, information to the player to aim at the Chile symbol by pushing forward is notified). On the other hand, in this flag conversion process, when the flag conversion lottery becomes non-winning and the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is converted to the sub-flag EX "replay (01)", the abbreviation is changed to "replay". Information for displaying the symbol combination is notified (for example, a pressing order other than forward pressing (irregular pressing) is notified).

Further, for example, when any of the internal winning combinations “F_reach eye lip A” to “F_reach eye lip D” is determined, as shown in FIG. 38B, the internal winning combinations “F_reach eye lip A” to “F_reach eye lip A” to “ "F_reach eye lip D" is converted into subflags "reach eye lip 1 (04)" to "reach eye lip 4 (07)", respectively.

Next, the sub-flags "reach-eye lip 1 (04)" to "reach-eye lip 4 (07)" become the sub-flag EX "reach-eye lip (08)" or "fixed combination (06)" when the flag conversion lottery is won. Will be converted. On the other hand, when the flag conversion lottery is not won, the sub-flags "reach-eye lip 1 (04)" to "reach-eye lip 4 (07)" are converted into the sub-flag EX "replay (01)".

As described in FIG. 24, when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is won, the symbol combination related to the abbreviation "reach eye lip" is used when the push order is correct. Is displayed, and when the push order is incorrect, the symbol combination related to the abbreviation "replay" is displayed. Therefore, in the present embodiment, when any one of the internal winning combination "F_reach eye lip A" to "F_reach eye lip D" is determined and the flag conversion lottery is won, the internal winning combination "F_reach eye" is determined. All of "Rip A" to "F_reach eye lip D" are treated as the combination of the sub-flag EX "reach eye lip (08)" or "fixed combination (06)".

Then, when the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" are converted into, for example, the sub-flag EX "reach eye lip (08)" or "fixed combination (06)" by this flag conversion process. , Information for displaying the symbol combination related to the abbreviation "reach eye lip" is notified (for example, information to the player to aim at the symbol "white 7" by pushing forward is notified). On the other hand, in this flag conversion process, when the flag conversion lottery becomes non-winning and the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" are converted into the sub-flag EX "replay (01)", it is abbreviated. Information for displaying the symbol combination related to "replay" is notified (for example, a pressing order other than forward pressing (irregular pressing) is notified).

Further, in the present embodiment, in the flag conversion process shown in FIG. 38A or 38B, when the player wins the flag conversion lottery and performs the stop operation according to the notification, it relates to the abbreviation "triple chili lip" or "reach eye lip". The symbol combination is stopped and displayed on the valid line, and a special privilege is given. In this granting process, a special privilege is given to the player according to the fact that the pachislot 1 wins the flag conversion lottery, but the abbreviation "3" is given to the player. By displaying the symbol combination related to "Ren Chiri Lip", it is possible to feel that a special privilege has been given.

In order to enhance the playability of pachislot, it may be preferable that the appearance frequency of the symbol combination to which the privilege is given is different depending on the state rather than being constant. Since the stop control (displayed symbol combination) differs depending on the type of internal winning combination, as a method of changing the appearance frequency of the symbol combination to which the privilege is given depending on the state, the winning probability of the internal winning combination is changed. A method is also conceivable (in pachislot 1, the winning probability of the internal winning combination can be different depending on the presence or absence of the bonus operation and the RT state. Therefore, for example, as the RT state corresponding to the ART game state, only the RT4 state is considered. Instead, a method of providing another RT state such as an RT6 state or an RT7 state is also conceivable). However, since the opportunity to make the winning probability of the internal winning combination different (the opportunity to shift to the RT state) is limited, this method lacks flexibility from the viewpoint of improving playability (interestingness).

On the other hand, in the pachislot machine 1 of the present embodiment, in addition to the internal lottery for determining the internal winning combination, the flag conversion lottery and the notification based on the lottery result are performed without changing the winning probability of the internal winning combination. , The appearance frequency of the symbol combination to which the privilege is given can be flexibly changed according to the state. That is, in a state where it is easy to win the flag conversion lottery, the appearance frequency of the symbol combination to which the privilege is given can be increased, and conversely, in a state where it is difficult to win the flag conversion lottery, the appearance of the symbol combination to which the privilege is given appears. The frequency can be reduced.

<Gameability during general game state>
Next, the flow of the game during the general game state will be described with reference to FIGS. 39A to 39C. In the pachislot machine 1 of the present embodiment, the gaming state shifts from the normal gaming state to the CZ during the general gaming state, and then the gaming state shifts from the CZ to the ART gaming state, whereby the general gaming state (non-ART gaming state) ) To the ART gaming state (see FIGS. 14A and 14B).

FIG. 39A is a diagram showing a flow of a game when the game state shifts from the normal game state to the CZ in the general game state. As shown in FIG. 39A, the normal gaming state has a low probability state and a high probability state as a lottery state of CZ. The low-probability state and the high-probability state are states in which the expectations for winning the CZ lottery performed during the normal gaming state are different from each other, the low-probability state is the state in which it is difficult to win the CZ lottery, and the high-probability state is the CZ. It is in a state where it is easy to win a lottery. Then, when the CZ lottery performed in the game during the normal game state is won, the game state shifts from the normal game state to the CZ.

In the pachislot machine 1 of the present embodiment, a plurality of chance zones of "CZ1", "CZ2" and "CZ3" are provided as CZs (chance zones). CZ1 to CZ3 are chance zones in which the expectation of winning an ART lottery performed in a game during CZ is different from each other, CZ3 is a chance zone in which an ART lottery is always won, and CZ1 and CZ2 have a predetermined probability. This is a chance zone to win the ART lottery. In the CZ lottery performed in the game during the normal game state, not only the winning / non-winning of the CZ but also the type of CZ (any of CZ1 to CZ3) to be transferred at the time of winning is determined (see FIG. 41 described later).

FIG. 39B is a diagram showing a game flow when the game state shifts from the general game state CZ1 and CZ2 to the ART game state. Both CZ1 and CZ2 are composed of a first half portion and a second half portion. The first half is a period for promoting the rank of the expectation of winning the ART lottery performed in the game during CZ, and the second half is a predetermined production of the lottery result of the ART lottery based on the rank (in this embodiment, the character). It is a period to be notified by (battle production by).

In CZ1, six modes (modes 1 to 6) are prepared as ranks, and the higher the mode, the higher the expectation of winning the ART lottery. In the first half of CZ1, the game is continuously played for the period of the first predetermined number of games (for example, 12 games at the maximum), and the mode promotion lottery is performed based on the internal winning combination. Then, in the first game of the latter half of CZ1, ART lottery is performed based on the mode promoted in the first half (the mode at the end of the first half).

In addition, in CZ2, points of 10 levels are prepared as ranks, and the higher the points, the higher the expectation of winning the ART lottery. In the first half of CZ2, games are continuously played for a period of a second predetermined number of games (for example, a maximum of 15 games), and points are promoted by lottery based on the internal winning combination. Then, in the first game of the second half of CZ2, the ART lottery is performed based on the points promoted in the first half (points at the end of the first half).

In the latter half of CZ1, a battle effect in which the ally character and the enemy character A play against each other is performed, and in the latter half of CZ2, a battle effect in which the ally character and the enemy character B play against each other is performed. This battle effect is performed over a period of a third predetermined number of games (for example, a maximum of 4 games). In addition, the victory or defeat of the battle production is managed (determined) based on the result of the ART lottery, and if the ART lottery is won, the ally character wins in the battle production, and if it is not the ART lottery, the battle The enemy character wins in the production.

Further, in each latter half of CZ1 and CZ2 (during the battle production), ART lottery is performed every game based on the internal winning combination. Then, when the ART lottery is won, the result of the battle effect is rewritten. For example, if a so-called "rare" role is determined as an internal winning role during a battle production, an ART lottery is performed, and the result of the battle production is rewritten based on the result.

In CZ1 and CZ2, if the ART is not won, the player is defeated in the battle effect in the latter half, and basically, the game state shifts to the normal game state after that. On the other hand, in CZ1 and CZ2, when the ART is won, the battle effect in the latter half is won, and then the game state shifts from the CZ to the normal ART via the ART preparation state. In addition, in this embodiment, a freeze may occur in the game of the first half of CZ1 and CZ2, and in that case, the game state is changed from CZ via the ART preparation state, and CT (additional addition) instead of normal ART is performed. Move to the chance zone).

FIG. 39C is a diagram showing a game flow when the game state shifts from the general game state CZ3 to the ART game state. The CZ3 is continuously played for a period of a fourth predetermined number of games (for example, 17 games at the maximum). Then, in CZ3, ART lottery is performed every game based on the internal winning combination.

The CZ3 ends when the ART lottery is won, and after the next game, the game state shifts from the CZ3 to the CT (additional chance zone) via the ART preparation state. Further, in CZ3, a freeze may occur, and even in that case, the game state shifts from CZ3 to CT (additional chance zone) via the ART preparation state after the next game. On the other hand, in CZ3, when the game period (fourth predetermined number of games) of CZ3 elapses without winning the ART lottery, the game state shifts from CZ3 to normal ART via the ART preparation state. That is, in the present embodiment, CZ3 is a chance zone in which the transition to the ART gaming state is confirmed.

<Various data tables used during the general game state>
Subsequently, with reference to FIGS. 40 to 45, various data tables used in the lottery process relating to the playability performed during the general game state will be described. The various data tables described below are stored in the main ROM 102.

Further, in the various data tables shown below, information on the lottery value is conceptually shown. "0" in the data table means that the lottery value corresponding to the winning probability "0%" is specified, and "extremely low" means the lottery corresponding to the winning probability "0% to less than 1%". It means that the value is specified, and "extremely low" means that the lottery value corresponding to the winning probability "1% to less than 10%" is specified. In addition, "low" in the data table means that a lottery value corresponding to a winning probability of "10% to less than 30%" is specified, and "medium" means a winning probability of "30% to less than 60%". It means that the lottery value corresponding to "" is specified, and "high" means that the lottery value corresponding to the winning probability "60% to less than 80%" is specified. Further, "extremely high" in the data table means that a lottery value corresponding to a winning probability of "80% to less than 99%" is defined, and "extremely high" means a winning probability of "99% to less than 99%". It means that the lottery value corresponding to "less than%" is specified, and "confirmed" means that the lottery value corresponding to the winning probability "100%" is specified.

Then, in the various data tables shown below, the random number register 1 of the random number circuit 110 sequentially subtracts the lottery random number values extracted from the predetermined numerical value range (0 to 65535) by the specified lottery values. , Internal lottery is performed by determining whether or not the result of subtraction is negative (whether or not so-called "digits" have occurred). In the present embodiment, an example in which the lottery value is subtracted from the lottery random value to determine the winning / non-winning in the lottery process related to the playability performed during the general game state has been described, but the present invention is limited to this. Instead, the lottery value is added to the extracted random number value for lottery, and it is determined whether or not the addition result exceeds 65536 (whether or not a so-called "digit overflow" has occurred), and the winning / non-winning is determined. May be good.

[Normal medium and high probability lottery table]
First, with reference to FIGS. 40A and 40B, a normal medium-high probability lottery table used in the transition lottery of the lottery state (low probability and high probability) of CZ will be described. In the pachislot machine 1 of the present embodiment, not only the transition lottery of the lottery state of the CZ is performed based on the internal winning combination in each game, but also at the end of the bonus, the end of the CZ, the end of the ART, etc. Transition of lottery state A lottery is performed. FIG. 40A is a configuration diagram of a normal middle-high probability lottery table that is referred to every game during the normal game state, and FIG. 40B is a normal middle-high that is referred to at the time of setting change, bonus end, CZ, ART end, etc. It is a block diagram of the probability lottery table. The name of the internal winning combination shown in FIG. 40A corresponds to the name of the sub-flag described above.

The normal medium-high probability lottery table shown in FIG. 40A shows each combination of the current CZ lottery state and the internal winning combination, the lottery result (low probability / high probability) of the CZ lottery state after the transition, and each lottery result. The correspondence with the associated lottery value information is specified.

As is clear from the normal medium-high probability lottery table shown in FIG. 40A, when the current lottery state of CZ is low probability, when the internal winning combination is the combination corresponding to the sub-flag "weak cherry", the CZ The lottery state is likely to shift to a high probability. On the other hand, when the current CZ lottery state has a high probability, when the internal winning combination is a combination corresponding to any of the subflags "common bell", "cactus", "weak cherry" and "strong cherry". In addition, the lottery state of CZ is maintained with high probability.

In the normal medium-high probability lottery table shown in FIG. 40B, each situation when referring to the table, the lottery result (low probability / high probability) of the lottery state of CZ after the transition, and the lottery associated with each lottery result. Define the correspondence with the value information. As is clear from the normal medium-high probability lottery table shown in FIG. 40B, the lottery state of CZ always shifts to a high probability at the end of the bonus.

[CZ lottery table]
Next, the CZ lottery table used in the CZ lottery will be described with reference to FIGS. 41A and 41B. FIG. 41A is a configuration diagram of a CZ lottery table used when performing a CZ lottery based on an internal winning combination during a normal game state, and FIG. 41B shows a CZ pullback at the time of CZ failure or ART end, for example. It is a block diagram of the CZ lottery table used when performing the CZ lottery whether or not to perform. The name of the internal winning combination shown in FIG. 41A corresponds to the name of the sub-flag described above.

The CZ lottery table shown in FIG. 41A shows each combination of the current CZ lottery state and the internal winning combination, the winning / non-winning (lottery result) of CZ1, CZ2, and CZ3, and the lottery associated with each lottery result. Specify the correspondence with the value information. As is clear from the CZ lottery table shown in FIG. 41A, when the current CZ lottery state is in the high probability, the CZ lottery is won more than in the case where the current CZ lottery state is in the low probability. The probability is high.

In the CZ lottery table shown in FIG. 41B, the correspondence between the winning / non-winning (lottery result) of CZ1, CZ2, and CZ3 at the time of CZ failure or the end of ART and the information of the lottery value associated with each lottery result. To specify. At the time of CZ failure (when the ART lottery in CZ1 and CZ2 is not won) or at the end of the ART game state, the CZ pullback lottery is performed using this CZ lottery table.

[CZ1 medium mode up lottery table]
Next, with reference to FIG. 42, the CZ1 medium mode-up lottery table used in the CZ1 mode-up lottery performed in the first half of CZ1 will be described. FIG. 42 is a configuration diagram of a mode-up lottery table in CZ1. The name of the internal winning combination shown in FIG. 42 corresponds to the name of the sub-flag described above.

The CZ1 medium mode-up lottery table has a correspondence relationship between each combination of the current mode and the internal winning combination, the mode-up lottery result (winning / non-winning), and the lottery value information associated with each lottery result. To specify. As shown in FIG. 44A described later, in CZ1, the higher the mode (the higher the value of the mode), the higher the probability of winning the ART lottery, and when the mode goes up to the mode 6, the ART lottery is always won.

The lottery result "mode 1 UP" in FIG. 42 means that the mode of CZ1 is raised by one step, and the lottery result "mode 2 UP" means that the mode of CZ1 is raised by two steps. Therefore, for example, in a situation where the current mode is mode 2, if the lottery result "mode 2 UP" is won, the mode of CZ1 goes up from mode 2 to mode 4. Further, for example, when the lottery result "mode 6UP_freeze occurrence" is won, the freeze occurs, and the winning of the ART lottery and the granting of CT are determined.

[CZ2 middle point lottery table]
Next, the CZ2 middle point lottery table used in the CZ2 point-up lottery performed in the first half of the CZ2 will be described with reference to FIG. 43. FIG. 43 is a configuration diagram of a point lottery table in CZ2. The name of the internal winning combination shown in FIG. 43 corresponds to the name of the sub-flag described above.

The CZ2 middle point lottery table shows the correspondence between each combination of the current points and the internal winning combination, the result of the point-up lottery (winning / non-winning), and the lottery value information associated with each lottery result. Prescribe. As shown in FIG. 44B described later, in CZ2, the higher the points, the higher the probability of winning the ART lottery, and when the points rise to "point 10", the ART lottery is always won. The lottery result "point 2 UP" in FIG. 43 means that "2" is added to the points of the current CZ2. For example, in a situation where the current point is "2", the lottery result "point 2 UP" If you win "Point 2 UP", the points of CZ2 will increase from "2" to "4". Further, for example, when the lottery result "point 10UP_freeze occurrence" is won, the freeze occurs, and the winning of the ART lottery and the granting of CT are determined.

[ART lottery table in CZ]
Next, the ART lottery table in CZ used in the ART lottery performed during CZ will be described with reference to FIGS. 44A-44C and 45. Note that FIG. 44A is a configuration diagram of an ART lottery table in CZ (for CZ1) used in the first game of the latter half of CZ1, and FIG. 44B is an ART in CZ used in the first game of the latter half of CZ2. It is a block diagram of the lottery table (for CZ2), and FIG. 44C is a block diagram of the ART lottery table in CZ (common to CZ1, CZ2 for the latter half of the battle) used in the latter half of CZ1 and CZ2. Further, FIG. 45 is a configuration diagram of an ART lottery table (for CZ3) in CZ used in the ART lottery executed in CZ3. The names of the internal winning combinations shown in FIGS. 44C and 45 correspond to the names of the sub-flags described above.

The ART lottery table in CZ (for CZ1) shown in FIG. 44A defines the correspondence between the current mode, the result of the ART lottery (presence or absence of winning), and the information of the lottery value associated with each lottery result. .. Further, the ART lottery table (for CZ2) in CZ shown in FIG. 44B shows the correspondence between the current points, the result of the ART lottery (presence or absence of winning), and the information of the lottery value associated with each lottery result. Prescribe.

As is clear from the ART lottery table in CZ (for CZ1) and the ART lottery table in CZ (for CZ2), in CZ1 and CZ2, the higher the rank (mode or point) of the first half, the easier it is to win the ART lottery.

The ART lottery table in CZ (common to CZ1 and CZ2 for the latter half of the battle) shown in FIG. 44C includes the internal winning combination, the result of the ART lottery (presence or absence of winning), and the lottery value information associated with each lottery result. Prescribe the correspondence of. As is clear from the ART lottery table in CZ (common to CZ1 and CZ2 for the latter half of the battle), in the latter half of CZ1 and CZ2, the role corresponding to the rare role (sub-flags "weak cherry", "cactus" or "strong cherry". ) Is determined as the internal winning combination, and the ART lottery is won with a predetermined probability.

The ART lottery table (for CZ3) in CZ shown in FIG. 45 shows each combination of the number of digestion games of CZ3 and the internal winning combination, the result of ART lottery (presence or absence of winning), and the lottery associated with each lottery result. Define the correspondence with the value information. As is clear from the ART lottery table in CZ (for CZ3), in the present embodiment, when the ART lottery is won in CZ3, the CT is always won.

<Playability during normal ART>
Next, the flow of the game during the game ART will be described with reference to FIGS. 46A and 46B. In the pachi-slot machine 1 of the present embodiment, as described above, normally ART and CT are provided as ART gaming states (see FIGS. 14A and 14B), and the inside of CT is used as an additional chance zone. Therefore, in the present embodiment, the player usually plays a game during ART with the aim of shifting to CT.

[Mode of transition from normal ART to CT]
FIG. 46A is a diagram showing a mode of transition of the gaming state from normal ART to CT. In the pachislot machine 1 of the present embodiment, as shown in FIG. 46A, when the CT lottery performed during the normal ART is won, the gaming state shifts from the normal ART to the CT. As shown in FIG. 46A, the pachislot machine 1 of the present embodiment is provided with an ART level and a CT lottery state as parameters that affect various lottery normally performed during ART.

As the ART level, four levels of levels 1 to 4 are provided, and this ART level is controlled (determined) mainly based on the number of continuous (digestion) games during normal ART. Then, the ART level affects the determination of the CT lottery state, the flag conversion lottery during the normal ART, which will be described later, and the like.

The CT lottery state is provided with four stages of low probability, normal, high probability, and ultra-high probability, and the CT lottery state is controlled mainly based on the ART level and the internal winning combination during normal ART ( It is determined. Then, the CT lottery state affects the CT lottery performed during the normal ART, the flag conversion lottery during the normal ART described later, and the like.

[Flag conversion during normal ART]
As described above, in the pachislot machine 1 of the present embodiment, during the RT4 state, that is, during the ART gaming state, the internal winning combinations "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_" When any one of "Reach Eye Lip D" is independently determined as an internal winning combination, a flag conversion lottery is performed, and a special privilege (for example, an addition of the number of ART games or a CT winning) is given according to the lottery result. .. FIG. 46B is a diagram showing an outline of a method of flag conversion lottery usually performed during ART.

In the present embodiment, as shown in FIG. 46B, the flag conversion lottery is performed in the normal ART with reference to the ART level and the CT lottery state. As a result, when the flag conversion lottery is won, a special privilege is given, and the symbol combination related to the abbreviation "triple chili lip" and the symbol combination related to the abbreviation "reach eye lip" are stopped and displayed on the effective line. Navigation (for example, notification of information to aim at a predetermined symbol by pushing forward) is performed. On the other hand, if the flag conversion lottery is not won, navigation (for example, notification of a push order other than forward push) is performed to stop and display the symbol combination related to the abbreviation "replay" on the effective line.

Then, when the player performs a stop operation according to this notification (navigation), the symbol combination according to the notification content is stopped and displayed on the effective line. Specifically, when the flag conversion lottery is won, the symbol combination related to the abbreviation "triple chili lip" and the symbol combination related to the abbreviation "reach eye lip" are stopped and displayed on the effective line and are not displayed in the flag conversion lottery. In the case of winning, the symbol combination related to the abbreviation "replay" is stopped and displayed on the effective line.

<Various data tables normally used during ART>
Next, with reference to FIGS. 47 to 51, various data tables normally used in the lottery process during ART will be described. The various data tables described below are stored in the main ROM 102.

[Flag conversion lottery table during ART]
FIGS. 47A and 47B are configuration diagrams of a flag conversion lottery table during ART used in a flag conversion lottery normally performed during ART.

In the pachi-slot machine 1 according to the present embodiment, the flag conversion lottery during normal ART is performed in two stages. Specifically, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won, the first stage flag conversion lottery is first performed, and if the first stage flag conversion lottery is won, then The second stage flag conversion lottery is performed. Then, when the second-stage flag conversion lottery is won, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is converted into the sub-flag EX "triple chili lip". On the other hand, if the first-stage flag conversion lottery or the second-stage flag conversion lottery is non-winning, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is converted to the sub-flag EX "replay". (Treat as a normal replay role). If any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is won, only the second stage flag conversion lottery is performed.

FIG. 47A is a configuration diagram of the flag conversion lottery table during ART used in the first stage flag conversion lottery, and FIG. 47B is a configuration diagram of the flag conversion lottery table during ART used in the flag conversion lottery of the second stage. is there.

The flag conversion lottery table during ART shown in FIG. 47A has an internal winning combination (“F_certain chili lip” or “F_1 certain chili lip”) and a lottery result of the first stage flag conversion lottery (no conversion / with conversion (provisional)). And the correspondence relationship with the lottery value information associated with each lottery result is defined.

The flag conversion lottery table during ART shown in FIG. 47B shows each combination of the internal winning combination, the ART level, and the CT lottery state, the lottery result of the second stage flag conversion lottery (without conversion / with conversion), and each lottery result. The correspondence with the lottery value information associated with is specified. In the game until the CT is won once in the normal ART, the table in the "First time (until the CT is won once)" column of the item "ART level" in FIG. 47B is referred to.

In the present embodiment, as shown in FIGS. 47A and 47B, in the first-stage and second-stage flag conversion lottery using each of the flag conversion lottery tables during ART, a random number value (0 to 0) having a probability denominator of "256". A lottery is performed using 255). Therefore, in the present embodiment, the above-mentioned two-step flag conversion lottery can be regarded as substantially the same lottery as the case where one lottery is performed using a random number value whose probability denominator is "65536".

In recent pachislot machines, the lottery (ART lottery, etc.) related to ball ejection, which was conventionally performed on the sub control board 72 side (hereinafter referred to as "sub side"), is performed on the main control board 71 side (hereinafter referred to as "main side"). It is required to do. However, since the capacity of the storage means (main ROM 102) on the main side is limited to a small capacity, there is a demand for a mechanism that enables lottery without impairing game playability while suppressing an increase in processing capacity.

Regarding this point, in the pachi-slot machine 1 of the present embodiment, the lottery having the probability denominator of "256" can be performed in two stages, so that the lottery having the probability denominator of "65536" can be performed. The increase in capacity on the side can be suppressed. Further, in the second stage lottery, since the ART level, the CT lottery state, etc. are referred to, not only the internal winning combination but also the flag conversion lottery according to the current state can be performed, and as a result, various playability can be achieved. You can perform a flag conversion lottery with you.

[ART level determination table]
FIGS. 48A and 48B are block diagrams of an ART level determination table used when determining an ART level. The ART level determination process is performed at the time of winning the ART when the transition to the ART gaming state is decided, and during the normal ART. FIG. 48A is a configuration diagram of an ART level determination table used at the time of winning ART, and FIG. 48B is a configuration diagram of an ART level determination table normally used during ART.

The ART level determination table shown in FIG. 48A defines the correspondence between the ART levels 1 to 4 (lottery results) and the lottery value information associated with each ART level. In the present embodiment, if a freeze occurs at the time of winning the ART, the ART level 2 is determined as the ART level.

The ART level determination table shown in FIG. 48B is a lottery associated with each combination of the current ART level and the number of elapsed (digested) games of the normal ART, various ART levels of the migration destination, and each ART level of the migration destination. Specify the correspondence with the value information. Further, the ART level determination table shown in FIG. 48B corresponds to each combination of the current ART level and the number of elapsed games of the normal ART at the time of CT entry, various ART levels of the migration destination, and each ART level of the migration destination. The correspondence with the information of the lottery value obtained is specified. That is, during normal ART, not only the ART level can be shifted when the number of elapsed (digested) games of normal ART reaches a predetermined number of games, but also the ART level can be changed at the timing of entering CT during normal ART. It becomes possible to migrate.

[Normal ART medium and high probability lottery table]
FIG. 49 is a block diagram of a normal ART medium-high probability lottery table used when determining a CT lottery state during normal ART.

The normal ART medium-high probability lottery table has a correspondence relationship between each combination of the current CT lottery state and the internal winning combination, various CT lottery states of the migration destination, and lottery value information associated with each CT lottery state. Prescribe. The name of the internal winning combination shown in FIG. 49 corresponds to the name of the sub-flag described above.

As is clear from the normal ART medium and high probability lottery table, the internal winning combination corresponding to the sub-flag "triple chili lip (triple chili lip A and triple chili lip B)" and the sub-flag "reach eye lip (reach eye lip 1-4)". If you win, the CT lottery state is likely to shift (fall) to a "low probability". However, as shown in FIG. 50 described later, when the internal winning combination corresponding to the sub-flags "triple chili lip" and "reach eye lip" is won, even if the CT lottery state falls, the CT lottery will be performed. The structure is such that it always wins.

[CT lottery table during ART]
FIG. 50 is a block diagram of a CT lottery table during ART used in a CT lottery normally performed during ART.

The CT lottery table during ART shows each combination of the current CT lottery state and the internal winning combination, various lottery results (non-winning / normal CT / high probability CT) of the CT lottery, and a lottery associated with each lottery result. Define the correspondence with the value information. The name of the internal winning combination shown in FIG. 50 corresponds to the name of the sub-flag described above.

In the present embodiment, the sub-flags "cactus", "weak cherry", "strong cherry", "triple chili lip (triple chili lip A and triple chili lip B)", and "reach eye lip (reach eye lip)" are used as internal winning roles. When the combination corresponding to "1 to 4)" or "BB" is determined, in the CT lottery processing using the CT lottery table during ART, the CT lottery using the random value in the range where the probability denominator is "256" Is done. In addition, if an internal winning combination other than these roles (for example, a combination corresponding to the sub-flags "replay", "common bell", "pushing order bell", etc.) is determined as the internal winning combination, CT during ART In the CT lottery process using the lottery table, CT lottery using random values in the range where the probability denominator is "65536" is performed.

In the pachislot machine 1 of the present embodiment, two types of CTs called "normal CT" and "high probability CT" are provided as CTs. Normal CT and high-probability CT have different expectations for the number of ART games added during CT (addition chance zone), and high-probability CT is a CT in which a larger number of ART games are more likely to be added than normal CT. (See FIG. 55 below).

[Normal ART extra lottery table]
FIG. 51 is a configuration diagram of an additional lottery table during normal ART, which is used in an additional lottery for the number of ART games performed during normal ART. The name of the internal winning combination shown in FIG. 51 corresponds to the name of the sub-flag described above.

Normally, the additional lottery table during ART defines the correspondence between the internal winning combination, various lottery results (non-winning / additional 10G to 300G) of the additional lottery, and the lottery value information associated with each lottery result.

<Playability during CT>
Next, the flow of the game during CT will be described with reference to FIGS. 52A to 52C. It should be noted that FIGS. 52A and 52B are mainly diagrams showing an outline of the game flow during CT at the time of winning the sub-flag EX "triple chili lip", and FIG. 52C shows an outline of the flag conversion process performed during CT. It is a figure.

[Game content during CT]
In the pachislot machine 1 of the present embodiment, in CT, one set of eight games (8 games) is played. During the CT period, an additional lottery for the number of ART games is performed based on the internal winning combination for each game. Then, when the additional lottery is won, the unit game number (game number) of the CT game is not subtracted, while when the additional lottery is non-winning, the unit game number (game number) of the CT game is not subtracted. Number) is subtracted. Therefore, during the CT period, the CT does not end in the game in which the number of ART games is added, and the CT ends when the game in which the number of ART games is not added is performed eight times in the same set. ..

Further, in the present embodiment, as shown in FIGS. 52A and 52B, when the sub-flag EX "triple chili lip" is won during the CT period, that is, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won. However, if the flag conversion lottery is won, the CT games 8 times per set are reset (stocked). Then, the set of the reset (stocked) CT game is started after the set of the CT game is completed.

For example, in the same set, after the unit game that is not a winning lottery is played 7 times in the lottery for adding the number of ART games, the CT ends when the CT game in which the number of ART games is not added is played once. If the sub-flag EX "Triple Chili Lip" is won, the CT game is reset. As a result, after the CT game is reset, the CT will not end until the unit game, which is a non-winning unit game, is performed eight times in the additional lottery for the number of ART games. Therefore, the game period of CT becomes long enough to win the sub-flag EX "triple chili lip".

[Flag conversion during CT]
Next, with reference to FIG. 52C, a method of flag conversion lottery performed during CT will be described. As described above, in the present embodiment, when the sub-flag EX "triple chili lip" is won during the CT period (internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won, and the flag conversion lottery is won. Then, CT is reset (stocked). Further, as shown in the CT flag conversion lottery table of FIG. 54 described later, if the internal winning combination “F_certain chili lip” or “F_1 certain chili lip” is won during CT, the flag conversion lottery is always won (sub-flag EX “sub-flag EX”. It will always be converted to "triple chili lip"). That is, in the present embodiment, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won during CT, the CT is always reset.

Further, in the flag conversion lottery when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is won, the flags are based on three types of flag conversion tables (tables 0 to 2). The winning probability of the conversion lottery is controlled. Specifically, as shown in FIG. 52C, table 0 is a flag conversion table having the lowest probability of being converted to the sub-flag EX "reach eye lip", and table 1 is converted to the sub-flag EX "reach eye lip". It is a flag conversion table having the next lowest probability, and table 2 is a flag conversion table having the highest probability of being converted to the sub-flag EX “reach eye lip”. If the sub-flag EX "reach eye lip" is won during CT, CT is newly added as shown in the lottery table for adding the number of sets in CT described later in FIG. 56.

Further, in the present embodiment, in normal CT, as shown in FIG. 52C, the flag conversion table is determined based on the ART level. On the other hand, in high-probability CT, table 0 is always determined as the flag conversion table regardless of the ART level.

<Various data tables used during CT>
Next, various data tables used in the lottery process performed during CT will be described with reference to FIGS. 53 to 56. The various data tables described below are stored in the main ROM 102.

[Table during CT lottery table]
FIG. 53 is a configuration diagram of a CT table lottery table used when determining a table to be used for the flag conversion lottery from the three-stage flag conversion tables (tables 0 to 2).

The lottery table during CT shows the correspondence between each state such as the ART level and the type of CT to be executed, the type of the flag conversion table (tables 0 to 2), and the lottery value information associated with each type. Prescribe. The table lottery table during CT is referred to when it is decided to win the CT lottery and shift to CT, or at the start of CT.

[Cut flag conversion lottery table]
FIG. 54 is a configuration diagram of a flag conversion lottery table during CT used in a flag conversion lottery performed during CT.

The flag conversion lottery table during CT includes an internal winning combination (one of "F_certain chili lip", "F_1 certain chili lip" and "F_reach eye lip A" to "F_reach eye lip D") and each flag conversion table ( The correspondence between the lottery result (without conversion / with conversion) of the flag conversion lottery in Tables 0 to 2) and the lottery value information associated with each lottery result is defined. As is clear from the flag conversion lottery table during CT, if the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is won during CT, the flag conversion lottery is always won (sub-flag EX "triple chili lip" is always won). Will be converted).

[Additional lottery table during CT]
FIG. 55 is a configuration diagram of an additional lottery table during CT used in an additional lottery for the number of ART games performed during CT.

The additional lottery table during CT is associated with each combination of the current CT state and the internal winning combination, various lottery results of the additional lottery (non-winning / additional 10 games / ... / additional 300 games), and each lottery result. The correspondence with the lottery value information is specified. The name of the internal winning combination shown in FIG. 55 corresponds to the name of the sub-flag described above, and when a combination other than the internal winning combination (sub-flag) shown in FIG. 55 is internally won, the additional lottery during CT is won. There is nothing to do.

Further, in the additional lottery during the normal CT of the present embodiment, the form of giving the number of additional games changes according to the number of wins of the sub-flag "triple chili lip" (internal winning combination "F_certain chili lip" or "F_1 certain chili lip"). To do.

Specifically, when the number of times the sub-flag "triple chili lip" is won in the same CT set is 1 to 8, it is given by the lottery results "addition_10G" and "addition_20G" shown in FIG. 55. The number of additional games will be 10 games and 20 games, respectively. Therefore, in this case, 10 games can be easily determined as the number of additional games of ART. Further, when the number of winnings of the sub-flag "triple chili lip" in the same CT set is 9 to 16 times, the additional game given by the lottery results "addition_10G" and "addition_20G" shown in FIG. 55. Both numbers will be 20 games. That is, the number of additional games (lottery result) corresponding to the lottery value "extremely high" of the sub-flag "triple chili lip" in FIG. 55 is promoted to 20 games. Therefore, in this case, 20 games can be easily determined as the number of additional games for ART.

Further, when the number of winnings of the sub-flag "triple chili lip" in the same CT set is 17 to 24 times, the additional game given by the lottery results "addition_10G" and "addition_20G" shown in FIG. 55. Both numbers will be 30 games. That is, the number of additional games (lottery result) corresponding to the lottery values "extremely high" and "extremely low" of the sub-flag "triple chili lip" in FIG. 55 is promoted to 30 games. Therefore, in this case, "30 games" can be easily determined as the number of additional games for ART. Further, when the number of winnings of the sub-flag "triple chili lip" in the same CT set is 25 times or more, the number of additional games given by the lottery results "addition_10G" and "addition_20G" shown in FIG. 55. Will both be 50 games. That is, the number of additional games (lottery result) corresponding to the lottery values "extremely high" and "extremely low" of the sub-flag "triple chili lip" in FIG. 55 is promoted to 50 games. Therefore, in this case, "50 games" can be easily determined as the number of additional games for ART.

As described above, in the pachislot machine 1 of the present embodiment, it is possible to increase the number of ART games that can be added by one additional lottery according to the number of times the sub-flag "triple chili lip" is won during CT. Further, as described above, in the present embodiment, as long as the number of ART games is added, the CT does not end, and when the sub-flag EX "triple chili lip" is applied, the CT is reset (stock). Is done. Therefore, in the present embodiment, the player can be expected to increase the additional amount per game as the CT continues, and the interest during the CT can be improved. In addition, the number of winnings of the sub-flag "Triple Chili Lip", which is an opportunity to increase the amount of addition per game, is more than the basic number of games (8 times) for one set of CT (9 times or more). It is possible to prevent an excessive profit from being given to the game, and it is possible to balance the profit between the player and the game store.

In the present embodiment, the number of winnings of the above-mentioned sub-flag "triple chili lip" (internal winning combination "F_certain chili lip" or "F_1 certain chili lip") is the number of times counted in the same CT set. The present invention is not limited to this. For example, a new CT given when a lottery for adding the number of sets performed during CT is won may be included in "in the same CT set".

[Lottery table with additional sets during CT]
FIG. 56 is a configuration diagram of an additional lottery table for the number of sets in CT used in the additional lottery for CT sets performed during CT.

The lottery table for adding the number of sets during CT is a combination of the current CT state and the internal winning combination (sub-flag "reach-eye rip (reach-eye rips 1 to 4)"), and various lottery results of the additional lottery (non-winning / normal). The correspondence between the CT winning / high-probability CT winning) and the lottery value information associated with each lottery result is defined.

As is clear from the additional lottery table for the number of sets during CT, if you win any of the internal winning roles "F_reach eye lip A" to "F_reach eye lip D" during CT, you will definitely win the additional lottery for the CT set. (The CT set is always stocked). The stocked CT set is started after the currently operating CT set is completed.

<Playability in bonus state>
Next, the flow of the game in the bonus state will be described with reference to FIGS. 57A to 57C. FIG. 57A is a diagram showing the flow of the game when the gaming state shifts to the bonus state during the general gaming state (ART non-winning), and FIG. 57B shows the case where the gaming state shifts to the bonus state during normal ART. FIG. 57C is a diagram showing the flow of the game in the above, and FIG. 57C is a diagram showing the flow of the game when the game state shifts to the bonus state during CT.

In the pachislot machine 1 of the present embodiment, as shown in FIGS. 57A to 57C, a normal BB and a special BB are provided as bonus types in terms of playability, and the type of this bonus is determined at the time of transition to the bonus state. Will be done. At this time, if the special BB is determined, the gaming state shifts to CT via the ART preparation state after the end of the bonus state. On the other hand, when the normal BB is determined, the game state of the transition destination differs depending on the state before the transition to the bonus state.

When the gaming state shifts from the general gaming state to the normal BB, as shown in FIG. 57A, in the game during the normal BB, the ART lottery is performed based on the internal winning combination. Then, when the ART lottery is won, the game state shifts to the normal ART via the ART preparation state after the end of the bonus state. In this case, in the game in the bonus state after winning the ART lottery, the number of ART games is added to the lottery.

When the gaming state shifts from the normal ART to the normal BB, as shown in FIG. 57B, a CT lottery is performed at the end of the normal BB. The winning probability of this CT lottery is 50%, and when the winning is done, the gaming state shifts to CT via the ART preparation state after the end of the bonus state. On the other hand, when the CT lottery is not won, the game state shifts to the normal ART via the ART preparation state after the end of the bonus state. In addition, in the game in the bonus state that has been transferred from the normal ART, an additional lottery for the number of ART games is also performed.

When the gaming state shifts from CT to normal BB or special BB, as shown in FIG. 57C, the gaming state shifts to CT via the ART preparation state after the end of the bonus state. In addition, in the game in the bonus state transferred from CT, an additional lottery for the number of ART games is also performed.

<Various data tables used in games in the bonus state>
Subsequently, with reference to FIGS. 58 to 60, various data tables used in the lottery process performed in the game in the bonus state will be described. The various data tables described below are stored in the main ROM 102.

[Bonus type lottery table]
FIG. 58 is a configuration diagram of a bonus type lottery table used when determining a bonus type (normal BB, special BB).

The bonus type lottery table shows each game state (CT and others) before the transition to the bonus state, various lottery results (bonus type: normal BB / special BB), and a lottery value associated with each lottery result. Define the correspondence with information. The bonus type determination process with reference to the bonus type lottery table is performed at the start of the bonus state.

[Lottery table with the number of ART games added during the bonus]
FIG. 59 is a configuration diagram of a lottery table for adding the number of ART games in the bonus used in the ART lottery and the lottery for adding the number of ART games performed in the game in the bonus state.

The lottery table for adding the number of ART games in the bonus is associated with each combination of the current bonus type and the internal winning combination, various lottery results of the additional lottery (non-winning / 5 games / ... / 300 games), and each lottery result. The correspondence with the information of the lottery value obtained is specified.

In the present embodiment, in the ART non-winning state (the state until the ART lottery is won in the normal BB shifted from the general game state), the lottery table for adding the number of ART games during the bonus is used for the ART lottery. Specifically, in the ART non-winning state, when the number of additional games of 1 game or more (50 games or more in the example shown in FIG. 59) is determined by the lottery using the lottery table for adding the number of ART games during the bonus, ART Along with winning the lottery, the corresponding number of games is given as the number of ART games. On the other hand, in the state after winning the ART, the lottery table for adding the number of ART games during the bonus is used only for the lottery for adding the number of ART games.

[CT lottery table at the end of bonus]
FIG. 60 is a configuration diagram of a CT lottery table at the end of the bonus used in the CT lottery performed at the end of the bonus state.

The CT lottery table at the end of the bonus shows each combination of the bonus type (normal BB, special BB) and the game state (during normal CT, high probability CT) before shifting to the bonus state, and various lottery results of the CT lottery (during normal CT, high probability CT). The correspondence between the non-winning / normal CT winning / high-probability CT winning) and the lottery value information associated with each lottery result is defined. As is clear from the CT lottery table at the end of the bonus, for example, if a normal BB is performed during a normal ART, there is a 50% chance of winning the CT at the end of the bonus state.

<Exceptional playability during general game state>
Next, with reference to FIG. 61, an exceptional game flow during the general game state will be described.

In the basic flow of the gaming state in the pachislot machine 1 of the present embodiment, the gaming state shifts from the normal gaming state to the CZ during the general gaming state, and the gaming state shifts to the ART gaming state by winning the ART lottery in the CZ. To do. Then, in the present embodiment, the ART gaming state is realized by notifying in the RT4 state. Further, in the present embodiment, as shown in FIG. 61, the transition control of the RT state is performed according to the symbol combination displayed as stopped.

It should be noted that the symbol combination for shifting the RT state is a stop display according to the player's stop operation order (push order) (see FIG. 24), so that the notification may not be performed. By chance, the RT state may shift to the RT4 state. Further, in the RT4 state, one of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" may be determined, so that even during the general gaming state (non-ART), It is possible to display a reach eye (a symbol combination related to the abbreviation "reach eye lip") to which a special privilege is given.

Therefore, in the pachislot machine 1 of the present embodiment, as shown in FIG. 61, the RT state accidentally shifts to the RT4 state during the general gaming state (non-ART), and the symbol combination related to the abbreviation "reach eye lip" can be displayed. In such a state, the gaming state can be shifted to the ART gaming state (normal ART) without going through the CZ.

More specifically, when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is determined in the general game state and in the RT4 state, a flag conversion lottery is performed. When this flag conversion lottery is won, notification (navigation) for displaying the symbol combination related to the abbreviation "reach eye lip" is performed, and the right of ART is granted. On the other hand, when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is determined in the general game state and in the RT4 state, the flag conversion lottery is not won. Notification is performed to display the symbol combination related to the abbreviation "replay", and control is performed so that the symbol combination related to the abbreviation "reach eye lip" is not displayed.

<Various data tables used for exceptional game control during the general game state>
Next, with reference to FIG. 62, a data table used in the lottery process performed in the exceptional game control in the general game state described above will be described. The data table described below is stored in the main ROM 102.

[Non-ART flag conversion lottery table]
FIG. 62 is a configuration diagram of a non-ART flag conversion lottery table used in a flag conversion lottery performed in a game in the general game state and in the RT4 state.

The non-ART flag conversion lottery table has an internal winning combination ("F_reach eye lip A" to "F_reach eye lip D"), a lottery result of the flag conversion lottery (without conversion / with conversion), and each lottery result. The correspondence with the associated lottery value information is specified.

<Notification function controlled by the main side>
In the conventional pachislot machine, information (navigation) of reel stop operation information (pushing order, etc.) is performed by controlling the sub (sub-control board 72) side during ART. However, since the presence or absence of this notification affects the profit of the player (so-called ball ejection), in recent years, it has been required to perform the notification on the main (main control board 71) side that manages the profit of the player. There is. Therefore, in the pachi-slot machine 1 of the present embodiment, as described above, the information display 6 controlled on the main side is provided with an instruction monitor (not shown) for notifying the information of the stop operation, and is controlled by the main side. A function for notifying information on the reel stop operation is provided.

Here, FIGS. 63A to 63D show the correspondence between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in the pachislot machine 1 of the present embodiment. Note that FIG. 63A is a diagram showing a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in the ART preparation state, and FIG. 63B is a diagram during ART (normal ART or CT). It is a figure which shows the correspondence relationship between the notification (navigation) performed on the main side, and the notification (navigation) performed on the sub side. Further, FIG. 63C is a diagram showing a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the RT5 state (between the BB1 flags), and FIG. 63D is a diagram showing the correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side. It is a figure which shows the correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in (between BB2 flags).

In the present embodiment, as shown in FIGS. 63A to 63D, on the main (main control board 71) side, the information of the reel stop operation is notified by displaying the numerical values of "1" to "11" on the instruction monitor. To do. The numerical values "1" to "11" displayed on the instruction monitor uniquely correspond to the contents of the stop operation notified by each.

Specifically, the numerical values "1" to "3" indicate the types of reels that perform the first stop operation, and the numerical values "1" mean that the first stop operation is performed on the left reel 3L. Then, the numerical value "2" means that the first stop operation is performed on the middle reel 3C, and the numerical value "3" means that the first stop operation is performed on the right reel 3R.

Further, the numerical values "4" to "9" indicate the push order to be notified, and the numerical value "4" means that the push order is "left, middle, right", and the numerical value "5". Means that the push order is "left, right, middle", the numerical value "6" means that the push order is "middle, left, right", and the numerical value "7" is the push order. The order is "middle, right, left", the numerical value "8" means that the pushing order is "right, left, middle", and the numerical value "9" is the pushing order. It means that the order is "right, middle, left".

In addition, the numerical values "10" and "11" respectively notify the bonus combination, and the numerical value "10" is a symbol combination related to the combination name "C_BB1" (design "white 7" -design "white 7"-. The symbol "white 7") is meant, and the numerical value "11" means a symbol combination (symbol "blue 7" -symbol "blue 7" -symbol "blue 7") related to the combination name "C_BB2".

Although the numerical values "1" to "11" notified on the main side (instruction monitor) uniquely correspond to the content of the stop operation to be notified, all players are clear based on the numerical values. It is not always possible to grasp the content of the notification. For example, it may not be possible for some players to grasp the content of the notification simply by displaying the numerical value "6" on the instruction monitor on the main side.

Therefore, in the pachi-slot machine 1 of the present embodiment, the information related to the stop operation of the stop button is notified on the sub side as well as the notification on the main side. Specifically, the display device 11 (projector mechanism 211 and display unit 212) controlled on the sub side is used to notify the information related to the stop operation under the control of the sub side.

For example, when notifying the push order in which the first stop operation is performed on the left reel 3L, the numerical value "1" is displayed on the instruction monitor on the main side, and the left reel in the display screen of the display device 11 is displayed on the sub side. A numerical value "1" is displayed above the 3L to notify that the left reel 3L is the target of the first stop operation. Further, when notifying the push order "middle, left, right", the numerical value "6" is displayed on the instruction monitor on the main side, and the numerical value is displayed above the middle reel 3C in the display screen of the display device 11 on the sub side. "1" is displayed, the numerical value "2" is displayed above the left reel 3L, and the numerical value "3" is displayed above the right reel 3R. Notify that Further, when the internal winning combination "F_BB1" is determined, the numerical value "10" is displayed on the instruction monitor on the main side, and "white 7"-"white 7" is displayed on the display screen of the display device 11 on the sub side. -Displays information about the symbol combination of "White 7" and informs the player of the symbol to be aimed at.

The timing of notification on the main side can be set to any timing as long as it is at least the period of one game in which notification is performed. For example, the main side may be notified at the timing when the player's start operation is detected (accepted), the main side may be notified at the start of reel rotation, and the first stop operation to the third stop operation may be performed. The main side may be notified at the timing when any of the stop operations is detected. On the other hand, the timing of performing the notification on the sub side is preferably at least a timing before the first stop operation. Therefore, in the pachi-slot machine 1 of the present embodiment, notification (navigation) is performed on both the main side and the sub side at the timing when the start operation is detected or the timing when the rotation of the reel starts. As a result, before the player performs the stop operation, the stop operation information is notified on both the instruction monitor on the main side and the display device 11 on the sub side.

In the ART preparation state, as shown in FIG. 63A, notifications (navigation) called "bell navigation", "maintenance lip navigation", "RT3 transition lip navigation" and "RT4 transition lip navigation" are performed by the control of the main side. In "Bell Navi", when the internal winning combination "F_3 choice bell_1st" to "F_3 choice bell_3rd" is decided, the symbol combination (see FIG. 29) related to the abbreviation "bell" is stopped and displayed on the effective line. The push order of is notified. In "Maintenance Lip Navi", when the internal winning combination "F_Maintenance Lip_1st" to "F_Maintenance Lip_3rd" is determined, the symbol combination (see FIG. 28) related to the abbreviation "Replay" is stopped and displayed on the effective line. The push order for is notified. In the "RT3 transition lip navigation", when the internal winning combinations "F_RT3 transition lip_1st" to "F_RT3 transition lip_3rd" are determined, the symbol combination (see FIG. 28) related to the abbreviation "RT3 transition lip" is placed on the effective line. The push order for displaying the stop is notified. Further, in the "RT4 transition lip navigation", when the internal winning combinations "F_RT4 transition lip_123" to "F_RT4 transition lip_3rd" are determined, the symbol combination (see FIG. 28) related to the abbreviation "RT4 transition lip" is effective. The push order for displaying the stop display on the top is notified.

Further, in the ART gaming state (normal ART or CT), as shown in FIG. 63B, the notifications referred to as "Bell Navi", "Maintenance Lip Navi", "RT3 Transition Lip Navi" and "RT4 Transition Lip Navi" are controlled by the main side. (Navigation) is performed. In the game in the ART game state (RT4 state), a flag conversion lottery is performed, and based on the lottery result, a symbol combination related to the abbreviations "triple chili lip", "reach eye lip" or "replay" is displayed. The push order is notified, but this notification is performed only on the sub side, not on the main side.

As mentioned above, since the symbol combination related to the abbreviation "triple chili lip" or "reach eye lip" is related to the granting of special benefits, the presence or absence of notification affects the player's profit (ball output). Although it seems to be given, in reality, in the pachislot machine 1 of the present embodiment, the special privilege is given based on the lottery result of the flag conversion lottery, so that the displayed symbol combination is the given privilege. It does not affect it. Therefore, for example, in the state of winning the flag conversion lottery, even if the symbol combination related to the abbreviation "replay" is stopped and displayed, a special privilege is given. On the other hand, even if the symbol combination related to the abbreviation "triple chili lip" or "reach eye lip" can be stopped and displayed in the state where the flag conversion lottery is not won, no special privilege is given. In the pachislot machine 1 of the present embodiment, when the symbol combination displayed in this way does not affect the profit (ball output) of the player, it is controlled on the sub side without notifying the instruction monitor on the main side. The notification is performed only on the display device 11.

Further, in the RT5 state (inter-flag state), as shown in FIGS. 63C and 63D, information is notified to the player to aim at the symbol combination related to the bonus combination carried over as the internal winning combination. For example, when the internal winning combination "F_BB1" is carried over, as shown in FIG. 63C, a notification (navigation) called "white 7 navigation" is performed by the control of the main side, and the internal winning combination "F_BB2" is performed. "Is carried over, as shown in FIG. 63D, a notification (navigation) called" blue 7 navigation "is performed by the control of the main side.

In "White 7 Navi", the symbol combination corresponding to the internal winning combination "F_BB1", that is, the symbol combination related to the combination name "C_BB1" ("White 7"-"White 7"-"White 7": see FIG. 28). Information on the stop operation for displaying the stop on the valid line is notified. Further, in "Blue 7 Navi", the symbol combination corresponding to the internal winning combination "F_BB2", that is, the symbol combination related to the combination name "C_BB2" ("Blue 7"-"Blue 7"-"Blue 7": FIG. 28 Information on the stop operation for displaying the stop display on the valid line (see) is notified.

In the inter-flag state, when the bonus combination and any of the internal winning combinations "off", "F_special 1", "F_special 2" and "F_special 3" are determined, as described in FIG. 24. , The symbol combination related to the bonus combination (BB combination) can be stopped and displayed on the effective line. However, if the internal winning combination other than the internal winning combination "missing", "F_special 1", "F_special 2" and "F_special 3" and the bonus combination are winning, the symbol combination related to the bonus combination Cannot be stopped and displayed on the valid line. Therefore, in the present embodiment, as shown in FIGS. 63C and 63D, the carried-over bonus combination and the internal winning combination “missing”, “F_special role 1”, “F_special role 2” and “F_special role” Only when any of "3" is the winning, the notification called "white 7 navigation" or "blue 7 navigation" is performed by the control of the main side. Therefore, in the present embodiment, the notification (navigation) called "white 7 navigation" or "blue 7 navigation" controlled by the main side can be performed at an appropriate timing in which the bonus combination can be won.

The pachi-slot machine 1 of the present embodiment is also provided with a function of notifying a bonus by displaying a bonus confirmation screen or turning on a bonus confirmation lamp, for example. Therefore, on the main side, the navigation called "white 7 navigation" or "blue 7 navigation" may be performed only after announcing (bonus notification) that the bonus combination has been determined as the internal winning combination.

As a bonus notification, for example, an effect that is performed over a plurality of game periods (so-called continuous effect) is generally performed, and a bonus confirmation screen is displayed according to the result of this continuous effect. There is. If "White 7 Navi" or the like is performed on the main side during such a continuous production, the result of the continuous production will be known in the middle, which may spoil the interest. Therefore, in the present embodiment, after the bonus notification is made, the main control board 71 is notified (navigation) called "white 7 navigation" or "blue 7 navigation" by the control of the main side.

The method of making it possible for the main side to grasp the timing of the bonus announcement is arbitrary. As one of the methods, when the bonus combination is determined as the internal winning combination, the main control board 71 determines the number of games required until the end of the bonus notification, and after digesting the games of this number of games, "White 7 Navi" or A method of performing notification (navigation) called "blue 7 navigation" can be considered. More specifically, when the main control board 71 determines the number of games required until the end of the bonus notification, the main control board 71 notifies the sub control board 72 of the number of games. The sub-control board 72 controls the production according to the number of games, and displays the bonus confirmation screen at the timing when the games of the number of games are exhausted, so that the timing when the bonus notification is made on the main side can be grasped. Can be done. That is, the main control board 71 counts the number of unit games since the bonus combination is determined as the internal winning combination in a state where the bonus combination has not been carried over, and after the counting result reaches a predetermined number of times, the bonus combination And, when any of the internal winning combination "missing", "F_special role 1", "F_special role 2" and "F_special role 3" is determined as the internal winning combination, "white 7 navigation" or "white 7 navigation" or " Perform "Blue 7 Navi".

Further, as another method, a method of controlling the bonus notification on the main side instead of the sub side can be considered. More specifically, when the main control board 71 determines the bonus combination as the internal winning combination in the state where the bonus combination is not carried over, the main control board 71 determines the effect (at least the number of games required for the effect) to be executed by the display device 11. Notify the sub-control board 72. By executing the effect notified by the sub-control board 72 and displaying the bonus confirmation screen, it is possible to grasp the timing at which the bonus notification is made on the main side.

It should be noted that the main side may be configured to be able to grasp the timing at which the bonus notification is made by a method other than the above two methods. In this case, since the main control board 71 cannot receive the signal from the sub control board 72 or the like, it is necessary to grasp the timing at which the bonus notification is made based on the signal that the main control board 71 can accept. For example, since the main control board 71 can accept the signal associated with the stop operation, when a predetermined stop operation (for example, other than forward pressing) is performed while the bonus combination is determined as the internal winning combination. In addition, a method of notifying a bonus is also conceivable. Specifically, the sub-control board 72 acquires information on the internal winning combination and information on the stop operation from the main control board 71, and gives a bonus notification when the combination of these information is a predetermined combination. By adopting such a bonus notification method, the trigger of the bonus notification can also be grasped by the main control board 71, so that the timing at which the bonus notification is made can be grasped on the main side.

<Explanation of operation of main control circuit>
Next, with reference to FIGS. 64 to 170, the contents of various processes executed by the main CPU 101 of the main control circuit 90 by using the program will be described.

[Processing when power is turned on (reset interrupt)]
First, the power-on (reset interrupt) processing of the pachi-slot machine 1 performed under the control of the main CPU 101 will be described with reference to FIGS. 64 and 65. FIG. 64 is a flowchart showing the procedure at the time of power-on (reset interrupt), and FIGS. 65A to 65C are sources for executing the processes of S2, S7, S8, and S13 in the flowchart, respectively. It is a figure which shows an example of a program. In the power-on (reset interrupt) processing shown in FIG. 64, when the power management circuit 93 detects that the supply of the power supply voltage to the microprocessor 91 has started, the reset signal is sent to the microprocessor 91. It is output to the "XSRST" terminal, and is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

First, the main CPU 101 determines whether or not the power supply monitoring port (power supply monitoring means) is in the ON state (S1).

In S1, when the main CPU 101 determines that the power supply monitoring port is in the ON state (when the determination in S1 is YES), the main CPU 101 repeats the process of S1. The state in which the power supply monitoring port is on is a state in which the power supply voltage (DC + 5V) supplied to the main CPU 101 is not stable.

On the other hand, when the main CPU 101 determines in S1 that the power supply monitoring port is not in the ON state (when the determination in S1 is NO), the main CPU 101 performs an initialization process of the timer circuit 113 (PTC) (S2). In this process, the main CPU 101 initially sets the timer circuit 113. Specifically, the main CPU 101 sets the frequency division ratio in the timer prescaler register (not shown), sets the timer control register (not shown) to interrupt enable, etc., and sets the timer counter (not shown). Set the initial count value.

Next, the main CPU 101 performs initialization processing of the first serial communication circuit 114 (SCU1) between the main control circuit 90 and the sub-control circuit 200, and the second serial communication circuit 115 (SCU2) for the second interface board. Initialization processing is performed (S3). Next, the main CPU 101 performs initialization processing of the random number circuit 110 (RDG) (S4). Next, the main CPU 101 performs a write test of the main RAM 103 (S5).

Next, the main CPU 101 determines whether or not the writing to the main RAM 103 has been normally performed as a result of the writing test (S6).

In S6, when the main CPU 101 determines that the writing to the main RAM 103 has not been performed normally (when the determination in S6 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, in S6, when the main CPU 101 determines that the writing to the main RAM 103 has been normally performed (when the determination in S6 is YES), the main CPU 101 is in the state of the timer control register (not shown) of the timer circuit 113. (S7).

Next, the main CPU 101 determines whether or not the current state is the occurrence timing of the interrupt process based on the acquired state of the timer control register (S8). Specifically, the main CPU 101 determines whether or not 1.1172 ms has elapsed from the start of the timer count based on the acquired state of the timer control register.

In the present embodiment, when the timer time 1.1172 ms is set by the initialization process of the timer circuit 113 in S2, the count process of the CPU built-in timer is started. After that, the status of the timer circuit 113 can be acquired by reading the information of the timer control register (not shown). Then, in the present embodiment, a bit (discrimination bit) capable of discriminating (seeing) whether or not the current state is the occurrence timing of the interrupt process (whether or not it is the timer interrupt state) in the timer control register. ) Is provided.

Therefore, in the process of S7, the main CPU 101 reads the information of the timer control register (not shown), and in the process of S8, the main CPU 101 is in the ON / OFF state of the discrimination bit in the timer control register (not shown). By referring to "1" / "0"), it is determined whether or not the current state is the timing at which the interrupt process occurs. When 1.1172 ms has elapsed from the start of counting by the timer circuit 113 (if the count value of the timer circuit 113 is 0), the discrimination bit is turned on.

In S8, when the main CPU 101 determines that the current state is not the timing at which the interrupt process occurs (when the determination in S8 is NO), the main CPU 101 returns the process to the process of S7 and repeats the processes after S7.

On the other hand, in S8, when the main CPU 101 determines that the current state is the occurrence timing of the interrupt process (when the determination in S8 is YES), the main CPU 101 performs a thumb check process (non-standard) (S9). .. In this process, the main CPU 101 performs a thumb check process of the main RAM 103, and this process is performed in an unspecified work area (see FIG. 12C) in the main RAM 103. Further, the program used in this thumb check process is stored in the non-standard area in the main ROM 102 (see FIG. 12B). The details of the thumb check process will be described later with reference to FIGS. 79 and 80 described later.

Further, in S8, when the main CPU 101 determines that the current state is the occurrence timing of the interrupt process (when the determination in S8 is YES), the main CPU 101 performs the interrupt process described later before the process in S9. The interrupt process (see FIG. 158 described later) is executed. Then, by this interrupt process, a no-operation command is transmitted from the main control circuit 90 (main control board 71) to the sub control circuit 200 (sub control board 72).

After the process of S9, the main CPU 101 determines whether or not the setting key type switch 54 is in the ON state (S10).

In S10, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (when the determination in S10 is YES), the main CPU 101 performs the process of S15 described later. On the other hand, in S10, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (when the determination in S10 is NO), the main CPU 101 determines the thumb check based on the result of the thumb check process in S9. It is determined whether or not the result is normal (S11).

In S11, when the main CPU 101 determines that the thumb check determination result is not normal (when the determination in S11 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, in S11, when the main CPU 101 determines that the thumb check determination result is normal (when the determination in S11 is YES), the main CPU 101 performs the game return process (S12). In this process, the main CPU 101 performs a process of returning the game state to the state before the power failure detection. The details of the game return process will be described later with reference to FIG. 66 described later.

When the determination in S6 or S11 is NO, the main CPU 101 displays the character string "rr" indicating the occurrence of an error on the information display 6 (7-segment LED display) (S13). After that, the main CPU 101 repeats the WDT clearing process (S14).

Here, returning to the process of S10 again, if S10 is a YES determination, the main CPU 101 performs a setting change confirmation process (S15). In this process, the main CPU 101 mainly performs a setting change command generation / storage process at the start of the setting change. The details of the setting change confirmation process will be described later with reference to FIG. 68 described later.

Next, the main CPU 101 performs a RAM initialization process (S16). In this process, the main CPU 101 sets the address "at the time of RAM abnormality or at the start of setting change" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game starts from the start address. Erase (clear) the information up to the final address of the RAM area. Then, after the processing of S16, the main CPU 101 starts the main processing described later (see FIG. 82 described later).

In the present embodiment, the power-on (reset interrupt) processing is performed as described above. Then, the processing of S2 during the power-on (reset interrupt) processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 65A.

In the source program of FIG. 65A, 10 MHz (supply clock is 20 MHz) is set as the CPU clock, 228 is set as the prescaler register set value, and 49 is set as the initial count value. As a result, 1.1172 ms (= 1 / (10 MHz / 288) × 49) is calculated as the timer time (execution cycle) of the interrupt process.

Further, the processes of S7 and S8 during the above-mentioned power-on (reset interrupt) process are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 65B. Specifically, the process of acquiring the state of the timer control register in S7 is executed by the "LD" instruction in FIG. 65B, and the determination process in S8 is executed by the "JBIT" instruction in FIG. 65B. Then, the "LD" command in FIG. 65B and the "JBIT" command in FIG. 65B are repeatedly executed until 1.1172 ms elapses from the start of counting by the timer circuit 113, and 1.1172 ms elapses from the start of counting by the timer circuit 113. , The interrupt request signal is output from the timer circuit 113 to the main CPU 101 via the interrupt controller 112. The main CPU 101, triggered by the input of this interrupt request signal, starts the interrupt process having the first 1.1172 ms cycle after the power is restored.

Since the command related to the game operation is not set in the first 1.1172 ms cycle interrupt process immediately after the power is restored (after the initialization when the power is turned on), the main control circuit 90 to the sub control circuit 200 No operation command is sent. By permitting the interrupt process immediately after the power is restored in this way, the no-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

Further, the data stored in the L register, the H register, the E register, the D register, and the C register are set in the communication parameters 1 to 5 constituting the non-operation command transmitted in this communication operation, respectively, when the power is restored. Will be done. Therefore, in the present embodiment, the data set in the communication parameters 1 to 5 of the non-operation command transmitted in the first interrupt process after the power is restored is made different (undefined) each time the power is restored. Can be done. That is, the sum value (BCC) of the non-operation command transmitted in the interrupt process immediately after the power is restored (after the initialization when the power is turned on) can be made different for each power restoration. In this case, fraudulent acts such as goto can be suppressed.

Further, the processing (interrupt prohibition processing) of S13 during the power-on (reset interrupt) processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 65C. .. Then, control when displaying the error code "rr" on the 2-digit 7-segment LED in the information display 6 is executed by one source code "LDW HL, 100H * cZCHRAR + cBX_PAYSEG" as shown in FIG. 65C. Then, the output operation of the 7-segment common output data and the output operation of the 7-segment cathode output data to the 2-digit 7-segment LED are performed at the same time.

That is, in the pachi-slot machine 1 of the present embodiment, the 7-segment common output data and the 7-segment cathode output data are output at the same time when the 2-digit 7-segment LED is dynamically lit and controlled. In this case, the number of instruction codes required for the dynamic lighting control of the 7-segment LED on the source program can be reduced, and the capacity of the source program (capacity used by the main ROM 102) can be reduced. Therefore, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

The "7-segment common output data" referred to here is LED drive data output to the common (common) terminal of the 7-segment LED when the 7-segment LED is dynamically controlled, and the "7-segment cathode output data" is , This is LED drive data output to each cathode terminal of the 7-segment LED when the 7-segment LED is dynamically lit and controlled.

[Game return processing]
Next, with reference to FIGS. 66 and 67, the game return process performed in S12 during the power-on (reset interrupt) process (see FIG. 64) will be described. Note that FIG. 66 is a flowchart showing the procedure of the game return process, and FIG. 67 is a diagram showing an example of a source program for executing the processes of S25 to S32 in the flowchart.

First, the main CPU 101 sets the stack pointer (SP) at the time of power failure (S21). Next, the main CPU 101 clears (offs) the on-edge data before the 10-interrupt processing of the input port and the currently set on-edge data (S22). Next, the main CPU 101 sets the backup data of the output port in the output port (S23). Next, the main CPU 101 reads the data of the input port and saves the data in the current data storage area of the input port and before the interrupt processing (S24).

Next, the main CPU 101 sets the address of the rotating cylinder control data storage area (S25). Next, the main CPU 101 sets the number of reels to be checked (“3” in this embodiment) (S26).

Next, the main CPU 101 acquires reel control management information (data related to fluctuation control of the display column when a power failure occurs) of a predetermined reel based on the address of the set rotation cylinder control data storage area (S27). The reel control management information (variation control management information in the display column) is information related to the control state (rotation status) of each reel, and is backed up and saved in the event of a power failure.

Next, the main CPU 101 determines whether or not the reel control management information is information corresponding to the rotation status during reel acceleration, constant speed waiting, or constant speed (S28).

When the main CPU 101 determines in S28 that the condition of S28 is not satisfied (when the determination in S28 is NO), the main CPU 101 performs the process of S31 described later. On the other hand, in S28, when the main CPU 101 determines that the condition of S28 is satisfied (YES in S28), the main CPU 101 clears the spinning control data (reel control management information) (S29). By this process, after returning to the game, the rotation control of the reel is started from the acceleration process. Next, the main CPU 101 sets the reel operation timing value (execution start timing “1” of the rotation cylinder control data) (S30). When "1" is set for the reel operation timing, the excitation change timing is set in the reel control process (see S903 in FIG. 158 described later), so that the main CPU 101 accelerates the reel rotation control. Start from.

After the processing of S30 or when the determination in S28 is NO, the main CPU 101 subtracts 1 from the value of the number of reels (S31). Next, the main CPU 101 determines whether or not the value of the number of reels after subtraction is "0" (S32).

In S32, when the main CPU 101 determines that the value of the number of reels after subtraction is not "0" (when the determination in S32 is NO), the main CPU 101 changes the reel to be checked and shifts the processing to the processing of S27. Return and repeat the processing after S27.

On the other hand, in S32, when the main CPU 101 determines that the value of the number of reels after subtraction is "0" (when the determination in S32 is YES), the main CPU 101 performs the RAM initialization process (S33). In this process, the main CPU 101 sets the address "at the time of power recovery" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the final address of the game RAM area is set from the start address. Delete (clear) the information up to the address.

Next, the main CPU 101 restores the data of all the registers saved at the time of power failure detection to all the registers (S34). Then, after the process of S34, the main CPU 101 ends the game return process and returns the process to the process at the time of power failure detection.

In the present embodiment, the game return process is performed as described above. In the game return processing of the present embodiment, as described above, the input / output state of each port at the time of power failure is secured at the time of power recovery, and when the reel is rotating at the time of power failure, reel control management is performed at the time of power recovery. The processing necessary for starting the re-rotation of the reel by acquiring the information is also performed (see the processing of S25 to S32). Therefore, in the present embodiment, the reel re-rotation control can be stably performed even when the reel is recovered from the electric power failure during the rotation of the reel, and the player is not uncomfortable.

Further, the processes S25 to S32 during the game return process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 67. As described above, the microprocessor 91 with a security function for a game machine used in the pachislot machine 1 of the present embodiment is provided with various instruction codes dedicated to the main CPU 101. For example, the "LDQ" instruction (predetermined read instruction) in FIG. 67 is one of the main CPU 101 dedicated instruction codes.

For example, when the source code "LDQ HL, k" is executed on the source program, the address specified by the contents of the Q register (stored data) and the 1-byte integer k (direct value) becomes the HL register. Loaded into. At this time, the content of the Q register becomes the address value on the upper side of the designated destination address, and the integer k (direct value) becomes the address value on the lower side of the designated destination address. Therefore, when the source code "LDQ HL, .LOW.wR1_CTRL" in FIG. 67 is executed, the contents of the Q register (the address value on the upper side of the address of the rotation control data storage area) and the integer value ". The address (address of the rotating cylinder control data storage area) specified by "LOW.wR1_CTRL" (address value on the lower side of the address of the rotating cylinder control data storage area) is loaded into the HL register. Note that ".LOW." Is not an actual instruction but a pseudo instruction. In this pseudo-instruction function, only the lower address of the address of the storage area specified after ".LOW." Is enabled. Further, the pseudo instruction is not an instruction stored in the actual ROM, but an instruction for the conversion program (assembler) to refer to when converting the source file into a format for storing in the ROM.

As described above, in the present embodiment, by using the instruction code dedicated to the main CPU 101 that specifies the address using the Q register (extension register), the main ROM 102, the main RAM 103, and the memory map I / O can be set by the direct value. Can be accessed. In this case, the instruction code related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Setting change confirmation process]
Next, the setting change confirmation process performed in S15 during the power-on (reset interrupt) process (see FIG. 64) will be described with reference to FIGS. 68 and 69. Note that FIG. 68 is a flowchart showing the procedure of the setting change confirmation process, FIG. 69A is a diagram showing an example of a source program for executing the processes of S44 to S47 in the flowchart, and FIG. 69B is a diagram showing an example of the source program. It is a figure which shows an example of the source program for executing the process of S57 in the flowchart.

First, the main CPU 101 performs an initialization process of an unspecified RAM area in the main RAM 103 (S41). Next, the main CPU 101 performs one interrupt wait process (S42). In this process, the main CPU 101 waits until the process of transmitting the non-operation command to the sub-control circuit 200 by the interrupt process is completed.

Next, the main CPU 101 performs a RAM initialization process (S43). In this process, the main CPU 101 sets the address "at the time of RAM abnormality or at the start of setting change" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game starts from the start address. Erase (clear) the information up to the final address of the RAM area.

Next, the main CPU 101 determines whether or not the setting key type switch 54 is in the ON state (S44). The setting key (not shown) inserted into the setting key type switch 54 is an operation key for operating the setting (settings 1 to 6) of the pachislot machine 1, and when the setting key is turned on, it is for setting. The key type switch 54 is turned on.

In S44, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (when the determination in S44 is NO), the main CPU 101 ends the setting change confirmation process and turns on the power (reset interrupt). ) Move to the processing of S16 of the time processing (see FIG. 64). On the other hand, in S44, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (when the determination in S44 is YES), the main CPU 101 performs a medal acceptance prohibition process (S45). By this process, the solenoid of the selector 66 (see FIG. 7) is not driven, and the inserted medals are ejected from the medal payout outlet 24 (see FIG. 2).

Next, the main CPU 101 sets the setting change start or setting confirmation start information (005H: first value) in the L register, and performs the generation and storage process of the setting change command (setting change / setting confirmation start) (S46). .. In this process, the main CPU 101 generates setting change command data (first command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the start of the setting change process or the setting confirmation process, and generates the command data. It is stored in the communication data storage area provided in the main RAM 103. The details of the setting change command generation and storage process will be described later with reference to FIG. 70 described later. Further, the setting change command (setting change / setting confirmation start) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. Will be sent to.

Next, the main CPU 101 sets the error count relay to the ON state (S47). Next, the main CPU 101 determines whether the setting change or the setting confirmation has been performed (S48).

In S48, when the main CPU 101 determines that the setting has not been changed (the setting has been confirmed) (when the determination in S48 is NO), the main CPU 101 performs the process of S55 described later.

On the other hand, in S48, when the main CPU 101 determines that the setting has been changed (the setting has not been confirmed) (when the determination in S48 is YES), the main CPU 101 updates the set value (S49). ). Next, the main CPU 101 performs a 7-segment display setting process of the set value (S50). By this process, the updated set value can be displayed on the 7-segment LED in the information display 6.

Next, the main CPU 101 determines whether or not the reset switch 76 is in the ON state (S51).

When the main CPU 101 determines in S51 that the reset switch 76 is in the ON state (when the determination in S51 is YES), the main CPU 101 returns the process to the process of S49 and repeats the processes after S49. On the other hand, in S51, when the main CPU 101 determines that the reset switch 76 is not in the ON state (when the determination in S51 is NO), the main CPU 101 determines whether or not the start switch 79 is in the ON state (S52). ..

When the main CPU 101 determines in S52 that the start switch 79 is not in the ON state (when the determination in S52 is NO), the main CPU 101 returns the process to the process in S51 and repeats the processes after S51. On the other hand, in S52, when the main CPU 101 determines that the start switch 79 is in the ON state (when the determination in S52 is YES), the main CPU 101 is set in the set value storage area (not shown) provided in the main RAM 103. Store the value (S53).

Next, the main CPU 101 determines whether or not the setting key type switch 54 is in the off state (S54).

In S54, when the main CPU 101 determines that the setting key type switch 54 is not in the off state (when the determination in S54 is NO), the main CPU 101 repeats the process of S54. On the other hand, in S54, when the main CPU 101 determines that the setting key type switch 54 is in the off state (when the determination in S54 is YES), the main CPU 101 performs the process of S55 described later.

When the determination in S48 is NO or the determination in S54 is YES, the main CPU 101 determines whether the setting change or the setting confirmation has been performed (S55).

In S55, when the main CPU 101 determines that the setting has not been changed (the setting has been confirmed) (when the determination in S55 is NO), the main CPU 101 performs the process of S57 described later. On the other hand, in S55, when the main CPU 101 determines that the setting has been changed (the setting has not been confirmed) (when the determination in S55 is YES), the main CPU 101 performs the RAM initialization process (S56). .. In this process, the main CPU 101 uses the address (the address next to the set value storage area) of the main RAM 103 shown in FIG. 12C at the end of the setting change, which is not shown, as the start address of the initialization start. It is set and the information from the start address to the final address of the game RAM area is erased (cleared).

After processing S56 or when S55 determines NO, the main CPU 101 sets the setting change end or setting confirmation end information (004H: second value) in the L register, and sets the setting change command (setting change / setting confirmation end). ) Is generated and stored (S57). In this process, the main CPU 101 generates setting change command data (second command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the end of the setting change process or the setting confirmation process, and generates the command data. It is stored in the communication data storage area provided in the main RAM 103. The details of the setting change command generation and storage process will be described later with reference to FIG. 70 described later. Further, the setting change command (setting change / setting confirmation end) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. Will be sent to. Then, after the processing of S57, the main CPU 101 ends the setting change confirmation processing, and shifts the processing to the processing of S16 of the power-on (reset interrupt) processing (see FIG. 64).

In the present embodiment, the setting change confirmation process is performed as described above. The processes S44 to S47 during the above-mentioned setting change confirmation process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 69A. Among them, for example, the state determination process of the setting key of S44 is executed by the source code "BITQ 7, (.LOW. (WIBUF + 4))" in FIG. 69A, and the error count relay of S47 is set to the ON state. The process is executed by the source code "SETQ 1, (.LOW.wECRRQ)" in FIG. 69A.

Both the "BITQ" instruction and the "SETQ" instruction are instruction codes dedicated to the main CPU 101 that specify an address using a Q register (extension register).

When, for example, the source code "BITQ b, (k)" is executed on the source program, the stored data (upper address value) of the Q register and the 1-byte integer value k (direct value: lower address value) are executed. If bit b of the memory at the address specified by) is checked and "1" is stored in the bit b, "0" is set in the zero flag (bit 6: see FIG. 11) of the flag register F. If "0" is stored in the bit b, "1" is set in the zero flag (predetermined bit area) of the flag register F. Therefore, when the source code "BITQ 7, (.LOW. (WIBUF + 4)" in FIG. 69A is executed, the stored data of the Q register and the address specified by the integer value ".LOW. (WIBUF + 4)" If bit 7 of the memory is checked and "1" is stored in the bit 7, "0" is set in the zero flag of the flag register F, and if "0" is stored in the bit 7. , "1" is set to the zero flag of the flag register F.

Further, for example, when the source code "SETQ b, (k)" is executed on the source program, the stored data (upper address value) of the Q register and the 1-byte integer value k (direct value: lower side) are executed. "1" is set in the memory bit b of the address specified by (address value). Therefore, when the source code "SETQ 1, (.LOW.wECRRQ)" in FIG. 69A is executed, the stored data of the Q register and the memory of the address specified by the integer value ".LOW.wECRRQ" are stored. Bit 1 is set to "1".

That is, in the setting change confirmation process of the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extension register) as described above are used, and the direct value is obtained by using these main CPU 101 dedicated instruction codes. Then, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed. In this case, the instruction code related to the address setting can be omitted, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space of the main ROM 102 can be increased, and the processing speed can be increased.

Further, the generation and storage process of the setting change command (initialization command) performed at the start of the setting change / setting confirmation of S46 during the setting change confirmation process described above is performed by the main CPU 101 executing the "CALLF" command in FIG. 69A. The generation / storage process of the setting change command (initialization command) performed at the end of the setting change / setting confirmation of S57 described above is performed by the main CPU 101 executing the "CALLF" command in FIG. 69B. The "CALLF" instruction is also an instruction code dedicated to the main CPU 101.

For example, when the source code "CALLF mn" is executed on the source program, the value (stored data) of the current PC register (program counter PC: see FIG. 11) is specified by the stack pointer (SP). It is saved in the memory, the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address specified by "mn". However, the "CALLF" instruction is a 2-byte instruction, and the jumpable address range is in the range of 0000H to 11FFH. Therefore, for example, when the source code "CALLF SB_PCIIT_00" in FIG. 69A is executed, the current value of the PC register is saved in the memory specified by the stack pointer (SP), and the stack pointer is updated by -2. , The address of "SB_PCIIT_00" is stored in the PC register, and the process jumps to the address specified by "SB_PCIIT_00".

In the present embodiment, an instruction code called a "CALL" instruction is also prepared as an instruction code of the same type as the "CALLF" instruction. Then, for example, when the source code "CALL mn" is executed on the source program, the value (stored data) of the current PC register (program counter PC: see FIG. 11) is changed as in the "CALLF" instruction. It is saved in the memory specified by the stack pointer (SP), the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address specified by "mn". However, the "CALL" instruction is a 3-byte instruction, and the jumpable address range is different from that of the "CALLF" instruction, and the jumpable address range is in the range of 0000H to FFFFH. Since the "CALLF" instruction is an instruction code having a smaller number of bytes than the "CALL" instruction, the capacity of the source program (the capacity used by the main ROM 102) can be reduced and the processing efficiency can be improved. be able to.

Further, in the setting change confirmation process of the present embodiment, as shown in FIGS. 69A and 69B, the jump destination address “SB_PCIT_00” specified by the “CALLF” instruction in S46 is the jump destination specified by the “CALLF” instruction in S57. It is the same as the address of. That is, in the present embodiment, the setting change command (initialization command) to be transmitted to the sub-control circuit 200 at the time of setting change (when the game machine is started), at the start of setting confirmation (during normal operation), and at the end of setting confirmation is generated and stored. The source programs for executing the above are the same as each other, and the source programs for the setting change command generation and storage processing used in both the processes of S46 and S57 are shared (modularized).

In this case, in both the processes of S46 and S57, it is not necessary to separately provide the source program for the setting change command generation and storage process, so that the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. .. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Setting change command generation and storage processing]
Next, the setting change command generation / storage process performed in S46 and S57 in the setting change confirmation process (see FIG. 68) will be described with reference to FIGS. 70 and 71. Note that FIG. 70 is a flowchart showing the procedure of the setting change command generation / storage process, and FIG. 71 is a diagram showing an example of a source program for executing the setting change command generation / storage process.

First, the main CPU 101 sets the information of the set values (1 to 6) in the E register (S61). Next, the main CPU 101 sets the RT state information in the C register (S62). Next, the main CPU 101 sets the command type information (02H) of the setting change command in the A register (S63).

Next, the main CPU 101 performs a communication data storage process (S64). In this process, the main CPU 101 has the information set in each register in S61 to S63 and the information set in the D register in S46 or S57 (see FIG. 68) (setting change start / setting change end / setting status). Setting change command data is generated by using (setting confirmation start / setting confirmation end), and the generated command data is saved in the communication data storage area. The details of the communication data storage process will be described later with reference to FIG. 72 described later.

After the process of S64, the main CPU 101 ends the setting change command generation and storage process. When the setting change command generation and storage process performed in S46 during the setting change confirmation process (see FIG. 68) is terminated, the main CPU 101 performs the process after the process of S64 in the setting change confirmation process (see FIG. 68). Move to the process of S47. Further, when ending the setting change command generation and storage process performed in S57 during the setting change confirmation process (see FIG. 68), the main CPU 101 ends the setting change command generation and storage process after the process of S64, and also sets the settings. The change confirmation process (see FIG. 68) is also completed.

In the present embodiment, the setting change command generation / storage process is performed as described above. The above-mentioned setting change command generation / storage process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 71.

As described above, in the setting change command generation and storage process, the setting status is stored in the D register as communication parameter 4 immediately before the setting change command generation and storage process is executed, and the set value is set during the execution of the setting change command generation and storage process. Is stored in the E register as the communication parameter 3, and the RT information is stored in the C register as the communication parameter 5. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), the communication parameters 3 to 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side, and these are used. New information is set in the communication parameters. On the other hand, the other communication parameters 1 and 2 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side, and are for communication parameters 1 and 2. Therefore, the values currently stored in the L register and the H register are set. Therefore, the values of the communication parameters 1 and 2 at the time of transmitting the setting change command (initialization command) are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[Communication data storage process]
Next, with reference to FIGS. 72 and 73, for example, the communication data storage process performed in S64 during the setting change command generation / storage process (see FIG. 70) will be described. The communication data storage process is executed not only when the setting change command is generated but also when other commands are generated. FIG. 72 is a flowchart showing the procedure of the communication data storage process, and FIG. 73 is a diagram showing an example of a source program for executing the processes of S71 to S76 during the communication data storage process.

First, the main CPU 101 stores the data set in the A register as communication command type data in the communication data temporary storage area (not shown) in the main RAM 103 (S71). Next, the main CPU 101 stores the data set in the H register and the L register in the communication data temporary storage area (predetermined storage area) in the main RAM 103 as parameters 1 and 2 of the communication command, respectively (S72). ..

Next, the main CPU 101 stores the data set in the D register and the E register as the parameters 3 and 4 of the communication command in the communication data temporary storage area in the main RAM 103 (S73). Next, the main CPU 101 stores the data set in the B register and the C register as the data of the parameter 5 of the communication command and the RT state, respectively, in the communication data temporary storage area in the main RAM 103 (S74).

Next, the main CPU 101 generates BCC data (sum value) of the communication command from the data values set in the A register to the L register (S75). Next, the main CPU 101 stores the generated BCC data in the communication data temporary storage area in the main RAM 103 (S76).

After the processing of S76, the main CPU 101 determines whether or not there is a free space in the communication data storage area in the main RAM 103 (S77). In this embodiment, a maximum of nine command data can be stored in the communication data storage area (see FIG. 75B described later).

When the main CPU 101 determines in S77 that there is no free space in the communication data storage area (when the determination in S77 is NO), the main CPU 101 ends the communication data storage process and, for example, sets change command generation and storage process (when the communication data storage area is determined to be NO). (See FIG. 70) also ends.

On the other hand, in S77, when the main CPU 101 determines that there is a vacancy in the communication data storage area (when the determination in S77 is YES), the main CPU 101 is stored in the communication data temporary storage area by the above-mentioned processes S71 to S76. The communication data is stored in the communication data storage area as communication command data (S78).

Next, the main CPU 101 performs the communication data pointer update process (S79). In this process, the main CPU 101 mainly updates the communication data pointer indicating the storage address of the communication data in the communication data storage area. The details of the communication data pointer update process will be described later with reference to FIG. 74 described later.

Then, after the process of S79, the main CPU 101 ends the communication data storage process and, for example, the setting change command generation and storage process (see FIG. 70).

In the present embodiment, the communication data storage process is performed as described above. The processes S71 to S76 during the above-mentioned communication data storage process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 73. Then, in this series of processing, the storage processing of the communication command type data, various communication parameters, the game state flag data, and the BCC data included in the command data is as shown in FIG. 73, in the Q register on the source program. It is executed by using the "LDQ" instruction, which is an instruction code dedicated to the main CPU 101 that specifies an address using (extension register).

Specifically, by executing the source code "LDQ (.LOW. (WPDT_TMP + 0)), A", the type data of the communication command stored in the A register becomes 1 with the stored data (upper address value) in the Q register. It is stored in the communication data temporary storage area of the address specified by the integer value ".LOW. (WPDT_TMP + 0)" (lower address value) of the byte. Further, by executing the source code "LDQ (.LOW. (WPDT_TPP + 1)), HL", the communication parameter 1 stored in the L register is changed to the stored data in the Q register and the 1-byte integer value ".LOW. (WPDT_TMP + 1)). The communication parameter 2 stored in the communication data temporary storage area of the address specified by "" and stored in the H register is stored in the communication data temporary storage area of the next address. Further, by executing the source code "LDQ (.LOW. (WPDT_TPP + 3)), DE", the communication parameter 3 stored in the E register is changed to the stored data in the Q register and the 1-byte integer value ".LOW. (WPDT_TPP + 3)". The communication parameter 4 stored in the communication data temporary storage area of the address specified by "" and stored in the D register is stored in the communication data temporary storage area of the next address. Then, by executing the source code "LDQ (.LOW. (WPDT_TPP + 5)), BC", the communication parameter 5 stored in the C register is changed to the stored data in the Q register and the 1-byte integer value ".LOW. (WPDT_TPP + 5)". The game state flag data stored in the communication data temporary storage area of the address specified by "" and stored in the B register is stored in the communication data temporary storage area of the next address.

Further, the BCC data which is the sum value of the command data set in the communication data storage process is calculated by executing a series of source codes "ADD (additional instruction code) A, H" to "ADD A, B", and A. Stored in a register. Then, by executing the source code "LDQ (.LOW. (WPDT_TPP + 7)), A", the BCC data stored in the A register becomes the stored data in the Q register and the 1-byte integer value ".LOW. (WPDT_TPP + 7)". It is stored in the communication data temporary storage area of the address specified in.

As described above, in the present embodiment, when creating one packet (8 bytes) of communication data (command data), various parameters are transferred from the register and stored in the communication data temporary storage area (communication buffer). In such a command data creation method, the data stored in each register at the time of command generation is stored as it is in the communication data temporary storage area as various parameters of the command data. Therefore, when command data including unused parameters is created, the value of the unused parameters becomes an indefinite value each time it is created. In this case, even if there is command data of the same type and the values of the parameters used are the same, the sum value (BCC data) of the command data can be changed each time the command is created. Further, in the present embodiment, the calculation of the sum value, which is one of the error codes, is calculated by ADD (addition instruction code), but instead of the addition instruction code, SUB (subtraction instruction code) and XOR (exclusive OR). The same effect can be obtained by calculating the error code using the instruction code). Further, the same effect can be obtained by calculating the error code using the MUL (multiplication instruction code) or DIV (division instruction code), which is an instruction dedicated to the main CPU 101.

Therefore, in the present embodiment, by setting the unused parameter to an indefinite value, it is possible to make it difficult to analyze the communication data and suppress fraudulent acts such as goto, and it is necessary to add unnecessary goto countermeasure processing. Therefore, it is possible to suppress the pressure on the program capacity of the main control circuit 90 due to the addition of the anti-goto processing.

[Communication data pointer update process]
Next, the communication data pointer update process performed in S79 during the communication data storage process (see FIG. 72) will be described with reference to FIGS. 74 and 75. 74 is a flowchart showing the procedure of the communication data pointer update process, FIG. 75A is a diagram showing an example of a source program for executing the communication data pointer update process, and FIG. 75B is a diagram showing an example of a source program for executing the communication data pointer update process. It is a figure which shows the structure of the communication data storage area which is actually set on the source program of an update process.

First, the main CPU 101 acquires the value of the currently set communication data pointer (S81).

Next, the main CPU 101 adds and updates the value of the communication data pointer by one packet (8 bytes) (S82). In this process, when the value of the updated communication data pointer is equal to or larger than the upper limit size of the communication data storage area (see FIG. 75B), the main CPU 101 sets the value of the updated communication data pointer to "0". ", This invalidates all command data stored in the communication data storage area (makes it the same state as the discarded state).

In the present embodiment, the amount of data (1 packet) transmitted in one transmission operation is 8 bytes. That is, in the present embodiment, one command data can be transmitted by one transmission operation. Further, in the present embodiment, since a maximum of 9 command data can be stored in the communication data storage area (see FIG. 75B), the upper limit size of the communication data storage area is 72 bytes (= 8 bytes × 9). .. Therefore, in the present embodiment, the range of the communication data pointer is set to "0" to "71", and in the process of S82, the value of the communication data pointer after the update (when the communication data pointer is updated by +8) is "71 (when the communication data pointer is updated by +8). If the value exceeds "upper limit value)", set the updated communication data pointer value to "0" (return the communication data storage destination address to the start address) and store the communication data. Disable all command data stored in the area (make it the same as the discarded state). If the value of the communication data pointer is set to "0", the next time the command data is stored in the communication data storage area, it is stored from the start address of the communication data storage area, so it is stored before that. The command data will be overwritten with new command data. Therefore, in the present embodiment, it is not necessary to initialize (clear) the communication data storage area when the value of the communication data pointer exceeds "71 (upper limit value)".

Then, after the process of S82, the main CPU 101 ends the communication data pointer update process and also ends the communication data storage process (see FIG. 72).

In the present embodiment, the communication data pointer update process is performed as described above. Then, the communication data pointer update process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 75A. Among them, the update process of the communication data pointer of S82 is executed by the "ADD" instruction and the "ICPLD" instruction (predetermined update instruction) in FIG. 75A, and this "ICPLD" instruction is also dedicated to the main CPU 101. It is an instruction code.

For example, when the source code "ICPLD A, n" is executed on the source program, the contents (stored data) of the A register and the integer n are compared, and when the contents of the A register are less than the integer n, the contents of the A register are compared. , "1" is added to the contents of the A register, and when the contents of the A register are an integer n or more, "0" is set in the A register.

Therefore, when the communication data pointer update process of S82 is executed, the source code "ADD A, 7" is first executed on the source program of FIG. 75A, and the contents of the A register (the communication data pointer before the update) are executed. "7" is added to the value), and the addition result is stored in the A register. Next, the source code "ICPLD A, 71" is executed, the contents of the A register (the value of the communication data pointer after adding 7) are compared with the integer "71", and the contents of the A register are less than the integer "71". If there is, "1" is added to the contents of the A register, and if the contents of the A register are an integer "71" or more, "0" is set in the A register. That is, in the process of S82, when the value of the communication data pointer is updated by +7, if the value of the updated communication data pointer exceeds the upper limit value "71", the process of clearing the communication data pointer to zero (communication). The process of returning the data storage address to the start address of the communication data storage area) is performed. On the other hand, if the updated communication data pointer value does not exceed the upper limit value "71", the communication data pointer value is totaled by adding "1" to the communication data pointer with the "ICPLD" instruction. Update +8.

As described above, in the present embodiment, in the communication data pointer update process, communication data is used by one "ICPLD" instruction code (an instruction code in which the upper limit determination instruction of the transmission buffer and the determination branch instruction are integrated). It is possible to collectively execute the pointer update (1 addition) process, the communication data pointer determination check process after the update, and the communication data pointer clear process. In this case, it is not necessary to provide an instruction code for executing each process separately. For example, the branch instruction code for determining whether or not the updated communication data pointer value exceeds the upper limit value "71" can be omitted.

Therefore, the capacity of the source program (the capacity used by the main ROM 102) can be reduced by using the "ICPLD" instruction code dedicated to the main CPU 101 in the communication data pointer update process or the like. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Processing at the time of power failure (external)]
Next, the power failure (external) processing of the pachi-slot machine 1 performed under the control of the main CPU 101 will be described with reference to FIG. 76. FIG. 76 is a flowchart showing a procedure of (external) processing at the time of power failure. In the power interruption (external) process shown in FIG. 76, when the power supply management circuit 93 detects a decrease in the power supply voltage (power interruption) supplied to the microprocessor 91, the power interruption detection signal is transmitted to the microprocessor 91. Is output to the "XINT" terminal of the above, and is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

First, the main CPU 101 saves the data set in all the registers (S91). Next, the main CPU 101 reads the data set in the power failure detection port (S92).

Next, the main CPU 101 determines whether or not the power failure detection port is in the ON state (S93).

In S93, when the main CPU 101 determines that the power interruption detection port is not in the ON state (when the determination in S93 is NO), the main CPU 101 sets the interrupt processing permission (S94). Then, after the processing of S94, the main CPU 101 ends the (external) processing at the time of power failure. It should be noted that these processes performed when S93 is a NO determination correspond to the process of countermeasures against momentary power failure that occurs when the power management circuit 93 momentarily detects a power failure or the like.

On the other hand, in S93, when the main CPU 101 determines that the power failure detection port is in the ON state (when the determination in S93 is YES), the main CPU 101 sets that the medal cannot be inserted and sets the stop of the hopper device 51. (S95).

Next, the main CPU 101 saves the currently set value of the stack pointer (SP) in the stack area of the game RAM area in the main RAM 103 (S96).

Next, the main CPU 101 performs a checksum generation process of the main RAM 103 (S97). This process is performed in the non-standard work area (see FIG. 12C) in the main RAM 103. Further, the program used in this checksum generation process is stored in the non-standard area in the main ROM 102 (see FIG. 12B). The details of the checksum generation process will be described later with reference to FIG. 77 described later.

Next, the main CPU 101 sets access prohibition to the main RAM 103 (S98). Then, after the processing of S98, the infinite loop processing is performed until the power supply is stopped (until the power supply voltage reaches a voltage at which the main CPU 101 cannot operate).

[Checksum generation process (non-standard)]
Next, the checksum generation process performed in S97 during the power failure (external) process (see FIG. 76) will be described with reference to FIGS. 77 and 78. 77 is a flowchart showing the procedure of the checksum generation process, FIG. 78A is a diagram showing an example of a source program for executing the checksum generation process, and FIG. 78B is a checksum generation process. It is a figure which shows the state of the update operation of the stack pointer and the operation of reading data from a main RAM 103 to a register which are executed.

First, the main CPU 101 saves the current stack pointer (SP) value (the address in use of the stack area of the game RAM area) in the non-standard stack area of the non-standard RAM area of the main RAM 103 (S101). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (S102). Next, the main CPU 101 sets the address value (F0H) on the upper side of the RAM address (address of the non-standard stack area) in the Q register (S103). Next, the main CPU 101 sets the power failure occurrence flag (S104).

Next, the main CPU 101 sets the stack pointer with the calculation start address of the sum value in the game RAM area, and sets the sum calculation counter with the value obtained by dividing the number of bytes of the sum value calculation target storage area by "2". Set (S105). The sum calculation counter is a counter for determining the end trigger of the sum value calculation, and is provided in the main RAM 103. Then, when the sum calculation counter set in S105 becomes "0", the sum value calculation process of the game RAM area of the main RAM 103 is terminated.

Next, the main CPU 101 clears the HL register to 0 (sets the value “0”) (S106). By this process, the initial value "0" of the sum value is set.

Next, the main CPU 101 executes an instruction code (source code "POP DE" shown in FIG. 78A) called an "POP instruction" (specific instruction), and stores the main RAM 103 set in the stack pointer (SP). The data (stored value) of the area for 2 bytes is read from the address of the area to the DE register (S107).

When the "POP" instruction is executed, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the lower register of the pair register and specified by the stack pointer. The data (memory contents) stored in the 1-byte area of the address where the updated address is updated by 1 is loaded into the register on the upper side of the pair register. Further, when the "POP" instruction is executed, an address update process for 2 bytes (a process of adding "2" to the address) is performed on the address set in the stack pointer (SP).

Therefore, in the process of S107, the data (memory contents) stored at the address specified by the stack pointer is loaded into the E register and saved at the address specified by the stack pointer plus "1". The data (memory contents) is loaded into the D register.

FIG. 78B shows a state of reading data to the DE register and updating the address set in the stack pointer when the “POP” instruction is executed. If the address set in the stack pointer (SP) is "F010h" at the start of calculation of the sum value, the data (memory contents) stored in the address "F010h" is loaded into the E register and the address. The data (memory contents) stored in "F011h" is loaded into the D register. Further, at this time, an update process of adding 2 to the address set in the stack pointer (SP) is performed, and the address set in the stack pointer (SP) is changed from "F010h" to "F012h". Then, when the "POP" instruction is executed again, the data (memory contents) stored in the address "F012h" is loaded into the E register, and the data (memory contents) stored in the address "F013h" is loaded. It is loaded into the D register. At this time, the address set in the stack pointer (SP) is updated, and the address set in the stack pointer (SP) is changed from "F012h" to "F014h". After that, every time the "POP" instruction is executed, the above-mentioned operation of reading data to the DE register and the operation of updating the address set in the stack ponter are repeated.

After the process of S107, the main CPU 101 performs a sum value calculation process (S108). Specifically, the main CPU 101 adds the value stored in the DE register to the value stored in the HL register, and stores the added value as a sum value in the HL register.

Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S109). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S110).

In S110, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S110 is NO), the main CPU 101 returns the process to the process of S107 and repeats the processes after S107. That is, the processes of S107 to S110 are repeated until the sum value calculation process of the game RAM area of the main RAM 103 is completed.

On the other hand, in S110, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S110 is YES), the main CPU 101 sets the DE register in the non-standard RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-standard sum count value is set in the sum calculation counter (S111). The non-standard sum count value is the number of bytes in the non-standard storage area. Therefore, when the sum calculation counter set in S111 becomes "0", the sum value calculation process of the non-standard RAM area of the main RAM 103, that is, the sum value calculation process of the entire main RAM 103 is completed.

Next, the main CPU 101 reads the data (stored value) of one byte from the address of the non-standard RAM area set in the DE register into the A register (S112).

Next, the main CPU 101 performs a sum value calculation process (S113). Specifically, the main CPU 101 adds the value stored in the A register to the value stored in the HL register, and stores the added value as a sum value in the HL register.

Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S114). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S115).

In S115, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S115 is NO), the main CPU 101 returns the processing to the processing in S112 and repeats the processing after S112. That is, the processes of S112 to S115 are repeated until the process of adding the sum value of the non-standard RAM area of the main RAM 103 to the sum value of the game RAM area is completed.

On the other hand, in S115, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S115 is YES), the main CPU 101 sets the value stored in the HL register when a power failure occurs. As the sum value of, it is stored in the sum value storage area (not shown) in the main RAM 103 (S116). Next, the main CPU 101 sets the value of the stack pointer (SP) saved in the non-standard stack area in S101 in the stack pointer (S117). Then, after the processing of S117, the main CPU 101 ends the checksum generation processing, and shifts the processing to the processing of S98 at the time of power failure (external) processing (see FIG. 76).

In the present embodiment, the checksum generation process is performed as described above. Then, the checksum generation process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 78A. As described above, in the present embodiment, the checksum of the main RAM 103 when a power failure occurs is calculated by an addition formula. At this time, in the calculation of the sum value of the game RAM area, addition processing is performed in 2-byte units (see the source code "ADD HL, DE" in FIG. 78A), and in the non-standard RAM area, addition processing is performed in 1-byte units. (See the source code "ADDWB HL, A" in FIG. 78A).

[Sum check processing (non-standard)]
Next, the thumb check process performed in S9 during the power-on processing (see FIG. 64) will be described with reference to FIGS. 79 to 81. 79 and 80 are flowcharts showing the procedure of the thumb check process, and FIG. 81 is a diagram showing an example of a source program for executing the processes of S122 to S132 during the checksum check process.

First, the main CPU 101 saves the current stack pointer (SP) value in the non-standard stack area (S121). Next, the main CPU 101 sets the address of the sum value storage area in the stack pointer, and sets the value obtained by dividing the number of bytes of the sum value calculation target storage area by "2" in the sum calculation counter (S122). The sum calculation counter set here is a counter for determining the end trigger of the sum value calculation (sum value subtraction process), and is provided in the main RAM 103. Next, the main CPU 101 acquires a sum value (checksum) from the sum value storage area (S123). By this process, the checksum (initial value before subtraction) generated when the power failure occurs is stored in the HL register.

Next, the main CPU 101 executes the "POP" instruction and reads the data (stored value) of the area of 2 bytes from the address of the storage area of the main RAM 103 set in the stack pointer (SP) into the DE register (S124). .. At this time, by executing the "POP" instruction, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the E register, and the address specified by the stack pointer is used. The data (memory contents) stored in the 1-byte area of the updated address is loaded into the D register (see FIG. 78B). Further, when the "POP" instruction is executed, an address update process for 2 bytes (a process of adding 2 addresses) is performed on the address set in the stack pointer (SP).

Next, the main CPU 101 performs a sum value calculation (subtraction) process (S125). Specifically, the main CPU 101 subtracts the value stored in the DE register from the value stored in the HL register (initial value of the sum value or the sum value after the previous subtraction process), and the subtraction is performed. Store the value as a sum value in the HL register.

Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S126). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S127).

In S127, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S127 is NO), the main CPU 101 returns the processing to the processing of S124, and repeats the processing after S124. That is, the processes of S124 to S127 are repeated until the subtraction process of the sum value is completed over the entire area of the game RAM area of the main RAM 103.

On the other hand, in S127, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S127 is YES), the main CPU 101 sets the DE register in the non-standard RAM area in the main RAM 103. The calculation start address of the sum value is set, and the non-standard sum count value is set in the sum calculation counter (S128). The non-standard sum count value is the number of bytes in the non-standard RAM area.

Next, the main CPU 101 reads the data (stored value) of one byte from the address of the non-standard RAM area set in the DE register into the A register (S129).

Next, the main CPU 101 performs a sum value calculation (subtraction) process (S130). Specifically, the main CPU 101 subtracts the value stored in the A register from the value stored in the HL register, and stores the subtracted value as a sum value in the HL register.

Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S131). Next, the main CPU 101 determines whether or not the value of the updated sum calculation counter is “0” (S132).

In S132, when the main CPU 101 determines that the value of the sum calculation counter is not "0" (when the determination in S132 is NO), the main CPU 101 returns the processing to the processing of S129, and repeats the processing after S129. That is, the processes of S129 to S132 are repeated until the subtraction process of the sum value is completed over the entire area of the non-standard RAM area of the main RAM 103.

On the other hand, in S132, when the main CPU 101 determines that the value of the sum calculation counter is "0" (when the determination in S132 is YES), the main CPU 101 sets "sum error" in the determination result of the thumb check process. (S133). Next, the main CPU 101 determines whether or not the calculated sum value is “0” (S134).

In this process, the main CPU 101 refers to the state (1/0) of the zero flag (bit 6) of the flag register F to determine whether or not the sum value is “0”. In the present embodiment, the sum value becomes "0" when the value of the sum calculation counter set in S128 becomes "0", that is, when the subtraction process of the sum value is completed over the entire area of the main RAM 103. If, the zero flag in the flag register F is set to "1", and if the sum value is not "0", the zero flag in the flag register F is set to "0". Therefore, if "1 (on state)" is set in the zero flag of the flag register F at the time of processing S134, the main CPU 101 determines that the sum value is "0".

In S134, when the main CPU 101 determines that the calculated sum value is not "0" (when the determination in S134 is NO), the main CPU 101 performs the process of S139 described later. On the other hand, in S134, when the main CPU 101 determines that the calculated sum value is "0" (when the determination in S134 is YES), the main CPU 101 sets "power failure" in the determination result (S135). ).

Next, the main CPU 101 acquires the power failure occurrence flag (S136). Next, the main CPU 101 determines whether or not the power failure generation flag is in the state without power failure (off state) (S137).

In S137, when the main CPU 101 determines that the power interruption occurrence flag is in the state of no power interruption (when the determination in S137 is YES), the main CPU 101 performs the process of S139 described later. On the other hand, in S137, when the main CPU 101 determines that the power interruption occurrence flag is not in the state without power interruption (when the determination in S137 is NO), the main CPU 101 sets "normal" in the determination result (S138).

After the processing of S138, if S134 is a NO determination or S137 is a YES determination, the main CPU 101 saves the determination result in the thumb check determination result and clears (offs) the power failure occurrence flag (S139). Next, the main CPU 101 sets the value of the stack pointer (SP) saved in the non-standard stack area in S121 to the stack pointer (S140). Then, after the processing of S140, the main CPU 101 ends the thumb check processing, and shifts the processing to the processing of S10 of the power-on processing (see FIG. 64).

In this embodiment, the sum check process is performed as described above. Then, the processes S122 to S132 during the above-mentioned checksum check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 81.

As described above, in the thumbchock determination process of the main RAM 103 in the present embodiment, first, the value of the checksum generated when the power failure occurs is sequentially subtracted from the data stored in the main RAM 103 when the power is restored. At this time, in the game RAM area, subtraction processing is performed in 2-byte units (see the source code "SUB HL, DE" in FIG. 81), and in the non-standard RAM area, subtraction processing is performed in 1-byte units (in FIG. 81). Source code "SUBWB HL, A") is performed. Next, it is determined whether or not an abnormality has occurred based on whether or not the final subtraction result is "0" (whether or not the zero flag is in the ON state). Then, when the subtraction result is "0" (when the zero flag is in the on state), it is determined to be normal, and when the subtraction result is not "0" (when the zero flag is in the off state), it is regarded as abnormal. It is judged.

That is, in the present embodiment, the checksum generation process when a power failure occurs is performed by an addition method, and the checksum determination process when the power is restored is performed by a subtractive method. Then, normal / abnormal determination is performed based on the final subtraction result of the checksum. When such a checksum generation process and determination process are performed, it is not necessary to generate a checksum again when the power is restored and to collate the checksum with the checksum when a power failure occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, it is possible to secure a free space corresponding to the omitted portion of the collation instruction code in the main ROM 102, and it is possible to improve the game playability by utilizing the increased free space. The "POP" instruction executed in the above-mentioned checksum generation process when a power failure occurs and the checksum determination process when the power is restored is a stack pointer (SP) operation-only instruction, and the source code ". In addition to "POP DE", there are source codes "POP HL", "POP AF" and the like.

[Main processing of pachislot under the control of the main CPU]
Next, with reference to FIG. 82, the main process (main operation process) of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described. Note that FIG. 82 is a flowchart (hereinafter referred to as a main flow) showing the procedure of the main process.

First, the main CPU 101 performs a RAM initialization process (S201). In this process, the main CPU 101 sets the address "at the end of one game" in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and from the start address, the game RAM area Delete (clear) the information up to the final address. The storage area in this range is, for example, a storage area in which data needs to be erased for each unit game (game) such as an internal winning combination storage area and a display combination storage area.

Next, the main CPU 101 performs medal acceptance / start check processing (S202). In this process, the main CPU 101 performs an input check process such as a medal sensor (not shown) and a start switch 79. The details of the medal reception / start check process will be described later with reference to FIG. 83 described later.

Next, the main CPU 101 performs a random number acquisition process (S203). In this process, the main CPU 101 uses a random number value for internal winning combination lottery (0 to 65535: a value of the random number register 0 of the random number circuit 110 that becomes a hard latch random number) and a random number value for production used in various ART-related lottery ( 0 to 65535: each value of the random number registers 1 to 3 of the random number circuit 110 to be a soft latch random number, 0 to 255: each value of the random number registers 4 to 7 of the random number circuit 110 to be a soft latch random number), etc. The extracted various random number values are stored in a random number value storage area (not shown) provided in the main RAM 103. The details of the random number acquisition process will be described later with reference to FIG. 91 described later.

Next, the main CPU 101 performs an internal lottery process (S204). In this process, the main CPU 101 performs an internal winning combination determination process by lottery based on the random number value (hard latch random number) extracted in S203. The details of the internal lottery process will be described later with reference to FIG. 92 described later.

Next, the main CPU 101 performs a symbol setting process (S205). In this process, the main CPU 101, for example, generates an internal winning combination from the hit request flag status (flag status information), expands the hit request flag data, and stores the hit request flag data in the hit request flag storage area. And so on. The details of the symbol setting process will be described later with reference to FIG. 97, which will be described later.

Next, the main CPU 101 performs a start command generation / storage process (S206). In this process, the main CPU 101 generates start command data to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. The start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. The start command is configured to include parameters (sub-flags, etc.) that specify the internal winning combination and the like.

Next, the main CPU 101 performs the second interface board control process (S207). The second interface board control process is executed in the non-standard work area of the main RAM 103. The details of the second interface board control process will be described later with reference to FIG. 102 described later.

Next, the main CPU 101 performs a state-specific control process (S208). In this process, the main CPU 101 mainly performs a game start process (start process) according to the game state. The details of the state-specific control processing will be described later with reference to FIG. 104 described later.

Next, the main CPU 101 performs a reel stop initial setting process (S209). In this process, the main CPU 101 refers to the reel stop initial setting table (see FIG. 26), and sets the pull-in priority table selection table number, the pull-in priority table number, and the stop table number based on the internal winning combination and the game state. The process of acquiring, the process of storing "3" in the stop button non-operation counter, and the like are performed.

Next, the main CPU 101 performs a reel rotation start process (S210). In this process, the main CPU 101 requests the start of rotation of all reels. Then, when the start of rotation of all reels is requested, three stepping motors (not shown) are driven by an interrupt process (see FIG. 158 described later) executed at a constant cycle (1.1172 msec). Is controlled, and the rotation of the left reel 3L, the middle reel 3C, and the right reel 3R is started. Each reel is then accelerated and controlled until its rotational speed reaches a constant speed, after which it is controlled to maintain that constant speed.

Next, the main CPU 101 performs a reel rotation start command generation / storage process (S211). In this process, the main CPU 101 generates data for a reel rotation start command to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. The reel rotation start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. The reel rotation start command is configured to include a parameter indicating that the reel rotation start operation has been started.

Next, the main CPU 101 performs a pull-in priority storage process (S212). In this process, the main CPU 101 acquires the attraction priority data and stores it in the attraction priority data storage area. The details of the pull-in priority storage process will be described later with reference to FIG. 126 described later.

Next, the main CPU 101 performs a reel stop control process (S213). In this process, the main CPU 101 controls the rotation stop of the corresponding reel based on the timing at which the left stop button 17L, the middle stop button 17C, and the right stop button 17R are pressed and the internal winning combination. The details of the reel stop control process will be described later with reference to FIG. 138 described later.

Next, the main CPU 101 performs a winning search process (S214). In this process, the main CPU 101 stores the data in the symbol code storage area (see FIG. 35) in the winning operation flag storage area (see FIGS. 28 to 30). Further, in this process, the main CPU 101 determines whether or not the display combination is displayed on the effective line, and sets the number of medals to be paid out based on the determination result. The details of the winning search process will be described later with reference to FIG. 145, which will be described later.

Next, the main CPU 101 performs an illegal hit check process (S215). In this process, the main CPU 101 synthesizes a hit request flag (internal winning combination) and a winning operation flag (display combination), and determines whether or not there is an illegal hit error based on the combination result. The details of the illegal hit check process will be described later with reference to FIG. 148 described later.

Next, the main CPU 101 performs a winning check / medal payout process (S216). In this process, the main CPU 101 performs a process of generating a winning operation command. Further, in this process, the main CPU 101 drives the hopper device 51 and updates the number of credits based on the number of payouts of the display combination determined in S214, and performs the medal payout process. The details of the winning check / medal payout process will be described later with reference to FIG. 150 described later.

Next, the main CPU 101 performs a BB check process (S217). In this process, the main CPU 101 controls the operation and termination of the bonus state. The details of the BB check process will be described later with reference to FIG. 154 described later.

Next, the main CPU 101 performs an RT check process (S218). In this process, the main CPU 101 performs RT state transition control based on the symbol combination stopped and displayed on the effective line. The details of the RT check process will be described later with reference to FIGS. 155 and 156 described later.

Next, the main CPU 101 performs CZ / ART end processing (S219). In this process, the main CPU 101 mainly performs a pullback lottery process for CZ. The details of the processing at the end of CZ / ART will be described later with reference to FIG. 157 described later. Then, after the processing of S219 (after the end of one game), the main CPU 101 returns the processing to the processing of S201.

[Medal reception / start check processing]
Next, the medal acceptance / start check process performed in S202 in the main flow (see FIG. 82) will be described with reference to FIGS. 83 and 84. FIG. 83 is a flowchart showing the procedure of the medal acceptance / start check process, and FIG. 84 is a diagram showing an example of a source program for executing the processes of S231 to S233 during the medal acceptance / start check process. is there.

First, the main CPU 101 determines whether or not the value of the automatic insertion medal counter is "0" (whether or not there is an automatic insertion request) (S221). In this process, when the automatic insertion medal counter is "1" or more, the main CPU 101 determines that there is an automatic insertion request. Further, the automatic insertion medal counter is data for identifying whether or not the display combination related to the replay is established in the previous unit game. When the display combination related to the re-game is established, the number of medals inserted in the previous unit game is automatically inserted into the automatic insertion medal counter.

In S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is "0" (when the determination in S221 is YES), the main CPU 101 performs the process of S225 described later.

On the other hand, in S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is not "0" (when the determination in S221 is NO), the main CPU 101 performs the medal insertion process (S222). In this process, the main CPU 101 performs a medal insertion command generation / storage process, an LED lighting control process for the number of medals inserted, and the like. The details of the medal insertion process will be described later with reference to FIG. 85 described later.

Next, the main CPU 101 subtracts 1 from the value of the automatic insertion medal counter (S223). Next, it is determined whether or not the value of the automatically inserted medal counter after subtraction is "0" (S224).

In S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is not "0" (when the determination in S224 is NO), the main CPU 101 returns the process to the process of S222 and repeats the processes after S222.

On the other hand, in S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is "0" (when S224 is a YES determination), or when S221 is a YES determination, the main CPU 101 is used for medal auxiliary storage. The storage switch check process is performed (S225). In this process, the main CPU 101 detects whether or not the medal auxiliary storage 52 is full of medals based on the on / off state of the medal auxiliary storage switch 75.

Next, the main CPU 101 performs a medal insertion state check process (S226). Next, the main CPU 101 determines whether or not the medal can be inserted based on the result of the medal insertion state check process (S227).

When the main CPU 101 determines in S227 that the medal cannot be inserted (when the determination in S227 is NO), the main CPU 101 performs the process of S231 described later.

On the other hand, in S227, when the main CPU 101 determines that the medal insertion is possible (when the determination in S227 is YES), the main CPU 101 performs the medal insertion check process (S228). In this process, the main CPU 101 credits the medal, for example, based on the medal sensor input state, a process of determining whether or not the medal has passed normally, and when the number of medals inserted exceeds a specified number. Perform processing and so on. The details of the medal insertion check process will be described later with reference to FIG. 87 described later.

Next, the main CPU 101 determines whether or not the medal insertion or credit is possible based on the result of the medal insertion check process (S229).

When the main CPU 101 determines in S229 that the medal can be inserted or credited (when the determination in S229 is YES), the main CPU 101 performs the process of S231 described later. On the other hand, in S229, when the main CPU 101 determines that the medal cannot be inserted or credited (when the determination in S229 is NO), the main CPU 101 performs a medal acceptance prohibition process (S230). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medals are ejected from the medal payout outlet 24.

After the processing of S230, if S227 is a NO determination or S229 is a YES determination, the main CPU 101 determines whether or not the current number of inserted medals is the playable start number (S231). In this embodiment, the number of games that can be started is three (see FIGS. 28 to 30).

In S231, when the main CPU 101 determines that the current number of inserted medals is the number of playable start numbers (when the determination in S231 is YES), the main CPU 101 performs the process of S234 described later. On the other hand, in S231, when the main CPU 101 determines that the current number of inserted medals is not the playable start number (when the determination in S231 is NO), the main CPU 101 determines whether or not there is a medal inserted (S232). ).

In S232, when the main CPU 101 determines that a medal has been inserted (when the determination in S232 is YES), the main CPU 101 returns the process to S226 and repeats the processes after S226. On the other hand, in S232, when the main CPU 101 determines that no medal has been inserted (NO in S232), the main CPU 101 performs the setting change confirmation process described with reference to FIG. 68 (S233). In this process, the main CPU 101 performs a setting change command generation / storage process at the start of setting confirmation.

After the processing of S233 or when the determination in S231 is YES, the main CPU 101 determines whether or not the start switch 79 is in the ON state (S234).

When the main CPU 101 determines in S234 that the start switch 79 is not in the ON state (when the determination in S234 is NO), the main CPU 101 returns the process to S226 and repeats the processes after S226.

On the other hand, in S234, when the main CPU 101 determines that the start switch 79 is in the ON state (when the determination in S234 is YES), the main CPU 101 performs a medal acceptance prohibition process (S235). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medals are ejected from the medal payout outlet 24. Then, after the processing of S235, the main CPU 101 ends the medal acceptance / start check processing, and shifts the processing to S203 of the main flow (see FIG. 82).

In the present embodiment, the medal acceptance / start check process is performed as described above. Then, the processes of S231 to S233 during the above-mentioned medal acceptance / start check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 84. Among them, in the process of S233, the process is jumped to the address "SB_WVSC_00" of the execution program of the setting change confirmation process by the "CALLF" instruction which is the instruction code dedicated to the main CPU 101, and the setting change confirmation described with reference to FIGS. 68 and 69. Perform processing.

Then, the process of S233 during the above-mentioned medal acceptance / start check process, that is, the setting change confirmation process, is executed regardless of the game state. Therefore, in the present embodiment, regardless of the game state, that is, even if the game state is a bonus state (special prize operation state), the set value and the hall menu (various history data (error, power failure history, etc.)) are displayed. It can be confirmed, and fraudulent acts such as goto can be suppressed.

[Medal insertion process]
Next, with reference to FIGS. 85 and 86, the medal insertion process performed in S222 during the medal acceptance / start check process (see FIG. 83) will be described. FIG. 85 is a flowchart showing the procedure of the medal insertion process, and FIG. 86 is a diagram showing an example of a source program for executing the medal insertion process.

First, the main CPU 101 adds "1" to the value of the medal counter (S241). The medal counter is a counter for counting the number of inserted medals, and is provided in the main RAM 103.

Next, the main CPU 101 performs a medal insertion command generation / storage process (S242). In this process, the main CPU 101 generates data of a medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. That is, the medal insertion command is transmitted from the main control circuit 90 to the sub control circuit 200 each time one medal is inserted. The medal insertion command is configured to include parameters for specifying the number of inserted medals and the like.

Next, the main CPU 101 turns off the first to third LEDs for displaying the number of inserted medals included in the LED 82 (see FIG. 7) (S243). Next, the main CPU 101 calculates LED lighting data (lighting control data) corresponding to the number of inserted medals based on the number of inserted medals (value of the medal counter) (S244). In this process, for example, when the number of inserted medals is one, the LED lighting data for lighting only the first LED for displaying the number of inserted medals is calculated, and for example, when the number of inserted medals is three. LED lighting data for lighting all of the first to third LEDs for displaying the number of inserted medals is calculated. The method for calculating the LED lighting data will be described in detail later.

Next, the main CPU 101 uses the calculated LED lighting data to light the corresponding LED for displaying the number of inserted medals (S245). Then, after the processing of S245, the main CPU 101 ends the medal insertion processing, and shifts the processing to S223 of the medal acceptance / start check processing (see FIG. 83).

In the present embodiment, the medal insertion process is performed as described above. The medal insertion process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 86. Among them, in the process of S244, the LED lighting data for displaying the number of inserted medals is generated not by the loop process referring to the table but by the arithmetic process. This arithmetic processing is performed by sequentially executing the source codes "LD A, L" to "OR L" in the source program shown in FIG. 86 by the main CPU 101.

In this arithmetic processing, first, by executing the source code "LDA, L", the data of the number of inserted medals stored in the L register is stored in the A register. For example, when the number of inserted medals is 3, "00000011B" (decimal number "3") is stored in the A register. In the present embodiment, the 1-byte data is described as "***** B", but the last character "B" is "0" or "1" indicated before the character "B". Means that it is bit data.

Next, by executing the source code "ADD A, A", the data stored in the A register is added to the data stored in the A register, and the addition result is stored in the A register. For example, when the data stored in the A register before the execution of this "ADD" instruction is "00000011B" (when the number of inserted medals is 3), this "ADD" instruction causes the addition result. "00000011B" is stored in the A register.

Next, by executing the source code "DEC A", the data stored in the A register is subtracted by 1, and the subtraction result is stored in the A register. For example, if the data stored in the A register before the execution of the "DEC" instruction is "0000001110B", the subtraction result "000000101B" is stored in the A register by this "DEC" instruction. ..

Next, by executing the source code "OR L", a logical sum operation is performed between the data stored in the L register (the number of medals inserted) and the data stored in the A register, and the calculation result is stored in the A register. Stored. For example, when the data stored in the A register is "000000101B" and the data stored in the L register is "00000011B" before the execution of this "OR" instruction (the number of medals inserted is three). In this case, the "OR" instruction stores "000000111B", which is the result of the OR operation of both data, in the A register. Then, the data stored in the A register by executing the "OR" command becomes the LED lighting data for displaying the number of inserted medals (data indicating the lighting state of the inserted medal LED).

For example, when the number of inserted medals is 3, as described above, the final calculation result "000000111B" is for displaying the number of inserted medals by the calculation process of the LED lighting data for displaying the number of inserted medals in S244. It becomes LED lighting data. Then, in the present embodiment, "1/0" of bit 0 of the finally calculated LED lighting data is "on / off" of the output port to the LED (first LED) for displaying the number of inserted medals of the first piece. Corresponding to the "1/0" state of bit 1, corresponds to the "on / off" state of the output port to the LED (second LED) for displaying the number of inserted medals of the second piece, and "1" of bit 2. "/ 0" corresponds to the "on / off" state of the output port to the LED (third LED) for displaying the number of inserted medals. Therefore, when the number of inserted medals is 3, as described above, "000000111B" is generated as the LED lighting data, so that all the output ports of the first to third LEDs for displaying the number of inserted medals are displayed. It is set to the on state, and all the first to third LEDs for displaying the number of inserted medals are turned on.

When the LED lighting data for displaying the number of inserted medals is generated by arithmetic processing as described above, the table data referred to when generating the LED lighting data for displaying the number of inserted medals is not required, so that the table area of the main ROM 102 It is possible to increase the free space of the LED and minimize the increase in the capacity of the program. That is, in the above-mentioned medal insertion process of the present embodiment, the process of displaying the medal insertion LED can be made more efficient, the free space of the main ROM 102 is secured (increased), and the increased free area is utilized. It becomes possible to enhance the playability.

[Medal insertion check process]
Next, the medal insertion check process performed in S228 during the medal acceptance / start check process (see FIG. 83) will be described with reference to FIGS. 87 and 88. FIG. 87 is a flowchart showing the procedure of the medal insertion check process, and FIG. 88 is a diagram showing an example of a source program for executing the processes of S255 to S258 during the medal insertion check process.

First, the main CPU 101 determines whether or not the game is being replayed (S251).

When the main CPU 101 determines in S251 that the game is being replayed (when the determination in S251 is YES), the main CPU 101 ends the medal insertion check process and performs the medal acceptance / start check process (see FIG. 83). Move to S229.

On the other hand, in S251, when the main CPU 101 determines that the replay is not in progress (when the determination in S251 is NO), the main CPU 101 permits medal acceptance (S252). In this process, the solenoid of the selector 66 (see FIG. 4) is driven, and medals inserted from the medal insertion slot 14 are accepted. The accepted medals are counted and then guided to the hopper device 51.

Next, the main CPU 101 performs a bet button check process (S253). In this process, the main CPU 101 determines whether or not the bet button (MAX bet button 15a or 1-bet button 15b) has been operated based on the ON / OFF state of the BET switch 77. Next, the main CPU 101 determines whether or not the betting operation is completed based on the result of the betting button check processing in S253 (S254).

When the main CPU 101 determines in S254 that the betting operation has been completed (when the determination in S254 is YES), the main CPU 101 ends the medal insertion check process and performs the medal acceptance / start check process (see FIG. 83). Move to S229.

On the other hand, in S254, when the main CPU 101 determines that the betting operation has not been completed (when the determination in S254 is NO), the main CPU 101 determines that the medal sensor input state (game medium reception state) at the time of the current processing. Acquires the medal sensor input state at the time of the previous processing (S255). The medal sensor input state is information indicating the passing status of the medal received in the medal insertion slot 14 in the selector 66, and is the detection result of each medal sensor (not shown) provided at the entrance and the exit of the selector 66. Is generated by.

In the present embodiment, the medal sensor input state is represented by 1 byte (8 bits) of data, and the upstream first medal sensor (not shown) provided at the exit of the selector 66 side by side in the medal passing direction. The detection result corresponds to the bit 0 information ("0" or "1"), and the detection result of the second medal sensor (not shown) on the downstream side corresponds to the bit 1 information ("0" or "1"). To do. When the passage of the medal is detected by the first medal sensor, "1" is set in bit 0, and when the passage of the medal is detected by the second medal sensor, "1" is set in bit 1. Will be done. Therefore, the medal sensor input state "0000000000B" indicates the state before or after passing the medal (at the time of passing), and the medal sensor input state "00000001B" indicates the state at the start of passing the medal, and the medal sensor input state "0000000000B". "00000011B" indicates a state in which the medal is passing, and "00000010B" in the medal sensor input state indicates a state immediately before the completion of passing the medal.

Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current processing has changed from the medal sensor input state at the time of the previous processing (S256).

In S256, when the main CPU 101 determines that the medal sensor input state at the time of the current processing has not changed from the medal sensor input state at the time of the previous processing (when the determination in S256 is NO), the main CPU 101 is described in S261 described later. Perform processing.

On the other hand, in S256, when the main CPU 101 determines that the medal sensor input state at the time of the current processing has changed from the medal sensor input state at the time of the previous processing (when the determination in S256 is YES), the main CPU 101 is at the time of the previous processing. Based on the medal sensor input state, a normal value (normal change value) of the medal sensor input state obtained at the time of the current processing is generated by arithmetic processing (S257).

In this process, when the medal sensor input state at the time of the previous process is "0000000000B" (when both the first and second medal sensors have not detected medals), it is regarded as a normal change value of the medal sensor input state. When "00000001B" (when the first medal sensor detects medals and the second medal sensor does not detect medals) is generated and the medal sensor input state at the time of the previous processing is "00000001B", the medal sensor "00000011B" (when both the first and second medal sensors are medal detection) is generated as a normal change value of the input state. Further, in this process, when the medal sensor input state at the time of the previous process is "00000011B", the normal change value of the medal sensor input state is "00000010B" (the first medal sensor has not detected a medal, and the second (When the medal sensor is medal detection) is generated, and when the medal sensor input state at the time of the previous processing is "00000010B", the normal change value of the medal sensor input state is "0000000000B" (first and second medals). If both sensors do not detect medals) is generated. The method of generating (calculating) the normal change value of the medal sensor input state will be described in detail later.

Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current processing is the same as the normal change value generated in S257 (S258). In this determination process, it is determined whether or not a medal retrograde error has occurred, and if the determination condition of S258 is not satisfied, the main CPU 101 determines that a medal retrograde error has occurred.

In S258, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is not the same as the normal change value generated in S257 (when the determination in S258 is NO), the main CPU 101 performs the processing of S262 described later. Do.

On the other hand, in S258, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is the same as the normal change value generated in S257 (when the determination in S258 is YES), the main CPU 101 is at the time of the current processing. It is determined whether or not the medal sensor input state of the above is the state at the time of passing the medal (“00000000B”) (S259). In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current process is the state at the time of passing the medal (when the determination in S259 is YES), the main CPU 101 performs the process of S263 described later.

In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current processing is not the state at the time of passing the medal (when the determination in S259 is NO), the main CPU 101 sets the medal passing check timer (S260). The time set in the medal passage check timer in this process can be set to any time as long as it is possible to determine whether or not the medal has passed the selector 66. Further, the timer value set in this process may be changed according to, for example, the medal sensor input state at the time of the current process.

After the processing of S260 or when the determination of S256 is NO, whether or not the medal sensor input state at the time of the current processing is the medal passing state (“000000111B”) and the medal passing check timer is stopped. (S261). In this determination process, it is determined whether or not a medal passing error (inserted medal passing time error) has occurred, and if the determination condition of S261 is satisfied, the main CPU 101 determines that a medal passing error has occurred.

When the main CPU 101 determines in S261 that the determination condition of S261 is not satisfied (when the determination in S261 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253.

On the other hand, in S261, when the main CPU 101 determines that the determination condition of S261 is satisfied (when S261 is a YES determination), or when S258 is a NO determination, that is, a medal passing error or a medal retrograde error has occurred. If it is determined, the main CPU 101 performs error processing (S262). In this process, the main CPU 101 performs various processes when an error occurs, such as an error command generation and storage process. The details of error handling will be described later with reference to FIG. 89 described later. Then, after the processing of S262, the main CPU 101 returns the processing to the processing of S253, and repeats the processing after S253.

Here, returning to the process of S259 again, if S259 is a YES determination, the main CPU 101 determines whether or not a specified number of medals (three medals in this embodiment) have already been inserted (S263). ..

In S263, when the main CPU 101 determines that the specified number of medals have not been inserted (NO in S263), the main CPU 101 performs the medal insertion process described with reference to FIG. 85 (S264). Then, after the processing of S264, the main CPU 101 returns the processing to the processing of S253, and repeats the processing after S253.

On the other hand, in S263, when the main CPU 101 determines that a specified number of medals have already been inserted (when the determination in S263 is YES), the main CPU 101 adds "1" to the value of the credit counter (S265). ). Next, the main CPU 101 performs a medal insertion command generation / storage process (S266). In this process, the main CPU 101 generates data of a medal insertion command to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158.

Next, the main CPU 101 determines whether or not the number of credits of the medal is the upper limit value (50 in the present embodiment) based on the value of the credit counter (S267).

In S267, when the main CPU 101 determines that the number of credits for medals is not the upper limit value (when the determination in S267 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253. On the other hand, in S267, when the main CPU 101 determines that the number of credits of medals is the upper limit value (when the determination in S267 is YES), the main CPU 101 ends the medal insertion check process and performs the medal acceptance / start check process. The process moves to S229 (see FIG. 83).

In the present embodiment, the medal insertion check process is performed as described above. Then, the processes of S255 to S258 during the above-mentioned medal insertion check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 88. Among them, the process of generating the normal change value of the medal sensor input state of S257 is performed not by the process of referencing and acquiring the table, but by the arithmetic process. Specifically, the normal change value generation process is performed by the main CPU 101 executing the source codes "RLA" and "AND cBX_MDINSW" in the source program shown in FIG. 88 in this order.

The "RLA" instruction is an instruction code that shifts the 1-byte data stored in the A register to the left (in the direction from bit 0 to bit 7) once (by 1 bit). In the example shown in FIG. 88, the 1-byte data indicating the previous medal sensor input state stored in the A register by the source code “LDA, B” executed before the “RLA” instruction is the “RLA” instruction. Shifts to the left once. At this time, the bit data newly stored in bit 0 is determined based on the execution result of the source code "CP cBX_MDISW2" executed before the "RLA" instruction.

The "CP" instruction is an instruction code that executes a comparison operation. Further, "cBX_MDISW2" is 1 byte of data, and is "00000010B" in this embodiment. When the source code "CP cBX_MDISW2" is executed, 1-byte data indicating the previous medal sensor input state stored in the A register is compared with "cBX_MDISW2 (00000010B)".

Then, as a result of executing the source code "CP cBX_MDISW2", if the result that the 1-byte data indicating the previous medal sensor input state is less than "cBX_MDISW2 (00000010B)" is obtained, the carry flag of the flag register F is obtained. (See FIG. 11) is set to "1", and when the "RLA" instruction is executed, the carry flag "1" of the flag register F is stored in bit 0 of the A register. On the other hand, as a result of executing the source code "CP cBX_MDISW2", if the result that the 1-byte data indicating the previous medal sensor input state is "cBX_MDISW2 (00000010B)" or more is obtained, the carry flag of the flag register F is obtained. (See FIG. 11) is set to "0", and when the "RLA" instruction is executed, the carry flag "0" of the flag register F is stored in bit 0 of the A register.

Therefore, for example, if the 1-byte data indicating the previous medal sensor input state is "0000000000B (state before or after passing the medal (when passing))" (<"cBX_MDISW2"), the "RLA" command is issued. By execution, "00000001B" is generated, and if the 1-byte data indicating the previous medal sensor input state is "00000001B (state at the start of medal passage)" (<"cBX_MDISW2"), the "RLA" command is executed. Will generate "00000011B". On the other hand, for example, if the 1-byte data indicating the previous medal sensor input state is "000000111B (state during medal passing)" (> "cBX_MDISW2"), "00000011B" is generated by executing the "RLA" instruction. If the 1-byte data indicating the previous medal sensor input state is "00000010B (state immediately before the completion of medal passage)" (= "cBX_MDISW2"), "00000100B" is generated by executing the "RLA" command. To.

Next, when the source code "AND cBX_MDINSW" is executed, the 1-byte data (stored data in the A register) generated by executing the "RLA" instruction is logically stacked with the 1-byte data "cBX_MDINSW", and the medal sensor. The normal change value of the input state is calculated. The 1-byte data "cBX_MDISW" is "00000011B" in this embodiment. Therefore, when the source code "AND cBX_MDINSW" is executed, only the data of bit 0 and bit 1 in the stored data of the A register is masked, and the other bit data becomes "0".

As a result, for example, if the 1-byte data indicating the previous medal sensor input state is "00000000000B (state before passing the medal)", the normal change value of the medal sensor input state is "00000001B (state at the start of passing the medal)". ) ”Is generated, and if the 1-byte data indicating the previous medal sensor input state is“ 00000001B (state at the start of medal passage) ”, the normal change value of the medal sensor input state is“ 000000111B (during medal passing). State) ”is generated. On the other hand, for example, if the 1-byte data indicating the previous medal sensor input state is "000000111B (state during medal passing)", the normal change value of the medal sensor input state is "00000010B (state immediately before the completion of medal passage)". Is generated, and if the 1-byte data indicating the previous medal sensor input state is "00000010B" (the state immediately before the completion of passing the medal), the normal change value of the medal sensor input state is "0000000000B (after passing the medal (passing)). Time) state) ”is generated.

As described above, by changing the detection process of the change mode of the medal sensor input state from the table reference process to the arithmetic process, the free space of the table storage area of the main ROM 102 can be increased and the capacity of the program can be increased. Can be minimized. Therefore, by adopting the above-mentioned method, it is possible to improve the efficiency of the detection process of the medal insertion sensor state, and it is possible to improve the playability by utilizing the increased free space in the main ROM 102.

[Error handling]
Next, with reference to FIGS. 89 and 90, for example, the error processing performed in S262 during the medal insertion check processing (see FIG. 87) will be described. FIG. 89 is a flowchart showing an error processing procedure, and FIG. 90 is a diagram showing an example of the configuration of an error table actually referred to on the error processing source program.

In the error table shown in FIG. 90, for each 1-byte data (for example, 1-byte data stored in the address “dERR_HE” in FIG. 90) indicating the on / off state of the port indicating the type of the error factor, Error display data (for example, 1-byte data stored in the addresses "dERR_HE + 1" and "dERR_HE + 2" in FIG. 90) is defined. This error display data is output to the 2-digit 7-segment LED (both for displaying the number of payouts and for displaying the error) included in the information display 6.

First, the main CPU 101 turns off the medal solenoid (S271). Specifically, the main CPU 101 stops driving the solenoid of the selector 66 (see FIG. 7). Next, the main CPU 101 saves the medal payout number display data (S272).

Next, the main CPU 101 performs an error table setting process (S273). By this process, the start address of the error table shown in FIG. 90 is set on the source program.

Next, the main CPU 101 acquires an error factor (S274). The error factor acquired in this process changes according to the process in which the error process currently being processed is read. As shown in FIG. 90, the error factors targeted in this embodiment include "hopper empty error", "hopper jam error", "inserted medal passing count error", "inserted medal passing check error", and "" "Insert medal passage check error", "Insert medal passage time error", "Insert medal retrograde error", "Insert medal auxiliary storage full error", and "Illegal hit error" are specified. For example, when the error processing is read after the processing of S258 during the medal insertion check processing, the “inserted medal retrograde error (Cr)” in FIG. 90 is acquired as an error factor in this processing. Further, for example, when the error process is read after the process of S261 during the medal insertion check process, the "inserted medal passing time error (CE)" in FIG. 90 is acquired as an error factor in this process. ..

Next, the main CPU 101 acquires error display data from the error table and the error cause (S275). For example, when the error factor is "insertion medal retrograde error (Cr)", the error shown in FIG. 90 is used as the error display data to be output to the upper digit 7-segment LED among the 2-digit 7-segment LEDs in this process. The 1-byte data "001001110B" stored in the address "dERR_CR + 1" in the table is acquired, and the 1-byte data "00000101B" stored in the address "dERR_CR + 2" is used as error display data to be output to the lower digit 7-segment LED. Is acquired. In this case, the two characters "Cr" are displayed as error information on the two-digit 7-segment LED.

Next, the main CPU 101 performs an error command (generation) generation and storage process (S276). In this process, the main CPU 101 generates data of an error command when an error occurs, which is transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. .. The error command when an error occurs stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. The error command when an error occurs includes a parameter indicating that an error has occurred.

Next, the main CPU 101 performs a standby process for an interrupt time (1.1172 ms) (S277). Next, the main CPU 101 determines whether or not the error has been cleared (S278).

When the main CPU 101 determines in S278 that the error has not been cleared (when the determination in S278 is NO), the main CPU 101 returns the process to the process in S277 and repeats the processes after S277.

On the other hand, in S278, when the main CPU 101 determines that the error has been cleared (when the determination in S278 is YES), the main CPU 101 performs an error factor clearing process (S279). This process is performed in a non-standard work area of the main RAM 103. Next, the main CPU 101 performs a restoration process of the payout number display data of the medals saved in S272 (S280).

Next, the main CPU 101 performs an error command (release) generation and storage process (S281). In this process, the main CPU 101 generates data of an error command at the time of error cancellation to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 75B) provided in the main RAM 103. .. The error command at the time of canceling the error stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. The error command at the time of error cancellation includes a parameter indicating error cancellation. Then, after the processing of S281, the main CPU 101 ends the error processing, and shifts the processing to, for example, S253 during the medal insertion check processing (see FIG. 87). In the error release, the generated error factor is released, and the error state is released by pressing the reset switch 76.

[Random number acquisition process]
Next, with reference to FIG. 91, the random number acquisition process performed in S203 in the main flow (see FIG. 82) will be described. Note that FIG. 91 is a flowchart showing the procedure of the random number acquisition process.

First, the main CPU 101 acquires a hard latch random number (0 to 65535) of the random number register 0 of the random number circuit, and uses the acquired random number value as a random number value for internal winning combination lottery, and uses a random number value storage area (non-standard) in the main RAM 103. It is stored in (shown) (S291).

Next, the main CPU 101 generates soft latch random numbers (0 to 65535: random numbers for production used in ART-related lottery processing, random numbers in 0 to 255: 1-byte lottery processing) of random number registers 1 to 7 of the random number circuit. The soft latch random number acquisition register is set for this purpose (S292). Next, the main CPU 101 sets the acquisition number (for example, 7) of the soft latch random numbers (S293).

Next, the main CPU 101 collectively acquires the number of acquired soft latch random numbers, and stores the acquired number of soft latch random numbers in the random number value storage area (S294). At this time, the soft latch random number (effect random number value, 2-byte random number value) acquired from the random number register 1 of the random number circuit 110 is the hardware acquired from the random number register 0 of the random number circuit in the random number value storage area. It is stored in an area different from the area in which the latch random number (random number value for the internal winning combination lottery) is stored. Then, after the processing of S294, the main CPU 101 ends the random number acquisition processing and shifts the processing to S204 of the main flow (see FIG. 82). In the present embodiment, in order to store four 2-byte random numbers and four 1-byte random numbers, a 12-byte storage area is allocated to the main RAM 103 as a random number storage area.

[Internal lottery processing]
Next, the internal lottery process performed in S204 in the main flow (see FIG. 82) will be described with reference to FIGS. 92 to 96. 92 is a flowchart showing the procedure of the internal lottery process, FIG. 93A is a diagram showing an example of a source program for executing the processes of S302 to S305 during the internal lottery process, and FIG. 93B is a diagram showing an example of the source program. It is a figure which shows an example of the source program for executing the process of S308-S309 in the internal lottery process.

Further, FIG. 94 is a diagram showing an example of the configuration of an internal lottery table (for general game) that is actually referred to on the source program of the internal lottery process, and FIG. 95 is a diagram on the source program of the internal lottery process. It is a figure which shows an example of the structure of the lottery value selection table by RT state which is actually referred. Further, FIG. 96 shows an internal lottery value table selection table, a 1-byte internal lottery value table, a 2-byte internal lottery value table, a 2-byte internal lottery value table, and an internal lottery value table for each 1-byte setting that are actually referred to on the source program of the internal lottery process. It is a figure which shows an example of the structure of the internal lottery value table by 2 byte setting. In the present embodiment, an internal lottery table for RB (BB) is also provided, but here, the configuration of the internal lottery table for RB referred to on the source program of the internal lottery process is shown. Omit.

First, the main CPU 101 performs a set value / medal insertion number check process (S301). In this process, the main CPU 101 checks the set value (any of 1 to 6) of the current game and the number of inserted medals (3 in the present embodiment).

Next, the main CPU 101 sets the internal lottery table for general games and the number of lottery (53 times in this embodiment) (S302). In this process, the value (winning request flag status) of the "special prize winning number + small winning combination winning number" in the internal lottery table (for general game) shown in FIG. 94 is set in the C register, and the "lottery value selection table or The value of the lottery coefficient table (judgment data: data related to the address) is set in the A register. As shown in FIG. 94, the winning request flag status is set to the special prize winning number ("00H (off)", "01H (BB1)", "02H (BB2)": decimal number 0, 1, 2). "25H (decimal number: 37 in decimal number (special prize number described later)) multiplied by the small winning combination winning number (" 00H "to" 24H ": 0 to 36 in decimal number) is added. ..

Next, the main CPU 101 determines whether or not the RB is in operation (S303). When the main CPU 101 determines in S303 that the RB is not in operation (when the determination in S303 is NO), the main CPU 101 performs the process of S305 described later.

On the other hand, when the main CPU 101 determines in S303 that the RB is in operation (when the determination in S303 is YES), the main CPU 101 sets the internal lottery table for RB and the number of lottery (5 times in this embodiment). Set (S304). In this process, the internal lottery table and the number of lottery for general games set in S302 are overwritten by the internal lottery table and the number of lottery for RB.

After the processing of S304 or when the determination in S303 is NO, the main CPU 101 acquires the determination data (data related to the address) of the lottery target combination from the set internal lottery table, and updates the lottery table address (S305).

Next, the main CPU 101 determines whether or not the determination data is RT state-specific data (S306). In this process, the main CPU 101 determines whether or not the currently acquired lottery target combination is an internal winning combination whose lottery value changes according to the RT state. Specifically, the main CPU 101 determines whether or not the address defined in the currently acquired lottery target combination determination data is the address in the lottery value selection table for each RT state shown in FIG. 95. ..

For example, in the determination data "(dRPPTR01-dRTRB_SEL) * 2 + 001H" associated with the internal winning combination "F_chililip" in the internal lottery table of FIG. 94, the internal winning in the lottery value selection table for each RT state shown in FIG. 95 Since the address "dRPPTR01" of the combination "F_chilip" is defined, the determination data associated with the internal winning combination "F_chilip" corresponds to the RT state-specific data. Therefore, when the currently acquired lottery target combination is the internal winning combination “F_Chillilip”, the main CPU 101 determines that the determination data is the RT state-specific data in the processing of S306.

In S306, when the main CPU 101 determines that the determination data is not the RT state-specific data (when the determination in S306 is NO), the main CPU 101 performs the process of S308 described later. On the other hand, in S306, when the main CPU 101 determines that the determination data is the data for each RT state (when the determination in S306 is YES), the main CPU 101 selects the RT state lottery value shown in FIG. 95 based on the determination data. Selection data is acquired from the table, and the acquired selection data is set in the determination data (S307).

After the processing of S307 or when the determination in S306 is NO, the main CPU 101 determines whether or not the determination data of the lottery target combination is the data for each setting (S308). In this process, the main CPU 101 determines whether or not the currently acquired lottery target combination is an internal winning combination whose lottery value changes according to the set value. Specifically, in the main CPU 101, the address defined in the currently acquired lottery target combination determination data is in the internal lottery value table for each 1-byte setting or the internal lottery value table for each 2-byte setting shown in FIG. It is determined whether or not the address is.

For example, in the determination data "((dNMLB00F289-dPRB_DB_WV) / 06H) * 2 + 080H" associated with the internal winning combination "F_strong Chile 1" in the internal lottery table of FIG. Since the address "dNMLB00F289" of the internal winning combination "F_strong Chile 1" in the lottery value table is specified, the judgment data associated with the internal winning combination "F_strong Chile 1" corresponds to the data for each setting. To do. Therefore, when the currently acquired lottery target combination is the internal winning combination “F_strong dust 1”, the main CPU 101 determines that the determination data is the setting-specific data in the process of S308.

In S308, when the main CPU 101 determines that the determination data is not the setting-specific data (when the determination in S308 is NO), the main CPU 101 performs the process of S310 described later. On the other hand, in S308, when the main CPU 101 determines that the determination data is the data for each setting (when the determination in S308 is YES), the main CPU 101 adds the set value data (any of 0 to 5) to the determination data. Then, the added value is set in the determination data (S309). The set value data added to the determination data in this process is the data associated with the set value, but the set value data "0" to "5" are not the values of the set value itself, but are "0" to "5", respectively. It is the data corresponding to "setting 1" to "setting 6".

After the processing of S309 or when the determination in S308 is NO, the main CPU 101 calculates the address of the area in which the lottery value of the lottery target combination is stored based on the set determination data (address data), and sets the address to the address. The stored lottery value is acquired (S310).

In the processing of S310, for example, when the lottery target combination is the internal winning combination “F_Sabo 2” whose lottery value does not depend on both the RT state and the set value, the 1-byte internal lottery value table shown in FIG. 96. The lottery value "128" stored in the address "dNM_B00F26" is acquired from. Further, for example, when the lottery target combination is the internal winning combination "F_RT3 lip_1st" whose lottery value changes depending on the RT state and the RT state is the RT2 state, the 2-byte internal lottery value table shown in FIG. The lottery value "1800" stored in the address "dRT2B00F13456" is acquired from.

Further, in the processing of S310, for example, when the lottery target combination is the internal winning combination “F_strong chili 1” whose lottery value changes depending on the set value, the internal lottery value table for each 1-byte setting shown in FIG. 96. From the six types of lottery values "150 (setting 1), 150 (setting 2), 150 (setting 3), 150 (setting 4), 160 (setting 5), 170 (setting 6)" specified in The lottery value corresponding to the set value is acquired. At this time, the lottery value corresponding to the set value is acquired by adding the set value data to the determination data (processing in S309) and designating the obtained address. Therefore, for example, when the lottery target combination is "F_strong chili 1" and the set value is "6" (set value data is "5"), the lottery value "dNMLB00F289 + 5" stored in the address "dNMLB00F289 + 5" 170 "is acquired.

In the present embodiment, in the case of a combination whose lottery value depends on both the RT state and the set value, such as the internal winning combination "F_maintenance lip A", the internal lottery value table and the internal lottery by setting are used. The lottery value is obtained by referring to both of the value tables.

Next, the main CPU 101 acquires a random number value (any of 0 to 65535) for the internal winning combination lottery stored in the random number storage area (S311).

Next, the main CPU 101 performs a lottery execution process (S312). In this process, the main CPU 101 adds the random number value acquired in S311 to the lottery value acquired in S310, and sets the addition result as the lottery result (winning / non-winning of the lottery target combination). In this lottery execution process, when the sum of the lottery value and the random number value exceeds 65535 (overflow), it is determined that the lottery target combination has been won (the lottery target combination has been determined as the internal winning combination). To.

Next, the main CPU 101 stores a value obtained by adding the lottery value to the random number value (random number value after the lottery execution) as a new random number value in the random number storage area (S313). Next, the main CPU 101 determines whether or not the lottery execution process has won (whether or not an overflow has occurred) (S314).

In S314, when the main CPU 101 determines that the winning is won in the lottery execution process (when the determination in S314 is YES), the main CPU 101 refers to the internal lottery table and refers to the winning request flag status (corresponding to the winning internal winning combination). The value of "special prize winning number + small winning combination winning number") is acquired (S315). For example, in a general game, if a winning combination is won in the lottery execution process when the lottery target combination is "F_certain chili lip", in the processing of S315, the winning request flag status "(00H * 25H) + 02H" (special prize winning number =). 0, small winning combination number = 2) is acquired. Then, after the processing of S315, the main CPU 101 ends the internal lottery processing, and shifts the processing to S205 of the main flow (see FIG. 82).

On the other hand, in S314, when the main CPU 101 determines that the lottery has not been won in the lottery execution process (when the determination in S314 is NO), the main CPU 101 updates the lottery target combination to the next combination in the internal lottery table, and draws the lottery. The number of times is subtracted by 1 (S316). Next, the main CPU 101 determines whether or not the number of lottery after subtraction is "0" (S317).

In S317, when the main CPU 101 determines that the number of lottery after subtraction is not "0" (when the determination in S317 is NO), the main CPU 101 returns the process to the process of S305 and repeats the processes after S305.

On the other hand, in S317, when the main CPU 101 determines that the number of lottery after subtraction is "0" (when the determination in S317 is YES), that is, when the internal winning combination is "missing", the main CPU 101 determines. Set the loss status (S318). The "missing status" corresponds to the winning request flag status in which both the special prize winning number and the small winning combination winning number are "0". Then, after the processing of S318, the main CPU 101 ends the internal lottery processing, and shifts the processing to S205 of the main flow (see FIG. 82).

In the present embodiment, the internal lottery process is performed as described above. The processes S302 to S305 during the internal lottery process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 93A. Among them, the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 93A.

On the source program, for example, when the source code "LDIN ss, (HL)" is executed, the memory specified by the address set in the HL register (pair register) and the address obtained by adding "1" to the address. The contents (data) of are loaded into the ss (BC, DE, AC, AE or BD) pair register, and the address set in the HL register is updated by +2 (2 addition). Therefore, when the source code "LDIN AC, (HL)" in FIG. 93A is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( Data) is loaded into the AC register, and the address set in the HL register is updated by +2 (addition of 2). In the determination data acquisition process of S305, as described above, the determination data (value of "lottery value selection table or lottery coefficient table") is stored in the A register by this "LDIN" instruction (predetermined read instruction). It is stored, and the request flag status (value of "special prize winning number + small winning combination winning number") is stored in the C register.

As described above, in the determination data acquisition process of S305 during the internal lottery process, both the data load process and the address update process can be performed by one instruction code (“LDIN” instruction). In this case, the instruction code related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, the processes of S308 and S309 during the internal lottery process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 93B. Among them, in the addition process of the set value data (any of 0 to 5) of S309, the main CPU 101 uses the source codes "MUL A, 6" and "ADDQ A, (.LOW.wWAVENUM)" in FIG. 93B. It is performed by executing in this order. Both the "MUL" instruction and the "ADDQ" instruction are instruction codes dedicated to the main CPU 101, and the "ADDQ" instruction is an instruction code dedicated to the main CPU 101 that specifies an address using a Q register (extension register).

When, for example, the source code "MUL A, n" is executed on the source program, the stored data in the A register is multiplied by the 1-byte integer n, and the multiplication result is stored in the A register. Therefore, in the source code "MUL A, 6" in FIG. 93B, the contents (stored data) of the A register are multiplied by a 1-byte integer 6, and the multiplication result is stored in the A register. This multiplication process is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, since the pachi-slot machine 1 of the present embodiment is provided with a dedicated calculation circuit (calculation circuit 107) for executing multiplication processing and division processing on the source program, the efficiency of multiplication processing and division processing should be improved. Can be done.

Further, for example, when the source code "ADDQ r, (k)" is executed on the source program, the stored data (upper address value) of the Q register and the 1-byte integer k (direct value: lower address value) are executed. The stored data of the r register (A, B, C, D, E, H or L register) is added to the memory contents (stored data) of the address specified by), and the addition result is stored in the r register. To. Therefore, when the source code "ADDQ A, (.LOW.wWAVENUM)" in FIG. 93B is executed, the stored data of the Q register and the memory of the address specified by the 1-byte integer value ".LOW.wWAVENUM". The contents (stored data) of the A register are added to the contents (set value data) of, and the addition result is stored in the A register.

That is, in the example shown in FIG. 93B, in the addition process of the set value in S309, the lottery target combination is obtained by multiplying the relative value for lottery table selection by the coefficient "6" and adding the set value data to the multiplied value. The address of the lottery table in which the lottery value of is stored is calculated.

As described above, in the present embodiment, the main CPU 101 dedicated instruction code (“ADDQ” instruction) using the Q register (extension register) is used in the internal lottery process, and if this instruction code is used, the direct value is used. This allows access to the main ROM 102, the main RAM 103, and the memory map I / O. Therefore, the instruction related to the address setting can be omitted on the source program of the internal lottery processing, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Design setting process]
Next, the symbol setting process performed in S205 in the main flow (see FIG. 82) will be described with reference to FIGS. 97 to 100.

FIG. 97 is a flowchart showing the procedure of the symbol setting process. FIG. 98 is a correspondence table between the special prize (bonus) winning number and the small winning combination winning number and the internal winning combination. In FIG. 98, the special prize winning number and the small winning combination winning number corresponding to "missing (00)" are not shown. Further, FIG. 99 is a diagram showing an example of a source program for executing the processes of S324 to S330 during the symbol setting process, and FIG. 100 is a hit actually referred to on the source program of the symbol setting process. It is a figure which shows an example of the structure of the request flag table (flag data table, winning flag table data).

First, the main CPU 101 extracts a special prize winning number and a small winning combination winning number based on the winning request flag status acquired by the internal lottery process, and extracts the extracted special winning winning number and the small winning combination winning number in the main RAM 103. It is stored in the winning number storage area (not shown) (S321).

In the present embodiment, as shown in FIG. 98, the special prize (bonus) winning numbers "1" and "2" are associated with the internal winning combinations "F_BB1" and "F_BB2", respectively. Further, the small winning combination "1" to "36" are associated with the internal winning combination "F_chili lip" to "F_RB combination 4", respectively. Then, as described with reference to FIG. 94, the value of the winning request flag status is obtained by multiplying the special prize winning number by the special prize number (“37 (25H in hexadecimal number)” in the present embodiment) and multiplying the value by the small winning combination winning number. It is the added value. Therefore, in the process of S321, since the special prize winning number and the small winning combination winning number are extracted from the value of the winning request flag status, in the present embodiment, the main CPU 101 sets the value of the winning request flag status to the special prize number (“37””. ) To divide. As a result, the value of the quotient generated by the division process becomes the special prize winning number (one of 0 to 2 in decimal number), and the remaining value becomes the small winning combination winning number (one of 0 to 36 in decimal number). Become.

Next, the main CPU 101 determines whether or not the small winning combination has been won based on the extracted small winning combination winning number (S322). In this process, if the small winning combination winning number is any of 1 to 36, the main CPU 101 determines that the small winning combination has won, and if the small winning combination winning number is 0, the main CPU 101 determines that the small winning combination has won. It is determined that the small role did not win.

In S322, when the main CPU 101 determines that the small winning combination has not been won (when the determination in S322 is NO), the main CPU 101 performs the process of S331 described later. On the other hand, in S322, when the main CPU 101 determines that the small winning combination has won (when the determination in S322 is YES), the main CPU 101 sets the small winning combination winning number as the initial value of the subtraction result (S323).

Next, the main CPU 101 sets the hit request flag table (see FIG. 100) (S324). Next, the main CPU 101 subtracts 1 from the subtraction result and updates the subtraction result (S325). Next, the main CPU 101 determines whether or not the subtraction result is less than "0" (S326).

In S326, when the main CPU 101 determines that the subtraction result is not less than "0" (when the determination in S326 is NO), the main CPU 101 performs the bit number calculation process (S327). In the bit number calculation process of S327, the number of blocks in the storage area of the hit request flag data corresponding to the small winning combination winning number specified in the hit request flag table is acquired.

In the present embodiment, the hit request flag storage area (internal winning combination storage area) is provided with blocks of hit request storage areas 0 to 7 and blocks of hit request storage areas 8 to 11. Therefore, the maximum value of the number of blocks in the storage area of the hit request flag data acquired by the bit number calculation process of S327 is “2”. For example, when the internal winning combination is "F_certain chili lip", as shown in the hit request flag table (see FIG. 100), the storage area 7 included in the blocks of the hit request storage areas 0 to 7 and the hit request Since the hit request flag data is defined in each of the storage areas 9 included in the blocks of the storage areas 8 to 11, the number of blocks in the storage area of the hit request flag data acquired in the bit number calculation process of S327 is "2". It becomes.

Next, the main CPU 101 performs a bit number calculation process (S328). In the bit number calculation process of S328, the number of bytes of the hit request flag data in the block unit specified in the hit request flag table (see FIG. 100) is calculated. For example, when the internal winning combination is "F_certain chili lip", 1 byte of hit request flag data is stored in both the storage area 7 and the storage area 9 as shown in the hit request flag table (see FIG. 100). Therefore, the number of bytes of the hit request flag data for each block acquired in the bit number calculation process of S328 is 1 byte. In the table shown in FIG. 100, the hit request flag data stored in the storage area 7 is described as "10000000B | 01000000B", but this is because the hit request flag data stored in the storage area 7 is described. It means that it is "10000000B" or ("|" is a symbol of the logical sum) "01000000B".

The above-mentioned processes of S325 to S328 are repeated as many times as the number of small winning combination winning numbers. For example, when the internal winning combination is "F_certain winning combination" (small winning combination number is "2"), the above-mentioned processing of S325 to S328 is repeated twice. When the processing of S325 to S328 is repeated a plurality of times, the number of blocks acquired in the bit number calculation processing of S327 and S328 and the number of bytes of the hit request flag data for each block are stored in another storage area. Will be done. Further, the number of blocks obtained by the above-mentioned processing of S325 to S328 and the number of bytes of the hit request flag data in the block unit are information (on-bit information) for designating the storage destination of the hit request flag data.

Here, returning to the processing of S326 again, when the main CPU 101 determines in S326 that the subtraction result is less than "0" (when the determination in S326 is YES), the main CPU 101 is in the hit request flag storage area ( The internal winning combination storage area) is set (S329). At this time, the main CPU 101 checks (updates) the hit request flag based on the number of blocks obtained by the above-mentioned processes of S325 to S328 and the number of bytes (on-bit information) of the hit request flag data for each block. Set only the storage area. Specifically, the address of the hit request flag storage area to be checked (updated) is stored in the DE register (see FIG. 99).

Next, the main CPU 101 performs a compressed data storage process (S330). In this process, the main CPU 101 mainly performs a process of transferring (expanding) the hit request flag data to a predetermined storage area in the hit request flag storage area to be checked (updated). The details of the compressed data storage process will be described later with reference to FIG. 101 described later.

After the processing of S330 or when the determination in S322 is NO, the main CPU 101 refers to the carry-over combination storage area (see FIG. 31) to determine whether or not there is a carry-over combination (S331). In S331, when the main CPU 101 determines that there is a carry-over combination (when the determination in S331 is YES), the main CPU 101 performs the process of S334 described later.

On the other hand, in S331, when the main CPU 101 determines that there is no carry-over combination (when the determination in S331 is NO), the main CPU 101 determines the bonus combination (BB1 or BB2) based on the special prize winning number extracted in the process of S321. ) Wins or not (S332).

In S332, when the main CPU 101 determines that the bonus combination has not been won (when the determination in S332 is NO), the main CPU 101 ends the symbol determination process and shifts the process to S206 in the main flow (see FIG. 82). Move.

On the other hand, in S332, when the main CPU 101 determines that the bonus combination has been won (when the determination in S332 is YES), the main CPU 101 stores the winning special prize winning number in the carry-over combination storage area (S333).

After the processing of S333 or when the determination in S331 is NO, the main CPU 101 sets the special prize winning number in the winning number storage area (not shown), sets the hit request flag data in the hit request flag storage area, and sets the RT state to RT5. Set to the state and clear (“0”) the number of RT games (the number of digestion games in the RT1 state) (S334). Then, after the processing of S334, the main CPU 101 ends the symbol setting processing and shifts the processing to S206 of the main flow (see FIG. 82).

In the present embodiment, the symbol setting process is performed as described above. The processing of S324 to S330 (compression / decompression processing of data related to winning) during the above-mentioned symbol setting processing is performed by sequentially executing each source code defined by the source program of FIG. 99 by the main CPU 101. .. Among them, the compressed data storage process of S330 is performed by the main CPU 101 executing the source code "CALLF SB_BTEP_00" in FIG. 99.

The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_BTEP_00" in FIG. 99 is executed, processing is performed at the address specified by "SB_BTEP_00". Jump and start the compressed data storage process. In the compressed data storage process of S330, as described above, the hit request flag data (compressed data) stored in the hit request flag table is expanded (copied) to the corresponding hit request flag storage area.

Further, the setting process of the address of the hit request flag storage area of S329 during the symbol setting process described above is performed by the main CPU 101 executing the source code "LDQ DE, .LOW. WWAVEBIT" in FIG. 99. That is, the processing of S329 during the symbol setting processing is performed by the "LDQ" instruction dedicated to the main CPU 101 that specifies the address using the Q register (extension register). In this case, the instruction code related to the address setting can be omitted on the source program of the symbol setting process, and the capacity of the source program of the symbol setting process (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the present embodiment, the data related to the winning is compressed / decompressed by the processing procedure described in S324 to S330 during the symbol setting process described above, and the command code dedicated to the main CPU 101 described above is used in the process. By using it, it is possible to improve the efficiency of the compression / decompression processing of the data related to the winning, and it is possible to effectively utilize the limited capacity of the main RAM 103.

[Compressed data storage process]
Next, with reference to FIG. 101, for example, the compressed data processing performed in S330 during the symbol determination processing (see FIG. 97) will be described. FIG. 101 is a flowchart showing the procedure of the compressed data storage process.

The compressed data storage process shown in FIG. 101 is executed not only in S330 during the symbol determination process (see FIG. 97) but also in S649 during the symbol code acquisition process (see FIG. 128 described later) described later. In the compressed data storage process executed in S330 during the symbol determination process (see FIG. 97), the flag data to be processed is the hit request flag data (flag data related to the winning combination), but the symbol code acquisition process described later In the compressed data storage process executed in S649 (see FIG. 128 described later), the flag data to be processed is the winning operation flag data (flag data related to the winning combination). Then, both processes are the same except that the types of flag data to be processed are different.

Therefore, in the flowchart of FIG. 101, the flag data to be processed is referred to as “process target flag data”, and the flag table to be processed is referred to as “process target flag table”. Further, in accordance with this description, also in the following description of the compressed data storage process, the hit request flag data or the winning operation flag data is referred to as "process target flag data", and the hit request flag table (see FIG. 100) or described later. The symbol-corresponding winning operation table (see, for example, FIG. 130A described later) is referred to as a “processing target flag table”.

First, the main CPU 101 sets the storage destination check bit (S341). In this process, the storage destination check bit is stored in a register other than the A register.

The storage destination check bit is 1-byte data for designating a block that is a storage destination (transfer destination) of the processing target flag data. In the present embodiment, the hit request flag storage area and the winning operation flag storage area are both composed of two blocks (blocks of storage areas 0 to 7 and blocks of storage areas 8 to 11). Then, for example, when the internal winning combination “F_certain chili lip” is determined, the hit request flag data is stored in each of the storage area 7 and the storage area 9 as shown in the hit request flag table of FIG. 100. (Because the number of blocks in the storage destination is "2"), in the process of S341, "00000011B" is set as the storage destination check bit. The bit 0 value (1/0) of this 1-byte data corresponds to the presence or absence of a storage destination in the block of the storage areas 0 to 7, and the bit 1 value (1/0) corresponds to the storage areas 8 to 11. Corresponds to the presence or absence of the storage destination in the block of.

Next, the main CPU 101 sets the value of the transfer counter in byte units to "8" (S342). In the present embodiment, since the number of bytes of each block is "8", "8" is set as the initial value of the transfer counter.

Next, the value of the transfer instruction bit is extracted from the storage destination check bit (S343). The transfer instruction bit corresponds to the data of bit 0 in the storage destination check bit, and in the processing of S343, the storage destination check bit stored in the 1-byte register is shifted to the right once (for 1 bit). As a result, the transfer instruction bit is extracted. Specifically, when the 1-byte register (register other than the A register) in which the storage destination check bit is stored is shifted to the right once, the data stored in bits 7 to 1 are changed to bits 6 to 0, respectively. As it moves, the data of bit 0 before the shift is output. Then, the data output by this shift process becomes the value of the transfer instruction bit.

Next, the main CPU 101 determines whether or not there is a transfer instruction based on the value of the extracted transfer instruction bit (S344). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is "1". For example, when "00000011B" is set as the storage destination check bit, transfer is performed in the first (corresponding to the first block of the storage area) and second (corresponding to the second block of the storage area) determination process of S344. Although it is determined that there is an instruction, in the determination process of S344 after the third time, it is determined that there is no transfer instruction.

In S344, when the main CPU 101 determines that there is no transfer instruction (when the determination in S344 is NO), the main CPU 101 performs the process of S354 described later.

On the other hand, in S344, when the main CPU 101 determines that there is a transfer instruction (when the determination in S344 is YES), the main CPU 101 acquires byte unit storage destination designation information from the processing target flag table (S345). In this process, the transfer destination is stored at the start address of the area in which the flag data of the process target combination (winning combination or winning combination) in the processing target flag table is stored as the byte unit storage destination specification information. Byte data is retrieved. For example, when the internal winning combination is "F_certain chili lip", it is stored at the start address of the area in which the flag data of "F_certain chili lip" is stored in the hit request flag table shown in FIG. 100. The 1-byte data "10000000B" that designates the area 7 as the transfer destination is acquired as the byte unit storage destination designation information.

Next, the main CPU 101 performs an update process (a process of adding 1 address) of the address referred to in the processing target flag table (S346). Further, in this process, the main CPU 101 sets as an initial address an address that specifies the head storage area of the block that is the storage (transfer) destination of the processing target flag data. For example, in the processing of the first block, the address of the storage area 0 is set as the initial address in the processing of S346, and in the processing of the second block, the address of the storage area 8 is set as the initial address in the processing of S346. ..

Next, the main CPU 101 extracts the value of the transfer instruction bit from the byte unit storage destination designation information (S347). The transfer instruction bit referred to here corresponds to bit 0 of the byte unit storage destination specification information, and in the processing of S347, the byte unit storage destination specification information stored in the 1-byte register is shifted to the right once. Extracts the value of the transfer instruction bit (outputs bit 0 data).

Next, the main CPU 101 determines whether or not there is a transfer instruction based on the value of the transfer instruction bit extracted in the process of S347 (S348). In this process, the main CPU 101 determines that there is a transfer instruction when the value of the extracted transfer instruction bit is “1”. For example, when "00000010B" is set as the byte unit storage destination designation information, the bit 1 data "1" is processed in S347 of the second time (the storage area 1 of the first block or the storage area 9 of the second block). Is output as the value of the transfer instruction bit, and it is determined that there is a transfer instruction. However, in the first and third to eighth processes of S347, it is determined that there is no transfer instruction.

In S348, when the main CPU 101 determines that there is no transfer instruction (when the determination in S348 is NO), the main CPU 101 performs the process of S351 described later.

On the other hand, in S348, when the main CPU 101 determines that there is a transfer instruction (when the determination in S348 is YES), the main CPU 101 is the processing target flag stored in the address in the currently set processing target flag table. The data (winning request flag data or winning operation flag data) is transferred (copied) to the designated storage area (S349).

For example, when the internal winning combination is "F_certain chili lip" and the current processing is performed on the storage area (storage area 0 to 7) of the first block, the byte unit storage destination specification information is ". Since it becomes "10000000B" (data that specifies the storage area 7 as the storage destination), it is determined that there is a transfer instruction in the eighth processing of S347, and in the subsequent processing of S349, the hit request flag data "10000000B" and "01000000B" are obtained. , "00100000B" and "00010000B" are transferred (copied) to the storage area 7 of the hit request flag storage area.

Next, the main CPU 101 performs an update process (a process of adding 1 address) of the address referred to in the processing target flag table (S350).

After the processing of S350 or when the determination in S348 is NO, the main CPU 101 performs an address update process (a process of adding 1 to the address) that specifies a storage area to be a storage destination of the processing target flag data (S351). Next, the main CPU 101 subtracts 1 from the value of the transfer counter (S352).

Next, the main CPU 101 determines whether or not the value of the transfer counter is "0" (S353). In S353, when the main CPU 101 determines that the value of the transfer counter is not "0" (when the determination in S353 is NO), the main CPU 101 returns the processing to the processing of S347 and repeats the processing after S347.

On the other hand, in S353, when the main CPU 101 determines that the value of the transfer counter is "0" (when the determination in S353 is YES), does the main CPU 101 have a transfer instruction target remaining in the current storage destination check bit? Whether or not it is determined (S354). In this process, the main CPU 101 determines whether or not a bit in which "1" is stored remains in the storage destination check bit at the time of the current process. Then, when the bit in which "1" is stored remains in the storage destination check bit, that is, when the block to be processed exists, the main CPU 101 gives a transfer instruction to the current storage destination check bit. Determine that the target remains.

In S354, when the main CPU 101 determines that the transfer instruction target remains in the current storage destination check bit (when the determination in S354 is YES), the main CPU 101 returns the process to the process of S342, and the process after S342. repeat. On the other hand, in S354, when the main CPU 101 determines that the transfer instruction target does not remain in the current storage destination check bit (when the determination in S354 is NO), the main CPU 101 ends the compressed data storage process and performs the process. For example, it is transferred to S331 during the symbol determination process (see FIG. 97).

[Second interface board control process (non-standard)]
Next, the second interface board control process performed in S207 in the main flow (see FIG. 82) will be described with reference to FIG. 102. FIG. 102 is a flowchart showing the procedure of the second interface board control process. This process is performed in the non-standard work area (see FIG. 12C) in the main RAM 103. Further, the program used in the second interface board control process is stored in the non-standard area in the main ROM 102 (see FIG. 12B).

First, the main CPU 101 saves the address data of the stack area in the main RAM 103 set in the stack pointer (SP) (S361). Next, the main CPU 101 sets the address data of the non-standard stack area in the main RAM 103 in the stack pointer (SP) (S362).

Next, the main CPU 101 acquires navigation data (S363). Next, the main CPU 101 sets the navigation conversion table in the non-standard work area in the main RAM 103 (S364).

Next, the main CPU 101 refers to the navigation conversion table and acquires the push order number for the second interface (S365). Next, the main CPU 101 stores the acquired push order number for the second interface in the non-standard push order number storage area (not shown) provided in the non-standard work area (S366). Next, the main CPU 101 sets "0" to the value of the pressing position table selection counter provided in the non-standard work area (S367).

Next, the main CPU 101 determines whether or not the acquired navigation data is push-order navigation (navigation data for push-order small combination) (S368). In S368, when the main CPU 101 determines that the acquired navigation data is the push order navigation (when the determination in S368 is YES), the main CPU 101 performs the process of S372 described later.

On the other hand, in S368, when the main CPU 101 determines that the acquired navigation data is not the push-order navigation (when the determination in S368 is NO), the main CPU 101 determines that the acquired navigation data is the navigation data (10) for the BB1 stop operation. It is determined whether or not it is (S369).

In S369, when the main CPU 101 determines that the acquired navigation data is the navigation data for the BB1 stop operation (when the determination in S369 is YES), the main CPU 101 performs the process of S371 described later. On the other hand, in S369, when the main CPU 101 determines that the acquired navigation data is not the navigation data for the BB1 stop operation (when the determination in S369 is NO), the main CPU 101 sets the value of the pressing position table selection counter to "1". Is added (S370). In S370, the process of adding "1" to the value of the pressing position table selection counter is a process performed to acquire the pressing position of BB2 from the pressing position table (not shown).

After the processing of S370 or when the determination in S369 is YES, the main CPU 101 adds "1" to the value of the pressing position table selection counter (S371). In S371, the process of adding "1" to the value of the pressing position table selection counter is a process performed to acquire the pressing position of BB1 or BB2 from the pressing position table (not shown).

After the processing of S371 or when the determination in S368 is YES, the main CPU 101 selects the pressing position table (not shown) based on the value of the pressing position table selection counter (S372). Next, the main CPU 101 refers to the selected pressing position table and acquires pressing position data for three reels (left reel 3L, middle reel 3C, and right reel 3R) (S373). Next, the main CPU 101 stores the acquired pressing position data in the non-standard pressing position storage area (not shown) provided in the non-standard work area (S374). By the processing of S367 to S371, if the navigation data is the push order navigation, the value of the push position table selection counter becomes "0", and if the navigation data is the navigation data for the BB1 stop operation, the push position table selection counter The value is "1", and if the navigation data is the navigation data for the BB2 stop operation, the value of the pressing position table selection counter is "2". That is, the pressed position data is acquired based on the navigation data.

Next, the main CPU 101 performs the second interface board output process (S375). The details of the second interface board output process will be described later with reference to FIG. 103 described later.

Next, the main CPU 101 performs a reset process of all the registers (S376). Next, the main CPU 101 sets the address data of the stack area saved in S361 in the stack pointer (SP) (S377). Then, after the processing of S377, the main CPU 101 ends the second interface board control processing, and shifts the processing to S208 of the main flow (see FIG. 82).

[Second interface board output processing]
Next, the second interface board output process performed in S375 during the second interface board control process (see FIG. 102) will be described with reference to FIG. 103. FIG. 103 is a flowchart showing the procedure of the second interface board output processing. The second interface board output process is performed in the non-standard work area of the main RAM 103.

First, the main CPU 101 determines whether or not the transmission operation is performed via the second interface serial line (second serial communication circuit 115: SCU2) (S381). When the main CPU 101 determines in S381 that the transmission operation is being performed via the serial line for the second interface (when the determination in S381 is YES), the main CPU 101 ends the second interface board output process. The process is transferred to S376 of the second interface board control process (see FIG. 102).

On the other hand, in S381, when the main CPU 101 determines that the transmission operation is not performed via the serial line for the second interface (when the determination in S381 is NO), the main CPU 101 is provided in the non-standard work area. The loop counter value is set to "3" (the number of reels), and the serial communication sum value is set to the initial value "1" (S382). Next, the main CPU 101 transmits transmission start data via the second interface serial line (second serial communication circuit 115: SCU2) (S383).

Next, the main CPU 101 refers to the non-standard pressing position storage area of the predetermined reel (rotary reel), and acquires the pressing position data of the predetermined reel (S384). Next, the main CPU 101 updates the reference non-standard pressing position storage area to that of the next target reel (rotary reel) (S385).

Next, the main CPU 101 acquires pulse number data corresponding to the pressing position data (symbol position) based on the pulse conversion data (not shown) and the acquired pressing position data (S386). The details of the correspondence between the pressing position data (symbol position) and the pulse number data will be omitted, but for example, the acquired pressing position data (symbol position) is "3" (symbol "white 7" in the left reel 3L). ), "38" is acquired as the pulse number data, and when the pressing position data (symbol position) is "10" (symbol "replay" in the left reel 3L), "38" is acquired as the pulse number data. 155 ”is acquired. Further, for example, when the acquired pressing position data (symbol position) is "12" (symbol "blue 7" in the left reel 3L), "189" is acquired as the pulse number data, and the pressing position data (symbol) is acquired. When the position) is "15" (the symbol "replay" in the left reel 3L), "239" is acquired as the pulse number data.

Next, the main CPU 101 transmits the acquired pulse number data via the second interface serial line (second serial communication circuit 115: SCU2) (S387). Next, the main CPU 101 adds the pulse number data to the serial communication sum value (S388). Next, the main CPU 101 subtracts 1 from the value of the loop counter (S389).

Next, the main CPU 101 determines whether or not the value of the loop counter is "0" (S390). In S390, when the main CPU 101 determines that the value of the loop counter is not "0" (when the determination in S390 is NO), the main CPU 101 changes the target reel to the next reel and returns the process to S384. The processing after S384 is repeated.

On the other hand, in S390, when the main CPU 101 determines that the value of the loop counter is "0" (when the determination in S390 is YES), the main CPU 101 sets the serial communication sum value to the serial line for the second interface (the first). 2 Serial communication circuit 115: SCU2) for transmission (S391). Then, after the processing of S391, the main CPU 101 ends the second interface board output processing, and shifts the processing to S376 of the second interface board control processing (see FIG. 102).

[Control processing by state]
Next, with reference to FIG. 104, the state-specific control processing performed in S208 in the main flow (see FIG. 82) will be described. FIG. 104 is a flowchart showing the procedure of the state-specific control process.

First, the main CPU 101 performs a sub-flag conversion process (S401). In this process, the main CPU 101 performs a process of converting the internal winning combination into sub-flags (see FIGS. 36 and 37). The details of the sub-flag conversion process will be described later with reference to FIG. 105 described later.

Next, the main CPU 101 performs a navigation set process (S402). In this process, the main CPU 101 acquires navigation data based on the RT state, the game state, and the small winning combination winning number. The details of the navigation set processing will be described later with reference to FIG. 108 described later.

Next, the main CPU 101 determines whether or not the current RT state is the RT4 state (S403). In S403, when the main CPU 101 determines that the current RT state is not the RT4 state (when the determination in S403 is NO), the main CPU 101 performs the process of S406 described later.

On the other hand, in S403, when the main CPU 101 determines that the current RT state is the RT4 state (when the determination in S403 is YES), the main CPU 101 performs a flag conversion process (S404). In this process, the main CPU 101 performs a flag conversion lottery process (compression process of sub-flag data) for converting the sub-flag into the sub-flag EX (see FIG. 36). By this flag conversion process, 19 types (including loss) of sub-flags are converted (compressed) into 9 types (including loss) of sub-flag EX. The details of the flag conversion process will be described later with reference to FIG. 111 described later.

Next, the main CPU 101 performs a sub-flag compression process (S405). In this process, the main CPU 101 converts the sub-flag EX into the sub-flag D (see FIG. 36), and further compresses the sub-flag data. By this sub-flag compression process, 9 types (including loss) of sub-flag EX are converted (compressed) into 7 types (including loss) of sub-flag D.

After the processing of S405 or when the determination in S403 is NO, the main CPU 101 determines whether or not the current gaming state is the normal gaming state (S406).

In S406, when the main CPU 101 determines that the current gaming state is the normal gaming state (when the determination in S406 is YES), the main CPU 101 performs the normal middle start process (S407). The details of the normal start processing will be described later with reference to FIG. 112 described later. Then, after the processing of S407, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

On the other hand, in S406, when the main CPU 101 determines that the current gaming state is not the normal gaming state (when the determination in S406 is NO), the main CPU 101 determines whether or not the current gaming state is CZ (when the current gaming state is determined to be NO). S408).

In S408, when the main CPU 101 determines that the current gaming state is CZ (when the determination in S408 is YES), the main CPU 101 performs the CZ middle start process (S409). The details of the CZ middle start processing will be described later with reference to FIG. 113 described later. Then, after the processing of S409, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

On the other hand, in S408, when the main CPU 101 determines that the current gaming state is not CZ (when the determination in S408 is NO), the main CPU 101 determines whether or not the current gaming state is normal ART (S410). ).

In S410, when the main CPU 101 determines that the current gaming state is the normal ART (when the determination in S410 is YES), the main CPU 101 performs the normal start processing during the ART (S411). The details of the normal start processing during ART will be described later with reference to FIG. 117 described later. Then, after the processing of S411, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

On the other hand, in S410, when the main CPU 101 determines that the current gaming state is not normal ART (when the determination in S410 is NO), the main CPU 101 determines whether or not the current gaming state is CT (S412). ).

In S412, when the main CPU 101 determines that the current gaming state is CT (when the determination in S412 is YES), the main CPU 101 performs a process at the start during CT (S413). The details of the processing at the start during CT will be described later with reference to FIG. 118 described later. Then, after the processing of S413, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

On the other hand, in S412, when the main CPU 101 determines that the current gaming state is not CT (when the determination in S412 is NO), the main CPU 101 determines whether or not the current gaming state is a bonus state (S414). ).

In S414, when the main CPU 101 determines that the current gaming state is the bonus state (when the determination in S414 is YES), the main CPU 101 performs the process at the start during BB (S415). The details of the BB start processing will be described later with reference to FIG. 125 described later. Then, after the processing of S415, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

On the other hand, in S414, when the main CPU 101 determines that the current gaming state is not the bonus state (when the determination in S414 is NO), the main CPU 101 performs other processing (S416). In this process, the main CPU 101 performs a process according to a game state other than the game state targeted by the various determination processes. For example, when the current gaming state is the ART preparation state, processing corresponding to the ART preparation state is performed. Then, after the processing of S416, the main CPU 101 ends the state-specific control processing, and shifts the processing to S209 of the main flow (see FIG. 82).

[Sub-flag conversion process]
Next, the sub-flag conversion process performed in S401 during the state-specific control process (see FIG. 104) will be described with reference to FIGS. 105 to 107. FIG. 105 is a flowchart showing the procedure of the sub-flag change processing. Further, FIG. 106 is a diagram showing an example of a source program for executing the sub-flag change process, and FIG. 107 is a diagram of a sub-flag conversion table (conversion table) actually referred to on the source program of the sub-flag conversion process. It is a figure which shows an example of the structure.

First, the main CPU 101 acquires a small winning combination winning number (0 to 36) (S421). Next, the main CPU 101 determines whether or not the bonus operation is currently in progress (S422).

In S422, when the main CPU 101 determines that the bonus is currently in operation (when the determination in S422 is YES), the main CPU 101 converts the small winning combination winning number into a sub-flag in which the bonus is operating and saves it (S423). .. The process of converting the small winning combination winning number into the sub-flag during the bonus operation is performed by the main CPU 101 executing the source code "SUB (subtraction instruction) cNHT_RBST-c7HT1_FLA" in FIG. 106. Then, in the present embodiment, by executing this "SUB" instruction, the small winning combination winning number is uniformly converted into the sub-flag "cactus (14)". Then, after the processing of S423, the main CPU 101 ends the sub-flag conversion processing, and shifts the processing to S402 of the state-based control processing (see FIG. 104).

On the other hand, in S422, when it is determined that the main CPU 101 is not currently operating the bonus (when the determination in S422 is NO), the main CPU 101 sets the sub-flag conversion table shown in FIG. 107 (S424). In this process, the initial value of the sub-flag to be determined is set to "loss (00)", and the sub-flag "loss (00)" is set as the initial address of the block in the sub-flag conversion table shown in FIG. Set the address ("dSBCBVTB + 1") in which is stored.

Next, in the main CPU 101, whether the data of the small winning combination winning number defined in the block in the sub-flag conversion table currently being referred to is the data corresponding to the small winning combination winning number acquired in the current game. Whether or not it is determined (S425).

In S425, the main CPU 101 determines that the data of the small winning combination winning number defined in the block in the sub-flag conversion table to be referred to is not the data corresponding to the small winning combination winning number acquired in the current game. At this time (when the determination in S425 is NO), the main CPU 101 updates the block in the sub-flag conversion table to be referred to to the block at the next address (S426). Next, the main CPU 101 adds "1" to the value of the sub flag (S427). Then, after the processing of S427, the main CPU 101 returns the processing to the processing of S425, and repeats the processing after S425.

On the other hand, in S425, the data of the small winning combination winning number defined in the block in the sub-flag conversion table referred to by the main CPU 101 is the data corresponding to the small winning combination winning number acquired in the current game. When it is determined (when the determination in S425 is YES), the main CPU 101 refers to the sub-flag conversion table shown in FIG. 107 and refers to the sub-flag conversion control data associated with the small winning combination winning number (of the address of the small winning combination winning number). The 1-byte data stored at the next address) is acquired, and the sub-flag conversion control data is stored in the sub-flag conversion control data storage area (not shown) provided in the main RAM 103 (S428). In this process, for example, when the small winning combination winning number acquired in the current game is "03" (internal winning combination "F_3 consecutive chili lip"), the sub-flag conversion table is referred to in FIG. 107 to convert the sub-flag. The control data "00000011B" is acquired. Then, after the processing of S428, the main CPU 101 ends the sub-flag conversion processing, and shifts the processing to S402 of the state-based control processing (see FIG. 104).

In the present embodiment, the sub-flag conversion process is performed as described above. The above-mentioned sub-flag conversion process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 106. Further, in the sub-flag conversion table shown in FIG. 107, which is actually referred to on the source program of the sub-flag conversion process, the sub-flag conversion control data (control status) is associated with each sub-flag. At this time, the same sub-flag conversion control data (control status) is associated with the same type of sub-flag.

For example, the sub-flag conversion control data (control status) "00000011B" is commonly assigned to the sub-flags "triple chili lip A" and "triple chili lip B". Further, for example, the sub-flag conversion control data (control status) "00000001B" is commonly assigned to the sub-flags "reach-eye lip 1" to "reach-eye lip 4". Then, in the flag conversion lottery process when converting the above-mentioned internal winning combination (sub-flag) to the sub-flag EX, the lottery is performed based on the sub-flag conversion control data (control status) stored in the sub-flag conversion control data storage area. ..

By providing common sub-flag conversion control data for the same type of internal winning combination (sub-flag) in the sub-flag conversion table for converting the flag managed on the main side (internal winning combination) to a flag manageable on the sub side. The versatility of the conversion table is increased, and changes in the conversion program due to a model change can be handled with minor changes, so that an increase in development cost can be suppressed.

[Naviset processing]
Next, with reference to FIGS. 108 to 110, the navigation set process performed in S402 during the state-based control process (see FIG. 104) will be described. FIG. 108 is a flowchart showing the procedure of the navigation set process. Further, FIG. 109 is a diagram showing an example of a source program for executing the processes of S434 to S436 described later during the navigation set processing, and FIG. 110 is a diagram actually referred to on the source program of the navigation set processing. It is a figure which shows an example of the structure of the navigation data table.

First, the main CPU 101 determines whether or not the navigation set flag is set in the sub-flag conversion control data storage area (not shown) (S431). Specifically, the main CPU 101 refers to the sub-flag conversion control data storage area, and the set sub-flag conversion control data is data corresponding to the small winning combination winning numbers (10 to 23) that generate push order navigation. Determine if it is. In S431, when the main CPU 101 determines that the navigation set flag is not set in the sub-flag conversion control data storage area (when the determination in S431 is NO), the main CPU 101 ends the navigation set processing and performs the processing according to the state. The control process (see FIG. 104) is transferred to S403.

On the other hand, in S431, when the main CPU 101 determines that the navigation set flag is set in the sub-flag conversion control data storage area (when the determination in S431 is YES), the RT state of the main CPU 101 is RT0 or RT1. Whether or not it is determined (S432). In S432, when the main CPU 101 determines that the RT state is not the RT0 or RT1 state (when the determination in S432 is NO), the main CPU 101 ends the navigation set process and controls the process according to the state (see FIG. 104). Move to S403.

On the other hand, in S432, when the main CPU 101 determines that the RT state is the RT0 or RT1 state (when the determination in S432 is YES), the main CPU 101 determines whether or not the gaming state is the general gaming state (when the RT state is determined to be YES). S433). In S433, when the main CPU 101 determines that the gaming state is the general gaming state (when the determination in S433 is YES), the main CPU 101 ends the navigation set process and controls the process according to the state (see FIG. 104). Move to S403.

On the other hand, in S433, when the main CPU 101 determines that the gaming state is not the general gaming state (when the determination in S433 is NO), the main CPU 101 acquires the small winning combination winning number (S434). Next, the main CPU 101 refers to the navigation data table shown in FIG. 110 and acquires navigation data (any of 1 to 9) based on the small winning combination winning number (S435).

Next, the main CPU 101 stores the acquired navigation data (information regarding the stop operation of the variable display of the plurality of display columns) in the navigation data storage area (stop operation instruction information storage area) (S436) in the main RAM 103. Then, after the processing of S436, the main CPU 101 ends the navigation set processing, and shifts the processing to S403 of the state-based control processing (see FIG. 104).

In this embodiment, the navigation set process is performed as described above. The processing of S434 to S436 during the navigation set processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 109. In this series of processing, as shown in FIG. 109, an "LDQ" instruction dedicated to the main CPU 101 that specifies an address using a Q register (extension register) is used on the source program.

For example, when the source code "LDQ A, (k)" is executed on the source program, the stored data in the Q register (upper address value) and the 1-byte integer k (direct value: lower address value). The contents (stored data) of the memory at the address specified in and are loaded into the A register. Therefore, for example, when the source code "LDQ A, (wHITFRT)" in FIG. 109 is executed, the stored data of the Q register and the contents of the memory of the address specified by the integer value "wHITFRT" are stored in the A register. Loaded into.

Further, for example, when the source code "LDQ (k), A" is executed on the source program, the stored data of the A register is the stored data of the Q register (upper address value) and the 1-byte integer k. It is loaded into the memory of the address specified by (direct value: lower address value). Therefore, for example, by executing the source code "LDQ (wNAVIPTN), A" in FIG. 109, the data (navigation data) stored in the A register becomes 1 byte with the stored data (upper address value) in the Q register. It is stored in the navigation data storage area of the address specified by the integer value "wNAVIPTN" (lower address value) of.

As described above, in the present embodiment, the main CPU 101 dedicated instruction code using the Q register (extension register) is used in the navigation set processing, and the main ROM 102, the main RAM 103, and the memory map I / O are accessed by direct values. can do. In this case, the instruction related to the address setting can be omitted on the source program of the navigation set processing, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Flag conversion process]
Next, with reference to FIG. 111, the flag conversion process performed in S404 during the state-based control process (see FIG. 104) will be described. Note that FIG. 111 is a flowchart showing the procedure of the flag conversion process.

First, the main CPU 101 determines whether or not it is the start of CT (S441).

When the main CPU 101 determines in S441 that it is not the start of CT (when the determination in S441 is NO), the main CPU 101 performs the process of S443 described later. On the other hand, in S441, when the main CPU 101 determines that it is the start of CT (when the determination in S441 is YES), the main CPU 101 determines the table number of the flag conversion lottery table used for the flag conversion lottery during CT by lottery. And set (S442).

After the processing of S442 or when the determination in S441 is NO, the main CPU 101 sets the flag conversion lottery table according to the current state (S443). For example, if the current state is the RT4 state during non-ART, the non-ART flag conversion lottery table (see FIG. 62) is set, and if the current state is the RT4 state during normal ART, The flag conversion lottery table during ART (see FIGS. 47A and 47B) is set, and when the current state is the RT4 state during CT, the flag conversion lottery table during CT (see FIG. 54) is set.

Next, the main CPU 101 refers to the set flag conversion lottery table, and performs the flag conversion lottery process based on the internal winning combination (S444). In fact, in this process, the main CPU 101 performs a flag conversion lottery process using the sub-flag conversion control data acquired from the sub-flag conversion control table shown in FIG. 107 based on the sub-flag corresponding to the internal winning combination.

Next, the main CPU 101 determines whether or not the flag conversion lottery of S444 has been won (S445).

In S445, when the main CPU 101 determines that the flag conversion lottery has been won (when the determination in S445 is YES), the main CPU 101 performs the sub-flag conversion process (S446). In this process, for example, when the internal winning combination is "F_1 certain chili lip", that is, when the sub flag is "triple chili lip B (03)", when the flag conversion lottery process is won, the sub flag conversion process of S446 is performed. , The sub-flag "triple chili lip B (03)" is converted to the sub-flag EX "fixed combination (06)" or the sub-flag EX "triple chili lip (07)" (see FIG. 36).

After the process of S446, the main CPU 101 determines whether or not the current gaming state is the non-ART state (S447). In S447, when the main CPU 101 determines that the current gaming state is not the non-ART state (when the determination in S447 is NO), the main CPU 101 ends the flag conversion process and controls the process according to the state (see FIG. 104). ) S405.

On the other hand, in S447, when the main CPU 101 determines that the current gaming state is the non-ART state (when the determination in S447 is YES), the main CPU 101 adds "1" to the number of ART sets (S448). Next, the main CPU 101 sets the ART preparation state in the game state of the next game (S449). Then, after the processing of S449, the main CPU 101 ends the flag conversion processing, and shifts the processing to S405 of the state-based control processing (see FIG. 104).

Here, returning to the process of S445 again, when the main CPU 101 determines in S445 that the flag conversion lottery has not been won (when the determination in S445 is NO), the main CPU 101 performs the sub-flag maintenance process (S450). .. In this process, for example, when the internal winning combination is "F_1 certain chili lip", that is, when the sub flag is "triple chili lip B (03)", and the flag conversion lottery is not winning, the sub flag of S450 is maintained. By the processing, the sub-flag "triple chili lip B (03)" is converted (maintained) into the sub-flag EX "replay (01)". Then, after the processing of S450, the main CPU 101 ends the flag conversion processing, and shifts the processing to S405 of the state-based control processing (see FIG. 104).

[Normal start processing]
Next, with reference to FIG. 112, the normal middle start process performed in S407 during the state-based control process (see FIG. 104) will be described. Note that FIG. 112 is a flowchart showing the procedure of the normal start processing.

First, the main CPU 101 refers to the CZ lottery table (see FIG. 41A), and performs the CZ lottery process based on the current CZ lottery state and the internal winning combination (sub flag) (S461). Next, the main CPU 101 determines whether or not the CZ lottery of S461 has been won (S462).

In S462, when the main CPU 101 determines that the CZ lottery has not been won (when the determination in S462 is NO), the main CPU 101 performs the process of S465 described later.

On the other hand, in S462, when the main CPU 101 determines that the CZ lottery has been won (when the determination in S462 is YES), the main CPU 101 sets the winning type CZ in the game state of the next game (S463). Next, the main CPU 101 sets the number of CZ games of the winning type in the CZ game number counter (S464). The CZ game number counter is a counter that counts the duration of CZ, and is provided in the main RAM 103. In the process of S464, for example, when CZ1 wins, the first predetermined number of games (for example, "12") is set in the CZ game number counter (first half), and CZ2 wins. Is set to a second predetermined number of games (for example, "15") in the CZ game number counter (first half), and when CZ3 wins, a fourth predetermined number of games is set in the CZ game number counter. (For example, "17") is set.

After the processing of S464 or when the determination in S462 is NO, the main CPU 101 usually refers to the medium-high probability lottery table (see FIG. 40A), and performs the transition lottery of the lottery state of CZ based on the internal winning combination (sub-flag) (S465). ). Next, the main CPU 101 updates the lottery state of CZ based on the result of the transition lottery (S466). Then, after the processing of S466, the main CPU 101 ends the normal middle start processing and also ends the state-specific control processing (see FIG. 104).

[Processing at start during CZ]
Next, with reference to FIG. 113, the CZ middle start process performed in S409 during the state-specific control process (see FIG. 104) will be described. Note that FIG. 113 is a flowchart showing the procedure of the CZ middle start processing.

First, the main CPU 101 determines whether or not the current gaming state is CZ1 (S471).

In S471, when the main CPU 101 determines that the current gaming state is CZ1 (when the determination in S471 is YES), the main CPU 101 performs CZ1 (CZ2) intermediate processing (S472). The details of the processing during CZ1 (CZ2) will be described later with reference to FIGS. 114 and 115 described later. Then, after the processing of S472, the main CPU 101 ends the processing at the start during CZ, and also ends the state-specific control processing (see FIG. 104).

On the other hand, in S471, when the main CPU 101 determines that the current gaming state is not CZ1 (when the determination in S471 is NO), the main CPU 101 determines whether or not the current gaming state is CZ2 (S473). ..

In S473, when the main CPU 101 determines that the current gaming state is CZ2 (when the determination in S473 is YES), the main CPU 101 performs CZ1 (CZ2) intermediate processing (S474). Details of the processing during CZ1 (CZ2) will be described later with reference to FIGS. 114 and 115 described later. Then, after the processing of S474, the main CPU 101 ends the processing at the start during CZ, and also ends the state-specific control processing (see FIG. 104). In the present embodiment, the CZ1 intermediate processing and the CZ2 intermediate processing differ only in the rank (mode or point) indicating the degree of expectation of winning the ART lottery, and the basic processing contents are the same. Therefore, in the present embodiment, the CZ1 intermediate process and the CZ2 intermediate process will be described as one process as the CZ1 (CZ2) intermediate process.

On the other hand, in S473, when the main CPU 101 determines that the current gaming state is not CZ2 (when the determination in S473 is NO), the main CPU 101 performs CZ3 intermediate processing (S475). The details of the processing during CZ3 will be described later with reference to FIG. 116 described later. Then, after the processing of S475, the main CPU 101 ends the processing at the start during CZ, and also ends the state-specific control processing (see FIG. 104).

[Processing during CZ1 (CZ2)]
Next, with reference to FIGS. 114 and 115, the CZ1 (CZ2) intermediate process performed in S472 or S474 during the CZ intermediate start process (see FIG. 113) will be described. It should be noted that FIGS. 114 and 115 are flowcharts showing the procedure of processing during CZ1 (CZ2).

First, the main CPU 101 determines whether or not the current game is a game in the first half of CZ1 (or CZ2) (S481). In S481, when the main CPU 101 determines that the current game is not the game of the first half of CZ1 (or CZ2) (when the determination in S481 is NO), the main CPU 101 performs the process of S490 described later.

On the other hand, in S481, when the main CPU 101 determines that the current game is the game of the first half of CZ1 (when the determination in S481 is YES), the main CPU 101 refers to the mode-up lottery table during CZ1 (see FIG. 42). Then, the mode-up lottery process is performed based on the internal winning combination (sub flag) (S482). Further, in S481, when the main CPU 101 determines that the current game is a game in the first half of CZ2 (when the determination in S481 is YES), the main CPU 101 refers to the CZ2 middle point lottery table (see FIG. 43). , A point-up lottery is performed based on the internal winning combination (sub flag) (S482).

Next, the main CPU 101 updates the rank (mode or point) based on the lottery result of S482 (S483). Next, the main CPU 101 determines whether or not the freeze is won in the lottery of S482 (S484).

In S484, when the main CPU 101 determines that the freeze has been won (when the determination in S484 is YES), the main CPU 101 performs a freeze process for temporarily stopping the progress of the game, and the number of ART sets and the number of CT sets. Add "1" to (S485). Further, in this process, the main CPU 101 determines and sets the ART level with reference to the ART level determination table (see FIG. 48A). When a freeze occurs, "ART level 2" is determined as the ART level.

Next, the main CPU 101 sets the ART preparation state in the game state of the next game (S486). Then, after the processing of S486, the main CPU 101 ends the processing during CZ1 (CZ2), and also ends the processing at the start during CZ (see FIG. 113).

Here, returning to the processing of S484 again, when it is determined in S484 that the main CPU 101 has not won the freeze (when the determination in S484 is NO), the main CPU 101 is the value of the CZ game number counter (first half). Is subtracted by 1 (S487). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (first half) is "0" (S488).

In S488, when the main CPU 101 determines that the value of the CZ game number counter (first half) is not "0" (when the determination in S488 is NO), the main CPU 101 ends the processing during CZ1 (CZ2), and at the same time, The CZ middle start process (see FIG. 113) also ends.

On the other hand, in S488, when the main CPU 101 determines that the value of the CZ game number counter (first half) is "0" (when the determination in S488 is YES), the main CPU 101 sets the CZ1 or the game state of the next game. The latter half of CZ2 is set (S489). Then, after the processing of S489, the main CPU 101 ends the processing during CZ1 (CZ2), and also ends the processing at the start during CZ (see FIG. 113).

Here, returning to the process of S481 again, when the determination in S481 is NO, the main CPU 101 determines whether or not the current game is the first game in the latter half of CZ1 or CZ2 (S490). In S490, when the main CPU 101 determines that the current game is not the first game in the latter half of CZ1 or CZ2 (when the determination in S490 is NO), the main CPU 101 performs the process of S495 described later.

On the other hand, in S490, when the main CPU 101 determines that the current game is the first game in the latter half of CZ1 or CZ2 (when the determination in S490 is YES), the main CPU 101 uses the ART lottery table in CZ (FIGS. 44A and 44A and). (Refer to 44B), the ART lottery process is performed based on the rank (mode or point) of the first half (S491).

Next, the main CPU 101 determines whether or not the ART lottery has been won (S492). In S492, when the main CPU 101 determines that the ART lottery has not been won (when the determination in S492 is NO), the main CPU 101 performs the process of S494 described later.

On the other hand, in S492, when the main CPU 101 determines that the ART lottery has been won (when the determination in S492 is YES), the main CPU 101 adds "1" to the number of ART sets and sets the ART level determination table (see FIG. 48A). ), The ART level lottery is performed, and the lottery result is set (S493).

After the processing of S493 or when the determination in S492 is NO, the main CPU 101 sets a predetermined value in the CZ game number counter (second half) (S494). In the processing of S494, for example, when the ART lottery is won, "4" is set in the CZ game number counter (second half), and when the ART lottery is not won, the number of CZ games is set. "3" is set in the counter (second half).

After the processing of S494 or when the determination in S490 is NO, the main CPU 101 refers to the ART lottery table in CZ (see FIG. 44C) and performs the ART lottery processing based on the internal winning combination (sub flag) (S495).

Next, the main CPU 101 determines whether or not the ART lottery has been won (S496). In S496, when the main CPU 101 determines that the ART lottery has not been won (when the determination in S496 is NO), the main CPU 101 performs the process of S498 described later.

On the other hand, in S496, when the main CPU 101 determines that the ART lottery has been won (when the determination in S496 is YES), the main CPU 101 adds "1" to the number of ART sets and sets the ART level determination table (see FIG. 48A). ), The ART level lottery is performed, and the lottery result is set (S497).

After the processing of S497 or when the determination in S496 is NO, the main CPU 101 subtracts 1 from the value of the CZ game number counter (second half) (S498). Next, the main CPU 101 determines whether or not the value of the CZ game number counter (second half) is "0" (S499).

In S499, when the main CPU 101 determines that the value of the CZ game number counter (second half) is not "0" (when the determination in S499 is NO), the main CPU 101 ends the processing during CZ1 (CZ2), and at the same time, The CZ middle start process (see FIG. 113) also ends.

On the other hand, in S499, when the main CPU 101 determines that the value of the CZ game number counter (second half) is "0" (when the determination in S499 is YES), the main CPU 101 has an ART set number of "1" or more. It is determined whether or not it is (S500).

In S500, when the main CPU 101 determines that the number of ART sets is "1" or more (when the determination in S500 is YES), the main CPU 101 sets the ART preparation state in the game state of the next game (S501). Then, after the processing of S501, the main CPU 101 ends the processing during CZ1 (CZ2), and also ends the processing at the start during CZ (see FIG. 113).

On the other hand, in S500, when the main CPU 101 determines that the number of ART sets is not "1" or more (when the determination in S500 is NO), the main CPU 101 sets the game state of the next game to the state at the time of CZ failure (when the CZ failure state is set). S502). Then, after the processing of S502, the main CPU 101 ends the processing during CZ1 (CZ2), and also ends the processing at the start during CZ (see FIG. 113).

[Processing during CZ3]
Next, with reference to FIG. 116, the CZ3 intermediate processing performed in S475 during the CZ intermediate start processing (see FIG. 113) will be described. Note that FIG. 116 is a flowchart showing the procedure of processing during CZ3.

First, the main CPU 101 refers to the ART lottery table in CZ (see FIG. 45), and performs the ART lottery process based on the internal winning combination (sub flag) (S511).

Next, the main CPU 101 determines whether or not the ART lottery has been won (S512). In S512, when the main CPU 101 determines that the ART lottery has not been won (when the determination in S512 is NO), the main CPU 101 performs the process of S518 described later.

On the other hand, in S512, when the main CPU 101 determines that the ART lottery has been won (when the determination in S512 is YES), the main CPU 101 adds "1" to the number of ART sets and adds "1" to the number of CT sets. Add (S513). Next, the main CPU 101 determines whether or not the freeze has been won in the ART lottery of S512 (S514).

In S514, when the main CPU 101 determines that the freeze has not been won (when the determination in S514 is NO), the main CPU 101 performs the process of S516 described later. On the other hand, in S514, when the main CPU 101 determines that the freeze has been won (when the determination in S514 is YES), the main CPU 101 performs a freeze process for temporarily stopping the progress of the game (S515).

After the processing of S515 or when the determination in S514 is NO, the main CPU 101 performs an ART level lottery process with reference to the ART level determination table (see FIG. 48A), and sets the lottery result (ART level) (S516). .. Next, the main CPU 101 sets the ART preparation state in the game state of the next game (S517). Then, after the processing of S517, the main CPU 101 ends the processing during CZ3 and also ends the processing at the start during CZ (see FIG. 113).

Here, returning to the process of S512 again, when the determination in S512 is NO, the main CPU 101 subtracts 1 from the value of the CZ game number counter (S518). Next, the main CPU 101 determines whether or not the value of the CZ game number counter is "0" (S519).

In S519, when the main CPU 101 determines that the value of the CZ game number counter is not "0" (when the determination in S519 is NO), the main CPU 101 ends the CZ3 middle processing and the CZ middle start processing (FIG. 113) also ends.

On the other hand, in S519, when the main CPU 101 determines that the value of the CZ game number counter is "0" (when the determination in S519 is YES), the main CPU 101 adds "1" to the number of ART sets and ARTs. An ART level lottery is performed with reference to the level determination table (see FIG. 48A), and the lottery result is set (S520). Next, the main CPU 101 sets the ART preparation state in the game state of the next game (S521). Then, after the processing of S521, the main CPU 101 ends the processing during CZ3 and also ends the processing at the start during CZ (see FIG. 113).

[Processing at start during normal ART]
Next, with reference to FIG. 117, the process at the start of normal ART performed in S411 during the state-specific control process (see FIG. 104) will be described. Note that FIG. 117 is a flowchart showing the procedure of the normal start processing during ART.

First, the main CPU 101 adds "1" to the value of the ART continuous game number counter (S531). The ART continuation game number counter is a counter that normally counts the number of games (the number of digested games) that ART has continued. Further, in the present embodiment, in addition to the ART continuous game number counter, an ART end game number counter that counts the number of games that can be normally continued by ART is also provided. Then, in the pachislot 1 of the present embodiment, the value of the ART continuous game number counter is compared with the value of the ART end game number counter, and when the value of the ART continuous game number counter reaches the value of the ART end game number counter, ART The game state ends.

Next, the main CPU 101 refers to the CT lottery table during ART (see FIG. 50), and performs the CT lottery process based on the current CT lottery state and the internal winning combination (sub flag) (S532). Next, the main CPU 101 determines whether or not the CT lottery has been won (S533). In S533, when the main CPU 101 determines that the CT lottery has not been won (when the determination in S533 is NO), the main CPU 101 performs the process of S536 described later.

On the other hand, in S533, when the main CPU 101 determines that the CT lottery has been won (when the determination in S533 is YES), the main CPU 101 adds "1" to the number of CT sets and adds "1" to the value of the CT game number counter. 8 ”is set (S534). Next, the main CPU 101 sets the winning type of CT in the game state of the next game (S535).

After the processing of S535 or when the determination in S533 is NO, the main CPU 101 refers to the ART level determination table (see FIG. 48B), draws the ART level based on the value of the ART continuous game number counter, and sets the lottery result. (S536). Next, the main CPU 101 refers to the normal ART medium-high probability lottery table (see FIG. 49), draws the CT lottery state of the migration destination based on the current CT lottery state and the internal winning combination (sub flag), and the lottery result. Is set (S537).

Next, the main CPU 101 refers to the additional lottery table during normal ART (see FIG. 51), and performs an additional lottery process for the number of ART games based on the internal winning combination (sub flag) (S538). Next, the main CPU 101 determines whether or not the additional lottery has been won (S539).

In S539, when the main CPU 101 determines that the additional lottery has not been won (when the determination in S539 is NO), the main CPU 101 performs the process of S541 described later. On the other hand, in S539, when the main CPU 101 determines that the additional lottery has been won (when the determination in S539 is YES), the main CPU 101 adds the winning result to the ART end game number counter (S540).

After the processing of S540 or when the determination in S539 is NO, the main CPU 101 determines whether or not the value of the ART continuous game number counter has reached the value of the ART end game number counter (S541). In S541, when the main CPU 101 determines that the value of the ART continuation game number counter has not reached the value of the ART end game number counter (when the determination in S541 is NO), the main CPU 101 normally processes at the start during ART. Is terminated, and the state-specific control process (see FIG. 104) is also terminated.

On the other hand, in S541, when the main CPU 101 determines that the value of the ART continuous game number counter has reached the value of the ART end game number counter (when the determination in S541 is YES), the main CPU 101 sets the number of ART sets to 1. Subtract (S542). Next, the main CPU 101 sets the state at the end of ART (S543). Then, after the processing of S543, the main CPU 101 ends the normal start processing during ART, and also ends the state-specific control processing (see FIG. 104).

[Processing at start during CT]
Next, with reference to FIG. 118, the process at the start of CT performed in S413 during the state-specific control process (see FIG. 104) will be described. Note that FIG. 118 is a flowchart showing the procedure of the start processing during CT.

First, the main CPU 101 refers to the additional lottery table during CT (see FIG. 55), and performs an additional lottery for the number of ART games based on the internal winning combination (sub flag) (S551). Next, the main CPU 101 determines whether or not the additional lottery has been won (S552).

In S552, when the main CPU 101 determines that the additional lottery has not been won (when the determination in S552 is NO), the main CPU 101 performs the process of S556 described later. On the other hand, in S552, when the main CPU 101 determines that the additional lottery has been won (when the determination in S552 is YES), the main CPU 101 adds the winning result to the ART end game number counter (S553). As described above, in the pachislot machine 1 of the present embodiment, as the number of times the sub-flag "triple chili lip (triple chili lip A or triple chili lip B)" is applied during the same CT increases, one lottery per lottery. The amount of extra is increased.

After the processing of S553, the main CPU 101 determines whether or not the internal winning combination corresponds to the sub-flag EX "triple chili lip" (or "fixed combination"), that is, the internal winning combination "F_certain chili lip" or "F_1". It is determined whether or not the flag conversion lottery process of S444 in FIG. 111 has been won (S554).

In S554, when the main CPU 101 determines that the internal winning combination does not correspond to the sub-flag EX "triple chili lip" (when the determination in S554 is NO), the main CPU 101 ends the processing at the start during CT, and at the same time, The state-specific control process (see FIG. 104) also ends.

On the other hand, in S554, when the main CPU 101 determines that the internal winning combination corresponds to the sub-flag EX "triple chili lip" (when the determination in S554 is YES), the main CPU 101 sets the value of the CT game number counter. "1" is added (S555). Then, after the processing of S555, the main CPU 101 ends the processing at the start during CT, and also ends the state-specific control processing (see FIG. 104).

Here, returning to the processing of S552 again, when the determination in S552 is NO, the main CPU 101 performs the CT lottery processing during CT (S556). In this process, the main CPU 101 mainly performs an additional lottery for the number of CT sets. The details of the CT lottery process during CT will be described later with reference to FIG. 119 described later.

Next, the main CPU 101 subtracts 1 from the value of the CT game number counter (S557). Next, the main CPU 101 determines whether or not the value of the CT game number counter is "0" (S558).

In S558, when the main CPU 101 determines that the value of the CT game number counter is not "0" (when the determination in S558 is NO), the main CPU 101 ends the CT start processing and state-specific control processing (when the CT game number counter value is not "0"). (See FIG. 104) also ends. On the other hand, in S558, when the main CPU 101 determines that the value of the CT game number counter is "0" (when the determination in S558 is YES), the main CPU 101 determines whether the number of CT sets is "1" or more. (S559).

In S559, when the main CPU 101 determines that the number of CT sets is "1" or more (when the determination in S559 is YES), the main CPU 101 subtracts 1 from the number of CT sets (S560). Next, the main CPU 101 sets the value of the CT game number counter to "8" (S561). Then, after the processing of S561, the main CPU 101 ends the processing at the start during CT, and also ends the state-specific control processing (see FIG. 104).

On the other hand, in S559, when the main CPU 101 determines that the number of CT sets is not "1" or more (when the determination in S559 is NO), the main CPU 101 sets the normal ART in the gaming state of the next game (S562). Then, after the processing of S562, the main CPU 101 ends the processing at the start during CT, and also ends the state-specific control processing (see FIG. 104).

[CT lottery processing during CT]
Next, with reference to FIG. 119, the CT lottery process during CT performed in S556 during the start process during CT (see FIG. 118) will be described. Note that FIG. 119 is a flowchart showing the procedure of CT lottery processing during CT.

First, the main CPU 101 sets the CT lottery table during CT (S571). The CT lottery table during CT set here is the lottery table with the number of sets during CT described in FIG. 56 above, but the CT lottery table during CT actually set on the source program (set during CT). The configuration of the number-added lottery table) will be described later with reference to FIG. 122 described later.

Next, the main CPU 101 performs a table data acquisition process (S572). In this process, the main CPU 101 acquires the address of the lottery table referred to in the CT lottery process during CT. The details of the table data acquisition process will be described later with reference to FIG. 120 described later.

Next, the main CPU 101 performs a 1-byte lottery process (S573). In this process, the main CPU 101 performs an additional lottery of the CT set. The details of the 1-byte lottery process will be described later with reference to FIG. 123 described later.

Next, the main CPU 101 determines whether or not the 1-byte lottery process has been won (S574). In S574, when the main CPU 101 determines that the 1-byte lottery process has not been won (when the determination in S574 is NO), the main CPU 101 ends the CT lottery process during CT and performs the process at the start of CT (FIG. (Refer to 118), move to S557.

On the other hand, in S574, when the main CPU 101 determines that the 1-byte lottery process has been won (when the determination in S574 is YES), the main CPU 101 adds "1" to the number of CT sets (S575). Then, after the processing of S575, the main CPU 101 ends the CT lottery processing during CT, and shifts the processing to S557 of the processing at the start during CT (see FIG. 118).

[Table data acquisition process]
Next, the table data acquisition process performed in S572 during the CT lottery process during CT (see FIG. 119) will be described with reference to FIGS. 120 to 122. FIG. 120 is a flowchart showing the procedure of the table data acquisition process. Further, FIG. 121 is a diagram showing an example of a source program for executing the table data acquisition process, and FIG. 122 is a diagram actually referred to on the source program of the CT lottery process and the table data acquisition process during CT. It is a figure which shows an example of the structure of the CT lottery table in CT (corresponding to the lottery table which added the number of sets in CT explained with FIG. 56). The specific lottery values stored in the CT lottery table during CT shown in FIG. 122 are examples.

In the present embodiment, when the lottery value referred to in the CT lottery process during CT is acquired, the lottery value is stored through the two-step address calculation process (first-step and second-step table data acquisition process). Calculate the address. First, in the first-stage table data acquisition process (processes S582 and S583 described later), a "selection value (1 byte)" associated with the internal winning combination (actually, the sub flag D) is acquired. The selected value is provided for each type of internal winning combination, it is possible to determine whether or not the internal winning combination is a lottery target, and it is possible to specify the placement destination of the lottery table associated with the internal winning combination. Value (relative value) is specified. Further, in the present embodiment, the selection value "0" is defined in advance for the internal winning combination (actually, the sub-flag D) in which the lottery result of the CT lottery processing during CT is non-winning, and the internal winning combination is set to 1. It is treated as "miss" at the time of the table data acquisition process of the stage. Then, in the second stage table data acquisition processing (processing of S585 to S587 described later), an address in which the lottery value of the internal winning combination in which the selection value other than "0" is defined is stored is calculated (lottery table). The address is calculated by adding the relative value (selected value) from the reference address (2 bytes) of.

First, the main CPU 101 refers to the CT lottery selection table during CT (not shown), and addresses the first and second stages of additional selection data for calculating the address of the CT lottery table during CT, and the CT. The number of lottery lottery (twice in this embodiment) is acquired (S581). Next, the main CPU 101 adds the address of the first-stage addition selection data to the address of the CT lottery table during CT to calculate the first-stage selection address (S582).

Next, the main CPU 101 acquires the selection value stored in the calculated first-stage selection address (S583). Next, the main CPU 101 determines whether or not the selected value is "0" (S584).

In S584, when the main CPU 101 determines that the selected value is "0" (when the determination in S584 is YES), the main CPU 101 ends the table data acquisition process and performs the CT lottery process during CT (FIG. 119). (See) to S573.

On the other hand, in S584, when the main CPU 101 determines that the selection value is not "0" (when the determination in S584 is NO), the main CPU 101 adds the selection value to the selection address to obtain the selection address of the second stage. Calculate (S585). Next, the main CPU 101 adds the address of the second-stage addition selection data to the second-stage selection address to calculate the selection address (S586).

Next, the main CPU 101 acquires the selection value stored in the selection address calculated in S586, adds the selection value to the selection address, and calculates the address to be referred to in the CT lottery table during CT (S587). .. Then, after the processing of S587, the main CPU 101 ends the table data acquisition processing, and shifts the processing to S573 of the CT lottery processing during CT (see FIG. 119).

In the present embodiment, the table data acquisition process is performed as described above. Then, the above-mentioned table data acquisition process is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 121.

Among them, in the first stage table data acquisition processing (processing of S581 to S584), the data was stored in the areas from the addresses "dCTCTSTTB" to "dCTCTS_RER-1" in the CT winning lottery table during CT shown in FIG. 122. The table (table selection relative table by winning combination) is referred to. In addition, in the table selection relative table (lottery table selection table) for each winning combination, each combination in which the CT winning is lost (sub-flag D "missing", "cactus", "weak cherry", "strong cherry", "fixed role" , "Triple chili lip"), "0" is stored as the selection value (relative value) described above. Then, in the first stage table data acquisition process (address calculation process), when the selected value is "0", the lottery result is set to "miss" (see the determination process in S584 above).

In the CT-in-CT winning lottery table having the above configuration, in the winning combination table selection relative table referred to in the first stage table data acquisition process, "loss" can be set only by the combination type, so that the lottery table can be set. It is no longer necessary to specify the lottery value for the "lost" role. Therefore, in the present embodiment, it is not necessary to store the lottery value data (“0”) of the “missing” role in the CT winning lottery table during CT, and the capacity of the table area of the main ROM 102 can be saved.

Further, in the processing of S587 during the table data acquisition processing (processing of S585 to S587) in the second stage (at the time of acquiring the sub-flag D “reach eye lip”), the CT shown in FIG. 122 is based on the calculated lottery table address. From the medium CT winning lottery table (corresponding to the lottery table with the number of sets added during CT in FIG. 56), the lottery table (starting address "dNMCTTS_RR") used in the normal CT state or the lottery table in the high probability CT state (starting address "dSPCTTS_RR"). ) Is selected.

In the lottery table used in the high-probability CT state, as shown in FIG. 122, a "judgment bit" (judgment data) composed of 1-byte data is stored in the address area next to the start address "dSPCTTS_RER". In the determination bit, data indicating a range of addresses in which the lottery value to be drawn is stored is stored. As in the example shown in FIG. 122, when the lottery value of the lottery target (high probability CT) is stored only in the next address of the storage area of the "judgment bit" of the lottery table in the high probability CT state, the judgment is made. In the bit storage area, 1-byte data "00000001B" in which "1" is stored only in bit 0 is stored as a determination bit. On the other hand, when the lottery value of the lottery target (high-accuracy CT and normal CT) is stored in the next address and the next address of the determination bit storage area as in the lottery table used in the normal CT state, FIG. 122 As shown in the above, 1-byte data “00000011B” in which “1” is stored only in bits 0 and 1 is stored as a determination bit in the determination bit storage area. When such a determination bit is provided, it is not necessary to store lottery value data that is not subject to lottery in the area of the address where the bit data is "0" in the determination bit in the lottery table.

Further, in the lottery table used in the high-probability CT state, as shown in FIG. 122, the lottery value of the high-probability CT win is stored in the address "dSPCTCTS_RER + 2" next to the "judgment bit", and is used as the lottery value of the high-probability CT win. The data specified in the address "cABS_HIT" is stored. In the present embodiment, the data defined in this address "cABS_HIT" is data indicating winning confirmation (100% winning) (hereinafter, referred to as "confirmed data"). Further, in the present embodiment, since it is not necessary to provide the lottery value data (“0”) for loss in the CT winning lottery table during CT, as shown in FIG. 122, the definite data defined in the address “cABS_HIT”. Can be specified as "0". That is, in the CT winning lottery table during CT having the above configuration, the lottery value "0" can be used as definite data.

As described in the lottery table for adding the number of sets during CT in FIG. 56, in the present embodiment, the “high probability CT winning” is always determined in the lottery for adding the number of sets during CT in the high probability CT state. Therefore, in the present embodiment, on the source program, the confirmed data can be stored as the lottery value of the high-probability CT win in the CT winning lottery table during CT shown in FIG. 122.

Like the lottery table in the second stage (when the sub-flag D “reach eye lip” is acquired) described above, the lottery target combination and the non-lottery target combination (sub flag D) of the CT lottery are determined by the value of each bit data constituting the determination bit. ) Is determined, so that it is not necessary to store the lottery value data (loss data) of the winning combination that is not subject to the lottery in the table. Further, the lottery value "0" can be used as the definite data in which the winning probability of the lottery target combination is 100%. From these facts, in this embodiment, the capacity of the CT winning lottery table during CT (the lottery table with the number of sets added during CT) can be compressed, and the free space can be secured (increased) in the main ROM 102. , It will be possible to improve the playability by utilizing the increased free space. Further, in the present embodiment, an example in which this technique is used in the CT winning process during CT has been described, but the present invention is not limited to this, and the ART lottery (see FIG. 115) and the number of ART games added lottery (see FIG. 117). ), CT lottery described later (see FIG. 154 described later), CZ pullback lottery described later (see FIG. 157 described later), and the like.

[1 byte lottery processing]
Next, with reference to FIGS. 123 and 124, the 1-byte lottery process performed in S573 during the CT lottery process during CT (see FIG. 119) will be described. FIG. 123 is a flowchart showing the procedure of the 1-byte lottery process. Further, FIG. 124 is a diagram showing an example of a source program for executing the 1-byte lottery process.

First, the main CPU 101 sets a 1-byte random number value (0 to 255: soft latch random number of the random number register 4 of the random number circuit 110) stored in the random number storage area (not shown) in the main RAM 103 for CT lottery during CT. Set (S591). Next, the main CPU 101 obtains lottery determination data (determination bits in the lottery table defined in the second stage of FIG. 122) from the CT lottery table during CT based on the address calculated in S587 during the table data acquisition process. Acquire (S592). Further, in this process, the main CPU 101 sets the number of determination bits "8" as the initial value of the number of lottery.

Next, the main CPU 101 determines whether or not the lottery determination data is a lottery target (S593). In this determination process, the main CPU 101 refers to the bit data in the determination bit associated with the current number of lottery, and if the bit data is "1", it determines that the lottery target is selected. In the present embodiment, the bits 0 to 7 in the determination bit are associated with the number of lottery "8" to "1", respectively.

In S593, when the main CPU 101 determines that the lottery determination data is not the lottery target (when the determination in S593 is NO), the main CPU 101 performs the process of S599 described later. On the other hand, in S593, when the main CPU 101 determines that the lottery determination data is the lottery target (when the determination in S593 is YES), the main CPU 101 acquires the lottery value from the CT lottery table during CT (S594).

Next, the main CPU 101 determines whether or not the lottery value is "0" (winning confirmation data) (S595).

In S595, when the main CPU 101 determines that the lottery value is "0" (when the determination in S595 is YES), the main CPU 101 ends the 1-byte lottery process, and performs the CT lottery process during CT (FIG. 119). (See) to S574. On the other hand, in S595, when the main CPU 101 determines that the lottery value is not "0" (when the determination in S595 is NO), the main CPU 101 performs a CT lottery (additional lottery of the number of CT sets) process (S596). Specifically, the main CPU 101 subtracts a lottery value from a random number value (1 byte random value), and uses the subtraction result as a random number value.

Next, the main CPU 101 determines whether or not the CT lottery of S596 has been won (S597). In the CT lottery of S596, the main CPU 101 determines that the winning result is obtained when the subtraction result of S596 is "0" or less (when a so-called "digit shift" occurs).

In S597, when the main CPU 101 determines that the CT lottery has been won (when the determination in S597 is YES), the main CPU 101 ends the 1-byte lottery process, and the process is the CT lottery process during CT (see FIG. 119). Move to S574. On the other hand, in S597, when the main CPU 101 determines that the CT lottery has not been won (when the determination in S597 is NO), the main CPU 101 refers to the lottery value storage address (lottery address) in the CT lottery table during CT. Is updated to the next lottery address (S598).

After the processing of S598 or when the determination in S593 is NO, the main CPU 101 subtracts 1 from the number of lottery (S599). Next, the main CPU 101 determines whether or not the number of lottery is "0" (S600).

In S600, when the main CPU 101 determines that the number of lottery is not "0" (when the determination in S600 is NO), the main CPU 101 returns the process to S593 and repeats the processes after S593. On the other hand, in S600, when the main CPU 101 determines that the number of lottery is "0" (when the determination in S600 is YES), the main CPU 101 ends the 1-byte lottery process, and performs the CT lottery process during CT (CT lottery process). (See FIG. 119).

In the present embodiment, the 1-byte lottery process is performed as described above. The 1-byte lottery process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 124.

In the random number acquisition process of S591 during the 1-byte lottery process, as shown in FIG. 124, an "LDQ" instruction, which is an instruction code dedicated to the main CPU 101 that specifies an address using a Q register (extension register), is issued on the source program. Used. Therefore, in the present embodiment, even in the 1-byte lottery process, the main ROM 102, the main RAM 103, and the memory map I / O are accessed by the direct value by using the instruction code using the Q register (extension register). Therefore, the instruction code related to the address setting can be omitted, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Processing at start during BB]
Next, with reference to FIG. 125, the BB start-time processing performed in S415 during the state-specific control processing (see FIG. 104) will be described. Note that FIG. 125 is a flowchart showing the procedure of the start processing during BB.

First, the main CPU 101 refers to the bonus lottery table for adding the number of ART games (see FIG. 59), and performs the lottery process for adding the number of ART games based on the internal winning combination (S611). Next, the main CPU 101 determines whether or not the additional lottery has been won (S612).

In S612, when the main CPU 101 determines that the additional lottery has not been won (when the determination in S612 is NO), the main CPU 101 ends the BB start processing and also performs the state-specific control processing (see FIG. 104). finish. On the other hand, in S612, when the main CPU 101 determines that the additional lottery has been won (when the determination in S612 is YES), the main CPU 101 adds the winning result (the number of additional games) to the ART end game number counter (S613). ..

Next, the main CPU 101 determines whether or not the number of ART sets is "0" (S614). When the main CPU 101 determines in S614 that the number of ART sets is not "0" (when the determination in S614 is NO), the main CPU 101 ends the BB start processing and the state-specific control processing (see FIG. 104). ) Also ends.

On the other hand, in S614, when the main CPU 101 determines that the number of ART sets is "0" (when the determination in S614 is YES), the main CPU 101 adds "1" to the number of ART sets (S615). Then, after the processing of S615, the main CPU 101 ends the processing at the start during BB, and also ends the state-specific control processing (see FIG. 104).

[Pull-in priority storage process]
Next, with reference to FIGS. 126 and 127, the pull-in priority storage process performed in S212 in the main flow (see FIG. 82) will be described. FIG. 126 is a flowchart showing the procedure of the pull-in priority storage process. Further, FIG. 127 is a diagram showing an example of a source program for executing the processes of S625 and S626 described later during the attraction priority storage process.

First, the main CPU 101 sets "3" to the number of search reels (S621). Next, the main CPU 101 performs a pull-in priority table selection process (S622). In this process, the pull-in priority table (see FIG. 27) is selected based on the internal winning combination and the operation stop button.

Next, the main CPU 101 performs a pull-in priority storage area selection process (S623). In this process, the pull-in priority data storage area of the reel to be searched is selected. Next, the main CPU 101 sets "20" as the number of symbol checks (number of times) (S624).

Next, the main CPU 101 performs a symbol code acquisition process (S625). In this process, the symbol code is acquired by referring to the winning operation flag storage area and the symbol code storage area corresponding to the number of symbol checks. The details of the symbol code acquisition process will be described later with reference to FIG. 128 described later.

Next, the main CPU 101 performs a logical product calculation process (S626). In this process, the main CPU 101 performs a process of generating the winning operation flag data. The details of the logical product calculation process will be described later with reference to FIG. 133 described later.

Next, the main CPU 101 performs a pull-in priority acquisition process (S627). In this process, in the main CPU 101, the bit is set to "1" in the winning operation flag (winning combination) storage area (see FIGS. 28 to 30), and the bit is set to "1" in the hit request flag storage area. With reference to the attraction priority table (see FIG. 27), the attraction priority data is acquired for the winning combination. The details of the pull-in priority acquisition process will be described later with reference to FIGS. 134 and 135 described later.

Next, the main CPU 101 stores the acquired attraction priority data in the attraction priority data storage area (not shown) in the main RAM 103 (S628). At this time, the attraction priority data is stored in the attraction priority data storage area so that the value of each priority and the bit of the storage area correspond to each other.

The pull-in priority data storage area is provided with a priority data storage area for each type of main reel. In each attraction priority data storage area, the attraction priority data determined according to each symbol position "0" to "19" of the corresponding main reel is stored. In the present embodiment, by referring to this attraction priority data storage area, it is searched whether or not a more appropriate number of sliding pieces exists in addition to the number of sliding pieces determined based on the stop table.

The content of the priority pull-in data stored in the pull-in priority data storage area differs depending on the type of the pull-in priority table number in the pull-in priority table referred to when determining the pull-in priority data. Further, the pull-in priority data indicates that the larger the value, the higher the priority. By referring to the pull-in priority data, it is possible to relatively evaluate the priority among the symbols arranged on the peripheral surface of the main reel. That is, the symbol whose highest value is determined as the attraction priority data is the symbol having the highest priority. Therefore, it can be said that the pull-in priority data indicates the order between the symbols arranged on the peripheral surface of the main reel. If there are a plurality of symbols having the same value of the pull-in priority data, one symbol is determined according to the priority order defined by the priority order table.

Next, the main CPU 101 updates the pull-in priority storage area (S629). In this process, the main CPU 101 sets a pull-in priority data storage area for the next check symbol. Next, the main CPU 101 subtracts 1 from the number of symbol checks (S630). Next, the main CPU 101 determines whether or not the number of symbol checks is "0" (S631).

In S631, when the main CPU 101 determines that the number of symbol checks is not "0" (when the determination in S631 is NO), the main CPU 101 returns the process to the process of S625 and repeats the processes after S625. On the other hand, in S631, when the main CPU 101 determines that the number of symbol checks is "0" (when the determination in S631 is YES), the main CPU 101 performs a search target reel change process (S632).

Next, the main CPU 101 subtracts 1 from the number of search reels (S633). Next, the main CPU 101 determines whether or not the number of search reels is "0", that is, whether or not the above-mentioned series of processes has been performed on all the main reels (S634).

In S634, when the main CPU 101 determines that the number of search reels is not "0" (when the determination in S634 is NO), the main CPU 101 returns the process to the process of S622 and repeats the processes after S622. On the other hand, in S634, when the main CPU 101 determines that the number of search reels is "0" (when the determination in S634 is YES), the main CPU 101 ends the attraction priority storage process and performs the process in the main flow (FIG. FIG. (Refer to 82), move to S213.

In the present embodiment, the attraction priority storage process is performed as described above. The processing of S625 and S626 during the above-described attraction priority storage processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 127.

Among them, the logical product calculation process of S626 is performed by the main CPU 101 executing the source code "CALLF SB_DAND_00" in FIG. 127. The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_DAND_00" in FIG. 127 is executed, processing is performed at the address specified by "SB_DAND_00". The jump is made and the logical product calculation process is started.

[Design code acquisition process]
Next, the symbol code acquisition process performed in S625 during the attraction priority storage process (see FIG. 126) will be described with reference to FIGS. 128 to 132. FIG. 128 is a flowchart showing the procedure of the symbol code acquisition process, and FIG. 129 is a diagram showing an example of a source program for executing the symbol code acquisition process. FIG. 130A is a diagram showing an example of the configuration of the first reel (left reel) symbol arrangement table actually referred to on the source program of the symbol code acquisition process, and FIG. 130B is a diagram showing a first reel symbol arrangement table set. It is a figure which shows an example of the structure of the symbol correspondence winning operation table which is sometimes referred to. FIG. 131A is a diagram showing an example of the configuration of the second reel (middle reel) symbol arrangement table actually referred to on the source program of the symbol code acquisition process, and FIG. 131B is a diagram showing a second reel symbol arrangement table set. It is a figure which shows an example of the structure of the symbol correspondence winning operation table which is sometimes referred to. Further, FIG. 132A is a diagram showing an example of the configuration of the third reel (right reel) symbol arrangement table actually referred to on the source program of the symbol code acquisition process, and FIG. 132B is a diagram showing the third reel symbol arrangement. It is a figure which shows an example of the structure of the symbol correspondence winning operation table which is referred to at the time of table setting.

First, the main CPU 101 clears the winning operation flag storage area (S641). In this process, the main CPU 101 sets "0" in all the storage areas in the winning operation flag storage area (see FIGS. 28 to 30). Next, the main CPU 101 sets the first reel symbol arrangement table (see FIG. 130A) (S642).

Next, the main CPU 101 determines whether or not the first reel (left reel 3L) is stopped (S643).

In S643, when the main CPU 101 determines that the first reel (left reel 3L) is stopped (when the determination in S643 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, in S643, when the main CPU 101 determines that the first reel (left reel 3L) is not stopped (when the determination in S643 is NO), the main CPU 101 uses the second reel symbol arrangement table (see FIG. 131A). Set (S644). In this process, the first reel symbol arrangement table set in the process of S642 is overwritten by the second reel symbol arrangement table.

Next, the main CPU 101 determines whether or not the second reel (middle reel 3C) is stopped (S645).

In S645, when the main CPU 101 determines that the second reel (middle reel 3C) is stopped (when the determination in S645 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, in S645, when the main CPU 101 determines that the second reel (middle reel 3C) is not stopped (when the determination in S645 is NO), the main CPU 101 uses the third reel symbol arrangement table (see FIG. 132A). Set (S646). In this process, the second reel symbol arrangement table set in the process of S644 is overwritten by the third reel symbol arrangement table.

After the processing of S646, or when the determination of S643 or S645 is YES, the main CPU 101 performs the symbol check processing at the time of executing the stop operation on the reel to be stopped controlled, and corresponds to the symbol corresponding to the symbol acquired by the symbol check processing. Acquire the winning operation table (S647). For example, when the first reel (left reel 3L) is stopped and the symbol located on the effective line during the stop operation is "white 7", the main CPU 101 has the address "dR1_SVN1" to the address "dR1_SVN2" in FIG. 130B. Obtain the start address of the symbol-corresponding winning operation table specified in the block in the range of -1 ”.

Next, the main CPU 101 sets the winning operation flag storage area (S648). Next, the main CPU 101 performs the compressed data storage process described with reference to FIG. 101 (S649). In this process, the main CPU 101 mainly performs a process of transferring (expanding) the winning operation flag data stored in the symbol-corresponding winning operation table to the corresponding storage area in the winning operation flag storage area.

For example, when the first reel (left reel 3L) is stopped and the symbol located on the effective line during the stop operation is "white 7", the symbol combinations (combinations) that can be won are shown in FIGS. 28 to 28 to FIG. As shown in 30, the combination names "C_2nd_A_01", "C_2nd_A_01" and "C_SP1_01" defined in the second storage area, and the combination names "C_9 sheets C_01" to "C_9 sheets C_03" defined in the third storage area, "C_9 sheets C_07" to "C_9 sheets C_09" and "C_9 sheets E_01", combination names defined in the fourth storage area "C_RB role A_01", "C_RB role A_02", "C_RB role B_01" to "C_RB role B_04" , "C_RB role C_01" and "C_RB role C_02", combination names defined in the sixth storage area "C_reach eye lip C_01" to "C_reach eye lip C_03", "C_reach eye lip D_01", "C_ Reach eye lip D_02 "and" C_reach eye lip E_01 ", and the combination name" C_BB1 "defined in the tenth storage area.

In this case, the storage destination of the first block (the 0th to 7th storage areas) of the winning operation flag data stored in the symbol-corresponding winning operation table is stored in the address "dR1_SVN1 + 1" in the table shown in FIG. 130B. It is designated by the 1-byte designated data "01011100B" (see the comment "storage area +2, +3, +4, +6" column in FIG. 130B). Further, the storage destination of the second block (8th to 11th storage areas) of the winning operation flag data stored in the symbol-corresponding winning operation table is stored in the address "dR1_SVN1 + 6" in the table shown in FIG. 130B. It is designated by the 1-byte designated data "10000000B" (see the comment "storage area +10" column in FIG. 130B).

In the present embodiment, the bits 0 to 7 of the designated data of the first block are bits for designating the 0th to 7th storage areas of the first block as storage destinations, respectively, and the designated data of the second block. Bits 0 to 3 are bits that specify the 8th to 11th storage areas of the second block as storage destinations, respectively. Then, in the 1-byte designated data of each block, "1" is stored in the bit corresponding to the storage area in the winning operation flag storage area, which is the storage destination of the winning operation flag data.

Therefore, for example, when the first reel (left reel 3L) is stopped and the symbol located on the effective line during the stop operation is "white 7", the address in the table shown in FIG. 130B in the processing of S649. The winning operation flag data "00010000B" or "00000100B" stored in "dR1_SVN1 + 2" is transferred from the symbol-corresponding winning operation table to the second storage area in the winning operation flag storage area, and stored in the address "dR1_SVN1 + 3". The winning operation flag data "00100000B" or "00000100B" is transferred from the symbol-corresponding winning operation table to the third storage area in the winning operation flag storage area. Further, in this case, in the process of S649, the winning operation flag data "10000000B", "01000000B" or "001000000B" stored in the address "dR1_SVN1 + 4" in the table shown in FIG. The winning operation flag data "00100000B", "00010000B" or "00001000B" transferred to the fourth storage area in the operation flag storage area and stored at the address "dR1_SVN1 + 5" is stored in the winning operation flag from the symbol-corresponding winning operation table. It is transferred to the sixth storage area in the area. Further, in this case, in the process of S649, the winning operation flag data "10000000B" stored in the address "dR1_SVN1 + 8" in the table shown in FIG. Transferred to storage area.

After the processing of S649, the main CPU 101 sets the winning operation flag storage area updated by the compressed data storage processing, sets the symbol code storage area, and the data length of the winning operation flag storage area (12 bytes in this embodiment). Is set (S650). Then, after the processing of S650, the main CPU 101 ends the symbol code acquisition processing, and shifts the processing to S626 of the pull-in priority storage processing (see FIG. 126).

In the present embodiment, the symbol code acquisition process is performed as described above. The symbol code acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 129. Among them, the compressed data storage process of S649 is performed by the main CPU 101 executing the source code "CALLF SB_BTEP_00" in FIG. 129.

The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_BTEP_00" in FIG. 129 is executed, processing is performed at the address specified by "SB_BTEP_00". Jump and start the compressed data storage process. Then, in this compressed data storage process, as described above, the winning operation flag data (compressed data) stored in the symbol-corresponding winning operation flag table of each reel is expanded (copied) in the winning operation flag storage area.

In this embodiment, the data related to the winning is compressed / decompressed by the processing procedure described in S647 to S649 during the symbol code acquisition process described above, and the command code dedicated to the main CPU 101 described above is performed in the process. By using the above, it is possible to improve the efficiency of the compression / decompression processing of the data related to the winning, and it is possible to effectively utilize the limited capacity of the main RAM 103.

Further, in the present embodiment, in the compressed data storage process of S649 during the symbol code acquisition process, the jump destination address “SB_BTEP_00” specified by the “CALLF” command is the compression of S330 during the symbol setting process described with reference to FIG. 97. In the data storage process, it is the same as the jump destination address specified by the "CALLF" instruction. That is, in the present embodiment, the source program for executing the compressed data storage process performed in the symbol code acquisition process is the same as the source program for executing the compressed data storage process performed in the symbol setting process, and is S649 and S330. In both processes, the source program for the compressed data storage process is shared (modularized). In this case, since it is not necessary to separately provide the source program for the compressed data storage process in both the processes S649 and S330, the capacity of the source program (capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Logical product operation processing]
Next, with reference to FIG. 133, for example, the logical product calculation process performed in S626 during the attraction priority storage process (see FIG. 126) will be described. FIG. 133 is a flowchart showing the procedure of the logical product calculation process. The logical product calculation process shown in FIG. 133 is not only in S626 in the attraction priority storage process (see FIG. 126), but also in S687 in the attraction priority acquisition process (see FIGS. 134 and 135 described later). Is also executed.

In the logical product calculation process executed in S626 during the pull-in priority storage process (see FIG. 126), the two data to be ANDed are stored in the winning operation flag set in S650 during the symbol code acquisition process described above. It is the data of the area and the data of the symbol code storage area. The former data corresponds to the "logical product destination data" described later, and the latter data corresponds to the "logical product source data" described later. Further, in this case, the number of bytes "12" of the data length (12 bytes) set in S650 during the above-mentioned symbol code acquisition process corresponds to the "number of logical products" described later.

On the other hand, in the logical product operation process executed in S687 in the attraction priority acquisition process (see FIGS. 134 and 135 described later), the two data to be ANDed are the hit (retract) request flag storage area. Data and data of the winning operation flag storage area. The former data corresponds to the "logical product destination data" described later, and the latter data corresponds to the "logical product source data" described later. Further, in this case, the number of bytes “1” of the data length (1 byte) of the RT operation combination display flag described in FIG. 136B described later corresponds to the “number of logical products” described later.

First, the main CPU 101 acquires the logical product source data (for example, the data of the symbol code storage area) (S661). Next, the main CPU 101 performs a logical product operation of the logical product source data and the logical product destination data (for example, data in the winning operation flag storage area), and saves the calculation result as the logical product destination data (S662).

Next, the main CPU 101 adds 1 to the address of the logical product source data to be acquired (S663). Next, the main CPU 101 adds 1 to the address of the logical product destination data to be referred to (S664).

Next, the main CPU 101 subtracts 1 from the number of logical products (S665). Next, the main CPU 101 determines whether or not the number of logical products is "0" (S666).

In S666, when the main CPU 101 determines that the number of logical products is not "0" (when the determination in S666 is NO), the main CPU 101 returns the process to the process of S661 and repeats the processes after S661. On the other hand, in S666, when the main CPU 101 determines that the number of logical products is "0" (when the determination in S666 is YES), the main CPU 101 ends the logical product calculation process and stores the process, for example, in the pull-in priority order. The process moves to S627 of the process (see FIG. 126).

[Pull-in priority acquisition process]
Next, the attraction priority acquisition process performed in S627 during the attraction priority storage process (see FIG. 126) will be described with reference to FIGS. 134 to 137. Note that FIGS. 134 and 135 are flowcharts showing the procedure of the attraction priority acquisition process. FIG. 136A is a diagram showing an example of a source program for executing the process of S680 to S683 described later during the attraction priority acquisition process, and FIG. 136B shows the process of S686 described later during the attraction priority acquisition process. FIG. 136C is a diagram showing an example of a source program for execution, and FIG. 136C is a diagram showing an example of a source program for executing the process of S687 described later during the pull-in priority acquisition process. Further, FIG. 137 is a diagram showing an example of the configuration of the attraction priority table that is actually referred to on the source program of the attraction priority acquisition process.

First, the main CPU 101 determines whether or not it is time to check the right reel 3R (specific display column) (S671).

When the main CPU 101 determines in S671 that it is not the time to check the right reel 3R (when the determination in S671 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S671, when the main CPU 101 determines that it is time to check the right reel 3R (when the determination in S671 is YES), the main CPU 101 "ANY combination" in the symbol combination (winning combination) related to the internal winning combination. It is determined whether or not (a combination of predetermined symbols) is included (S672). The "ANY combination" here means a combination in which the winning is confirmed regardless of at least the stop symbol of the right reel 3R (at least the winning combination in which the stop symbol of the right reel 3R is an arbitrary symbol).

In S672, when the main CPU 101 determines that the symbol combination related to the internal winning combination does not include the "ANY combination" (when the determination in S672 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S672, when the main CPU 101 determines that the symbol combination related to the internal winning combination includes the "ANY combination" (when the determination in S672 is YES), the main CPU 101 determines that the "ANY combination" in the winning operation flag storage area. The storage area corresponding to the "combination" is masked (S673). Specifically, the main CPU 101 sets "1" in the bit corresponding to the "ANY combination" in the winning operation flag storage area.

After the processing of S673, or when S671 or S672 is determined to be NO, the main CPU 101 sets "1" to the address of the last storage area as the address of the winning operation flag storage area (see FIGS. 28 to 30). The added address is set, the stop prohibition data is set, and the winning operation flag data length (data length of the winning operation flag storage area: 12 bytes in this embodiment) is set (S674). Next, the main CPU 101 acquires the value of the stock button operation counter and the stop button operation state (S675). The stop button operation counter is a counter for managing the number of stop buttons for which a stop operation is detected. Further, the operation stop button operation state is acquired by referring to the operation stop button storage area (see FIG. 33).

Next, the main CPU 101 subtracts (updates -1) the address of the set winning operation flag storage area by 1 (S676). Next, the main CPU 101 generates hit request flag data from the set winning operation flag storage area and the corresponding hit request flag storage area (see FIGS. 28 to 30), and the generated hit request flag data. The prohibited winning operation position is generated based on (S677).

Next, the main CPU 101 determines whether or not the stop operation position is the prohibited winning operation position (S678).

In S678, when the main CPU 101 determines that the stop operation position is not the prohibited winning operation position (when the determination in S678 is NO), the main CPU 101 performs the process of S684 described later. On the other hand, in S678, when the main CPU 101 determines that the stop operation position is the prohibited winning operation position (when the determination in S678 is YES), the value of the stop button operation counter of the main CPU 101 is the value of the third stop. Whether or not it is determined (S679).

In S679, when the main CPU 101 determines that the value of the stop button operation counter is the value of the third stop (when the determination in S679 is YES), the main CPU 101 performs the process of S705 described later. On the other hand, in S679, when the main CPU 101 determines that the value of the stop button operation counter is not the value of the third stop (when the determination in S679 is NO), the value of the stop button operation counter of the main CPU 101 is the second stop. It is determined whether or not it is a value (S680).

In S680, when the main CPU 101 determines that the value of the stop button operation counter is not the value of the second stop (when the determination in S680 is NO), the main CPU 101 performs the process of S684 described later. On the other hand, in S680, when the main CPU 101 determines that the value of the stop button operation counter is the value of the second stop (when the determination in S680 is YES), whether or not the main CPU 101 is after the right reel 3R is stopped. (S681).

When the main CPU 101 determines in S681 that the right reel 3R has been stopped (when the determination in S681 is YES), the main CPU 101 performs the process of S684 described later. On the other hand, in S681, when the main CPU 101 determines that the right reel 3R has not been stopped (when the determination in S681 is NO), the main CPU 101 has a flag that the hit request flag may be interfered with by the "ANY combination". It is determined whether or not (whether or not "ANY combination" is not included in the symbol combination (winning combination) related to the internal winning combination) (S682).

In S682, when the main CPU 101 determines that the hit request flag is not a flag that may be interfered with by the "ANY combination" (when the determination in S682 is YES), the main CPU 101 performs the process of S684 described later. On the other hand, in S682, when the main CPU 101 determines that the hit request flag is a flag that may be interfered with by the "ANY combination" (when the determination in S682 is NO), the main CPU 101 currently checks "ANY". It is determined whether or not it is time to check the hit request flag including the "combination" (S683).

In S683, when the main CPU 101 determines that the current check is the time to check the hit request flag including the "ANY combination" (when the determination in S683 is YES), the main CPU 101 performs the process of S705 described later.

On the other hand, in S683, when the main CPU 101 determines that the current check is not at the time of checking the hit request flag including "ANY combination" (when S683 is NO determination), when S678 or S680 is NO determination, or S681. Alternatively, when the determination in S682 is YES, the main CPU 101 subtracts 1 from the winning operation flag data length (S684). Next, the main CPU 101 determines whether or not the winning operation flag data length is “0” (S685).

In S685, when the main CPU 101 determines that the winning operation flag data length is not "0" (when the determination in S685 is NO), the main CPU 101 returns the processing to the processing of S676 and repeats the processing after S676.

On the other hand, in S685, when the main CPU 101 determines that the winning operation flag data length is "0" (when the determination in S685 is YES), the main CPU 101 performs a stop control pull-in request flag setting process (S686). .. This process is performed by sequentially executing each process specified in the source program of FIG. 136B by the main CPU 101. Therefore, in this process, the AND operation process described with reference to FIG. 133 is performed. In the logical product operation process executed in the process of S686, as described above, the data of the hit (pull-in) request flag storage area is set in the "logical product destination data", and the data of the winning operation flag storage area is set. It is set in the "logical product source data", and the number of bytes "1" of the data length (1 byte) of the RT operation combination display flag is set in the "logical product count". The RT operation combination display flag is a storage area in which the symbol combination related to the RT transition is defined in the winning operation flag storage area, and in the present embodiment, only the storage area 11 is defined as shown in FIGS. 28 to 30. Become.

Next, the main CPU 101 refers to the pull-in priority table address storage area and acquires the pull-in priority table (S687). This process is performed by sequentially executing each process specified in the source program of FIG. 136C by the main CPU 101. Therefore, in this process, the initial value "1 (001H)" of the pull-in priority data is set to the currently set address, and the start address shown in FIG. 137 is "dPLVLTB00" to "dPLVLTB05". The pull-in priority table stored in one of the blocks is acquired. The attraction priority tables stored in the blocks whose start addresses are "dPLVLTB00" to "dPLVLTB05" shown in FIG. 137 are the attraction priority table numbers "00" to "05" shown in FIG. 27, respectively. Corresponds to the pull-in priority table.

Next, the main CPU 101 determines whether or not the data in the pull-in priority table stored at the currently set address is the end code (000H) (S688).

In S688, when the main CPU 101 determines that the data in the pull-in priority table stored at the currently set address is the end code (when the determination in S688 is YES), the main CPU 101 uses S705, which will be described later. Is processed. On the other hand, in S688, when the main CPU 101 determines that the data in the pull-in priority table stored at the currently set address is not the end code (when the determination in S688 is NO), the main CPU 101 operates the winning operation. The flag storage area is set (S689).

Next, the main CPU 101 acquires the attraction priority data from the attraction priority table based on the currently set address (S690). Next, the main CPU 101 sets the block counter of the pull-in priority table (S691). In the present embodiment, in this process, the main CPU 101 sets "2" to the value of the block counter in the pull-in priority table.

Next, the main CPU 101 sets the number of checks of the attraction priority table, and adds 1 (+1 update) to the address of the attraction priority table to be referred to (S692). In this embodiment, in this process, the main CPU 101 sets the number of checks in the pull-in priority table to "8" (the number of bits of check data defined in the pull-in priority table shown in FIG. 137).

Next, the main CPU 101 acquires check data (see FIG. 137) based on the updated address of the pull-in priority table, and extracts check bits from the check data (S693). In the present embodiment, the check bit extracted here corresponds to bit 0 of the check data. For example, in the processing of S690, when the attraction priority data "03EH" is acquired from the attraction priority table defined in the block whose start address is "dPLVLTB00", in the processing of S693, "10001000B" is set as the check data. It is acquired and "0" is extracted as the value of the check bit.

Next, the main CPU 101 determines whether or not the value of the extracted check bit is “1” (S694).

In S694, when the main CPU 101 determines that the value of the extracted check bit is not "1" (when the determination in S694 is NO), the main CPU 101 performs the process of S699 described later. On the other hand, in S694, when the main CPU 101 determines that the value of the extracted check bit is "1" (when the determination in S694 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referred to. (+1 update), and based on the updated address, determination data (“flag determination data” in FIG. 137) is acquired from the pull-in priority table (S695).

Next, the main CPU 101 determines whether or not the currently acquired winning operation flag data is the determination target based on the determination data acquired in S695 (S696). In this process, the main CPU 101 compares the currently acquired winning operation flag data with the determination data, determines whether or not the former corresponds to the latter, and the former corresponds to the latter. In that case, it is determined that the currently acquired winning operation flag data is the determination target.

In S696, when the main CPU 101 determines that the winning operation flag data is not the determination target (when the determination in S696 is NO), the main CPU 101 performs the process of S699 described later. On the other hand, in S696, when the main CPU 101 determines that the winning operation flag data is the determination target (when the determination in S696 is YES), the main CPU 101 updates the attraction priority data (S697). In this process, the main CPU 101 updates (overwrites) the currently set attraction priority data with the attraction priority data associated with the determination data acquired in S697.

Next, the main CPU 101 updates the check data (S698). In this process, the main CPU 101 shifts the check data by one bit to the right (direction from bit 7 to bit 0). In this process, "0" is set in the bit 7 of the check data after the shift.

After the processing of S698, or when S694 or S696 is determined to be NO, the main CPU 101 determines whether or not there is a bit to be checked (a bit in which "1" is set) in the check data (S699).

In S699, when the main CPU 101 determines that there is no bit to be checked in the check data (when the determination in S699 is NO), the main CPU 101 performs the process of S702 described later. On the other hand, in S699, when the main CPU 101 determines that the check data has a bit to be checked (when the determination in S699 is YES), the main CPU 101 adds 1 to the address of the winning operation flag storage area to be checked (+1 update). ), And the number of checks is subtracted by 1 (S700).

Next, the main CPU 101 determines whether or not the number of checks is "0" (S701). When the main CPU 101 determines in S701 that the number of checks is not "0" (when the determination in S701 is NO), the main CPU 101 returns the process to the process of S698 and repeats the processes after S698.

On the other hand, in S701, when the main CPU 101 determines that the number of checks is "0" (when the determination in S701 is YES), the main CPU 101 sets the number of checks to the address of the winning operation flag storage area currently referred to. The initial value "8" is added to update the address of the winning operation flag storage area, and the value of the block counter is subtracted by 1 (S702). Next, the main CPU 101 determines whether or not the value of the block counter is "0" (S703).

In S703, when the main CPU 101 determines that the value of the block counter is not "0" (when the determination in S703 is NO), the main CPU 101 returns the process to the process of S692 and repeats the processes after S692.

On the other hand, in S703, when the main CPU 101 determines that the value of the block counter is "0" (when the determination in S703 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referred to (+1 update). ) (S704). For example, when the currently referenced pull-in priority table is the pull-in priority table specified in the block whose start address is "dPLVLTB00", this process causes the refer-in pull-in priority table to have a start address of "dPLVLTB00". It is changed to the pull-in priority table specified in the block which is "dPLVLTB01". Then, after the processing of S704, the main CPU 101 returns the processing to the processing of S688, and repeats the processing after S688.

Here, returning to the processing of S679, S683 or S688 again, if S679, S683 or S688 is a YES determination, the main CPU 101 uses the attraction order data set at this time as the final attraction priority data. Set (S705). If S679 or S683 is YES, the main CPU 101 sets "0 (00H)" as the final pull-in priority data. In this case, since the end code is assigned to the pull-in priority data "0 (00H)", no pull-in data (stop prohibition) is set. Then, after the processing of S705, the main CPU 101 ends the attraction priority acquisition process, and shifts the process to S628 of the attraction priority storage process (see FIG. 126).

In the present embodiment, the attraction priority acquisition process is performed as described above. The pull-in priority handling process of the “ANY combination” of S680 to S683 during the above-mentioned pull-in priority acquisition process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 136A. Be told. Among them, for example, the determination process of S683 is executed by a "JCP" instruction (predetermined determination instruction) on the source program. The "JCP" instruction is an instruction that executes an operation equivalent to a comparison instruction, and is an instruction code dedicated to the main CPU 101.

When, for example, the source code "JCP cc, A, n, e" is executed on the source program, the contents (stored data) of the A register are compared with the integer n, and the comparison result is the condition of cc. If so, the process is jumped to the address specified by e. In the "cc condition" of the "JCP" instruction, one of the carry flag state and the zero flag state in the flag register F is specified (see FIG. 11). For example, if "C" is specified for cc, the condition of cc means that the carry flag is "1" (on state), and if "NC" is specified for cc, the condition of cc. Means that the carry flag is "0" (off state). Further, for example, if "Z" is specified for cc, the condition of cc means that the zero flag is "1" (on state), and if "NZ" is specified for cc, the condition of cc is The condition means that the zero flag is "0" (off state).

As shown in FIG. 136A, when the "JCP" instruction is used on the source program of the pull-in priority correspondence process of the "ANY combination", the instruction related to the address setting can be omitted (the instruction related to the address setting is separately provided). Therefore, it is possible to increase the processing efficiency of the pull-in priority handling process of the "ANY combination" and reduce the capacity of the source program (the capacity used by the main ROM 102).

Further, the stop control pull-in request flag setting process of S686 during the above-mentioned pull-in priority acquisition process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 136B. In the stop control pull-in request flag setting process of S686, as shown in FIG. 136B, the "LDQ" instruction for specifying the address using the Q register (extension register), which is the instruction code dedicated to the main CPU 101, and the "CALLF". The instruction is used.

Therefore, by using the "LDQ" instruction using the Q register (extension register) in the stop control pull-in request flag setting process of S686, the main ROM 102, the main RAM 103, and the memory map I / O are accessed by the direct value. can do. In this case, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced. Further, the "CALLF" instruction is a 2-byte instruction code as described above. Therefore, by using these main CPU 101 dedicated instruction codes in the stop control pull-in request flag setting process, the processing efficiency can be improved and the limited capacity of the main RAM 103 can be effectively utilized. ..

Further, in the present embodiment, in the stop control pull-in request flag setting process of S686 during the priority pull-in order acquisition process, the address "SB_DAND_00" of the jump destination logical product operation process specified by the "CALLF" instruction is the above-mentioned FIG. 126. It is the same as the jump destination address specified by the "CALLF" instruction in the logical product operation processing of S626 during the attraction priority storage processing described in (see FIG. 127). That is, in the present embodiment, the source program for executing the AND operation processing performed in the stop control pull-in request flag setting process of S686 during the priority pull-in order acquisition process is the logic performed in S626 during the pull-in priority storage process. It is the same as the source program for executing the AND operation process, and the source program for the AND operation process is shared (modularized) in both the S686 and S626 processes. In this case, in both the processes of S686 and S626, it is not necessary to separately provide the source program for the AND operation processing, so that the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the acquisition process of the attraction priority table (see FIG. 137) of S687 during the above-mentioned attraction priority acquisition process, the main CPU 101 sequentially executes each source code defined by the source program of FIG. 136C. Will be done. Then, in the acquisition process of the pull-in priority table in S687, as shown in FIG. 136C, the "LDQ" instruction that specifies the address using the Q register (extension register), which is the instruction code dedicated to the main CPU 101, is used.

Therefore, even in the acquisition process of the pull-in priority table of S687, the instruction related to the address setting can be omitted on the source program by using the "LDQ" instruction. As a result, the efficiency of the acquisition process of the pull-in priority table can be improved, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced.

As described above, in the various processes during the priority attraction order acquisition process of the present embodiment, the various instruction codes dedicated to the main CPU 101 described above are appropriately used to improve the efficiency of the corresponding processes and reduce the capacity of the source program. are doing. As a result, in the present embodiment, it is possible to improve the efficiency of the program processing speed of the main control circuit 90 and reduce the capacity, and it is possible to improve the playability by utilizing the free area corresponding to the reduced capacity. It becomes.

[Reel stop control process]
Next, the reel stop control process performed in S213 in the main flow (see FIG. 82) will be described with reference to FIGS. 138 to 140. Note that FIG. 138 is a flowchart showing the procedure of the reel stop control process. FIG. 139 is a diagram showing an example of a source program for executing the processes of S711 to S716 described later during the reel stop control process, and FIG. 140 is a diagram showing the process of S726 described later during the reel stop control process. It is a figure which shows an example of the source program for this.

First, the main CPU 101 performs a reel stop enable signal OFF process (S711). In this process, the main CPU 101 mainly performs the port output process of the reel stop enable signal OFF data. Further, this process is performed using the non-standard work area of the main RAM 103. The details of the reel stop enable signal OFF process will be described later with reference to FIG. 141 described later.

Next, the main CPU 101 determines whether or not the rotation speeds of all the reels have reached a predetermined constant speed (whether or not the speed has reached a "constant speed") (S712). In S712, when the main CPU 101 determines that the rotation speeds of all reels are not "constant speed" (when the determination in S712 is NO), the main CPU 101 repeats the process of S712.

On the other hand, in S712, when the main CPU 101 determines that the rotation speeds of all the reels have reached "constant speed" (when the determination in S712 is YES), the main CPU 101 performs a reel stop enable signal ON process (S713). In this process, the main CPU 101 mainly performs the port output process of the reel stop enable signal ON data. Further, this process is performed using the non-standard work area of the main RAM 103. The details of the reel stop enable signal ON processing will be described later with reference to FIG. 142 described later.

Next, the main CPU 101 determines whether or not a valid stop button has been pressed (S714).

When the main CPU 101 determines in S714 that the valid stop button is not pressed (when the determination in S714 is NO), the main CPU 101 returns the process to the process of S713 and repeats the processes after S713. On the other hand, in S714, when the main CPU 101 determines that a valid stop button has been pressed (when the determination in S714 is YES), the main CPU 101 updates the operation stop button storage area (see FIG. 33), and the stop button is not yet pressed. The value of the operation counter is subtracted by 1 (S715).

Next, the main CPU 101 determines the search target reel from the operation stop button (S716). Further, in this process, the address (start address) set process of the reel control data storage area in which the reel control management information of the search target reel is stored is also performed (source code "LDQ IX, wR1_CTRL- (wR2_CTRL)" in FIG. 139. -WR1_CTRL) ").

Next, the main CPU 101 performs a reel stop enable signal OFF process (S717). Similar to S711, this process is performed using the non-standard work area of the main RAM 103. The details of the reel stop enable signal OFF process will be described later with reference to FIG. 141 described later. Next, the main CPU 101 stores the stop start position in the main RAM 103 based on the value of the symbol counter (S718).

Next, the main CPU 101 performs a reel stop selection process (S719). Although detailed description is omitted, in this process, the main CPU 101 performs a process of selecting the number of sliding pieces.

Next, the main CPU 101 determines a scheduled stop position based on the stop start position and the number of sliding pieces determined in S719, and stores the determined stop scheduled position in the main RAM 103 (S720). In this process, the main CPU 101 adds the number of sliding pieces to the stop start position, and sets the addition result as the stop scheduled position.

Next, the main CPU 101 executes the symbol code storage process (S721). In this process, the symbol code corresponding to the scheduled stop position is stored in the symbol code storage area. Next, the main CPU 101 determines whether or not the reel to be controlled is the reel of the final stop (third stop) (S722). In this process, the main CPU 101 determines whether or not the reel to be controlled is the reel of the final stop (third stop) based on the value of the stop button non-operation counter, and the value of the stop button non-operation counter is set. When it is "0", it is determined that the reel to be controlled is the reel at the final stop.

In S722, when the main CPU 101 determines that the reel to be controlled is not the reel of the final stop (when the determination in S722 is NO), the main CPU 101 performs the control change process (S723). In this process, the stop information group used for stopping the reel is updated when the reel is at a specific stop position. Next, the main CPU 101 performs the pull-in priority storage process described with reference to FIG. 126 (S724).

Next, the main CPU 101 performs a stop interval remaining time standby process (S725). In this process, the main CPU 101 performs a standby process until a preset predetermined reel stop interval time elapses. Then, after the processing of S725, the main CPU 101 returns the processing to the processing of S711, and repeats the processing after S711.

Here, returning to the process of S722 again, when the main CPU 101 determines in S722 that the reel to be controlled is the reel of the final stop (when the determination in S722 is YES), the main CPU 101 excites all the reels. Determines whether or not is in the stopped state (S726). In S726, when the main CPU 101 determines that the excitation of all reels is not in the stopped state (when the determination in S726 is NO), the main CPU 101 repeats the process of S726.

On the other hand, in S726, when the main CPU 101 determines that the excitation of all reels is in the stopped state (when the determination in S726 is YES), the main CPU 101 keeps the stop button operated for the third stop in the ON state. It is determined whether or not (the stop button is not released) (S727). In S727, when the main CPU 101 determines that the stop button operated by the third stop operation remains in the ON state (when the determination in S727 is YES), the main CPU 101 repeats the process of S727. On the other hand, in S727, when the main CPU 101 determines that the stop button operated by the third stop operation is not in the ON state (when the determination in S727 is NO), the main CPU 101 ends the reel stop control process and performs the process. Move to S214 of the main flow (see FIG. 82).

In the present embodiment, the reel stop control process is performed as described above. The processes S711 to S716 during the reel stop control process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 139. As shown in FIG. 139, in the source program of the reel stop control process of the present embodiment, an instruction code dedicated to the main CPU 101, for example, an "LDQ" instruction for specifying an address using a Q register (extension register) or "LDQ" instruction " The "CALLF" instruction is used.

Therefore, by using such a main CPU 101 dedicated instruction code in the reel stop control process, the capacity of the source program of the reel control process can be reduced and the processing efficiency of the reel stop control process can be improved. it can. That is, in the present embodiment, it is possible to improve the efficiency of the program processing speed and reduce the capacity of the main control circuit 90, and utilize the free area of the main ROM 102 increased according to the reduced capacity for playability. Can be increased.

Further, the determination process of S726 during the reel stop control process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 140. As shown in FIG. 140, this process is executed by using the "LDQ" instruction and the "ORQ" instruction (predetermined OR operation instruction) on the source code.

The "ORQ" instruction is an instruction code that performs a logical sum operation, and is an instruction code dedicated to the main CPU 101 that specifies an address using a Q register (extension register). Then, for example, when the source code "ORQ (k)" is executed on the source program, the stored data (upper address value) of the Q register and the 1-byte integer k (direct value: lower address value) are used. A logical sum operation is performed between the contents of the memory (stored data) at the specified address and the contents (stored data) of the A register, and the calculation result is stored in the A register.

Therefore, in the determination process of S726 during the reel stop control process, when the source code "LDQ A, (.LOW.wR1_TIM)" in FIG. 140 is first executed, the stored data of the Q register and the integer value ". The contents of the memory (excitation timer value of the first reel) at the address specified by ".LOW.wR1_TIM" are loaded into the A register. In the present embodiment, the address of the area in the main RAM 103 where the excitation timer value of the first reel is stored is "F032h". Then, in the determination process of S726 described above, the upper address value "F0h" of the address "wR1_TIM (F032h)" is set in the Q register in advance when the LDQ instruction is executed, and the lower side is set to the k value (direct value). The address value (".LOW.wR2_TIM" = 32h) is substituted.

Next, when the source code "ORQ (.LOW.wR2_TIM)" in FIG. 140 is executed, the address "wR2_TIM (wR2_TIM) of the area in which the stored data (F0h) of the Q register and the excitation timer value of the second reel are stored. The logical sum operation of the memory contents (excitation timer value of the second reel) of the address specified by the lower address value (3Dh) of "F03Dh)" and the contents of the A register (excitation timer value of the first reel) is performed. The calculation result (combined result of the excitation timer value of the first reel and the excitation timer value of the second reel) is stored in the A register. Next, when the source code "ORQ (.LOW.wR3_TIM)" in FIG. 140 is executed, the address "wR3_TIM (wR3_TIM) of the area in which the stored data (F0h) of the Q register and the excitation timer value of the third reel are stored. The contents of the memory of the address specified by the lower address value (48h) of "F048h)" (excitation timer value of the third reel) and the contents of the A register (excitation timer value of the first reel and the excitation timer of the second reel). A logical sum operation with the value (combination result with the value) is performed, and the operation result (combination result of the excitation timer values of the first to third reels) is stored in the A register.

As described above, in the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extension register) are used in the check process of the stopped state of the reel (rotary cylinder). Therefore, by using these main CPU 101 dedicated instruction codes, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values, and the instruction related to the address setting is omitted on the source program. Therefore, the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

As described above, in the various processes during the reel stop control process of the present embodiment, the various instruction codes dedicated to the main CPU 101 described above are appropriately used to improve the efficiency of the corresponding processes and reduce the capacity of the source program. ing. As a result, in the present embodiment, it is possible to improve the efficiency of the program processing speed of the main control circuit 90 and reduce the capacity, and it is possible to improve the playability by utilizing the free area corresponding to the reduced capacity. It becomes.

[Reel stoptable signal OFF processing]
Next, with reference to FIG. 141, the reel stop enable signal OFF process performed in S711 or S717 during the reel stop control process (see FIG. 138) will be described. Note that FIG. 141 is a flowchart showing the procedure of the reel stop enable signal OFF process.

First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S731). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S732).

Next, the main CPU 101 saves the data set in all the registers (S733). Next, the main CPU 101 performs a set process of the reel stop enable signal OFF data (S734).

Next, the main CPU 101 performs non-standard port output processing (S735). In this process, the main CPU 101 generates and outputs OFF output data (output off mode data), which will be described later, based on the reel stop enable signal OFF data. This process is performed using the non-standard work area of the main RAM 103. Details of the non-standard port output processing will be described later with reference to FIG. 143, which will be described later.

Next, the main CPU 101 restores the data of all the registers saved in S733 (S736). Next, the main CPU 101 sets the address of the stack area saved in S731 in the stack pointer (SP) (S737).

Then, after the processing of S737, the main CPU 101 ends the reel stop enable signal OFF processing. At this time, if the executed reel stop enable signal OFF process is the process of S711 in the reel stop control process (see FIG. 138), the main CPU 101 shifts the process to the process of S712 in the reel stop control process. On the other hand, when the executed reel stop enable signal OFF process is the process of S717 in the reel stop control process (see FIG. 138), the main CPU 101 shifts the process to the process of S718 in the reel stop control process.

[Reel stoptable signal ON processing]
Next, with reference to FIG. 142, the reel stop enable signal ON process performed in S713 during the reel stop control process (see FIG. 138) will be described. Note that FIG. 142 is a flowchart showing the procedure of the reel stop enable signal ON processing.

First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S741). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S742).

Next, the main CPU 101 saves the data set in all the registers (S743). Next, the main CPU 101 refers to the operation stop button storage area (see FIG. 33) and acquires the stop button state (S744). Next, the main CPU 101 performs a set process of the reel stop enable signal ON data (S745).

Next, the main CPU 101 performs non-standard port output processing (S746). In this process, the main CPU 101 generates and outputs ON output data (output on mode data), which will be described later, based on the reel stop enable signal ON data. This process is performed using the non-standard work area of the main RAM 103. Details of the non-standard port output processing will be described later with reference to FIG. 143, which will be described later.

Next, the main CPU 101 restores the data of all the registers saved in S743 (S747). Next, the main CPU 101 sets the address of the stack area saved in S741 in the stack pointer (SP) (S748). Then, after the processing of S748, the main CPU 101 ends the reel stop enable signal ON processing, and shifts the processing to the processing of S714 in the reel stop control processing (see FIG. 138).

[Non-standard port output processing]
Next, with reference to FIGS. 143 and 144, the non-standard port output process performed in S735 during the reel stoptable signal OFF process (see FIG. 141) and S746 during the reel stoptable signal ON process (see FIG. 142). explain. Note that FIG. 143 is a flowchart showing the procedure of the non-standard port output process. Further, FIG. 144 is a diagram showing an example of a source program for executing the non-standard port output process.

First, the main CPU 101 determines whether or not the port output setting is the ON output mode (S751). In this process, the main CPU 101 determines that the port output setting is the ON output mode when the reel stop enable signal ON data is set, and when the reel stop enable signal OFF data is set, the main CPU 101 determines. , Judge that the port output setting is not ON output mode.

In S751, when the main CPU 101 determines that the port output setting is the ON output mode (when the determination in S751 is YES), the main CPU 101 performs the process of S753 described later. On the other hand, in S751, when the main CPU 101 determines that the port output setting is not the ON output mode (when the determination in S751 is NO), the main CPU 101 performs an OFF output data (output off mode data) generation process (S752). ). In this process, among the ports (bits) that are currently in the output on state, the port (bit) that you want to turn off is turned off, and the port (bit) that is currently in the output off state is turned off. OFF output data for maintaining the state is generated.

After the processing of S752 or when the determination in S751 is NO, the main CPU 101 performs an ON output data (output on mode data) generation process (S753). In this process, among the ports (bits) that are currently in the output off state, the port (bit) that you want to turn on is turned on, and the port (bit) that is currently in the output on state is turned on. ON output data for maintaining the state is generated. Next, the main CPU 101 outputs the generated output data from the designated port (S754).

Then, after the processing of S754, the main CPU 101 ends the non-standard port output processing. At this time, if the executed non-standard port output process is the process of S735 during the reel stop enable signal OFF process (see FIG. 141), the main CPU 101 processes the process of S736 during the reel stop enable signal OFF process. Move to. On the other hand, when the executed non-standard port output process is the process of S746 during the reel stop enable signal ON process (see FIG. 142), the main CPU 101 changes the process to the process of S747 during the reel stop enable signal ON process. Move.

In the present embodiment, the non-standard port output process is performed as described above. Then, the above-mentioned non-standard port output processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 144.

Among them, in the process of generating the OFF output data of S752 during the above-mentioned non-standard port output process, the source codes "XOR (HL)" and "AND (HL)" in FIG. 144 are executed in this order. Will be done. Further, the ON output data generation process of S753 during the non-standard port output process described above is performed by executing the source code “OR (HL)” in FIG. 144.

By performing such output data generation processing on the source program, the OFF output data generated in S752 is generated even if the ON output data generation processing of S753 is performed after the OFF output data generation processing of S752. Does not change.

For example, the port output setting is the OFF output mode, and the output data indicating the non-standard port that you want to turn off in this process is "00010111" ("1" is the bit that you want to turn off), and the non-standard port is currently When the output data (backup data) output to is "0100011" ("1" is the bit currently on), the data of bit 0, bit 1 and bit 5 of the backup data is changed from "1" to "1". OFF output data for setting to "0" is generated. In this case, first, when the source code "XOR (HL)" in FIG. 144 is executed, an exclusive OR operation is performed between the output data "00010111" and the backup data "0101011", and the operation result is " 01000100 ”is obtained. Next, when the source code "AND (HL)" in FIG. 144 is executed, a logical product operation of the calculation result "010000100" and the backup data "01000111" is performed, and the calculation result "01000000" is used as OFF output data. Generated.

After that, when the ON output data generation process of S753 (source code “OR (HL)” in FIG. 144) is executed, the calculation result “01000000” (OFF output data) is turned on by this process. A logical sum operation is performed with the output data "00000000000" indicating the non-standard port to be desired (since the port output setting is the OFF output mode, "0" is set for each bit of the output data), and the calculation result is “01000000” is obtained, and the OFF output data does not change. Qualitatively, when the port output setting is the OFF output mode, in the ON output data generation process of S753, the output for keeping the port (bit) that is in the output ON state in the OFF output data in the ON state. Since the data is generated, the OFF output data generated in S752 does not change even if the ON output data generation process of S753 is performed after the OFF output data generation process of S752.

[Prize search process]
Next, the winning search process performed in S214 in the main flow (see FIG. 82) will be described with reference to FIGS. 145 to 147. Note that FIG. 145 is a flowchart showing the procedure of the winning search process. FIG. 146 is a diagram showing an example of a source program for executing the winning search process. Further, FIG. 147 is a diagram showing an example of the configuration of the payout number data table that is actually referred to on the source program of the winning search process.

First, the main CPU 101 transfers and stores the data of each storage area stored in the symbol code storage area (see FIG. 35) to the corresponding storage area of the winning operation flag storage area (see FIGS. 28 to 30). (S761). Then, at the end of this processing, the address at the end of the winning operation flag storage area is set in the DE register.

Next, the main CPU 101 sets the address of the payout number data table (the start address “dPAYNUMTB” of the payout number data table shown in FIG. 147) in the HL register (S762). Next, the main CPU 101 sets the number of payout number tables (“5” in this embodiment) as the initial value of the winning search counter, and sets the initial value in the B register (S763).

Next, the main CPU 101 sets the data of the number of medals to be paid out (in this embodiment, any one of 1, 2, 3, and 9) in the C register based on the address set in the HL register. , The determination target data is set in the A register, and "2" is added (+2 update) to the address set in the HL register (S764). In the payout number data table shown in FIG. 147, the data of the payout number of medals is "payout number (1, 2, 3 or 9) * 2 + 0", and the determination target data is next to the payout number data. It is 1-byte data (for example, "11111000B" or the like) stored in the address. Further, in the following, the data "0" in the data "number of medals to be paid out (1, 2, 3 or 9) * 2 + 0" set in the C register will be referred to as a "judgment bit". This determination bit is information indicating whether or not the block is the determination target block of the winning search.

Next, the main CPU 101 extracts the value of the determination bit from the data of the number of medals to be paid out set in the C register (S765). Next, the main CPU 101 determines whether or not the block is a determination target block based on the value of the extracted determination bit (S766). In this process, the main CPU 101 determines that the block is a determination target block when the value of the extracted determination bit is "1". In this embodiment, as shown in FIG. 147, the value of the determination bit is always "0" regardless of the number of medals to be paid out, so that the processing of S766 is always a NO determination.

In S766, when the main CPU 101 determines that the block is not the determination target block (when the determination in S766 is NO), the main CPU 101 performs the process of S768 described later. On the other hand, in S766, when the main CPU 101 determines that the block is the determination target block (when the determination in S766 is YES), the main CPU 101 subtracts 1 from the address of the winning operation flag storage area set in the DE register (-). 1 update) (S767).

After the processing of S767 or when the determination in S766 is NO, the main CPU 101 extracts the data of the storage area specified by the address of the winning operation flag storage area set in the DE register as the determination data (S768).

Next, the main CPU 101 determines whether or not the determination result is a prize based on the determination target data set in the A register in S764 and the determination data extracted in S768 (S769). In this process, if the determination target data set in the A register in S764 is the same as the determination data extracted in S768, the main CPU 101 determines that the determination result is a prize.

In S769, when the main CPU 101 determines that the result of the determination is not a prize (when the determination in S769 is NO), the main CPU 101 performs the process of S776 described later. On the other hand, in S769, when the main CPU 101 determines that the result of the determination is a winning result (when the determination in S769 is YES), the main CPU 101 has three current games (a game in which the number of medals bet is three). ) (S770).

In S770, when the main CPU 101 determines that the current game is a three-card game (when the determination in S770 is YES), the main CPU 101 performs the process of S772 described later. On the other hand, in S770, when the main CPU 101 determines that the current game is not a three-card game (when the determination in S770 is NO), the main CPU 101 pays out a two-card game (a game in which the number of medals bet is two). The number of sheets (2 sheets) is set in the C register (S771).

After the processing of S771 or when the determination in S770 is YES, the main CPU 101 updates the number of payouts (S772). Specifically, the main CPU 101 adds the number of medals to be paid out set in the C register to the current value of the winning number counter, and sets the added value to the number of payouts.

Next, the main CPU 101 determines whether or not the value of the number of payouts is less than the maximum number of payouts "10" (S773).

In S773, when the main CPU 101 determines that the value of the number of payouts is less than the maximum number of payouts "10" (when the determination in S773 is YES), the main CPU 101 performs the process of S775 described later. On the other hand, in S773, when the main CPU 101 determines that the value of the payout number is not less than the maximum payout number "10" (when the determination in S773 is NO), the main CPU 101 sets the maximum payout number "10" to the payout number. (S774).

After the processing of S774 or when the determination in S773 is YES, the main CPU 101 stores the payout number in the winning number counter (S775).

After the processing of S775 or when the determination in S769 is NO, the main CPU 101 determines whether or not there is another prize (S776). In S776, when the main CPU 101 determines that there is another prize (when the determination in S776 is YES), the main CPU 101 returns the process to the process of S769 and repeats the processes after S769.

On the other hand, in S7776, when the main CPU 101 determines that there is no other prize (when the determination in S776 is NO), the main CPU 101 subtracts 1 (updates -1) the value of the prize search counter (S777). In addition, as in the present embodiment, when there is only one effective line, since a plurality of small winning combinations are not duplicated and won a prize, the determination process of S776 is always a NO determination.

Next, the main CPU 101 determines whether or not the value of the winning search counter is "0" (S778).

In S778, when the main CPU 101 determines that the value of the winning search counter is not "0" (when the determination in S778 is NO), the main CPU 101 returns the processing to the processing of S764 and repeats the processing after S764. On the other hand, in S778, when the main CPU 101 determines that the value of the winning search counter is "0" (when the determination in S778 is YES), the main CPU 101 ends the winning search process and performs the process in the main flow (FIG. FIG. (Refer to 82), the process proceeds to S215.

In the present embodiment, the winning search process is performed as described above. Then, the above-mentioned winning search process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 146. Among them, the set processing of the number of payouts and the data to be determined in S764 is performed by the main CPU 101 executing the source code "LDIN AC, (HL)".

When, for example, the source code "LDIN ss, (HL)" is executed on the source program, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( Data) is loaded into the ss (BC, DE, AC, AE or BD) pair register, and the address set in the HL register is updated by +2 (2 additions). Therefore, when the source code "LDIN AC, (HL)" in FIG. 146 is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( The number of payouts and the data to be determined) are loaded into the AC register, and the address set in the HL register is updated by +2 (2 additions). In the process of S764, by this "LDIN" instruction, the data of the number of payouts is stored in the A register, the determination target data is stored in the C register, and the address set in the HL register is updated by +2.

As described above, in the winning search process of the present embodiment, both the data load process and the address update process can be performed by one "LDIN" command. In this case, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, the acquisition process of the value of the medal counter referred to in the determination process of S770 during the above-mentioned winning search process, the acquisition process of the value of the winning number counter referred to in the processing of S772, and the winning number counter performed in the processing of S775. As shown in FIG. 146, all the save (update) processes are executed by the "LDQ" instruction (instruction code dedicated to the main CPU 101) that specifies the address using the Q register (extension register). Therefore, in the winning search process of the present embodiment, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by the direct value by using the "LDQ" instruction. The instruction related to the setting can be omitted (it is not necessary to separately provide the instruction related to the address setting), and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, as shown in FIG. 146, the determination process of S769 during the winning search process described above is executed by the "JSLAA" instruction (predetermined determination instruction) on the source program. The "JSLAA" instruction is an instruction that executes an operation equivalent to a left shift (SLA) instruction.

For example, when the source code "JSLAA cc, e" is executed on the source program, if the condition of cc is satisfied, the process is jumped to the address specified by e. The state of the carry flag in the flag register F is specified in the "cc condition" specified by the "JSLAA" instruction. For example, if "C" is specified for cc, the condition of cc means that the carry flag is "1" (on state), and if "NC" is specified for cc, the condition of cc. Means that the carry flag is "0" (off state). Therefore, in the source code "JSLAA NC, MN_CKLN_06" in FIG. 146, if the carry flag is "0" (off state), the process jumps to the address specified by "MN_CKLN_06".

Further, as shown in FIG. 146, the determination processing of S770 and S773 during the winning search processing described above is executed by the "JCP" instruction on the source program. As described above, the "JCP" instruction is an instruction that executes an operation equivalent to a comparison instruction, and is an instruction code dedicated to the main CPU 101.

Therefore, when the above-mentioned "JSLAA" command and "JCP" command are used on the source program of the winning search process, the command related to the address setting can be omitted (it is necessary to separately provide the command related to the address setting). The capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Illegal hit check processing]
Next, the illegal hit check process performed in S215 in the main flow (see FIG. 82) will be described with reference to FIGS. 148 and 149. Note that FIG. 148 is a flowchart showing the procedure of the illegal hit check process. Further, FIG. 149 is a diagram showing an example of a source program for executing the illegal hit check process. An illegal hit is a BB winning number and a small winning combination (internal winning combination) that are drawn by the internal lottery process (see FIG. 92) and stored in the winning number storage area by the symbol setting process (see FIG. 97). Based on this, it is a term indicating that the left reel 3L, the middle reel 3C, and the right reel 3R are stopped on the effective line with a combination of symbols that cannot be established (symbol combination is not established).

First, the main CPU 101 sets the address of the winning operation flag storage area (see FIGS. 28 to 30) (S781). Next, the main CPU 101 sets the size of the winning operation flag storage area (the number of bytes, “12” in this embodiment) to the value of the check counter (S782).

Next, the main CPU 101 is based on the address of the winning operation flag storage area currently set, and the internal winning combination stored in the storage area in the hit request flag storage area (internal winning combination storage area) corresponding to the address. Data (hit request flag data) is acquired (S783). Next, the main CPU 101 synthesizes the winning combination data (winning operation flag data) stored in the address of the currently set winning operation flag storage area and the internal winning combination data (winning request flag data) ( S784).

In this synthesis process, the main CPU 101 first obtains the exclusive OR of the winning combination data (winning operation flag data) and the internal winning combination data (winning request flag data) (source program shown in FIG. 149). Source code inside "XOR (HL)"). Next, the main CPU 101 obtains the logical product of the calculated exclusive-OR calculation result and the winning combination data (winning operation flag data) (source code “AND (HL)” in the source program shown in FIG. 149. ), The calculation result of the logical product is used as the synthesis result. If no illegal hit error has occurred, the value of this synthesis result will be "0".

Next, the main CPU 101 determines whether or not an illegal hit error has occurred based on the result of the synthesis process of S784 (S785).

In S785, when the main CPU 101 determines that an illegal hit error has not occurred (NO in S785), the main CPU 101 updates the address of the winning operation flag storage area to be referred to by +1 (S786). Next, the main CPU 101 subtracts 1 from the value of the check counter (S787). Next, the main CPU 101 determines whether or not the value of the check counter is "0" (S788).

In S788, when the main CPU 101 determines that the value of the check counter is not "0" (when the determination in S788 is NO), the main CPU 101 returns the process to the process of S783 and repeats the processes after S783. On the other hand, in S788, when the main CPU 101 determines that the value of the check counter is "0" (when the determination in S788 is YES), the main CPU 101 ends the illegal hit check process and performs the process in the main flow (FIG. FIG. (Refer to 82), the process proceeds to S216.

Here, returning to the processing of S785 again, when the main CPU 101 determines in S785 that an illegal hit error has occurred (when the determination in S785 is YES), the main CPU 101 performs the error processing described with reference to FIG. (S789). By this process, the two-digit 7-segment LED (both for displaying the number of payouts and for displaying the error) included in the information display 6 is used to display the two characters "EE" indicating the occurrence of an illegal hit error as error information. Error display data is output. The state in which the illegal hit error occurs (error state) is released by pressing the reset switch 76 (see FIG. 7).

Next, the main CPU 101 clears the value of the winning number counter and the data of the hit request flag storage area (S790). Then, after the processing of S790, the main CPU 101 ends the illegal hit check processing, and shifts the processing to the processing of S216 in the main flow (see FIG. 82).

In the present embodiment, the illegal hit check process is performed as described above. Then, the above-mentioned illegal hit check process is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 149.

In this embodiment, as shown in FIGS. 28 to 30, the configuration of the winning operation flag storage area (display combination storage area) is the same as that of the hit request flag storage area (internal winning combination storage area). The winning request flag storage area and the winning operation flag storage area arranged in the main RAM 103 at the time of combining the winning combination of the winning operation flag storage area and the internal winning combination can have the same configuration. Therefore, the calculation result of S784 in the illegal hit check process of the present embodiment (the result of synthesizing the data of the winning combination and the data of the internal winning combination) is the data of the winning combination and the internal on the source program as described above. It is obtained by simply logically producting the winning combination data (executed with the "AND" instruction). As a result, in the present embodiment, the illegal hit check process can be made more efficient and simplified, the free space of the main control program can be secured (increased), and the increased free space can be used for playability. It becomes possible to increase.

[Prize check / medal payout process]
Next, the winning check / medal payout process performed in S216 in the main flow (see FIG. 82) will be described with reference to FIGS. 150 and 151. Note that FIG. 150 is a flowchart showing the procedure of winning check / medal payout processing. Further, FIG. 151 is a diagram showing an example of a source program for executing the processes of S804 to S808 described later during the winning check / medal payout process.

First, the main CPU 101 performs a winning operation command generation process (S801). In this process, the main CPU 101 generates type data and various communication parameters included in the winning operation command transmitted to the sub-control circuit 200. The winning operation command is configured to include a parameter for specifying a winning operation flag (display combination) and the like.

Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 72 (S802). By this process, the winning operation command data is stored in the communication data storage area (see FIG. 75B) provided in the main RAM 103. The winning operation command is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158.

Next, the main CPU 101 determines whether or not the value of the winning number counter is "0" (S803). In S803, when the main CPU 101 determines that the value of the winning number counter is "0" (when the determination in S803 is YES), the main CPU 101 ends the winning check / medal payout process, and performs the process in the main flow (when the winning check / medal payout process is completed). (Refer to FIG. 82), the process proceeds to S217.

On the other hand, in S803, when the main CPU 101 determines that the value of the winning number counter is not "0" (when the determination in S803 is NO), the main CPU 101 has the maximum number of medals credited (stored). In the embodiment, it is determined whether or not the number is 50 or more (S804).

In S804, when the main CPU 101 determines that the number of credits for medals is not equal to or greater than the upper limit (when the determination in S804 is NO), the main CPU 101 adds "1" to the value of the credit counter (updates +1) (upgrading +1). S805). The added value of the credit counter is displayed by a 2-digit 7-segment LED (not shown) for displaying the number of stored sheets included in the information display 6. Next, the main CPU 101 performs a medal payout number check process (S806). The details of the medal payout number check process will be described later with reference to FIG. 152 described later.

Next, the main CPU 101 determines whether or not the payout of medals has been completed (S807). In S807, when the main CPU 101 determines that the medal payout has been completed (when the determination in S807 is YES), the main CPU 101 ends the winning check / medal payout process, and the process is in the main flow (see FIG. 82). Move to the processing of S217.

On the other hand, in S807, when the main CPU 101 determines that the payout of medals has not been completed (when the determination in S807 is NO), the main CPU 101 performs a payout interval standby process (S808). In this process, the main CPU 101 waits until the preset medal payout interval time (60.33 msec in this embodiment: 54 cycles of the interrupt process (1.1172 msec cycle) described later with reference to FIG. 158) elapses. Wait. Then, after the processing of S808, the main CPU 101 returns the processing to the processing of S803, and repeats the processing after S803.

Here, returning to the process of S804 again, when the main CPU 101 determines in S804 that the number of credits for medals is equal to or greater than the upper limit (50) (when the determination in S804 is YES), the main CPU 101 determines. The medal payout process is performed (S809). By this process, one medal is paid out. Then, after the processing of S809, the main CPU 101 ends the winning check / medal payout processing, and shifts the processing to the processing of S217 in the main flow (see FIG. 82).

In the present embodiment, the winning check and the medal payout process are performed as described above. The processes S804 to S808 during the winning check / medal payout process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 151.

In the present embodiment, when the payout operation is continued after the credit counter is updated (+1), the main CPU 101 performs a wait (payout interval wait) process for 60.33 ms in the process of S808. On the source program, the main CPU 101 is realized by executing the source codes "LD BC, cTM_PAYC" and "RST SB_W1BC_00" in this order. In this way, in the winning check / medal payout process, if a wait (waiting for payout interval) of 60.33 ms is performed when the payout operation is continued after updating the credit counter (+1), useless waiting time is reduced. It is possible to reduce the mental burden on the player.

[Check process for paying out medals]
Next, with reference to FIGS. 152 and 153, the medal payout number check process performed in S806 during the winning check / medal payout process (see FIG. 150) will be described. Note that FIG. 152 is a flowchart showing the procedure of the medal payout number check process. Further, FIG. 153A is a diagram showing an example of a source program for executing the processes of S811 to S814 described later during the medal payout number check process, and FIG. 153B shows S816 and S816 described later during the medal payout number check process. It is a figure which shows an example of the source program for executing the process of S817.

First, the main CPU 101 adds (+1 update) to the value of the medal OUT counter (S811). The medal OUT counter is a counter for counting the number of times the medal is paid out. Next, the main CPU 101 adds (+1 update) to the value of the payout number counter (S812). The payout number counter is a counter for counting the payout number of medals.

Next, the main CPU 101 performs a payout number 7SEG display process (S813). In this process, the main CPU 101 performs a control process of displaying the value of the payout number counter by a 2-digit 7-segment LED (not shown) for displaying the payout number included in the information display 6.

Next, the main CPU 101 performs an update process of the winning combination end number counter (S814). The winning combination end number counter is a counter for counting the remaining number of medals to be paid out corresponding to the winning combination. In this process, the main CPU 101 compares the value of the combination end number counter with the lower limit value “0”, and if the value of the combination end number counter is larger than the lower limit value “0”, the combination end number counter. The value of the counter is subtracted by 1 (updated by -1), and when the value of the winning combination end number counter is equal to or less than the lower limit value "0", the value of the winning combination ending number counter is held at "0".

Next, the main CPU 101 subtracts 1 (updates -1) the value of the winning number counter (S815).

Next, the main CPU 101 performs a credit information command generation process (S816). In this process, the main CPU 101 generates type data and various communication parameters included in the credit information command transmitted to the sub-control circuit 200. The credit information command is configured to include a parameter for specifying the number of credits for medals.

Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 72 (S817). By this process, the credit information command data is stored in the communication data storage area (see FIG. 75B) provided in the main RAM 103. The credit information command is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. 158. Then, after the processing of S817, the main CPU 101 ends the medal payout number check process, and shifts the process to the process of S807 during the winning check / medal payout process (see FIG. 150).

In the present embodiment, the medal payout number check process is performed as described above. The processes of S811 to S814 during the above-mentioned medal payout number check process are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 153A. Among them, the update process of the winning combination end number counter in S814 is executed by the "DCPLD" instruction (predetermined update instruction) in FIG. 153A. The "DCPLD" instruction is an instruction code dedicated to the main CPU 101.

When, for example, the source code "DCPLD (HL), n" is executed on the source program, the memory contents (stored data) of the address specified by the HL register are compared with the integer n, and the memory contents are changed. If it is larger than the integer n, the contents of the memory are subtracted by 1, and if the contents of the memory are not more than the integer n, the integer n is stored in the memory at the address specified by the HL register. Therefore, when the source code "DCPLD (HL), 0" in FIG. 153A is executed, the contents of the memory at the address specified by the HL register (value of the winning combination end number counter) and an integer 0 (lower limit value). If the memory content (value of the winning combination end number counter) is greater than an integer 0, the memory content is subtracted by 1, and if the memory content is an integer 0 or less, the memory content is subtracted. "0" is set in (value of the number counter for the end of the winning combination). That is, if the value of the current combination end number counter is larger than "0", the combination end number counter is updated, and if the current combination end number counter value is "0" or less. , The process of holding the value of the winning combination end number counter at "0" is performed.

As described above, in the process of S814 during the medal payout number check process, one "DCPLD" command (a command in which the lower limit judgment command of the number management counter and the judgment branch command are integrated) is used to complete the number of consecutive combinations. Both the counter update (subtraction) process and the process of holding the value of the continuous end number counter at "0" can be executed. In this case, it is not necessary to provide an instruction code for executing both processes separately. For example, the determination branch instruction code for determining whether or not the value of the continuous end number counter is "0" can be omitted. Therefore, in the medal payout number check process of the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, and the free space can be secured (increased) in the main ROM 102, resulting in an increase. It is possible to improve the playability by utilizing the free space.

Further, the processes of S816 and S817 during the above-mentioned medal payout number check process are performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 153B.

Among them, in the processing of S816, as shown in FIG. 153B, the value of the payout counter is set in the communication parameter 1 of the credit information command via the L register, and the credit is set in the communication parameter 5 via the C register. The value of the counter is set. However, the other communication parameters 2 to 4 constituting the credit information command are set with values (indefinite values) currently stored in the H register, the E register, and the D register, respectively. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[BB check process]
Next, the BB check process performed in S217 in the main flow (see FIG. 82) will be described with reference to FIG. 154. Note that FIG. 154 is a flowchart showing the procedure of the BB check process.

First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S821). In S821, when the main CPU 101 determines that the current gaming state is not the bonus state (when the determination in S821 is NO), the main CPU 101 performs the process of S832 described later.

On the other hand, in S821, when the main CPU 101 determines that the current gaming state is the bonus state (when the determination in S821 is YES), the main CPU 101 is for counting the number of medals that can be paid out during the bonus state. The number of medals paid out in the winning check / medal payout process is subtracted from the value of the BB payout number counter (S822).

Next, the main CPU 101 determines whether or not the value of the BB payout number counter is less than "0" (S823). In S823, when the main CPU 101 determines that the value of the payout number counter in BB is not less than "0" (when the determination in S823 is NO), the main CPU 101 ends the BB check process and performs the process in the main flow (FIG. (Refer to 82), the process proceeds to S218.

On the other hand, in S823, when the main CPU 101 determines that the value of the payout number counter in BB is less than "0" (when the determination in S823 is YES), the main CPU 101 performs the bonus end processing (S824). In this process, the main CPU 101 clears various information in the bonus state and sets the RT1 state flag to the on state.

Next, the main CPU 101 refers to the CT lottery table at the end of the bonus (see FIG. 60) and performs the CT lottery at the end of the bonus (S825). Next, the main CPU 101 determines whether or not the CT lottery at the end of the bonus has been won (S826).

In S826, when the main CPU 101 determines that the CT lottery has not been won (when the determination in S826 is NO), the main CPU 101 performs the process of S828 described later. On the other hand, in S826, when the main CPU 101 determines that the CT lottery has been won (when the determination in S826 is YES), the main CPU 101 adds "1" to the number of CT sets (S827). If the CT lottery is won when the number of ART sets is "0", "1" is added to the number of CT sets and "1" is also added to the number of ART sets in the processing of S827. ..

After the processing of S827 or when the determination in S826 is NO, the main CPU 101 determines whether or not the number of ART sets or the number of CT sets is "1" or more (S828).

In S828, when the main CPU 101 determines that the number of ART sets or the number of CT sets is "1" or more (when the determination in S828 is YES), the main CPU 101 sets the ART preparation state in the game state of the next game. (S829). Then, after the processing of S829, the main CPU 101 ends the BB check processing and shifts the processing to the processing of S218 in the main flow (see FIG. 82).

On the other hand, in S828, when the main CPU 101 determines that the number of ART sets or the number of CT sets is not "1" or more (when the determination in S828 is NO), the main CPU 101 sets the normal game state to the game state of the next game. (S830). Next, the main CPU 101 draws the lottery state of CZ with reference to the normal medium-high probability lottery table (see FIG. 40B), and sets the lottery result (S831). Then, after the processing of S831, the main CPU 101 ends the BB check processing, and shifts the processing to the processing of S218 in the main flow (see FIG. 82).

Here, returning to the process of S821 again, when the determination in S821 is NO, the main CPU 101 determines whether or not the symbol combination related to the BB combination (the symbol combination of the combination "C_BB1" or "C_BB2") is displayed. (S832). In S832, when the main CPU 101 determines that the symbol combination related to the BB combination is not displayed (when the determination in S832 is NO), the main CPU 101 ends the BB check process and performs the process in the main flow (see FIG. 82). Move on to the processing of S218 inside.

On the other hand, in S832, when the main CPU 101 determines that the symbol combination related to the BB combination is displayed (when the determination in S832 is YES), the main CPU 101 refers to the bonus type lottery table (see FIG. 58) and gives a bonus. The type is drawn and the lottery result is set (S833). Next, the main CPU 101 sets a predetermined value (the number of payouts that triggers the end of the bonus: "216" in the present embodiment) to the value of the payout number counter during BB (S834).

Next, the main CPU 101 performs a bonus start processing (S835). In this process, the main CPU 101 performs various processes necessary for starting the operation of the bonus, such as setting a bonus state in the game state of the next game. Then, after the processing of S835, the main CPU 101 ends the BB check processing and shifts the processing to the processing of S218 in the main flow (see FIG. 82).

[RT check processing]
Next, the RT check process performed in S218 in the main flow (see FIG. 82) will be described with reference to FIGS. 155 and 156. Note that FIGS. 155 and 156 are flowcharts showing the procedure of RT check processing.

First, the main CPU 101 determines whether or not the RT state is the RT5 state (S841). In S841, when the main CPU 101 determines that the RT state is the RT5 state (when the determination in S841 is YES), the main CPU 101 ends the RT check process and performs the process in S219 in the main flow (see FIG. 82). Move to the processing of.

On the other hand, in S841, when the main CPU 101 determines that the RT state is not the RT5 state (when the determination in S841 is NO), the main CPU 101 determines whether or not the RT state is the RT0 state (S842). In S842, when the main CPU 101 determines that the RT state is not the RT0 state (when the determination in S842 is NO), the main CPU 101 performs the process of S845 described later.

On the other hand, in S842, when the main CPU 101 determines that the RT state is the RT0 state (when the determination in S842 is YES), the main CPU 101 displays the symbol combination of the abbreviation "bell spilled eyes" (see FIG. 28). It is determined whether or not it is (S843). In S843, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" is not displayed (when the determination in S843 is NO), the main CPU 101 ends the RT check process and performs the process in the main flow (FIG. (Refer to 82), the process proceeds to S219.

On the other hand, in S843, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" is displayed (when the determination in S843 is YES), the main CPU 101 sets the RT2 state flag to the ON state (S844). .. By this process, the RT state shifts from the RT0 state to the RT2 state. Then, after the processing of S844, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

Here, returning to the process of S842 again, when the determination in S842 is NO, the main CPU 101 determines whether or not the RT state is the RT1 state (S845). In S845, when the main CPU 101 determines that the RT state is not the RT1 state (when the determination in S845 is NO), the main CPU 101 performs the process of S850 described later.

On the other hand, in S845, when the main CPU 101 determines that the RT state is the RT1 state (when the determination in S845 is YES), the main CPU 101 determines whether or not the symbol combination of the abbreviation "bell spilled eye" is displayed. (S846).

In S846, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eye" is displayed (when the determination in S846 is YES), the main CPU 101 sets the RT1 state flag to the off state and sets the RT2 state flag. Is set to the on state (S847). By this process, the RT state shifts from the RT1 state to the RT2 state. Then, after the processing of S847, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

On the other hand, in S846, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" is not displayed (when the determination in S846 is NO), the main CPU 101 determines whether or not 20 games have passed in the RT1 state. (S848).

In S848, when the main CPU 101 determines that 20 games in the RT1 state have not elapsed (NO in S848), the main CPU 101 ends the RT check process and performs the process in the main flow (see FIG. 82). ) Moves to the processing of S219. On the other hand, in S848, when the main CPU 101 determines that 20 games have passed in the RT1 state (when the determination in S848 is YES), the main CPU 101 sets the RT1 state flag to the off state (S849). By this process, the RT state shifts from the RT1 state to the RT0 state. Then, after the processing of S849, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

Here, returning to the process of S845 again, when S845 is a NO determination, the main CPU 101 determines whether or not the RT state is the RT2 state (S850). In S850, when the main CPU 101 determines that the RT state is not the RT2 state (when the determination in S850 is NO), the main CPU 101 performs the process of S853 described later.

On the other hand, in S850, when the main CPU 101 determines that the RT state is the RT2 state (when the determination in S850 is YES), the main CPU 101 displays the symbol combination (see FIG. 28) of the abbreviation "RT3 transition lip". It is determined whether or not it is present (S851). In S851, when the main CPU 101 determines that the symbol combination of the abbreviation "RT3 transition lip" is not displayed (when the determination in S851 is NO), the main CPU 101 ends the RT check process and performs the process in the main flow (FIG. (Refer to 82), the process proceeds to S219.

On the other hand, in S851, when the main CPU 101 determines that the symbol combination of the abbreviation "RT3 transition lip" is displayed (when the determination in S851 is YES), the main CPU 101 sets the RT2 state flag to the off state and RT3. The state flag is set to the on state (S852). By this process, the RT state shifts from the RT2 state to the RT3 state. Then, after the processing of S852, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

Here, returning to the process of S850 again, when the determination in S850 is NO, the main CPU 101 determines whether or not the RT state is the RT3 state (S853). In S853, when the main CPU 101 determines that the RT state is not the RT3 state (when the determination in S853 is NO), the main CPU 101 performs the process of S862 described later.

On the other hand, in S853, when the main CPU 101 determines that the RT state is the RT3 state (when the determination in S853 is YES), the main CPU 101 displays the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip". It is determined whether or not it has been done (S854).

In S854, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is displayed (when the determination in S854 is YES), the main CPU 101 sets the RT3 state flag to the off state. At the same time, the RT2 state flag is set to the on state (S855). By this process, the RT state shifts from the RT3 state to the RT2 state. Then, after the processing of S855, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

On the other hand, in S854, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is not displayed (when the determination in S854 is NO), the main CPU 101 has the abbreviation "RT4 transition". It is determined whether or not the symbol combination (see FIG. 28) of "Rip" is displayed (S856).

In S856, when the main CPU 101 determines that the symbol combination of the abbreviation "RT4 transition lip" is not displayed (when the determination in S856 is NO), the main CPU 101 ends the RT check process and performs the process in the main flow (when it is determined as NO). (Refer to FIG. 82), the process proceeds to S219. On the other hand, in S856, when the main CPU 101 determines that the symbol combination of the abbreviation "RT4 transition lip" is displayed (when the determination in S856 is YES), the main CPU 101 sets the RT3 state flag to the off state and RT4. The state flag is set to the on state (S857). By this process, the RT state shifts from the RT3 state to the RT4 state.

After the process of S857, the main CPU 101 determines whether or not the game state is the ART preparation state (S858). In S858, when the main CPU 101 determines that the gaming state is not the ART ready state (when the determination in S858 is NO), the main CPU 101 ends the RT check process and performs the process in the main flow (see FIG. 82) S219. Move to the processing of.

On the other hand, in S858, when the main CPU 101 determines that the gaming state is the ART preparation state (when the determination in S858 is YES), the main CPU 101 determines whether or not the number of CT sets is "1" or more. (S859).

In S859, when the main CPU 101 determines that the number of CT sets is "1" or more (when the determination in S859 is YES), the main CPU 101 sets CT in the game state of the next game and sets the CT game number counter. Set "8" (S860). Then, after the processing of S860, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

On the other hand, in S859, when the main CPU 101 determines that the number of CT sets is not "1" or more (when the determination in S859 is NO), the main CPU 101 sets the normal ART in the game state of the next game, and the ART end game. A predetermined value is set in the number counter (S861). Then, after the processing of S861, the main CPU 101 ends the RT check processing and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

Here, returning to the process of S853 again, when the determination in S853 is NO, the main CPU 101 determines whether or not the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is displayed (S862). In S862, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is not displayed (when the determination in S862 is NO), the main CPU 101 ends the RT check process. , The process is transferred to the process of S219 in the main flow (see FIG. 82).

On the other hand, in S862, when the main CPU 101 determines that the symbol combination of the abbreviation "bell spilled eyes" or "RT2 transition lip" is displayed (when the determination in S862 is YES), the main CPU 101 turns off the RT4 state flag. At the same time, the RT2 state flag is set to the on state (S863). By this process, the RT state shifts from the RT4 state to the RT2 state. Then, after the processing of S863, the main CPU 101 ends the RT check processing, and shifts the processing to the processing of S219 in the main flow (see FIG. 82).

[Processing at the end of CZ / ART]
Next, with reference to FIG. 157, the processing at the end of CZ / ART performed in S219 in the main flow (see FIG. 82) will be described. Note that FIG. 157 is a flowchart showing a procedure for processing at the end of CZ / ART.

First, the main CPU 101 determines whether or not the current gaming state is at the time of CZ failure or at the end of ART (S871). In S871, when the main CPU 101 determines that the current gaming state is neither at the time of CZ failure nor at the end of ART (when the determination of S871 is NO), the main CPU 101 ends the processing at the end of CZ / ART. The process is transferred to the process of S201 in the main flow (see FIG. 82).

On the other hand, in S871, when the main CPU 101 determines that the current gaming state is either when the CZ fails or when the ART ends (when the determination in S871 is YES), the main CPU 101 uses the CZ lottery table (see FIG. 41B). ), The pullback lottery of CZ is performed (S872). Next, the main CPU 101 determines whether or not the CZ pullback lottery has been won (S873).

In S873, when the main CPU 101 determines that the CZ pullback lottery has been won (when the determination in S873 is YES), the main CPU 101 sets the winning type CZ in the game state of the next game (S874). Next, the main CPU 101 sets a value corresponding to the winning type of CZ in the CZ game number counter (S875). Then, after the processing of S875, the main CPU 101 ends the processing at the end of CZ / ART, and shifts the processing to the processing of S201 in the main flow (see FIG. 82).

On the other hand, in S873, when the main CPU 101 determines that the CZ pullback lottery has not been won (when the determination in S873 is NO), the main CPU 101 sets the normal game state to the game state of the next game (S876). Next, the main CPU 101 draws the lottery state of CZ with reference to the normal medium-high probability lottery table (see FIG. 40B), and sets the lottery result (S877). Then, after the processing of S877, the main CPU 101 ends the processing at the end of CZ / ART, and shifts the processing to the processing of S201 in the main flow (see FIG. 82).

[Interrupt processing controlled by the main CPU (1.1172 msec)]
Next, with reference to FIG. 158, the interrupt process performed by the main CPU 101 at a cycle of 1.1172 msec will be described. Note that FIG. 158 is a flowchart showing the procedure of the interrupt process. The interrupt process repeatedly executed at a cycle of 1.1172 msec is generated based on the output timing of the timeout signal of the timer circuit 113 set in the initialization process of the timer circuit 113 (PTC) (see S2 in FIG. 64). This is a process executed when the interrupt request signal from the interrupt controller 112 is input to the main CPU 101.

First, the main CPU 101 performs a register save process (S901). Next, the main CPU 101 performs an input port check process (S902). In this process, signals input from various switches such as a stop switch are checked.

Next, the main CPU 101 performs a reel control process (S903). In this process, the main CPU 101 starts rotating the left reel 3L, the middle reel 3C, and the right reel 3R when all the reels are requested to start rotating, and then each reel rotates at a constant speed. Drive and control three stepping motors. When the number of sliding pieces is determined, the main CPU 101 updates the symbol counter of the corresponding reel by the number of sliding pieces. Then, the main CPU 101 waits for the updated symbol counter to match the value corresponding to the scheduled stop position (the symbol at the scheduled stop position reaches the area on the effective line of the display window) of the corresponding reel. The corresponding stepping motor is driven and controlled so that the rotation is decelerated and stopped.

Next, the main CPU 101 performs a communication data transmission process (S904). In this process, various commands stored in the communication data storage area are mainly transmitted to the sub-control circuit 200 via the first serial communication circuit 114 (see FIG. 9) of the main control circuit 90. After transmitting a command to the sub-control circuit 200, the main CPU 101 subtracts and updates the communication data pointer by one packet (not shown), and clears the transmitted command data in the communication data storage area. When a plurality of command data are stored in the communication data storage area, the command data is transmitted to the sub-control circuit 200 in the order of the oldest stored command data. Further, when the command data is not stored in the communication data storage area, that is, when the value of the communication data pointer is "0", a non-operation command is generated and transmitted to the sub-control circuit 200. Next, the main CPU 101 performs a insertion medal passage check process (S905). In this process, the main CPU 101 checks whether or not the inserted medal has passed the selector 66 based on the detection result (medal sensor input state) of the medal sensor (not shown). Next, the main CPU 101 performs the WDT restart process (S906).

Next, the main CPU 101 performs a 7-segment LED drive process (S907). In this process, the main CPU 101 drives and controls various 7-segment LEDs included in the information display 6, and displays, for example, the number of medals paid out, the number of credits, the stop button pressing order data, and the like. The details of the 7-segment LED drive process will be described later with reference to FIG. 159, which will be described later.

Next, the main CPU 101 performs a timer update process (S908). In this process, the main CPU 101 performs a count (subtraction) process of various set timers. The details of the timer update process will be described later with reference to FIG. 164 described later.

Next, the main CPU 101 performs an error detection process (S909). Next, the main CPU 101 performs a door open / close check process (S910). In the door open / close check process, the main CPU 101 checks the open / closed state of the front door 2b (see FIG. 2) by checking the on (door closed) / off (door open) state of the door open / close monitoring switch 67.

Next, the main CPU 101 performs a test firing test signal control process (S911). In this process, control process is performed when various test signals are output to the testing machine via the second interface boat or the like. Further, this process is executed using the non-standard work area (see FIG. 12C) of the main RAM 103. In the present embodiment, this process is also performed at a time other than the test firing test (after the pachislot machine 1 is installed in the game store), but at this time, the main control board 71 passes through the second interface boat or the like. Since it is not connected to the testing machine, various test signals are generated but not output. The details of the test firing test signal control process will be described later with reference to FIG. 166 described later.

Next, the main CPU 101 performs a register reset process (S912). Then, after the processing of S912, the main CPU 101 ends the interrupt processing.

[7-segment LED drive processing]
Next, the 7-segment LED drive process performed in S907 during the interrupt process (see FIG. 158) will be described with reference to FIGS. 159 and 160. Note that FIG. 159 is a flowchart showing the procedure of the 7-segment LED drive process. Further, FIG. 160A is a diagram showing an example of a source program for executing the processes of S923 to S925 described later during the 7-segment LED drive process, and FIG. 160B is a diagram showing S931 to be described later during the 7-segment LED drive process. It is a figure which shows an example of the source program for executing the process of S936.

First, the main CPU 101 adds (+1 update) to the value of the interrupt counter (S921). Next, the main CPU 101 determines whether or not the value of the interrupt counter is an odd number (S922).

In S922, when the main CPU 101 determines that the value of the interrupt counter is not an odd number (when the determination in S922 is NO), the main CPU 101 ends the 7-segment LED drive process and interrupts the process (see FIG. 158). ) Moves to the processing of S908. That is, in the present embodiment, the 7-segment LED drive process is performed every two interruption cycles. In the present embodiment, an example of executing the 7-segment LED drive process when the value of the interrupt counter is even has been described, but the present invention is not limited to this, and the 7-segment LED drive process is not limited to this when the value of the interrupt counter is odd. The LED drive process may be executed, or the execution timing of the 7-segment LED drive process may be determined by using the quotient or the remainder when the value of the interrupt counter is divided by an arbitrary integer.

On the other hand, in S922, when the main CPU 101 determines that the value of the interrupt counter is an odd number (when the determination in S922 is YES), the main CPU 101 acquires navigation data from the navigation data storage area (S923). Next, the main CPU 101 sets the address of the push order display data storage area for storing the push order display data output to each cathode of the 7-segment LED (S924).

Next, the main CPU 101 performs a 7-segment display data generation process (S925). In this process, the main CPU 101 creates push order display data (7-segment display data) based on the navigation data, and stores the generated push order display data in the push order display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 161 described later.

Next, the main CPU 101 acquires the value of the credit counter (S926). Next, the main CPU 101 sets the address of the credit display data storage area for storing the credit display data output to each cathode of the 7-segment LED (S927).

Next, the main CPU 101 performs a 7-segment display data generation process (S928). In this process, the main CPU 101 generates credit display data (7-segment display data) based on the value of the credit counter, and stores the generated credit display data in the credit display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 161 described later.

Next, the main CPU 101 sets the address of the 7-segment common counter storage area for storing the value of the 7-segment common counter described later (S929). Next, the main CPU 101 adds (+1 update) to the value of the 7-segment common counter (S930). In this process, when the updated 7-segment common counter value becomes "8", the main CPU 101 sets the 7-segment common counter value to "0". In the present embodiment, since the 7-segment LED is dynamically controlled, the value of the 7-segment common counter is updated every 8 times.

Next, the main CPU 101 creates common selection data based on the value of the 7-segment common counter, and addresses the target cathode data storage area (push order display data storage area or target storage area in the credit display data storage area). Is set (S931). Next, the main CPU 101 outputs clear data to the cathode of the 7-segment LED (S932). This process is performed in order to eliminate the influence of the afterimage by temporarily turning off the 7-segment LED.

Next, the main CPU 101 acquires and sets 7-segment cathode output data from the target cathode data storage area (S933). Next, the main CPU 101 generates 7-segment common output data from the 7-segment common backup data and the common selection data (S934).

Next, the main CPU 101 stores the 7-segment common output data and the 7-segment cathode output data in the 7-segment common backup data and the 7-segment cathode backup data, respectively (S935). Next, the main CPU 101 outputs 7-segment cathode output data and 7-segment common output data (S936). Then, after the processing of S936, the main CPU 101 ends the 7-segment LED drive processing, and shifts the processing to the processing of S908 in the interrupt processing (see FIG. 158).

In this embodiment, the 7-segment LED drive process is performed as described above. The processing of S923 to S925 during the above-mentioned 7-segment LED drive processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 160A. Further, the processes of S931 to S936 during the above-mentioned 7-segment LED drive process are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 160B.

Among them, the output processing of each 7-segment output data of S936 is executed by one source code "LD (cPA_SEGCOM), BC" as shown in FIG. 160B. Therefore, in the 7-segment LED drive process of the present embodiment, the 7-segment common output (selection) data and the 7-segment cathode output data are output at the same time when the 2-digit 7-segment LED is dynamically lit and controlled. That is, in the dynamic lighting control of the 7-segment LED when performing push order navigation on the instruction monitor, and the 7-segment common output (7-segment common output) in the dynamic lighting control of the 7-segment LED when displaying credit information with the 2-digit 7-segment LED. (Selection) data and 7-segment cathode output data are output at the same time.

In this case, the number of instruction codes required for the dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, it becomes possible to improve the playability. Further, in the present embodiment, an example in which a 7-segment drive circuit (not shown) that performs a 7-segment LED drive process is configured by a cathode common circuit and controlled by the cathode has been described, but the present invention is not limited to this, and 7 The seg drive circuit may be composed of an anode common circuit, and the 7-segment LED may be controlled by the anode.

Further, as shown in FIG. 160A, the Q register (extension register) is used for both the acquisition process of the navigation data of S923 and the address set process of the push display data storage area of S924 during the 7-segment LED drive process described above. It is executed by the "LDQ" instruction (instruction code dedicated to the main CPU 101) that specifies the address. Therefore, in the 7-segment LED drive process of the present embodiment, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by the direct value by using the "LDQ" instruction, so that the source program can be used. , The instruction related to the address setting can be omitted (it is not necessary to separately provide the instruction related to the address setting), and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[7-segment display data generation process]
Next, the 7-segment display data generation process performed in S925 and S928 in the 7-segment LED drive process (see FIG. 159) will be described with reference to FIGS. 161 to 163. Note that FIG. 161 is a flowchart showing the procedure of the 7-segment display data generation process. FIG. 162 is a diagram showing an example of a source program for executing the 7-segment display data generation process. Further, FIG. 163 is a diagram showing an example of the configuration of the 7-segment cathode table that is actually referred to on the source program of the 7-segment display data generation process.

The "display data" described later generated by the 7-segment display data generation process performed in S925 during the 7-segment LED drive process (see FIG. 159) corresponds to the push-order display data, and the 7-segment LED drive process (FIG. 159). The "display data" described later generated in the 7-segment display data generation process performed in S928 in (see 159) corresponds to the credit display data.

First, the main CPU 101 divides the display data set in the cathode data storage area by "10", acquires the quotient value of the division result as the display data of the upper digit of the 2-digit 7-segment LED, and divides the data. The remaining value of the result is acquired as the display data of the lower digit (S941). Next, the main CPU 101 determines whether or not to display the upper digit based on the acquired display data of the upper digit (S942).

In S942, when the main CPU 101 determines that the upper digit display is to be performed (when the determination in S942 is YES), the main CPU 101 performs the process of S944 described later. On the other hand, in S942, when the main CPU 101 determines that the upper digit is not displayed (when the determination in S942 is NO), the main CPU 101 sets no display of the upper digit (S943).

After the processing of S943 or when the determination in S942 is YES, the main CPU 101 refers to the 7-segment cathode table (see FIG. 163) and acquires the display data of the upper digit (S944). Next, the main CPU 101 saves the acquired high-order digit display data in the high-order digit display data storage area (not shown) (S945).

Next, the main CPU 101 refers to the 7-segment cathode table (see FIG. 163) and acquires the display data of the lower digits (S946). Next, the main CPU 101 saves the acquired low-order digit display data in the low-order digit display data storage area (not shown) (S947).

Then, after the processing of S947, the main CPU 101 ends the 7-segment display data generation processing. At this time, if the executed 7-segment display data generation process is the process of S925 during the 7-segment LED drive process (see FIG. 158), the main CPU 101 changes the process to the process of S926 during the 7-segment LED drive process. Move. On the other hand, when the executed 7-segment display data generation process is the process of S928 in the 7-segment LED drive process (see FIG. 158), the main CPU 101 shifts the process to the process of S929 in the 7-segment LED drive process. ..

In the present embodiment, the 7-segment display data generation process is performed as described above. The 7-segment display data generation process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 162.

[Timer update process]
Next, the timer update process performed in S908 during the interrupt process (see FIG. 158) will be described with reference to FIGS. 164 and 165. Note that FIG. 164 is a flowchart showing the procedure of the timer update process. Further, FIG. 165 is a diagram showing an example of a source program for executing the processes of S951 to S954 described later during the timer update process.

First, the main CPU 101 sets the update start address of the 2-byte timer storage area (not shown) in the HL register, and sets the number of 2-byte timers in the B register (S951).

Next, the main CPU 101 compares the number of 2-byte timers with the lower limit value "0", and if the number of 2-byte timers is larger than the lower limit value "0", subtracts 1 from the number of 2-byte timers (updates -1). When the number of 2-byte timers is equal to or less than the lower limit value "0", the number of 2-byte timers is held at "0" (S952). Further, in the process of S952, the main CPU 101 subtracts 2 (-2 updates) the update start address of the 2-byte timer storage area set in the HL register.

Next, the main CPU 101 subtracts (updates -1) the number of 2-byte timers set in the B register by 1 (S953). Next, the main CPU 101 determines whether or not the number of 2-byte timers set in the B register is "0" (S954).

In S954, when the main CPU 101 determines that the number of 2-byte timers set in the B register is not "0" (when the determination in S954 is NO), the main CPU 101 returns the processing to the processing of S952, and after S952. Repeat the process.

On the other hand, in S954, when the main CPU 101 determines that the number of 2-byte timers set in the B register is "0" (when the determination in S954 is YES), the main CPU 101 stores the 1-byte timer in the HL register. The update start address of is set, and the number of 1-byte timers is set in the B register (S955).

Next, the main CPU 101 compares the number of 1-byte timers with the lower limit value "0", and if the number of 1-byte timers is larger than the lower limit value "0", the number of 1-byte timers is subtracted by 1 (-1 update). However, when the number of 1-byte timers is equal to or less than the lower limit value "0", the number of 1-byte timers is held at "0" (S956). Further, in the process of S956, the main CPU 101 subtracts 1 (-1 update) the update start address of the 1-byte timer storage area set in the HL register.

Next, the main CPU 101 subtracts (updates -1) the number of 1-byte timers set in the B register by 1 (S957). Next, the main CPU 101 determines whether or not the number of 1-byte timers set in the B register is "0" (S958).

In S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is not "0" (when the determination in S958 is NO), the main CPU 101 returns the processing to the processing of S956, and after S956. Repeat the process.

On the other hand, in S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is "0" (when the determination in S958 is YES), the main CPU 101 performs an electromagnetic counter control process (S959). ). In this process, an output control process is performed when a signal indicating IN / OUT of the medal is output to the external centralized terminal plate 47. Then, after the processing of S959, the main CPU 101 ends the timer update processing, and shifts the processing to the processing of S909 in the interrupt processing (see FIG. 158).

In the present embodiment, the timer update process is performed as described above. The processes S951 to S954 (two-byte timer update process) during the timer update process described above are performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 165.

Among them, the process of S952 (update process of the 2-byte timer) is executed by the "DCPWLD" instruction (predetermined update instruction) in FIG. 165. The "DCPWLD" instruction is an instruction code dedicated to the main CPU 101.

When, for example, the source code "DCPWLD (HL), n" is executed on the source program, the contents (stored data) of the memory for 2 bytes from the address specified in the HL register are compared with the integer n. If the contents of the memory for 2 bytes are larger than the integer n, the contents of the memory for 2 bytes are subtracted by 1, and if the contents of the memory for 2 bytes are less than or equal to the integer n, it is specified by the HL register. The integer n is stored in the memory for 2 bytes from the address.

Therefore, in the source code "DCPWLD (HL), 0" in FIG. 165, the contents of the memory for 2 bytes (the number of 2-byte timers) and the integer "0" (lower limit value) from the address specified by the HL register are used. When the contents of the memory for 2 bytes are larger than the integer "0", the contents of the memory for 2 bytes are subtracted by 1, and the contents of the memory for 2 bytes are equal to or less than the integer "0". Is set to "0" in the contents of the memory for 2 bytes. That is, if the current number of 2-byte timers is larger than "0", the 2-byte timer update process is performed, and if the current number of 2-byte timers is "0" or less, the number of 2-byte timers is "0". Is held in.

As described above, in the timer update process of the present embodiment, both the process of updating (subtracting) the number of timers and the process of holding the number of timers at "0" are executed by the "DCPWLD" instruction which is the instruction code dedicated to the main CPU 101. can do. In this case, it is not necessary to provide an instruction code for executing both processes separately. Further, the determination branch instruction code for determining whether or not the number of timers is "0" can be omitted. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, it becomes possible to improve the playability. In the present embodiment, an example in which the "DCPWLD" instruction is used only in the update process of the 2-byte timer has been described, but the present invention is not limited to this, and the "DCWPLD" instruction is also used in the update process of the 1-byte timer. You may use it.

[Test firing test signal control processing (non-standard)]
Next, with reference to FIG. 166, the test firing test signal control process performed in S911 during the interrupt process (see FIG. 158) will be described. Note that FIG. 166 is a flowchart showing the procedure of the test firing test signal control process.

First, the main CPU 101 saves the address of the stack area of the main RAM 103 (S961). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S962). Next, the main CPU 101 saves the data of all the registers (S963).

Next, the main CPU 101 performs a rotating cylinder braking signal generation process (S964). In this process, the main CPU 101 generates and outputs a rotation control signal (drive signal) for each reel, which is output to the testing machine via the second interface boat or the like. The details of the rotating cylinder braking signal generation process will be described later with reference to FIG. 167, which will be described later.

Next, the main CPU 101 performs a special prize signal control process (S965). In this process, the main CPU 101 performs an output process of a bonus (special prize) ON / OFF signal (test signal) output to the testing machine. The details of the prize signal control process will be described later with reference to FIG. 168 described later.

Next, the main CPU 101 performs the condition device signal control process (S966). In this process, the main CPU 101 performs a control signal output process corresponding to the state of the condition device signal control flag. The details of the condition device signal control process will be described later with reference to FIGS. 169 and 170 described later.

Next, the main CPU 101 performs a restoration process of the data of all the registers saved in the process of S963 (S967). Next, the main CPU 101 sets the address of the stack area saved in the process of S961 in the stack pointer (SP) (S968). Then, after the processing of S968, the main CPU 101 ends the test firing test signal control processing, and shifts the processing to the processing of S912 in the interrupt processing (see FIG. 158).

[Rotating cylinder braking signal generation processing]
Next, with reference to FIG. 167, the rotating cylinder braking signal generation process performed in S964 during the test firing test signal control process (see FIG. 166) will be described. Note that FIG. 167 is a flowchart showing the procedure of the rotating cylinder braking signal generation processing.

First, the main CPU 101 sets a rotation cylinder control data storage area (not shown) in the non-standard work area (S971). Next, the main CPU 101 sets the number of reels to "3" and clears the rotation cylinder control signal and its generation state (1 byte data) (S972).

Next, the main CPU 101 determines whether or not the rotation control data is “less than stopped” data (S973). The "less than stopped" rotation control data here is rotation control data other than the rotation control data for stopping the reel, that is, rotation control data for rotationally driving the reel (acceleration). It is one of the states of preparation, acceleration, constant speed waiting, constant speed, and waiting for the stop start position).

In S973, when the main CPU 101 determines that the rotation control data is "less than stopped" data (when the determination in S973 is YES), the main CPU 101 performs the process of S975 described later. On the other hand, in S973, when the main CPU 101 determines that the rotation control data is not "less than stopped" data (when the determination in S973 is NO), the main CPU 101 determines that the rotation control data is "statically indeterminate hold control end". It is determined whether or not the data is (S974). The rotating cylinder control data of "statically indeterminate hold control end" referred to here is rotation cylinder control data indicating a state in which all phases and all phases of the reel are stopped.

In S974, when the main CPU 101 determines that the rotation control data is "statically indeterminate hold control end" data (when the determination in S974 is YES), the main CPU 101 performs the process of S976 described later. On the other hand, in S974, when the main CPU 101 determines that the rotation control data is not "statically indeterminate hold control end" data (when S974 is a NO determination), or when S973 is a YES determination, the main CPU 101 determines. Bit 3 of the rotation control signal generation state (1 byte data) is turned on (“1”) (S975).

After the processing of S975 or when the determination in S974 is NO, the main CPU 101 shifts the data of each bit in the generated state by one bit to the right (in the direction from bit 7 to bit 0) (S976). Next, the main CPU 101 updates the address of the rotating cylinder control data storage area to the address of the next reel to be controlled (S977).

Next, the main CPU 101 subtracts 1 from the number of reels (S978). Next, the main CPU 101 determines whether or not the number of reels is "0" (S979).

In S979, when the main CPU 101 determines that the number of reels is not "0" (when the determination in S979 is NO), the main CPU 101 returns the processing to the processing of S973 and repeats the processing after S973.

On the other hand, in S979, when the main CPU 101 determines that the number of reels is "0" (when the determination in S979 is YES), the main CPU 101 outputs the data in the generated state via the rotating cylinder braking signal output port. Output to the first interface board 301 (see FIG. 7) for use (S980). Then, after the processing of S980, the main CPU 101 ends the rotation cylinder braking signal generation processing, and shifts the processing to the processing of S965 in the test firing test signal control processing (see FIG. 166).

[Special prize signal control processing]
Next, with reference to FIG. 168, the special prize signal control process performed in S965 during the test firing test signal control process (see FIG. 166) will be described. Note that FIG. 168 is a flowchart showing the procedure of the special prize signal control process.

First, the main CPU 101 acquires the game state flag by referring to the game state flag storage area (see FIG. 32) (S991). Next, the main CPU 101 determines whether or not the gaming state is the RB gaming state (S992).

In S992, when the main CPU 101 determines that the gaming state is the RB gaming state (when the determination in S992 is YES), the main CPU 101 sends an ON signal from the RB medium signal port for the test signal to the first interface for the test machine. Output to board 301 (see FIG. 7) (S993). On the other hand, in S992, when the main CPU 101 determines that the gaming state is not the RB gaming state (when the determination in S992 is NO), the main CPU 101 sends an OFF signal from the RB medium signal port for the test signal to the first test machine. Output to the interface board 301 (see FIG. 7) (S994).

After the processing of S993 or S994, the main CPU 101 refers to the game state flag storage area (see FIG. 32) and determines whether or not the game state is the BB game state (S995).

In S995, when the main CPU 101 determines that the gaming state is the BB gaming state (when the determination in S995 is YES), the main CPU 101 sends an ON signal from the BB medium signal port for the test signal to the first interface for the test machine. Output to board 301 (see FIG. 7) (S996). On the other hand, in S995, when the main CPU 101 determines that the gaming state is not the BB gaming state (when the determination in S995 is NO), the main CPU 101 sends an OFF signal from the BB medium signal port for the test signal to the first test machine. Output to the interface board 301 (see FIG. 7) (S997).

Then, after the processing of S996 or S997, the main CPU 101 ends the special prize signal control processing, and shifts the processing to the processing of S966 in the test firing test signal control processing (see FIG. 166).

[Condition device signal control processing]
Next, the condition device signal control process performed in S966 during the test firing test signal control process (see FIG. 166) will be described with reference to FIGS. 169 and 170. Note that FIGS. 169 and 170 are flowcharts showing the procedure of the condition device signal control process.

First, the main CPU 101 determines whether or not the condition device signal control flag is in the initial state (S1001). In S1001, when the main CPU 101 determines that the condition device signal control flag is in the initial state (when the determination in S1001 is YES), the main CPU 101 ends the condition device signal control process and performs the test firing test signal control process. (See FIG. 166) The process proceeds to S967.

On the other hand, in S1001, when the main CPU 101 determines that the condition device signal control flag is not in the initial state (when the determination in S1001 is NO), the main CPU 101 sets the condition device signal control flag to the ON state of the replay state identification signal. It is determined whether or not it is indicated (S1002).

In S1002, when the main CPU 101 determines that the condition device signal control flag indicates the ON state of the replay state identification signal (when the determination in S1002 is YES), the main CPU 101 serves the condition device signal control state. The ON state of the physical condition device signal is set (S1003). Next, the main CPU 101 outputs the RT state information from the condition devices 1 to 6 signal ports to the first interface board 301 for the testing machine (see FIG. 7) (S1004). Then, after the processing of S1004, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 166).

On the other hand, in S1002, when the main CPU 101 determines that the condition device signal control flag does not indicate the ON state of the replay state identification signal (when the determination in S1002 is NO), the condition device signal control flag is set in the main CPU 101. It is determined whether or not the re-game state identification signal indicates an off state (S1005).

In S1005, when the main CPU 101 determines that the condition device signal control flag indicates the off state of the replay state identification signal (when the determination in S1005 is YES), the main CPU 101 uses the condition devices 1 to 8 signal ports. Outputs the OFF signal from the first interface board 301 for the testing machine (see FIG. 7) (S1006). Then, after the processing of S1006, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 166).

On the other hand, in S1005, when the main CPU 101 determines that the condition device signal control flag does not indicate the off state of the replay state identification signal (when the determination in S1005 is NO), the main CPU 101 has the condition device signal control state. It is determined whether or not the accessory condition device signal is on (S1007).

In S1007, when the main CPU 101 determines that the condition device signal control state is the ON state of the accessory condition device signal (when the determination in S1007 is YES), the main CPU 101 wins a special prize from the condition devices 1 to 8 signal ports. The number information is output to the first interface board 301 for the testing machine (see FIG. 7), and at this time, the ON signal is output from the condition device 8 signal port to the first interface board 301 for the testing machine (see FIG. 7) (see FIG. 7). S1008). Next, the main CPU 101 sets a predetermined waiting time (24.58 ms in this embodiment) in the condition device signal output waiting timer (S1009). Next, the main CPU 101 sets the condition device signal control state to the state of waiting for the condition device signal output (S1010). Then, after the processing of S1010, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 166).

On the other hand, in S1007, when the main CPU 101 determines that the condition device signal control state is not the ON state of the accessory condition device signal (when the determination in S1007 is NO), the main CPU 101 has the condition device signal control state as the condition device signal. It is determined whether or not the output is waiting (S1011).

In S1011, when the main CPU 101 determines that the condition device signal control state is the state of waiting for the condition device signal output (when the determination of YES in S1011), the value of the condition device signal output wait timer of the main CPU 101 is "0". It is determined whether or not it is (S1012).

In S1012, when the main CPU 101 determines that the value of the condition device signal output waiting timer is not "0" (when the determination in S1012 is NO), the main CPU 101 ends the condition device signal control process and tests the process. The process shifts to the processing of S967 in the signal control processing (see FIG. 166). On the other hand, in S1012, when the main CPU 101 determines that the value of the condition device signal output waiting timer is "0" (when the determination in S1012 is YES), the main CPU 101 is in the condition device signal control state. The on state of the signal or the off state of the condition device signal is set (S1013). Then, after the processing of S1013, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 166).

Here, returning to the processing of S1011 again, when the main CPU 101 determines in S1011 that the condition device signal control state is not the state of waiting for the condition device signal output (when the determination in S1011 is NO), the main CPU 101 determines the condition. It is determined whether or not the device signal control state is the on state of the small combination condition device signal (S1014).

In S1014, when the main CPU 101 determines that the condition device signal control state is the on state of the small combination condition device signal (when the determination in S1014 is YES), the main CPU 101 has a small combination from the condition devices 1 to 8 signal ports. The winning number information is output to the first interface board 301 for the testing machine (see FIG. 7), and at this time, the ON signal is output from the condition device 7 signal port to the first interface board 301 for the testing machine (see FIG. 7). (S1015). Next, a predetermined waiting time (24.58 ms in this embodiment) is set in the condition device signal output waiting timer (S1016). Next, the main CPU 101 sets the condition device signal control state to the state of waiting for the condition device signal output (S1017). Then, after the processing of S1017, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 166).

On the other hand, in S1014, when the main CPU 101 determines that the condition device signal control state is not the ON state of the small winning combination condition device signal (when the determination in S1014 is NO), the main CPU 101 is turned off from the condition devices 1 to 8 signal ports. The signal is output to the first interface board 301 for the testing machine (see FIG. 7) (S1018). Then, after the processing of S1018, the main CPU 101 ends the condition device signal control processing, and shifts the processing to the processing of S967 in the test firing test signal control processing (see FIG. 166).

<Explanation of operation of sub-control circuit>
Next, with reference to FIGS. 171 to 173, the contents of various processes executed by the sub CPU 201 of the sub control circuit 200 by using the program will be described.

[Sub-side navigation control processing]
First, the sub-side navigation control process will be described with reference to FIG. 171. Note that FIG. 171 is a flowchart showing the procedure of the sub-side navigation control process.

First, the sub CPU 201 determines whether or not the navigation data has been acquired (S1101). The sub CPU 201 acquires the navigation data determined by the main control board 71 from the start command data received from the main control board 71. Therefore, in the process of S1101, the sub CPU 201 determines whether or not the received start command data includes the navigation data.

When the sub CPU 201 determines in S1101 that the navigation data has been acquired (when the determination in S1101 is YES), the sub CPU 201 sets the sub-side navigation data according to the navigation data (S1102). For example, when the sub CPU 201 acquires the navigation data "4", as shown in FIG. 63, the navigation data for notifying the push order "left, middle, right" is set as the sub side navigation data in this process. To. As a result, the content of the stop operation can be notified on both the main side and the sub side. Then, after the processing of S1102, the sub CPU 201 ends the sub-side navigation control processing.

On the other hand, in S1101, when the sub CPU 201 determines that the navigation data has not been acquired (when the determination in S1101 is NO), the sub CPU 201 determines whether or not navigation (notification of stop operation) is necessary. (S1103). In the present embodiment, the sub CPU 201 needs to be navigated, for example, when a flag conversion lottery is performed on the main control board 71 or when a predetermined combination is determined as an internal winning combination on the main control board 71. Is determined. The result of the flag conversion lottery and the type of the internal winning combination are included in the start command data. Therefore, in the process of S1103, the sub CPU 201 determines whether or not navigation is necessary based on these various pieces of information included in the start command data.

When the sub CPU 201 determines in S1103 that navigation is not necessary (NO in S1103), the sub CPU 201 ends the sub-side navigation control process.

On the other hand, in S1103, when the sub CPU 201 determines that navigation is necessary (when the determination in S1103 is YES), the sub CPU 201 sets the sub-side navigation data according to various lottery results (S1104). For example, when the internal winning combination "F_certain chili lip" is determined and the flag conversion lottery is won, the sub CPU 201 is a navigation system for displaying the symbol combination related to the abbreviation "triple chili lip" in this process. Set the data (for example, navigation data that aims at the Chilean pattern by pushing forward). Further, for example, when the internal winning combination "F_certain chili lip" is determined and the flag conversion lottery is not winning, the sub CPU 201 is for displaying the symbol combination related to the abbreviation "replay" in this process. Set navigation data (for example, navigation data indicating a push order other than forward push). By these processes, even if the main side does not notify the content of the stop operation, the sub side alone can notify the content of the stop operation. Then, after the processing of S1104, the sub CPU 201 ends the sub-side navigation control processing.

[Player registration process]
Next, the player registration process will be described with reference to FIG. 172. Note that FIG. 172 is a flowchart showing the procedure of the player registration process.

First, the sub CPU 201 determines whether or not the registration operation has been accepted (S1111). For example, when the operation of the registration button 222b is accepted on the menu screen 222 (see FIG. 5B) of the sub display device 18, and the predetermined operation is accepted on the registration screen (not shown) displayed in that case, the sub CPU 201 performs the registration operation. Is determined to have been accepted.

When the sub CPU 201 determines in S1111 that the registration operation has been accepted (when the determination in S1111 is YES), the sub CPU 201 sets the player registration state (S1112). In the situation where the player registration state is set, the sub CPU 201 can display the game information screens 223, 224, 225 (see FIGS. 5C to 5E) on the sub display device 18. Control the display screen. Then, after the process of S1112, the sub CPU 201 ends the player registration process.

On the other hand, when it is determined in S1111 that the sub CPU 201 has not accepted the registration operation (when the determination in S1111 is NO), the sub CPU 201 determines whether or not the registration deletion operation has been accepted (S1113). For example, when a specific operation is accepted on the registration screen of the sub display device 18, the sub CPU 201 determines that the registration deletion operation has been accepted.

When the sub CPU 201 determines in S1113 that the registration deletion operation is not accepted (when the determination in S1113 is NO), the sub CPU 201 ends the player registration process.

On the other hand, in S1113, when it is determined that the sub CPU 201 has accepted the registration deletion operation (when the determination in S1113 is YES), the sub CPU 201 clears the player registration state (S1114). In the situation where the player registration state is cleared, the sub CPU 201 makes it impossible to display the game information screens 223, 224, 225 (see FIGS. 5C to 5E) on the sub display device 18. Control the display screen of. Then, after the process of S1114, the sub CPU 201 ends the player registration process.

[History management process]
Next, the history management process will be described with reference to FIG. 173. Note that FIG. 173 is a flowchart showing the procedure of the history management process.

First, the sub CPU 201 acquires the game result from various command data received from the main control board 71 (S1121). For example, in this process, the sub CPU 201 can grasp the type of the winning combination determined as the internal winning combination from the start command data. Further, for example, in this process, the sub CPU 201 can grasp the symbol combination displayed from the winning operation command data (that is, the presence or absence of winning of the winning combination determined as the internal winning combination). Further, for example, in this process, the sub CPU 201 can grasp the current gaming state and the transition status of the gaming state from the start command data and the like.

Next, the sub CPU 201 performs a game history update process based on the acquired game result (S1122). By this process, the sub CPU 201 is based on the game results acquired from various command data, for example, the number of bonuses, the number of ARTs, the number of games (number of games), the number of CZs, the number of CZ successes, the number of winnings of each combination and the winnings. It is possible to manage various game histories such as probabilities. Then, after the process of S1122, the sub CPU 201 ends the history management process.

<Various effects>
In the pachislot machine 1 of the present embodiment, the following various effects can be obtained in terms of playability.

[Management of duration during CT]
In the pachislot machine 1 of the present embodiment, a CT is provided as an additional chance zone in which the duration of the normal ART can be extended, and the number of ART games is added based on the internal winning combination (sub-flag) in the CT. In CT, eight games are played in one set, but if the number of ART games can be added during CT, the number of games is not subtracted, and the number of games is increased only when the number of games cannot be added. Subtract. Therefore, the player does not know how long the CT will last, and the CT will not end as long as the addition is performed, so that the interest of the game during the CT can be enhanced.

Further, in the present embodiment, when the sub-flag EX "triple chili lip" is won (winned in the sub-flag conversion lottery) and added during CT, the CT game 8 times per set is also reset (stock). Will be done. In this case, for example, even if the CT game period is just before the end, when the sub-flag EX "triple chili lip" is won, the addition is performed and the CT is restarted from the beginning. You will have a strong interest in it, and you will be able to continue the game without getting bored, and you will be able to enhance the interest of the game during CT.

In addition, the addition of the sub-flag EX "triple chili lip" at the time of winning is performed only when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined as the internal winning combination and the flag conversion lottery is won. .. Therefore, it is possible to prevent giving an excessive profit to the player, and it is possible to balance the profit between the player and the game store. In the above embodiment, an example (see FIG. 54) in which the flag conversion lottery is always won when the internal winning combination “F_certain chili lip” or “F_1 certain chili lip” is determined during CT has been described. The present invention is not limited to this, and the winning probability of the flag conversion lottery can be appropriately set according to the balance of profits between the player and the game store.

[Number of additional games at the time of winning the "triple chili lip" during CT]
In the pachislot machine 1 of the above embodiment, when the sub-flag "triple chili lip" is won during CT and the number of additions based on the sub-flag "triple chili lip" exceeds a predetermined number of times, one additional lottery is performed. The number of additional games for winning ART will increase (see FIG. 55). Further, as described above, as long as the number of ART games is added, the CT does not end, and when the sub-flag EX "triple chili lip" is won, the CT is reset. Therefore, from the player's point of view, it is possible to expect that the additional amount per one time (one game) will increase as the CT continues, and the interest during the CT will improve. Furthermore, since the number of times (9 times or more) that triggers the increase in the amount of addition per game (1 game) is larger than the basic number of games (8 times) for one set of CT, the player is asked. It is possible to prevent excessive profits from being given, and to balance (keep good) the profits between the player and the game store.

[Bonus notification performed on the main side]
In the pachi-slot machine 1 of the above embodiment, the numerical value "10" is uniquely associated with the information of the stop operation for displaying the symbol combination related to the bonus combination (BB combination) on the instruction monitor (not shown) of the information display 6. "(Or" 11 ") is displayed to notify the bonus on the main side (see FIG. 63). However, in pachislot, the priority of the symbol to be drawn (stopped and displayed) on the effective line is usually set, and when the bonus combination and other combinations are determined as the internal winning combination, the priority is set. Depending on the situation, the combination of symbols related to the bonus combination may or may not be drawn.

For example, in the pachislot machine 1 of the present embodiment, the bonus combination and any one of the internal winning combination "missing", "F_special role 1", "F_special role 2", and "F_special role 3" are determined in duplicate. If so, the symbol combination related to the bonus combination can be drawn in, but the bonus combination and the internal winning combination "off", "F_special role 1", "F_special role 2" and "F_special role 3" If a combination other than the winning combination is determined in duplicate, the symbol combination related to the bonus combination cannot be drawn in. Therefore, in the present embodiment, the bonus combination and any one of the internal winning combination "missing", "F_special role 1", "F_special role 2", and "F_special role 3" are determined in duplicate. Only in this case, the numerical value "10" (or "11") is displayed on the instruction monitor. In this case, the navigation (bonus notification) on the main side can be performed at an appropriate timing in which the bonus combination can be won.

Further, in the pachislot machine 1 of the present embodiment, the bonus combination and any one of the internal winning combination "missing", "F_special role 1", "F_special role 2" and "F_special role 3" are determined in duplicate. Even so, the numerical value "10" (or "11") is not displayed (without navigation) on the instruction monitor until the predetermined number of games have passed since the bonus combination was first won, and the predetermined number of games have been played. The numerical value "10" (or "11") is displayed on the instruction monitor on condition that the game has passed.

In addition, for example, when an effect (so-called continuous effect) performed over a plurality of games is performed with the winning of the bonus role as an opportunity, the numerical value "10" (or "or" 10 ") is displayed on the instruction monitor during this continuous effect. If 11 ") is displayed, the meaning of the continuous production is diminished, and there is a possibility that the interest is spoiled. Therefore, in the pachi-slot machine 1 of the present embodiment, the display is not performed by the instruction monitor until the predetermined number of games have elapsed, and the display is performed by the instruction monitor after the predetermined number of games have elapsed. As a result, the bonus notification on the main side can be performed without impairing the effect of the effect.

[Notification performed on both the main side and sub side and notification performed on the sub side alone]
In the pachi-slot machine 1 of the present embodiment, a plurality of types of combinations having different symbol combinations displayed according to the mode (pushing order) of the stop operation are provided (see FIG. 24), and the symbols to be displayed are provided for these plurality of types of combinations. A combination in which different benefits are given depending on the combination and a combination in which the same privilege is given even if the displayed symbol combinations are different are included.

For example, the number of medals to be paid out differs depending on whether the symbol combination related to the abbreviation "bell" is displayed or the symbol combination related to the abbreviation "bell spilled eye" is displayed, and these combinations are displayed symbols. It is a role in which different benefits are given depending on the combination. In addition, whether or not the RT state is transferred in addition to the operation of the replay between the case where the symbol combination related to the abbreviation "Replay" is displayed and the case where the symbol combination related to the abbreviation "RT2 transition lip" is displayed. Therefore, the internal winning combinations "F_3 selection bell_1st" and "F_maintenance lip_1st" are also roles in which different benefits are given depending on the displayed symbol combination.

On the other hand, in both the case where the symbol combination related to the abbreviation "triple chili lip" is displayed and the case where the symbol combination related to the abbreviation "replay" is displayed, the replay operation is only performed. Therefore, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is a role in which the same privilege is given even if the displayed symbol combinations are different. As described above, the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" has different benefits depending on the result of the flag conversion lottery, but the benefits given by the displayed symbol combination. It is not a role that affects.

In the pachislot machine 1 of the present embodiment, the winning combination to which different benefits are given depending on the displayed symbol combination is notified on both the main side and the sub side, but the same even if the displayed symbol combinations are different. The combination to which the privilege is given is not notified by the instruction monitor on the main side, but is notified only by the display device 11 on the sub side. By providing such a notification function, notifications that affect the benefits are appropriately performed by the instruction monitor on the main side that manages the benefits, while notifications that do not affect the benefits are diverse on the display device 11 on the sub side. It can be done with the navigation.

[Game history display function]
In the pachi-slot machine 1 of the present embodiment, a sub-display device 18 is provided separately from the display device 11 (projector mechanism 211 and display unit 212), and the sub-display device 18 displays various information useful to the player. For example, as shown in FIGS. 5A to 5E, a top screen 221 showing the outline game history, a menu screen 222 capable of performing various operations on the pachislot machine 1, and a game information screen 223, 224, 225 showing the detailed game history are sub-display devices. It can be displayed at 18.

Further, the pachi-slot machine 1 of the present embodiment has a function of enabling registration of a player who plays a game via a sub-display device 18, and a function of providing a unique service to the registered player. For example, in the present embodiment, when the registration of the player is not accepted, the game information screens 223, 224, and 225 showing the detailed game history cannot be displayed on the sub display device 18, but the registration of the player is performed. When accepting, the game information screens 223, 224, and 225 showing the detailed game history can be displayed on the sub display device 18. Since making it possible to confirm a more detailed game history leads to an improvement in the convenience of the player, in the present embodiment, the convenience can be improved when the registration of the player is accepted.

Further, in the pachi-slot machine 1 of the present embodiment, the sub-display device 18 is provided separately from the display device 11 that performs the effect. The sub display device 18 is controlled by the sub control board 72 (sub CPU 201) via the liquid crystal relay board 87. Further, the display unit 212 constituting the display device 11 is controlled by the sub control board 72 (sub CPU 201) via the accessory relay board (not shown). Therefore, in the present embodiment, the sub-display device 18 can be controlled separately from the display device 11. Specifically, the display screen of the sub-display device 18 can be switched even during the game (that is, during the execution of the effect by the display device 11). Therefore, even during the game, the player can acquire various information by switching the display of the sub-display device 18 without disturbing the effect executed by the display device 11.

Further, in the display device 11 of the pachi-slot machine 1 of the present embodiment, a flat image display is used by switching a plurality of screen mechanisms (display unit 212) for displaying an image by irradiating the irradiation light from the projector mechanism 211. When performing an effect, an effect using an image display with a sense of depth (three-dimensional effect), and an effect using a curved image display, the effect can be significantly enhanced. However, such a display form of information is not suitable for displaying information unrelated to the production such as a game history during the production. Therefore, in the pachi-slot machine 1 of the present embodiment, information unrelated to the effect can be displayed on the sub-display device 18 provided separately from the display device 11, so that the effect of the effect is not impaired and the game is played. Various information such as history can be displayed appropriately.

By the way, in a general pachislot machine, a medal insertion slot 14 is provided on the right side of the pedestal portion 13 when viewed from the player side, and bet buttons 15a and 15b and a start lever 16 are provided on the left side of the pedestal portion 13. Therefore, normally, when advancing the game, the player operates the operation unit on the right side or the left side (side) of the pedestal portion 13.

On the other hand, in the pachi-slot machine 1 of the present embodiment, the sub-display device 18 is provided on the side (left side) of the surface that stands substantially vertically from the pedestal portion 13, and the sub-display device 18 is provided on the screen of the sub-display device 18. A touch sensor 19 for switching the display screen of is provided. Therefore, in the present embodiment, the sub-display device 18 and the input device (touch sensor 19) for controlling the display are provided at the place where the player's hand is located during the game, so that the player's operability Can be improved. In particular, when the sub display device 18 with the touch sensor 19 is provided on the surface of the pedestal portion 13 that stands upright from the horizontal plane as in the present embodiment, the player puts his / her hand on the pedestal portion 13. However, the sub display device 18 can be operated. In this case, not only the operability of the player is improved, but also the fatigue of the player due to the operation can be reduced, and as a result, the operating rate can be expected to be improved.

[Non-standard ROM area and non-standard RAM area]
In the pachi-slot machine 1 of the present embodiment, as shown in FIG. 12B, various programs and various types used for various processes (various processes that do not affect the playability) that are not directly related to the playability of the game performed by the player. The data (table) is stored in the main ROM 102 in a non-standard ROM area arranged at an address different from the game ROM area.

In such a configuration of the main ROM 102, programs and data unnecessary for the game itself actually played by the player are arranged in a ROM area (non-standard ROM area) where programs and the like cannot be arranged under the conventional rules. can do. Therefore, in the present embodiment, it is possible to avoid pressure on the capacity of the game ROM area in the main ROM 102 of the main control board 71, and to enhance the expandability of the program and the table in the main ROM 102.

[Effects obtained by processing when the power is turned on (reset interrupt)]
In the power-on (reset interrupt) processing of the pachi-slot machine 1 of the present embodiment, as shown in FIG. 64, the first 1.1172 ms cycle interrupt processing is performed immediately after the power is restored (before the thumb check) (S7 and S8). ), A non-operation command is transmitted from the main control circuit 90 to the sub control circuit 200. By permitting the interrupt process immediately after the power is restored in this way, the no-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

Further, the communication parameters 1 to 5 constituting the non-operation command transmitted immediately after the power is restored are set with the data stored in the L register, the H register, the E register, the D register, and the C register, respectively, when the power is restored. Will be done. Therefore, in the present embodiment, the sum value (BCC) of the non-operation command transmitted in the interrupt process immediately after the power is restored can be made different every time the power is restored, and fraudulent acts such as goto can be suppressed. it can.

Further, the control for displaying the error code "rr" on the 2-digit 7-segment LED in the information display 6 performed in the processing of S13 during the power-on (reset interrupt) processing is one "LDW". It is executed by an instruction (predetermined read instruction), and the output operation of the 7-segment common output (selection) data to the 2-digit 7-segment LED and the output operation of the 7-segment cathode output data are performed at the same time (see FIG. 65C). That is, in the pachi-slot machine 1 of the present embodiment, when the 2-digit 7-segment LED is dynamically lit and controlled in the power-on (reset interrupt) processing, the 7-segment common output (selection) data and the 7-segment cathode output data are displayed. It is output at the same time.

In this case, the number of instruction codes required for the dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, the playability can be enhanced.

[Effects obtained by game return processing]
In the game return processing of the pachislot machine 1 of the present embodiment, as shown in FIG. 66, the input / output state of each port at the time of power failure is secured at the time of power recovery, and when the reel is rotating at the time of power failure, When the power is restored, the reel control management information is acquired and the processing necessary for starting the reel rotation is also performed (see S25 to S32). Therefore, in the present embodiment, it is possible to stably control the re-rotation of the reel even when the reel is recovered from the electric power failure during the rotation of the reel, and the player is not discomforted.

Further, as described above, the pachi-slot machine 1 of the present embodiment includes a microprocessor 91 with a security function for a game machine. The microprocessor 91 is provided with various instruction codes (instruction codes dedicated to the main CPU 101) specific to the microprocessor 91 that can be specified on the source program, and the instruction codes dedicated to the main CPU 101 are used in various processes. This makes it possible to improve processing efficiency and reduce program capacity.

For example, in the game return process, as shown in FIG. 67, the "LDQ" instruction, which is one of the instruction codes dedicated to the main CPU 101, is used on the source program. The "LDQ" instruction is an instruction code that specifies an address using a Q register (extension register), and as described above, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed with direct values. In this case, the instruction code related to the address setting can be omitted, and the capacity of the source program for the game return processing (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by setting change confirmation processing]
In the setting change confirmation process of the pachi-slot machine 1 of the present embodiment, as shown in FIG. 69A, the "BITQ" instruction and the "SETQ" instruction (predetermined instruction), which are instruction codes dedicated to the main CPU 101, are used on the source program. .. Both the "BITQ" instruction and the "SETQ" instruction are instruction codes for specifying an address using a Q register (extension register), and when these instruction codes are used, as described above, the main RAM 103 is a direct value. And memory map I / O can be accessed. In this case, the instruction code related to the address setting can be omitted, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space of the main ROM 102 can be increased, and the processing speed can be increased.

Further, the generation and storage processing of the setting change command (initialization command) performed at the time of setting change / setting confirmation start of S46 and at the end of setting change / setting confirmation of S57 during the setting change confirmation processing is as shown in FIGS. 69A and 69B. In addition, it is executed by the "CALLF" command, which is a command code dedicated to the main CPU 101, on the source program. The jump destination address specified by the "CALLF" instruction in S46 is the same as the jump destination address specified by the "CALLF" instruction in S57. That is, in the present embodiment, the setting change command (initialization command) to be transmitted to the sub-control circuit 200 at the time of setting change (when the game machine is started), at the start of setting confirmation (during normal operation), and at the end of setting confirmation is generated and stored. The source programs for executing the above are the same as each other, and the source programs are shared (modularized) in both the processes of S46 and S57.

In this case, in both the processes of S46 and S57, it is not necessary to separately provide the source program for the generation and storage process of the setting change command, so that the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. it can. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by setting change command generation and storage processing]
In the setting change command generation and storage process of the pachislot machine 1 of the present embodiment, as shown in FIG. 70, the set value is stored in the E register as the communication parameter 3, and the RT information is stored in the C register as the communication parameter 5. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), the communication parameters 3 and 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side, and these are used. New information is set in the communication parameters. On the other hand, the other communication parameters 1, 2 and 4 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side, and are communication parameters 1, 2 and 4. For and 4, the values currently stored in the L register, H register, and D register are set. Therefore, the values of the communication parameters 1, 2 and 4 at the time of transmitting the setting change command (initialization command) are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[Effects obtained by communication data storage processing]
In the communication data storage process of the pachislot 1 of the present embodiment, as shown in FIG. 72, the data stored in the A register is set as the type data of the communication command, and the L register, the H register, the E register, the D register and the C register are set. The data stored in the registers are set as communication parameters 1 to 5 of the communication command, respectively, and the data stored in the B register is set as the game state flag data of the communication command. That is, in the present embodiment, when creating one packet (8 bytes) of communication data (command data), various parameters are transferred from the register and stored in the communication data temporary storage area (communication buffer).

In this case, when command data including unused parameters is created, the value of the unused parameters becomes an indefinite value each time it is created. That is, in the command data including unused parameters, even if there is command data of the same type and the values of the used parameters are the same, the sum value (BCC data) of the command data can be changed for each command creation. .. Therefore, in the present embodiment, by setting the unused parameter to an indefinite value, it is possible to make it difficult to analyze the communication data and suppress fraudulent acts such as goto, and it is necessary to add unnecessary goto countermeasure processing. Therefore, it is possible to suppress the pressure on the program capacity of the main control circuit 90 due to the addition of the anti-goto processing.

[Effects obtained by updating the communication data pointer]
In the communication data pointer update process of the pachislot machine 1 of the present embodiment, as shown in FIG. 75A, the "ICPLD" instruction, which is an instruction code dedicated to the main CPU 101, is used on the source program.

In the communication data pointer update process, the "ICPLD" instruction is an instruction code in which the upper limit determination instruction of the transmission buffer and the determination branch instruction are integrated. There is no need to provide it. Therefore, by using the "ICPLD" instruction, the capacity of the source program for the communication data pointer update process (the capacity used by the main ROM 102) can be reduced. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by checksum generation process and checksum check process]
In the checksum generation process (non-standard) performed at the time of power failure in the pachi-slot machine 1 of the present embodiment, the checksum is calculated by sequentially adding the data of the main RAM 103 as shown in FIG. 77. On the other hand, in the thumb check process (non-standard) performed when the power is turned on (when the power is restored), the value of the checksum generated when the power is cut off is stored in the main RAM 103 when the power is restored, as shown in FIG. 79. The data is sequentially subtracted, and the presence or absence of an abnormality is determined based on whether or not the final subtraction result is "0". That is, in the present embodiment, the checksum generation process when a power failure occurs is performed by an addition method, and the checksum determination process when the power is restored is performed by a subtractive method.

When such a checksum generation process and determination process are adopted, it is not necessary to generate a checksum again when the power is restored and to collate the checksum with the checksum when a power failure occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, in the main ROM 102, it is possible to secure (increase) the free space corresponding to the omission of the collation instruction code, and it is possible to utilize the increased free space to improve the playability. Become.

[Effects obtained by medal reception / start check processing]
In the medal acceptance / start check process of the pachislot machine 1 of the present embodiment, as shown in FIG. 83, the setting change confirmation process (process of S233) is performed, and this process is executed regardless of the gaming state. Therefore, in the present embodiment, even if the game state is a bonus state (special prize operating state), the set value and the hall menu (various history data (error, power failure history, etc.)) can be confirmed, and the game can be checked. It is possible to suppress fraudulent activities.

[Effects obtained by inserting medals]
In the medal insertion process of the pachislot machine 1 of the present embodiment, as shown in FIG. 85, in the process of S244, the LED lighting data for displaying the number of inserted medals is generated by arithmetic processing instead of loop processing with reference to the table. .. Specifically, a series of source codes "LD A, L" to "OR L" in the source program shown in FIG. 86 are sequentially executed to generate LED lighting data for displaying the number of inserted medals.

When the LED lighting data for displaying the number of inserted medals is generated by arithmetic processing, the free space of the table area of the main ROM 102 can be increased, and the increase in the capacity of the program can be minimized. That is, in the medal insertion process of the present embodiment, the process of displaying the medal insertion LED can be made more efficient, the free space of the main ROM 102 is secured (increased), and the increased free area is utilized to improve the playability. Can be enhanced.

[Effects obtained by medal insertion check processing]
In the medal insertion check process (see FIG. 87) of the pachi-slot machine 1 of the present embodiment, the process of generating the normal change value of the medal sensor input state of S257 is performed by an arithmetic process, not a process of acquiring by referring to the table. Specifically, the medal sensor input state normal change value is calculated by sequentially executing the source codes "RLA" and "AND cBX_MDINSW" in the source program shown in FIG. 88.

By changing the detection process of the change mode of the medal sensor input state from the table reference process to the arithmetic process, the free space of the table storage area of the main ROM 102 can be increased and the increase in the program capacity can be minimized. it can. Therefore, by adopting the above-mentioned processing method, it is possible to improve the efficiency of the detection processing of the change mode of the medal insertion sensor state, and to utilize the increased free space in the main ROM 102 to improve the playability. it can.

[Effects obtained by internal lottery processing]
In the internal lottery process of the pachi-slot machine 1 of the present embodiment (see FIG. 92), the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 93A. By executing this "LDIN" instruction, in the processing of S305, the determination data (the value of the "lottery value selection table or lottery counting table") is stored in the A register, and the request flag status ("special prize winning number") is stored in the C register. + Value of "small winning combination winning number") is stored. Further, by executing the "LDIN" instruction, the address set in the HL register is updated by +2 (addition of 2).

That is, in the determination data acquisition process of S305 during the internal lottery process, both the data load process and the address update process can be performed by one instruction code (“LDIN” instruction). In this case, the instruction code related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the addition processing of the set value data (any of 0 to 5) of S309 of the internal lottery processing, the main CPU 101 uses the source codes "MUL A, 6" and "ADDQ A, (.LOW.wWAVENUM)" in FIG. 93B. ) ”Is executed in this order.

The "MUL" instruction is an instruction code for multiplication processing dedicated to the main CPU 101, and the execution of this instruction is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, since the pachi-slot machine 1 of the present embodiment is provided with a dedicated calculation circuit (calculation circuit 107) for executing multiplication processing and division processing on the source program, the efficiency of multiplication processing and division processing should be improved. Can be done.

Further, the "ADDQ" instruction (predetermined addition instruction) is an instruction code dedicated to the main CPU 101, and is an instruction code for specifying an address using a Q register (extension register). Then, by using this "ADDQ" instruction, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by the direct value. Therefore, by using the "ADDQ" instruction, the instruction related to the address setting can be omitted on the source program of the internal lottery processing, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. Can be done. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by design setting process]
In the symbol setting process (see FIG. 97) of the pachi-slot machine 1 of the present embodiment, the compressed data storage process of S330 is performed by the main CPU 101 executing the source code "CALLF SB_BTEP_00" in FIG. 99. The "CALLF" instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above, and when the source code "CALLF SB_BTEP_00" in FIG. 99 is executed, processing is performed at the address specified by "SB_BTEP_00". Jump and start the compressed data storage process.

Further, the setting process of the address of the hit request flag storage area of S329 during the symbol setting process is performed by the main CPU 101 executing the source code "LDQ DE, .LOW. WWAVEBIT" in FIG. 99. That is, the processing of S329 is performed by the "LDQ" instruction dedicated to the main CPU 101 using the Q register (extension register). In this case, the instruction code related to the address setting can be omitted on the source program of the symbol setting process, and the capacity of the source program of the symbol setting process (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the present embodiment, the data related to the winning is compressed / decompressed by the processing procedure described in S324 to S330 during the symbol setting process described above, and the command code dedicated to the main CPU 101 described above is used in the process. By using it, it is possible to improve the efficiency of the compression / decompression processing of the data related to the winning, and it is possible to effectively utilize the limited capacity of the main RAM 103.

[Effects obtained by sub-flag conversion processing]
In the sub-flag conversion table shown in FIG. 107, which is actually referred to on the source program of the sub-flag conversion process in the pachi-slot machine 1 of the present embodiment, the sub-flag conversion control data (control status) is associated with each sub-flag. .. At this time, the same sub-flag conversion control data (control status) is associated with the same type of sub-flag.

For example, the sub-flag conversion control data (control status) "00000011B" is commonly assigned to the sub-flags "triple chili lip A" and "triple chili lip B". Then, in the flag conversion lottery process when converting the internal winning combination (sub-flag) to the sub-flag EX, the lottery is performed based on the sub-flag conversion control data (control status) associated with the sub-flag.

In this way, in the sub-flag conversion table managed on the main side, by providing common sub-flag conversion control data for the same type of internal winning combination (sub-flag), the versatility of the conversion table is increased, and the conversion table is changed. Since changes in the conversion program can be handled with minor changes, it is possible to suppress an increase in development costs.

[Effects obtained by navigation set processing]
In the navigation set processing of the pachislot machine 1 of the present embodiment, as shown in FIG. 109, the "LDQ" instruction (instruction code dedicated to the main CPU 101) that specifies the address using the Q register (extension register) is used in the source program. Be done.

Therefore, in the navigation set processing of the present embodiment, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by table data acquisition processing]
In the table data acquisition process of the pachislot machine 1 of the present embodiment (see FIG. 120), in the table data acquisition process of the first stage of S581 to S584, the table selection by winning combination in the CT winning lottery table during CT (see FIG. 122) is selected. Relative table is referenced. Then, in the table selection relative table for each winning combination referred to in the table data acquisition process of the first stage, the "loss" of the CT lottery is set by the selection value provided for each type of the internal winning combination (sub flag D). Therefore, it is not necessary to specify the lottery value of the "missing" role in the lottery table. Therefore, in the present embodiment, it is not necessary to store the lottery value data of the “missing” role in the CT winning lottery table during CT, and the capacity of the table area of the main ROM 102 can be saved.

Further, in the lottery table of the second stage (when subflag D "reach eye lip" is acquired) in the CT winning lottery table during CT, the lottery target combination or the non-lottery target combination is determined by the value of each bit constituting the determination bit. This eliminates the need to store lottery value data (loss data) in a table for a combination that is not subject to lottery. Further, in the CT winning lottery table during CT, the lottery value "0" can be used as the definite data in which the winning probability of the winning combination of the lottery target combination is 100%. From these facts, in this embodiment, the capacity of the CT winning lottery table during CT (the lottery table with the number of sets added during CT) can be compressed, and the free space can be secured (increased) in the main ROM 102. , You can improve the playability by utilizing the increased free space.

[Effects obtained by design code acquisition processing]
In the symbol code acquisition process (see FIG. 128) of the pachislot machine 1 of the present embodiment, the data related to the winning is compressed / decompressed by the processing procedure described in S647 to S649, and the main CPU 101 dedicated command in the processing is performed. By using a code (such as a "CALLF" command), it is possible to improve the efficiency of the data compression / decompression processing related to the winning, and it is possible to effectively utilize the limited capacity of the main RAM 103.

Further, in the present embodiment, in the compressed data storage process of S649 during the symbol code acquisition process, the jump destination address specified by the "CALLF" command is the compressed data storage process of S330 during the symbol setting process (see FIG. 97). Is the same as the jump destination address specified by the "CALLF" instruction. That is, in the present embodiment, the source program for executing the compressed data storage process is shared (modularized) in both the symbol code acquisition process and the symbol setting process. In this case, since it is not necessary to separately provide the source program for the compressed data storage process in each process, the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by pull-in priority acquisition processing]
In the pull-in priority order acquisition process of the pachi-slot machine 1 of the present embodiment (see FIGS. 134 and 135), the determination process of S683 during the pull-in priority correspondence process of the “ANY combination” is performed by the main CPU 101 dedicated instruction code on the source program. It is executed by a certain "JCP" instruction (comparison instruction) (see FIG. 136A).

When the "JCP" command is used in the source program of the "ANY role" pull-in priority processing, the command related to the address setting can be omitted as described above, so the "ANY role" pull-in priority support The processing efficiency of the processing can be increased, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced.

Further, in the stop control pull-in request flag setting process of S686 during the pull-in priority acquisition process, as shown in FIG. 136B, the Q register (extension register), which is the instruction code dedicated to the main CPU 101, is used on the source program. The "LDQ" instruction and the "CALLF" instruction for specifying an address are used.

Therefore, in the stop control pull-in request flag setting process of S686, by using the "LDQ" instruction, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (use of the main ROM 102). Capacity) can be reduced. Further, the "CALLF" instruction is a 2-byte instruction code as described above. Therefore, by using these main CPU 101 dedicated instruction codes in the stop control pull-in request flag setting process, the processing efficiency can be improved and the limited capacity of the main RAM 103 can be effectively utilized. ..

Further, in the present embodiment, in the stop control pull-in request flag setting process of S686 during the priority pull-in order acquisition process, the address of the jump destination logical product operation process specified by the "CALLF" instruction is the pull-in priority order storage process ( It is the same as the jump destination address specified by the "CALLF" instruction in the logical product operation processing of S626 in (see FIG. 126) (see FIG. 127). That is, in the present embodiment, the source program for executing the AND operation processing is shared (modularized) in both the priority attraction order acquisition process and the attraction priority order storage process.

In this case, since it is not necessary to separately provide the source program for the logical product operation processing in both the priority attraction order acquisition process and the attraction priority order storage process, the capacity of the source program (the capacity used by the main ROM 102) is increased accordingly. Can be reduced. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the acquisition process of the attraction priority table (see FIG. 137) of S687 during the attraction priority acquisition process, as shown in FIG. 136C, the "LDQ" instruction (instruction code dedicated to the main CPU 101) is used. Therefore, even in the acquisition process of the pull-in priority table in S687, the instruction related to the address setting can be omitted on the source program. As a result, the efficiency of the acquisition process of the pull-in priority table can be improved, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced.

[Effects obtained by reel stop control processing]
In the reel stop control process of the pachi-slot machine 1 of the present embodiment (see FIG. 138), in the processes of S711 to S715, as shown in FIG. 139, the address is specified by using the Q register (extension register) on the source program. The "LDQ" instruction and the "CALLF" instruction are used.

Therefore, in the present embodiment, by using these main CPU 101 dedicated instruction codes, the capacity of the source program for the reel control processing can be reduced, and the processing efficiency of the reel stop control processing can be improved. That is, in the present embodiment, it is possible to improve the efficiency of the program processing speed and reduce the capacity of the main control circuit 90, and utilize the free area of the main ROM 102 increased according to the reduced capacity to improve the playability. Can be enhanced.

Further, in the determination process of S726 during the reel stop control process (check process of the stop state of the reel (rotary cylinder)), as shown in FIG. 140, the "LDQ" instruction and the "ORQ" instruction (Q) are displayed on the source program. A main CPU 101 dedicated instruction code) that specifies an address using a register (extension register) is used.

Therefore, in the present embodiment, the instruction related to the address setting can be omitted on the source program of the reel stop control process, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. .. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by winning search processing]
In the winning search process of the pachislot machine 1 of the present embodiment (see FIG. 145), in the set process of the number of payouts and the determination target data in S764, as shown in FIG. 146, the "LDIN" command is used on the source program.

Therefore, in the winning search process of the present embodiment, both the data load process and the address update process can be performed by one "LDIN" command. In this case, the instruction related to the address setting can be omitted on the source program of the winning search process, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, the acquisition process of the medal counter value referred to in the determination process of S770 during the prize search process, the acquisition process of the value of the prize number counter referred to in the process of S772, and the saving of the prize number counter performed in the process of S775 ( In each of the (update) processes, as shown in FIG. 146, an "LDQ" instruction for specifying an address using a Q register (extension register) is used. Therefore, in the winning search process of the present embodiment, the instruction related to the address setting can be omitted on the source program, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

Further, in the determination process of S769 during the winning search process, as shown in FIG. 146, the "JSLAA" instruction is used on the source program, and in the determination process of S770 and S773, the "JCP" instruction is used. When the "JSLAA" command and the "JCP" command are used on the source program of the winning search process, the command related to the address setting can be omitted as described above, and the capacity of the source program (main ROM 102) can be omitted accordingly. (Capacity used) can be reduced. As a result, in the present embodiment, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve the playability.

[Effects obtained by illegal hit check processing]
In the present embodiment, as shown in FIGS. 28 to 30, the configuration of the winning operation flag storage area (display combination storage area) is the same as that of the hit request flag storage area (internal winning combination storage area). Therefore, in the arithmetic processing of S784 in the illegal hit check processing of the present embodiment, the data of the winning combination and the data of the internal winning combination are simply ANDed on the source program (see FIG. 149) by a logical product (“AND” instruction). You can get the result of combining the winning combination data and the internal winning combination data just by executing).

Therefore, in the present embodiment, the illegal hit check process can be made more efficient and simplified, and as a result, the free space of the main control program can be secured, and the free space can be used to enhance the game playability. be able to.

[Effects obtained by winning check / medal payout processing]
In the winning check / medal payout process (see FIG. 150) of the pachislot machine 1 of the present embodiment, when the payout operation is continued after the credit counter is updated (+1), the wait (payout interval) of 60.33 ms is performed in the process of S808. Wait) Processing is performed. In this case, unnecessary waiting time can be reduced, and the mental burden on the player can be reduced.

[Effects obtained by checking the number of medals paid out]
In the update process of the winning combination end number counter of S814 during the medal payout number check process (see FIG. 152) of the pachislot machine 1 of the present embodiment, as shown in FIG. 153A, it is an instruction code dedicated to the main CPU 101 on the source program. The "DCPLD" instruction is used.

In the processing of S814, the "DCPLD" instruction is an instruction code in which the lower limit determination instruction of the number management counter and the determination branch instruction are integrated. Both processes of holding the counter value at "0" can be executed. In this case, it is not necessary to provide an instruction code for executing both processes separately. Therefore, in the medal payout number check process of the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, and the free space can be secured (increased) in the main ROM 102, resulting in an increase. It is possible to improve the playability by utilizing the free space.

Further, in the process of S816 during the medal payout number check process, as shown in FIG. 153B, the value of the payout counter is set in the communication parameter 1 of the credit information command, and the value of the credit counter is set in the communication parameter 5. Will be done. However, the values stored in the H register, the E register, and the D register at the present time are set in the other communication parameters 2 to 4 (unused parameters) constituting the credit information command. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and fraudulent acts such as goto can be suppressed.

[Effects obtained by 7-segment LED drive processing]
As shown in FIG. 160B, the output processing of the 7-segment common output (selection) data and the 7-segment cathode output data performed in S936 in the 7-segment LED drive processing (see FIG. 159) of the pachislot machine 1 of the present embodiment is one source. It is executed by the code "LD (cPA_SEGCOM), BC". That is, in the present embodiment, in the 7-segment LED drive process, when the 2-digit 7-segment LED is dynamically lit and controlled, the 7-segment common output data and the 7-segment cathode output data are output at the same time. This output control is also performed when the push order display data is displayed on the instruction monitor in the information display 6.

In this case, the number of instruction codes required for the dynamic lighting control of the 7-segment LED can be reduced on the source program of the 7-segment LED drive process. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, the playability can be enhanced.

[Effects obtained by timer update processing]
In the process of S952 (update process of the 2-byte timer) in the timer update process of the pachislot machine 1 of the present embodiment (see FIG. 164), as shown in FIG. The "DCPWLD" command is used.

When the "DCPWLD" instruction is executed in the timer update process, both the process of updating (subtracting) the number of timers (number of 2-byte timers) and the process of holding the number of timers at "0" are executed as described above. Can be done. In this case, it is not necessary to provide an instruction code for executing both processes separately. Therefore, in the present embodiment, the capacity of the source program (the capacity used by the main ROM 102) can be reduced, the free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized. Therefore, the playability can be enhanced.

<Various deformation examples>
The configuration and operation of the gaming machine according to the present invention have been described above, including their effects. However, the present invention is not limited to the above-described embodiments, and includes various other embodiments and modifications as long as it does not deviate from the gist of the present invention described in the claims.

[Modification example 1: CT precursor game and notification lottery during normal ART]
In the pachislot machine 1 of the above embodiment, in order to facilitate understanding, an example in which the gaming state is shifted from the next game (next game) to an advantageous state when the player wins a favorable state (for example, CT). However, the present invention is not limited to this. For example, when performing game control in an advantageous state for a player, the game control in the advantageous state may be performed after performing a predetermined number of games, which is called a so-called "precursor game". ..

Here, with reference to FIGS. 174A and 174B, as an example thereof, an example in which the gaming state shifts from the normal ART to the CT via a predetermined number of precursor games will be described. Note that FIG. 174A is a diagram showing a game flow at the time of winning the CT lottery in the first modification, and FIG. 174B is a configuration diagram of a flag conversion lottery table used in the flag conversion lottery performed during the precursory game.

In the game during the normal ART of this example, first, as shown in FIG. 174A, the CT lottery table during the ART (see FIG. 50) is used as in the above embodiment, and the CT lottery is based on the internal winning combination (sub flag). I do. When the CT lottery is won, it is determined that the gaming state shifts to a state advantageous for the player called CT (additional chance zone). Therefore, various lottery for the CT lottery during the period until the CT is won. Is performed on the main side (main control board 71). For example, the main control board 71 (main CPU101) performs an internal lottery for determining the internal winning combination, and also as the internal winning combination, the internal winning combination “F_certain chili lip”, “F_1 certain chili lip”, and “F_reach eye lip A”. When any of "F_reach eye lip D" is determined, the flag conversion lottery is performed using the flag conversion lottery table during ART (see FIGS. 47A and 47B).

Next, when a CT lottery is won in a game during normal ART, in this example, a precursory game (CT precursory game) for a predetermined period is performed before the transition to CT. In this example, in the CT precursor game, for example, a privilege for a player such as a CT lottery based on a sub-flag EX ("triple chili lip", "reach eye lip", "replay", etc.) determined by a flag conversion lottery. The lottery that grants the above will not be performed. However, in this example, in the CT precursor game, for example, a flag conversion lottery using the flag conversion lottery table shown in FIG. 174B is performed on the sub side (sub-control board 72 side), and the flag conversion lottery performed on this sub side is performed. Based on the result, the content of the notification performed on the sub side is controlled (determined). For example, when the flag conversion lottery performed on the sub side is won, the display device 11 (projector mechanism 211 and display unit 212) notifies the information for displaying the symbol combination related to the abbreviation "reach eye lip". When the flag conversion lottery is not won, the display device 11 notifies the information for displaying the symbol combination related to the abbreviation "replay".

As described above, in recent pachislot machines, it is required that the main side perform a lottery that affects the profit (ball output) of the player, but in the pachislot machine 1 of this example, the lottery result of the flag conversion lottery is the game. A period (period of CT precursor game) that does not affect the interests of the person is provided, and the flag conversion lottery is performed on the sub side only during this period. Therefore, in this example, for example, in a situation where the privilege of being in the CT omen is decided, it is possible to increase the chance of displaying a special symbol combination such as the symbol combination related to the abbreviation "reach eye lip". At the same time, it is possible to increase the variation of how to show the combination of symbols. As a result, according to the configuration of this example, it is possible to further improve the playability.

The lottery table shown in FIG. 174B is a flag conversion lottery table in the CT precursor used for the flag conversion lottery performed on the sub side, and is stored in the ROM cartridge substrate 86. The flag conversion lottery table in the CT omen includes the internal winning roles "F_reach eye lip A" to "F_reach eye lip D", the lottery result (non-winning / winning) of the flag conversion lottery performed on the sub side, and each lottery. The correspondence with the lottery value information associated with the result is specified.

As is clear from the flag conversion lottery table shown in FIG. 174B, in this example, in the CT precursor game, the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" have a very high probability of sub-flag EX ". It is converted to "reach eye lip" (wins the flag conversion lottery). That is, in the CT precursor game, when any of the internal winning combinations "F_reach eye lip A" to "F_reach eye lip D" is determined, the symbol combination of the abbreviation "reach eye lip" is stopped and displayed with high probability. Therefore, it is possible to suggest to the player that the current game is in the CT precursor game. At this time, as described above, when the flag conversion lottery performed on the sub side in the CT precursor game is won, the notification for displaying the symbol combination related to the abbreviation "reach eye lip" is performed, but the privilege is given. There is no.

In this example, the flag conversion lottery during the CT precursor game may be performed on the main side. However, as in the example described with reference to FIGS. 174A and 174B, the data capacity and processing load on the main side can be reduced by performing the lottery on the sub side during a period that does not affect the profit of the player.

[Modification example 2: Another example of push order for triple chili lip display]
In the pachislot machine 1 of the above embodiment, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, if the stop button pressing order is correct, the symbol combination related to the abbreviation "triple chili lip" is used. An example has been described in which a symbol combination related to the abbreviation "replay" is displayed when the display is displayed and the pressing order is incorrect (see FIG. 24). Further, in the above-described embodiment, an example has been described in which the correct push order associated with the internal winning combinations “F_certain chili lip” and “F_1 certain chili lip” is “forward push”. However, the present invention is not limited to this.

For example, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, the types of symbol combinations displayed when the pressing order is incorrect are increased, and the internal winning combination "F_certain chili lip" is increased. The correct push order when "" is determined may be different from that when the internal winning combination "F_1 certainty lip" is determined. An example thereof (modification example 2) will be described with reference to FIGS. 175A and 175B. Note that FIG. 175A is a diagram showing the correspondence relationship between the internal winning combination and the symbol combination (stop symbol (abbreviation)) displayed as a stop in the modified example 2, and FIG. 175B is a diagram showing the correspondence between the internal winning combination and the symbol combination (stop symbol (abbreviation)) displayed in the stop. It is a figure which shows the correspondence relationship between the result of the flag conversion lottery of, and the navigation type performed on the sub side.

In this example, as shown in FIG. 175A, when the internal winning combination "F_certain chili lip" is determined, the correct push order is "forward push (left reel 3L is the first stop)", and the wrong answer is pushed. The order is "first stop of the middle reel 3C (hereinafter referred to as" middle push ") or first stop of the right reel 3R (hereinafter referred to as" reverse push ")", that is, "irregular push". Then, in this example, when the internal winning combination "F_certain chili lip" is determined, the symbol combination related to the abbreviation "triple chili lip" is displayed when pressed forward, and the abbreviation "replay" is displayed when pressed in the middle. The symbol combination related to is displayed, and when it is pushed backward, the symbol combination related to the abbreviation "double chili lip" is displayed.

Further, in this example, when the internal winning combination "F_1 certainty lip" is determined, the correct answer is pushed in the reverse order, and the incorrect answer is pushed in the forward and middle push orders. Then, in this example, when the internal winning combination "F_1 certain chili lip" is determined, when it is pressed backward, the symbol combination related to the abbreviation "triple chili lip" is displayed, and when it is pressed in the middle, the abbreviation "replay" is displayed. The symbol combination according to is displayed, and when it is pushed forward, the symbol combination related to the abbreviation "double chili lip" is displayed.

In the pachislot machine 1 of this example, when either the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, if the player presses forward, the abbreviation "triple chili lip" or the abbreviation "triple chili lip" or The symbol combination related to "double chili lip" is displayed. In addition, when either the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined and pressed backward, the abbreviation "triple chili lip" or "double chili lip" is used depending on the type of internal winning combination. The symbol combination related to "" is displayed. Further, in this example, when either of the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined, if the player presses the button in the middle, the symbol combination related to the abbreviation "replay" is performed regardless of the type of the internal winning combination. Is displayed.

When the correspondence between the internal winning combination and the symbol combination displayed as stopped (stop symbol (abbreviation)) is set to the relationship shown in FIG. 175A, for example, the internal winning combination “F_certain chili lip” or “F_1 certain chili lip” is determined. In that case, it becomes possible to carry out various navigations (notifications) for the player to aim at the Chilean pattern.

For example, both "navigation that aims at the chili symbol by pushing forward" and "navigation that aims at the chili symbol by pushing backward" can be performed. In addition, when the internal winning role "F_certain chili lip" is decided, "navigation that aims at the chili symbol by pushing forward" becomes a navigation for displaying the symbol combination related to the abbreviation "triple chili lip", and " "Navi that aims at the chili symbol by reverse pressing" is a navigation for not displaying the symbol combination related to the abbreviation "triple chili lip" (navigation that displays the symbol combination related to the abbreviation "double chili lip"). On the other hand, when the internal winning combination "F_1 certain chili lip" is decided, "navigation that aims at the chili symbol by pushing forward" is a navigation for not displaying the symbol combination related to the abbreviation "triple chili lip" (abbreviation "navigation"). The navigation that displays the symbol combination related to "double chili lip"), and the "navigation that aims at the chili symbol by reverse pressing" is the navigation for displaying the symbol combination related to the abbreviation "triple chili lip".

In this example, the decision as to whether or not to perform the above-mentioned navigation is managed by the flag conversion lottery performed on the main side, and the navigation is executed by the control of the sub side based on the result of the flag conversion lottery on the main side. .. At this time, the correspondence between the lottery result of the flag conversion lottery normally performed on the main side during ART and the navigation type controlled on the sub side is the correspondence relationship shown in FIG. 175B.

Also in this example, when the internal winning combination "F_certain chili lip" or "F_1 certain chili lip" is determined in the game during normal ART, the main control board 71 (main CPU 101) performs a two-step flag conversion lottery ( See FIG. 47). On the other hand, on the sub side, the result of the two-step flag conversion lottery is acquired from the start command data, and the navigation to be performed by the display device 11 is determined based on the result of the two-step flag conversion lottery.

Therefore, in this example, when the lottery result is non-winning at the time of the first stage flag conversion lottery, the sub control board 72 (sub CPU201) is referred to as "replay navigation" as shown in FIG. 175B. Perform the so-called navigation. In the "replay navigation", information instructing the player to press the button is notified. In this example, as shown in FIG. 174A, regardless of whether the internal winning combination is "F_certain chili lip" or "F_1 certain chili lip", the symbol combination related to the abbreviation "replay" is displayed at the time of middle pressing. ..

Further, in this example, when the first stage flag conversion lottery is won and the lottery result of the second stage flag conversion lottery is non-winning, the sub control board 72 (sub CPU201) is shown in FIG. 175B. As shown in, the navigation called "Chililip fan navigation" is performed. In addition, in the "Chile Lip Fan Navi", when the internal winning combination "F_certain Chile Lip" is determined, the player is notified of the instruction information to aim the Chile symbol by pushing back. On the other hand, in the "Chile Lip Fan Navi", when the internal winning combination "F_1 Definite Chile Lip" is determined, the player is notified of the instruction information to aim the Chile symbol by pushing forward. Then, in such a "chili lip fan navigation", as shown in FIG. 174A, when the internal winning is "F_certain chili lip", the symbol combination related to the abbreviation "double chili lip" is displayed at the time of reverse pressing. When the internal winning combination is "F_1 certain chili lip", the symbol combination related to the abbreviation "double chili lip" is displayed at the time of forward pressing.

Further, in this example, when both the first stage and the second stage flag conversion lottery are won, the sub control board 72 (sub CPU201) is referred to as a "chili lip aligned navigation" as shown in FIG. 175B. Navigating. In addition, in the "Chile Lip Matching Navi", when the internal winning combination "F_certain Chile Lip" is determined, the player is notified of the instruction information to aim the Chile symbol by pushing forward. On the other hand, in the "Chile Lip Matching Navi", when the internal winning combination "F_1 Definite Chile Lip" is determined, the player is notified of the instruction information to aim the Chile symbol by pushing back. Then, in such a "chili lip matching navigation", as shown in FIG. 174A, when the internal winning is "F_certain chili lip", the symbol combination related to the abbreviation "triple chili lip" is displayed at the time of forward pressing. When the internal winning combination is "F_1 certain chili lip", the symbol combination related to the abbreviation "triple chili lip" is displayed at the time of reverse pressing.

In this example, the notification based on the lottery result of the flag conversion lottery described above does not affect the profit (the flag conversion lottery itself affects the profit, but the symbol combination displayed as a result affects the profit. Therefore, the above notification operation of this example is not performed on the main side (instruction monitor), but is performed only on the sub side (display device 11). Further, in this example, as described above, by performing not only the "chili lip matching navigation" but also the "chili lip fanning navigation", the navigation that does not affect the profit can be controlled by the sub side in various modes. .. As a result, the interest of the game can be improved.

[Modification 3: Another example of the bell navigation mode between flags and between non-flags]
In the pachi-slot machine 1 of the above embodiment, as described above, the main side is notified by displaying the numerical value uniquely corresponding to the information of the reel stop operation on the instruction monitor (not shown). At this time, the correspondence relationship of the navigation data described with reference to FIGS. 63A to 63D is referred to. Then, in the above embodiment, an example in which "white 7 navigation" and "blue 7 navigation" are performed during the BB flag state (RT5 state) but "bell navigation" is not performed has been described. Not limited. In the state between BB flags (RT5), "Bell Navi" or the like may be performed in addition to "White 7 Navi" or "Blue 7 Navi".

In this case, the numerical values displayed on the instruction monitor may be different from each other in the state between the BB flags and the state between the non-BB flags. Here, FIGS. 176A and 176B show the correspondence between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the state between the BB flags in the modified example 3. Note that FIG. 176A is a diagram showing a correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the RT5 state (between the BB1 flags), and FIG. 176B is a diagram showing the correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side. It is a figure which shows the correspondence relationship between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side in (between BB2 flags).

Further, in this example, the correspondence between the notification (navigation) performed on the main side and the notification (navigation) performed on the sub side during the non-BB flag state is the same as that of the above embodiment (see FIGS. 63A and 63B). .. Therefore, when "Bell Navi" is performed in the non-BB flag state, numerical values "1" to "3" (pushing order second instruction information) are displayed on the instruction monitor.

In this example, as shown in FIGS. 176A and 176B, when "Bell Navi" is performed in the state between BB flags, numerical values "12" to "14" (pushing order first instruction information) are displayed on the instruction monitor. The flag. The present invention is not limited to this, and the numerical value displayed on the instruction monitor can be appropriately changed when "Bell Navi" is performed in the state between the BB flags. In this example, the navigation on the sub side performed by using the display device 11 may be provided in common in both the BB flag inter-flag state and the non-BB flag inter-flag state.

[Modification 4: Another example of granting benefits]
In the pachi-slot machine 1 of the above embodiment, since the notification content is controlled based on the result of the flag conversion lottery performed on the main side, the symbol combination displayed is different when the stop operation is performed according to the notification. That is, in the above embodiment, an example in which whether or not to grant the privilege is determined based on the result of the flag conversion lottery performed on the main side has been described, but the present invention is not limited to this. For example, on the main side (main control board 71), the privilege may be given based on the actually displayed symbol combination.

In this case, the main control board 71 (main CPU 101) gives a privilege when a predetermined symbol combination is displayed according to the notification performed according to the result of the flag conversion lottery, and when the notification is not followed, the main control board 71 (main CPU 101) gives a privilege. , Even if a predetermined symbol combination is displayed, the privilege may not be given. In the pachislot machine 1 of the above embodiment, the symbol combinations displayed according to the pressing order are different, but even when the player ignores the notification and performs the stop operation, the symbol combinations related to the abbreviation "triple chili lip" are used. There is a possibility that a special symbol combination such as, etc. will be displayed. Therefore, in this example, even if the notification is ignored and a special symbol combination is displayed, the privilege is given only when the special symbol combination is displayed according to the notification without giving the privilege. You may.

[Modification 5: Another example of notification control that does not affect profits (privileges)]
In the pachislot machine 1 of the above modification 1 (see FIGS. 174A and 174B), whether or not to perform the notification that affects the profit is determined by the notification lottery (flag conversion lottery) on the main side and does not affect the profit. An example in which whether or not to perform notification is determined by a notification lottery on the sub side has been described. Then, as an example of the notification that does not affect the profit, an example of performing the notification for displaying the symbol combination related to the abbreviation "reach eye lip" during the precursory game has been described, but the notification that does not affect the profit is described. , Not limited to this example.

In recent pachislot machines, the game may be changed to a state in which it is easy (difficult) to lock the game according to the order of stop operations. For example, transitioning to a state where it is easy to lock the game when the pressing order is "left, middle, right", and transitioning to a state where it is difficult to lock the game when the pressing order is "right, middle, left". There is. In such a pachislot machine, it is possible to shift to a state in which it is easy (difficult) to lock the game by notifying the pushing order. However, if whether or not to lock the game affects the profit, it is necessary to control this notification on the main side. If whether or not to lock the game does not affect the profit, this notification may be controlled on the sub side.

Further, as a case where whether or not to perform the game lock affects the profit, for example, it is conceivable that the game lock is performed to win the ART lottery. On the other hand, when whether or not to perform the game lock does not affect the profit, it is the case where the game lock is performed as an effect. For example, by frequently performing the game lock during the precursory game in which it is decided to give a profit (privilege), it becomes possible to show in the production that the profit will be given in the subsequent game. ..

Here, with reference to FIGS. 177A and 117B, a configuration example in which the push order and the locked state are associated with each other in the modified example 5 will be described. It should be noted that FIG. 177A is a diagram showing the correspondence relationship between the push order and the locked state, and FIG. 177B is a diagram showing the relationship between the presence or absence of the influence of the game lock on the profit and the notification mode.

In the example shown in FIG. 177A, when the internal winning combination “F_maintenance lip A” is determined and the stop operation is performed in the pressing order of “left, middle, right”, the lock state is “0” (a state in which it is difficult to lock). ) To "1" (easy to lock), and when the stop operation is performed in the pressing order of "left, right, middle", "middle, left, right" or "middle, right, left", the current When the locked state of is maintained and the stop operation is performed in the pressing order of "right, left, middle" or "right, middle, left", the locked state changes from "1" to "0". In addition, when the internal winning combination "F_maintenance lip B" is determined, if the stop operation is performed in the pressing order of "middle, left, right", the lock state changes from "0" (a state in which it is difficult to lock) to "1". "(Easy to lock state), and when the stop operation is performed in any other pressing order, the current locked state is maintained.

In the example shown in FIG. 117A, in order to simplify the explanation, an example in which the lock state is set to two stages of "0 (difficult to lock state)" and "1 (easy to lock)" will be described. The present invention is not limited to this. For example, a locked state of three or more stages may be provided. Further, in this case, the lock state may not be changed step by step, but may be changed in multiple steps at one time.

Then, in this example, as shown in FIG. 117B, when the game lock affects the profit, a notification lottery for whether or not to perform notification is performed on the main (main control board 71) side, and the lottery result is performed. The predetermined push order is notified on both the main side and the sub side based on. On the other hand, when the game lock does not affect the profit, a notification lottery for whether or not to perform notification is performed on the sub (sub-control board 72) side, and a predetermined push order is performed on the sub side based on the lottery result. Is notified.

As pachislot, there are pachislots in which the game lock affects the profit for the entire period of the game, and there are pachislots in which the game lock does not affect the profit for the entire period of the game. Further, as a pachislot, there is a pachislot in which the game lock affects the profit during a predetermined period of the game, but the game lock does not affect the profit during a specific period of the game. Therefore, during the period when the game lock affects the profit, the main side performs a notification lottery as to whether or not to notify, and based on the lottery result, both the main side and the sub side notify the predetermined push order. On the other hand, during the period when the game lock does not affect the profit, the sub side may perform a notification lottery as to whether or not to notify, and the sub side may notify the predetermined push order based on the lottery result. Good.

Since the game lock is normally controlled on the main side (main control board 71), the main control board 71 is provided with a function of transitioning the locked state according to the pressing order shown in FIG. 117A. That is, the main control board 71 draws lots for whether or not to lock the game with a probability according to the lock state setting means for setting the lock state based on the order of the detected stop operations and the lock state set by the lock state setting means. It also functions as a game lock determination means determined by the above, and a lock execution means for temporarily stopping the progress of the game when it is determined that the game lock determination means performs the game lock. Further, when the lock state setting means sets the lock state in which the game lock is easy (difficult), the main control board 71 and / or the sub control board 72 is notified by lottery as to whether or not to notify the push order. It also functions as a lottery means and a notification means for notifying a predetermined push order based on the lottery result of the notification lottery means.

[Modification 6: Another example of normal ART and CT termination conditions]
Normally, the termination conditions for ART and CT are not limited to the examples described in the above embodiments, and any termination conditions can be adopted. For example, the number of medals awarded during normal ART or CT, the number of times a unit game is digested during normal ART or CT, the number of times information is notified that is advantageous to the player during normal ART or CT, When the predetermined number of games (for example, 50 games) is set as one set, the end condition such as the number of sets and the continuation rate at the end of one set can be adopted.

Further, as a method for counting the number of medals given during normal ART or CT, for example, a method for counting the number of medals paid out in a unit game may be adopted, or a method of counting the number of medals paid out in a unit game may be adopted. A method of counting the difference number (net increase number) obtained by subtracting the number of bets (multiplications) of the medals used in the unit game from the number of medals played may be adopted. Further, as a method for counting the number of medals given during normal ART or CT, a method of calculating based on the actually increased medals (calculation based on the actual value) may be adopted, or has the number actually increased? Regardless of whether or not, a method of calculating based on the number of medals scheduled to increase when following the notification (calculation based on an ideal value) may be adopted.

Further, depending on the type of internal winning combination, a configuration in which the number of medals granted is not increased, that is, a configuration in which the number of medals that is the end condition of the number of medals granted or the difference is not counted may be adopted. .. For example, even if a part of the winning combination (rare role) with a low probability of being determined as the internal winning combination or a combination in which the display / non-display of the symbol combination is switched according to the timing of the stop operation is determined as the internal winning combination. , The number of medals granted may not be increased or decreased (counted).

<Second Embodiment>
Subsequently, another embodiment of the pachi-slot machine 1 according to the present invention will be described. The pachi-slot machine 1 of the second embodiment shown below is different in game playability from the pachi-slot machine 1 of the first embodiment and various modified examples, and the data compression / expansion described in the first embodiment and various modified examples is performed. It can be applied in the same way to control related to how to hold data and various processes. Further, in the second embodiment, detailed description of the same configuration as that of the first embodiment will be omitted.

In the pachi-slot machine 1 of the second embodiment, among the pseudo lines connecting the patterns of 3 rows × 3 columns displayed in the frame of the reel display window 4, the cross-down line is used as an effective line, and the other lines are simulated. Used as a line. That is, the pachislot 1 has a unit symbol display area in the upper part of the left reel 3L, and a reel 3C in the middle, in the unit symbol display area of 3 rows × 3 columns for displaying one symbol of each reel in the reel display window 4. The cross-down line formed by connecting the unit symbol display area in the middle row and the unit symbol display area in the lower row of the right reel 3R is used as an effective line, and is formed by connecting the other unit symbol display areas. Line is used as a pseudo line. The pseudo lines include, for example, a top line connecting the unit symbol display areas on the upper stage of each reel, a center line connecting the unit symbol display areas on the middle stage of each reel, and a bottom line connecting the unit symbol display areas on the lower stage of each reel. , And a cross-up line connecting the unit symbol display areas of the lower part of the reel 3L, the middle part of the reel 3C, and the upper part of the reel 3R.

<Transition flow of game state>
First, various gaming states managed by the main control circuit 90 (main CPU 101) of the pachi-slot machine 1 of the second embodiment and their transition flows will be described with reference to FIG. 178.

[Basic game state transition flow]
In the pachislot machine 1 of the present embodiment, a big bonus (hereinafter referred to as "BB") is provided as a type of bonus game. The BB is a continuous accessory actuating device for a regular bonus (hereinafter referred to as “RB”) called a first-class special accessory, and continuously operates the RB.

Therefore, in the present embodiment, the main control circuit 90 manages the gaming state based on the presence or absence of winning / operating (winning) of the bonus combination. Specifically, as shown in FIG. 178, the main control circuit 90 has a winning / operating (winning) of a bonus combination (internal winning combination of the names "F_BB_black", "F_BB_red", and "F_BB_blue" described later). Based on the above, three types of gaming states called "bonus non-winning state", "between flags state", and "bonus state" are managed.

The bonus non-winning state is a state in which the bonus is not winning and the bonus is not activated (winning), and the bonus state is a state in which the bonus is activated. Further, in the present embodiment, when the bonus combination is determined as the internal winning combination, the bonus combination is carried over as the internal winning combination over a plurality of games until the bonus is won. The inter-flag state is a state in which the bonus combination is carried over as an internal winning combination, that is, a state in which the bonus combination is won and the bonus is not activated.

Further, in the present embodiment, eight types of states from the RT0 gaming state to the RT7 gaming state in which the types of internal winning combinations related to the replay and the winning probabilities thereof are different from each other (hereinafter, referred to as "RT0 state" to "RT7 state", respectively). Is provided. In the present embodiment, the RT state in the bonus non-winning state is any of the RT0 state to the RT3 state, the RT state in the inter-flag state is the RT4 state or the RT5 state, and the RT state in the bonus state is the RT6 state or RT7. It becomes a state.

The RT0 state, RT1 state, RT4 state, RT5 state and RT7 state are low RT states in which the winning probability of the internal winning combination related to the replay is low, and the RT2 state, RT3 state and RT6 state are the internal winning related to the replay. It is a high RT state with a high probability of winning a role.

As shown in FIG. 178, when the symbol combination related to the abbreviation "bell spilled eyes" (see FIGS. 195 to 201 described later) is displayed on the valid line in the RT0 state (when the transition condition (1) is satisfied). , The main control circuit 90 shifts the gaming state from the RT0 state to the RT1 state. In the RT1 state, when the symbol combination related to the abbreviation "RT2 transition lip" (see FIGS. 195 to 201 described later) is displayed on the valid line (when the transition condition (2) is satisfied), the main control circuit 90 is set to. The gaming state is changed from the RT1 state to the RT2 state.

Further, in the RT2 state or the RT3 state, when the symbol combination (see FIGS. 195 to 201 described later) related to the abbreviation "bell spilled eye" or "RT1 transition lip" is displayed on the valid line (transition condition (3)). The main control circuit 90 shifts the gaming state from the RT2 state or the RT3 state to the RT1 state. Further, in the RT2 state, when the symbol combination related to the abbreviation "RT3 transition lip" (see FIGS. 195 to 201 described later) is displayed on the effective line (when the transition condition (4) is satisfied), the main control circuit 90 Shifts the gaming state from the RT2 state to the RT3 state.

Further, when the bonus combination is determined as the internal winning combination in the bonus non-winning state, the main control circuit 90 shifts the gaming state from the bonus non-winning state to the inter-flag state. Specifically, when the internal winning combination related to the name "F_BB_black" or "F_BB_red" described later is determined as the bonus combination (when the transition condition (5) is satisfied), the main control circuit 90 sets the gaming state. It shifts from the bonus non-winning state to the RT4 state between the flags. Further, when the internal winning combination related to the name "F_BB_blue" is determined as the bonus combination (when the transition condition (6) is satisfied), the main control circuit 90 changes the gaming state from the bonus non-winning state to the inter-flag state RT5. Move to the state.

Further, when the bonus combination is won in the inter-flag state, the main control circuit 90 shifts the gaming state from the inter-flag state to the bonus state. Specifically, when the symbol combination (see FIGS. 195 to 201 described later) related to the abbreviation "black BB (name" C_BB_A "described later)" is displayed on the valid line (when the transition condition (7) is satisfied). ), The main control circuit 90 shifts the gaming state from the inter-flag state to the RT6 state of the bonus state. Further, the symbol combination (see FIGS. 195 to 201 described later) relating to the abbreviation "red BB (names" C_BB_B1 "and" C_BB_B2 "described later)" or "blue BB (names" C_BB_C1 "and" C_BB_C2 "described later)" is effective. When displayed on the line (when the transition condition (8) is satisfied), the main control circuit 90 shifts the gaming state from the inter-flag state to the RT7 state of the bonus state. The RT6 state in the bonus state may be referred to as "special BB" below, and the RT7 state in the bonus state may be referred to as "normal BB" below.

Further, when the number of medals exceeding the specified number is paid out in the bonus state and the bonus state ends (when the transition condition (9) is satisfied), the main control circuit 90 changes the game state from the bonus state to the RT0 state in which the bonus is not won. To migrate to. Here, in the present embodiment, the specified number of sheets that triggers the end of the bonus state is "27 sheets" in the special BB and "297 sheets" in the normal BB.

As for the symbol combination related to the abbreviation "bell spilled eyes", the internal winning combination (small combination) related to the names "F_1stB_1" to "F_3rdB_2" described later is determined, and the order of the stop operation is for each type of the small combination. It is a combination of symbols displayed when the answer is incorrect with respect to the pressing order specified in (see FIG. 194 described later). Further, as for the symbol combination related to the abbreviation "RT1 transition lip", the internal winning combination (replay combination) related to the names "F_lip RT3_1st" to "F_lip RT I_3rd" described later is determined, and the order of the stop operations is determined. It is a combination of symbols displayed when the answer is incorrect with respect to the push order determined for each type of the replay combination (see FIG. 194 described later).

Further, for the symbol combination related to the abbreviation "RT2 transition lip", the internal winning combination (replay combination) related to the names "F_lip RT2_123" to "F_lip RT2_321" described later is determined, and the order of the stop operations is the replay. This is a combination of symbols displayed when the answer is correct for the push order determined for each combination type (see FIG. 194 described later).

Further, as for the symbol combination related to the abbreviation "RT3 transition lip", the internal winning combination (replay combination) related to the names "F_lip RT3_1st" to "F_lip RT3_3rd" described later is determined, and the order of the stop operation is the replay. This is a combination of symbols displayed when the answer is correct for the push order determined for each combination type (see FIG. 194 described later).

<Structure of data table stored in main ROM>
Next, the configurations of various data tables stored in the main ROM 102 will be described with reference to FIGS. 179 to 193.

[Design arrangement table]
First, the symbol arrangement table will be described with reference to FIG. 179. The symbol arrangement table is data that specifies the position of each symbol in each rotation direction of the left reel 3L, the middle reel 3C, and the right reel 3R, and the type of the symbol arranged at each position (hereinafter, symbol code (in FIG. 179). (Refer to the symbol code table of)) and stipulate the correspondence with.

In the pachislot machine 1 of the second embodiment, as shown in the symbol code table, each reel has the symbols "black BAR", "white BAR", "red 7", "blue 7", "replay 1", "replay 2", and "replay 2". Ten kinds of symbols of "bell", "watermelon", "cherry" and "blank" are displayed.

[Internal lottery table]
Next, the internal lottery table referred to when determining the internal winning combination will be described with reference to FIGS. 180 and 181. The internal lottery table is provided for each game state, and defines the correspondence between various internal winning combinations and the lottery value when each internal winning combination is determined. In the RT0 state in the bonus non-winning state, the internal lottery table for RT0 is referred to, and in the RT1 state in the bonus non-winning state, the internal lottery table for RT1 is referred to, and in the RT2 state in the bonus non-winning state. Refers to the internal lottery table for RT2, and refers to the internal lottery table for RT3 during the RT3 state in which the bonus is not won. In addition, the internal lottery table for the black flag is referred to during the inter-flag state carrying over the internal winning combination "F_BB_black", and the red flag is referred to during the inter-flag state carrying over the internal winning combination "F_BB_red". The internal lottery table for the inter-flag is referred to, and the internal lottery table for the blue flag is referred to during the inter-flag state in which the internal winning combination "F_BB_blue" is carried over. Further, during the bonus state of the special BB, the internal lottery table for the special BB is referred to, and during the bonus state of the normal BB, the internal lottery table for the normal BB is referred to.

[Correspondence table between internal winning combination and symbol combination (winning combination) (symbol combination determination table)]
Next, with reference to FIGS. 182 to 193, a correspondence table (symbol combination determination table) between the internal winning combination and the symbol combination will be described. The symbol combination determination table defines the correspondence between various internal winning combinations and symbol combinations (combinations) that can be displayed on the effective line and are associated with each internal winning combination. That is, when the internal winning combination is determined, the type of symbol combination that can be displayed on the valid line (type of display combination that can be won) is uniquely determined.

The various data described in the symbol combination column in each symbol combination determination table is for identifying the symbol combination that is permitted to be displayed along the effective line set over the left reel 3L, the middle reel 3C, and the right reel 3R. It is data. The relationship between each name described in the symbol combination (display combination) column and a specific symbol combination will be described later in FIGS. 195 to 201.

Further, the "○" mark described in the symbol combination determination table indicates a symbol combination (combination) that can be displayed on the effective line in the determined internal winning combination, that is, a display combination that can win a prize. It should be noted that the symbol combination determination table does not specify the case where the "internal winning combination" is "off", but this is all the symbols defined by the symbol combination table shown in FIGS. 182 to 193. Indicates that the display of combinations is not allowed.

In the pachislot machine 1 of the present embodiment, the main control circuit 90 (main CPU 101) has different stop controls depending on the internal winning combination and the gaming state, and when a predetermined combination is determined as the internal winning combination, FIGS. The rotation stop control of the left reel 3L, the middle reel 3C, and the right reel 3R is performed so that the corresponding symbol combinations shown in FIG. 193 can be displayed. In the correspondence table shown in FIGS. 182 to 193, all the symbol combinations that can be displayed for the determined internal winning combination are listed by "○", but the symbols marked with "○" are listed. Even if it is a combination, it may not be displayed even if it is a combination of symbols marked with "○" due to the relationship of the symbols to be drawn in with priority.

[Correspondence between winning combination and symbol combination displayed as stopped]
Here, with reference to FIG. 194, the correspondence between the internal winning combination and the symbol combination displayed as a stop will be described. Note that FIG. 194 is a diagram showing a correspondence relationship between various internal winning combinations that can be determined and a symbol combination (abbreviation) that is stopped and displayed when each internal winning combination is determined.

In the pachi-slot machine 1 of the present embodiment, a so-called “pushing order combination” is provided in which the symbol combinations displayed differ according to the order (pushing order) of the player's stop operations. As described above, for a part of the push order combination, the correct push order is shown in a part of the name. For example, the internal winning combination with "1st" in a part of the name means that the correct push order is that the first stop operation is for the left reel 3L, and "2nd" is part of the name. A certain internal winning combination means that the correct push order is for the middle reel 3C, and an internal winning combination with "3rd" as part of the name is the correct pushing order. However, it means that the first stop operation is for the right reel 3R. In addition, the end "123" of the name of the internal winning combination means that the correct push order is "left, middle, right", and the end "132" of the name of the internal winning combination is the correct answer. Means that the push order is "left, right, middle", and the last "213" in the name of the internal winning combination means that the correct push order is "middle, left, right". The ending "231" of the name of the internal winning combination means that the correct push order is "left, right, middle", and the ending "312" of the name of the internal winning combination is It means that the correct push order is "right, left, middle", and the end "321" of the name of the internal winning combination is the correct push order in the order of "right, middle, left". It means that there is.

As shown in FIG. 194, the internal winning combination "F_BB_black" is a combination in which the displayed symbol combinations are irrelevant to the pressing order, and the timing of the stop operation is accurate (so-called, so-called eye pressing is accurate). ) Shows any of the displayable symbol combinations shown in FIGS. 182 to 193 of the symbol combinations related to the abbreviation "black BB" (see FIGS. 195 to 201 described later) along the effective line. To. Further, the internal winning combination "F_BB_red" is a combination in which the displayed symbol combinations are irrelevant to the pressing order, and when the timing of the stop operation is accurate, the symbol combination related to the abbreviation "red BB" (described later). Any of the displayable symbol combinations shown in FIGS. 182 to 193 of FIGS. 195 to 201) is displayed along the effective line.

Further, the internal winning combination "F_BB_blue" is a combination in which the displayed symbol combinations are irrelevant to the pressing order, and when the timing of the stop operation is accurate, the symbol combination related to the abbreviation "blue BB" (described later). Any of the displayable symbol combinations shown in FIGS. 182 to 193 of FIGS. 195 to 201) is displayed along the effective line. In addition, the internal winning combination "F_normal lip" is a combination in which the displayed symbol combinations are not related to the pressing order, and the symbol combinations related to the abbreviation "normal replay" are used regardless of the timing of the stop operation (FIGS. 195 to 195 described later). Any of the displayable symbol combinations shown in FIGS. 182 to 193 of (see FIG. 201) is displayed along the effective line.

In addition, the internal winning combinations "F_rip RT2_123" to "F_rip RT2_321" are push order combinations in which the symbol combinations displayed according to the push order are different, and when the push order is correct, the abbreviation "RT2 transition lip" is used. Any of the displayable symbol combinations shown in FIGS. 182 to 193 of the symbol combinations (see FIGS. 195 to 201 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, one of the displayable symbol combinations shown in FIGS. 182 to 193 of the symbol combinations (see FIGS. 195 to 201 described later) according to the abbreviation "normal replay" is used. Displayed along the valid line.

In addition, the internal winning combinations "F_rip RT3_1st" to "F_rip RT3_3rd" are push order combinations in which the symbol combinations displayed according to the push order are different, and when the push order is correct, the abbreviation "RT3 transition lip" is used. Any of the displayable symbol combinations shown in FIGS. 182 to 193 of the symbol combinations (see FIGS. 195 to 201 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, any of the displayable symbol combinations shown in FIGS. 182 to 193 of the symbol combinations (see FIGS. 195 to 201 described later) according to the abbreviation "RT1 transition lip". Is displayed along the valid line.

In addition, the internal winning combinations "F_Rip RT I_123" and "F_Rip RT I_3rd" are push order combinations with different symbol combinations displayed according to the push order, and when the push order is correct, the abbreviation " Any of the displayable symbol combinations shown in FIGS. 182 to 193 of the symbol combinations related to "normal replay" (see FIGS. 195 to 201 described later) is displayed along the effective line. On the other hand, if the pressing order is not correct, any of the displayable symbol combinations shown in FIGS. 182 to 193 of the symbol combinations (see FIGS. 195 to 201 described later) according to the abbreviation "RT1 transition lip". Is displayed along the valid line.

In addition, the internal winning combination "F_Rip BARF" is a combination in which the displayed symbol combinations are not related to the pressing order, and when the timing of the stop operation is accurate, the symbol combination related to the abbreviation "BAR fanning" (described later). Any of the displayable symbol combinations shown in FIGS. 182 to 193 of (see FIGS. 195 to 201) is displayed along the effective line. In addition, the internal winning combinations "F_Rip BARS_1" to "F_Rip BART" are roles in which the displayed symbol combinations are not related to the pressing order, and when the timing of the stop operation is accurate, the abbreviation "BAR alignment" is used. Any of the displayable symbol combinations shown in FIGS. 182 to 193 of the symbol combinations according to the above (see FIGS. 195 to 201 described later) is displayed along the effective line. The letters "S", "W", and "T" following "Rip BAR" in the internal winning roles "F_Rip BARS_1" to "F_Rip BAR" are five lines including valid lines and pseudo lines. Of these, "white BAR-white BAR-white BAR" indicates the number of lines displayed side by side, and the internal winning combination "F_Rip BARS_1" and "F_" with "S" attached after "Rip BAR". In "Rip BARS_2", "White BAR-White BAR-White BAR" is displayed side by side only on one of the five lines, and "W" is added after "Rip BAR". For "F_Rip BARW_1" and "F_Rip BARW_1", "White BAR-White BAR-White BAR" is displayed side by side on two of the five lines, and "T" follows "Rip BAR". In the attached internal winning combination "F_lip BAR", "white BAR-white BAR-white BAR" is displayed side by side on three of the five lines.

In addition, the internal winning combinations "F_1stB_1" to "F_3rdB_2" are push order combinations in which the symbol combinations displayed according to the push order are different, and when the push order is correct, the symbol combination related to the abbreviation "bell" ( Any of the displayable symbol combinations shown in FIGS. 182 to 193 of (see FIGS. 195 to 201) described later is displayed along the effective line. On the other hand, when the pressing order is not correct, the display shown in FIGS. 182 to 193 of the symbol combinations (see FIGS. 195 to 201 described later) according to the abbreviation "first sheet" or "bell spilled eye". Any of the possible symbol combinations are displayed along the valid line.

Further, the internal winning combination "F_ALLB" is a combination in which the displayed symbol combinations are irrelevant to the pressing order, and regardless of the timing of the stop operation, the symbol combination related to the abbreviation "bell" (see FIGS. 195 to 201 described later). ), Any of the displayable symbol combinations shown in FIGS. 182 to 193 is displayed along the effective line. Further, the internal winning combination "F_WMLN" is a combination in which the displayed symbol combinations are irrelevant to the pressing order, and when the timing of the stop operation is accurate, the symbol combination related to the abbreviation "watermelon" (FIG. 195 described later). (See FIG. 201), any of the displayable symbol combinations shown in FIGS. 182 to 193 is displayed along the effective line.

In addition, the internal winning combination "F_CHE" is a combination in which the displayed symbol combinations are irrelevant to the pressing order, and when the timing of the stop operation is accurate, the symbol combination related to the abbreviation "weak cherry" (the figure described later). Any of the displayable symbol combinations shown in FIGS. 182 to 193 of (195 to FIG. 201) is displayed along the effective line. In addition, the internal winning combination "F_SCHE" is a combination in which the displayed symbol combinations are not related to the pressing order, and when the timing of the stop operation is accurate, the symbol combination related to the abbreviation "strong cherry" (the figure described later). Any of the displayable symbol combinations shown in FIGS. 182 to 193 of (195 to FIG. 201) is displayed along the effective line.

In addition, the internal winning combination "F_PCHE" is a combination in which the displayed symbol combinations are irrelevant to the pressing order, and when the timing of the stop operation is accurate, the symbol combination related to the abbreviation "middle cherry" (the figure described later). Any of the displayable symbol combinations shown in FIGS. 182 to 193 of (195 to FIG. 201) is displayed along the effective line. In addition, the internal winning combination "F_CHANGE" is a combination in which the displayed symbol combinations are not related to the pressing order, and when the timing of the stop operation is accurate, the symbol combination related to the abbreviation "chance eye" (the figure described later). Any of the displayable symbol combinations shown in FIGS. 182 to 193 of (195 to FIG. 201) is displayed along the effective line.

Further, the internal winning combination "F_JAC" is a combination in which the displayed symbol combinations are irrelevant to the pressing order, and regardless of the timing of the stop operation, the symbol combination related to the abbreviation "bell" (see FIGS. 195 to 201 described later). ), Any of the displayable symbol combinations shown in FIGS. 182 to 193 is displayed along the effective line.

In the inter-flag state, the winning combination related to the carry-over bonus is always determined as the internal winning combination, so that the stop control can be different from the state other than the inter-flag state. In this regard, in pachislot 1, during the inter-flag state, the concept of correct / incorrect push order is removed from the above-mentioned push order combination, and when the push order combination is determined as the internal winning combination, the push order is always correct. The stop control is performed so that the symbol combination of is displayed along the effective line. As an example, when the internal winning combination "F_1stB_1" is determined as the internal winning combination during the inter-flag state, the symbol combination related to the abbreviation "bell" is always used regardless of the pressing order (see FIGS. 195 to 201 described later). One of the displayable symbol combinations shown in FIGS. 182 to 193 is displayed along the effective line.

[Contents of symbol combination]
Next, the specific contents of the symbol combination will be described with reference to FIGS. 195 to 201. In FIGS. 195 to 201, the combination column means a symbol combination of each reel 3L, 3C, 3R displayed along the effective line when each reel 3L, 3C, 3R is stopped. In addition, the payout column defines the number of medals to be paid out when the corresponding symbol combination is displayed. In addition, the abbreviation column indicates the role of each symbol combination and the abbreviation given from the characteristics of each symbol combination.

The combination name "C_BB_A" is a symbol combination related to the continuous operation device (BB) of the first-class special accessory, and the abbreviation is "black BB". When the symbol combination of the abbreviation "black BB" is displayed along the valid line, the game state shifts to the bonus state (special BB) (see FIG. 178).

Further, the combination names "C_BB_B1" and "C_BB_B2" are symbol combinations related to the continuous operation device (BB) of the first-class special accessory, and the abbreviation is "red BB". Further, the combination names "C_BB_C1" and "C_BB_C2" are symbol combinations related to the continuous operation device (BB) of the first-class special accessory, and the abbreviation is "blue BB". When the symbol combination of the abbreviation "red BB" or "blue BB" is displayed along the valid line, the game state shifts to the bonus state (normal BB) (see FIG. 178).

Further, the combination names "C_C Lip 1_01" to "C_CU Lip 4_04" are symbol combinations related to the abbreviation "normal replay", and when they are displayed along the effective line, the replay operation is performed.

Further, the combination names "C_RT1 rip 1_01" to "C_RT1 rip 2_02" are symbol combinations related to the abbreviation "RT1 transition rip". When the symbol combination of the abbreviation "RT1 transition lip" is displayed along the effective line, the re-game operation is performed and the game state shifts to the RT1 state (see FIG. 178).

Further, the combination names "C_RT2 rip_01" to "C_RT2 rip_08" are symbol combinations related to the abbreviation "RT2 transition rip". When the symbol combination of the abbreviation "RT2 transition lip" is displayed along the effective line, the re-game operation is performed and the game state shifts to the RT2 state (see FIG. 178).

Further, the combination names "C_RT3 lip 1" to "C_RT3 lip 5_04" are symbol combinations related to the abbreviation "RT3 transition lip". When the symbol combination of the abbreviation "RT3 transition lip" is displayed along the effective line, the re-game operation is performed and the game state shifts to the RT3 state (see FIG. 178).

In addition, the combination names "C_BAR Lip 1", "C_BAR Lip 7_01", "C_BAR Lip 8", "C_BAR Lip 10", and "C_BAR Lip 11" are symbol combinations related to the abbreviation "BAR alignment" and are displayed along the effective line. Then, the re-game is activated. In addition, the combination names "C_BAR Lip 2" to "C_BAR Lip 6_02", "C_BAR Lip 7_02", "C_BAR Lip 9", "C_BAR Lip 12" to "C_BAR Lip 15" are symbol combinations related to the abbreviation "BAR fan". When displayed along the valid line, the re-game is activated.

Further, the combination names "C_CUB_01" to "C_CDB" are symbol combinations related to the abbreviation "bell", and when displayed along the valid line, nine medals are paid out. Further, the combination names "C_CUWML_01" to "C_CUWML_06" are symbol combinations related to the abbreviation "watermelon", and when displayed along the valid line, four medals are paid out.

Further, the combination names "C_CHE1_01" to "C_CHE6_10" are symbol combinations related to the abbreviation "strong cherry", and when displayed along the valid line, one medal is paid out. Further, the combination names "C_CHE7_01" to "C_CHE12_07" are symbol combinations related to the abbreviation "weak cherry", and when displayed along the valid line, one medal is paid out.

Further, the combination names "C_PCHE_01" to "C_PCHE_06" are symbol combinations related to the abbreviation "middle cherry", and when displayed along the valid line, one medal is paid out. Further, the combination name "C_CHA" is a symbol combination related to the abbreviation "chance eye", and when displayed along the valid line, one medal is paid out.

Further, the combination names "C_control L1_01" to "C_control R32" are symbol combinations related to the abbreviation "first piece", and when displayed along the valid line, one medal is paid out. Further, the combination names "R_transition L_01" to "R_transition R2_04" are symbol combinations related to the abbreviation "bell spilled eyes", and when displayed along the valid line, the game is played without medals being paid out. The state shifts to the RT1 state (see FIG. 178).

[Transition flow of game state considering whether or not the notification (ART) function is activated]
Subsequently, with reference to FIG. 202, a transition flow of the gaming state in consideration of whether or not the notification (ART) function is activated will be described. In the present embodiment, the main control circuit 90 (main CPU 101) determines whether or not a function (ART function) for notifying a stop operation advantageous to the player is activated. Therefore, in the present embodiment, the activated / non-activated state of the ART function is also managed as the gaming state in the bonus non-operating state.

In the pachi-slot machine 1 of the present embodiment, as shown in FIG. 202, in the non-bonus operating state, the main control circuit 90 is in the “normal game state”, “ART preparing”, and “ART game” based on the presence or absence of notification (ART). "State" is managed as a separate game state.

The normal gaming state is a gaming state (non-ART) in which information on a stop operation that is advantageous to the player is not notified, and is a gaming state that is disadvantageous to the player. Further, the normal gaming state is any of the RT0 to RT3 states, and is an ART non-winning gaming state.

On the other hand, the ART gaming state is a gaming state that notifies information on a stop operation that is advantageous to the player, and is a gaming state that is advantageous to the player. Further, the ART gaming state is basically the RT3 state and the gaming state during the ART winning. In the present embodiment, when the precursor game ends in the state of winning the ART (more specifically, the cycle described later ends) and the RT state shifts to the RT3 state, the ART game starts.

During the ART preparation, it is a preparation period for shifting from the normal gaming state to the ART gaming state. During the ART preparation, the information of the stop operation required to shift the RT state to the RT3 state is notified, and as a result, when the RT state shifts to the RT3 state during the ART preparation, the main control circuit 90 shifts the gaming state. It shifts from the preparation for ART to the ART game state.

As shown in FIG. 202, when the ART lottery described later is won in the normal game state and a predetermined game period elapses (when the transition condition (A) is satisfied), the main control circuit 90 changes the game state from the normal game state. Transition during ART preparation. In the pachislot machine 1 of the present embodiment, the game in the normal game state is managed by the cycle, and when the ART lottery is won at the end of the cycle, the main control circuit 90 sets the game state to the normal game. Transition from the state to ART preparation. Therefore, the predetermined game period after winning the ART lottery means the period from winning the ART lottery to the end of the cycle in the pachislot machine 1 of the present embodiment, but after winning the ART lottery. The predetermined game period is not limited to this, and for example, in the case of a pachislot machine in which a precursory game is performed after winning an ART lottery, the period in which the precursory game is performed corresponds to the predetermined game period.

Then, when the RT state shifts to the RT3 state during the ART preparation (when the transition condition (B) is satisfied), the main control circuit 90 shifts the gaming state from the ART preparation to the ART gaming state. Since the RT state shifts based on the combination of displayed symbols (see FIG. 178), depending on the game situation, the ART lottery is won, and the RT state at the timing when the predetermined game period has elapsed is already RT3. It may be in a state. In such a case, in pachislot 1, it is assumed that both the transition conditions (A) and (B) are satisfied at the timing when the ART lottery is won and the predetermined game period has elapsed, and the game state is set to the normal game. Shift from the state to the ART game state (skipping during ART preparation).

Further, when the ART termination condition is satisfied in the ART gaming state (when the transition condition (C) is satisfied), the main control circuit 90 shifts the gaming state from the ART gaming state to the normal gaming state. The pachislot machine 1 of the present embodiment has a normal ART and an episode ART as ART gaming states. Normally, ART is a game state in which a predetermined number of games (15 to 42 games) are set as one set and the duration is managed by the number of sets or the continuation rate, and the episode ART is fixed when a specific condition is satisfied. It is a gaming state that continues for the number of games (30 games). In such a pachislot machine 1, the condition that the end condition of ART is satisfied means that the game is discontinued by continuous lottery in a state where there is no remaining set number of ART, and the number of remaining games of ART is 0 times. Say.

Further, in the normal ART, when the EP point described later reaches 5 points (when the transition condition (D) is satisfied), the main control circuit 90 shifts the gaming state from the normal ART to the episode ART. Then, when the game is played 30 times in the episode ART (when the transition condition (E) is satisfied), the main control circuit 90 shifts the game state from the episode ART to the normal ART.

Further, in each of the normal game state, the preparation for ART, and the ART game state, when the winning combination related to the bonus is won and the bonus starts (when the transition condition (F) is satisfied), the main control circuit 90 sets the game state. Move to the bonus state. Then, when the ART right is not granted at the end of the bonus state (when the transition condition (G) is satisfied), the main control circuit 90 shifts the gaming state from the bonus state to the normal gaming state, and the bonus state If the ART right is granted at the end of (when the transition condition (H) is satisfied), the gaming state is shifted from the bonus state to the ART preparation.

[Abbreviation for internal winning role]
Subsequently, the details of the flow of the game in the pachislot machine 1 of the present embodiment will be described, but in the following description, the name of the internal winning combination will be simplified. FIG. 203 is a correspondence table regarding the abbreviations of the internal winning combinations. As an example, in the following description, the internal winning combinations "F_normal lip" to "F_lip BARF" are abbreviated as "normal lip", and the internal winning combinations "F_1stB_1" to "F_3rdB_2" are abbreviated as "pushing". It becomes "Shun Bell". Similarly, the other internal winning combinations are abbreviated as shown in FIG. 203.

<Playability during normal game state>
Next, the flow of the game during the normal game state will be described with reference to FIGS. 204 and 205. In the pachislot machine 1 of the present embodiment, during the normal game state, it is managed based on the cycle, and if the ART lottery is won during one cycle, the normal game state (non-ART) is changed to the ART game state after waiting for the end of the cycle. Will be migrated.

Specifically, in the normal game state, the game is performed with one cycle being a period including one or a plurality of modes in which each of the modes continues for a predetermined number of games. As shown in FIG. 204 (A), during the normal game state, the ART lottery at the start of the cycle and the MAP lottery are performed at the start of the cycle, and each game during the cycle is subjected to the transition lottery of the cycle MAP and during the cycle. ART lottery is performed. The MAP lottery is a lottery for drawing a periodic MAP that defines the types of modes constituting one cycle of the game, and the transition lottery for the periodic MAP is a lottery for changing the currently used periodic MAP to another MAP. It is a lottery to change (migrate).

As shown in FIG. 204 (B), the pachi-slot machine 1 of the present embodiment has four types of modes: start mode, accept mode, transfer mode, and decision mode, and among these four modes, the period One or more modes defined by the MAP constitute a period of one cycle. The start mode and the accept mode are modes in which the probability of winning the ART lottery during the cycle is low, the transfer mode is the mode in which the probability of winning the ART lottery during the cycle is high, and the decision mode is the mode in which the probability of winning the ART lottery during the cycle is high. This is a mode with an extremely high probability of winning.

In pachislot 1, during the normal game state, the modes are connected (promoted) in the order of the start mode, the accept mode, the transfer mode, and the decision mode, and the game is aimed at winning the ART. In the same cycle, the start mode is basically easy to connect to the accept mode, but the accept mode may be skipped and connected to the transfer mode or the decision mode. Further, in the same cycle, it is basically easy to connect to the conversion mode from the acceptance mode, but it may be connected to the determination mode by skipping the determination mode, and conversely, it does not lead to the activation mode. Further, in the same cycle, the conversion mode is connected to the decision mode, and is not connected to the start mode and the acceptance mode. Moreover, in the same cycle, the decision mode does not lead to another mode.

That is, when one cycle is composed of four modes, the start mode, the accept mode, the transfer mode, and the decision mode, the activation mode is first used for the game, then the acceptance mode is used for the game, and then the transfer mode. The mode is used for the game, and finally the decision mode is used for the game. Although the types of modes that compose the cycle differ depending on the type of cycle MAP, the order relationship of each mode does not change.

Subsequently, FIG. 204 (C) is a correspondence table showing the types of periodic MAPs in pachislot 1. As shown in FIG. 204 (C), the pachi-slot machine 1 has 15 types of periodic MAPs of MAP1 to MAP15 as periodic MAPs. For example, MAP1 is a periodic MAP whose cycle is composed only of the start mode, MAP3 is a periodic MAP whose cycle is composed of the start mode and the acceptance mode, and MAP15 is the activation mode and the acceptance mode. , A cycle MAP whose cycle is composed of a conversion mode and a decision mode.

For example, in the cycle in which MAP1 is determined as the cycle MAP, the cycle ends when a predetermined number of games are played using the start mode. Further, in the cycle in which MAP3 is determined as the cycle MAP, when a predetermined number of games are played using the start mode, then a predetermined number of games are played using the accept mode, and then the cycle ends. .. Then, if the ART lottery has been won in the cycle, the game state shifts to the ART game state through the preparation for ART. On the other hand, if the ART lottery is not won in the cycle, the next cycle is performed without shifting the gaming state.

In the cycle in which MAP1 is determined as the cycle MAP, the cycle ends without connecting from the start mode to the previous mode, but the cycle MAP is changed based on the above-mentioned MAP transition lottery, so that during the cycle. Will lead to other modes. As an example, when the cycle MAP is changed from MAP1 to MAP3, the mode is connected to the acceptance mode after the activation mode.

Subsequently, FIG. 205 (D) is a correspondence table showing an outline of the effect during the cycle. In the pachislot machine 1, a predetermined effect is performed using the effect stages corresponding to each of the start mode, the accept mode, the transfer mode, and the decision mode. Specifically, the sub-control circuit 200 produces an effect on the display unit 212 using an effect stage corresponding to the mode on the main (main control circuit 90) side. For example, in a situation where the main control circuit 90 is playing a game using the start mode, the sub control circuit 200 performs a predetermined effect on the start stage. In the pachislot machine 1, the sub-control circuit 200 may perform an effect using an effect stage different from the mode on the main side, and this point will be described later.

Subsequently, FIG. 205 (E) is a correspondence table showing an outline of the effect at the time of mode transition. As described above, in the pachislot machine 1, the modes during the cycle are managed by the cycle MAP, and basically, the modes are shifted one by one in the order of the start mode, the accept mode, the transfer mode, and the decision mode. When the modes shift one by one, the sub-control circuit 200 performs a normal stage switching effect according to the mode shift, but when the mode shifts by skipping a specific mode, the sub-control circuit 200 A special stage switching effect is performed according to the mode transition. For example, in the cycle MAP "MAP3", the cycle is composed of the start mode and the accept mode. In this case, since the mode shifts from the start mode to the accept mode, the sub-control circuit 200 performs a normal stage switching effect in accordance with the mode shift. On the other hand, in the cycle MAP "MAP5", the cycle is composed of a start mode and a turn mode. In this case, since the mode skips the acceptance mode and shifts from the start mode to the change mode, the sub-control circuit 200 performs a special stage switching effect according to the shift of the mode.

Further, as will be described later, the mode basically shifts to the next mode when the predetermined number of games is completed, but when it becomes necessary to shift to the mode due to the shift of the periodic MAP, the predetermined number of times May move to the next mode before the game is played. When the sub-control circuit 200 shifts to the next mode due to the completion of the predetermined number of games, the sub-control circuit 200 performs a normal stage switching effect and shifts to the next mode before the predetermined number of games are played. May be a special stage switching effect. As will be described in detail later, for example, when the cycle MAP shifts to MAP4 (transfer mode) while staying in the acceptance mode, the transition from the acceptance mode to the transfer mode is performed before the duration of the mode ends. become. In this case, although the mode transitions are sequentially shifted one by one, the sub-control circuit 200 is special in accordance with the mode shift because the mode shifts to the next mode before the end of the mode duration ends. Perform stage switching production.

Subsequently, FIG. 205 (F) shows the effect configuration of each mode. The start mode, the accept mode, and the transfer mode are modes that continue for 16 to 39 games, and an introduction part of 2 games is provided at the start of each mode, and a judgment of 3 games is provided at the end of each mode. A part is provided. In the introductory part, the episode effect performed in each mode is explained, and in the judgment part, the effect of notifying the result of whether or not to connect to the next mode is performed after the mode ends. Whether or not to connect to the next mode after the end of the mode is managed by the periodic MAP, and if the mode after the current mode is specified by the periodic MAP, it is connected to the next mode, and conversely, If the mode after the current mode is not specified by the cycle MAP, the current cycle ends.

In addition, in games other than the introduction part and the judgment part, episode production is performed. The episode production is an production that shows an episode according to each mode. For example, in a story in which the main character and an enemy character play against each other, in the start mode, the enemy character is dominant in the episode production, and in the acceptance mode, the main character is the main character. The episode production that is being brought back is performed, in the transfer mode, an episode production in which an equal battle is performed is performed, and in the final mode, the final episode of the battle is performed. In Pachislot 1, the remaining 5 games during the episode production are counted down to the judgment part. That is, the start mode, the accept mode, and the transfer mode continue for 16 to 39 games, but when the end of each mode is approached, a countdown is performed until the end of the mode (determination part).

On the other hand, the final mode is a mode that continues for five games, and during the final mode, a final episode showing the final battle between the main character and the enemy character is performed. If the ART lottery is won during this cycle, the hero wins the game, and the game state shifts to the ART game state. On the other hand, if the ART lottery is not won during this cycle, the main character will be defeated, and the next cycle will start without shifting the game state.

<Various data tables used during normal gaming>
Subsequently, various data tables used during the normal gaming state will be described with reference to FIGS. 206 to 218.

[ART lottery table at the start of the cycle]
FIG. 206 is a cycle start ART lottery table used for the ART lottery performed at the start of one cycle. The ART lottery table at the start of the cycle defines the lottery value information for the lottery result of the ART lottery.

[Periodic MAP lottery table]
FIG. 207 is a cycle MAP lottery table used for drawing the cycle MAP used for the current cycle at the start of one cycle. The periodic MAP lottery table is provided for each lottery state, and defines information on the lottery value for the periodic MAP used in the current cycle. In addition, as the lottery state, "(no loop mode stock) and (end with transfer / decision)""(no loop mode stock) and (1, 4, 7 ... period)""(No loop mode stock), (1, 4, 7 ... cycle) and (ends with transfer / decision)""(No loop mode stock) and (other than that)""( There are 5 patterns of states (with loop mode stock) ”.

When the ART lottery (FIG. 206) at the start of the cycle is won, the loop mode described later is given. Therefore, "without / with loop mode stock" means whether or not the ART lottery performed at the start of the cycle was won, and if it was won, "with loop mode stock" or non-winning. In that case, refer to "No stock in loop mode". In addition, "end by transfer / decision" means that the previous cycle ended in the transfer mode or decision mode, and at the start of the next cycle that ended in the transfer mode or decision mode, "end by transfer / decision". See. Further, "1, 4, 7 ... Cycle" means the number of cycles performed so far, and this cycle is the 1, 4, 7 ... Cycle (that is, 3n-2). In the case of (cycle th), refer to "1, 4, 7 ... Cycle th". The number of cycles means the number of cycles performed without shifting to the ART gaming state, and is cleared (updated to 0) when shifting to the ART gaming state.

With reference to the periodic MAP lottery table, it can be seen that MAP1 (initiated mode) or MAP3 (initiated mode and accepted mode) can be easily determined as the periodic MAP at the start of the cycle when there is no stock in the loop mode. Therefore, if there is no stock in the loop mode at the start of the cycle, the cycle will start from the start mode with an extremely high probability. On the other hand, if there is a stock of loop mode, the cycle MAPs at the start of the cycle are MAP8 (decision mode), MAP12 (transition mode and decision mode), MAP13 (start mode, transfer mode and decision mode), and MAP15 (decision mode). Start mode, acceptance mode, transfer mode and decision mode) are determined. Therefore, if there is a stock of the loop mode at the start of the cycle, the cycle is likely to be started from the start mode, but the start mode may be skipped and started from the rotation mode or the decision mode.

[Game number lottery table]
FIG. 208 is a game number lottery table used for drawing the number of games in the start mode, the accept mode, and the transfer mode. As described above, the start mode, the accept mode, and the transfer mode are modes that continue for 16 to 39 games, and the game number lottery table defines the lottery value information for the number of games in each mode. In FIG. 208, the number of games having a predetermined range such as "16 to 23 games" is defined as the lottery result, but in the present embodiment, the number of games is randomly selected from the number of games in this range. The number of games played is determined as the number of games in each mode.

Here, the timing of drawing the number of games in the start mode, the accept mode, and the transfer mode is arbitrary. For example, since the mode is defined by the periodic MAP, the number of games for all the modes defined by the periodic MAP may be drawn at once at the timing when the periodic MAP is determined (or shifted). At the timing, the number of games for the mode specified by the cycle MAP may be individually drawn. Further, at the start of each mode, only the number of games for the mode may be drawn.

[ART lottery table]
FIG. 209 is an ART lottery table used for an ART lottery performed during a normal game state or during preparation for ART, and FIG. 209 (A) shows an ART lottery table during a cycle referred to during a cycle during the ART non-winning period (ART non-winning). 209 (A) is an ART lottery table during the cycle referred to during the cycle after winning ART (for after winning ART), and FIG. 209 (C) is referenced during preparation for ART. Preparing for ART lottery table (for preparing for ART).

The ART lottery table during the cycle (for non-winning ART) defines the lottery value information about the lottery result of the ART lottery for each internal winning combination and the current mode, and the ART lottery table during the cycle (after the ART winning). The ART lottery table (for ART preparation) defines the lottery value information about the lottery result of the ART lottery for each internal winning combination.

As described above, in the pachislot machine 1 of the present embodiment, the duration of the ART gaming state (normal ART) is managed by the number of sets or the continuation rate. Therefore, the pachislot machine 1 has an ART right having a continuation rate (loop mode 0 to 3) and an ART right not having a continuation rate (loop mode 4). Specifically, the loop modes 0 to 3 having a continuation rate may be determined to be continued with a probability corresponding to the loop mode in the continuous lottery of the normal ART, and if it is determined to be continued, the said It is maintained without consumption in the normal ART of the set. On the other hand, the loop mode 4 having no continuation rate is always determined to be non-continuation in the continuous lottery of the normal ART, and as a result, it is consumed when one set of the normal ART is completed.

When an ART lottery using an ART lottery table (for non-winning ART) is won during the cycle, one of loop modes 0 to 3 having a continuation rate is given. On the other hand, when the ART lottery using the ART lottery table (for after winning ART) and the ART lottery table under preparation (for preparing for ART) is won during the cycle, one loop mode 4 having no continuation rate is given. Will be done.

In the ART lottery table shown in FIG. 209, when the abbreviation "middle-tier cherry" is determined as the internal winning combination, the abbreviation "middle-tier cherry" is always a non-winning combination, but the abbreviation "middle-tier cherry" is the internal winning combination. When determined as, one stock of loop mode 3 and three stocks of loop mode 4 are given. More specifically, if the abbreviation "middle cherry" is determined as the internal winning combination, it will always be non-winning in the lottery process using the ART lottery table, but the stock of loop mode 3 will be stocked based on other processes. One and three stocks of loop mode 4 are given.

With reference to the ART lottery table (for non-winning ART) during the cycle of FIG. 209 (A), comparing the start mode and the accept mode with the transfer mode and the decision mode, the start mode and the accept mode win the ART lottery. It can be seen that the probability of winning the ART lottery is high in the transfer mode and the decision mode. In addition, when comparing the transfer mode and the decision mode, when the abbreviations "watermelon", "weak cherry", "strong cherry", "chance eye", and "BB" are determined as internal winning roles, the decision mode has a higher probability. Although it wins the ART lottery, it can be seen that in the transfer mode, even if the abbreviations "off", "normal lip", "push order bell", and "common bell" are determined as the internal winning roles, the ART lottery is won. ..

[MAP transition lottery table]
FIGS. 210 to 217 are MAP transition lottery tables used for the transition lottery of the periodic MAP performed in each game during the cycle. The MAP transition lottery table is provided for each mode in which the user is currently staying and the presence or absence of stock in the current loop mode. FIG. 210 is a MAP transition lottery table that is referred to when there is no loop mode stock and the mode currently staying is the start mode, and FIG. 211 is a loop mode stock and is currently It is a MAP transition lottery table referred to when the mode staying is the acceptance mode, and FIG. 212 is referred to when there is no stock of the loop mode and the mode currently staying is the transfer mode. It is a MAP transition lottery table, and FIG. 213 is a MAP transition lottery table that is referred to when there is no stock of the loop mode and the mode currently staying is the decision mode. Further, FIG. 214 is a MAP transition lottery table that is referred to when there is a loop mode stock and the mode currently staying is the start mode, and FIG. 215 is a loop mode stock and is a reference. , The MAP transition lottery table referred to when the mode currently staying is the acceptance mode, FIG. 216 shows the case where there is a stock of loop mode and the mode currently staying is the transfer mode. It is a MAP transition lottery table to be referred to, and FIG. 217 is a MAP transition lottery table to be referred to when there is a stock of loop mode and the mode currently staying is the decision mode.

In the MAP transition lottery table (FIGS. 210 to 213) that is referred to when there is no stock in the loop mode, the data to be referred to is further different depending on the presence or absence of cycle continuation. Here, the presence / absence of cycle continuation means whether or not the cycle ends in the mode in which the person is currently staying, and when the cycle ends in the mode in which the person is currently staying, the data in the "end column" is referred to. If the cycle does not end in the mode in which you are currently staying, the data in the "continuation column" is referred to. Here, whether or not the cycle ends in the mode currently staying is defined by the cycle MAP, so the result of the transition lottery of the cycle MAP is used in the mode currently staying and in the current cycle. It depends on the period MAP.

For example, referring to FIG. 204 (C), the period MAP including the acceptance mode is MAP2,3,6,7,10,11,14,15, but the period of MAP2,3 ends in the acceptance mode. It is a periodic MAP, and the other MAPs are periodic MAPs in which a transfer mode or a decision mode is performed following the acceptance mode. Therefore, when the mode currently staying is the acceptance mode and the cycle MAP used in the current cycle is MAP2,3, the data in the "end column" of FIG. 211 is referred to, and the current cycle When the period MAP used in is MAP 6,7,10,11,14,15, the data in the “continuation column” of FIG. 211 will be referred to.

Further, in the MAP transition lottery table (FIGS. 214 to 217), which is referred to when there is a stock in the loop mode, data to be referred to depending on whether it is the first hit of the ART lottery or after the winning is further obtained. different. The first hit of the ART lottery means the game of winning the ART lottery without the stock of the loop mode, and after the winning of the ART lottery, the winning of the ART lottery without the stock of the loop mode. A game that is later than the game that was played. Therefore, for example, in the game in which the ART lottery is won while staying in the start mode, the data in the “first hit column” of FIG. 214 is referred to, and in the subsequent games during the cycle, the MAP shifts according to the mode in which the player is staying. The data in the "after-winning column" in the lottery table is referred to.

As shown in FIGS. 210 to 217, the MAP transition lottery table defines information on the lottery value for the cycle map of the transition destination for each internal winning combination. Here, when the transition lottery of the periodic MAP is won, the mode shifts to the periodic MAP including the mode prior to the mode specified by the currently used periodic MAP, and the mode is higher than the mode specified by the currently used periodic MAP. There is no transition to the period MAP of the previous mode only.

For example, when the cycle MAP currently used is a cycle MAP ending in the start mode, the cycle MAP shifts to the cycle MAP including the acceptance mode, the transfer mode, or the decision mode, and the cycle MAP currently used ends in the acceptance mode. If, the cycle MAP includes the transfer mode or the decision mode, and if the cycle MAP currently used is a cycle MAP that ends in the transfer mode, the cycle MAP includes the decision mode. On the contrary, for example, the cycle MAP including the acceptance mode does not shift to the cycle MAP ending in the start mode, and the cycle MAP including the transfer mode does not shift to the cycle MAP ending in the start mode or the acceptance mode. There is no transition from a periodic MAP containing the MAP to a periodic MAP ending in the start mode, the accept mode or the transfer mode.

With reference to FIGS. 210 to 217, the transition of the periodic MAP is likely to be performed when a so-called rare role such as the abbreviations "watermelon", "weak cherry", "strong cherry", and "chance eye" is determined as the internal winning role, and the abbreviation It can be seen that it is difficult to perform when a winning combination with a high winning probability, such as "off", "normal lip", "pushing order bell", or "common bell", is determined as an internal winning combination. Further, as shown in FIG. 207, when there is no stock in the loop mode, it is easy to determine the MAP1 or MAP3 that ends in the start mode and the accept mode, which have a low probability of winning the ART lottery, as the cycle MAP at the start of the cycle, and ART. It is difficult to determine the periodic MAP including the transfer mode and the decision mode, which have a high probability of winning the lottery. Therefore, in the pachislot machine 1, during the cycle, the rare role is used as an opportunity to shift from the MAP 1 or the MAP 3 to the cycle MAP including the transfer mode and the decision mode.

However, referring to FIGS. 210 and 211, when this cycle ends in the start mode or the accept mode, not only the rare role but also the abbreviations "off", "normal lip", "push order bell", and "common bell" are used. Even if there is, the transition of the periodic MAP may be performed. Here, the case where the periodic MAP is transferred based on the rare combination and the case where the periodic MAP is transferred based on the combination other than the rare combination will be compared. When ending in the start mode (that is, MAP1), referring to FIG. 210, in the transition of the periodic MAP based on the rare combination, it is possible to shift to MAP3, 4, 5 but the periodic MAP based on the combination other than the rare combination. In the migration, only MAP3 is migrated. Here, the MAP 3 is configured to include the start mode and the accept mode, and the MAPs 4 and 5 are configured to include the transfer mode. Therefore, in the transition of the periodic MAP based on the combination other than the rare combination, it is possible to shift only to the periodic MAP including the next acceptance mode of the start mode ending in the current periodic MAP, while in the transition of the periodic MAP based on the rare combination, It can be seen that it is possible to shift to the cycle MAP including the conversion mode two ahead of the start mode that ends in the current cycle MAP.

Further, referring to FIG. 210, when the current cycle ends in the start mode, it is easy to shift to the MAP 3 composed of the start mode and the acceptance mode when the cycle MAP shifts (more than a predetermined probability). , It can be seen that it is difficult to shift to MAPs 4 and 5 including the transfer mode without including the acceptance mode (less than a predetermined probability). Similarly, referring to FIG. 211, when the current cycle ends in the acceptance mode, when the cycle MAP transition is performed, it is easy to shift to the MAP 7 composed of the start mode, the acceptance mode, and the transfer mode (see FIG. 211). It can be seen that (more than a predetermined probability). For this reason, in Pachislot 1, the mode basically shifts (promotes) in the order of start mode, acceptance mode, and transfer mode, but skips acceptance mode and directly shifts from activation mode to conversion mode. Because it may be done, it is possible to have diversity.

[Mode transition game number lottery table]
In pachislot 1, when the cycle MAP is changed, the mode may also be changed in accordance with this change. FIG. 218 is a mode transition game number lottery table for drawing the number of games (mode transition games) from the transition of the periodic MAP to the mode transition in accordance with the transition of the periodic MAP. The mode transition game number lottery table defines information on the lottery value for the lottery result (mode transition game number).

Whether or not to shift the mode according to the shift of the periodic MAP can be controlled by an arbitrary method. For example, at the timing when it is decided to shift the periodic MAP, a predetermined lottery may be performed once, and when the lottery is won, the mode may be changed according to the transition of the periodic MAP, or the periodic MAP may be changed. In each game from the time when it is decided to shift to the mode until the mode shifts, a predetermined lottery is performed, and when the lottery is won, the mode may be shifted according to the shift of the periodic MAP. Good.

Further, when the mode shift becomes necessary due to the shift of the periodic MAP, the mode may be shifted according to the shift of the periodic MAP. In the present embodiment, when the mode shift becomes necessary, the cycle may be changed. The mode is to be changed according to the change of MAP. Specifically, as shown in FIGS. 210 to 217, the transition of the periodic MAP is performed based on the mode currently staying, but the mode currently staying in the cycle MAP after the transition is not included. Sometimes. For example, when staying in the start mode, it may shift to MAP4 (see FIG. 210), and since MAP4 consists only of the transfer mode, in this case, the start currently staying in the cycle MAP after the shift. Mode is not included. In such a case, the pachislot machine 1 determines that the mode shift is necessary due to the shift of the cycle MAP, performs the shift of the cycle MAP, and then waits for the elapse of the number of mode shift games to shift the mode.

(Example of transition of periodic MAP)
Subsequently, an example of transition of the periodic MAP will be described with reference to FIGS. 219 and 220. FIG. 219 (A) shows a transition example 1 of the periodic MAP when the mode transition is not necessary. In FIG. 219 (A), as a result of non-winning the ART lottery at the start of the cycle, the cycle MAP of MAP1 (starting mode) is determined in the MAP lottery at the start of the cycle, and then during the stay in the starting mode defined by MAP1. , The ART lottery has not been won, and the transition lottery to MAP3 has been won. As a result, in the cycle MAP at the start of the cycle, the cycle ends only in the start mode, but the cycle ends after the acceptance mode is performed following the start mode.

After that, while staying in the acceptance mode specified by MAP3, he wins the transition lottery to MAP7 without winning the ART lottery. As a result, the cycle ends in the start mode and the accept mode, but the cycle ends after the transfer mode is performed following the accept mode.

After that, while staying in the transfer mode defined by MAP7, he won the ART lottery and also won the transition lottery to MAP15. As a result, the cycle ends at the end of the turn mode, and the next cycle (normal game state) starts, but after the turn mode is followed by the decision mode, the cycle Is finished, and then the ART game state is performed.

Further, FIG. 219 (B) shows a transition example 2 of the periodic MAP when the mode transition is not necessary. In FIG. 219 (B), as a result of not winning the ART lottery at the start of the cycle, the cycle MAP of MAP1 is determined in the MAP lottery at the start of the cycle, and then the ART lottery is performed during the stay in the start mode defined by MAP1. Winning and winning the transition lottery to MAP15. As a result, in the cycle MAP at the start of the cycle, the cycle ends only in the start mode and the next cycle (normal game state) starts. After the mode and the decision mode are performed, the cycle ends, and then the ART gaming state is performed.

Further, FIG. 220 (C) shows a transition example 3 of the periodic MAP when the mode transition is necessary. In FIG. 220 (C), as a result of not winning the ART lottery at the start of the cycle, the cycle MAP of MAP1 is determined in the MAP lottery at the start of the cycle. After that, during the stay in the start mode specified by MAP1, the lottery for transition to MAP3 was won without winning the ART lottery, and during the stay in the start mode specified by MAP3, the ART lottery was won and MAP12 You are winning the transition lottery to.

Here, in the transition to MAP3 performed during the stay in the activation mode, since the activation mode is also defined in the MAP3 after the transition, it is not necessary to perform the mode transition with the transition of the periodic MAP, and the activation mode is used. You can wait for the end to move to the next mode. On the other hand, in the transition to the MAP 12 performed during the stay in the activation mode, since the activation mode is not specified in the MAP 12 after the transition, it is necessary to perform the mode transition with the transition of the periodic MAP. Therefore, the main control circuit 90 draws out the number of mode transition games, shortens the number of games in the activation mode, and shifts the mode from the activation mode to the rotation mode.

As a result, in the cycle MAP at the start of the cycle, the cycle ends after waiting for the number of games in the start mode to be exhausted, and the next cycle (normal game state) starts. After the transfer mode and the decision mode are performed without waiting for the number to be exhausted, the cycle ends, and then the ART game state is performed.

Further, FIG. 220 (D) shows a transition example 4 of the periodic MAP when the mode transition is necessary. In FIG. 220 (D), as a result of winning the ART lottery at the start of the cycle, the cycle MAP of the MAP 15 is determined in the MAP lottery at the start of the cycle, and then the transition to the MAP 12 is performed during the stay in the start mode defined by the MAP 15. You are winning the lottery.

As described above, in the transition to the MAP 12 performed during the stay in the activation mode, since the activation mode is not specified in the MAP 12 after the transition, it is necessary to perform the mode transition with the transition of the periodic MAP. Therefore, the main control circuit 90 draws out the number of mode transition games, shortens the number of games in the activation mode, and shifts the mode from the activation mode to the rotation mode. As a result, in the cycle MAP at the start of the cycle, the situation where the cycle ends after waiting for the number of games in the start mode, the accept mode, the transfer mode, and the decision mode to be exhausted is the number of games in the start mode and the accept mode. After the transfer mode and the decision mode are performed without waiting for the digestion, the cycle ends, and then the ART game state is performed.

(Example of mode transition)
Subsequently, an example of mode transition will be described with reference to FIG. 221. FIG. 221 (A) is a mode transition example 1, and shows a mode transition example when there is no need for mode transition. At the start of the wake-up mode, the number of games in the wake-up mode (16 to 39 games) is determined by lottery, and when the determined number of games elapses, the wake-up mode ends. Since the MAP 1 is composed of only the start mode, when the cycle MAP is MAP1, when the start mode ends, the current cycle also ends.

On the other hand, since the MAP 3 includes the start mode and the accept mode, if the transition from the MAP 1 to the MAP 3 is performed during the stay in the start mode, the accept mode starts after the end of the start mode. If there is no need to shift to the mode, the mode will not shift immediately even after the cycle MAP has shifted, and the acceptance mode will start after the number of games determined at the start of the start mode has elapsed.

FIG. 221 (B) is a mode transition example 2, and shows a mode transition example when mode transition is necessary. In FIG. 221 (B), the transition from MAP1 to MAP12 is performed during the stay in the start mode. Since the MAP 12 after the transition does not include the start mode during the current stay, the mode also shifts in accordance with the shift of the periodic MAP. Specifically, the number of mode transition games (1 to 4 games) is determined by lottery, and when the number of mode transition games elapses after the cycle MAP is shifted, the mode is changed. Since the MAP 12 includes a transfer mode and a decision mode, when the transition from the MAP 1 to the MAP 12 is performed, the number of games determined at the start of the start mode is shortened, and the MAP 12 shifts to the transfer mode.

FIG. 221 (C) is a mode transition example 3, and shows a mode transition example when mode transition is necessary. As described above, the final 3 games of the start mode, the accept mode, and the transfer mode are produced by the judgment part to report the result of whether or not the next mode is connected, and the judgment is made from the remaining 5 games during the episode production. A countdown to the part is performed (see FIG. 205 (F)). In pachislot 1, the number of games is shortened in order to ensure continuity in production even when the cycle MAP that requires mode transition is changed between the countdown and the judgment part. Mode transition is performed without any.

Specifically, when the transition from MAP1 to MAP12 while staying in the start mode is performed in a game in which the number of remaining games until the end of the start mode is 8 games or less, as shown in FIG. 221 (C). , The next mode will be entered after the number of games determined at the start of the start mode has elapsed. On the other hand, when the transition from MAP1 to MAP12 while staying in the wake-up mode is performed in a game in which the number of remaining games until the end of the wake-up mode is 9 or more, as shown in FIG. 221 (B), the wake-up mode The number of games decided at the start will be shortened, and the game will move to the next mode.

<Playability in bonus state>
Next, with reference to FIG. 222, the flow of the game in the bonus state will be described. FIG. 222 (A) is a diagram showing a flow of games in a normal BB, and FIG. 222 (B) is a diagram showing a flow of games in a special BB.

As shown in FIG. 222 (A), during normal BB, ART lottery and counting of the number of white BARs are performed during each game. Normally, the ART lottery in BB is always won when the abbreviation "TBAR Lip" is determined as the internal winning combination, and is always non-winning when the other combination is determined as the internal winning combination. Further, the number of white BARs is counted when the abbreviations "SBAR rip" and "WBAR rip" are determined as the internal winning combination, and when the abbreviation "SBAR rip" is determined as the internal winning combination, the number of white BARs is 1. When the numbers are added and the abbreviation "WBAR Lip" is determined as the internal winning combination, the number of white BARs is added by 2.

Also, during normal BB, ART lottery is performed at the end of the bonus state. The ART lottery at the end is performed based on the number of white BARs normally counted in the BB. Basically, the larger the number of white BARs, the higher the probability of winning, and the number of white BARs is "5". If so, be sure to win. When the number of white BARs normally counted in the BB is "6" or more, the loop mode 4 having no continuation rate is given by the amount exceeding "5". For example, when the number of white BARs normally counted during BB is "7", two loop modes 4 are given.

When the normal BB ends, if the ART lottery is won, the game state shifts to the ART game state while the ART is being prepared, and if the ART lottery is not won, the game state is changed to the normal game state. The transition is made and a new cycle is started.

Further, as shown in FIG. 222 (B), the special BB is given one loop mode 3 at the start of the bonus state, and the number of white BARs is counted during each game in the special BB. The count of the number of white BARs in the special BB is performed when the abbreviations "SBAR rip", "WBAR rip" and "TBAR rip" are determined as the internal winning combination, and when the abbreviation "SBAR rip" is determined as the internal winning combination. , When the number of white BARs is added by 1 and the abbreviation "WBAR rip" is determined as the internal winning combination, the number of white BARs is added by 2 and when the abbreviation "TBAR rip" is determined as the internal winning combination, the number of white BARs is determined. Is added by 3. During the special BB, the loop mode 4 which does not have a continuation rate for the number of white BARs counted is given. For example, when the number of white BARs counted in the special BB is "7", seven loop modes 4 are given.

Since the special BB is given the loop mode 3 at the start of the bonus state, when the special BB ends, the game state shifts to the ART game state through the preparation for ART.

[ART lottery table at the end of BB]
FIG. 223 is an ART lottery table at the end of BB, which is usually used for ART lottery performed at the end of BB. The ART lottery table at the end of the BB defines the lottery value information about the lottery result of the ART lottery for each number of white BARs normally counted during the BB.

[Loop mode lottery table]
FIG. 224 (A) is a loop mode lottery table used for drawing which loop mode is to be given. The loop mode lottery table defines the lottery value information for each of the loop modes 0 to 3. In the pachislot machine 1, when loop modes 0 to 3 having a continuation rate are given, the loop mode lottery table is referred to and a lottery is made as to which loop mode is to be given.

Here, FIG. 224 (B) shows the relationship between the winning opportunity of the ART lottery and the stock to be granted. As shown in FIG. 224 (B), when the ART lottery at the start of the cycle in the normal game state is won, any of loop modes 0 to 3 having a continuation rate is given. In addition, when the ART lottery performed in each game during the cycle of the normal game state is won, if the loop mode having the continuation rate is not yet given (first hit), the loop mode 0 to having the continuation rate Any of 3 is given. On the other hand, if a loop mode having a continuation rate has already been granted at the time of winning the ART lottery performed in each game during the cycle (after winning), a loop mode 4 having no continuation rate is granted.

Further, when the abbreviation "TBAR lip" is determined as the internal winning combination in the normal BB, any of loop modes 0 to 3 having a continuation rate is given. Further, when the ART lottery based on the number of white BARs normally performed at the end of the BB is won, any of loop modes 0 to 3 having a continuation rate is given. It should be noted that, for the portion exceeding 5 of the number of white BARs normally counted in the BB, the loop mode 4 is given by the excess number.

Further, when the special BB is established, the loop mode 3 is given. The establishment of the special BB may mean that the abbreviation "SBB" is determined as the internal winning combination, and the combination of the symbols of the abbreviation "black BB" is displayed along the effective line. There may be. In addition, the loop mode 4 is given as many as the number of white BARs counted in the special BB.

Further, in any of the gaming states, when the abbreviation "middle-stage cherry" is determined as the internal winning combination, the loop mode 3 is given and three loop modes 4 are given. Further, as will be described later, when the ART lottery performed during the ART game state (normal ART or episode ART) is won, the loop mode 4 is given.

<Playability during ART game state>
Next, with reference to FIG. 225, the flow of the game during the ART game state (normal ART) will be described. As shown in FIG. 225 (A), in the normal ART, a continuous lottery based on the loop mode used for the current set is performed at the start of one set. If the continuous lottery is won, the loop mode is maintained without being consumed, and if the continuous lottery is not won, the loop mode is consumed. If the loop mode is consumed and the stock of the loop mode is exhausted at the end of the normal ART, the ART gaming state ends and the gaming state shifts to the normal gaming state.

Further, as shown in FIG. 225 (B), in the normal ART, EP points are drawn at the start of one set, and the drawn EP points are given. EP points are given 0 to 5 points per set, and during normal ART, the EP points given in each set are accumulated and managed. As a result, when the total is 4 points or less, the normal ART is performed based on the result of the continuous lottery, and when the total is 5 points or more, the episode ART is started after the end of one set of the normal ART. When the episode ART is started, the EP points are subtracted by 5.

Further, as shown in FIG. 225 (C), the ART lottery is normally performed during the ART, and when the ART lottery is won, the loop mode 4 is given. Normally, during ART, a high accuracy that makes it easy to win an ART lottery and a low accuracy that makes it difficult to win an ART lottery are provided, and the ART lottery is performed based on the current state (high accuracy / low accuracy).

<Various data tables used during ART game state>
Subsequently, various data tables used during the ART gaming state will be described with reference to FIGS. 226 to 230.

[High accuracy map lottery table]
FIG. 226 (A) is a high-accuracy map lottery table for drawing a high-accuracy map that defines the state (high-accuracy / low-accuracy) of the ART lottery during normal ART. The high-accuracy map lottery table defines lottery value information for each type of high-accuracy map. Here, FIG. 226 (B) is a diagram showing the contents of the high-accuracy map. As shown in FIG. 226 (B), the high accuracy map defines the number of sets of normal ARTs that use high accuracy as the ART lottery state. For example, it is stipulated that the high-accuracy map "Map 0" uses high accuracy during the 4th set of normal ART and low accuracy during the 1st to 3rd sets and 5th to 8th sets of normal ART. .. The state of the ART lottery remains unchanged during a set of normal ARTs.

In pachislot 1, the state of ART lottery for eight sets is determined in advance based on the high accuracy map, and high accuracy / low accuracy is set at the start of each set. The lottery timing of the high-accuracy map is the start of the normal ART of the 1, 9, 17 ... Set (that is, the 8n-7th set).

[Continuous lottery table]
FIG. 227 is a continuous lottery table used for continuous lottery usually performed at the start of setting ART. The continuous lottery table defines the lottery value information about the lottery result of the continuous lottery for each of the continuation modes having the continuation rate. If the continuous lottery is discontinued, the loop mode used for the continuous lottery is deleted, and conversely, if the continuous lottery is continued, the loop mode used for the continuous lottery is maintained.

[EP point lottery table]
FIG. 228 is an EP point lottery table used for drawing EP points normally given to each set of ART. The EP point lottery table defines the lottery value information about the lottery result of the EP points to be given. When loop mode 4 is used for the normal ART of this set, lottery is performed using the EP point lottery table, but any of loop modes 0 to 3 is used for the normal ART of this set. If it is used, the lottery using the EP point lottery table is performed only when the continuous lottery is continued, and when the continuous lottery is not continued, the EP points are not drawn and the points are always "0 points".

[ART game number lottery table]
FIG. 229 is an ART game number lottery table used for drawing the duration (ART game number) of the normal ART of this set. The ART game number lottery table defines information on the lottery value for the number of normal ART games of this set in association with the result of continuous lottery and the number of EP points given in this set. In the case of discontinuation in the continuous lottery at the start of the set, the number of normal ART games is determined by referring to the "discontinuation column", and in the case of continuation in the continuous lottery at the start of the set, in the "continuation column" The number of normal ART games is determined by referring to the data corresponding to the number of EP points given. When the loop mode 4 is used for the normal ART of this set, the number of games of the normal ART is determined by referring to the data corresponding to the number of EP points given in the "continuation column". ..

With reference to the ART game number lottery table, if the continuous lottery at the start of the set is not continued, "15 to 18 games" and "42 games" are not determined as the number of ART games, and the continuation at the start of the set is continued. Even if the lottery is continued, if the EP points given are "0 points", it can be seen that "15 to 18 games" are not determined as the number of ART games.

[ART lottery table and additional lottery table]
FIGS. 230 (A) and 230 (B) are ART lottery tables during ART used for ART lottery performed during the ART game state, and FIG. 230 (A) shows an ART lottery table during ART used during normal ART during low accuracy. (For low accuracy of normal ART), FIG. 230 (A) shows the ART lottery table during ART used during normal ART or episode ART during high accuracy (for high accuracy of normal ART or during episode ART). Is.

The ART lottery table during ART defines the lottery value information about the lottery result of the ART lottery for each internal winning combination and the current mode. When the ART lottery using the ART lottery table during ART is won, basically, one loop mode 4 is given. However, when the ART lottery using the ART lottery table during ART is won, if there is no loop mode 0 to 3 having a continuation rate, any of the loop modes 0 to 3 may be given.

In the ART lottery table during ART shown in FIGS. 230 (A) and 230 (B), when the abbreviation "middle cherry" is determined as the internal winning combination, the abbreviation is always non-winning. When the "middle cherry" is determined as the internal winning combination, one stock in loop mode 3 and one stock in loop mode 4 are obtained based on other processing different from the lottery processing using the ART lottery table during ART. Three will be granted.

Further, FIG. 230C is an additional lottery table used for adding one more loop mode 4 to be given when the ART lottery performed during the ART game state is won. The additional lottery table at the time of additional winning is referred to when the ART lottery using the ART lottery table during ART in FIGS. 230 (A) and 230 (B) is won, and whether or not to further add (double push) in the loop mode 4 is performed. Specify the lottery value information about the table. At the time of additional winning When the lottery using the additional lottery table is won, one loop mode 4 is further given in addition to the loop mode given by the ART lottery using the ART lottery table during ART.

<Explanation of operation of main control circuit>
Next, with reference to FIGS. 231 to 243, the contents of various processes executed by the main CPU 101 of the main control circuit 90 by using the program will be described. The same processing as that of the pachi-slot machine 1 of the first embodiment will be omitted or briefly described. For example, the power-on (reset interrupt) processing to the thumb check processing (non-standard) in FIGS. 64 to 80 are the same as those of the pachi-slot machine 1 of the first embodiment, and thus the description thereof will be omitted.

[Main processing of pachislot under the control of the main CPU]
First, the main process (main operation process) of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described with reference to FIG. 231.

First, the main CPU 101 performs a RAM initialization process (S2001). Next, the main CPU 101 performs medal acceptance / start check processing (S2002). Next, the main CPU 101 performs a random number acquisition process (S2003). These processes are basically the same as those of the pachislot machine 1 of the first embodiment.

Next, the main CPU 101 performs an internal lottery process (S2004). Next, the main CPU 101 performs a symbol setting process (S2005). These processes are basically the same as those of the pachislot machine 1 of the first embodiment, but the type of the winning combination determined as the internal winning combination and the RT that shifts when the winning combination related to the bonus is determined as the internal winning combination. The type of state and the like match the specifications of the pachi-slot machine 1 of the second embodiment. Further, in the internal lottery process of the pachislot machine 1 of the second embodiment, when the abbreviation "middle-stage cherry" is determined as the internal winning combination, one stock of the loop mode 3 and three stocks of the loop mode 4 are given. ..

Next, the main CPU 101 performs a start command generation / storage process (S2006). Next, the main CPU 101 performs the second interface board control process (S2007). These processes are basically the same as those of the pachislot machine 1 of the first embodiment.

Next, the main CPU 101 performs a state-specific control process (S2008). In this process, the main CPU 101 mainly performs a game start process (start process) according to the game state. The details of the state-specific control processing will be described later with reference to FIG. 232 described later.

Next, the main CPU 101 performs a reel stop initial setting process (S2009). Next, the main CPU 101 performs a reel rotation start process (S2010). Next, the main CPU 101 performs a reel rotation start command generation / storage process (S2011). Next, the main CPU 101 performs a pull-in priority storage process (S2012). Next, the main CPU 101 performs a winning search process (S2014). These processes are basically the same as those of the pachislot machine 1 of the first embodiment.

Next, the main CPU 101 performs a reel stop control process (S2013). Next, the main CPU 101 performs an illegal hit check process (S2015). Next, the main CPU 101 performs a winning check / medal payout process (S2016). These processes are basically the same as those of the pachislot machine 1 of the first embodiment.

Next, the main CPU 101 performs a BB check process (S2017). In this process, the main CPU 101 controls the operation and termination of the bonus state. The details of the BB check process will be described later with reference to FIG. 242 described later.

Next, the main CPU 101 performs an RT check process (S2018). In this process, the main CPU 101 performs RT state transition control based on the symbol combination stopped and displayed on the effective line. The details of the RT check process will be described later with reference to FIG. 243 described later.

[Control processing by state]
Subsequently, with reference to FIG. 232, the state-specific control processing of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described.

First, the main CPU 101 determines whether or not the gaming state is in the normal gaming state (S2031). When the gaming state is in the normal gaming state (YES), the main CPU 101 subsequently performs the normal middle start process (S2032). The details of this normal start processing will be described later with reference to FIG. 233 described later.

On the other hand, when the gaming state is not in the normal gaming state in S2031 (NO), the main CPU 101 determines whether or not the gaming state is preparing for ART (S2033). If the game state is in preparation for ART (YES), the main CPU 101 subsequently refers to the table in preparation for ART in FIG. 209 (C), performs an ART lottery in preparation for ART, and draws the ART. In the case of winning, one stock of loop mode 4 is given (S2034).

On the other hand, if the gaming state is not in ART preparation in S2033 (NO), the main CPU 101 determines whether or not the gaming state is in the ART gaming state (S2035). If the gaming state is in the ART gaming state (YES), the main CPU 101 subsequently performs a navigation set process (S2036). In this process, the main CPU 101 acquires and sets navigation data that informs the correct push order when the push order combination is determined as the internal winning combination. Subsequently, the main CPU 101 performs a start-time process during ART (S2037). The details of the start-time processing during ART will be described later with reference to FIG. 237 described later.

On the other hand, if the gaming state is not in the ART gaming state in S2035 (NO), the main CPU 101 determines whether or not the gaming state is in the inter-flag state (S2038). When the game state is in the inter-flag state (YES), the main CPU 101 subsequently performs the navigation set process (S2039). In this process, the main CPU 101 acquires and sets navigation data based on the current gaming state (whether or not it is in the ART gaming state).

In the pachislot machine 1 of the present embodiment, during the inter-flag state, the concept of the correct / incorrect push order is removed from the push order combination as described above, and the symbol combination at the time of the correct push order is always displayed. Stop control is to be performed. Therefore, it is not necessary to navigate the correct push order during the inter-flag state, but in pachislot 1, if the inter-flag state is entered during the ART game state, the push order combination or the like is subsequently used as the internal winning combination. When it is decided, the navigation of the push order is performed a predetermined number of times. It should be noted that the push order to be navigated is arbitrary and may be determined at random, or may be determined for each type of push order combination determined as the internal winning combination.

Further, the push order combination for navigating the push order during the inter-flag state may be specifically the internal winning combination "F_rip RT2_123" to "F_rip RT3_3rd" "F_1stB_1" to "F_3rdB_2". Alternatively, "F_normal lip" and "F_ALLB" may be added to these push order combinations. That is, in this navigation set process, the main CPU 101 refers to the internal lottery table in the inter-flag state shown in FIG. 180, and determines the internal winning combinations "F_normal lip" to "F_ALLB" together with the winning combination related to the bonus. In this case, the navigation data of the push order that is not originally needed is acquired and set.

As a result, when the state shifts to the inter-flag state during the ART game state, the mode of push order navigation can be matched before and after the shift, and the player can use the mode of push order navigation as the internal winning combination. It can be difficult to grasp what has been decided.

On the other hand, if the gaming state is not in the inter-flag state in S2038 (NO), the main CPU 101 determines whether or not the gaming state is in the bonus state (S2040). If the gaming state is in the bonus state (YES), the main CPU 101 subsequently performs the start-time processing during the bonus (S2041). The details of the start processing during the bonus will be described later with reference to FIG. 241 described later.

Following the processing of S2032, S203, S2037, S2039, S2041 or when the gaming state is not in the bonus state in S2040 (NO), the main CPU 101 subsequently performs other processing (S2042) and controls by state. End the process.

[Normal start processing]
Subsequently, with reference to FIG. 233, the normal middle start processing of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described.

First, the main CPU 101 determines whether or not the current game is at the start of the cycle (S2051). If it is at the start of the cycle (YES), the main CPU 101 subsequently performs an ART lottery at the start of the cycle (S2052) with reference to the ART lottery table at the start of the cycle (FIG. 206), and subsequently, this It is determined whether or not the ART lottery has been won (S2053).

If the ART lottery at the start of the cycle is won (YES), the main CPU 101 subsequently draws the loop mode with reference to the loop mode lottery table (FIG. 224 (A)), and selects the winning loop mode. Stock one (S2054). On the other hand, when the ART lottery at the start of the cycle is not won (NO), or following the process of S2054, the main CPU 101 refers to the cycle MAP lottery table (FIG. 207) and uses the cycle for the current cycle. The MAP is drawn and set (S2055).

Following the processing of S2055, or if it is not at the start of the cycle in S2051 (NO), the main CPU 101 subsequently performs the current game at the start of the start mode, the accept mode, the transfer mode, or the decision mode. It is determined whether or not there is (S2056). If the current game is at the start of the mode (YES), the main CPU 101 determines and sets the number of games in the mode (S2057). Specifically, at the start of the start mode, the accept mode, or the transfer mode, the main CPU 101 draws and sets one game number from 16 to 39 games with reference to the game number lottery table (FIG. 208). To do. Further, at the start of the decision mode, the main CPU 101 determines and sets 5 games as the number of games in the mode.

Following the processing of S2057, or when the current game is not at the start of the mode in S2056 (YES), the main CPU 101 subsequently performs the normal ART lottery processing (S2058) and the MAP transition processing (S2059). , And the mode transition process (S2060) are performed, and the normal middle start process is terminated. The details of the normal ART lottery process will be described later with reference to FIG. 234 described later, and the details of the MAP transition process will be described later with reference to FIG. 235 described later. Details will be described later with reference to FIG. 236 described later.

[Normal ART lottery processing]
Subsequently, with reference to FIG. 234, an ART lottery process during normal operation of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described.

First, the main CPU 101 performs an ART lottery based on the internal winning combination (S2071). In this process, when there is no stock in the loop mode, the main CPU 101 refers to the ART lottery table (for non-winning ART) during the cycle of FIG. 209 (A) and is based on the current mode and the internal winning combination. If there is a stock in the loop mode, the ART lottery is performed based on the internal winning combination with reference to the ART lottery table (for after the ART winning) during the cycle of FIG. 209 (B).

Subsequently, the main CPU 101 determines whether or not the ART lottery has been won (S2072). If the ART lottery is not won (NO), the main CPU 101 ends the ART lottery process during normal operation, while if the ART lottery is won (YES), the main CPU 101 subsequently terminates the ART lottery process. It is determined whether or not it is the first hit of the ART lottery (S2073). Specifically, the main CPU 101 determines that it is the first hit when it wins the ART lottery when there is no stock in the loop mode, and determines that it is not the first hit when it wins the ART lottery when there is stock in the loop mode. ..

At the time of the first hit (YES), the main CPU 101 subsequently refers to the loop mode lottery table (FIG. 224 (A)), draws the loop mode, stocks one winning loop mode (S2054), and normally The middle ART lottery process is completed. On the other hand, if it is not the first hit (NO), the main CPU 101 subsequently stocks one loop mode 4 (S2075) and ends the normal ART lottery process.

[MAP migration process]
Subsequently, with reference to FIG. 235, the MAP migration process of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described.

First, the main CPU 101 performs a transition lottery of the periodic MAP based on the internal winning combination (S2091). In this process, when there is no stock in the loop mode, the main CPU 101 depends on the current mode and the presence / absence of cycle continuation in the MAP transition lottery table (for when there is no stock in the loop mode) shown in FIGS. 210 to 213. With reference to the MAP transition lottery table, the transition lottery of the periodic MAP is performed based on the internal winning combination. If there is stock in the loop mode, the current mode in the transition lottery table (for when there is stock in the loop mode) in FIGS. 214 to 217 and the MAP transition according to the first hit / after the ART lottery. With reference to the lottery table, the transition lottery of the periodic MAP is performed based on the internal winning combination.

Subsequently, the main CPU 101 determines whether or not the transition lottery of the periodic MAP has been won (S2092). If the cycle MAP transition lottery is not won (NO), the main CPU 101 ends the MAP transition process, while if the cycle MAP transition lottery is won (YES), the main CPU 101 is Subsequently, the current cycle MAP is updated to the winning cycle MAP (S2093).

Subsequently, the main CPU 101 determines whether or not the mode shift is necessary (S2094). Specifically, the main CPU 101 determines whether or not the cycle MAP after updating in S2093 is a cycle MAP including the current mode, and if the cycle MAP does not include the current mode, it is necessary to shift to the mode. It is determined that the mode transition is not necessary when the current mode is included.

If there is no need for mode transition (NO), the main CPU 101 ends the MAP transition process, while if mode transition is required (YES), the main CPU 101 subsequently enters the current mode. It is determined whether or not the number of remaining games is 9 games or more (S2095). If the number of remaining games in the current mode is 8 games or less (NO), the main CPU 101 ends the MAP transition process, while if it is 9 games or more (YES), the main CPU 101 continues. Then, referring to the mode transition game number lottery table (FIG. 218), the mode transition game number is drawn, the remaining number of games in the current mode is updated to the lottered mode transition game number (S2096), and the MAP transition process is performed. To finish.

[Mode transition process]
Subsequently, the mode transition process of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described with reference to FIG. 236.

First, the main CPU 101 updates (subtracts 1) the number of remaining games in the current mode (S2111). Subsequently, the main CPU 101 determines whether or not the number of remaining games in the current mode has become 0 (S2112). If the number of remaining games in the current mode is not 0 (NO), the main CPU 101 ends the mode transition process, while the number of remaining games in the current mode is 0 (YES), the main The CPU 101 subsequently determines whether or not the cycle MAP has the next mode, that is, whether or not it is at the end of the cycle (S2113).

If the cycle MAP has the next mode (YES), it is not the end of the cycle, so the main CPU 101 subsequently sets the next mode based on the cycle MAP, and at the start of the winning mode in the next game. Is set (S2114). When this process is completed, the main CPU 101 ends the mode transition process.

On the other hand, if the cycle MAP does not have the next mode (NO), it is at the end of the cycle, so the main CPU 101 subsequently determines whether or not there is stock in the loop mode (S2115). If there is a loop mode stock (YES), the main CPU 101 subsequently sets the next game to be preparing for ART (S2116), and ends the mode transition process. On the other hand, when there is no stock in the loop mode (NO), the main CPU 101 subsequently sets the cycle start time in the next game (S2117), and ends the mode transition process.

[Processing at start during ART]
Subsequently, with reference to FIG. 237, the process at the start of ART of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described.

First, the main CPU 101 determines whether or not it is normally in ART (S2131). When the normal ART is in progress (YES), the main CPU 101 subsequently performs the normal ART in-process described later in FIGS. 238 and 239 (S2132), and ends the ART in-start process. On the other hand, when it is not normally in ART (YES), since it is in episode ART, the main CPU 101 subsequently performs the episode ART in-process (S2133) described later in FIG. 240, and ends the ART in-start process. To do.

[Normal ART processing]
Subsequently, with reference to FIG. 238, the processing during normal ART of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described.

First, the main CPU 101 determines whether or not it is at the start of one set of normal ART (that is, the first game of each set of normal ART) (S2151). When it is the start of the normal ART (YES), the main CPU 101 subsequently performs the loop mode setting process (S2152). In this process, the main CPU 101 determines the loop mode to be set from the stocked loop modes according to the following rules.

(1) When the stock of the loop mode 4 is 1 or more, the loop mode 4 is set as the loop mode used for the normal ART of this set.
(2) If there is no stock of loop mode 4 and this set is the first set in the ART gaming state, the loop mode having the smallest value among the stocked loop modes 0 to 3 is selected. Set as the loop mode used for normal ART of this set.

(3) If there is no stock of loop mode 4 and loop mode 0 is used in the normal ART of the previous set, it is used in the latest set of the stocked loop modes 0 to 3 in the past. The loop mode that was used is set as the loop mode used for the normal ART of this set. However, if the loop mode used in the past set is not stocked, the loop mode with the smallest value among the stocked loop modes 0 to 3 is set as the loop mode used for the normal ART of this set. set.

(4) If there is no stock of loop mode 4 and the loop mode used in the normal ART of the previous set is other than loop mode 4, if the normal ART of the previous set is continued, the previous set When the loop mode used in the set is set as the loop mode used for the normal ART of this set and the normal ART of the previous set is discontinued, the smallest value among the stocked loop modes 0 to 3 is set. The loop mode is set as the loop mode used for the normal ART of this set.

Subsequently, the main CPU 101 determines whether or not the high-accuracy map is set (S2153). Specifically, the main CPU 101 determines that the high-accuracy map is not set when the normal ART of the 1, 9, 17 ... Set is started, and is high in other cases. Determine that the probability map is set.

If the high-accuracy map is not set (NO), the main CPU 101 draws the high-accuracy map with reference to the high-accuracy map lottery table (FIG. 226 (A)), and the high-accuracy map determined by the lottery. Is set (S2154).

Following the processing of S2154 or when the high accuracy map is set in S2153 (YES), the main CPU 101 continues based on the loop mode set in S2152 with reference to the continuous lottery table (FIG. 227). A lottery is performed (S2155). If loop modes 0 to 3 having a continuation rate are set in the normal ART of this set, the loop mode 4 having a continuation rate will continue with a probability according to the loop mode. If it is set, it will always be discontinued. Subsequently, the main CPU 101 determines whether or not the continuous lottery has been discontinued (S2156). If the continuous lottery is not continued (YES), the main CPU 101 erases the loop mode set in S2152 (S2157).

Following the processing of S2157, or when the continuous lottery is won in S2156 (NO), the main CPU 101 subsequently refers to the EP point lottery table (FIG. 228) to determine whether or not to continue. Based on this, EP points are drawn (S2158). Here, when the continuous lottery of S2155 is performed using the loop modes 0 to 3, EP points of 0 to 5 points are determined when the continuous lottery is won, and the continuous lottery is not won. In that case, 0 point EP points are always determined. Further, when the continuous lottery of S2155 is performed using the loop mode 4, EP points of 0 to 5 points are determined.

Subsequently, the main CPU 101 draws and sets the number of ART games of this set based on the presence / absence of continuation and the EP points with reference to the ART game number lottery table (FIG. 229) (S2159). Subsequently, the main CPU 101 sets high accuracy or low accuracy as the ART lottery state of this set based on the high accuracy MAP (S2160). Subsequently, the main CPU 101 accumulates and stores the EP points determined in S2158 (S2161).

Following the processing of S2161, or if it is not the start of one set of normal ART in S2151 (NO), the main CPU 101 subsequently enters the ART lottery state (high accuracy / low accuracy) of this set. With reference to the corresponding ART lottery table during ART (FIGS. 230 (A) or (B)), the ART lottery is performed based on the internal winning combination (S2171). Subsequently, the main CPU 101 determines whether or not the ART lottery has been won (S2172).

If the ART lottery is won (YES), the main CPU 101 subsequently determines whether or not there is stock in loop modes 0 to 3 (S2173). If there is no stock in loop modes 0 to 3 (NO), the main CPU 101 grants one stock in loop mode erased at the start of this set (S2174). On the other hand, when there is stock in loop modes 0 to 3 (YES), the main CPU 101 grants one stock in loop mode 4 (S2175).

Following the processing of S2174 or S2175, the main CPU 101 refers to the additional lottery table (FIG. 230 (C)) at the time of the additional winning, and further performs the additional lottery processing at the time of the additional winning (S2176), and subsequently, this It is determined whether or not the additional lottery process has been won (S2177). If the additional lottery process is won (YES), the main CPU 101 subsequently grants one stock of loop mode 4 (S2178).

Following the process of S2178, in the case of non-winning in S2177 (NO) or in the case of non-winning in S2172 (NO), the main CPU 101 updates (subtracts 1) the number of ART games (S2179). Subsequently, the main CPU 101 determines whether or not the number of ART games is 0 (S2180). If the number of ART games is not 0 (NO), the main CPU 101 normally ends the process during ART.

On the other hand, when the number of ART games is 0 (YES), the main CPU 101 subsequently determines whether or not there is stock in the loop mode (S2181). When there is no stock in the loop mode (NO), the main CPU 101 subsequently sets the cycle start time of the normal game state in the next game (S2182), clears the EP point, and performs normal ART processing. finish.

On the other hand, if there is a loop mode stock (YES), the main CPU 101 subsequently determines whether or not the cumulative EP points are 5 points or more (S2183). If the cumulative EP points are 5 points or more (YES), the main CPU 101 subsequently subtracts the cumulative EP points by 5 (S2184) and sets the start time of the episode ART in the next game (S2185). ), Normally, the process during ART is terminated.

On the other hand, when the EP points are less than 5 points (NO), the main CPU 101 subsequently sets the start time of the normal ART in the next game (S2186), and ends the processing during the normal ART.

[Processing during episode ART]
Subsequently, with reference to FIG. 240, the processing during the episode ART of the pachislot machine 1 executed under the control of the main CPU 101 will be described.

First, the main CPU 101 determines whether or not it is the start of the episode ART (S2191). If it is the start of the episode ART (YES), the main CPU 101 subsequently sets 30 as the number of EP games (S2192).

Following the processing of S2192, or if it is not at the start of the episode ART in S2191 (NO), the main CPU 101 is the ART lottery table during the ART of FIG. 230 (B) (usually the high accuracy of the ART or the episode ART). With reference to (intermediate use), an ART lottery is performed based on the internal winning combination (S2193), and it is determined whether or not the winning is won (S2194).

If the ART lottery is won, the main CPU 101 subsequently grants one stock of loop mode 4 (S2195). Subsequently, the main CPU 101 refers to the additional lottery table (FIG. 230 (C)) at the time of the additional winning, and further performs the additional lottery processing at the time of the additional winning (S2196), and subsequently, the additional lottery processing is performed. It is determined whether or not the winning is achieved (S2197). If the additional lottery process is won (YES), the main CPU 101 subsequently grants one stock of loop mode 4 (S2198).

Following the process of S2198, if the additional lottery process is not won in S2197 (NO), or if the ART lottery is not won in S2194 (NO), the main CPU 101 updates the number of EP games (1). Subtract) (S2199). Subsequently, the main CPU 101 determines whether or not the number of EP games is 0 (S2200), and if the number of EP games is not 0 (NO), ends the processing during the episode ART. On the other hand, when the number of EP games is 0 (YES), the main CPU 101 subsequently sets the start time of the normal ART in the next game (S2201), and ends the processing during the episode ART.

[Processing at start during bonus]
Subsequently, the process at the start of the bonus of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described with reference to FIG. 241.

First, the main CPU 101 determines whether or not it is normally in the BB (S2211). When normally in BB (YES), the main CPU 101 subsequently determines whether or not the abbreviation "TBAR lip" has been determined as the internal winning combination (S2212). When the abbreviation "TBAR lip" is determined as the internal winning combination (YES), the main CPU 101 refers to the loop mode lottery table (FIG. 224 (A)) and has a continuation rate of loop modes 0 to 3. One loop mode is drawn from among them, and one stock of the loop mode is given (S2213).

Following the processing of S2213, if the abbreviation "TBAR lip" is not determined as the internal winning combination in S2212 (NO), or if it is not in the normal BB in S2211 (NO), the main CPU 101 has the internal winning combination. The number of white BARs is counted based on (S2214), and the processing at the start during the bonus is terminated. Specifically, during normal BB, the main CPU 101 adds 1 to the number of white BARs when the abbreviation "SBAR lip" is determined as the internal winning combination, and the abbreviation "WBAR lip" is determined as the internal winning combination. Add 2 to the number of white BARs. Further, during the special BB, the main CPU 101 adds 1 to the number of white BARs when the abbreviation "SBAR lip" is determined as the internal winning combination, and the number of white BARs when the abbreviation "WBAR lip" is determined as the internal winning combination. 2 is added, and when the abbreviation "TBAR Lip" is determined as the internal winning combination, the number of white BARs is added by 3.

[BB check process]
Subsequently, the BB check process of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described with reference to FIG. 242.

First, the main CPU 101 determines whether or not the symbol combination of the abbreviation "black BB" is displayed along the effective line (S2231). When the symbol combination of the abbreviation "black BB" is displayed (YES), the main CPU 101 subsequently grants one stock of loop mode 3 and sets a special BB in the next game (S2322). , Ends the BB check process.

On the other hand, when the symbol combination of the abbreviation "black BB" is not displayed (NO), the main CPU 101 subsequently displays the symbol combination of the abbreviation "red BB" or "blue BB" along the valid line. It is determined whether or not it is (S2233). When the symbol combination of the abbreviation "red BB" or "blue BB" is displayed (YES), the main CPU 101 subsequently sets the normal BB in the next game (S2234), and ends the BB check process. ..

On the other hand, when the symbol combination of the abbreviations "red BB" and "blue BB" is not displayed (NO), the main CPU 101 subsequently changes the current gaming state to the bonus state, that is, during normal BB or special. It is determined whether or not it is in BB (S2235). If the current gaming state is not in the bonus state (NO), the main CPU 101 ends the BB check process.

On the other hand, when the current gaming state is in the bonus state (YES), the main CPU 101 determines whether or not the number of medals paid out during the bonus state exceeds the specified number of medals. (S2236). As described above, in the present embodiment, the specified number of sheets in the normal BB is "297 sheets", and the specified number of sheets in the special BB is "27 sheets". If the number of payouts does not exceed the specified number (NO), the main CPU 101 ends the BB check process.

On the other hand, when the number of payouts exceeds the specified number (YES), the main CPU 101 subsequently performs an ART lottery process based on the number of white BARs in the bonus state (S2237). Specifically, during normal BB, the main CPU 101 refers to the ART lottery table at the end of BB (FIG. 223), performs an ART lottery based on the number of white BARs, and wins the ART lottery. The type of loop mode to be assigned is determined with reference to the loop mode lottery table (FIG. 224 (A)). Further, when the number of white BARs normally counted in the BB is "6" or more, the main CPU 101 imparts a loop mode 4 having no continuation rate by the amount exceeding "5". Further, during the special BB, the main CPU 101 imparts a loop mode 4 having no continuation rate for the number of white BARs counted in the special BB.

Subsequently, the main CPU 101 updates the number of stocks in various loop modes based on the result of the ART lottery process in S2237 (S2238). Subsequently, the main CPU 101 determines whether or not there is stock in the loop mode (S2239). If there is a stock in the loop mode (YES), the main CPU 101 subsequently sets the next game to be preparing for ART (S2240), and ends the BB check process. On the other hand, when there is no stock in the loop mode (NO), the main CPU 101 subsequently sets the cycle start time of the normal game state in the next game (S2241), and ends the BB check process.

[RT check processing]
Subsequently, with reference to FIG. 243, the RT check process of the pachi-slot machine 1 executed under the control of the main CPU 101 will be described.

First, the main CPU 101 performs an RT state transition process (S2251). In this process, the main CPU 101 shifts the RT state according to the shift conditions shown in FIG. 178. Subsequently, the main CPU 101 determines whether or not the RT state after the RT state transition process is performed is the RT3 state (S2252). If it is not in the RT3 state (NO), the main CPU 101 ends the RT check process.

On the other hand, in the case of the RT3 state (YES), the main CPU 101 subsequently determines whether or not the current gaming state is preparing for ART (S2253). If the ART is not being prepared (NO), the main CPU 101 ends the RT check process, while if the ART is being prepared (YES), the main CPU 101 subsequently performs a normal ART in the next game. The start time is set (S2254), and the RT check process ends.

<Control peculiar to pachislot 1>
The playability of the pachi-slot machine 1 of the present embodiment has been described above. Subsequently, the control peculiar to the pachi-slot machine 1 of the present embodiment will be described individually.

[ART start timing control]
In a pachislot machine having an ART function, when the ART right is granted, the game state is changed to the ART preparation after a predetermined number of games have elapsed, and the RT state is changed to the high RT state during the ART preparation. By doing so, the ART game state is started. Hereinafter, the start timing of the ART gaming state in the pachi-slot machine 1 of the present embodiment will be described with reference to FIG. 244.

The predetermined number of games after the right of ART is granted is, for example, in the pachislot machine 1 of the present embodiment, a game after winning an ART lottery during a cycle until the end of the cycle. In the case of other pachislot machines, the number of games played during the precursory period after the ART right is granted until the notification that the ART right has been granted is the predetermined number of times after the ART right is granted. It can be said that it is a game of.

Here, in recent pachislot machines that do not have a push order penalty during non-ART, depending on the player's stop operation, it may shift to a high RT state during non-ART, and ART remains in a high RT state. May transition during preparation. FIG. 244 (A) is a diagram showing the start timing of the ART gaming state when the RT state of the timing shifted during ART preparation is the low RT state, and FIGS. 244 (B) and 244 (C) are ART. FIG. 244 (C) is a diagram showing the start timing of the ART gaming state when the RT state of the timing shifted during preparation is the high RT state, and FIG. 244 (C) shows the start of the ART gaming state in the pachislot machine 1 of the present embodiment. The timing is shown, and FIG. 244 (B) shows the start timing of the ART gaming state for comparison with the pachislot machine 1 of the present embodiment.

As shown in FIG. 244 (A), in the pachislot machine 1, when the RT state is other than the RT3 state (low RT state) at the end of the cycle, the main control circuit 90 changes the gaming state to the normal gaming state at the end of the cycle. Transition from to during ART preparation. In pachislot 1 (main control circuit 90 and sub control circuit 200), navigation is performed to shift the RT state to the RT3 state during the ART preparation, and when the RT state shifts to the RT3 state during the ART preparation, then the main control circuit 1 is used. The control circuit 90 shifts the gaming state from the ART preparation to the ART gaming state.

Further, the main control circuit 90 sends a signal indicating that the current gaming state is the ART gaming state via the external centralized terminal plate 47 at the timing when the gaming state shifts to the ART gaming state, such as a data counter or a hall computer. Output to external devices such as. As a result, even on the external device side, it is possible to grasp the exact timing at which the pachislot 1 shifts to the ART gaming state.

On the other hand, as shown in FIGS. 244 (B) and 244 (C), the RT state may already be the RT3 state at the end of the cycle. In the comparative example of FIG. 244 (B), the gaming state is changed from the normal gaming state to the ART preparation at the end of the cycle, and during the ART preparation, the RT state is changed to a state other than the RT3 state, and then RT. We are navigating to shift the state to the RT3 state. Then, as a result of this navigation, if the RT state shifts to the RT3 state during the ART preparation, then the game state shifts from the ART preparation to the ART gaming state.

Here, in the comparative example of FIG. 244 (B), what was already in the high RT state at the end of the cycle is once dropped to the low RT state during ART preparation and then promoted to the high RT state again. , The game from falling to the low RT state to promotion to the high RT state will be prolonged, and the game being prepared for ART will be delayed.

Therefore, in the pachi-slot machine 1 of the present embodiment, as shown in FIG. 244 (C), when the RT state is already the RT3 state (high RT state) at the end of the cycle, the main control circuit 90 ends the cycle. As a result, the gaming state is directly changed from the normal gaming state to the ART gaming state. As a result, in the pachi-slot machine 1 of the present embodiment, the ART game state can be started from the timing when the cycle of winning the ART lottery ends, so that the game being prepared for ART may be delayed as in the comparative example. Absent.

Further, the main control circuit 90 outputs a signal indicating that the current gaming state is the ART gaming state to the external device via the external centralized terminal plate 47 at the timing when the gaming state shifts to the ART gaming state. To do. As a result, even on the external device side, it is possible to grasp the exact timing at which the pachislot 1 shifts to the ART gaming state.

[ART end timing control]
Subsequently, with reference to FIG. 245, the output timing of the external signal at the end of the ART gaming state in the pachi-slot machine 1 of the present embodiment will be described. In a pachislot machine having an ART function, when the final game in the ART game state ends, the ART game state ends, and the next game shifts to the normal game state. In the pachi-slot machine 1 of the present embodiment, the output timing of the external signal when the ART gaming state ends is different from that of the conventional pachi-slot machine.

The output pattern A of FIG. 245 (A) is the output timing (comparative example) of the external signal at the end of the ART gaming state in the conventional pachislot machine, and the output pattern B of FIG. 245 (B) is the pachislot machine of the present embodiment. This is the output timing of the external signal at the end of the ART gaming state in 1.

In the output pattern A (comparative example) of FIG. 245 (A), the main control circuit 90 is in the ART gaming state in the current gaming state with respect to the external device while the final game in the ART gaming state is being performed. When the final game is completed (for example, when the operation of the stop button accompanying the third stop operation is OFF), a signal indicating that the current game state is not the ART game state is output to the external device. It is outputting.

When an external signal is output as in the output pattern A in this way, as shown in FIG. 245 (B), the data counter displays that the player is currently in the ART game state during the final game. When the final game is completed, the display indicating that the game is in the ART game state disappears.

Here, in pachislot machines that manage the duration of an ART gaming state based on a continuation rate or the like, there is also known a gaming machine that performs a so-called revival effect in which the ART gaming state is pretended to end and then continued. It should be noted that the revival effect is, for example, an effect at the time of continuation after making it appear that the ART game state ends by performing a non-continuation effect even though the continuation of the ART game state is internally determined. Is to do. Such a revival effect may be performed, for example, at an arbitrary timing during the apparent final game in the ART game state, or may be performed in accordance with the start operation of the next game of the apparent final game.

When the revival effect is performed according to the start operation of the next game of the apparent final game, it is confirmed that the ART game state will continue inside the pachislot, so at the end of the apparent final game Even if there is, a signal indicating that the current game state is the ART game state is output to the external device, and as a result, on the data counter, the operation to start the next game after the apparent final game is performed. It is displayed that the ART game state is in progress until the above is performed.

On the other hand, when the revival effect is not performed, the ART game state is terminated internally in the game machine, so that when an external signal is output as in the output pattern A (comparative example), the final game is completed. At that point, the display of the data counter is switched from the ART game state to the non-ART game state, so that it can be seen from the data counter display that the revival effect is not performed according to the start operation of the next game.

Therefore, in the pachi-slot machine 1 of the present embodiment, when the start operation of the next game of the final game in the ART game state is detected as in the output pattern B of FIG. 245 (A), the current game is played with respect to the external device. A signal indicating that the state is not the ART gaming state is output. Specifically, in the output pattern B, the main control circuit 90 outputs a signal indicating that the current gaming state is the ART gaming state to the external device at the timing when the final game in the ART gaming state is completed. After that, when the start operation of the next game is detected, a signal indicating that the current game state is not the ART game state is output to the external device.

When an external signal is output as in the output pattern B in this way, as shown in FIG. 245 (B), the data counter waits until the start operation of the next game is detected even after the final game is completed. A display indicating that the ART gaming state is currently in progress will be performed. As a result, the player cannot determine whether or not the revival effect is performed until the start operation of the next game is performed, and the expectation is maintained from the end of the final game to the start of the next game. be able to.

It should be noted that the control of the production surface is arbitrary. Normally, the production screen is different between the ART game state and the non-ART state, and if the revival effect is not performed, the effect screen in the ART game state returns to the non-ART effect screen. On the contrary, when the revival effect is performed, the effect screen during the ART game state continues.

As a control of the production surface when the revival effect is not performed, for example, an end screen for displaying the number of medals won and the number of continuous games in the ART game state due to the third stop operation of the final game is displayed, and then the next The production screen during non-ART may be displayed along with the start operation of the game, and the end screen is not displayed at the time of the third stop operation of the final game, and then the start operation of the next game is performed. Along with this, the end screen may be displayed, and the effect screen during non-ART may be displayed at the timing when any of the first stop operation to the third stop operation of the game is performed.

On the other hand, as a control of the production side when the revival effect is not performed, for example, an end screen for displaying the number of medals won and the number of continuous games during the ART game state is displayed in association with the third stop operation of the apparent final game. After that, when the start operation of the next game is performed, a predetermined effect of reversing from discontinuation to continuation may be performed, and the effect screen during the ART game state may be displayed. In addition, the effect screen during non-ART is displayed in accordance with the start operation of the next game, and then, at any of the timings of the first stop operation to the third stop operation, the discontinuation is reversed to the continuation. It is also possible to perform the effect of and display the effect screen during the ART game state. In addition, the end screen is not displayed at the time of the third stop operation of the apparent final game, and after that, a predetermined effect of reversing from discontinuity to continuation is performed according to the start operation of the next game, and the ART game state is in progress. It may be possible to display the effect screen of. In addition, the end screen is not displayed at the time of the third stop operation of the apparent final game, and then the end screen is displayed with the start operation of the next game, and then the first stop operation to the third stop operation. It is also possible to perform a predetermined effect of reversing from discontinuation to continuation at the timing when any of the above is performed, and display the effect screen during the ART gaming state.

Further, in the examples shown in FIGS. 244 and 245, ON of the external signal indicates the ART gaming state and OFF indicates the non-ART, but conversely, OFF indicates the ART gaming state and ON indicates the non-ART. May be indicated. In this case, the above-mentioned control may be appropriately changed (opposite) according to the content indicated by the external signal.

[Production stage when the power is turned on]
As described above, in the pachislot machine 1, since the production is performed using the production stage according to the mode, the player can grasp the current mode from the production stage. Here, when clearing (initializing) the information related to the game at the time of power failure, the cycle MAP is newly determined after the power is turned on, and as a result, the start mode basically corresponds to the start mode, which is the initial mode. Although the production will be performed using the stage, if the information about the game at the time of power failure is not initialized, the mode at the time of power failure will be set as it is after the power is turned on, so skip the start stage and accept the stage. The game may start from such as. For example, when the setting is changed, the information about the game is usually initialized. Therefore, if the production stage after the power is turned on is other than the starting stage, the setting may not be changed. It can be inferred that the sex is high.

Therefore, in the pachi-slot machine 1 of the present embodiment, in the first cycle after the power is turned on, the cycle MAP on the main (main control circuit 90) side is converted on the sub (sub control circuit 200) side to perform the effect. .. More specifically, the sub-control circuit 200 starts the production stage from the starting stage for the first cycle after the power is turned on, regardless of the mode on the main side.

FIG. 246 (A) is a diagram showing the relationship between the mode on the main side when the power is turned on and the periodic MAP on the sub side. Since the start mode is a mode used only at the start of the cycle, if the mode on the main side at the time of power-on is the start mode, the sub side does not convert the cycle MAP and the main side and the sub side. The effect is performed using the periodic MAP and the mode that match with.

On the other hand, when the mode on the main side when the power is turned on is the acceptance mode, it will be known that the information about the game has not been cleared if the game has started from the acceptance stage, so the sub-control circuit 200 is the main. Convert the side period MAP. Specifically, the sub-control circuit 200 converts the periodic MAP on the main side into a periodic MAP in which the portions constituting the start mode and the accept mode are replaced with the start mode. For example, the sub-control circuit 200 converts MAP3 (start mode and accept mode) to MAP1 (start mode), and converts MAP15 (start mode, accept mode, transfer mode and decision mode) to MAP13 (start mode, transfer mode). Convert to mode and decision mode).

Similarly, when the mode on the main side at the time of turning on the power is the rotation mode, the sub control circuit 200 converts the period MAP on the main side. Specifically, the sub-control circuit 200 converts the portion of the main-side periodic MAP that constitutes the activation mode to the rotation mode into a periodic MAP in which the portion constituting the activation mode is replaced with the activation mode. For example, the sub-control circuit 200 converts MAP7 (start mode, acceptance mode and transfer mode) to MAP1 (origin mode), and converts MAP13 (initiation mode, transfer mode and determination mode) to MAP9 (initiation mode and determination mode). Mode).

Since the duration of the decision mode is as short as 5 games, in the present embodiment, even if the mode on the main side when the power is turned on is the decision mode, the cycle MAP is not converted on the sub side and the main side is not converted. The effect is performed using the periodic MAP and the mode that match with the sub side. Of course, even in the case of the decision mode, the period MAP on the main side may be converted on the sub side.

Subsequently, with reference to FIGS. 246 (B) and 246 (C), the relationship between the main mode and the sub mode when the power is turned on will be described. FIG. 246 (B) is a diagram showing the relationship between the mode on the main side and the mode on the sub side when the power is turned on when MAP3 is used as the period MAP on the main side. Further, the pattern P1 in FIG. 246 (B) shows an example of a pattern when the main mode at the time of power-on is the start mode, and the pattern P2 shows the case where the main mode at the time of power-on is the accept mode. An example of the pattern of is shown.

When the mode on the main side at the time of power-on is the start mode as in pattern P1, the cycle MAP and mode that match between the main side and the sub side are used on the sub side without converting the cycle MAP. It will be. Therefore, the sub side also starts from the start mode first, and when the remaining number of games in the start mode is exhausted, it then shifts to the accept mode based on MAP3.

As a result, in the pattern P1, the sub-control circuit 200 performs an effect using the start stage according to the start mode when the power is turned on, and then when the mode shifts from the start mode to the acceptance mode, the acceptance stage corresponding to the acceptance mode is used. It will be the production that was there.

On the other hand, when the mode on the main side at the time of turning on the power is the acceptance mode as in the pattern P2, the cycle MAP is converted from MAP3 to MAP1 on the sub side. As a result, while the main side is playing a game using the MAP3 acceptance mode, the sub side is playing a game using the MAP1 start mode, and then the number of remaining games in the main side acceptance mode is increased. Once digested, this cycle ends and the next cycle begins.

As a result, in the pattern P2, although the acceptance mode is used on the main side, the sub-control circuit 200 uses the activation stage according to the activation mode instead of the acceptance stage according to the acceptance mode when the power is turned on. Do. As a result, the mode and the production stage do not match, but it is not possible to determine whether or not the information related to the game has been initialized (whether or not the setting has been changed) from the production stage.

Subsequently, FIG. 246 (C) is a diagram showing the relationship between the mode on the main side and the mode on the sub side when the power is turned on when the MAP 15 is used as the period MAP on the main side. Further, the pattern P3 in FIG. 246 (C) shows a pattern example when the main mode at the time of power-on is the start mode, and the pattern P4 shows the case where the main mode at the time of power-on is the accept mode. Pattern P5 shows a pattern example when the main mode at power-on is the rotation mode, and pattern P6 shows a pattern when the main mode at power-on is the decision mode. An example is shown.

In the pattern P3, since the mode on the main side when the power is turned on is the start mode, the main side and the sub side do not convert the period MAP on the sub side as in the pattern P1 in FIG. 246 (B). The period MAP and mode that match in will be used. As a result, in the pattern P1, the sub-control circuit 200 performs an effect using the start stage according to the start mode when the power is turned on, and then when the mode shifts from the start mode to the acceptance mode, the acceptance stage corresponding to the acceptance mode is used. It will be the production that was there.

Further, in the pattern P4, since the mode on the main side when the power is turned on is the acceptance mode, the cycle MAP is converted from MAP15 to MAP13 on the sub side. As a result, while the main side is playing the game using the acceptance mode of MAP15, the sub side is playing the game using the raising mode of MAP13. Further, since the sub-control circuit 200 performs the effect using the start stage according to the start mode instead of the reception stage according to the reception mode on the main side when the power is turned on, has the information related to the game been initialized from the production stage? It becomes impossible to determine whether or not.

In the pattern P4, when the remaining number of games in the accept mode on the main side is exhausted, the mode shifts to the turning mode according to MAP15 on the main side and MAP13 on the sub side, and the main side and the sub side The modes will match. Further, the sub-control circuit 200 will perform the effect by using the rotation stage according to the rotation mode as the mode shifts to the rotation mode. Here, in the pachi-slot machine 1, the stage switching effect is performed when the effect stage is switched (see FIG. 205 (E)), but when the mode is skipped and the mode is changed as described above, the sub-control circuit 200 sets the sub-control circuit 200. A special stage switching effect that is different from the normal stage switching effect is performed. In the case of the pattern P4, the sub-control circuit 200 performs a special stage switching effect because the receiving stage is skipped and the stage is switched from the starting stage to the turning stage in terms of appearance from the effect.

Further, in the pattern P5, since the mode on the main side when the power is turned on is the rotation mode, the period MAP is converted from MAP15 to MAP9 on the sub side. As a result, while the main side is playing the game using the rolling mode of MAP15, the sub side is playing the game using the raising mode of MAP9. Further, since the sub-control circuit 200 performs the effect using the start stage according to the start mode instead of the turn stage according to the turn mode on the main side when the power is turned on, has the information related to the game been initialized from the effect stage? It becomes impossible to determine whether or not.

In the pattern P5, when the remaining number of games in the turning mode on the main side is exhausted, the mode shifts to the decision mode according to MAP15 on the main side and MAP9 on the sub side, and the main side and the sub side The modes will match. Further, the sub-control circuit 200 performs the effect by using the change stage according to the decision mode as the mode shifts to the decision mode. Even in this case, the acceptance stage and the change stage also appear to be from the effect. The sub-control circuit 200 performs a special stage switching effect because the start stage is switched to the final stage by skipping.

Further, in the pattern P6, since the mode on the main side at the time of turning on the power is the determination mode, the period MAP and the mode that match between the main side and the sub side are used without converting the period MAP on the sub side. It will be. As a result, in the pattern P6, the sub-control circuit 200 performs an effect using the decision stage according to the decision mode when the power is turned on, and after that, when the remaining number of games in the decision mode is exhausted, various types associated with the end of the cycle Processing will be performed.

As described above, in the pachislot machine 1 of the present embodiment, when the main mode at the time of turning on the power is the acceptance mode or the turning mode, the starting stage is used as the effect stage after the power is turned on, so that information on the game from the effect stage can be used. Makes it difficult to determine whether or not has been initialized. Here, since the duration of the start mode, the accept mode, and the transfer mode is between 16 and 39 games, the mode on the main side at the time of turning on the power is the accept mode, and the number of remaining games in the accept mode is the continuation. If it is shorter than the minimum number of games in the period (16 games), the production stage is switched in a short period of time, and as a result, it can be determined from the timing of switching the production stage whether or not the information related to the game has been initialized. There is a possibility that it will end up.

Therefore, the type of the cycle MAP to be converted on the sub side may be different according to the number of remaining games in the mode on the main side when the power is turned on. FIG. 247 (A) is a diagram showing another example of the mode on the main side when the power is turned on and the periodic MAP on the sub side.

When the mode on the main side when the power is turned on is the acceptance mode and the number of remaining games in the acceptance mode is 16 games or more, the mode (directing stage) is not switched in a short period of time, so that the sub-control circuit 200 , The part constituting the start mode and the accept mode in the cycle MAP on the main side is converted into the cycle MAP in which the start mode is replaced. For example, the sub-control circuit 200 converts MAP3 (start mode and accept mode) to MAP1 (start mode), and converts MAP15 (start mode, accept mode, transfer mode and decision mode) to MAP13 (start mode, transfer mode). Convert to mode and decision mode).

On the other hand, if the mode on the main side when the power is turned on is the acceptance mode and the number of remaining games in the acceptance mode is less than 16 games, the mode (directing stage) will be switched in a short period of time, so that the sub-control The circuit 200 converts the portion that constitutes the start mode and the accept mode in the cycle MAP on the main side, and the cycle MAP that replaces the mode that shifts to the next mode after the accept mode in the cycle MAP with the start mode. For example, the sub-control circuit 200 converts MAP3 (starting mode and accepting mode) to MAP1 (starting mode), and converts MAP15 (starting mode, accepting mode, turning mode and decision mode) to MAP9 (starting mode and decision mode). Mode).

Subsequently, with reference to FIG. 247 (B), the relationship between the mode on the main side and the mode on the sub side when the power is turned on will be described. FIG. 247 (B) is a diagram showing the relationship between the mode on the main side and the mode on the sub side when the power is turned on when the MAP 15 is used as the period MAP on the main side, and is a pattern in FIG. 247 (B). P11 shows a pattern example in which the mode on the main side at the time of power-on is the acceptance mode and the number of remaining games in the acceptance mode is 16 games or more, and pattern P12 is the mode on the main side at the time of power-on. An example of a pattern in the case where the mode is the acceptance mode and the number of remaining games in the acceptance mode is less than 16 games is shown.

The flow of the pattern P11 is the same as that of the pattern P4 in FIG. 246 (B), and as a result of converting the periodic MAP from MAP15 to MAP13 on the sub side, while the game is being performed using the acceptance mode of MAP15 on the main side. On the sub side, the game is performed using the start mode of MAP13. At this time, since the sub-control circuit 200 performs the effect using the start stage according to the start mode, it is not possible to determine whether or not the information related to the game has been initialized from the effect stage.

In this pattern P11, the number of remaining games in the current mode (main side: acceptance mode, sub side: activation mode) is equal to or greater than the minimum number of games (16 games) in the duration of activation mode, acceptance mode, and transfer mode. , The mode transition will take place after the possible duration of the start mode has been exhausted. Therefore, even if the mode on the sub side is shifted and the production stage is switched according to the transition timing of the mode on the main side, it is determined from the timing of switching the production stage whether or not the information related to the game is initialized. It is not possible.

On the other hand, in the pattern P12, since the number of remaining games in the current mode (main side: accept mode, sub side: start mode) is less than 16 games, the mode transition is before the duration that the start mode can take is exhausted. Will be done. Therefore, if the mode on the sub side is shifted and the production stage is switched according to the transition timing of the mode on the main side, it can be determined from the timing of switching the production stage whether or not the information related to the game has been initialized. There is a possibility that it will end up.

Therefore, in the pattern P12, even if the mode on the main side shifts once, the mode is maintained on the sub side without shifting, and the production stage is maintained as the starting stage. Specifically, in the sub-control circuit 200, when the mode on the main side when the power is turned on is the acceptance mode and the number of remaining games in the acceptance mode is less than 16 games, the main is limited to this cycle. Even if the mode on the side shifts once, the mode is maintained on the sub side without shifting, and then the mode shifts on the sub side according to the converted cycle MAP at the timing when the mode on the main side shifts.

As a result, in the pattern P12, after the power is turned on, the main side plays the game using the acceptance mode of MAP15, and the sub side plays the game using the start mode of MAP9. Therefore, the main side and the sub side The mode shifts with. Further, even after the first mode transition in the same cycle, the game is played using the rotation mode of MAP15 on the main side, and the game is played using the start mode of MAP9 on the sub side, so that the power is turned on. Not only later, but also after the first mode transition in the same cycle, the mode shifts between the main side and the sub side. However, since it is not possible to switch from the starting stage to another production stage within a short period of time after the power is turned on, it is possible to make it difficult to determine whether or not the information related to the game has been initialized from the timing of switching the production stage. ..

When the information about the game is initialized, various processes at the start of the cycle are performed, and the cycle MAP is newly determined. At this time, referring to the periodic MAP lottery table (FIG. 207), MAP1 can be easily determined as the periodic MAP, and as a result, the start mode, which is basically the initial mode, is set, and the sub side uses the start stage to produce the effect. However, when MA4 or the like is determined as the period MAP, the mode immediately after initialization may be a mode different from the start mode such as the transfer mode. Therefore, on the main (main control circuit 90) side, in the first cycle after the initialization process is performed, the cycle MAP including the start mode is always determined, and a mode other than the start mode is selected as the mode immediately after the initialization. It may be prevented from being set.

Further, this deviation may be controlled on the sub (sub control circuit 200) side. That is, when the sub control circuit 200 receives the initialization command from the main side, the main (main control) side is the sub (sub control circuit 200) side for the first cycle after receiving the initialization command, as described above. The period MAP on the circuit 90) side may be converted to produce the effect.

By performing such processing on the main side or the sub side, after the initialization, the effect is performed using the starting stage, so that it becomes impossible to determine whether or not the information related to the game has been initialized from the effect stage.

[Direction during normal ART]
Subsequently, the production during the normal ART will be described with reference to FIGS. 248 to 252. In the pachislot machine 1 of the present embodiment, during normal ART, the main character and the boss character perform a mahjong confrontation with two people. In this mahjong showdown, the victory or defeat is usually decided for each set of ART, and at the start of one set, the main character wins if it continues in the continuous lottery on the main side, and the boss character wins if it does not continue (however,) , If loop mode 4 is used for the normal ART of this set, the main character wins).

FIG. 248 is a diagram showing an outline of a method of determining a mahjong confrontation production, which is a production during normal ART. As shown in FIG. 248 (A), on the sub (sub control circuit 200) side, at the start of one set of normal ARTs, the distribution level, the winning form, and the progress pattern are determined by lottery.

The distribution level is information for determining the production during the mahjong confrontation. Basically, the higher the level, the more dominant the main character is. As will be described later, the distribution level is drawn based on the number of ART games, which is the duration of one set of normal ART determined by the main side, and the score of mahjong at the time of victory. The mahjong score at the time of victory is determined based on the EP points given in the normal ART of this set determined by the main side, and as shown in FIG. 248 (B), the EP points of this set are 0. If it is a point, it is "less than full", if it is 1 point, it is "full", if it is 2 points, it is "jumping", if it is 3 points, it is "doubled", and if it is 4 points. Is "triple full", and if it is a point, it is "good". In addition, since EP points are determined based on the presence or absence of continuation of normal ART in this set, the distribution level is drawn based on the number of ART games determined by the main side at the start of the set, the presence or absence of continuation, and the number of EP points. It can also be said that.

In addition, the winning form is the final winning form in the mahjong showdown. In addition, as the winning form, the role of mahjong at the time of winning may be decided, or the specific tiles constituting the role may be decided. For example, "Chiniisou", which plays the role of mahjong, can take various patterns as the type of tile to be dyed in one color (manko, tsutsuko, cordo) and the number of tiles. Therefore, as the winning form, only "Chiniisou" may be determined, or even the specific types and numbers of the tiles constituting "Chiniisou" may be determined. As will be described later, the winning form is drawn based on the distribution level and the mahjong score. In addition, since the distribution level and mahjong points are determined based on the number of ART games determined by the main side and the number of EP points determined by the presence or absence of continuation of the set, the winning form is also determined by the main side at the start of the set. It can also be said that the lottery is based on the number of ART games played, the presence or absence of continuation, and the number of EP points.

In addition, the progress pattern is the production data showing the flow of a series of mahjong in the mahjong confrontation, and the simplest is the production data that defines the incoming tiles and the discarded tiles until the main character or the boss character finishes. Is. In pachislot 1, when the winning form is determined, a progress pattern that finally becomes the winning form is determined, and in each game during one set of normal ART, an effect corresponding to the progress pattern is performed. As will be described later, the progress pattern is drawn based on the distribution level, the winning form, and the number of ART games, so the progress pattern is also based on the number of ART games, the presence or absence of continuation, and the number of EP points determined by the main side at the start of the set. It can also be said that the lottery is based on.

As shown in FIG. 248 (A), if the distribution level, winning form and progress pattern are determined at the start of one set of normal ART, then in each game in the set, mahjong progresses based on the progress pattern. However, Mahjong will be settled at any time in the set. The victory or defeat of mahjong is also decided in advance by the progress pattern, and as mentioned above, if the continuation is decided on the main side, the progress pattern that the hero wins is decided, and if the continuation is decided on the main side, the continuation is decided. The progress pattern in which the main character is defeated is determined.

<Various data tables for directing mahjong confrontation>
Subsequently, with reference to FIGS. 249 to 252, various data tables used for directing the mahjong confrontation will be described. The various data tables described below are stored in the ROM cartridge board 86.

[Distribution level lottery table]
FIG. 249 is a distribution level lottery table used to draw the distribution level for determining the production during the mahjong confrontation at the start of one set of normal ART. As shown in FIG. 249, the distribution level lottery table is provided for each number of ART games determined on the main (main control circuit 90) side, and when "short" is determined as the number of ART games, FIG. 249 (A) ) Is referred to the distribution level lottery table, and when "medium" is determined as the number of ART games, the distribution level lottery table shown in FIG. 249 (B) is referred to and "long" is determined as the number of ART games. And the distribution level lottery table of FIG. 249 (C) is referred to. The number of ART games "short" means the case where the number of ART games is "15 to 18 games", and the number of ART games "medium" means the case where the number of ART games is "32 to 37 games". Good, the number of ART games "long" means the case where the number of ART games is "38 to 42 games".

The distribution level lottery table defines the lottery value information for the lottery result (distribution level) for each mahjong score at the end of the game. At the start of one set of normal ART, the sub-control circuit 200 (sub-CPU 201) refers to the distribution level lottery table and distributes it based on the number of ART games determined by the main side, the presence / absence of continuation, and the number of EP points. Determine the tile level.

[Agari-type lottery table]
FIG. 250 is a winning form lottery table used to draw a winning form of a mahjong showdown at the start of a set of regular ARTs. As shown in FIG. 250, the winning type lottery table is provided for each mahjong score at the end of the game, and when the mahjong score at the end of the game is "less than full", the drawing table of FIG. 250 (A) is provided. The winning type lottery table is referred to, and when the mahjong score at the time of winning is "Mannuki", the winning type lottery table shown in FIG. 250 (B) is referred to. Although other winning-type lottery tables are omitted in FIG. 250, for example, when the mahjong score at the time of winning is "jumping", the corresponding winning-type lottery table is referred to. Will be.

The winning type lottery table defines the lottery value information for the lottery result (winning type) for each distribution level. In the winning type lottery table, only winning types that satisfy the corresponding points are specified. For example, in the "less than Mannuki" winning form lottery table, the winning form of more than Mannuki is not specified, and in the "Mannuki" winning form lottery table, the winning form of less than Mannuki and more than jumping is specified. Not specified. The sub control circuit 200 (sub CPU201) refers to the winning type lottery table at the start of one set of normal ARTs, and sums them based on the number of ART games determined by the main side, the presence / absence of continuation, and the number of EP points. Determine the final form.

[Progress pattern lottery table]
FIG. 251 is a progress pattern lottery table used to draw a progress pattern of a mahjong confrontation at the start of a set of normal ARTs. As shown in FIG. 251, the progress pattern lottery table is provided for each winning type and the number of ART games, and when the winning type is “less than full-blown 1” and the number of ART games is “medium”, FIG. 251 (A). ), The progress pattern lottery table of FIG. 251 (B) is referred to, and when the winning form is “less than Mannuki 1” and the number of ART games is “long”, the progress pattern lottery table of FIG. When it is "less than 2" and the number of ART games is "medium", the progress pattern lottery table of FIG. 251 (C) is referred to. In FIG. 251, other progress pattern lottery tables are omitted, but for example, in the case of the winning form "Mannuki 3" and the number of ART games "short", the corresponding progress pattern lottery table is referred to. Also, if you lose the Mahjong showdown, the progress pattern lottery table for defeat is referred to.

The progress pattern lottery table defines the lottery value information for the lottery result (progress pattern) for each distribution level. In the progress pattern lottery table, only progress patterns (for example, incoming tiles and discarded tiles) that satisfy the corresponding winning form are defined. Therefore, if the mahjong confrontation progresses according to the progress pattern, the final form will be completed and the mahjong confrontation will be settled. The sub-control circuit 200 (sub-CPU 201) refers to the progress pattern lottery table at the start of one set of normal ARTs, and based on the number of ART games determined by the main side, the presence / absence of continuation, and the number of EP points, the progress pattern To determine.

[Tile type change lottery table]
Subsequently, FIG. 252 is a tile type change lottery table used for changing the type of mahjong tile (manko, tube child, cord child). In the pachislot machine 1 of the present embodiment, in the mahjong confrontation, the winning form and the progress pattern are determined in advance, so a large amount of labor and a huge amount of data are required to increase the pattern of the production. Here, the mahjong tiles are a combination of the types of tiles (manko, tsutsuko, cordo) and the numbers of the tiles (1 to 9), so from the viewpoint of the display side in the production of the mahjong confrontation, the tiles Even if the numbers are the same, if the types of tiles are different, the effect will be performed in different display modes.

Therefore, in the pachislot machine 1 of the present embodiment, the variation of the production is increased by changing only the type of tile without changing the number of tiles. As shown in FIG. 252 (A), the tile type change lottery table defines the lottery value information for the lottery result (change pattern). Here, as shown in FIG. 252 (B), the change pattern is information that defines a pattern for changing the tile type of the original data defined by the progress pattern. For example, the change pattern 0 changes the original data. The change pattern 1 is a pattern in which the cylinder and the cord of the original data are exchanged, and the change pattern 5 is a pattern in which the tile of the original data is replaced with the cylinder, the cylinder is replaced with the cord, and the tile is replaced with the tile. It is a pattern to replace with a child.

When the sub-control circuit 200 (sub CPU201) determines the original data (progress pattern) of the effect content of the mahjong confrontation, the sub-control circuit 200 subsequently changes the tile type of the determined original data by referring to the tile type change lottery table. Determine the change pattern. Then, the sub control circuit 200 (sub CPU201) controls the display unit 212 so that the mahjong confrontation is performed based on the original data of the effect content of the mahjong confrontation and the tiles according to the change pattern. As a result, it is possible to produce a plurality of patterns from one original data, so that various productions can be performed without labor, and the amount of data for the production can be reduced.

Note that FIG. 252 (C) shows an example of changing the type of tile based on the change pattern 4. Comparing the "original data" tile and the "change tile type" tile in FIG. 252 (C), the arrangement of the tile numbers is the same simply by changing the tile type of the original data. , Depending on the player, it may feel like a similar production. However, in the mahjong game, the tiles are tiled according to the prescribed rules, so in the "after the tiles" hand tiles, the arrangement of the numbers of the tiles will be different from the "original data" hand tiles, and the tiles will look different. Can be done.

In addition, although there are "3 colors", "mixed one color", "chiniisou", etc. as the roles that the type of tile affects in the role composition of mahjong, two are replaced while maintaining one of the types of tiles. As long as (change patterns 1 to 3) or all three of the tile types are replaced so as not to overlap (change patterns 4 and 5), the role composition of mahjong will not change. On the other hand, if the tile numbers are changed, the role composition is likely to change, which complicates the rules for changing the tile numbers. Therefore, by changing the type of tile instead of the number of tiles among the parameters related to the effect display, it is possible to increase the variation of the effect with simple rules.

<Various effects>
In the pachislot machine 1 of the present embodiment, the following various effects can be obtained in terms of playability.

[ART lottery during normal game]
In the pachislot machine 1 of the present embodiment, in the normal gaming state, ART lottery is performed using one of a plurality of modes (start mode, accept mode, transfer mode, and decision mode) having different expectations of ART. , The degree of expectation of ART can be different depending on the type of mode used for the game. Here, this mode is for shifting based on the cycle MAP which defines the game of one period, hardly figure out in advance at any timing expectations of ART increases, to have a new gaming property relates ART lottery be able to.

Further, in pachislot 1, the cycle MAP itself may shift during one cycle of the game. When the periodic MAP shifts, the transition mode of the mode in which the expected degree of ART is different is different, so that the ART lottery in the normal gaming state can be further varied.

At this time, in pachislot 1, the transition of the periodic MAP is performed based on the current mode and the current periodic MAP. Therefore, even if the current modes are the same, if the periodic MAPs are different, the changed periodic MAPs. The tendency of is also different. As a result, even if the current apparent state (mode) is the same, the subsequent game playability changes according to the type of the internal state (cycle MAP), so that a wider variety of games can be played. Can have sex.

In addition, when the current cycle ends in the start mode, the transition of the cycle MAP basically shifts to MAP3 composed of the start mode and the acceptance mode, but there is a low probability that the transition mode does not include the acceptance mode. It may shift to MAPs 4 and 5 including. As a result, it is possible to skip the mode with the transition of the periodic MAP, and it is possible to have more various playability.

Further, in pachislot 1, when the cycle MAP is changed, the mode may be changed before the duration of the current mode ends in accordance with the change of the cycle MAP, or even if the cycle MAP is changed, the current mode is changed. The mode may not be changed until the duration of the mode ends. From the player's point of view, if the player switches to another mode after the duration of the current mode ends, he / she will feel that the other mode has been planned from the beginning regardless of whether or not the cycle MAP has been changed. When the mode is switched according to the transition of the periodic MAP, it is felt that the mode is switched due to the change of the periodic MAP, and there is an expectation for the subsequent game. As described above, in the pachislot machine 1, when the cycle MAP is changed, the mode is switched in various modes, so that the pachislot machine is rich in game playability and it is possible to make it difficult to get tired of the game.

At this time, in the pachi-slot machine 1, when the cycle MAP is changed and the current mode is switched to another mode after the continuation period of the current mode ends, a normal stage switching effect is performed and the continuation period of the current mode ends. When switching to another mode before, a special stage switching effect is performed. From the player's point of view, it can be inferred that the cycle map has been changed from the mode of the stage switching effect accompanying the mode switching, and it is possible to have expectations for the subsequent game.

[Production stage when the power is turned on]
Further, in the pachi-slot machine 1, since the production is performed using the production stage according to the mode, the current mode can be discriminated from the production stage. However, in Pachislot 1, when the power is turned on, regardless of the type of the current mode (specifically, the decision mode is excluded), the effect is performed using the start stage according to the start mode, so that the initialization process is performed when the power is turned on. Whether or not the above is performed, the production will be performed using the initial production stage (starting stage). As a result, it is possible to make it difficult to determine whether or not the initialization process is performed due to the setting change or the like from the production stage.

[Start timing of ART game state]
Further, in pachislot 1, if an ART lottery is won during a cycle, basically, after the end of the cycle, the game shifts to the ART preparation period, and the ART game state is started by shifting to the RT3 state during the ART preparation period. However, if the RT3 state has already been reached at the end of the cycle, the ART gaming state is suddenly started at the end of the cycle without going through the preparation for ART. As a result, the ART game state can be started at an appropriate timing without delaying the game being prepared for ART.

[Output timing of ART game state end]
Further, in pachislot 1, when the final game in the ART game state is completed, the ART game state is ended and the game state is shifted to the normal game state, but the output of the ART end is not the end of the final game but the next game. Do it at the beginning of. As a result, even if the so-called revival effect is performed at the start of the next game of the apparent final game, it is actually advantageous whether the revival effect is performed until the start operation of the next game is performed. It becomes impossible to determine whether the state has ended. As a result, according to the pachislot machine 1, it is possible to appropriately manage the timing at which the ART gaming state ends.
As the output of the end of ART, the signal output to the external device has been described as an example in the above embodiment, but when the pachi-slot machine 1 itself has a means (for example, an ART lamp) for notifying that the pachislot machine 1 is currently in the ART gaming state. Also includes on / off of the means. That is, when the final game in the ART game state is completed, the pachi-slot machine 1 does not turn off the ART lamp that it owns, but turns off the ART lamp on the condition that the start operation of the next game is detected. May be.

[Direction during ART game state]
Further, in pachislot 1, the effect to be performed during the ART game state is determined based on whether or not the normal ART of this set is continued, the number of EP points given in this set, and the number of ART games in this set. .. From the content of the production, the player can expect, for example, whether or not the ART game state will continue. In addition, since the episode ART is performed when the EP points reach a predetermined number, the player can also have expectations about the episode ART from the content of the production. In this way, in order to perform the effect according to the result of the game in the ART game state, the player pays attention to the effect to be executed and plays the game, and improves the interest of the game in the ART game state. Can be done.

Further, in the pachi-slot machine 1, a part of the parameters related to the display among the original data of the effect prepared in advance may be changed to perform the effect. As a result, it is possible to produce a plurality of patterns from one original data, so that various productions can be performed without labor, and the amount of data for the production can be reduced.

[Modification example]
In the second embodiment, four modes, a start mode, an accept mode, a transfer mode, and a decision mode, are used as modes having different probabilities of winning the ART lottery, but the present invention is not limited to this. For example, two modes having different probabilities of winning the ART lottery, such as the start mode and the transfer mode, may be used, and the probabilities of winning the ART lottery, such as the start mode, the accept mode, and the transfer mode, are different3. One mode may be used, or five or more modes may be used. Further, in the second embodiment, the decision mode is positioned as a settlement part during the cycle, and is used as a mode for demonstrating the result of the ART lottery during the cycle, and other modes (start mode, acceptance mode, and transfer) are used. Although the playability is different such that the number of continuous games is different from that of the mode), the game is not limited to this, and the same number of games as other modes may be continued.

Further, in the second embodiment, the plurality of modes have different probabilities of winning the ART lottery. Here, the fact that the probabilities of winning the ART lottery are different may mean that the probabilities in each mode are all different, or the probabilities in some modes may be common. As an example, the probabilities of winning the ART lottery in the start mode, the accept mode, the transfer mode, and the decision mode may all be different, and the probabilities of winning the ART lottery in the start mode and the accept mode are common. , The probability of winning the ART lottery in the start mode and the accept mode, the probability of winning the ART lottery in the transfer mode, and the probability of winning the ART lottery in the decision mode may be different from each other.

Further, in the second embodiment, the order relation of each mode is defined when the plurality of modes constitute a cycle. Specifically, in the second embodiment, basically, the order of each mode is determined so that the probability of winning the ART lottery increases each time the mode shifts, but this is limited to this. It is not something that can be done. For example, although the order relationship of each mode is defined, the relationship between the mode transition and the winning probability of the ART lottery may be different. As an example, when two modes with a low winning probability of ART lottery, two modes with a medium winning probability, and two modes with a high winning probability are used, the order of each mode is changed. By defining in the order of low mode, mode with medium winning probability, mode with high winning probability, mode with low winning probability, mode with medium winning probability, and mode with high winning probability, the winning probability of ART lottery is low. Various cycles can be provided, such as a cycle of transitioning to medium, high, low, medium, and high, and a cycle of transitioning to high and low winning probabilities of ART lottery.

Further, the order of the plurality of modes may not be determined in the first place. In the example of the second embodiment, for example, it may be possible to shift to the start mode or the accept mode after the transfer mode. In the example of the second embodiment, how to shift the mode can be specified by the periodic MAP, but it is not limited to the periodic MAP and may be specified by any method. By defining the cycle MAP as in the second embodiment, it is preferable to manage the modes constituting the cycle accompanying the transition of the cycle MAP.

Further, in the MAP transition lottery table (see FIGS. 210 to 217) shown in the second embodiment, the cycle MAP of the migration destination is configured to be a cycle MAP different from the cycle MAP currently used. , Not limited to this. That is, in the pachislot machine 1 according to the present invention, for example, the cycle MAP (or mode) of the migration destination may be the same cycle MAP (or mode) as the cycle MAP (or mode) currently used. Further, when the cycle MAP or the like of the transition destination is made the same as the current cycle MAP or the like in this way, the number of continuous games of the mode during the stay may be initialized or added.

Specifically, as described above, the start mode, the accept mode, and the transfer mode are modes that continue for 16 to 39 games, and even if the cycle MAP shifts, if there is no mode shift, the game concerned. It will wait for the number to be exhausted before moving to the next mode, but if the destination cycle MAP is the same as the current cycle MAP (or if the destination cycle MAP includes the current mode) , The number of games elapsed until winning the transition lottery of the periodic MAP may be reset, the number of games of 16 to 39 games may be newly determined, and the number of games corresponding to the determined number of games may be stayed in the corresponding mode. In addition, when the cycle MAP of the migration destination is the same as the current cycle MAP (or when the cycle MAP of the migration destination includes the current mode), the number of games of 16 to 39 games is newly determined, and the number of games is newly determined. The number of games may be added to the number of remaining games at the timing of winning the transition lottery of the periodic MAP, and the mode may be stayed in the mode corresponding to the number of games after the addition.

By doing so, the number of games in the mode during the stay will be added. For example, if the cycle MAP is the same as the current cycle MAP while staying in the transfer mode, the probability of winning the ART lottery is high. The length of stay in the transfer mode can be extended, and the interest can be enhanced. If the number of games in the mode with a low probability of winning the ART lottery is added, the interest may be impaired. Therefore, among the plurality of modes, the probability of winning the ART lottery is equal to or higher than a predetermined probability (that is, The number of continuous games in the mode during the stay may be initialized or added only for the mode in which the expected degree of the advantageous state is equal to or higher than a predetermined value. In the example of the second embodiment, the start mode and the accept mode have a low probability of winning the ART lottery, and the transfer mode has a high probability of winning the ART lottery. Therefore, in the case of the example of the second embodiment, when shifting to the same cycle MAP as the current cycle MAP while staying in the start mode or the accept mode, the number of continuous games in the staying mode is initialized or If the player shifts to the same cycle MAP as the current cycle MAP while staying in the transfer mode without adding, the number of continuous games in the staying mode may be initialized or added.

Further, in the example of the second embodiment, when the transition lottery of the periodic MAP is won, the transition is made only to the periodic MAP including the mode prior to the mode specified by the periodic MAP currently used. , Not limited to this. For example, when the cycle MAP currently used is MAP3 (starting mode and acceptance mode), the transition to MAP1 (starting mode) may be performed. In this case, it may be possible to shift to MAP1 only while staying in a specific mode (start mode or accept mode) of MAP3, or it may be possible to shift from MAP3 to MAP1 regardless of the mode during stay. In the example of the second embodiment, although the transition of the periodic MAP is disadvantageous to the player, in consideration of the overall profit balance (ball output rate), the control that is advantageous to the player in other parts is performed. It will be easier to do. Further, as described above, the order of the modes is as follows: a mode with a low winning probability, a mode with a medium winning probability, a mode with a high winning probability, a mode with a low winning probability, a mode with a medium winning probability, and a high winning probability. When the order of modes is specified, even if the order shifts to the periodic MAP including the previous mode, the player is not necessarily disadvantaged.

In the example of the second embodiment, after the cycle MAP is shifted, the mode before the staying mode is not used, but the mode before the staying mode is included only in this way. When it is possible to shift to the periodic MAP, the mode before the mode during the stay may be used after the transition to the periodic MAP, or may not be used. When a mode before the staying mode is used, for example, the mode shifts to the wake-up mode with the transition from MAP3 to MAP1 during the staying mode. On the contrary, when the mode before the staying mode is not used, for example, if the mode is changed from MAP3 to MAP1 during the staying mode, the cycle may be terminated.

Further, in the example of the second embodiment, when the cycle MAP is shifted and there is no mode shift (the mode currently staying in the cycle MAP after the shift is included), the game of the mode during stay is included. It will wait for the number to be exhausted before moving to the next mode, and if there is a mode transition (the mode currently staying in the cycle MAP after the transition is not included), wait for the number of mode transition games to elapse. Transition modes, but not limited to this. For example, even when the periodic MAP is shifted, it may be possible to always wait for the number of games in the mode being stayed to be exhausted before shifting to the next mode, and when the periodic MAP is shifted, it is always possible. , Mode transition The mode may be transitioned after waiting for the number of games to elapse.

Further, the mode transition method may be changed in consideration of the number of transitions of the periodic MAP. For example, if the transition of the periodic MAP is less than the predetermined number of times, the game shifts to the next mode after waiting for the number of games in the mode being stayed, and if the transition of the periodic MAP is more than the predetermined number of times, The mode may be shifted after the lapse of the number of mode shift games (regardless of whether or not the mode currently staying in the cycle MAP after the shift is included). In this case, the period for counting the number of transitions of the periodic MAP is arbitrary, for example, it may be between one cycle, between a plurality of cycles, or the same during one cycle. It may be staying in the mode of, or may be staying in a plurality of modes during one cycle.

In this regard, referring to the MAP transition lottery table of FIG. 210 of the second embodiment, MAP4 (transfer mode) is determined as the cycle MAP of the transition destination in the data of the "continuation column" during the stay in the start mode. Become. Therefore, for example, during the stay in the start mode of MAP1 (start mode), a transition lottery using the data in the "end column" is won, and after shifting to MAP3 (start mode and acceptance mode), during the stay in the start mode of MAP3. If you win the transition lottery using the data in the "continuation column", you will be transitioned to MAP4. In the example of the second embodiment, the cycle MAP is performed twice while staying in the same mode for one cycle. When the mode is changed, the mode is changed, and the mode is changed after waiting for the number of mode change games to elapse. Such control can be realized by using the MAP transition lottery table that shifts to the periodic MAP that does not include the mode currently staying when the data in the "continuation column" is referred to.

As described above, when the mode shift is performed along with the shift of the periodic MAP, a special stage switching effect is performed.

Further, in the second embodiment, an internal winning combination or the like is used as a parameter used for the transition lottery of the periodic MAP (see FIG. 210), but the parameter used for the transition lottery of the periodic MAP is not limited to this. Instead, other information may be used. For example, the parameters used for the transition lottery of the periodic MAP include a set value, an internal winning combination, a random number value used for determining the internal winning combination, and another random number value different from the random number value used for determining the internal winning combination. Be done. Further, the timing for determining the cycle MAP is also arbitrary, for example, it may be at the time of setting change, power-on, end of one cycle (start of the next cycle), and a predetermined combination is an internal winning combination. It may be when the number of times determined as is reached a predetermined number of times.

It should be noted that the time when the predetermined number of times the predetermined combination is determined as the internal winning combination reaches the predetermined number may be limited to one cycle of the game, and the entire game period may be limited regardless of the cycle. It may be, or it may be during a multi-period game. Further, it may be between one or a plurality of cycles, and the one or a plurality of cycles may be determined by an arbitrary method such as lottery. Further, a predetermined combination can be arbitrarily determined, and one or a plurality of combinations may be determined as a predetermined combination. The number and types of predetermined combinations may be determined based on the period (number of cycles) for counting the predetermined combinations, and conversely, the predetermined number and types of combinations may be determined. The period (number of cycles) for counting the winning combination may be determined.

Further, the timing for determining the number and type of predetermined combinations and / or the timing for determining the period (number of cycles) for counting the predetermined combinations is also arbitrary. For example, the predetermined combination is determined as the internal winning combination. It may be the timing when the transition lottery of the cycle MAP is performed when the number of times of the transition reaches a predetermined number, or at the end of the cycle in which the transition lottery is performed (at the start of the next cycle). It may be.

Further, in the second embodiment, the EP point lottery is not performed when the continuous lottery during the ART gaming state is discontinued (see FIG. 228), but the present invention is not limited to this, and the discontinuation is not performed. Even in this case, EP points may be drawn and given. In this case, if a privilege (episode ART) is granted along with the granting of EP points in the case of discontinuation, the discontinuation may be rewritten to continuation and then transferred to episode ART. It will be maintained as discontinued, and will be transferred to the episode ART on the condition that the addition etc. was not performed during the normal ART, and conversely, if the addition etc. is not performed during the normal ART, the privilege (episode ART) May be extinguished and the ART gaming state may be terminated.

In addition, the privilege given based on the EP points is also optional, and the privilege related to the payout given to the player (for example, the addition of the duration of the ART game state (episode ART), the discontinuation is rewritten to continue, loop mode 4 It may be a privilege other than the payout (for example, opening of a privilege video or custom opening of pachislot 1).

Further, in the example of the second embodiment, EP points are given to the ART gaming state, but the present invention is not limited to this, and the timing of giving EP points is arbitrary. For example, EP points may be given not only during the ART gaming state but also during non-ART. In this case, a predetermined number of EP points are given at the time of transition from the non-ART to the ART gaming state. The timing of giving EP points during non-ART is also arbitrary, and it may be at each game, at the start of a cycle, at the time of mode transition, or at the time of mode transition. , It may be at the time of transition of the periodic MAP, or it may be that a predetermined combination has been determined as an internal winning combination.

Further, in the above example, the timing of outputting a signal indicating that the current gaming state is not the ART gaming state to the external device is set as the time of detecting the start operation of the next game of the game in which the ART gaming state has ended. However, the present invention is not limited to this, and may be the timing at which any of the first stop operation to the third stop operation of the next game is detected. That is, in the pachi-slot machine 1 according to the present invention, when the main control circuit 90 and the external centralized terminal plate 47 end the ART game state, a predetermined operation (start operation, first operation) in the next game of the game in which the ART game state ends. Information (external output signal) indicating that the ART gaming state has ended may be output to the external device in response to the detection of the 1st stop operation, the 2nd stop operation, or the 3rd stop operation). Since the so-called revival effect may be performed at the timing when any of the first stop operation to the third stop operation of the game following the game in which the ART game state has ended is detected, the timing of outputting the signal is also these. By adjusting to the timing, it is possible to output a signal to an external device at a more accurate timing.

Further, in the above embodiment, the game playability in the non-ART game state and the game playability in the ART game state are distinguished, the game playability in the non-ART game state is applied only during the non-ART game state, and the game playability in the ART game state is ART. An example is shown in which the application is applied only during the gaming state, but the present invention is not limited to this, and the gaming property applied during the non-ART (gaming property during the non-ART) can be applied even during the ART gaming state. Often, the game playability applied during the ART game state (game property during the ART game state) may be applied during the non-ART game state.

Specifically, for example, in the pachi-slot machine 1 of the second embodiment, a plurality of modes having different winning expectations of the ART lottery are provided during non-ART, and the ART lottery is performed with a probability corresponding to these modes, and these modes are performed. Mode is managed based on the periodic MAP. In this respect, the game property of performing lottery regarding ART according to the mode managed based on such a periodic MAP may be performed during the ART gaming state. In this case, if the ART lottery based on the mode is won, the ART game state will be added instead of the first hit of the ART game state. The target of addition is appropriately adjusted according to the management method of the duration of the ART game state, such as the number of games, the number of sets, the number of navigations, and the number of differences.

Further, the content of the notification performed during the ART gaming state is not limited to the above-mentioned example, and is arbitrary. For example, the order of stop operations (pushing order) in which a special symbol combination that is advantageous to the player is displayed may be notified, or the timing of the stop operation required for displaying the symbol combination ( The symbol to be aimed at) may be notified.

As an advantageous state for the player, the winning probability of the internal winning combination related to the re-game does not change (or changes within a range that does not affect the game playability), but the mode of the stop operation that is advantageous for the player. It may be in a gaming state in which the notification function, that is, the AT function is activated. Further, as an advantageous state for the player, a re-game high probability state (replay time) in which the winning probability of the internal winning combination related to the re-game is high is activated, and a mode of the stop operation advantageous for the player is notified. It may be in a gaming state in which the function is activated, that is, the ART function is activated.

Further, the method of managing the duration of the ART gaming state is also arbitrary. For example, the duration may be managed by the number of games, the duration may be managed by the number of medals paid out during the ART game state, or the difference number, or the medals may be managed during the ART game state. The duration may be managed by the number of notifications (number of navigations) that affect the payout, or the duration may be managed by the continuation determination performed at an arbitrary timing during the ART game state.

Further, in the pachi-slot machine 1 of the above embodiment, an example of displaying various display screens on the sub-display device 18 provided on the left side of the reel display window 4 when viewed from the player side has been described, but the present invention is not limited thereto. .. For example, another sub-display device may be provided on the right side of the reel display window 4 when viewed from the player side, and various display screens may be displayed on this sub-display device as well. In this case, a touch sensor is provided on the display surface of the sub display device provided on the right side of the reel display window 4, and the display screen of the sub display device is switched based on the touch input information output from the touch sensor. It may be.

Further, in the pachi-slot machine 1 of the above embodiment, the notification (ART) function is operated under the control of the main (main control board 71) side, but the present invention is not limited to this, and the sub (sub-control) is not limited to this. The notification (ART) function may be operated by the control on the board 72) side.

Further, in the pachi-slot machine 1 of the above embodiment, the CZ or ART gaming state is shifted to the CZ or ART gaming state by winning the transition lottery performed during the normal gaming state. Here, in the pachi-slot machine 1 of the above-described embodiment, it is possible to give a setting difference to the transition lottery, but the transition lottery may be performed based on "information having no difference in the set value". In addition, "information with no difference in set values" means a combination that is determined as an internal winning combination with the same probability in all the set values in the internal lottery process (setting unquestioned combination), and all settings when all reels are stopped. It includes at least a symbol combination (a symbol combination with no setting difference) that will be displayed with the same probability in the value.

That is, in the modified example of pachislot 1, when the unquestioned winning combination is determined as the internal winning combination, a lottery for transitioning to the CZ or ART game state is performed, and the combination with the setting difference (setting difference combination) is determined as the internal winning combination. If so, the lottery for transition to the CZ or ART game state is not performed. Further, in the pachislot machine 1 of the present embodiment, when a symbol combination having no setting difference is displayed when all reels are stopped, a lottery for shifting to the CZ or ART game state is performed, and the symbol combination having a setting difference is displayed. In that case, the lottery for transition to the CZ or ART gaming state is not performed.
In addition, in this specification, not performing lottery includes not only not performing lottery itself, but also including lottery but always being non-winning.

Further, the lottery for transitioning to the CZ or ART gaming state may be performed based on a predetermined probability of perfection that does not fluctuate at all. The "predetermined perfect probability that does not fluctuate at all" means at least a probability that does not fluctuate based on the set value (that is, the probability that the winning probability is the same regardless of the set value).
It should be noted that the "perfect probability that is predetermined and does not fluctuate at all" may be further included as the probability that is uniquely determined for "information that does not differ in the set value". In recent game machines, a state in which it is easy to win a transition lottery and a state in which it is difficult to win may be provided. In such a case, when the transition lottery is performed with the "probability uniquely determined for the information having no difference in the set value", for example, at the time of winning the setting unquestioned role, regardless of the gaming state. The transition lottery that wins with the same probability will be performed. On the contrary, when the transition lottery is performed with a "probability that is not a uniquely determined probability (that is, a probability that fluctuates) for information that does not have a difference in the set value", for example, when the setting unquestioned role is won, A transition lottery that wins with a probability according to the current gaming state, that is, if the current gaming state is a high probability state, a transition lottery that wins with a high probability is performed, and the current gaming state is a low probability state. In that case, a transition lottery, which wins with a low probability, will be performed.

By performing the transition lottery based on "information with no difference in the set value" with the same probability of winning regardless of the set value, the pachislot machine 1 of the modified example will be in the CZ or ART game state. The degree of expectation regarding the transition can be made the same for each set value, and the difference in ball ejection performance can be suppressed to the winning probability of the setting difference combination with the setting difference.

In addition, when such a modification is applied to the pachislot machine 1 of the second embodiment, the ART lottery performed during the cycle is performed according to the setting unquestioned combination, while the internal winning combination is not set for the transition of the cycle MAP. It may be performed only when it is a combination, or it may be performed regardless of the type of internal winning combination (setting difference combination, setting unquestioned combination).

In addition, the lottery for shifting to the CZ or ART game state includes (1) an internal lottery for determining the internal winning combination, (2) a transition lottery for whether or not to perform the transition, and (3) a case of shifting. Three lottery of advantageous section type lottery for deciding transfer destination can be considered. In pachislot 1, these three lottery may be performed by using individual random numbers, all the lottery may be performed by using a common random number value, and the two lottery may be common. The random number value of the above may be used, and the remaining one lottery may be performed using the individual random number values. It should be noted that using a common random number value means, for example, (1) when a predetermined set unquestioned combination is determined in the random number range of "0 to 128" in the internal lottery, (2) "0 to 64" is shifted. Non-winning random number range for lottery, "65-128" is the transition random number range for lottery, and (3) "65-83" is the random number range where the migration destination is CZ1, "83-99" is migrated. The destination is a random number range with CZ2, "99 to 115" is a random number range with a transfer destination of CZ3, and "115-128" is a random number range with a transfer destination in the ART gaming state. In other words, the lottery results of other lottery are assigned to a part of the random number range that is won in one lottery.

Further, in the above-described embodiment and various modifications, the pachi-slot machine has been described as an example, but the present invention is not limited thereto. Features other than the features peculiar to pachislot 1, such as the features related to reel control and the features related to setting change and confirmation of the present invention, can be applied to a gaming machine called "pachinko", and the same effect can be obtained. For example, checksum generation and determination processing, various processing using the main CPU 101 dedicated instruction code (address specification processing using the Q register, soft timer update processing, 7-segment LED drive processing, communication data generation and storage processing, etc. ), Various processes using the non-standard ROM area and the non-standard RAM area, and the like can also be applied to "pachinko".

<Various functions of the main control board and sub control board>
The embodiments and various modifications of the pachi-slot machine 1 according to the present invention have been described above. Here, various functions possessed by the main control board 71 (main control circuit 90, main CPU 101) and the sub control board 72 (sub control circuit 200, sub CPU 201) of the pachislot machine 1 according to the present invention will be collectively described.

The main control board 71 is connected to the start switch 79 and the stop switch board 80, and controls the progress of the game shown in FIG. Therefore, the main control board 71 functions as a start operation detecting means, a symbol changing means, an internal winning combination determining means, a stop operation detecting means, a reel stop control means (stop control means), and a winning determination means.

Further, the main control board 71 may determine the cycle MAP used for the current cycle and change the determined cycle MAP to another cycle MAP during the normal gaming state. Then, the main control board 71 determines and changes the mode based on the determined period MAP. Therefore, the main control board 71 functions as a first mode determining means, a second mode determining means, a third mode determining means, a map determining means, a map changing means, a mode determining means, and a mode changing means.

Further, the main control board 71 performs the ART lottery with a probability according to the mode determined based on the periodic MAP, and when the ART lottery is won, the ART game state is performed. ) Functions as a privilege granting means, an advantageous state determining means, and an advantageous state starting means. When the main control board 71 functions as a privilege granting means, the main control board 71 grants the privilege of the ART gaming state, and the privilege granted here is in addition to the first hit of the ART gaming state. , The addition of the ART game state is also included.

Further, the main control board 71 grants EP points during the ART gaming state, and when the EP points reach a predetermined point, grants a predetermined privilege, and thus functions as a point granting means and a privilege granting means. Further, the main control board 71 determines the number of ART games according to the number of EP points given. As the number of ART games increases, the ART game state continues for a long time, which is advantageous for the player, and the smaller the number, the more disadvantageous the player is. Therefore, the main control board 71 for determining the number of ART games functions as an advantage degree determining means. ..

Further, since the main control board 71 and the power supply device 53 detect the power-on, they function as power-on detecting means. Further, the main control board 71 clears various game information (that is, clears the mode and cycle MAP used in the current game) when the predetermined conditions are satisfied and the initialization process is performed. Functions as an initialization means. Then, when the cycle MAP or mode is cleared as a result of this initialization process, the main control board 71 functions as a mode determining means because the cycle MAP or mode is newly determined as the process at the start of the cycle. At this time, since the sub-control board 72 performs the effect on the display unit 212 using the raising stage regardless of the mode newly determined by the main control board 71, the sub-control board 72 and the display unit 212 are the effect means. Functions as.

Further, the sub-control board 72 performs a predetermined effect on the display unit 212 using the effect stage according to the mode, and determines and determines the effect based on the information determined on the main side during the ART game state. The production is performed via the display unit 212. Therefore, the sub-control board 72 functions as an effect determining means, and the sub-control board 72 and the display unit 212 function as an effect means.
Since the sub-control board 72 changes some parameters of the original data of the effect, it also functions as an effect changing means.

Further, the main control board 71 functions as a state control means because it starts the ART gaming state when the transition condition to the ART gaming state is satisfied and ends the ART gaming state when the ending condition is satisfied. Then, when the ART game state ends, the main control board 71 transmits an external signal indicating that the ART game state has ended via the external centralized terminal board 47 in response to the detection of the start operation of the next game. Since the output is to an external device, the main control board 71 and the external centralized terminal board 47 function as output means.

Further, since the main control board 71 shifts the RT state according to the transition condition of the RT state, it functions as an RT transition means. Then, the main control board 71 performs an ART lottery, and when the ART lottery is won, the ART gaming state is started during the RT3 state after the end of the cycle, so that the main control board 71 functions as a notification determination means and a notification state control means.

<Supplementary note (summary of the present invention)>
[First game machine]
Conventionally, in the game machine having the above-described configuration, there is known a game machine that obtains a checksum of data stored in a RAM at the time of power failure and performs a checksum determination process obtained at the time of power failure when the power is restored (. For example, see Japanese Patent Application Laid-Open No. 2009-011375). In the gaming machine of JP-A-2009-011375, in the checksum determination process at the time of power restoration, an error notification is performed when the checksum obtained at the time of power restoration does not match the checksum obtained at the time of power failure.

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of the game playability, and there is a demand for reducing the capacity of processing programs and tables other than the game playability managed by the main control circuit.

The present invention has been made to solve the above-mentioned first problem, and the first object of the present invention is to reduce the capacity of processing programs, tables, etc. other than playability managed by the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free capacity of the ROM of the main control circuit and enhancing the game playability by utilizing the free space of the ROM corresponding to the increased capacity.

In order to solve the first problem, the present invention provides a first gaming machine having the following configuration.

An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling a game operation, and a first storage means (for example, the main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. A second storage means (for example, the main RAM 103) for storing information necessary for executing the arithmetic processing by the arithmetic processing means, and a power supply means for supplying a power supply voltage (for example, a power supply board 53b and a switching regulator 94). ) And a start-up means (for example, a reset signal output process of the power supply management circuit 93) that outputs a start-up signal to the arithmetic processing means when the power supply voltage exceeds a predetermined start-up voltage value (for example, 10 V). ) And the power failure means (for example, power failure detection of the power management circuit 93) that outputs a power failure signal to the arithmetic processing means when the power supply voltage falls below a predetermined power failure voltage value (for example, 10.5 V). (Signal output processing), the arithmetic processing means outputs a flag register (for example, flag register F) for storing data corresponding to the result of the arithmetic processing, and the power failure means outputs the power failure signal. A sum value calculating means (for example, a check sum generation process) that calculates a sum value by cumulatively adding all the information stored in a predetermined storage area (for example, a gaming RAM area) in the second storage means. ) And the activation signal is output, and the information stored in the predetermined storage area is sequentially subtracted from the sum value generated by the sum value calculation means when the latest power failure occurs. When the subtraction processing by the sum value subtracting means for the sum value subtracting means (for example, S122 to S131 during the thumb check processing) and all the information stored in the predetermined storage area is completed, the flag A thumb value determining means (for example, S134 during thumb check processing) for determining the presence or absence of an abnormality based on the data corresponding to the subtraction result set in a predetermined bit area (for example, the zero flag) in the register, and A game machine characterized by having.

Further, in the first gaming machine of the present invention, the sum value calculating means executes a specific instruction (for example, a POP instruction) when adding information stored in the predetermined storage area. The continuously stored 2 bytes of information are acquired and added, and the information of the read start address of the information is updated by 2 bytes, and the sum value subtracting means is the sum generated when a power failure occurs. When the information stored in the predetermined storage area is subtracted from the value, by executing the specific instruction, the information for two consecutively stored bytes is acquired and subtracted, and the information is read out. The information of the start address may be updated by 2 bytes.

Further, in the first gaming machine of the present invention, the arithmetic processing means has a stack pointer capable of setting the address of the predetermined storage area of the second storage means, and the sum value calculation means stores the predetermined storage. The specific instruction to be executed when adding the information stored in the area may be a dedicated instruction (for example, a POP instruction) for operating the stack pointer.

According to the first gaming machine of the present invention having the above configuration, the capacity of processing programs and tables other than game playability is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the capacity is increased. The playability can be improved by using the free area of the ROM corresponding to the capacity.

[2nd to 5th game machines]
Conventionally, in a gaming machine having the above-described configuration, a gaming machine equipped with a main control device that processes numerical data by using a stack pointer as an operation command has been proposed (see, for example, Japanese Patent Application Laid-Open No. 2005-237737). ).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above-mentioned second problem, and a second object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the second problem, the present invention provides a second gaming machine having the following configuration.

An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling a game operation, and a first storage means (for example, the main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. And a second storage means (for example, the main RAM 103) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, the arithmetic processing means is the arithmetic processing of the arithmetic processing means. A general-purpose register in which data is stored at the time of execution, a dedicated register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and data is stored and stored when the arithmetic processing is executed by the arithmetic processing means. It has an expansion register (for example, a Q register) capable of designating a part of an address in the first storage means or the second storage means based on the data, and the arithmetic processing means uses the expansion register. A gaming machine characterized in that it is possible to execute predetermined commands (for example, "BITQ" command, "SETQ" command, "LDQ" command, etc.) capable of designating an address in the second storage means.

Further, in the second gaming machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

Further, in order to solve the second problem, the present invention provides a third gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, internal lottery processing) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. The stop control means (for example, reel stop control process) to be caused, the arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the stop operation of the display column by the stop control means, and the arithmetic processing means. A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing is stored, and a second storage means (for example, for example) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. The main RAM 103) is provided, and the arithmetic processing means stores a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and data is stored when the arithmetic processing is executed by the arithmetic processing means. A dedicated register and an expansion register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and a part of an address in the first storage means or the second storage means can be specified by the stored data (an expansion register). For example, a Q register), and the arithmetic processing means can specify an address in the second storage means by using the expansion register in the process of checking the stop state of the display column. (For example, the "LDQ" instruction) is executed to read the information indicating the state of the variable display of the predetermined display column stored in the second storage means, and then the expansion register is used. A predetermined logical sum operation instruction (for example, "ORQ" instruction) capable of specifying an address in the second storage means is executed, and the other display string stored in the second storage means is executed. While reading the information indicating the state of the variable display , The OR operation is performed on the information and the information indicating the state of the variable display of the predetermined display column, and then the execution of the predetermined OR operation instruction is repeated to obtain the result of the OR operation and the rest. The logical sum operation with the information indicating the variable display state of each display column is repeated, and all the display columns are stopped based on the result of the operation sum operation obtained when the logical sum operation for all the display columns is completed. A gaming machine characterized in determining whether or not it is in a state.

Further, in the third gaming machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

Further, in order to solve the second problem, the present invention provides a fourth gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, internal lottery processing) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. Stop control means (for example, reel stop control processing) to be caused, arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling the determination operation of the internal winning combination by the internal winning combination determining means, and the arithmetic. A first storage means (for example, the main ROM 102) in which information necessary for executing the arithmetic processing by the processing means is stored, and a second storage means in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. (For example, the main RAM 103), the arithmetic processing means includes a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and data is stored when the arithmetic processing is executed by the arithmetic processing means. Data is stored at the time of executing the arithmetic processing by the stored dedicated register and the arithmetic processing means, and a part of the address in the first storage means or the second storage means can be specified by the stored data. The internal winning combination, which has an expansion register (for example, a Q register) and is determined by the internal winning combination determining means, is set to adjust an expected value for determining the internal winning combination related to privilege granting. An internal winning combination for each setting is provided in which the winning probability changes according to the value, and the arithmetic processing means uses the expansion register to specify an address in the second storage means in the process of determining the internal winning combination. By executing a predetermined addition instruction (for example, "ADDQ" instruction) that can be performed, the current lottery value is stored at the start address of the area in which the lottery value for each set value of the internal winning combination for each setting to be lottery is stored. The set value is added and associated with the current set value. A gaming machine characterized in that an address in which a lottery value of an internal winning combination according to the setting is stored is specified and the lottery value is acquired.

Further, in the fourth gaming machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

Further, in order to solve the second problem, the present invention provides a fifth gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, internal lottery processing) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. When the change display of the plurality of display columns is stopped by the stop control means (for example, reel stop control process) to be caused and the stop control means, on the determination line set across the plurality of display columns. The privilege granting determination means (for example, winning search processing) for determining whether or not the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed, and the determination operation by the privilege grant determination means are controlled. The arithmetic processing means (for example, the main CPU 101) that performs the arithmetic processing for the purpose, the first storage means (for example, the main ROM 102) in which the information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and the arithmetic processing. A second storage means (for example, a main RAM 103) for storing information necessary for executing the arithmetic processing by the means is provided, and the arithmetic processing means stores data when the arithmetic processing is executed by the arithmetic processing means. The arithmetic processing means is predetermined in the process of determining whether or not the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line. When a read command (for example, a "LDIN" command) is executed and a combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line, the game medium can be given. A game characterized by simultaneously acquiring data on the number of payouts and determination data indicating the type of combination of symbols corresponding to the internal winning combination related to the payout of the game medium, which is associated with the data on the number of payouts. Machine.

Further, in the fifth game machine of the present invention, the arithmetic processing means determines whether or not the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line. In the process, the game medium is paid out by executing a predetermined determination command (for example, the "JSLAA" command) that can execute the determination command, the process jump destination address designation command, and the process jump operation command with one command. It may be determined whether or not the combination of symbols corresponding to the internal winning combination according to the above is stopped and displayed.

According to the second to fifth gaming machines of the present invention having the above configuration, the capacity of processing programs and tables managed by the main control circuit is reduced to reduce the free capacity of the ROM (first storage means) of the main control circuit. It is possible to increase the number and improve the playability by utilizing the free area of the ROM corresponding to the increased capacity.

[6th and 7th game machines]
Conventionally, in the game machine having the above-described configuration, when an abnormality occurs in the data stored in the RAM of the main control unit, the RAM abnormality error state is controlled, the progress of the game is disabled, and the setting change mode is performed. When a new setting value is selected / set based on the setting change operation, a game machine has been proposed that cancels the state in which the game progress is disabled and makes the game progressable (the game machine is proposed). For example, see Japanese Patent Application Laid-Open No. 2007-209810).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above-mentioned third problem, and a third object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the third problem, the present invention provides a sixth gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, internal lottery processing) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. Stop control means (for example, reel stop control process) to be caused, data transmission means for transmitting command data related to the game operation (for example, S904 (communication data transmission process) during interrupt processing), and internal winning related to privilege granting. A setting change confirmation means (for example, a setting change confirmation process) capable of executing a setting value change process and a setting value confirmation process for adjusting an expected value for which a combination is determined, and a set value by the setting change confirmation means. An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a change operation or a confirmation operation, and a first storage means (for example,) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. The main ROM 102) and a second storage means (for example, the main RAM 103) for storing information necessary for executing the arithmetic processing by the arithmetic processing means are provided, and the arithmetic processing means changes the set value. Alternatively, at the start of the set value confirmation process, the start command generation means for generating the first command data (for example, S43 during the setting change confirmation process) and the set value change process or the set value confirmation process. At the end, the first command data having the end command generation means (for example, S57 during the setting change confirmation process) for generating the second command data, and being executed by the start command generation means. The game machine is characterized in that the generation process of the second command data and the generation process of the second command data executed by the command generation means at the end are shared.

Further, in the sixth gaming machine of the present invention, the arithmetic processing means has a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and the arithmetic processing means is the first. When generating the command data of, the first value (for example, "005H") is set in a predetermined register (for example, L register) of the general-purpose register, the generation process is executed, and the second When generating the command data of, a second value (for example, "004H") may be set in a predetermined register of the general-purpose register to execute the generation process.

Further, in order to solve the above-mentioned third problem, the present invention provides a seventh gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, internal lottery processing) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. The stop control means (for example, reel stop control process) to be caused, the data transmission means for transmitting command data related to the game operation (for example, S904 (communication data transmission process) during interrupt processing), and the command data are created. Communication data generation means (for example, setting change command generation and storage processing and communication data storage processing), setting value change processing and setting value confirmation processing for adjusting the expected value for which the internal winning combination related to privilege grant is determined. To control the setting change confirmation means (for example, the setting change confirmation process), the command data generation operation by the communication data generation means, and the setting value change operation or confirmation operation by the setting change confirmation means. The arithmetic processing means (for example, the main CPU 101) that performs the arithmetic processing, the first storage means (for example, the main ROM 102) in which the information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and the arithmetic processing means. A second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process is provided, and the calculation processing means starts the setting value change process or the set value confirmation process. At the end of the start command generation means (for example, S43 during the setting change confirmation process) and the set value change process or the set value confirmation process, the end command data is generated. The end-time command generation means (for example, S57 during the setting change confirmation process), the start-time command data generation process executed by the start-time command generation means, and the end-time command generator. The end-time command data generation process executed by the stage is shared, and the arithmetic processing means has a plurality of types of data in which a plurality of types of data are stored when the arithmetic processing is executed by the arithmetic processing means. The arithmetic processing means has a general-purpose register, and in the command data generation process, the communication parameter used among a plurality of types of communication parameters constituting the command data corresponds to the correspondence among the plurality of general-purpose registers. The communication parameters used set in the general-purpose register are stored in a predetermined storage area (for example, a communication data temporary storage area) in the second storage means, and the plurality of types of communication are performed. If there is a communication parameter that is not used among the parameters, the data stored in the general-purpose register associated with the unused communication parameter at the time of generating the command data is stored in the predetermined storage area as the communication parameter. A gaming machine characterized in that a sum value of the command data is generated based on the data stored in the general-purpose register associated with the communication parameter.

Further, in the seventh game machine of the present invention, in the command data generation process, the value stored in the general-purpose register associated with the communication parameter is added to the value stored in the accumulator of the general-purpose register. By doing so, the sum value of the command data may be generated, and the generated sum value may be stored in the predetermined storage area.

According to the sixth and seventh gaming machines of the present invention having the above configuration, the capacity of the processing program and the table managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the increased capacity is increased. The playability can be improved by using the free area of the ROM of the minute.

[8th and 9th game machines]
Conventionally, in a game machine having the above-described configuration, a game machine that transmits a command from a game control board (main control circuit) to an effect control board (sub control circuit) is known (see, for example, Japanese Patent Application Laid-Open No. 2002-360766). ).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above-mentioned fourth problem, and a fourth object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the fourth problem, the present invention provides an eighth game machine having the following configuration.

An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a game operation, and a first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. A second storage means (for example, the main RAM 103) that stores information necessary for executing the calculation process by the calculation processing means, and a data transmission means (for example, during interrupt processing) for transmitting communication data related to the game operation. S904 (communication data transmission processing)) and communication data generation in which the communication data is created and the generated communication data is stored in a communication data storage area provided in a predetermined address range in the second storage means. A storage means (for example, a communication data storage process and a communication data pointer update process) is provided, and the communication data generation storage means moves from the storage area of the start address of the predetermined address range to the storage area of the last address. Sequentially, when storing the communication data in the communication data storage area, a predetermined update instruction (for example, "ICPLD" instruction) capable of executing an update instruction, an upper limit determination instruction, and a determination branch instruction with one instruction is executed. Thereby, the current value of the communication data pointer, which is a parameter related to the address designation in the communication data storage area, is compared with the upper limit value of the communication data pointer corresponding to the last address, and the current communication data is compared. If the pointer is less than the upper limit value, the communication data pointer is added and updated, and if the current communication data pointer is equal to or more than the upper limit value, the communication data pointer is used as the communication data pointer corresponding to the start address. A game machine characterized by changing to a lower limit value.

Further, in the eighth game machine of the present invention, when the communication data generation and storage means changes the communication data pointer to the lower limit value of the communication data pointer corresponding to the start address, the communication data storage area The communication data stored in may be invalidated.

Further, in order to solve the fourth problem, the present invention provides a ninth game machine having the following configuration.

An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling a game operation, and a first storage means (for example, the main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. And a second storage means (for example, main RAM 103) in which information necessary for executing the calculation process by the calculation processing means is stored, the calculation processing means has a predetermined value related to the progress of the game operation. In the data value counting process (for example, the medal payout number check process), when updating the predetermined data value, a predetermined update that can execute an update command, a lower limit judgment command, and a judgment branch command with one command. By executing an instruction (for example, a "DCPLD" instruction), the current value of the predetermined data is compared with the lower limit of the value of the predetermined data, and the current value of the predetermined data is the predetermined value. If it is larger than the lower limit of the value of the predetermined data, the value of the predetermined data is subtracted and updated, and if the current value of the predetermined data is equal to or less than the lower limit of the value of the predetermined data, the value of the predetermined data A gaming machine characterized in that the value is held at the lower limit value.

Further, in the ninth game machine of the present invention, the predetermined data may be the number of payouts of the game medium.

According to the eighth and ninth gaming machines of the present invention having the above configuration, the capacity of processing programs and tables managed by the main control circuit is reduced to reduce the free capacity of the ROM (first storage means) of the main control circuit. It is possible to increase the number and improve the playability by utilizing the free area of the ROM corresponding to the increased capacity.

[10th game machine]
Conventionally, in the game machine having the above-described configuration, a game machine controlled by a timer subtraction process by software is known (see, for example, Japanese Patent Application Laid-Open No. 2004-041261).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above-mentioned fifth problem, and a fifth object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the fifth problem, the present invention provides a tenth gaming machine having the following configuration.

An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling a game operation, and a first storage means (for example, the main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. And a second storage means (for example, main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means, the calculation processing means counts the number of timers of a soft timer (for example). For example, in the timer update process), by executing a predetermined update instruction (for example, "DCPWLD" instruction) that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction, the current soft timer of the soft timer The number of timers is compared with the lower limit of the number of timers, and if the current number of timers of the soft timer is larger than the lower limit, the number of timers of the soft timer is subtracted and updated, and the current number of timers of the soft timer is updated. When is equal to or less than the lower limit value, the gaming machine is characterized in that the number of timers of the soft timer is held at the lower limit value.

In the tenth gaming machine of the present invention, the soft timer may be a 2-byte soft timer.

Further, in the tenth gaming machine of the present invention, the arithmetic processing means has a fixed cycle processing means (for example, an interrupt process repeatedly executed at a cycle of 1.1172 msec) that performs processing at a fixed cycle. The counting process of the number of timers by the soft timer is executed by the fixed cycle processing means, and the elapsed time of the soft timer is determined based on the cycle of processing by the fixed cycle processing means and the number of timers. You may do so.

Further, in the tenth gaming machine of the present invention, the processing by the fixed cycle processing means is executed based on the interrupt signal generated by the timer function (for example, the timer circuit 113) built in the arithmetic processing means. You may do so.

According to the tenth gaming machine of the present invention having the above configuration, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit. It is possible to provide a gaming machine capable of enhancing game playability by utilizing the free area of the ROM corresponding to the increased capacity.

[11th and 12th game machines]
Conventionally, in the game machine having the above-described configuration, there is known a game machine that displays the internal lottery result with a 7-segment LED by controlling the main control circuit (see, for example, Japanese Patent Application Laid-Open No. 2008-237337).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above-mentioned sixth problem, and a sixth object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the sixth problem, the present invention provides an eleventh gaming machine having the following configuration.

An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the game operation, a plurality of 7-segment LEDs for notifying specific information about the game, and a 7-segment LED drive for driving the plurality of 7-segment LEDs. Necessary for executing the arithmetic processing by the means (for example, 7-segment LED drive processing), the LED drive control means that controls the drive operation of the plurality of 7-segment LEDs by the 7-segment LED drive means, and the arithmetic processing means. A first storage means (for example, main ROM 102) in which various information is stored, and a second storage means (for example, main RAM 103) in which information necessary for executing the calculation process by the calculation processing means is stored. The LED drive control means performs dynamic drive control on the plurality of 7-segment LEDs, executes a predetermined read command (for example, "LDW" command), and is common to the plurality of 7-segment LEDs. A gaming machine characterized in that selection data and cathode data are output at the same time.

Further, in the eleventh gaming machine of the present invention, the arithmetic processing means has a fixed cycle processing means (for example, an interrupt process repeatedly executed at a cycle of 1.1172 msec) that performs processing at a fixed cycle. The constant cycle processing means may count the number of times the process is executed by the fixed cycle processing means, and when the counted value is an even number, the control process by the LED drive control means may be executed. ..

Further, in order to solve the sixth problem, the present invention provides a twelfth gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, the variable display means (for example, three reels 3L, 3C, 3R) that variablely displays the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. A stop control means (for example, a reel stop control process) to be caused, an instruction display (for example, an instruction monitor) including a plurality of 7-segment LEDs for notifying information regarding a stop operation of the variation display of the plurality of display columns, and the plurality of instructions. 7-segment LED driving means (for example, 7-segment LED driving processing) for driving the 7-segment LED, and arithmetic processing for controlling the driving operation of the plurality of 7-segment LEDs by the 7-segment LED driving means. For executing the arithmetic processing by the means (for example, the main CPU 101), the first storage means (for example, the main ROM 102) in which the information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and the arithmetic processing means. A second storage means (for example, main RAM 103) for storing necessary information is provided, and the arithmetic processing means performs dynamic drive control on the plurality of 7-segment LEDs to perform a predetermined read instruction (for example, for example). A gaming machine characterized in that common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs by executing the "LDW" command).

Further, in the twelfth gaming machine of the present invention, the arithmetic processing means includes a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and a general-purpose register when the arithmetic processing is executed by the arithmetic processing means. The data is stored, and the stored data has an expansion register (for example, a Q register) capable of designating a part of the address in the second storage means, and the arithmetic processing means uses the expansion register. By executing a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means, the second storage means is arranged and the plurality of display columns are changed. The address of the stop operation instruction information storage area (for example, the navigation data storage area) for storing the information related to the display stop operation is specified, and the information related to the stop operation of the variable display of the plurality of display columns is stored. It may be stored in the area.

According to the eleventh and twelfth gaming machines of the present invention having the above configuration, the capacity of processing programs and tables managed by the main control circuit is reduced to reduce the free capacity of the ROM (first storage means) of the main control circuit. It is possible to increase the number and improve the playability by utilizing the free area of the ROM corresponding to the increased capacity.

[13th game machine]
Conventionally, in a game machine having the above-described configuration, a game machine in which a game control board (main control board) controls a reel unit is known (see, for example, Japanese Patent Application Laid-Open No. 2012-034914).

By the way, in the rotation control of the reel (rotating cylinder), the lack of stability of the rotation operation of the reel causes discomfort to the player (especially a skilled person), and there is a possibility that the discomfort may reduce the interest of the game. There is. In this case, the game store may be disadvantaged and the sales of the game machine itself may be affected.

The present invention has been made to solve the above-mentioned seventh problem, and a seventh object of the present invention is to suppress a lack of stability in the rotation operation of the reel and not to give a player discomfort. It is to provide a gaming machine that can be used.

In order to solve the seventh problem, the present invention provides a thirteenth gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A variable display means (for example, three reels 3L, which includes a start switch 79) and a plurality of display columns and variablely displays a symbol provided in each display column based on the detection of a start operation by the start operation detecting means. 3C, 3R), a stop operation detecting means (for example, a stop switch board 80) that detects a stop operation by a player, and an arithmetic processing means (for example, a main CPU 101) that performs arithmetic processing for controlling a game operation. The first storage means (for example, the main ROM 102) in which the information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and the information necessary for executing the arithmetic processing by the arithmetic processing means are stored. The two storage means (for example, the main RAM 103) and the setting switch for initializing a predetermined area of the second storage means (for example, the setting key type switch 54) are provided, and the arithmetic processing means is described as described above. The internal winning combination determining means (for example, internal lottery processing) that determines the internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, the determination result of the internal winning combination determining means, and the stop. Based on the detection of the stop operation by the operation detection means, the stop control means (for example, reel stop control processing) for stopping the variation display of the symbol, and the input state and output port of the input port when a power failure occurs when the power is restored. When the output state of the above is set and the display column is fluctuating when the power failure occurs, the fluctuation control management information of the display column at the time of the power failure stored in the second storage means (for example, It is characterized by having a game return means (for example, a game return process) that clears the reel control management information) and sets the change control management information of the display column with information instructing the start of change of the display column. A game machine to play.

Further, in the thirteenth game machine of the present invention, when the setting switch is in the off state, the arithmetic processing means executes the process by the game return means, and when the setting switch is in the on state. Alternatively, the predetermined area of the second storage means may be initialized without executing the process by the game return means.

According to the thirteenth gaming machine of the present invention having the above configuration, it is possible to suppress the lack of stability of the reel rotation operation (variation display operation of the display row) so as not to give the player discomfort. ..

[14th game machine]
Conventionally, in a game machine having the above-described configuration, a game machine capable of displaying a set value (1 to 6) by operating a setting change switch is known (for example, Japanese Patent Application Laid-Open No. 2008-245704 and Japanese Patent Application Laid-Open No. 2008-245704). 2013-042870 (see).

By the way, conventionally, while a game is being played in a game state advantageous to the player, such as during a bonus game or an ART game, a game machine whose set value cannot be confirmed is the mainstream. In such a game machine, if a bonus game or an ART game is started immediately after a cheating called "goto", the cheating cannot be confirmed, which may be disadvantageous to the game store. is there.

The present invention has been made to solve the above-mentioned eighth problem, and an eighth object of the present invention is to play a game even while the game is being played in a gaming state which is advantageous to the player. It is to provide a game machine capable of confirming information such as set values and deterring fraudulent acts such as goto.

In order to solve the eighth problem, the present invention provides a fourteenth gaming machine having the following configuration.

Necessary for executing the arithmetic processing by the setting switch arranged at a predetermined position inside the game machine main body, the arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the game operation, and the arithmetic processing means. A first storage means (for example, main ROM 102) in which various information is stored, a second storage means (for example, main RAM 103) in which information necessary for executing the calculation process by the calculation processing means is stored, and a game medium. A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the player, and a starting operation detecting means (for example, a start switch) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. 79), an internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the starting operation by the starting operation detecting means, and the internal winning combination determining means. Based on the determined internal winning combination, the advantageous gaming means (for example, a bonus game described later) that executes a gaming state advantageous to the player, and the probability that the internal winning combination is determined according to the operation of the setting switch. Based on the detection of the start operation by the start operation detection means, which includes a setting change confirmation means (for example, S233 during the medal reception / start check process) capable of changing or confirming the setting value according to the above, and a plurality of display columns. A variable display means (for example, three reels 3L, 3C, 3R) for variablely displaying a symbol provided in each display row and a stop operation detecting means (for example, a stop switch board 80) for detecting a stop operation by a player. A stop control means (for example, reel stop control process) for stopping the variation display of the symbol based on the determination result of the internal winning combination determination means and the detection of the stop operation by the stop operation detection means, and the game. The game start determination means (for example, medal reception / start check processing) for determining whether or not the start is possible is provided, and the setting change confirmation means receives an internal win in response to an operation of the setting switch when the power is turned on. When it is possible to change the set value related to the probability that the winning combination is determined, it is determined that the game can be started by the game start determination means, and the setting switch is operated, the inside is irrespective of the game state. A gaming machine characterized in that a set value related to the probability that a winning combination is determined can be confirmed by processing by the setting change confirmation means.

Further, in the fourteenth game machine of the present invention, when the power is turned on to the game machine while the setting switch is operated, the setting change confirmation means has a predetermined storage area of the second storage means. May be initialized, the set value may be changed, and the changed set value may be stored in the second storage means.

According to the fourteenth gaming machine of the present invention having the above configuration, even during a game being played in a gaming state advantageous to the player, such as during a bonus game or an ART game, the set value and the like can be set. Information can be confirmed, and fraudulent acts such as goto can be deterred.

[15th and 16th game machines]
Conventionally, in the game machine having the above-described configuration, a game machine provided with a display device for displaying the number of inserted medals is known (see, for example, Japanese Patent Application Laid-Open No. 1999-197883).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the above-mentioned ninth problem, and a ninth object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the ninth problem, the present invention provides a fifteenth gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, an internal lottery process) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. Detected by the stop control means (for example, reel stop control process), the game medium detection means (for example, the medal sensor) for detecting the reception state (for example, the medal sensor input state) of the game medium, and the game medium detection means. A game medium reception state determination means for determining whether or not the current change mode of the reception state of the game medium is normal, based on the reception state of the game medium detected in the previous process, by arithmetic processing. (For example, S255 to S258 during the medal insertion check process) and a gaming machine.

In the fifteenth game machine of the present invention, the game medium reception state determining means is a normal value of the reception state of the game medium that can be detected in the current process based on the reception state of the game medium detected in the previous process. May be calculated by a logical operation, and the normal value may be compared with the current reception state of the game medium to determine whether or not the change mode of the reception state of the game medium is normal. ..

Further, in the fifteenth game machine of the present invention, the game medium reception state determination means determines whether or not the change mode of the reception state of the game medium is normal by two bits in the 1-byte information. You may do so.

In order to solve the ninth problem, the present invention provides a sixteenth gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, internal lottery processing) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. Stop control means (for example, reel stop control processing) and display means (for example, first LED to third LED) for notifying information indicating the number of input of the game medium in a display mode corresponding to the number of input of the game medium. And the arithmetic processing means (for example, the main CPU 101, the medal insertion processing) that performs the arithmetic processing for controlling the notification operation by the display means, and the information necessary for executing the arithmetic processing by the arithmetic processing means are stored. The arithmetic processing means includes a first storage means (for example, a main ROM 102) and a second storage means (for example, a main RAM 103) for storing information necessary for executing the arithmetic processing by the arithmetic processing means. , The lighting control data for notifying the information indicating the number of input of the game medium in a display mode corresponding to the number of input of the game medium is generated by a logical operation process based on the number of input of the game medium. A game machine to be.

Further, in the sixteenth game machine of the present invention, in the logical operation process, the lighting control data of the game medium may be generated from three-bit data of information within one byte.

According to the fifteenth and sixteenth gaming machines of the present invention having the above configuration, the capacity of the processing program and the table managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the increased capacity is increased. The playability can be improved by using the free area of the ROM of the minute.

[17th and 18th game machines]
Conventionally, in a game machine having the above-described configuration, a game machine in which a main board (main control board) and a sub board (sub control board) are connected by communication and a command is transmitted from the main board to the sub board is known. (See, for example, Japanese Patent No. 5725590).

By the way, conventionally, the communication between the main control board that controls the game and the sub-control board that controls the effect is one-way communication from the main control board to the sub-control board, and when the power is turned on. There is a large gap between the start-up time of the main control board and that of the sub-control board. Therefore, the communication connection between the main control board and the sub control board at the time of turning on the power may become unstable.

The present invention has been made to solve the tenth problem, and a tenth object of the present invention is a main control board (main control means) and a sub control board (sub control means) at the time of turning on the power. The purpose of the present invention is to provide a game machine capable of stably operating communication between the two.

In order to solve the tenth problem, the present invention provides a seventeenth gaming machine having the following configuration.

A main control means (for example, a main control circuit 90) for transmitting communication data related to a game operation is provided, and the main control means executes an interrupt process at a predetermined cycle during a control process by the main control means to interrupt. When there is no communication data related to the game operation at the time of processing execution, an interrupt processing execution means (for example, interrupt processing) that sends a non-operation command and a power restoration processing execution that executes a predetermined power restoration processing when the power is restored. The means (for example, power-on processing) is provided, and the power restoration processing executing means waits after the power restoration processing is started until the interrupt processing can be executed by the interrupt processing executing means. Processing (for example, S7 and S8 during power-on processing) is performed, and the interrupt processing executing means executes the interrupt processing at the end of the standby by the power restoration processing executing means to perform the non-operation command. Is transmitted to the sub-control means.

Further, in the seventeenth gaming machine of the present invention, the main control means performs the interrupt processing based on the timer circuit (for example, timer circuit 113) for measuring the predetermined cycle and the timeout signal of the timer circuit. It has an interrupt circuit (for example, an interrupt controller 112) that generates an interrupt signal for execution, and the power recovery processing execution means sets the initial setting for generating the timeout signal in the predetermined cycle. After setting in the timer circuit, a process of waiting until the interrupt process can be executed by the interrupt process executing means is performed, and the end of the wait is based on the presence or absence of the timeout signal of the timer circuit. You may make a judgment.

Further, in order to solve the tenth problem, the present invention provides an eighteenth gaming machine having the following configuration.

Arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling game operation, and communication data generation means (for example, setting change command generation and storage processing and communication data storage processing) that create command data related to game operation. , The interrupt processing execution means that executes the interrupt processing at a predetermined cycle during the control processing by the arithmetic processing means and transmits a non-operation command when there is no command data related to the game operation at the time of executing the interrupt processing ( For example, interrupt processing), power restoration processing execution means (for example, power-on processing) that executes a predetermined power restoration processing at the time of power restoration, and information necessary for executing the arithmetic processing by the arithmetic processing means are stored. The power is restored by providing the first storage means (for example, the main ROM 102) and the second storage means (for example, the main RAM 103) for storing the information necessary for executing the arithmetic processing by the arithmetic processing means. After the start of the power recovery process, the process execution means performs a process of waiting until the interrupt process can be executed by the interrupt process execution means (for example, S7 and S8 during the power-on process), and the process is described. The interrupt processing executing means executes the interrupt processing and transmits the non-operation command at the end of the standby by the power recovery processing executing means, and the arithmetic processing means performs the arithmetic processing by the arithmetic processing means. Has a plurality of general-purpose registers in which a plurality of types of data are stored at the time of execution, the command data is composed of a command type, a plurality of communication parameters, and a sum value, and the plurality of the communication parameters are each a plurality of. The communication data generation means assigned to the general-purpose register is set in the general-purpose register after setting the communication parameter in the general-purpose register assigned to the communication parameter according to the command type of the command data. Communication parameters are stored in a predetermined storage area (for example, communication data temporary storage area) in the second storage means, and among the plurality of communication parameters, communication parameters that are not used based on the command type of the command data. Even if there is, the data stored in the general-purpose register associated with the unused communication parameter is stored as the communication parameter in the predetermined storage area, and the command type and the communication parameter are assigned. A gaming machine characterized in that a sum value of the command data is generated based on the data stored in a general-purpose register.

Further, the eighteenth gaming machine of the present invention includes a power supply monitoring means (for example, a power supply monitoring port) for monitoring the state of the power supply voltage, and the arithmetic processing means is in the case where the state of the power supply voltage is not stable. After initializing the timer circuit, serial communication circuit, and random number circuit of the arithmetic processing means on the condition that the state of the power supply voltage is stable, the timer circuit, the serial communication circuit, and the random number circuit of the arithmetic processing means are initialized. It is confirmed whether or not the second storage means is normal by using the predetermined area of the second storage means, and the no-operation command is transmitted on condition that the second storage means is normal. You may do so.

According to the 17th and 18th gaming machines of the present invention having the above configuration, it is possible to stably operate the communication between the main control board and the sub control board when the power is turned on.

[19th and 20th game machines]
Conventionally, in the game machine having the above-described configuration, for example, a game machine that executes a control called pull-in control of the winning symbol of the reel and a control called kicking control of the winning symbol of the reel is known based on the lottery result. (See, for example, Japanese Patent Application Laid-Open No. 2002-219213).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Furthermore, in recent years, as the playability has become complicated and the pattern combination pattern of the winning combination (winning combination) has increased, the RAM capacity of the main control circuit has been squeezed, and the efficiency of the processing executed by the main control circuit has been improved. , Development of technology that can effectively utilize the limited RAM capacity of the main control circuit is required.

The present invention has been made to solve the eleventh problem, and the eleventh object of the present invention is to improve the efficiency of processing executed by the main control circuit and to make the RAM capacity of the main control circuit effective. It is to provide a game machine that can be utilized.

In order to solve the eleventh problem, the present invention provides a nineteenth gaming machine having the following configuration.

An arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling a game operation, and a first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. And a second storage means (for example, main RAM 103) in which information necessary for executing the calculation process by the calculation processing means is stored, the calculation processing means has a predetermined probability of internal winning. An internal lottery means (for example, internal lottery processing) that determines flag status information (for example, a winning request flag status) related to a combination, and an internal winning combination that generates an internal winning combination from the flag status information acquired by the internal lottery means. Correspondence between the generation means (for example, S321 during the symbol setting process), the internal winning combination, the corresponding flag data, and the storage destination data that specifies the storage destination of the flag data in the second storage means. The flag table expanding means (for example, S324 during the symbol setting process) that defines the above and expands the flag data table (for example, the hit request flag table) stored in the first storage means in the second storage means. With the flag storage area designating means (for example, S329 during the symbol setting process) that is arranged in the second storage means and specifies the address of the flag data storage area (for example, the hit request flag storage area) that stores the flag data. , A flag that transfers and stores the flag data corresponding to the internal winning combination generated by the internal winning combination generating means from the flag table into the flag data storage area based on the corresponding storage destination data. A gaming machine characterized by having a data storage means (for example, S330 during a symbol setting process).

Further, in the nineteenth game machine of the present invention, the arithmetic processing means calculates on-bit information indicating the storage destination data of the flag data table and sets it as the on-bit information to be transferred. The flag data may be transferred to the flag data storage area.

Further, in order to solve the eleventh problem, the present invention provides a twentieth game machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A variable display means (for example, three reels 3L, which includes a start switch 79) and a plurality of display columns and variablely displays a symbol provided in each display column based on the detection of a start operation by the start operation detecting means. 3C, 3R), a stop operation detecting means (for example, a stop switch board 80) that detects a stop operation by a player, and an arithmetic processing means (for example, a main CPU 101) that performs arithmetic processing for controlling a game operation. The first storage means (for example, the main ROM 102) in which the information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and the information necessary for executing the arithmetic processing by the arithmetic processing means is stored. The arithmetic processing means includes two storage means (for example, a main RAM 103), and the arithmetic processing means includes a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and execution of the arithmetic processing by the arithmetic processing means. Data is sometimes stored, and an expansion register (for example, a Q register) that can specify a part of the address in the first storage means or the second storage means by the stored data, and a predetermined probability. An internal lottery means (for example, an internal lottery process) that determines flag status information (for example, a winning request flag status) related to an internal winning combination, and an internal that generates an internal winning combination from the flag status information acquired by the internal lottery means. Winning combination generating means (for example, S321 during the symbol setting process), the internal winning combination, the corresponding winning flag data, and the storage destination data for designating the storage destination of the winning flag data in the second storage means. The winning flag table expanding means (for example, S324 during the symbol setting process) that expands the winning flag data table (for example, the winning request flag table) that defines the correspondence with the second storage means, and the expansion register. By executing a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means, the data is arranged in the second storage means and the winning flag data is stored. Winning flag storage area designating means for designating the address of the winning flag data storage area (for example, hit request flag storage area) (for example, S329 during the symbol setting process) and the inside. The winning flag data corresponding to the internal winning combination generated by the winning combination generating means is transferred from the winning flag table to the winning flag data storage area and stored based on the corresponding storage destination data. A stop control means for stopping the variation display of the symbol based on the flag data storage means (for example, S330 during the symbol setting process), the determination result of the internal lottery means, and the detection of the stop operation by the stop operation detection means. (For example, reel stop control processing) and when the variable display of the plurality of display columns is stopped by the stop control means, the internal winning combination is placed on a determination line set across the plurality of display columns. By executing the winning combination determining means (for example, winning search processing) for determining whether or not the combination of symbols corresponding to is stopped and displayed, and the predetermined reading command, the combination is arranged in the second storage means. Winning flag storage area designating means (for example, symbol) for designating the address of the winning flag data storage area (for example, winning operation flag storage area) for storing the winning flag data corresponding to the combination of symbols stopped and displayed on the determination line. By executing S648) during the code acquisition process and the predetermined read command, the symbol code data corresponding to the combination of the symbols arranged in the second storage means and stopped and displayed on the determination line is stored. A gaming machine characterized by having a symbol code storage area setting means (for example, S650 during a symbol code acquisition process) for designating an address of a symbol code storage area.

Further, in the twentieth game machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

According to the 19th and 20th gaming machines of the present invention having the above configuration, it is possible to improve the efficiency of the processing executed by the main control circuit and effectively utilize the RAM (second storage means) capacity of the main control circuit. ..

[21st and 22nd game machines]
Conventionally, in the game machine having the above-described configuration, the stop control of the variable display of the reel symbol is performed based on the internal winning combination and the stop operation of the player, the winning judgment is made by the combination of the symbols, and the hopper is determined based on the result of the winning judgment. A gaming machine that controls (medal payout device) to control medal payout is known (see, for example, Japanese Patent Application Laid-Open No. 2008-119498).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the twelfth problem, and a twelfth object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the twelfth problem, the present invention provides a twenty-first gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, internal lottery processing) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. The stop control means (for example, reel stop control process) to be caused, the arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the stop operation of the display column by the stop control means, and the arithmetic processing means. A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing is stored, and a second storage means (for example, for example) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. The arithmetic processing means includes a main RAM 103), and the arithmetic processing means stores a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and data is stored when the arithmetic processing is executed by the arithmetic processing means. An expansion register (for example, a Q register) capable of designating a part of an address in the second storage means by the stored data, and an address designation in the second storage means can be performed using the expansion register. The stop operation detection result acquisition means (for example, S714 during the reel stop control process) that acquires the detection result of the stop operation by the stop operation detection means by executing a predetermined read command (for example, the “LDQ” command) that can be performed. When the stop operation of the player with respect to the predetermined display row is detected by the stop operation detection means, by executing the predetermined read command, the data is arranged in the second storage means and the predetermined display is displayed. Stop control data storage area setting means for designating the address of the stop control data storage area for storing the stop control data of the column variation display (for example, the source code "LDQ IX, wR1_CTRL- (wR)" in FIG. 139. 2_CTRL-wR1_CTRL) "), and a gaming machine characterized by having.

Further, in the 21st gaming machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

Further, in order to solve the twelfth problem, the present invention provides a 22nd game machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, internal lottery processing) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. When a plurality of types of internal winning combinations are determined by the stop control means (for example, reel stop control processing) and the internal winning combination determining means, a plurality of types of symbols corresponding to the plurality of types of internal winning combinations are used. Among the combinations, the priority stop symbol determination means (for example, the pull-in priority acquisition process) for determining the combination of the symbols to be preferentially stopped and displayed on the determination line set across the plurality of display columns, and the above. An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the stop operation of the display column by the stop control means and the determination operation of the combination of symbols to be stopped and displayed by the priority stop symbol determination means, and the said. A first storage means (for example, main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and a second storage in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. The arithmetic processing means includes means (for example, a main RAM 103), and the arithmetic processing means includes a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and data when the arithmetic processing is executed by the arithmetic processing means. Is stored, and an expansion register (for example, a Q register) that can specify a part of the address in the second storage means by the stored data, and an address designation in the second storage means using the expansion register. The stop operation detection result acquisition means (for example, the reel stop control process) for acquiring the detection result of the stop operation by the stop operation detection means by executing a predetermined read command (for example, the “LDQ” command). With S714) inside When the player's stop operation with respect to the predetermined display row is detected by the stop operation detecting means, the stop operation is arranged in the second storage means and the predetermined display row is executed by executing the predetermined read command. With the stop control data storage area setting means for designating the address of the stop control data storage area for storing the stop control data of the fluctuation display (for example, the source code "LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)" in FIG. 139). In the process of determining the combination of symbols to be stopped and displayed on the determination line with priority by the priority stop symbol determining means, a comparison determination instruction, a process jump destination address designation instruction, and a process jump operation instruction are issued. By executing a predetermined judgment command (for example, "JCP" command) that can be executed by one command, a specific display column currently being judged (for example, a combination of symbols corresponding to the internal winning combination to be judged) ( For example, it is determined whether or not a predetermined combination of symbols (for example, "ANY" combination) in which the stop symbol on the determination line on the right reel 3R) is included is determined, and the internal winning combination to be determined is determined. When it is determined that the combination of symbols corresponding to is included in the combination of the predetermined symbols, the arbitrary combination handling processing means (for example,) for prohibiting the stop display of the combination of symbols corresponding to the internal winning combination to be determined. , S683) in the process of acquiring the pull-in priority, and the gaming machine.

Further, in the 22nd gaming machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

According to the 21st and 22nd gaming machines of the present invention having the above configuration, the capacity of the processing program and the table managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the increased capacity is increased. The playability can be improved by using the free area of the ROM of the minute.

[23rd to 25th game machines]
Conventionally, in the game machine having the above-described configuration, there is known a game machine that controls the stop of a symbol by using a pull-in priority table at the time of stop control of a symbol (see, for example, Japanese Patent Application Laid-Open No. 2007-175450).

By the way, conventionally, as a limitation peculiar to the above-mentioned gaming machine, the program capacity of the main control circuit is limited to a small capacity by a rule. Further, in recent years, the capacity of the ROM of the main control circuit has been squeezed due to the complexity of game playability, and there is a demand for reducing the capacity of processing programs and tables managed by the main control circuit.

The present invention has been made to solve the thirteenth problem, and the thirteenth object of the present invention is to reduce the capacity of a processing program, a table, etc. managed by the main control circuit to reduce the capacity of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space of the ROM and enhancing the game playability by utilizing the free area of the ROM corresponding to the increased capacity.

In order to solve the thirteenth problem, the present invention provides a twenty-third gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, internal lottery processing) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. When a plurality of types of internal winning combinations are determined by the stop control means (for example, reel stop control processing) and the internal winning combination determining means, a plurality of types of symbols corresponding to the plurality of types of internal winning combinations are used. Among the combinations, the priority stop symbol determination means (for example, the pull-in priority acquisition process) for determining the combination of the symbols to be preferentially stopped and displayed on the determination line set across the plurality of display columns, and the above. Necessary for execution of the arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling the determination operation of the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, and the arithmetic processing by the arithmetic processing means. A first storage means (for example, main ROM 102) in which various information is stored, and a second storage means (for example, main RAM 103) in which information necessary for executing the calculation process by the calculation processing means is stored. The arithmetic processing means is a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and data is stored when the arithmetic processing is executed by the arithmetic processing means. In a process of having an expansion register (for example, a Q register) capable of designating a part of an address in the second storage means, and determining a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means. , The arithmetic processing means uses the expansion register to execute a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means, thereby causing the second storage means. It is placed inside and the internal winning combination The winning flag storage area specifying means (for example, S686 during the pull-in priority acquisition process) that specifies the address of the winning flag data storage area (for example, the winning request flag storage area) that stores the winning flag data corresponding to the above. By executing the read command of, the winning flag data storage area (for example, winning operation) for storing the winning flag data corresponding to the combination of the symbols arranged in the second storage means and stopped and displayed on the determination line. The logical product of the winning flag storage area designating means (for example, S686 during the attraction priority acquisition process) that specifies the address of the flag storage area), the winning flag data, and the corresponding winning flag data. A gaming machine characterized by having a calculation means (for example, S686 during a pull-in priority acquisition process).

Further, in the 23rd game machine of the present invention, in the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, the combination of symbols corresponding to the internal winning combination to be determined. Includes a combination of predetermined symbols (for example, "ANY" combination) in which the stop symbol on the determination line in the specific display column (for example, the right reel 3R) currently being determined is arbitrary. The arithmetic processing means includes address designation processing of the winning flag data storage area by the winning flag storage area designating means, address designation processing of the winning flag data storage area by the winning flag storage area designating means, and AND operation. The logical product operation processing by the means may not be executed.

Further, in order to solve the thirteenth problem, the present invention provides a twenty-fourth gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, internal lottery processing) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. When a plurality of types of internal winning combinations are determined by the stop control means (for example, reel stop control processing) and the internal winning combination determining means, a plurality of types of symbols corresponding to the plurality of types of internal winning combinations are used. Among the combinations, the priority stop symbol determination means (for example, the pull-in priority acquisition process) for determining the combination of the symbols to be preferentially stopped and displayed on the determination line set across the plurality of display columns, and the above. Necessary for execution of the arithmetic processing means (for example, main CPU 101) that performs arithmetic processing for controlling the determination operation of the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, and the arithmetic processing by the arithmetic processing means. A first storage means (for example, main ROM 102) in which various information is stored, and a second storage means (for example, main RAM 103) in which information necessary for executing the calculation process by the calculation processing means is stored. The arithmetic processing means is a general-purpose register in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and data is stored when the arithmetic processing is executed by the arithmetic processing means. A symbol having an expansion register (for example, a Q register) capable of designating a part of an address in the first storage means or the second storage means, and preferentially stopped and displayed by the priority stop symbol determining means. In the process of determining the combination, the arithmetic processing means executes a predetermined read instruction (for example, "LDQ" instruction) capable of designating an address in the second storage means using the expansion register. , Placed in the second storage means In addition, the winning flag storage area specifying means for designating the address of the winning flag data storage area (for example, the hit request flag storage area) for storing the winning flag data corresponding to the internal winning combination (for example, during the attraction priority acquisition process). S686) and the winning flag data storage that stores the winning flag data corresponding to the combination of the symbols arranged in the second storage means and stopped and displayed on the determination line by executing the predetermined read command. The logic of the winning flag storage area designating means (for example, S686 during the attraction priority acquisition process) that specifies the address of the area (for example, the winning operation flag storage area), the winning flag data, and the corresponding winning flag data. A combination of symbols to be stopped and displayed between the combination of the logical product calculation means for performing the product operation (for example, S686 during the pull-in priority acquisition process) and the combination of the plurality of types of symbols by executing the predetermined read command. A gaming machine characterized by having a priority data table acquisition means (for example, S687 during a pull-in priority acquisition process) for acquiring a data table for which priority is defined.

Further, in the 24th game machine of the present invention, in the process of determining the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means, the combination of symbols corresponding to the internal winning combination to be determined. Includes a combination of predetermined symbols (for example, "ANY" combination) in which the stop symbol on the determination line in the specific display column (for example, the right reel 3R) currently being determined is arbitrary. The arithmetic processing means includes address designation processing of the winning flag data storage area by the winning flag storage area designating means, address designation processing of the winning flag data storage area by the winning flag storage area designating means, and AND operation. The logical product operation processing by the means may not be executed.

Further, in order to solve the thirteenth problem, the present invention provides a twenty-fifth gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, internal lottery processing) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. A stop control means (for example, a reel stop control process) to be caused, an error detection means for determining the presence / absence of an illegal hit error (for example, an illegal hit check process), and an operation for controlling the determination operation by the error detection means. The arithmetic processing means (for example, the main CPU 101) that performs the processing, the first storage means (for example, the main ROM 102) in which the information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and the arithmetic processing means. A general-purpose storage means (for example, main RAM 103) for storing information necessary for executing arithmetic processing is provided, and the arithmetic processing means stores data when the arithmetic processing is executed by the arithmetic processing means. A register, an extension register (for example, a Q register) in which data is stored when the arithmetic processing is executed by the arithmetic processing means and a part of an address in the second storage means can be specified by the stored data. In the process of determining whether or not an illegal hit error has occurred by the error detecting means, the arithmetic processing means can specify an address in the second storage means by using the expansion register. By executing a read command (for example, a "LDQ" command), it corresponds to a combination of symbols arranged in the second storage means and stopped and displayed on a determination line set across the plurality of display columns. Winning flag storage area specifying means for specifying the address of the winning flag data storage area (for example, winning operation flag storage area) for storing the winning flag data (for example, illegal hit check processing) A logical product calculation means (for example, illegal) that performs a logical product calculation of S781) in the process, the winning flag data stored in the winning flag data storage area, and the winning flag data indicating the corresponding internal winning combination. It has S784) during the hit check process and an error determination means (for example, S785 during the illegal hit check process) for determining whether or not an illegal hit error has occurred based on the calculation result by the logical product calculation means. A gaming machine characterized in that the configuration of the winning flag data storage area (for example, the winning request flag storage area) in which the winning flag data is stored is the same as the configuration of the winning flag data storage area.

Further, in the 25th gaming machine of the present invention, a part of the address that can be specified by the expansion register may be an upper address value that constitutes the address.

Further, in the 25th gaming machine of the present invention, the arithmetic processing means has an error processing means for performing error processing when it is determined by the error detecting means that there is an illegal hit error. The error processing means may visually notify the illegal hit error and stop the game until the illegal hit error is cleared.

According to the 23rd to 25th gaming machines of the present invention having the above configuration, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit, and the increased capacity is increased. The playability can be improved by using the free area of the ROM of the minute.

[26th game machine]
Conventionally, in a game machine having the above-described configuration, a game machine that transmits command data from a game control board (main control board) to an effect control board (sub-control board) is known (for example, Japanese Patent Application Laid-Open No. 2013-027655). And Japanese Patent Application Laid-Open No. 2014-033751).

By the way, in recent years, with the diversification of playability, there is a tendency that the processing related to playability increases in the effect control by the sub-control circuit. Therefore, a fraudulent act called "goto" that falsifies the communication data transmitted from the main control circuit to the sub control circuit has occurred, causing damage to the amusement store. On the other hand, conventionally, as proposed in Japanese Patent Application Laid-Open No. 2014-033751 and the like, measures have been taken to prevent the transmission data from being squeezed in the main control circuit. However, the addition of such anti-goto processing causes a problem that the program capacity of the main control circuit is squeezed.

The present invention has been made to solve the above-mentioned fourteenth problem, and the fourteenth object of the present invention is to suppress fraudulent acts without performing fraud prevention processing on transmitted data, and at the same time. It is to provide a gaming machine capable of eliminating the pressure on the program capacity of the main control circuit due to fraud prevention processing.

In order to solve the 14th problem, the present invention provides a 26th gaming machine having the following configuration.

Data transmission means for transmitting communication data related to the game operation (for example, main control circuit 90), communication data generation means for creating the communication data (for example, communication data storage processing), and communication data by the communication data generation means. An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling the generation operation of the data, and a first storage means (for example, the main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. ) And a second storage means (for example, the main RAM 103) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and the arithmetic processing means is the arithmetic processing by the arithmetic processing means. Has a plurality of general-purpose registers in which a plurality of types of data are stored at the time of execution, and the arithmetic processing means has a plurality of types of communication parameters constituting the communication data in the communication data generation processing by the communication data generation means. Are assigned to the plurality of general-purpose registers, and among the plurality of types of communication parameters constituting the communication data, the communication parameters are set in the corresponding general-purpose registers among the plurality of general-purpose registers based on the type of the communication data. Then, the communication parameters set in the general-purpose register are stored in a predetermined storage area (communication data temporary storage area) in the second storage means, and among the plurality of types of communication parameters, the communication data is not generated at the time of generation. The data stored in the general-purpose register associated with the communication parameter used is stored in the predetermined storage area as a communication parameter, and the data set in the plurality of general-purpose registers is set according to the plurality of types of communication parameters. A gaming machine characterized in that a sum value of the communication data is generated based on the above.

Further, in the 26th gaming machine of the present invention, the communication data generating means is set in the plurality of general-purpose registers when there is no space in a predetermined storage area in the second storage means. The communication data generation process may be terminated without storing the parameters in the predetermined storage area in the second storage means.

According to the 26th gaming machine of the present invention having the above configuration, fraudulent activity can be suppressed without performing fraud prevention processing on the transmitted data (communication data), and the program capacity of the main control circuit by the fraud prevention processing. The pressure on the device can be eliminated.

[27th game machine]
Conventionally, in the game machine having the above-described configuration, a game machine having a function of updating the number of credits according to the number of medals paid out by the control of the main control circuit is known (for example, Japanese Patent Application Laid-Open No. 2009- 077977 (see).

By the way, conventionally, in games during ART or bonus, medals are paid out more frequently, but at this time, the payout interval for each medal is often controlled uniformly (constantly). In this case, a wasteful waiting time occurs during the medal payout period. Therefore, for example, in a long-time game such as ART, the game period becomes unnecessarily long, which may be a mental burden on the player.

The present invention has been made to solve the above fifteenth problem, and the fifteenth object of the present invention is to reduce unnecessary waiting time and reduce the mental burden on the player during the medal payout period. It is to provide a game machine capable of being able to do so.

In order to solve the fifteenth problem, the present invention provides a 27th gaming machine having the following configuration.

A closing operation detecting means (for example, BET switch 77) for detecting the closing operation of the game medium, and a starting operation detecting means (for example, for example) for detecting the starting operation by the player after the closing operation is detected by the closing operation detecting means. A start switch 79), an internal winning combination determining means (for example, internal lottery processing) that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means, and a plurality of display columns. Including, variable display means (for example, three reels 3L, 3C, 3R) that variablely display the symbols provided in each display column based on the detection of the start operation by the start operation detection means, and the stop operation by the player. The variation display of the symbol is stopped based on the determination result of the stop operation detecting means (for example, the stop switch board 80) for detecting the above, the determination result of the internal winning combination determining means, and the detection of the stop operation by the stop operation detecting means. When the change display of the plurality of display columns is stopped by the stop control means (for example, reel stop control process) and the stop control means, on the determination line set across the plurality of display columns. A privilege granting determination means (for example, a winning search process) for determining whether or not a combination of symbols corresponding to an internal winning combination related to the payout of the game medium is stopped and displayed, and the privilege grant determination means paying out the game medium. When it is determined that the combination of symbols corresponding to the internal winning combination according to the above is stopped and displayed on the determination line, the game medium payout means (for example, winning check / medal payout process) for paying out the game medium and the above A game medium storage means (for example, a credit function) for storing game media and an arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the payout operation of the game medium by the game medium payout means. In addition, the arithmetic processing means determines that the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed on the determination line by the privilege grant determination means, and the game medium storage means When the number of stored game media stored in the game medium is less than the upper limit, the game medium adding means for adding 1 to the number of stored game media (for example, S805 during the winning check / medal payout process). After the game medium is added to the stored number of the game media by the game medium addition means, the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed. The payout of all the payouts of the game media has been completed. When it is determined by the payout end determination means (for example, S807 during the winning check / medal payout process) and the payout end determination means that the total number of payouts of the game medium has not been paid out. The gaming machine is characterized by having a weight generating means (for example, S808 during the winning check / medal payout process) that generates a weight that invalidates the operation related to the game for a predetermined period.

Further, in the 27th gaming machine of the present invention, the arithmetic processing means has an interrupt processing executing means for executing interrupt processing at a predetermined cycle, and the operation related to the game by the wait generating means becomes invalid. In the wait, the interrupt process by the interrupt process execution means may be executed a predetermined number of times.

According to the 27th gaming machine of the present invention having the above configuration, it is possible to reduce unnecessary waiting time and reduce the mental burden on the player during the medal (game medium) payout period.

[28th and 29th game machines]
Conventionally, in the game machine having the above-described configuration, there is known a game machine in which a lottery table for determining an internal winning combination or an AT game is stored in a ROM (see, for example, Japanese Patent Application Laid-Open No. 2009-125459).

By the way, in the game machine described in JP-A-2009-125459, the lottery table and the lottery processing program of AT games are stored in a ROM provided on a sub-control board having a sufficient storage capacity. However, for reasons peculiar to the game machine industry in recent years, it is necessary to store the table and the program related to the lottery of the AT game in the ROM provided on the main control board. Therefore, the ROM capacity of the main control board, which is limited to a small capacity, is compressed.

The present invention has been made to solve the above 16th problem, and the 16th object of the present invention is to reduce the amount of data used in the processing of the main control circuit and to free the ROM of the main control circuit. It is to provide a game machine capable of increasing the capacity.

In order to solve the 16th problem, the present invention provides a 28th gaming machine having the following configuration.

A start operation detecting means (for example, a start switch 79) that detects a start operation by a player, and an internal winning combination determination that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means. Based on the means (for example, internal lottery processing) and the internal winning combination determined by the internal winning combination determining means, a privilege granting decision is made to determine by lottery whether or not to grant a gaming state advantageous to the player as a privilege. The lottery table includes means (for example, CT lottery processing during CT) and a lottery table referred to by the privilege grant determination means (for example, CT win lottery table during CT). Judgment data (for example, determination bit) that specifies the type of combination and the lottery value of the internal winning combination that is the lottery target specified in the determination data are defined, and the lottery value of the internal winning combination that is not subject to lottery. Is not specified, and a value other than 0 is specified for the lottery value of the internal winning combination of the lottery target having a winning probability of less than 100%, and the lottery value of the internal winning combination of the lottery target having a winning probability of 100%. A gaming machine characterized in that 0 is specified for.

Further, in the 28th game machine of the present invention, the privilege granting determining means acquires a 1-byte random number value from a soft latch random number, and draws a random number using the acquired random number value and the lottery value. , It may be decided whether or not to give a gaming state advantageous to the player as a privilege.

In order to solve the 16th problem, the present invention provides a 29th gaming machine having the following configuration.

A start operation detecting means (for example, a start switch 79) that detects a start operation by a player, and an internal winning combination determination that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means. Based on the means (for example, internal lottery processing) and the internal winning combination determined by the internal winning combination determining means, a privilege granting decision is made to determine by lottery whether or not to grant a gaming state advantageous to the player as a privilege. A means (for example, CT lottery processing during CT) and a lottery table (for example, a CT lottery table during CT) which is referred to by the privilege granting determination means and is provided for each type of the internal winning combination are currently determined. A lottery table selection table for selecting the lottery table associated with the internal winning combination (for example, a table selection relative table for each winning combination) is provided, and in the lottery table selection table, the type of the internal winning combination is provided. For each, a selection value that can determine whether or not the internal winning combination of the type is a lottery target and can specify the placement destination of the lottery table associated with the internal winning combination of the type is defined. The selection value of the internal winning combination that is not subject to lottery is defined as 0 in which the lottery result by the privilege granting determination means is treated as a loss, and the selection value of the internal winning combination that is subject to lottery is 0. A gaming machine characterized in that data other than the above are specified.

Further, in the 29th game machine of the present invention, the selection value of the lottery table selection table is a relative value up to the lottery table to be selected, and even if the relative value is a value of 1 byte. Good.

According to the 28th and 29th gaming machines of the present invention having the above configuration, the amount of data used in the processing of the main control circuit can be reduced, and the free space of the ROM of the main control circuit can be increased.

[30th game machine]
Conventionally, in the gaming machine having the above-described configuration, the program and the table are arranged in a fixed area in the ROM mounted on the main control board (see, for example, Japanese Patent Application Laid-Open No. 2012-110635).

By the way, the programs and tables that can be arranged in the ROM of the main control board like the game machine described in JP2012-110635A are limited by the rules of the game machine industry, and the ROM of the main control board. The extensibility of programs and tables within is extremely poor.

The present invention has been made to solve the above-mentioned seventeenth problem, and the seventeenth object of the present invention is a gaming machine capable of enhancing the expandability of a program and a table in a ROM of a main control board. Is to provide.

In order to solve the 17th problem, the present invention provides a 30th gaming machine having the following configuration.

An arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling a game operation, and a first storage means (for example, the main ROM 102) in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored. A second storage means (for example, a main RAM 103) for storing information necessary for executing the calculation process by the calculation processing means, and the first storage means is a game performed by a player. It is arranged in a game storage area (for example, a game ROM area) in which information necessary for executing a process related to the gameability of the game is stored, and an area different from the game storage area, and is executed by the player. A gaming machine characterized in that a non-standard storage area (for example, a non-standard ROM area) in which information necessary for executing a process not related to the game playability is stored is provided.

Further, in the thirtieth gaming machine of the present invention, the second storage means is for gaming in which information necessary for executing a process related to the playability of the game performed by the player is temporarily stored. The game playability of the game, which is arranged in an area different from the game temporary storage area (for example, the game RAM area) including the work area and the game stack area and the game temporary storage area, and is performed by the player. A non-standard work area for temporarily storing information necessary for executing processing that is not related to the non-standard and a non-standard temporary storage area (for example, a non-standard RAM area) including a non-standard stack area are provided. May be good.

Further, in the thirtieth gaming machine of the present invention, the arithmetic processing means has a stack pointer as a dedicated register, and the arithmetic processing means is a program stored in the non-specified storage area of the first storage means. When executing, the address of the non-standard stack area of the second storage means is set in the stack pointer, and when the program stored in the non-standard storage area of the first storage means is terminated, The address of the game stack area of the second storage means saved when the program stored in the non-standard storage area is executed is set in the stack pointer, and the game storage of the first storage area is set. You may return to the program stored in the area.

According to the thirtieth gaming machine of the present invention having the above configuration, the expandability of the program and the table in the ROM of the main control board can be enhanced.

[31st game machine]
Conventionally, in the gaming machine having the above-described configuration, in order to use the information of the internal winning combination determined by the main control circuit in the production control of the sub-control circuit, the internal winning combination is converted into a sub-flag that summarizes the types in group units. A gaming machine having a function is known (see, for example, Japanese Patent Application Laid-Open No. 2010-051471).

In the gaming machine described in JP-A-2010-051471, the conversion table and the conversion processing program for converting the internal winning combination into sub-flags are stored in a ROM provided on the sub-control board having a sufficient storage capacity. Has been done. However, for reasons peculiar to the amusement machine industry in recent years, it is no longer possible to transmit the information of the internal winning combination determined by the main control circuit to the sub control circuit, and a conversion table and a conversion processing program related to the sub flag are also provided on the main control board. It is necessary to store it in the ROM. In this case, these tables and programs put pressure on the ROM capacity of the main control board, which is limited to a small capacity. Therefore, it is required to develop a technology that can suppress the pressure on the ROM capacity of the main control board by the conversion table and conversion processing program related to the sub-flag, and can efficiently respond to changes in the model, planning, specifications, etc. of the game machine. ing.

The present invention has been made to solve the above-mentioned eighteenth problem, and the eighteenth object of the present invention is to suppress pressure on the ROM capacity of the main control board, and to obtain a model, plan, and specification of a game machine. It is to provide a game machine capable of efficiently responding to such changes.

In order to solve the 18th problem, the present invention provides a 31st gaming machine having the following configuration.

A start operation detecting means (for example, a start switch 79) that detects a start operation by a player, and an internal winning combination determination that determines an internal winning combination with a predetermined probability based on the detection of the start operation by the start operation detecting means. A first sub-flag conversion means (for example, a sub-flag conversion means) that converts a means (for example, an internal lottery process) and an internal winning combination determined by the internal winning combination determining means into a first sub-flag (for example, a sub-flag) with reference to a conversion table. For example, the sub-flag conversion process) and the first sub-flag obtained by the conversion process by the first sub-flag conversion means are referred to a lottery table (for example, various flag conversion lottery tables), and the second sub-flag is drawn by lottery. A second sub-flag conversion means (for example, flag conversion processing) for converting to (for example, sub-flag EX) is provided, and in the conversion table, the internal winning combination and the control status data associated with the internal winning combination are , The correspondence with the first sub-flag is defined, the control status data of the same value is assigned to the first sub-flag of the same type, and the lottery by the second sub-flag conversion means is the control status. A game machine characterized by being performed based on data.

Further, the gaming machine of the present invention includes a data transmitting means for transmitting command data related to the gaming operation, and the data transmitting means is triggered by the start operation detecting means detecting the start operation. The sub-flag of is transmitted as a communication parameter of command data.

According to the 31st gaming machine of the present invention having the above configuration, it is possible to suppress the pressure on the ROM capacity of the main control board and efficiently respond to changes in the model, planning, specifications, etc. of the gaming machine.

[32nd to 34th game machines]
In the gaming machine having the above-described configuration, Japanese Patent Application Laid-Open No. 2002-85629 is advantageous for the player, such as information for establishing the internal winning combination so that the combination determined as the internal winning combination is not missed. A game machine that notifies a player of such information is known. It should be noted that the notification of information that gives the player an advantage in this way is generally referred to as navigating (navigating), and the period during which the navigating is performed is referred to as AT (assist time), and has an AT function. Game machines are called AT machines and ART machines.

By the way, in such an AT machine (ART machine), a state in which the expectation degree of winning the AT lottery such as a high probability or a low probability state is different is provided during the non-AT period, and the AT lottery performed during the non-AT period is won. Then, the gaming state is changed from the non-AT period to the AT period. In this respect, in the conventional game machine, the state in which the expectation degree of winning the AT lottery is different is managed based on the number of games and the internal winning combination. Specifically, in a conventional game machine, when a specific number of games is reached, the low-probability state is shifted to the high-probability state, and when a specific combination is determined as an internal winning combination, the low-probability state is changed to a high-probability state. It was transitioning to the state.

However, such a conventional method for managing a high-probability / low-probability state of AT lottery may reduce the interest of the game. That is, in the method of managing the high-probability / low-probability state based on the number of games, the player focuses on the so-called zone aiming, in which only the number of games with high expectation of the high-probability state is played. There is a problem that the interest of the period other than several bands is lowered and the operation is lowered, and in the method of managing the high probability / low probability state based on the internal winning role, the role for shifting the state ( Unless the so-called rare role) is determined as the internal winning role, there is no transition to a high-probability state, so if the situation in which the winning role does not continue continues, the game becomes monotonous and the interest is reduced. ..

In order to solve the 19th problem, the present invention provides a 32nd gaming machine having the following configuration.

A plurality of reels (for example, reels 3L, 3C, 3R) on which a plurality of symbols are displayed, a symbol display means (for example, a reel display window 4) for displaying a part of the plurality of symbols displayed on the reels, and The symbol is rotated by rotating the start operation detecting means (for example, the main control circuit 90, the start switch 79) for detecting the start operation by the player and the start operation detected by the start operation detecting means. An internal winning combination that determines an internal winning combination with a predetermined probability from a plurality of combinations according to the symbol changing means (for example, the main control circuit 90, the stepping motor) to be changed and the detection of the start operation by the start operation detecting means. A determination means (for example, a main control circuit 90) and a stop operation detection means (for example, a main control circuit 90, a stop switch board) provided corresponding to the plurality of reels and detecting a stop operation for stopping each reel. 80), the internal winning combination determined by the internal winning combination determining means, and the timing at which the stop operation is detected by the stop operation detecting means, the rotation of the reel is stopped to cause the symbol display means. A reel stop control means (for example, a main control circuit 90, a stepping motor) for stopping the fluctuation of the displayed symbol, and a plurality of winning modes (for example,) having different expectations regarding the granting of benefits when a predetermined condition is satisfied. , The first mode determining means (for example, main control circuit 90, period MAP) for determining one or more winning modes from among the winning modes), and the one or more winnings determined by the first mode determining means. From the modes, depending on the second mode determining means (for example, the main control circuit 90) for determining one winning mode used for the game and the one winning mode used for the game determined by the second mode determining means. The privilege granting means (for example, the main control circuit 90) for granting the privilege is provided, and the second mode determining means is the one described above when the first mode determining means determines a plurality of winning modes. When a predetermined number of games (for example, 16 to 39 games) are played using the winning mode, the winning mode used for the game is changed from the one winning mode to the plurality of winning modes determined by the first mode determining means. A gaming machine characterized by changing to a winning mode other than the winning mode of one of the above.

Further, when the first mode determining means determines a plurality of winning modes, the second mode determining means determines the winning mode to be used for the game in order from the winning mode having the lowest expectation for granting the privilege. It may be characterized by that.

Further, a third mode determination for changing the one or more winning modes determined by the first mode determining means to another one or a plurality of winning modes according to the internal winning combination determined by the internal winning combination determining means. A means (for example, a main control circuit 90) is further provided, and the second mode determining means includes the one winning mode or the one winning mode among the one or more winning modes changed by the third mode determining means. When a winning mode other than the other winning mode changed from the mode is included and a predetermined number of games are played using the one winning mode or the other winning mode, the winning mode used for the game is changed to the above. It may be characterized by changing to the winning mode other than the winning mode of the one or the winning mode determined by the third mode determining means or the other winning mode.

Further, in order to solve the 19th problem, the present invention provides a 33rd game machine having the following configuration.

A gaming machine that plays a game with a period consisting of one or a plurality of winning modes (for example, start-up and transfer modes) that continue for a predetermined number of games as one cycle, and a plurality of reels on which a plurality of symbols are displayed. (For example, reels 3L, 3C, 3R), a symbol display means for displaying a part of a plurality of symbols displayed on the reel (for example, a reel display window 4), and a start operation for detecting a start operation by a player. A symbol changing means (for example, main control) that changes the symbol by rotating the reel in response to the detection of the detection means (for example, the main control circuit 90, the start switch 79) and the start operation by the start operation detecting means. The circuit 90 (stepping motor) and the internal winning combination determining means (for example, the main control circuit 90) that determines the internal winning combination from a plurality of combinations according to the detection of the start operation by the start operation detecting means. A stop operation detecting means (for example, a main control circuit 90, a stop switch board 80) that is provided corresponding to the plurality of reels and detects a stop operation for stopping each reel, and the internal winning combination determining means. By stopping the rotation of the reel according to the internal winning combination determined by the above and the timing when the stop operation is detected by the stop operation detection means, the fluctuation of the symbol displayed on the symbol display means is stopped. The current cycle is selected from the reel stop control means (for example, the main control circuit 90, the stepping motor) and a plurality of cycle maps (for example, cycle MAP) that define the type of winning mode constituting the game for the period of one cycle. A map determining means (for example, the main control circuit 90) for determining one periodic map used in the above, and one used for the game from the plurality of winning modes according to the one periodic map determined by the map determining means. A mode determining means (for example, the main control circuit 90) for determining the winning mode of the above, and a privilege giving means (for example, an ART gaming state) for granting a privilege (for example, an ART gaming state) according to the one winning mode determined by the mode determining means. , Main control circuit 90) and the above-mentioned one winning mode are used to play a predetermined number of times (for example, 16 to 39 games), and the winning mode used for the game is set according to the cycle map used in this cycle. A mode changing means for changing from one winning mode to another winning mode (for example, the main control circuit 90) and a map changing means for changing the cycle map used for this cycle from the one cycle map to another cycle map (for example, the main control circuit 90). For example, the main control circuit 90) is provided, and the plurality of periodic circuits are provided. The map includes a predetermined cycle map and a specific cycle map in which the type of winning mode that constitutes the game for the period of one cycle is different from that of the predetermined cycle map, and the map changing means is used for the current game. When the cycle map used for the current cycle is changed when the winning mode is a specific winning mode (for example, the start mode), the cycle map used for the current cycle is the predetermined cycle map (for example, the predetermined cycle map). For example, the tendency of the cycle map after the change is different between the case of MAP1) where the cycle ends in the start mode and the case of the specific cycle map (for example, MAP3 where the cycle does not end in the start mode). A featured game machine.

Further, the map changing means is used in the current game when the cycle map used in the current cycle is changed when the cycle map used in the current cycle is the predetermined cycle map (for example, MAP3). After the change, the winning mode is changed between the specific winning mode (for example, the start mode) and the predetermined winning mode (for example, the acceptance mode) different from the specific winning mode. It may be characterized in that the tendency of the periodic map is different.

Further, the plurality of winning modes include a first winning mode (for example, a start mode) in which the degree of expectation regarding the granting of the privilege is low, and the first winning mode in the case where the degree of expectation regarding the granting of the privilege is low and a cycle is formed. 1 The second winning mode used for the game after the winning mode (for example, the acceptance mode), and the game has a high degree of expectation regarding the granting of the privilege, and when the cycle is configured, the game is performed after the second winning mode. A third winning mode (for example, a turning mode) to be used is included, and the plurality of cycle maps include the first winning mode and the second winning mode as winning modes constituting the game for the period of the one cycle. The first period map (for example, MAP3) that defines, at least the second cycle map (for example, MAP7) that defines the second winning mode and the third winning mode, and the second winning mode are not specified. , At least a third period map (eg, MAP4) that defines the third winning mode is included, and the map changing means is such that the period map used in this cycle is the first period map (for example, MAP3). ), When the cycle map used for this cycle is changed, if the winning mode used in the current game is the second winning mode (for example, acceptance mode), the cycle is changed to this cycle. When the cycle map to be used can be changed to the second cycle map (for example, MAP7), and the winning mode used in the current game is the first winning mode (for example, starting mode). The period map used for this period may be changed to the third period map (for example, MAP4).

Further, in order to solve the 19th problem, the present invention provides a 34th gaming machine having the following configuration.

A gaming machine that plays a game with a period consisting of one or a plurality of winning modes (for example, start-up and transfer modes) that continue for a predetermined number of games as one cycle, and a plurality of reels on which a plurality of symbols are displayed. (For example, reels 3L, 3C, 3R), a symbol display means for displaying a part of a plurality of symbols displayed on the reel (for example, a reel display window 4), and a start operation for detecting a start operation by a player. A symbol changing means (for example, main control) that changes the symbol by rotating the reel in response to the detection of the detection means (for example, the main control circuit 90, the start switch 79) and the start operation by the start operation detecting means. The circuit 90 (stepping motor) and the internal winning combination determining means (for example, the main control circuit 90) that determines the internal winning combination from a plurality of combinations according to the detection of the start operation by the start operation detecting means. A stop operation detecting means (for example, a main control circuit 90, a stop switch board 80) that is provided corresponding to the plurality of reels and detects a stop operation for stopping each reel, and the internal winning combination determining means. By stopping the rotation of the reel according to the internal winning combination determined by the above and the timing when the stop operation is detected by the stop operation detection means, the fluctuation of the symbol displayed on the symbol display means is stopped. The current cycle is selected from the reel stop control means (for example, the main control circuit 90, the stepping motor) and a plurality of cycle maps (for example, cycle MAP) that define the type of winning mode constituting the game for the period of one cycle. A map determining means (for example, the main control circuit 90) for determining one periodic map used in the above, and one used for the game from the plurality of winning modes according to the one periodic map determined by the map determining means. A mode determining means (for example, the main control circuit 90) for determining the winning mode of the above, and a privilege giving means (for example, an ART gaming state) for granting a privilege (for example, an ART gaming state) according to the one winning mode determined by the mode determining means. When a predetermined number of games are played using the main control circuit 90) and the one winning mode, the winning mode used for the game is changed from the one winning mode to another winning mode according to the cycle map used in this cycle. According to the mode changing means (for example, the main control circuit 90) for changing to the mode and the internal winning combination determined by the internal winning combination determining means, the cycle map used for this cycle is changed from the one cycle map to another cycle. A map changing means (for example, main control circuit 90) for changing to a map, and When the map changing means changes the cycle map used in the current cycle, the mode changing means is changed after the number of times the game using the current winning mode has been played reaches a predetermined number of times. A gaming machine characterized in that the winning mode used for the game can be changed to another winning mode according to the cycle map of the above.

Further, when the map changing means changes the cycle map used in the current cycle, the mode changing means changes the current winning mode as the winning mode in which the changed cycle map constitutes the game for the period of the one cycle. If specified, after the number of times the game using the current winning mode has been played reaches a predetermined number, the winning mode used for the game is changed to another winning mode, and the changed cycle map. If the current winning mode is not specified as the winning mode constituting the game for the period of one cycle, before the number of games played using the current winning mode reaches the predetermined number of times. It may be characterized in that the winning mode used for the game is changed to another winning mode.

Further, when the winning mode used by the mode changing means for the game is changed, the effect means (for example, the display unit 212, the sub-control circuit 200) for performing a predetermined effect is further provided, and the effect means changes the current winning mode. When changing the winning mode to another winning mode after the number of times the used game has been played reaches a predetermined number of times, and before the number of times the game using the current winning mode has been played reaches the predetermined number of times. It may be characterized in that the predetermined effect is performed in a different manner from the case where the corresponding winning mode is changed to another winning mode.

[35th game machine]
In the game machine having the above-described configuration, the advantage / disadvantage of the game depends on the internal state of the game machine (for example, the high probability / low probability state regarding the lottery of whether or not to notify). Before the store opens, it may be initialized to return various information related to game playability to the initial state. Regarding such an initialization process, Japanese Patent Application Laid-Open No. 2016-049285 automatically initializes the game information according to the time from the occurrence of the power failure to the time when the power is turned on in order to reduce the burden on the clerk. The game machine is disclosed.

By the way, since the game machine is designed so that the result of the game within a certain period of time falls within a predetermined value, it is not always preferable that the game machine is automatically initialized when the game machine is turned off. On the other hand, since the initialization process may be performed due to the setting change, the advantage / disadvantage of the player is affected by the gaming machine that can easily determine whether or not the initialization process has been performed. Therefore, there is a need for a mechanism that makes it difficult to determine whether or not the initialization process has been performed.

In order to solve the twentieth problem, the present invention provides a thirty-five gaming machine having the following configuration.

A gaming machine that plays a game with a period consisting of one or a plurality of winning modes (for example, start-up and transfer modes) that continue for a predetermined number of games as one cycle, and a plurality of reels on which a plurality of symbols are displayed. (For example, reels 3L, 3C, 3R), a symbol display means for displaying a part of a plurality of symbols displayed on the reel (for example, a reel display window 4), and a start operation for detecting a start operation by a player. A symbol changing means (for example, a main control circuit) that changes the symbol by rotating the reel based on the detection of the detection means (for example, the main control circuit 90 and the start switch 79) and the start operation by the start operation detecting means. 90, a stepping motor) and an internal winning combination determining means (for example, the main control circuit 90) that determines an internal winning combination from a plurality of combinations according to the detection of the start operation by the start operation detecting means. By a stop operation detecting means (for example, a main control circuit 90, a stop switch board 80) that is provided corresponding to the plurality of reels and detects a stop operation for stopping each reel, and the internal winning combination determining means. A reel that stops the fluctuation of the symbol displayed on the symbol display means by stopping the rotation of the reel based on the determined internal winning combination and the timing at which the stop operation is detected by the stop operation detecting means. A stop control means (for example, a main control circuit 90, a stepping motor), a mode determining means for determining one winning mode to be used for a game from the plurality of winning modes (for example, the main control circuit 90), and the mode determination. A predetermined number of games are performed using the privilege granting means (for example, the main control circuit 90) for granting a privilege (for example, an ART gaming state) according to the one winning mode determined by the means, and the one winning mode. Then, a predetermined winning mode is used to change the winning mode used for the game from the one winning mode to another winning mode (for example, the main control circuit 90) and an effect stage corresponding to the winning mode used for the game. The plurality of winnings are provided with an effect means (for example, a sub control circuit 200, a display unit 212) for performing an effect and a power on detection means (for example, a main control circuit 90, a power device 53) for detecting the power on. The modes include a first winning mode (for example, a start mode) that is determined as the winning mode used for the game first when the cycle is configured, and a game after the first winning mode when the cycle is configured. A second winning mode determined as the winning mode to be used (eg, , Acceptance mode or transfer mode), and the production stage includes a first production stage (for example, a start stage) which is a production stage corresponding to the first winning mode, and a second winning mode. A second production stage (for example, a reception stage or a transfer stage), which is a corresponding production stage, is included at least, and the production means is a winning mode used for a game when the power-on detection means detects the power-on. A gaming machine characterized in that the predetermined effect is performed using the first effect stage even if the second winning mode is determined.

Further, when a predetermined condition is satisfied (for example, when the RAM initialization process is performed), an initialization means (for example, the main control circuit 90) for clearing the winning mode used in the current game is further provided. When the winning mode used in the current game is cleared by the initializing means, the mode determining means newly determines the winning mode used in the game, and the effecting means uses the initializing means. When the winning mode used in the current game is cleared, the predetermined effect is performed using the first effect stage regardless of the winning mode determined by the mode determining means. May be good.

Further, a map determining means (for example, the main control circuit 90) for determining one periodic map to be used for the current cycle from a plurality of periodic maps defining the type of winning mode constituting the game for the period of one cycle is provided. Further, the mode determining means and the mode changing means may be characterized in that the winning mode used for the game is determined according to the one periodic map determined by the map determining means.

Further, the plurality of winning modes include a third winning mode (for example, a turning mode) which is determined as a winning mode to be used for a game after the second winning mode (for example, the acceptance mode) when forming a cycle. Further included, the effect stage further includes a third effect stage (for example, a transfer stage) which is an effect stage corresponding to the third win mode, and the effect means is set to the second win mode. On the other hand, when the winning mode used by the mode changing means for the game is changed from the second winning mode to the third winning mode in the cycle of performing the predetermined effect using the first effect stage, the third effect stage When the effect stage for performing the predetermined effect is changed from the first effect stage to the second effect stage, and from the second effect stage, the effect means performs the predetermined effect. The effect stage may be changed in different modes depending on whether the stage is changed to the third effect stage or the first effect stage is changed to the third effect stage.

[36th game machine]
In the gaming machine having the above-described configuration, Japanese Patent Application Laid-Open No. 2002-85629 is advantageous for the player, such as information for establishing the internal winning combination so that the combination determined as the internal winning combination is not missed. A game machine that notifies a player of such information is known. It should be noted that the notification of information that gives the player an advantage in this way is generally referred to as navigating (navigating), and the period during which the navigating is performed is referred to as AT (assist time), and has an AT function. Game machines are called AT machines and ART machines.

Further, in a game store where a game machine is actually installed, it is common that an external device such as a data counter or a hall computer is installed together with the game machine. For example, it is installed above the game machine. In the data counter, the number of games, the number of bonuses, and the like are displayed in response to the signal output from the game machine, and during the AT period, the data counter also displays that the AT period is in progress.

By the way, in the AT machine, the AT period is managed by various methods, and for example, a game machine that performs a so-called revival effect in which the AT period is pretended to end and then continued is also known. In such a game machine, there is room for further ingenuity in the relationship between the management of the AT period in the game machine and the AT period shown to the player.

That is, in the case of performing the revival effect, since it is determined that the AT period will continue internally in the game machine, for example, the revival effect is performed according to the start operation of the next game of the apparent final game. When performing, it is displayed on the data counter that the AT period is in progress from the apparent final game to the start operation of the next game. On the other hand, if the revival effect is not performed, the AT period has expired internally in the game machine, so the data counter display will switch from the AT period to the non-AT period when the final game ends. It ends up. Therefore, from the player's point of view, by checking the data counter apparently or at the timing when the actual final game is completed, it is known in advance whether or not the revival effect will be performed according to the start operation of the next game. Not preferred.

In order to solve the 21st problem, the present invention provides a 36th gaming machine having the following configuration.

A gaming machine having a normal state (for example, a normal game state) and an advantageous state (for example, an ART game state) that is more advantageous to the player than the normal state as a state in which a game is performed, and a plurality of symbols are displayed. A plurality of reels (for example, reels 3L, 3C, 3R), a symbol display means for displaying a part of a plurality of symbols displayed on the reels (for example, a reel display window 4), and a start operation by a player. The start operation detecting means (for example, the main control circuit 90, the start switch 79) for detecting the start operation, and the symbol changing means for changing the symbol by rotating the reel in response to the detection of the start operation by the start operation detecting means. (For example, the main control circuit 90, the stepping motor) and the internal winning combination determining means (for example, the internal winning combination determining means) that determines the internal winning combination from a plurality of combinations according to the detection of the start operation by the start operation detecting means. A main control circuit 90), a stop operation detecting means (for example, a main control circuit 90, a stop switch board 80) provided corresponding to the plurality of reels and detecting a stop operation for stopping each reel, and the above. The symbol displayed on the symbol display means by stopping the rotation of the reel according to the internal winning combination determined by the internal winning combination determining means and the timing at which the stop operation is detected by the stop operation detecting means. A reel stop control means (for example, a main control circuit 90, a stepping motor) for stopping the fluctuation of the above, and a state in which the advantageous state is started when a predetermined start condition is satisfied and the advantageous state is terminated when a predetermined end condition is satisfied. A control means (for example, a main control circuit 90) and an output means (for example, a main control circuit 90, an external centralized terminal board 47) for outputting information (for example, an external output signal) according to the current gaming state are provided. When the advantageous state ends, the output means terminates the advantageous state in response to the start operation detecting means detecting the start operation in the next game of the game in which the advantageous state ends. A gaming machine characterized by outputting the information to be shown.

[37th game machine]
In the gaming machine having the above-described configuration, information advantageous to the player, such as information for establishing the internal winning combination, is provided to the player so as not to miss the role determined as the internal winning combination in recent years. A game machine that notifies is known. It should be noted that the notification of information that gives the player an advantage in this way is generally referred to as navigating (navigating), and the period during which the navigating is performed is referred to as AT (assist time). In a gaming machine equipped with such an AT function, a high-probability replay state (RT: replay time) in which the probability that a replay (replay) is determined as an internal winning combination is high for notification of information advantageous to the player. ), It is also common to realize an advantageous state (ART) that is advantageous to the player.

By the way, since the game in the advantageous state tends to be monotonous, in recent years, attempts to diversify the game playability in the advantageous state have been widely made. For example, in Japanese Patent Application Laid-Open No. 2005-152165, a free game is played when a predetermined condition is satisfied, and the number of fighter symbols stopped and displayed as a result of the free game is displayed on a liquid crystal display. By setting the number of remaining fighters on the player side of the shooting game to be played, the game machines with various production and payout forms are disclosed.

However, since a free game is a game that is performed in a pseudo manner unlike a normal game, a player who is accustomed to the game feels that the game during the free game is delayed. , There was a risk of spoiling the interest.

In order to solve the 22nd problem, the present invention provides a 37th gaming machine having the following configuration.

A gaming machine having a normal state (for example, a normal game state) and an advantageous state (for example, an ART game state) that is more advantageous to the player than the normal state as a state in which a game is performed, and a plurality of symbols are displayed. A plurality of reels (for example, reels 3L, 3C, 3R), a symbol display means for displaying a part of a plurality of symbols displayed on the reels (for example, a reel display window 4), and a start operation by a player. The start operation detecting means (for example, the main control circuit 90, the start switch 79) for detecting the start operation, and the symbol changing means for changing the symbol by rotating the reel in response to the detection of the start operation by the start operation detecting means. (For example, the main control circuit 90, the stepping motor) and the internal winning combination determining means (for example, the internal winning combination determining means) that determines the internal winning combination from a plurality of combinations according to the detection of the start operation by the start operation detecting means. A main control circuit 90), a stop operation detecting means (for example, a main control circuit 90, a stop switch board 80) provided corresponding to the plurality of reels and detecting a stop operation for stopping each reel, and the above. The symbol displayed on the symbol display means by stopping the rotation of the reel according to the internal winning combination determined by the internal winning combination determining means and the timing at which the stop operation is detected by the stop operation detecting means. A reel stop control means (for example, main control circuit 90, stepping motor) for stopping the fluctuation of the above, an advantageous state start means (for example, main control circuit 90) for starting the advantageous state when a predetermined start condition is satisfied, and a point. The number of points given by the point giving means (for example, the main control circuit 90) that determines the number (for example, EP points) and gives the determined number of points and the number of points given by the point giving means during the advantageous state are predetermined numbers (for example). For example, when it reaches 5 pt), the degree of advantage of the player in the advantageous state (for example, according to the privilege giving means (for example, the main control circuit 90) for giving a predetermined privilege and the number of points given by the point giving means). For example, an advantage degree determining means (for example, the main control circuit 90) for determining the period of the ART gaming state (number of games, number of navigations, difference number of sheets, etc.), the number of points given by the point giving means, and the degree of advantage. The effect determining means (for example, the sub-control circuit 200) that determines the effect in the advantageous state according to the degree of advantage determined by the determining means, and the advantageous state according to the effect determined by the effect determining means. A director who performs a predetermined effect inside A gaming machine including a stage (for example, a sub-control circuit 200, a display unit 212).

Further, the effect performed during the advantageous state is an effect (for example, mahjong effect) in which the first parameter (for example, the number of mahjong tiles) and the second parameter (for example, the type of mahjong tile) are combined. The effect changing means (for example, the sub-control circuit 200) for changing the second parameter of the effect determined by the effect determining means to another second parameter is further provided, and the effect means is the effect determined by the effect determining means. The effect of changing the second parameter of the above to the other second parameter may be performed during the advantageous state.

[38th game machine]
In the gaming machine having the above-described configuration, as shown in Japanese Patent Application Laid-Open No. 2002-85629, information for establishing the internal winning combination and the like so as not to miss the winning combination determined in recent years. A gaming machine is known that notifies a player of information that is advantageous to the player. It should be noted that the notification of information that gives the player an advantage in this way is generally referred to as navigating (navigating), and the period during which the navigating is performed is referred to as AT (assist time). In a gaming machine having such an AT function, in addition to the AT function, a gaming machine having a function of operating a gaming state in which the winning probability of replay is higher than normal, that is, a function of replay time (hereinafter referred to as "RT") is provided. Has also been developed, and a gaming state in which both AT and RT are operating may be referred to as ART or the like.

Further, in the game machine provided with such an AT and RT function (ART function), conventionally, it is controlled so that an excessive profit is not given due to the execution of a stop operation (specific operation order) not intended by the designer. For example, Japanese Patent Application Laid-Open No. 2011-125640 discloses a gaming machine that imposes a penalty such as not performing an ART lottery for a certain period of time when a stop operation is performed in a specific operation order during a non-ART period. Has been done.

By the way, in the conventional game machine, a penalty may be imposed due to an operation error not intended by the player or a malicious operation by another player, which gives the player an unnecessary disadvantage. Therefore, in recent years, it has stopped imposing a penalty on the player's stop operation, allowing the RT function to operate during the non-ART period and increasing the probability of winning the replay. As a result, in recent game machines, there is room for further improvement regarding the start of the ART period.

Specifically, in a gaming machine equipped with an ART function, normally, when the operation of the AT function is permitted, the process shifts to preparation after a predetermined sign, and the RT function is activated during this preparation. , Start the ART period. In this regard, in recent game machines that allow the operation of the RT function during the non-ART period, the RT function may already be activated at the timing when a predetermined precursor is completed. In such a case, it is conceivable to start the ART period by navigating to activate the RT function again after ending the operating RT function once, but it is not preferable because the game is delayed. ..

In order to solve the 23rd problem, the present invention provides a 38th gaming machine having the following configuration.

A gaming machine having at least a first RT state (for example, RT0 to RT2 state) and a second RT state (for example, RT3 state) as RT states in which the probability that the replay related to the replay is determined as the internal winning combination is different. , A plurality of reels (for example, reels 3L, 3C, 3R) on which a plurality of symbols are displayed, and a symbol display means (for example, a reel display window 4) for displaying a part of the plurality of symbols displayed on the reels. The symbol is rotated by rotating the start operation detecting means (for example, the main control circuit 90, the start switch 79) for detecting the start operation by the player and the start operation detected by the start operation detecting means. The internal winning combination is determined with a predetermined probability from a plurality of combinations according to the detection of the starting operation by the symbol changing means (for example, the main control circuit 90, the stepping motor) and the starting operation detecting means. A combination determining means (for example, a main control circuit 90) and a stop operation detecting means (for example, a main control circuit 90, a stop switch) provided corresponding to the plurality of reels and detecting a stop operation for stopping each reel. The symbol display means by stopping the rotation of the substrate 80), the internal winning combination determined by the internal winning combination determining means, and the timing at which the stop operation is detected by the stop operation detecting means. A reel stop control means (for example, a main control circuit 90, a stepping motor) for stopping the fluctuation of the symbol displayed in the above, and when a predetermined condition is satisfied, the RT state is shifted to the second RT state, and a specific condition is set. When the RT state is satisfied, the RT transition means (for example, the main control circuit 90) that shifts the RT state to the first RT state and the effect state related to the game are notified of the information of the advantageous stop operation (for example, the ART game state). A predetermined gaming period has elapsed since the notification determining means (for example, the main control circuit 90) that determines whether or not to shift to the notification state and the notification determining means decide to shift to the notification state (for example, one cycle). In the state during the second RT state after the game is completed), the notification state control means (for example, the main control circuit 90) that starts the notification state and the output means (for example, the output means that outputs information according to the current game state). For example, the output means includes a main control circuit 90 and an external centralized terminal board 47), and when the gaming state when the predetermined gaming period has elapsed is the first RT state, the gaming state is subsequently changed to the first RT state. When the state shifts to the second RT state, the current gaming state is the above-mentioned notification state. When the gaming state when the predetermined gaming period has elapsed is the second RT state, the current gaming state is the notification state at the timing when the predetermined gaming period has elapsed. A game machine characterized by outputting information indicating that.

1 ... Pachislot, 3L, 3C, 3R ... Reel, 4 ... Reel display window, 6 ... Information display, 11 ... Display device, 17L, 17C, 17R ... Stop button, 18 ... Sub display device, 71 ... Main control board, 72 ... Sub control board, 90 ... Main control circuit, 91 ... Microprocessor, 101 ... Main CPU, 102 ... Main ROM, 103 ... Main RAM, 107 ... Arithmetic circuit, 114 ... First serial communication circuit, 115 ... Second serial Communication circuit, 200 ... Sub control circuit, 201 ... Sub CPU 201, 301 ... First interface board, 302 ... Second interface board

Claims (1)

A start operation detection means for detecting a start operation by a player,
A symbol rotating means that includes a plurality of display columns and rotates a symbol provided in each display column based on the detection of the start operation by the start operation detecting means.
A stop operation detection means that detects a stop operation by the player,
Based on the detection of the stop operation by the stop operation detection means, the stop control means for stopping the rotation of the symbol and the stop control means.
Arithmetic processing means that performs arithmetic processing to control game operations,
A first storage means in which information necessary for executing the arithmetic processing by the arithmetic processing means is stored, and
A second storage means for storing information necessary for executing the arithmetic processing by the arithmetic processing means, and
With
The arithmetic processing means
A plurality of general-purpose registers in which data is stored when the arithmetic processing is executed by the arithmetic processing means, and
An extension register in which data is stored when the arithmetic processing is executed by the arithmetic processing means and a part of an address in the second storage means can be specified by the stored data.
Have,
The first storage means has at least a game storage area in which programs and data related to game playability are stored, and an out-of-specification storage area in which programs and data not directly related to game playability are stored. ,
The second storage means has a game storage area used by a program stored in the game storage area and an out-of-specification storage area used by a program stored in the non-standard storage area.
In the game storage area, a constant speed rotation determining means for determining whether or not the rotation of the symbol in a predetermined display row has reached a predetermined constant speed is stored.
In the non-standard storage area,
Port output processing that outputs on-data or off-data ports,
When the constant speed rotation determining means determines that the rotation of the symbol has reached the predetermined constant speed, the on-data output processing for outputting the on-data of the stoptable signal from the port output processing, and the on-data output processing.
After the on-data output process outputs on-data, the off-data output process that outputs off-data of a stoptable signal from the port output process based on the detection of the stop operation by the stop operation detection means, and the off-data output process.
Is remembered,
In the on-data output process and the off-data output process executed by the arithmetic processing means, after saving the values of all the registers of the plurality of general-purpose registers, the port output process is called and then saved. After returning the values of all the registered registers to the plurality of general-purpose registers, the program is transferred to the program stored in the game storage area.
A production means that can perform production using the production stage,
Power-on detection means to detect power-on and
Further prepare
The production means can shift the production stage to another production stage according to the progress of the game, and the production stage before the power is turned off is changed according to the power-on detection means detecting the power-on. It is possible to move to the production stage,
The production stage has a specific production stage and a first production stage and a second production stage different from the specific production stage.
The specific production stage is a production stage capable of shifting from the first production stage to the second production stage.
The effect means is a case where it is determined to shift from the first effect stage to the specific effect stage via the second effect stage, and the effect has been transferred from the first effect stage. When a power failure occurs in the second production stage, the power-on detecting means shifts the second production stage to the first production stage in response to detecting the power-on, but after that, the power-on detection means shifts to the first production stage. A gaming machine characterized in that it is possible to shift from the first production stage to the specific production stage without going through the second production stage.

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