JP2021026303A - Data transfer unit - Google Patents

Abstract

To solve the problem that a module stall occurs because of competition of memory access and hence a processing speed decreases in a system in which a memory is shared by plural modules for performing double buffering control.SOLUTION: When competition of memory access occurs and when the other SRAM used for double buffering can be accessed, a stall is avoided by performing swap control for switching an access destination.SELECTED DRAWING: Figure 3

Description

The present invention relates to a system in which a plurality of modules share a memory.

In order to realize high-quality image printing in a printer or a multifunction device, various image processings are performed on the printed image. For example, removal of noise generated during shooting, filter processing to make edges stand out, color space conversion processing to convert RGB images taken by a camera into CMYK images so that they can be printed by a printer, according to the characteristics of a printer or scanner device. There is also gamma correction processing. These image processes are configured to be processed at high speed by using a circuit dedicated to image processing instead of a CPU, which is a general-purpose arithmetic circuit, so that these image processes can be processed at high speed.

However, since the image data to be processed by these images handles a large amount of data of several hundred MB per page, it is becoming difficult to hold the image data in the internal memory of the image processing circuit. Therefore, it is common to store the image data in an external DRAM, take out the data required by the image processing circuit little by little, and process the entire image. In such an image processing circuit, if an SRAM that stores a part of image data is installed in each image processing module that performs filter processing and color space conversion processing, the module may be recreated due to an image size change at the time of diversion. There was a case that I did. Therefore, as in Patent Document 1, in order to suppress the increase in the circuit area due to the re-creation of the module due to the specification change and the mounting of the SRAM individually, a configuration in which the SRAM is shared by a plurality of modules has been proposed.

Patent No. 5338008

However, in a configuration in which the SRAM is shared by a plurality of modules, access contention may occur in which the SRAM is accessed from each module at the same time. Modules for which memory access permission was not obtained due to this conflict waited for memory access, which could increase processing time.

The present invention has been made in view of such circumstances, and provides a data transfer device that suppresses the occurrence of stall even when an access conflict with the SRAM occurs in a configuration in which the SRAM is shared by a plurality of modules. It is an object.

The data transfer device of the present invention includes a plurality of modules that perform double buffering control, a plurality of SRAMs shared by the plurality of modules, and an arbitration means for arbitrating access to the SRAM from the plurality of modules. When the arbitration means simultaneously accesses one of the SRAMs from the plurality of modules, the arbitration means does not access an SRAM different from the SRAM accessed from the plurality of modules. When there is a writable area, it is characterized in that the access destination of a part of the plurality of modules accessing the one SRAM is controlled to be switched to the other SRAM.

When an access conflict with the shared SRAM occurs, the memory access stall can be reduced and the decrease in processing speed can be suppressed by switching the access destination SRAM.

It is a block diagram which shows the structural example of the multifunction device in Embodiment. It is a block diagram which shows the structural example of the arithmetic unit. It is a block diagram which shows the configuration example of a buffer. It is a figure explaining the operation of the double buffering control. It is a block diagram which shows the structural example of the arbitration part in 1st Embodiment. It is a block diagram which shows the control sequence of the swap control part in 1st Embodiment. It is a figure explaining the operation of swap control. It is a block diagram which shows the control sequence of the swap control part in 2nd Embodiment. It is a figure explaining the operation of the swap control in the 2nd Embodiment. It is a block diagram which shows the control sequence of the swap control part in 3rd Embodiment. It is a figure explaining the operation at the time of access conflict.

Embodiments of the present invention will be described below with reference to the figures.

<First Embodiment>
FIG. 1 is a block diagram showing a configuration example of a multifunction device. The multifunction device 100 of FIG. 1 is composed of a control unit 110, a scanner 120, and a printer 130.

The scanner 120 is an optical device that reads a document and converts it into image data. Specifically, an image sensor that irradiates a document with light and receives the reflected light generates analog data and performs A / D conversion to obtain image data.

The printer 130 is a printing device that forms an image on paper by ejecting ink onto the paper according to print image data. Of course, the method is not limited to such an inkjet method, and an electrophotographic method or other printing method may be used.

The control unit 110 is a control device that gives an operation instruction to the scanner 120 and the printer 130, transfers an image, and performs image processing. The control unit 110 is composed of a CPU 111, a memory controller 112, a DRAM 113, a scanner I / F 114, a printer I / F 115, and a calculation unit 116, and each of them is connected via a bus 117.

The CPU 111 is a processor that controls the multifunction device 100.

Bus 117 is a bus used when transferring data between devices. Since a plurality of data cannot be transferred on the bus 117 at the same time, which data is transferred on the bus 117 is controlled by the memory controller 112.

The memory controller 112 is a controller that manages data transfer requests made on the bus 117. Receives the requests sent from each device and executes them in order. When requests are received from multiple devices at the same time, the request with the highest priority is executed first.

The DRAM 113 is the main storage device on this system. Image data used for scanning and printing is recorded.

The calculation unit 116 is a device that performs image processing on a scanned image or a printed image. For the image data read by the scanner 120, γ correction for correcting the color tone shifted due to the characteristics of the optical element to a natural color, edge enhancement for clarifying the outline of characters, and the like are performed. The image data to be printed is subjected to color space conversion that converts it into a printable CMYK color space, γ conversion, etc. so that the gradation becomes appropriate when expressed with ink.

Next, as an operation example of this system, the operation when performing copy processing will be described. When the copy process is instructed by the user's operation, the CPU 111 starts executing the copy process program. First, the CPU 111 activates the scanner 120 through the scanner I / F 114 and starts the scanning process. The scanner I / F 114 issues a transfer request to the memory controller 112 so as to write the image data read by the scanner 120 to the DRAM 113. When scan data for several lines is written to the DRAM 113, the scanner I / F 114 transmits an interrupt to the CPU 111. In response to this, the CPU 111 activates the calculation unit 116 in order to execute processing on the scanned image. The calculation unit 116 reads the scanned image data from the DRAM 113, performs scan image processing, and writes the processed image data back to the DRAM 113. When all the data processed by the arithmetic unit 116 is written back to the DRAM 113, an interrupt is transmitted to the CPU 111. Upon completion of the scan image processing, the CPU 111 starts control for the printing processing. First, the CPU 111 restarts the calculation unit 116 in order to generate print image data. The calculation unit 116 reads the scanned image processed image data from the DRAM 113, performs print image processing on the read image data, and writes the processed image data back to the DRAM 113. Here, as in the scan process, when all the data processed by the arithmetic unit 116 is written back to the DRAM 113, an interrupt is transmitted to the CPU 111. In response to this, the CPU 111 starts the printer 130 through the printer I / F 115 to perform printing. The printer I / F 115 reads the printed image processed image data on the DRAM 113 and transmits the printed image data to the printer 130 to print on paper. The copy process is completed by repeating the above process for the entire original.

Next, the calculation unit 116 that performs image processing will be described with reference to FIG. The calculation unit 116 is composed of RDMAC201, WDMAC202, buffer 203, and IP (1) 204 to IP (N) 205.

RDMAC 201 is a DMAC that reads data from DRAM 113. When the arithmetic unit 116 is activated from the CPU 111, the RDMAC 201 performs read access to the address where the image data of the DRAM 113 is stored, takes out a part of the image data, and transfers the image data to the buffer 203.

IP (1) to IP (N) are image processing circuits that perform image processing such as edge enhancement, color conversion, and γ conversion. The IP (1) reads out the image data acquired by the RDMAC 201 and stored in the buffer 203, applies image processing, and transfers the IP (1) to the IP (2). Image processing is applied in order from IP (2) to IP (N-1), and IP (N) applies image processing to the image data transferred from IP (N-1) and transfers it to buffer 203. .. By performing various image processing with IP (1) to IP (N) in this way, image data to which image processing for scanning and printing is applied is generated.

WDMAC202 is a DMAC that writes data to DRAM 113. The image data subjected to various image processing by IP (1) to IP (N) is read from the buffer 203 and written to the DRAM 113. When the image processing for one page of image data is completed and the writing to the DRAM 113 is completed, an interrupt for notifying the CPU 111 of the completion of the image processing is raised.

The buffer 203 is a control circuit that holds and sends out image data in response to access from WDMAC202, IP (1) 204, IP (N) 205, and RDMAC202. As shown in FIG. 3, the buffer 203 is composed of an arbitration unit 301, SRAM (A) 302, and SRAM (B) 303. The received access is received by the arbitration unit 301, arbitrated, and then issued to the SRAM. Here, a method of storing data in the SRAM in the arbitration unit will be described with reference to FIG.

FIG. 4A shows an empty state in which data is not stored in SRAMs (A) 302 and SRAM (B) 303. An IN area and an OUT area are assigned to each SRAM. The IN area is an area used by RDMAC201 and IP (1) 204, the OUT area is an area used by IP (N) and WDMAC, and SRAMs are used by a plurality of modules. Is configured to share. As a result, the setting of the area allocated to each image processing circuit in the shared SRAM can be changed without newly designing the SRAM, for example, when the enlargement processing is performed in the image processing, the OUT area is set large. Can be done. In this embodiment, the IN area and the OUT area are set, but when the SRAM is shared by a plurality of modules, a new area may be provided.

First, when the image data is transmitted from the RDMAC 201 to the buffer 203, the image data is stored in the IN area of the SRAM (A) 302 as shown in 401 of FIG. 4 (b). When the storage of the image data in the IN area of the SRAM (A) 302 is completed as shown in 402 of FIG. 4 (c), the SRAM accessed from the RDMAC 201 is switched as shown in 404 of FIG. 4 (d), and the SRAM (B) 303 Image data is stored in the IN area of. At the same time, IP (1) 204 starts reading from the IN area of SRAM (A) 302 in which image data is stored as shown in 403 of FIG. 4 (d). RDMAC 201 completes writing to the IN area of SRAM (B) 303 as shown in 406 of FIG. 4 (e), and IP (1) 204 is the IN area of SRAM (A) 302 as shown in 405 of FIG. 4 (e). When the reading from is completed, the SRAM of each access destination is replaced. Subsequently, RDMAC 201 writes to the IN area of SRAM (A) 302 as shown in 407 of FIG. 4 (f), and IP (1) 204 is written from the IN area of SRAM (B) 303 as shown in 408 of FIG. 4 (f). Read image data. In this way, the buffer 203 performs double buffering control for data transfer while switching between the SRAMs accessed by RDMAC 201 and IP (1) 204. As a result, when the access latency fluctuates when the RDMAC 201 accesses the DRAM 113, or when a temporary stall occurs on the IP (1) side, data transfer can be continued without affecting each other. Become. Further, for IP (N) 205 and WDMAC202, the same double buffering control is performed using the OUT area of the SRAM.

However, in such a configuration in which the SRAM is shared by a plurality of modules, the RDMAC 201 and the IP (N) 205 simultaneously issue write access to the SRAM (A) 302, and a plurality of accesses to one SRAM at the same time. May occur. Due to such access conflict, one of the accesses may be waited for and the data transfer speed may be reduced. In this embodiment, the arbitration unit 301 is provided with a configuration for suppressing the occurrence of such a stall. The arbitration unit 301 having this feature will be described in detail below.

FIG. 5 shows a block diagram of the arbitration unit 301, and the arbitration unit 301 is composed of a swap control unit 501 and a swap information storage unit 502.

The swap control unit 501 is a control circuit that monitors SRAM access from each module and arbitrates SRAM access according to the situation so as to reduce access contention.

The swap information storage unit 502 is a circuit that stores swap information generated by the swap control unit 501 when avoiding access conflicts.

The control sequence of the swap control unit 501 will be described with reference to FIG. First, when the swap control unit 501 receives the access to the SRAM from each module, it confirms in S601 whether or not the access to the same SRAM has occurred. If access to the same SRAM has not occurred, the transition to S607 is performed and the received SRAM access is executed. If an access conflict has occurred in S601, the process transitions to S602 to check what kind of SRAM access is conflicting. When the access causing the conflict in S602 is only the read access, the process proceeds to S606, and one of the read accesses is selected and executed by the Last Recentry Used (LRU) algorithm or the like. If there is a conflict between write access and read access in S602, the process proceeds to S603. In S603, it is determined whether or not the access causing the SRAM conflict can be executed at the same time. If simultaneous execution is possible, transition to S605 to perform swap control, and if not possible, transition to S604, and one of the accesses is selected and executed.

Here, swap control will be described with reference to FIG. FIG. 7A shows a state in which write access 701 for the IN region and write access 702 for the OUT region of the SRAM (A) 302 occur at the same time. At this time, since the SRAM (A) 302 can accept only one of the accesses, the one of the accesses will be stalled. Therefore, when the swap control unit 501 detects that such an access conflict has occurred, it confirms whether it is possible to switch the access to the other SRAM. Specifically, as shown in FIG. 7A, the SRAM (B) is not being accessed, and access conflict does not occur even if the access destination SRAM is switched. In addition, it is confirmed whether the read access to the corresponding address 703 is completed by the other module having double buffering control, and data corruption due to overwriting does not occur even if the swap destination address 703 is written. When this condition is satisfied, the write access to the IN area is changed to the access 711 of the SRAM (B) 303 to the same address as shown in FIG. 7B, and the swap information 714 indicating the switching of the accessed SRAM is changed to the swap information. Record at the corresponding address 714 of the storage unit 502. Such swap control enables simultaneous execution of write access even when access contention occurs. Although FIG. 7 shows an example of performing swap control in the IN area, either of the areas for performing swap control may be selected. At the time of reading, the swap control unit 301 refers to the swap information recorded in the swap information storage unit 502, and if swapping is performed for the read address, the swap destination SRAM is switched and read. .. As a result, it is possible to correctly read the data whose write destination has been switched by the swap control.

As described above, the arbitration unit 301 that receives memory access from a plurality of modules monitors the access from each module, and when the same SRAM is accessed from a plurality of modules at the same time, swap control is performed according to the situation. I do. As a result, it is possible to reduce module stall due to waiting for memory access and suppress an increase in processing time.

<Second embodiment>
In double buffering control, when the operating speeds on the read side and the write side are biased, one module waits for SRAM switching, which causes a period to stop memory access and reduces memory access efficiency. There was a possibility. A main object of the second embodiment is to provide a configuration for improving memory access efficiency even in such a case.

In the second embodiment, only the control sequence of the swap control unit 501 is different from the first embodiment. Therefore, this control sequence will be described below.

FIG. 8 shows a control sequence of the swap control unit 501 in the second embodiment, and a progress check S808 is provided. Other than this progress check S808, the same control as in the first embodiment is performed. In S808, in the module performing double buffering control, the progress of the write side and the read side is checked, and in consideration of the memory access efficiency, the swap execution S805 or the sequential access S804 is performed. This progress check will be specifically described with reference to FIG. FIG. 9 shows a situation in which write access 901 for the IN area of SRAM (A) 302 and write access 902 for the OUT area occur at the same time, and read access 903 occurs in the swap destination SRAM (B) 303. There is. In such a situation, the swap control unit 501 determines that an access conflict has occurred in S801, and transitions to S802. In S802, since write access is occurring at the same time in the race condition check, the transition to S803 occurs. Further, in S803, since read access has occurred in the SRAM (B) 303 of the swap destination of the competing write access, the transition to S808 occurs. In this S808, the progress status of the write side and the read side of the module performing the double buffering control is confirmed. In FIG. 9A, the progress of the write access 902 to the OUT area of the SRAM (A) 302 and the progress of the read access 904 to the OUT area of the SRAM (B) are checked. When the read access 904 is sufficiently ahead of the write access 902 as shown in FIG. 9A, the read access is completed first, and the read access is not performed until the operation on the write side is completed. Since read access to the SRAM (B) 303 cannot be executed until the SRAM can be switched, the utilization rate of the SRAM (B) decreases. Therefore, when the read access is sufficiently ahead of the write access, the read access 914 for the SRAM (B) 303 is stalled as shown in FIG. 9B. Further, swap control is performed so that the access 901 that has caused the conflict in the SRAM (A) 302 is written to the SRAM (B) 303. As a result, the read access to the OUT area of the SRAM (B) 303 stalls and the period until completion is extended, but since the read is sufficiently preceded, the SRAM of the module accessing the OUT area is switched. Will not be delayed. On the other hand, since the write access that caused the conflict with the SRAM (A) 302 can be executed at the same time, the memory access efficiency can be improved as a whole.

<Third embodiment>
A main object of the third embodiment is to provide a method of managing swap information that reduces access contention.

In the third embodiment, only the control sequence of the swap control unit 501 is different from the first embodiment. Therefore, this control sequence will be described below.

FIG. 10 shows a control sequence of the swap control unit 501 according to the third embodiment, and provides a swap amount check S1009. Other than this progress check S1009, the same control as in the first embodiment is performed. In S1009, when the number of swapped addresses recorded in the swap information storage unit 502 exceeds a predetermined amount and the access on the write side of the module performing double buffering control is ahead of the read side. , S1008. In S1008, the light access is stalled. If the above conditions are not met, the transition to the SRAM conflict check of S1001 is performed, and the control equivalent to that of the first embodiment is performed. This swap amount check will be specifically described with reference to FIG.

FIG. 11 shows a state in which the swap information storage unit 502 stores the swapped address information 1103 in a predetermined amount or more. The swap control unit 501 controls to access the SRAM designated as the access destination for the non-swap area, and to switch back to the access destination SRAM for the swapped area. Therefore, as shown in FIG. 11, there is a possibility that the module performing double buffering control performs the write access 1101 and the read access 1102 to the same SRAM. That is, as the swap amount increases, the probability of access contention between modules performing double buffering control may increase. Therefore, when the swap amount exceeds a predetermined amount, the progress of the write side and the read side is confirmed, and control is performed so that the read precedes. Then, when a read is performed on the swapped area, control is performed so that the swap information is deleted. By controlling in this way, when the swapped address area increases, the swap information can be deleted without widening the difference in progress between the write side and the read side.

201 RDMAC
301 Mediation section 302 SRAM (A)
303 SRAM (B)

Claims (3)

Multiple modules that perform double buffering control and
With a plurality of SRAMs shared by the plurality of modules,
A arbitration means for arbitrating access to the SRAM from the plurality of modules is provided.
When the arbitration means simultaneously accesses one of the SRAMs from the plurality of modules, the arbitration means does not access an SRAM different from the SRAM accessed from the plurality of modules. When there is a writable area, the data transfer device is characterized in that it controls to switch the access destination of some modules to the other SRAM among the plurality of modules accessing the one SRAM. .. When the plurality of modules simultaneously generate write access to one of the SRAMs and read access to another SRAM, the arbitration means controls double buffering of the modules. In claim 1, when the access on the read side precedes the access on the write side, the access on the read side is stalled and the other write access is controlled to be switched to the access to another SRAM. The data transfer device described. The mediation means
Swap control means that performs swap control and
A swap information storage means for recording swap information executed by the swap control means is provided.
When the swap information recorded in the swap information storage means exceeds a predetermined amount, the swap control means controls the double buffering control of the module so that the access on the read side precedes the access on the write side. The data transfer device according to claim 1 or 2.

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