JP2021018769A - Circuit design method, program and information processor - Google Patents

Abstract

To arrange a module pin to a proper position before adjusting a timing between blocks.SOLUTION: In a circuit design method, a module pin is initially arranged on a side being a boundary between first and second blocks, then a first flip flop which exists in the first block and coupled to the module pin, a second flip flop which exists in the second block and coupled to the module pin, and a third flip flop which exists in the second block and coupled to the second flip flop, are identified, then before executing timing verification about a signal through the module pin, the module pin is moved into a coordinate range corresponding to an overlap range between a first range in which a point on a path for coupling the first and second flip flops by a shortest Manhattan distance exists on a side, and a second range in which a point on a path for coupling the first and third flip flops by a shortest Manhattan distance exists on a side.SELECTED DRAWING: Figure 17

Description

The disclosure of the present application relates to a circuit design method, a program, and an information processing apparatus.

In LSI hierarchical physical design, a chip is divided into a plurality of blocks having each function, and development is performed in parallel for each block. Connection pins with adjacent blocks called module pins are arranged at the block boundary, and by connecting the wiring in the block to the module pin for each block, the wiring connecting the blocks when assembled on the chip is connected to each other. If the module pins are not arranged at the proper positions, the wiring connecting the blocks will be bypassed, which will lead to timing adjustment across the blocks and deterioration of wiring properties, so the arrangement position of the module pins is important.

In the conventional procedure for determining the arrangement position of the module pin, the module pin is initially arranged on the side of each block which is a boundary between the blocks at the initial stage of the design stage. In this initial arrangement, the order of the input / output pins of the RAM and the order of the bus signal lines are taken into consideration, but the signal timing is not taken into consideration. After the initial placement of the module pins, the timing within each block is verified and the timing adjustment within the block is executed, and then the timing of the signal straddling the blocks is verified and the timing adjustment between blocks is executed. At the time of this inter-block timing adjustment, the position of the module pin remains in the initial arrangement state without considering the timing, so in order to realize a design that can achieve the target frequency, it is necessary to move the position of the module pin. Often needed. Furthermore, it may be necessary to move the position of the flip-flop in the block as the position of the module pin moves.

As described above, in the inter-block timing adjustment in the latter stage of the design, when it is necessary to move the module pins and flip-flops existing in the region where the design has been substantially completed, the following problems occur. First, when moving the module pin, it is necessary to secure a destination area in order to move the module pin, interference with other paths that meet the timing and movement of other paths occur, and the timing adjustment is redone. Occurs. In addition, since the clock skew changes as the flip-flop moves, the setup timing and hold timing deteriorate. For these reasons, there is a problem that the development design process is significantly increased.

Japanese Unexamined Patent Publication No. 10-50845 Japanese Unexamined Patent Publication No. 9-101974

In view of the above, a circuit design method for arranging the module pins at appropriate positions before adjusting the timing between blocks is desired.

In a circuit design method performed by a computer, the computer initially places module pins on the side that is the boundary between the first block and the second block, and is present in the first block. A first flip-flop connected to the module pin, a second flip-flop existing in the second block and connected to the module pin, and a second flip-flop existing in the second block and connected to the second flip-flop. Before identifying the flip-flop of 3 and performing timing verification on the signal via the module pin, a point on the path connecting the first flip-flop and the second flip-flop with the shortest Manhattan distance is Between the first range existing on the side and the second range where a point on the path connecting the first flip-flop and the third flip-flop with the shortest Manhattan distance exists on the side. The module pin is moved within the coordinate region corresponding to the overlapping range.

According to at least one embodiment, the number of development steps can be reduced by arranging the module pins at appropriate positions before adjusting the timing between blocks.

It is a flowchart which shows the procedure of the circuit design method in a related technique. It is a figure which shows the relationship of a chip, a block, and a module pin. It is a figure which shows the relationship between each block and a module pin. It is a figure for demonstrating the timing adjustment in a block of interest. It is a figure for demonstrating the timing adjustment between the blocks of interest. It is a figure for demonstrating the range defined by the shortest Manhattan distance between two flip-flops. It is a figure which shows an example of the state which needs the flip-flop movement. It is a flowchart which shows an example of a circuit design method. It is a functional block diagram of the apparatus which executes the circuit design method shown in FIG. It is a figure which shows an example of a netlist. It is a figure which shows an example of the connection information file about a module pin and a flip-flop. It is a figure which shows an example of the arrangement information file about a chip. It is a figure which shows an example of the positional relationship of a block. It is a figure which shows an example of the connection information and position information file about a module pin and a flip-flop. It is a figure which shows an example of the arrangement information file about the connection between blocks. It is a flowchart which shows the details of the moving destination area determination and the module pin arrangement position determination process. It is a figure which shows an example of the desired module pin arrangement area specified by the three-point evaluation. It is a figure which shows another example of the desired module pin arrangement area specified by the three-point evaluation. It is a figure which shows an example of the module pin movement target list. It is a flowchart which shows an example of the procedure of the module pin movement destination determination processing based on a scoring algorithm. It is a figure for demonstrating 4 neighborhoods for calculating the degree of non-congestion. It is a figure for demonstrating the score which shows the degree of non-congestion. It is a figure which shows the specific example of the score which shows the degree of non-congestion. It is a figure which shows the wiring possible position corresponding to the module pin movement target list shown in FIG. It is a figure which shows an example of the move destination determination process for one module pin. It is a figure which shows an example of the move destination determination process for the next one module pin. Further, it is a figure which shows an example of the move destination determination process for the next one module pin. It is a figure which shows the state which moved and arranged the module pin m-pin (c). It is a figure which shows an example of the module pin movement destination list. It is a figure which shows an example of the case where it is determined that the highest score is not more than a predetermined threshold value. It is a figure which shows an example of the immovable list in an area. It is a figure which shows an example of the immovable list in an area where a layer position was moved to the upper layer. It is a figure which shows an example of the moving destination determination processing for a module pin in the upper layer. It is a figure which shows the state after moving a module pin m-pin (a'). It is a table which shows whether or not it is possible to move to the upper layer of the movement destination. It is a figure which shows an example of the module pin movement list. It is a figure which shows an example of the arrangement of a module pin and three flip-flops. It is a figure which shows an example of the movement destination area specified by the evaluation between three points. It is a figure which shows an example of the movement target list. It is a figure which shows an example of the move destination determination process for a module pin. It is a figure which shows an example of a move destination list. It is a figure which shows an example of a moving list. It is a figure which shows an example of the module pin movement. It is a figure explaining the module pin to move in the circuit design method in a related technique. It is a figure explaining the moving target module pin in the circuit design method of this invention. It is a figure which shows the relationship between the number of flip-flop stages considered when specifying the moving destination area of a module pin, the arrangement error of a module pin, and the amount of calculation. It is a figure which shows the relationship between the number of branches and the amount of calculation. It is a figure which shows the total number of paths existing in each stage when a flip-flop output is branched into two. It is a figure which shows an example of the structure of a circuit design apparatus.

FIG. 1 is a flowchart showing a procedure of a circuit design method in a related technique. The circuit design method in the related technique shown in FIG. 1 is to be compared with the circuit design method of the present invention described later. The circuit design method in the related technology is executed by the following procedure.

In step S1, the RAM and the flip-flop are arranged based on the floor plan. In step S2, the module is configured by considering the RAM input / output pin arrangement and the ascending or descending order (bus signal line arrangement order) for each bus, and giving priority to the upper layer with the earlier timing for the path where the setup timing is strict. Determine the pin placement layer and placement position. Among the module pins, there are module pins that are connected to the RAM or flip-flop via a connection cell (logic circuit such as an inverter or a buffer circuit). Since the connection cells are not arranged at this stage, the connection destination cannot be specified for those module pins. Therefore, the direction of the adjacent block to which the module pin is connected is confirmed, and the module pin is initially arranged on the side of the four sides of the block of interest that is in contact with the adjacent block.

FIG. 2 is a diagram showing the relationship between chips, blocks, and module pins. The chip 10 shown in FIG. 2 is divided into four blocks 10A (Ablock), 10B (Bblock), 10C (Cblock), and 10D (Dblock). Module pins 11 are arranged at the boundaries of the four blocks 10A, 10B, 10C, and 10D.

FIG. 3 is a diagram showing the relationship between each block and the module pin. FIG. 3A shows a block 10A and a module pin 11 provided on the block 10A. FIG. 3B shows a block 10B and a module pin 11 provided on the block 10B. As illustrated in FIGS. 3A and 3B, module pins 11 belonging to the block are arranged on the side of each block in contact with the adjacent block. By connecting these plurality of blocks to the chip 10 as shown in FIG. 1, the paths connecting the blocks, that is, the paths 12A shown in FIG. 3A and the paths shown in FIG. 3B, for example, are formed. 12B is combined.

Returning to FIG. 1, in step S3, in-block timing adjustment is executed in each block. Specifically, the flip-flop placement position is adjusted based on the timing check result in the block, and a design capable of achieving the target frequency is realized. At this stage, connection cells and logical cells are also arranged as appropriate.

FIG. 4 is a diagram for explaining timing adjustment in the block of interest. FIG. 4 shows block 10A as an example. By adjusting the arrangement positions of the flip-flops FF1 and FF2, the time required for signal transmission via the path 13A from the flip-flop FF1 to the flip-flop FF2 is adjusted, and data transmission / reception at a desired frequency becomes possible. ..

Returning to FIG. 1, in step S4, in each block, it is checked whether or not the signal transmission operation in each block is executed without any problem. If there is a problem as a result of the check, the process returns to step S3 and the timing adjustment in the block is continued. If the result of the check is OK, the process proceeds to step S5.

In step S5, attention is paid to the timing between blocks, and the timing adjustment between blocks is executed. Specifically, the target frequency is set for the signal transmitted between blocks by adjusting the position and driving force of the connecting cell and logic cell, and adjusting the position of the signal wiring in consideration of crosstalk. Achieve an achievable design.

FIG. 5 is a diagram for explaining timing adjustment between blocks of interest. FIG. 5 shows, as an example, a path for transmitting a signal between the blocks 10A and the block 10C. A signal is transmitted from the flip-flop FF3 of the block 10A to the flip-flop FF4 of the block 10C via the path 14A, the module pin 11, and the path 14C. In inter-block timing adjustment, for example, the timing is checked for this path, and the timing is adjusted as necessary.

Returning to FIG. 1, in step S6, it is checked whether or not the signal transmission operation between the blocks is executed without any problem. If the result of the check is OK, the process ends. If there is a problem as a result of the check, the process proceeds to step S7.

In step S7, it is determined whether or not the module pins have been rearranged. In the inter-block timing adjustment, the module pins may be rearranged as needed, and in this step S7, it is determined whether or not such module pin rearrangement has already been executed. If the rearrangement has been completed, the process proceeds to step S5 to continue the inter-block timing adjustment. If the module pin rearrangement has not been performed yet, the process proceeds to step S8.

In step S8, the module pins are moved (rearranged) as needed. Specifically, the inter-block paths for which signal transmission / reception at the target frequency is not realized are extracted, and the module pins belonging to the path and the first and second paths connected to the first and second ends of the path, respectively. Identify the flip-flop. Further, it is determined whether or not the module pin is located in a range in which a point on the path connecting the first flip-flop and the second flip-flop with the shortest Manhattan distance exists on the boundary between blocks.

FIG. 6 is a diagram for explaining a range defined by the shortest Manhattan distance between two flip-flops. In FIG. 6, there is a path (not shown) that straddles the side 15 of the block, which is a boundary between blocks, and the flip-flop FF1 and the flip-flop FF2 are connected to both ends of the path. The position of each flip-flop is defined by the lower left corner position (the position indicated by the black circle in the figure) of the rectangular area occupied by each flip-flop. The range in which an arbitrary path connecting the flip-flop FF1 and the flip-flop FF2 with the shortest Manhattan distance (L1 distance) exists corresponds to the rectangular region A1 shown in FIG. The range 15A on the side 15 corresponding to the rectangular region A1 is the range in which a point on the path connecting the flip-flop FF1 and the flip-flop FF2 with the shortest Manhattan distance exists on the side 15.

In the module pin movement process in step S8, if the module pin 11 belonging to the path connecting the flip-flop FF1 and the flip-flop FF2 does not exist in the range 15A on the side 15, the module pin 11 is moved into the range 15A. .. The same process is performed for all inter-block paths for which signal transmission / reception at the target frequency has not been realized.

Next, in step S9, it is determined whether or not the flip-flop needs to be moved. It is necessary to readjust the position of the flip-flop in each block, such as when moving the module pin does not achieve proper operation at the desired frequency. If it is determined in step S9 that the flip-flop does not need to be moved, the process returns to step S5 and the inter-block timing adjustment is continued. If it is determined in step S9 that the flip-flop needs to be moved, the process returns to step S3 and restarts from the in-block timing adjustment.

FIG. 7 is a diagram showing an example of a state in which flip-flop movement is required. In FIG. 7, the flip-flop FF1 and the flip-flop FF2 are connected across the side 15 which is the boundary between blocks. The flip-flop FF2 is further connected to the flip-flop FF3, and the flip-flop FF3 is connected to the flip-flop FF4. In FIG. 7, the module pin 11 is located within a range in which a point on the path connecting the flip-flop FF1 and the flip-flop FF2 with the shortest Manhattan distance exists on the side 15. However, considering not only the flip-flops FF1 and FF2 but also the flip-flops FF3, the position of the flip-flops FF2 is not optimal. In such a case, it may be necessary to move the flip-flop FF2 to the position P1 as shown by a dotted line, and further move the module pin 11 to the position P2.

In the circuit design method in the related technology described above, it is necessary to move the module pins and flip-flops existing in the region where the design has been substantially completed in the inter-block timing adjustment in the latter stage of the design. When moving the module pin, it is necessary to secure a destination area, interference with other paths that meet the timing and movement of other paths occur, and timing adjustment is redone. In addition, since the clock skew changes as the flip-flop moves, the setup timing and hold timing deteriorate. For these reasons, there is a problem that the development design process is significantly increased.

FIG. 8 is a flowchart showing an example of a circuit design method according to an embodiment of the present invention. In FIG. 8 and the following figures, the execution order of each step described in the flowchart is merely an example, and the technical scope intended by the present application is not limited to the execution order described. For example, even if it is described in the present application that the B step is executed after the A step, not only the B step can be executed after the A step, but also the A step is executed after the B step. It may be physically and logically possible to do so. In this case, if all the results affecting the processing of the flowchart are the same regardless of the order in which the steps are executed, for the purpose of the technique disclosed in the present application, step B is followed by step A. Is self-evident that may be performed. Even if it is explained in the present application that the B step is executed after the A step, it is not intended to exclude the above-mentioned obvious cases from the technical scope intended by the present application, and such a case is not intended. If it is self-evident, it naturally falls within the technical scope intended by the present application.

FIG. 9 is a functional block diagram of an apparatus that executes the circuit design method shown in FIG. The device shown in FIG. 9 includes an element arranging unit 20, a tying unit 21, an area determining unit 22, a moving destination determining unit 23, and a timing adjusting unit 24. The functions of each of these parts are realized by the CPU (Central Processing Unit) in the hardware described later executing a predetermined program. The boundary between each functional block and other functional blocks shown in each box basically indicates a functional boundary, and does not necessarily correspond to a control logical separation or the like.

In step S11 of FIG. 8, the element arranging unit 20 arranges the RAM and the flip-flop based on the floor plan. In step S12, the element arranging unit 20 determines the arrangement layer and the arrangement position of the module pin. At this time, the element arranging unit 20 considers the input / output pin arrangement of the RAM and the ascending or descending order (arrangement order of the bus signal lines) in each bus, and gives priority to the upper layer having an early timing for the path where the setup timing is strict. By doing so, the module pins are initially placed on the boundary edge.

Among the module pins, there are module pins that are connected to the RAM or flip-flop via a connection cell (logic circuit such as an inverter or a buffer circuit). Since the connection cells are not arranged at this stage, the connection destination cannot be specified for those module pins. Therefore, the direction of the adjacent block to which the module pin is connected is confirmed, and the module pin is initially arranged on the side of the four sides of the block of interest that is in contact with the adjacent block. The relationship between the chip, the block, and the module pin is as shown in FIG. 2 above, and the relationship between each block and the module pin is as shown in FIG. 3 above.

In the above initial arrangement, the signal timing is not taken into consideration, and there is a large room for adjustment in the module pin arrangement position. By adjusting the module pin arrangement position in this state by the processing of steps S13 to S15 executed immediately after the initial arrangement step, the module pin is moved to a more appropriate position. In the processing of these steps, the position of the module pin is adjusted based on the position of three or more flip-flops and the degree of non-congestion of the wiring without checking the timing of the signal. These processes will be described below.

In step S13, the linking unit 21 links the three flip-flops to each other according to the logical connection in preparation for the evaluation between the three points. Here, in the three-point evaluation, a preferable coordinate area is specified as the module pin arrangement position based on the positions of the three flip-flops connected to the module pin of interest, and the initial arrangement position of the module pin of interest is the coordinate area. It is to evaluate whether or not it exists in. In the associative process as a preparation, in order to identify the three flip-flops, first, the module pin existing on the boundary edge between two adjacent blocks is focused on. Then, the first flip-flop existing in the first block and connected to the module pin of interest and the second flip-flop existing in the second block and connected to the module pin of interest are specified. Further, a third flip-flop existing in the second block and connected to the second flip-flop is specified.

The above-mentioned linking process will be described in detail with reference to the drawings. FIG. 10 is a diagram showing an example of a netlist. FIG. 11 is a diagram showing an example of a connection information file relating to a module pin and a flip-flop. FIG. 12 is a diagram showing an example of an arrangement information file relating to the chip. FIG. 13 is a diagram showing an example of the positional relationship of the blocks. FIG. 14 is a diagram showing an example of connection information and position information files related to module pins and flip-flops. FIG. 15 is a diagram showing an example of an arrangement information file relating to connection between blocks.

First, for two adjacent blocks (eg Ablock and Bblock), the logic is traced from the module pin on the boundary edge based on the netlist (Fig. 10), and the flip-flop instance name connected to the module pin. Is extracted. In the example shown in FIG. 10, DFF_1 and DFF_2 are extracted. If the module pin of interest is an input pin (for example, "input m-pin (a)" shown in Cblock in FIG. 10), the flip-flop instance name is traced to the flip-flop (DFF_3) connected one more ahead. Is extracted. This process is executed for all the module pins existing in the chip, and for each module pin, a connection information file regarding three flip-flops as shown in FIG. 11 is created. In the description here, the case where three flip-flops are linked is used as an example, but the number of flip-flops to be linked is not limited to three, and may be three or more.

Next, based on the arrangement information file relating to the chip shown as an example in FIGS. 12 (a) and 12 (b), the connection information and the position information file (by inserting the coordinate information into the connection information file shown in FIG. 11) FIG. 14) is created. Here, in the arrangement information file shown in FIG. 12A, information regarding the X coordinate, the Y coordinate, and the like of the instances existing in each block is stored. These coordinates are coordinate values for each block with the lower left corner of the block as a reference point (origin (0,0)). Information about the position of each block is stored in the arrangement information file shown in FIG. 12B. In the example shown in FIG. 12B, Bblock is located at the origin position (0,0), Ablock is located above Bblock, Dblock is located on the right side of Bblock, and Cblock is located on the upper right of Bblock (for example, as shown in FIG. 13). (Positional relationship).

In the coordinate example shown in FIG. 12B, as also shown in FIG. 13, the Y coordinate position of the reference point, which is the lower left corner, is deviated from each other by "10,000" between Ablock and Cblock. ing. When performing a three-point evaluation for a module pin on the boundary between two blocks (for example, Ablock and Cblock) adjacent to each other in the X-axis direction in this way, the Y coordinate in each block is corrected in consideration of the deviation. Need to be done. Similarly, when performing a three-point evaluation for a module pin on the boundary edge between two blocks adjacent to each other in the Y-axis direction, it is necessary to correct the X coordinate in each block in consideration of the deviation.

In the connection information and position information files shown in FIG. 14, the Y coordinates of the module pin and the flip-flop are modified with respect to Ablock. That is, the Y coordinates of the module pin and the flip-flop before modification are "30,000" and "35,000", respectively, while the Y coordinates after modification are "40,000" and "45,000", respectively. It has become. That is, considering that the Y coordinate positions of Ablock and Cblock are deviated from each other by "10,000", "10,000" is added to the Y coordinate of each element in Ablock, and the coordinate value is corrected. There is. The X coordinate value of each element in Cblock also takes into consideration the X coordinate value of the Cblock reference point.

After that, a placement information file (FIG. 15) relating to the connection between blocks is generated based on the connection information and location information files shown in FIG. The arrangement information file relating to this inter-block connection indicates that DFF_1, m-pin (a), DFF_2, and DFF_3 are connected in this order, and each element has a coordinate position described in the file.

Returning to FIG. 8, in step S14, the area determination unit 22 determines the module pin movement destination area by the evaluation between three points. Next, in step S15, the movement destination determination unit 23 determines the arrangement position (movement destination position) of the module pin by using a scoring algorithm in consideration of the degree of non-congestion. By using the scoring algorithm in consideration of the degree of non-congestion in this way, efficient design in consideration of the influence of crosstalk noise between wirings becomes possible. These processes will be described in detail below.

FIG. 16 is a flowchart showing details of the movement destination area determination and the module pin arrangement position determination process. In FIG. 16, after the associating process for each module pin (same as step S13 shown in FIG. 8), in step S21, the area determination unit 22 determines whether or not the arrangement position of each module pin is appropriate. Judgment is made by point-to-point evaluation. If the position of the module pin is appropriate, the process related to the module pin is terminated. If the position of the module pin is not appropriate, the process proceeds to step S22. In step S22, the area determination unit 22 determines the destination area of the module pin by a three-point evaluation.

FIG. 17 is a diagram showing an example of a desired module pin arrangement region specified by a three-point evaluation.

In FIG. 17, there is a path (not shown) that straddles the side 15 of the block, which is a boundary between blocks, and the flip-flop FF1 and the flip-flop FF2 are connected to both ends of the path. The position of each flip-flop is defined by the position of the lower left corner of the rectangular area occupied by each flip-flop. The range in which an arbitrary path connecting the flip-flop FF1 and the flip-flop FF2 with the shortest Manhattan distance (L1 distance) exists corresponds to the rectangular region A2 shown in FIG. Also, for the flip-flop FF3 connected to the flip-flop FF2, the shortest Manhattan distance from the flip-flop FF1 is considered. The range in which an arbitrary path connecting the flip-flop FF1 and the flip-flop FF3 with the shortest Manhattan distance exists corresponds to the rectangular region A3 shown in FIG. The area where these rectangular areas A2 and the rectangular area A3 overlap is equal to the rectangular area A2.

The range 15B on the side 15 existing in the rectangular region A2 is a desired module pin arrangement region determined by the evaluation between three points, that is, a coordinate region in which the arrangement position of the module pin 11 is appropriate. When the module pin 11 does not belong to the desired coordinate range 15B as shown in FIG. 17, the region determination unit 22 determines that the module pin 11 of interest is not in an appropriate position. At this time, the area determination unit 22 selects the coordinate range 15B as the movement destination area of the module pin 11.

The definition of the coordinate range 15B can be explained in other words as follows. First, a first range in which a point on the path connecting the first flip-flop FF1 and the second flip-flop FF2 with the shortest Manhattan distance exists on the side 15 is specified. Further, a second range in which a point on the path connecting the first flip-flop FF1 and the third flip-flop FF3 with the shortest Manhattan distance exists on the side 15 is specified. The coordinate area 15B corresponding to the overlapping range between the first range and the second range becomes a desired module pin arrangement area (movement destination area). The module pin will be moved within this destination area.

FIG. 18 is a diagram showing another example of a desired module pin arrangement region specified by a three-point evaluation.

In FIG. 18, the range in which an arbitrary path connecting the flip-flop FF1 and the flip-flop FF2 with the shortest Manhattan distance (L1 distance) exists corresponds to the rectangular region A2. Further, the range in which an arbitrary path connecting the flip-flop FF1 and the flip-flop FF3 with the shortest Manhattan distance exists corresponds to the rectangular region A3 shown in FIG. The area where these rectangular areas A2 and the rectangular area A3 overlap is equal to the rectangular area A4. The range 15B on the side 15 existing in the rectangular area A4 is a desired module pin arrangement area, that is, a coordinate area in which the arrangement position of the module pin 11 is appropriate.

For example, in FIGS. 17 and 18, the flip-flop FF3 may be located above the flip-flop FF1 in the drawing (the side where the Y coordinate value is larger). In such a case, the area where the rectangular area A2 and the rectangular area A3 overlap is considered to be a line area which is a boundary line between both rectangular areas, and further, the intersection of the line area and the side 15 is a coordinate area. It can be considered to be 15B. Further, for example, the output of the flip-flop FF2 may be connected to the inputs of the two flip-flops FF3, respectively. In such a case, two rectangular areas A3 are obtained for each of the two flip-flops FF3, and a total of three rectangular areas, one rectangular area A2 and two rectangular areas A3, overlap each other. May be specified and this rectangular area may be defined as the destination area. The same applies to the case where the number of flip-flops FF3 is 3 or more.

Further, FIGS. 17 and 18 have described the case where the boundary side is in the vertical direction (the case where the boundary side is along the Y axis), but also the case where the boundary side is in the horizontal direction (the direction along the X axis). , Can be thought of in the same way.

Returning to FIG. 16, in step S23, the area determination unit 22 creates a module pin movement target list. That is, a list file containing necessary information is created for all module pins to be moved.

FIG. 19 is a diagram showing an example of a module pin movement target list. In the example shown in FIG. 19, the layer positions of the three module pins m-pin (a), m-pin (b), and m-pin (c) that are moving targets existing on one boundary edge, Information about the current coordinate position and the destination coordinate area is shown in the list.

Next, in step S24 of FIG. 16, the movement destination determination unit 23 determines the movement destination of the module pin by the scoring algorithm. Specifically, the move destination determination unit 23 calculates a score indicating the degree of non-congestion of the wiring for the candidate position of the move destination to move the module pin, and determines the move destination to move the module pin according to the score. ..

FIG. 20 is a flowchart showing an example of the procedure of the module pin movement destination determination process based on the scoring algorithm. In step S31, the move destination determination unit 23 selects a module pin from the move target list. That is, the movement destination determination unit 23 selects one movement target module pin from the module pin movement target list shown in FIG. 19, for example.

In step S32, the movement destination determination unit 23 excludes all the movement target module pins on the boundary edge of interest. That is, the current wiring position of the module pin to be moved is treated as a position where the module pin does not exist and can be used as a movement destination candidate. This will be explained in detail later. In step S33, the movement destination determination unit 23 calculates a score indicating the degree of non-congestion for the wiringable location in the movement destination region.

FIG. 21 is a diagram for explaining four neighborhoods for calculating the degree of non-congestion. In FIG. 21, wiring positions A to J are shown as wiringable locations (locations where module pins can be arranged). As shown in FIG. 21, the 4 neighborhood positions marked with a circle with respect to the module pin placement candidate position M, that is, the wiring possible positions at the left 2 neighborhood of the candidate position M and the right 2 neighborhood of the candidate position M are not set. Consider when calculating the degree of congestion. Specifically, the points are calculated according to whether or not the module pins are arranged at the wiring positions near these four.

The neighborhood positions to be considered are not limited to 4 neighborhoods, and for example, a total of 6 neighborhoods, that is, the left 3 neighborhood and the right 3 neighborhood may be considered. However, considering the degree of non-congestion is to consider the crosstalk noise between wirings and the degree of freedom of wiring when determining the module pin movement destination, and crosstalk from the third (three adjacent) wiring positions next to each other. The effect of is negligibly small. Therefore, in general, only the four neighborhoods need to be considered, and by considering only the four neighborhoods, an efficient design with a small amount of calculation becomes possible.

FIG. 22 is a diagram for explaining points indicating the degree of non-congestion. In FIG. 22, the presence / absence of the module pin in the vicinity of the left 2 (position L1 and position L2) and the vicinity of the right 2 (position R1 and position R2) is indicated by “1” or “0”. “1” indicates that the pin exists, and “0” indicates that the pin does not exist. When the pin exists at the nearest position (position L1 or position R1) with respect to the placement candidate position M, a large penalty (-30 points in this example) is imposed because the crosstalk is large. Even when the pin exists at the second position (position L2 or position R2) adjacent to the placement candidate position M, there is a non-negligible crosstalk, and a certain penalty (-20 points in this example). Imposing. As a result, a score as shown in FIG. 22 is obtained for each of the plurality of patterns indicating the presence / absence of the module pin in the vicinity of 4. The perfect score is 100 points, and the lowest score is 0 points.

FIG. 23 is a diagram showing a specific example of a score indicating the degree of non-congestion. When the module pin is arranged at the position indicated by "1" and each wiring position A to J is set as the candidate position M, the score is as shown in FIG. 23. Here, the wiring position A corresponds to the edge of the boundary side, that is, the corner position of the block, and the score is always 0 at such a corner position. Further, at the position B one adjacent to the corner position, the score is reduced by 30 points from the score according to the pattern shown in FIG.

FIG. 24 is a diagram showing a wiring possible position corresponding to the module pin movement target list shown in FIG. In the module pin movement target list shown in FIG. 19, the arrangement positions and movement destination regions of the three movement target module pins are all in the range of the X coordinate values 50 to 140. In the example shown in FIG. 24, six module pins a to f are arranged in the range of the X coordinate value from 50 to 140. Of the X coordinate positions where the module pins are arranged, the module pins a, b, and c arranged at 50, 80, and 110 are movement target pins.

FIG. 25 is a diagram showing an example of a movement destination determination process for one module pin. As described in step S32 of the flowchart shown in FIG. 20, all module pins to be moved are excluded. Therefore, in FIG. 25, the module pins a, b, and c shown in FIG. 24 are excluded. In the case of the module pin m-pin (a) in the module pin movement target list shown in FIG. 19, the X coordinate of the movement destination region is in the range of 100 to 140. Therefore, when determining the destination of the module pin m-pin (a), the score in the destination region PA shown in FIG. 25 is taken into consideration. In the example shown in FIG. 25, the points indicating the degree of non-congestion are shown at all the points, but the points may be calculated only at the places where the module pins are not arranged.

Returning to FIG. 20, in step S34, the movement destination determination unit 23 determines whether or not the maximum score of the movement destination region is higher than a predetermined threshold value. Here, the predetermined threshold value may be an appropriate threshold value that is predetermined in consideration of the degree of influence of acceptable crosstalk, etc. For example, a wiringable position having a score of 20 points or less is not possible as a movement destination. It may be determined in advance that there is.

In step S35, the movement destination determination unit 23 determines whether or not there are a plurality of locations having the same maximum score in the movement destination region. When there are a plurality of locations having the same maximum score, in step S36, the movement destination determination unit 23 selects the coordinates of the highest point closest to the current position of the module pin of interest as the movement destination. If it is determined in step S35 that there is only one portion having the same maximum score, the process skips step S36 and proceeds to step S37. In step S37, the move destination determination unit 23 sets the coordinates of the highest point (or the coordinates of one selected highest point) as the move destination coordinates (X, Y) with respect to the module pin of interest in the module pin move destination list. Append.

In the example shown in FIG. 25, among the points of the vacant wiringable positions in the movement destination area PA, the maximum score is 70 points at the X coordinate 140, and this score is higher than the threshold value of 20 points, and the maximum score is 1. There is only one. Therefore, the position of the X coordinate 140 is the destination for moving the module pin a of interest.

In step S39 of FIG. 20, the movement destination determination unit 23 determines whether or not there is a module pin whose movement destination is undecided other than the module pin determined to be immovable. If there is a module pin whose destination has not been determined, the process returns to step S31, and the same process as described above is executed for the next module pin.

FIG. 26 is a diagram showing an example of a move destination determination process for the next one module pin. FIG. 26 shows a state in which the module pin m-pin (a) is moved to the X coordinate 140 and arranged, and the score in this state is recalculated. In the case of the module pin m-pin (b) in the module pin movement target list shown in FIG. 19, the X coordinate of the movement destination region is in the range of 50 to 70. Therefore, when determining the destination of the module pin m-pin (b), the score in the destination region PB shown in FIG. 26 is taken into consideration. Among the points of the movable position in the movement destination area PB, the maximum score is 80 points at the X coordinate 50, and this score is higher than the threshold value of 20 points, and there is only one maximum score. Therefore, the position of the X coordinate 50 is the destination for moving the module pin b of interest.

FIG. 27 is a diagram further showing an example of the movement destination determination process for the next one module pin. FIG. 27 shows a state in which the module pin m-pin (b) is moved to the X coordinate 50 and arranged, and the score in this state is recalculated. In the case of the module pin m-pin (c) in the module pin movement target list shown in FIG. 19, the X coordinate of the movement destination region is in the range of 60 to 90. Therefore, when determining the destination of the module pin m-pin (c), the score in the destination region PC shown in FIG. 27 is taken into consideration. Among the points of vacant wiringable positions in the destination area PC, the highest points are 50 points at the X coordinate 80 and the X coordinate 90, and these points are higher than the threshold value 20 points, and the X coordinate 90 is higher. It is close to the original X coordinate 110 of the module pin m-pin (c). Therefore, the position of the X coordinate 90 is the destination for moving the module pin c of interest. FIG. 28 shows a state in which the module pin m-pin (c) is moved to the X coordinate 90 and arranged.

FIG. 29 is a diagram showing an example of a module pin movement destination list. The module pin movement destination list shown in FIG. 29 is obtained by adding the movement destination coordinates of each module pin to the module pin movement target list shown in FIG. The destination coordinates added here are the destination coordinates determined according to the processing of the flowchart shown in FIG.

Returning to FIG. 20, when it is determined in step S34 that the maximum score is equal to or less than a predetermined threshold value, the process proceeds to step S38. In step S38, the move destination determination unit 23 creates an intra-area non-movable list. After that, the process proceeds to step S39. If it is determined in step S39 that there is no module pin whose destination has not been determined, the process ends.

FIG. 30 is a diagram showing an example when it is determined that the maximum score is equal to or less than a predetermined threshold value. When the module pins are arranged as indicated by "1" or "0" at the writable positions A to J, the points indicating the degree of non-congestion are shown at the bottom of FIG. At this time, the positions E and G where the module pins can be moved have a score of 20 points, which is equal to or less than a predetermined threshold value of 20 points. Therefore, in the case shown in FIG. 30, an intra-regional immovable list is created.

FIG. 31 is a diagram showing an example of an intra-regional immovable list. In the example shown in FIG. 31, since it is determined that the module pin m-pin (a') does not have an appropriate wiring position as the movement destination in the movement destination region, the movement destination is set to “none”.

When the processing of the flowchart shown in FIG. 20 is completed as described above, the process returns to the flowchart of FIG. That is, the module pin movement destination determination process (that is, the process of the flowchart shown in FIG. 20) in step S24 of FIG. 16 is completed, and the process proceeds to step S25. In step S25, the movement destination determination unit 23 determines whether or not the module pin can be moved within the area between the three points (within the module pin movement destination area). The process proceeds to step S27 for the module pin determined to be movable. The process proceeds to step S28 for the module pin determined to be non-movable (that is, corresponding to the intra-region non-movable list).

In step S28, the movement destination determination unit 23 determines whether or not the upper layer can be moved within the area between the three points (in the module pin movement destination area). The LSI is provided with a plurality of wiring layers, and the wiring width becomes thicker toward the upper layer, and the layer becomes a layer having a high signal transmission speed. If the move destination is not found as a result of searching for the move destination in the layer where the module pin to be moved is currently placed as described above, the move destination is similarly set in the layer two layers above the currently placed layer. look for. Here, in the hierarchical structure of the LSI, since the X-direction wiring layers and the Y-direction wiring layers are laminated so as to be arranged alternately, when the module pin is moved to the upper layer, it is not on the first layer but on the second layer. You will be looking for a destination.

FIG. 32 is a diagram showing an example of an in-region immovable list in which the layer position has been moved to the upper layer. The movement destination determination unit 23 creates the list shown in FIG. 32 by increasing the numerical value indicating the layer position by 2 in the in-region non-movable list shown in FIG. 31. As a result, the movement destination region for searching the movement destination of the movement target module pin is moved from the sixth layer to the eighth layer two layers above.

FIG. 33 is a diagram showing an example of the movement destination determination process for the module pin in the upper layer. In the case of the module pin m-pin (a') shown in the list of FIG. 32, the X coordinate of the destination region is in the range of 80 to 170. FIG. 33 shows a score indicating the degree of non-congestion in the range of X coordinates 80 to 170 in the eighth layer, which is two layers above the original sixth layer. Among the points in the movement destination region, the maximum score is 80 points at the X coordinate 80, and this score is higher than the threshold value of 20 points, and there is only one maximum score. Therefore, this position is the destination for moving the module pin m-pin (a'). FIG. 34 is a diagram showing a state after the module pin m-pin (a') is moved to the X coordinate 80. The move destination determination unit 23 creates a module pin move destination list by inserting the coordinate values (X, Y) of the move destination as the move destination information in the list shown in FIG. 32.

In this way, when the points are equal to or less than the predetermined points for all the candidate positions existing in the movement destination area, the movement destination is searched for in the movement destination area above the layer where the module pin is currently arranged. As described above, the higher the wiring layer, the wider the wiring width and the faster the signal transmission speed. Therefore, by including the upper layer in the search target when searching for the movement destination of the module pin, it is possible to move the module pin which is advantageous in terms of timing by utilizing the empty space of the upper layer, which is a more favorable condition in terms of timing. ..

FIG. 35 is a table showing whether or not the movement destination can be moved to the upper layer. When the number of layers of the wiring layer is 13 in total, as shown in FIG. 35, the destination of the 12th layer and the 13th layer cannot be moved to a further upper layer. Further, as shown in FIG. 33, if it is found that there is no appropriate destination as a result of checking the score indicating the degree of non-congestion in the destination region in the upper layer, it is not possible to move to the upper layer.

If it is not possible to move to the upper layer as described above, a NO determination is made in step S26 of FIG. 16, and the process proceeds to step S28. In step S28, the movement destination determination unit 23 moves the module pin to the movement destination with the movable position outside the area closest to the movement destination area as the movement destination.

In this way, when there is no destination with a score higher than the predetermined score in the destination region of the upper layer, the position outside the destination region and closest to the destination region in the layer where the module pin is currently arranged. Move the module pin to. This makes it possible to move the module pin to a position in better condition than the current initial placement position even when the module pin cannot be moved within the desired movement destination area obtained by the three-point evaluation. Become. Therefore, it is possible to realize a module pin arrangement state that is a better condition than the initial condition.

If YES is determined in step S26, the process proceeds to step S27. In step S27, the movement destination determination unit 23 adds the module pin movement destination list created based on the list of FIG. 32 to the module pin movement destination list shown in FIG. 29, and further, the coordinates in the block from the coordinate values based on the chip. Convert to a value and create a module pin move list.

FIG. 36 is a diagram showing an example of a module pin movement list. The module pin movement list shows the name of the module pin to be moved, the destination layer, and the coordinate value of the destination. Note that the module pin having the movement destination (movement destination set outside the movement destination area) determined in step S28 may also be added to this module pin movement list. The movement destination determination unit 23 moves the movement target module pin based on the module pin movement list.

When the processing of the flowchart shown in FIG. 16 is completed as described above, the process returns to the flowchart of FIG. When the module pin is appropriately moved from the initial arrangement position and arranged at an appropriate position by the processing of the flowchart of FIG. 16, the timing adjustment unit 24 then executes the in-block timing adjustment in step S16. Specifically, the flip-flop placement position is adjusted based on the timing check result in the block, and a design capable of achieving the target frequency is realized. At this stage, connection cells and logical cells are also arranged as appropriate. Position adjustment and driving force adjustment may be performed on the connection cell and the logic cell, and the position of the signal wiring may be adjusted in consideration of crosstalk.

In step S17, the timing adjusting unit 24 checks whether or not the signal transmission operation in each block is executed without any problem in each block. If there is a problem as a result of the check, the process returns to step S16 and the timing adjustment in the block is continued. If the result of the check is OK, the process proceeds to step S18.

In step S18, the timing adjustment unit 24 pays attention to the timing between blocks and executes the timing adjustment between blocks. Specifically, the target frequency is set for the signal transmitted between blocks by adjusting the position and driving force of the connecting cell and logic cell, and adjusting the position of the signal wiring in consideration of crosstalk. Achieve an achievable design.

In step S19, the timing adjusting unit 24 checks whether or not the signal transmission operation between the blocks is executed without any problem. If there is a problem as a result of the check, the process returns to step S18 and the interblock timing adjustment is continued. If the result of the check is OK, the process ends.

The module pin movement process described above will be briefly described below, focusing on one module pin.

FIG. 37 is a diagram showing an example of the arrangement of the module pin and the three flip-flops. A module pin 11 (named m-pin (a)) is initially arranged at the position of the X coordinate 50 on the boundary side 15 between blocks extending in the X-axis direction. The flip-flop FF1 supplies an output signal to the module pin 11, and the flip-flop FF2 receives an input signal from the module pin 11. The flip-flop FF3 receives a signal output by the flip-flop FF2 as an input signal. These module pins 11 and 3 flip-flops are identified and associated on the netlist.

FIG. 38 is a diagram showing an example of a destination region specified by a three-point evaluation. The range in which an arbitrary path connecting the flip-flop FF1 and the flip-flop FF2 with the shortest Manhattan distance (L1 distance) exists corresponds to the rectangular region A2. Further, the range in which an arbitrary path connecting the flip-flop FF1 and the flip-flop FF3 with the shortest Manhattan distance exists corresponds to the rectangular region A3. The area where these rectangular areas A2 and the rectangular area A3 overlap is equal to the rectangular area A4. The range 15B on the side 15 existing in the rectangular area A4 is the movement destination area of the module pin 11. In the example shown in FIG. 38, the initial arrangement position of the module pin 11 is the X coordinate 50, and the movement destination region is in the range of the X coordinate 100 to the X coordinate 140.

FIG. 39 is a diagram showing an example of a movement target list. In the example shown in FIG. 38, the initial arrangement position of the module pin 11 is the X coordinate 50 and is outside the movement destination region, so that the movement target list shown in FIG. 39 is created. In the movement target list, the name of the module pin, information indicating the number of layers in which the module pin is arranged, the current coordinate position, and the movement destination area (coordinate area) are shown.

FIG. 40 is a diagram showing an example of a movement destination determination process for a module pin. Since all the module pins to be moved are excluded, the module pin a (m-pin (a)) is excluded in FIG. 40. In the module pin movement target list shown in FIG. 39, the X coordinate of the movement destination region is in the range of 100 to 140. Therefore, when determining the destination of the module pin m-pin (a), the score in the destination region PA shown in FIG. 40 is taken into consideration. Among the points of vacant wiringable positions in the movement destination area PA, the highest point is 70 points at the X coordinate 140, and this point is higher than the threshold value of 20 points, and there is only one maximum point. Therefore, the position of the X coordinate 140 is the destination for moving the module pin m-pin (a) of interest.

FIG. 41 is a diagram showing an example of a movement destination list. When the movement destination for moving the module pin m-pin (a) is determined to be the X coordinate 140 as shown in FIG. 40, the movement destination coordinate (X coordinate 140) is related to the movement target list shown in FIG. 39. By adding the information, the destination list shown in FIG. 41 is created.

FIG. 42 is a diagram showing an example of a movement list. From the information included in the movement destination list shown in FIG. 41, information regarding the module pin name, the movement destination layer, and the movement destination coordinate value is extracted, and a movement list including these information is created. At this time, the coordinate value of the movement destination is converted from the absolute coordinate value in the chip to the coordinate value in the block whose origin is the reference point (lower left corner) of each block. As a result, the move list shows the name of the module pin to move, the layer to move to, and the coordinate values in the block to move to.

FIG. 43 is a diagram showing an example of module pin movement. Based on the movement list shown in FIG. 42, the module pin 11 (X coordinate value 50 before movement) shown in FIG. 38 is moved to the X coordinate value 140 as shown by the arrow 30. As a result, the module pin movement process shown in steps S13 to S15 of the flowchart shown in FIG. 8 is completed.

As described above, according to the circuit design method of the present invention, the module pin in the initial arrangement state, which includes the arrangement position determined in the unspecified state of the connection destination, is not sufficiently considered. Move the module pin to the proper position. At this time, the arrangement position of the module pin is adjusted based on the position of three or more flip-flops connected to the module pin and the degree of non-congestion of the wiring without checking the signal timing. This makes it unnecessary to move the module pins and flip-flops existing in the region where the design has been substantially completed in the inter-block timing adjustment in the latter stage of the design. Therefore, it is possible to prevent the timing adjustment from being redone from the state in which the design has been substantially completed, and to prevent deterioration of the setup timing and the hold timing. As a result, it is possible to avoid an increase in the development and design process.

FIG. 44 is a diagram illustrating a moving target module pin in a circuit design method in a related technique. In the example shown in FIG. 44, module pins are arranged at the writable positions A to K on the boundary side 15 between the blocks. It is assumed that the module pin shown in the dotted line frame among these module pins is a module pin determined to be NG (does not satisfy the desired operating frequency condition) by the inter-block timing check. Further, it is assumed that the module pin indicated by the black circle is a module pin determined not to exist in the moving region based on the evaluation between two points as shown in FIG. In the circuit design method in the related technique shown in FIG. 1, the module pin to be moved is only the module pin determined to be NG by the inter-block timing check. Among such module pins, module pins that do not exist in the movement area are actually movement targets.

FIG. 45 is a diagram illustrating a moving target module pin in the circuit design method of the present invention. The module pin shown in the dotted line frame is the module pin corresponding to the NG condition in the inter-block timing check, and the module pin indicated by the black circle is the module pin determined not to exist in the moving area based on the evaluation between three points. Is. In the circuit design method of the present invention, the arrangement position of the module pin is adjusted based on the three-point evaluation without checking the signal timing. Therefore, not only the module pins corresponding to the NG condition in the inter-block timing check, but also all the module pins existing outside the moving area including the module pins having no timing problem are the moving targets. In this way, since the module pin position is adjusted in advance based on the evaluation between three points before the timing check between blocks, it is not necessary to move the flip-flop at the stage of timing check between blocks, which increases the development and design process. Can be avoided.

FIG. 46 is a diagram showing the relationship between the number of flip-flop stages considered when specifying the movement destination region of the module pin, the arrangement error of the module pin, and the calculation amount. In FIG. 46, the horizontal axis shows the number of flip-flop stages to be considered when specifying the movement destination area of the module pin, and the vertical axis shows the arrangement error of the module pin and the calculation amount at the time of calculating the movement destination area. In FIG. 46, the characteristic curve 41 shows the placement error, and the characteristic curve 42 shows the amount of calculation.

When considering only two flip-flops directly connected to the module pin of interest, that is, in the case of the two-point evaluation shown in FIG. 6 in the related technique, the number of flip-flop stages to be considered is two. Further, in the case of the three-point evaluation shown in FIGS. 17 and 18 in the present invention, the number of flip-flop stages to be considered is three. In the present invention, the number of flip-flop stages does not necessarily have to be 3, and may be, for example, 4 or more. However, it is also necessary to consider the increase in the amount of calculation as the number of stages increases.

FIG. 47 is a diagram showing the relationship between the number of branches and the amount of calculation. The path does not branch in the path from the flip-flop FF1 to the flip-flop FF2 via the module pin. However, after the output of the flip-flop FF2, the path may branch. In FIG. 47, the flip-flops existing in each stage when the output in each stage of the flip-flops FF2 to FF4 is branched into two, that is, when the output of one flip-flop is supplied to the inputs of the two flip-flops. The number of flip-flops is shown.

FIG. 48 is a diagram showing the total number of paths existing in each stage when the outputs of the flip-flops FF2 to FF4 are branched into two. The amount of calculation at the time of calculating the destination area can be considered to be proportional to the total number of paths existing in each stage. That is, the relative calculation amount can be considered to be 8 when considering 2 or 4 stages when considering 3 stages and 32 when considering 5 stages. The computational complexity shown as the characteristic curve 42 in FIG. 46 is the computational complexity thus calculated.

The placement error shown in FIG. 46 was calculated as follows. When the circuit design method in the related technique shown in FIG. 1 was applied to a certain circuit example, the module pins arranged outside the movement destination region were 50% of the total module pins at the time of adjusting the timing between blocks. Therefore, the placement error in this case was calculated to be 50%. When the circuit design method of the present invention shown in FIG. 8 is applied to the circuit example, the module pins arranged in the movement destination region in the same layer as the original layer after the module pin movement is the entire module pin. It was 90% of. Further, the module pins arranged in the movement destination region in the upper layer accounted for 8% of the total module pins. Further, the module pins arranged outside the movement destination region accounted for 2% of the total module pins. Therefore, the placement error in this case was calculated to be 2%. The arrangement error for each number of stages calculated in the same manner is shown in FIG. 46 as the characteristic curve 41.

As can be seen from FIG. 46, the number of flip-flop stages to be considered is three, and a sufficiently small arrangement error is realized. On the other hand, even if the number of flip-flop stages to be considered is more than three, the arrangement error does not change so much, but the amount of calculation increases sharply. In view of the above, the number of flip-flop stages to be considered is preferably three.

FIG. 49 is a diagram showing an example of the hardware configuration of the device that executes the circuit design method.

As shown in FIG. 49, the device that executes the circuit design method is realized by a computer such as a personal computer or an engineering workstation. The device of FIG. 49 comprises a computer 510, a display device 520 connected to the computer 510, a communication device 523, and an input device. Input devices include, for example, a keyboard 521 and a mouse 522. The computer 510 includes a CPU 511, a RAM 512, a ROM 513, a secondary storage device 514 such as a hard disk, a commutative medium storage device 515, and an interface 516.

The keyboard 521 and the mouse 522 provide an interface with the user, and various commands for operating the computer 510, a user response to the requested data, and the like are input. The display device 520 displays the result processed by the computer 510 and displays various data in order to enable dialogue with the user when operating the computer 510. The communication device 523 is for communicating with a peripheral device or a remote place, and includes, for example, a modem, a network interface, a USB (Universal Serial Bus), and the like.

The circuit design method is provided as a computer program that can be executed by the computer 510. This computer program is stored in a storage medium M that can be attached to the replaceable medium storage device 515, and is loaded from the storage medium M into the RAM 512 or the secondary storage device 514 via the replaceable medium storage device 515. Alternatively, the computer program is stored in a peripheral device or a remote storage medium (not shown), and is loaded from this storage medium into the RAM 512 or the secondary storage device 514 via the communication device 523 and the interface 516. Will be done.

Upon receiving a program execution instruction from the user via the keyboard 521 and / or the mouse 522, the CPU 511 loads the program from the storage medium M, the peripheral device, the remote storage medium, or the secondary storage device 514 into the RAM 512. The CPU 511 uses the free storage space of the RAM 512 as a work area to execute the program loaded in the RAM 512, and proceeds with the process while interacting with the user as appropriate. At this time, the RAM 512 may store circuit design data such as a floor plan or a netlist as data necessary for executing the circuit design method. The ROM 513 stores a control program for controlling the basic operation of the computer 510.

By executing the computer program, the computer 510 executes the circuit design method as described in each of the above embodiments.

Although the present invention has been described above based on the examples, the present invention is not limited to the above examples, and various modifications can be made within the scope of the claims.

10 Chip 10A, 10B, 10C, 10D Block 15 Boundary side 20 Element placement part 21 Linking part 22 Area determination part 23 Movement destination determination part 24 Timing adjustment part 510 Computer 511 CPU
512 RAM
513 ROM
514 Secondary storage device 515 Convertible medium storage device 516 Interface 520 Display device 521 Keyboard 522 Mouse 523 Communication device

Claims (7)

A circuit design method performed by a computer, wherein the computer
Initially place the module pins on the side that is the boundary between the first block and the second block.
A first flip-flop existing in the first block and connected to the module pin, a second flip-flop existing in the second block and connected to the module pin, and a second flip-flop existing in the second block. Then, identify the third flip-flop connected to the second flip-flop,
Before performing timing verification on the signal via the module pin, a first point on the path connecting the first flip-flop and the second flip-flop with the shortest Manhattan distance exists on the side. A coordinate region corresponding to an overlapping range between a range and a second range in which a point on the path connecting the first flip-flop and the third flip-flop with the shortest Manhattan distance exists on the side. Move the module pin in
A circuit design method characterized by that. The operation of moving the module pin is
For the candidate position of the destination to move the module pin, the score indicating the degree of non-congestion of the wiring was calculated.
The destination to move the module pin is determined according to the score, and
Move the module pin to the determined destination,
The circuit design method according to claim 1, wherein the circuit design method includes the above. The operation of determining the destination is
When the maximum number of points for a plurality of candidate positions existing in the coordinate region is larger than a predetermined number, the candidate position having the maximum number of points is determined as the movement destination.
When the score is equal to or less than a predetermined score for all the candidate positions existing in the coordinate region, the movement destination is searched for in the coordinate region above the layer where the module pin is currently arranged.
2. The circuit design method according to claim 2. The operation of moving the module pin is
When there is a movement destination in which the score is larger than the predetermined score in the coordinate region of the upper layer, the module pin is moved to the movement destination in the upper layer.
When there is no destination in the coordinate region of the upper layer in which the score is larger than the predetermined score, the layer in which the module pin is currently arranged is outside the coordinate region and closest to the coordinate region. Move the module pin to a position,
The circuit design method according to claim 3, which includes the above. The score is a score calculated based on whether or not other module pins are arranged at the writable positions in the vicinity of the left 2 of the candidate position and the vicinity of the right 2 of the candidate position, according to claims 2 to 2. 4. The circuit design method according to any one of the items. In the circuit design, the module pins are initially placed on the side that is the boundary between the first block and the second block.
A first flip-flop existing in the first block and connected to the module pin, a second flip-flop existing in the second block and connected to the module pin, and a second flip-flop existing in the second block. Then, identify the third flip-flop connected to the second flip-flop,
Before performing timing verification on the signal via the module pin, a first point on the path connecting the first flip-flop and the second flip-flop with the shortest Manhattan distance exists on the side. A coordinate region corresponding to an overlapping range between a range and a second range in which a point on the path connecting the first flip-flop and the third flip-flop with the shortest Manhattan distance exists on the side. Move the module pin in
A program that lets a computer perform processing. A storage unit that stores circuit design programs and data,
A processing unit that operates based on the circuit design program and data stored in the storage unit, and
The processing unit includes
Initially place the module pins on the side that is the boundary between the first block and the second block.
A first flip-flop existing in the first block and connected to the module pin, a second flip-flop existing in the second block and connected to the module pin, and a second flip-flop existing in the second block. Then, identify the third flip-flop connected to the second flip-flop,
Before performing timing verification on the signal via the module pin, a first point on the path connecting the first flip-flop and the second flip-flop with the shortest Manhattan distance exists on the side. A coordinate region corresponding to an overlapping range between a range and a second range in which a point on the path connecting the first flip-flop and the third flip-flop with the shortest Manhattan distance exists on the side. Move the module pin in
An information processing device characterized by this.

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