JP2021015419A - Computer system loaded with fpga accelerator, computer for constructing logical configuration in fpga accelerator, and control method - Google Patents

Abstract

To increase a processing speed in a computer system loaded with an FPGA accelerator by allowing an appropriate logical configuration of the FPGA accelerator to be selected in response to a parameter change during the execution of processing.SOLUTION: In processing using an FPGA accelerator, configuration information indicating logical configurations to be loaded to the FPGA accelerator in accordance with parameters to be determined during the execution of a processing program and correspondence relations between the parameters and the logical configurations to be loaded is prepared and generated previously. When the processing is executed, a corresponding logical configuration is loaded to the FPGA accelerator in accordance with a parameter and the configuration information.SELECTED DRAWING: Figure 1

Description

The present invention relates to a technique for constructing a logical configuration for a reconfigurable FPGA (Field Programmable Gate Array).

In recent years, for the purpose of improving the processing capacity of a computer system, a computer system equipped with a device capable of high-speed calculation and offloading the processing of a CPU (Central Processing Unit) to an FPGA has been proposed. Such a device that offloads CPU processing is called an accelerator.

There are various types of accelerator devices, but FPGA devices that can reconfigure hardware logic are attracting particular attention, and high-speed processing is made possible by implementing appropriate arithmetic circuits according to the processing content.

On the other hand, in recent years, services have been developed for the purpose of improving the convenience and utilization efficiency of IT resources, and computer systems are becoming multi-user and multi-tenant. Along with this, the processing content to be offloaded to the accelerator is changed depending on the user who uses the computer and the processing timing.

Patent Document 1 discloses a technique of analyzing a program in which processing contents are described and presenting which part of the processing should be offloaded to the FPGA based on a performance profile and a logic synthesis result.

International Publication No. 2017/565548

The logical configuration of the arithmetic circuit to be mounted on the FPGA device needs to be obtained by performing logic synthesis based on the program in which the processing contents are described before executing the processing. However, since logic synthesis takes time, the computer When logic synthesis is performed after a process execution instruction is given to the system, it is conceivable that the logic synthesis takes a long time and the processing time as a whole becomes long even if the processing speed is high.

Regarding the processing content to be offloaded, the type of processing and the algorithm itself may be changed, but in recent years, parameters (number of iterations, vector dimension, etc.) are frequently used especially in machine learning algorithms using neural networks. Since these parameters are often changed and are given together with the processing execution instruction each time, if it is necessary to perform logic synthesis each time the parameter is changed, speeding up of processing cannot be expected.

In addition, if the possible range of parameters is assumed in advance and the logical configuration covering the entire area is synthesized in advance, the data width and the number of pipeline stages cannot be adjusted according to the parameters, resulting in wasted resources in the FPGA. It occurs and the calculation efficiency decreases.

According to the above-mentioned Patent Document 1, a technique of analyzing a program in which processing contents are described and offloading which part of processing to FPGA based on a performance profile or a logic synthesis result is disclosed. No mention is made of giving the corresponding FPGA logic configuration.

Therefore, an object of the present invention is an FPGA accelerator, a computer system equipped with an FPGA accelerator that makes it possible to select an appropriate logical configuration of an FPGA accelerator in response to a parameter change during processing execution and to speed up processing. The purpose is to provide a computer for constructing a logical configuration and a control method.

One aspect of the computer system that solves the above problems is that in a computer system that is equipped with a CPU and an FPGA accelerator and performs calculation processing according to a processing program and parameters given at the time of executing the processing program, the parameters given at the time of processing the calculation processing are used. , A selection unit that selects the logical configuration to be loaded into the FPGA accelerator, a load unit that loads the logical configuration selected by the selection unit into the FPGA accelerator, and the FPGA accelerator is an operation that constitutes the logical configuration loaded by the loading unit. Has a circuit.

Even if the parameters given at the time of processing execution are changed, the processing can be speeded up.

Further, since the logical configuration of the FPGA accelerator can be adjusted to the change of the parameter, the logical utilization efficiency of the FPGA accelerator is improved. In addition, the operating frequency is improved and the performance is also improved accordingly.

It is a hardware block diagram of the computer system of an Example. It is a figure which shows the processing flow of the computer system of an Example. It is a figure which shows an example of the parameter table of the computer system of an Example. It is a figure which shows the processing flow of the selection part of the computer system of an Example.

Hereinafter, examples will be described with reference to the drawings. It should be noted that the examples described below do not limit the invention according to the claims, and not all combinations of elements described in the examples are essential for the means for solving the invention. ..

FIG. 1 shows the configuration of the computer system 100 of the embodiment. The computer system 110 includes a computer 101 having a central processing unit (CPU) 110, a main storage (MEM) 120, and a storage device (STORAGE) 130, and an FPGA accelerator 140 connected to the computer 101 via a PCI slot 150. ..

The CPU 110 has a function of a selection unit 111 for selecting the FPGA logical configuration and a load unit 112 for loading the FPGA logical configuration into the FPGA accelerator 140. The selection unit 111 and the load unit 112 are realized by executing a program stored in the memory.

The memory 120 stores a program (called a processing program in order to prevent confusion with other programs) 121 indicating the processing content and a parameter 122 designated together with the execution instruction of the processing program 121. These are read into the CPU 110 at the time of execution.

The storage device 130 stores a configuration file 131 indicating the FPGA logical configuration and a parameter table 132 indicating the correspondence between the parameters and the FPGA logical configuration.

An arithmetic circuit 141 is mounted on the FPGA accelerator 140.

The configuration file 131, along with the parameter 122, is referenced by the selection unit 111. The selection unit 111 selects a configuration file 131 that shows the FPGA logical configuration, which is suitable for executing the processing program 121.

The FPGA logical configuration shown by the configuration file 131 is selected by the selection unit 111 and loaded into the FPGA accelerator 140 by the loading unit 112. The FPGA accelerator 140 constructs the arithmetic circuit 141 according to the loaded FPGA logic configuration.

In the configuration file 131 stored in the storage device 130, for example, the content indicating the logical configuration and the identifier A, which is an identifier thereof, are stored in correspondence with each other. Further, in the parameter table 132, as shown in the parameters 2 to m of FIG. 4, each parameter such as the number of repetitions, the vector dimension, and the number of pipelines is managed in correspondence with the identifier B for identifying the logical configuration. The identifier A of the configuration file 131 and the identifier B of the parameter table 132 are corresponding information.

It should be noted that a plurality of FPGA accelerators 140 can be connected to the computer 101, and in that case, the parameter 122 is read from the contents to be processed by each FPGA accelerator 140 (the processing to be performed by each FPGA accelerator 140 in the processing program 121). It may be loaded into each FPGA.

FIG. 2 shows a processing flow in the computer system of the embodiment.

Step S201 is the first step of the process, and indicates that the selection unit 111 described above is executed. In step S201, the selection unit 111 refers to the parameter table 132, acquires the identifier B of the corresponding logical configuration from the parameters of the process of offloading to the FPGA accelerator 140, and corresponds to the identifier A corresponding to the acquired identifier B. Select the logical configuration stored in the configuration file 131. That is, among the configuration files 131 showing the FPGA logical configuration, the one suitable for executing the processing program 121 is selected.

Step S202 is the second step, and indicates that the load unit 112 described above is executed. In step S202, the load unit 112 loads the FPGA logical configuration indicated by the configuration file 131 selected by the selection unit 111 into the FPGA accelerator 140.

Step S203 is a third step, indicating that the processing program 121 is to be executed, and the processing is executed in this order.

FIG. 3 shows the format of the parameter table 132.

Parameter 1 (311 and 321) is a field indicating a matching condition for the first type of parameter type included in parameter 122, and the condition is indicated by a regular expression indicating a range of numerical values or a character string pattern. This field serves, for example, a weighting for determining a match between the parameter for processing execution and each parameter 2 to m in the parameter table 132.

Parameter 2 (312, 322) is a field indicating a matching condition for the second type of parameter type included in parameter 122, and 313 and 323 are for the mth type. The number of parameter types is variable. Parameter 2 includes, for example, parameters such as the number of iterations, the vector dimension, and the number of pipelines.

The corresponding logical configurations 314 and 324 are fields indicating the FPGA logical configurations 131 suitable for execution of the processing program 121. For example, the identifier B corresponding to the logical configuration of the FPGA is registered.

The set of 311, 312, 313, 314 is the first line, and the set of 321, 322, 323, 324 is the nth line. The number of rows is variable.

FIG. 4 shows a processing flow of the selection unit 111, which is the first step of processing.

When the processing of the processing program 121 is started in the computer system 100, the processing flow is started.

In step S401, along with the execution instruction of the processing program 121, the designated parameters 122 for executing the processing program 121, for example, parameters such as the number of iterations, the vector dimension, and the number of pipelines are acquired.

In step S402, the parameter table 132 is read.

In step S403, the parameter condition in the row of interest in the parameter table 132 is compared with the parameter 122. As a result of the comparison, if they match, the process proceeds to step S404, and if they do not match, the process proceeds to step S405.

In step S404, the FPGA logical configuration shown in the row of interest in the parameter table 132, which is suitable for execution of the processing program 121, is acquired. For example, the identifier B corresponding to the logical configuration is acquired, and the logical configuration of the FPGA is acquired from the configuration file 131 based on the identifier A corresponding to the identifier B acquired from the parameter table 132.

In step S405, it is determined whether or not the row of interest in the parameter table 132 is the last row. If it is not the last line, the process proceeds to step S406, and if it is the last line, the process proceeds to step S407.

In step S406, the row of interest in the parameter table 132 is advanced to the next row, and the process returns to step S403.

In step S407, an error indicating that the row corresponding to the parameter 122 was not found in the parameter table 132 is transmitted, and the process ends.

Based on the processing flow of the selection unit 111 shown in FIG. 4, when the parameter 122 matches the parameter matching condition shown in the fields 311, 312, 313, it is suitable for executing the processing program 121 shown in the field 314. The FPGA logical configuration 131 is selected.

Based on the processing flow shown in FIG. 2, the load unit 112 subsequently loads the FPGA accelerator 140, and the arithmetic circuit 141 is mounted. The means for loading the FPGA logical configuration 131 into the FPGA accelerator can be realized by using, for example, a driver of the FPGA accelerator device.

Finally, the processing program 121 is executed. The processing program 121 performs arithmetic processing by transmitting input data to the arithmetic circuit 141 mounted on the FPGA accelerator 140 and receiving output data which is an arithmetic result. The means for inputting / outputting to the arithmetic circuit 141 mounted on the FPGA accelerator 140 can be realized by using, for example, a driver of the FPGA accelerator device.

Even if the parameters given at the time of processing execution are changed, the processing speed of the computer system using the FPGA accelerator is increased.

Further, since the logical configuration of the FPGA accelerator can be adjusted to the change of the parameter, the logical utilization efficiency of the FPGA accelerator is improved, and the operating frequency is improved and the performance is also improved accordingly.

110: Central processing unit,
111: Selection part,
112: Road section,
120: Main memory,
121: Program,
122: Parameter,
130: Storage device,
131: Configuration file containing FPGA logical configuration,
132: Parameter table,
140: FPGA Accelerator,
141: Arithmetic circuit.

Claims (11)

In a computer system equipped with a CPU and an FPGA accelerator and performing calculation processing according to a processing program and parameters given when the processing program is executed.
The CPU
A selection unit that selects the logical configuration to be loaded into the FPGA accelerator according to the parameters given when the calculation process is executed.
A load unit that loads the logical configuration selected by the selection unit into the FPGA accelerator, and
Have,
The FPGA accelerator is a computer system including an arithmetic circuit constituting a logical configuration loaded by the loading unit. The computer system according to claim 1.
A computer system characterized in that the calculation processing of the computer system is given by a calculation result by the calculation circuit configured in the FPGA accelerator. The computer system according to claim 1.
It is characterized by having a storage device that stores a configuration file that manages a plurality of logical configurations and a first identifier correspondingly, and a parameter table that manages a correspondence relationship between a parameter and a second identifier of the logical configuration. Computer system. The computer system according to claim 3.
The selection unit refers to the parameter table stored in the storage device from the parameters at the time of execution of the processing program, and selects one logical configuration from the plurality of logical configurations stored in the configuration file. A computer system characterized by that. In a computer equipped with an FPGA accelerator and loading a logical configuration into the FPGA accelerator in a computer system that performs calculation processing according to a processing program and parameters given at the time of execution of the processing program.
The calculator
A selection unit that selects the logical configuration information to be loaded into the FPGA accelerator according to the parameters given at the time of processing execution.
A load unit that loads the logical configuration information given by the selection unit into the FPGA accelerator, and
A computer characterized by having. It is a control method of a computer system equipped with a CPU and an FPGA accelerator and performing calculation processing according to a processing program and parameters given at the time of processing execution of the processing program.
The step of selecting the logical configuration to be loaded into the FPGA accelerator according to the parameters given at the time of processing execution by the selection unit of the CPU, and
A step of loading the logical configuration given by the selected step by the load unit of the CPU into the FPGA accelerator, and a step of loading the logical configuration into the FPGA accelerator.
A method of controlling a computer system, characterized in that it has. The method for controlling a computer system according to claim 6.
The FPGA accelerator constitutes an arithmetic circuit by loading a logical configuration.
A control method of a computer system, characterized in that the result of the calculation process is given by the calculation result of the calculation circuit configured in the FPGA accelerator. The method for controlling a computer system according to claim 6.
The selection step is characterized in that one logical configuration is selected from a plurality of logical configurations stored in the configuration file by referring to the parameter table stored in the storage device from the parameters at the time of execution of the processing program. The control method of the computer system. The method for controlling a computer system according to claim 8.
A method for controlling a computer system, wherein the selected step includes a parameter given at the time of execution of the processing program and a step of loading the parameter table. The method for controlling a computer system according to claim 9.
The step to be selected is
It has a step of accessing the parameter table that manages the correspondence between the parameter given at the time of executing the processing program and the second identifier indicating the logical configuration.
A method for controlling a computer system, which comprises a step of selecting one logical configuration from a plurality of logical configurations of the configuration file based on the first identifier corresponding to the second identifier. The method for controlling a computer system according to claim 8.
The selection step selects one logical configuration from a configuration file that stores a plurality of logical configurations of the FPGA accelerator based on the parameters given at the time of processing execution and the parameter table.
The loading step is a control of a computer system characterized in that the logical configuration selected by the selected step is loaded into the FPGA accelerator and an arithmetic circuit having the selected logical configuration is constructed in the FPGA accelerator. Method.

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