JP2021005355A - Methods, devices, apparatus and storage media for processing loop instruction set - Google Patents

Abstract

To provide a method of eliminating the pipeline waiting caused by conditional judgment in a first entry into and a last exit from a loop, or the pipeline flushing caused by a failure of branch prediction.SOLUTION: A method includes: in response to obtaining a first start instruction of a loop instruction set, storing a first loop number, related to the loop instruction set, in a first register; storing a value of a first program counter, corresponding to a loop instruction following the first start instruction in the loop instruction set, in a second register; obtaining the loop instruction following the first start instruction in the loop instruction set for executing the loop instruction; in response to obtaining a first end instruction for indicating an end of the loop instruction set, determining loop execution of the loop instruction set based on the first loop number in the first register and the value of the program counter in the second register.SELECTED DRAWING: Figure 2

Description

The embodiments of the present invention relate to the computer field, and particularly to methods, devices, devices and storage media for processing loop instruction sets.

With the development of computer technology, the number of codes in software programs is increasing rapidly. Currently, the number of instructions in the application is already large. Further, with the increase of various applications, applications formed by various instructions are widely used not only in servers but also in various portable electronic devices.

When executing the program code of each application or server, generally, a five-step pipeline process such as instruction acquisition, decoding, execution, memory access, and write back is executed. In general, the instruction can be executed accurately by performing the above-mentioned five-step pipeline processing. Also, there are still many problems to be solved in the process of executing commands.

The embodiments of the present invention provide a plan for processing a loop instruction set.

In the first aspect of the present invention, a method for processing a loop instruction set is provided. In this method, in response to the acquisition of the first start instruction of the loop instruction set, the number of first loops related to the loop instruction set is stored in the first register, and the first start instruction in the loop instruction set is stored. A step of storing the first program counter value corresponding to the next next loop instruction in the second register, a step of acquiring the loop instruction after the first start instruction in the loop instruction set, and a step of executing the loop instruction. In response to the acquisition of the first end instruction indicating the end of the loop instruction set, the loop instruction set is cyclically cycled based on the number of first loops in the first register and the program counter value in the second register. It comprises a step to decide to perform.

In the second aspect of the present invention, an apparatus for processing a loop instruction set is provided. In response to the acquisition of the first start instruction of the loop instruction set, the device stores the number of first loops related to the loop instruction set in the first register, and receives the first start instruction in the loop instruction set. Acquires the first storage module configured to store the first program counter value corresponding to the next next loop instruction in the second register and the loop instruction after the first start instruction in the loop instruction set. The number of first loops in the first register and the second register in response to the acquisition of the loop instruction acquisition module configured to execute the loop instruction and the first end instruction indicating the end of the loop instruction set. It comprises a first loop decision module configured to determine to execute the loop instruction set cyclically based on the program counter value in.

In a third aspect of the invention, the electronic device provides an electronic device comprising one or more processors including at least two registers and a storage device for storing one or more programs. When one or more processors are executed by one or more processors, one or more processors realize the method of the first aspect of the present invention.

A fourth aspect of the present invention provides a computer-readable storage medium in which a computer program is stored, and the method of the first aspect of the present invention is realized when the program is executed by a processor.

It should be noted that the content described in the outline of the invention is not intended to limit the essential or important features of the examples of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the disclosure are facilitated by the following description.

By referring to the following detailed description with reference to the drawings, the above and other features, advantages and aspects of each embodiment of the present disclosure will become clearer. The same or similar reference numerals in the drawings always represent the same or similar components. here,
FIG. 5 is a schematic diagram showing an exemplary environment 100 for processing a loop instruction set according to an embodiment of the present invention. 6 is a flowchart showing a method 200 for processing a loop instruction set according to an embodiment of the present invention. 6 is a flowchart showing a method 300 for processing a loop instruction set according to an embodiment of the present invention. It is a schematic block diagram which shows the apparatus 400 for processing the Example loop instruction set of this invention. It is a block diagram which shows the computer equipment 500 which can carry out a plurality of examples of this invention.

Examples of the present disclosure will be described in more detail below with reference to the drawings. Although some embodiments of the present disclosure are shown in the drawings, the present disclosure can be realized in various forms and should not be construed as being limited to the embodiments described herein. Conversely, it should be understood that by providing these examples, the present disclosure is intended to be more obvious and fully understood. It should be understood that the drawings and examples of the present disclosure are exemplary only and do not limit the scope of protection of the present disclosure.

In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood to include openly, i.e., "include, but not limited to". The term "based on" should be understood to mean "at least partially based." The term "one embodiment" or "the embodiment" should be understood to mean "at least one embodiment". Terms such as "first" and "second" can refer to different or identical objects. The following description may also include other explicit and implied definitions.

Loop programs are relatively common in programs and encounter data adventure (RAW) and control adventure issues at the end of the loop program to determine if it is okay to leave the loop program. In some cases, the processor pipeline is interrupted and you have to wait for the condition to complete, resulting in significant performance loss. Since there are a large number of matrix operations in an artificial intelligence (AI) processor, there are a large number of loop programs and multi-level Nestin group programs, and in such a situation, if the processor improves the processing efficiency for the loop programs and Nesdin group programs. , The instruction execution efficiency of the entire processor can be improved.

In order to solve the problem of waiting for the pipeline due to data adventure and control adventure in the judgment of the loop program, the conventional measures are usually as follows. Plan 1 is to insert two instructions (delay slot is 2) before or after the loop body into the jump delay slot by the compiler. In plan 2, the branch prediction allows the subsequent instruction to be executed in advance without waiting for the completion of the determination condition calculation. Plan 3 is to jump by the automatic learning of the hardware by the loop buffer zone and automatically store the subsequent instruction (for example, ARMx86), and when the jump occurs again, the initial position is not recalculated. , It is possible to jump directly to the command stage stored in advance. Plan 4 is a method in which a loop buffer zone is matched with a plurality of digital signal processing (DSP) processors, and the number of loops and the initial position of the loop are stored in advance using a compiler. This method is a method in which the loop count and the loop body are pre-written in the loop buffer zone by the compiler. In Plan 5, some designs use a compiler to store the number of loops in advance and use special instructions to mark the start and end of the loop so that the loop does not need to be recalculated. You can jump directly to the beginning of the loop at the end of.

However, the above-mentioned conventional measures have the following problems or drawbacks. Plan 1 is highly restrictive and is determined according to whether the compiler can find and fill the appropriate instructions, performing special processing even at the boundaries of the loop and increasing the depth of the pipeline. If it is deep, it will be difficult to realize. The problem with Plan 2 is that if the branch prediction fails, the entire pipeline needs to be flushed, and the cost is very high, especially the prediction failure problem at the initial entry and final exit of the loop. It is inevitable. The design of Plan 3 is mainly to reduce the pressure and energy consumption of the instruction acquisition module, it does not solve the delay slot wait problem in the jump, and at the same time, it does not support loop nesting, the loop buffer zone. There are many restrictions, such as not supporting loops beyond depth and not supporting having more jump commands within the loop. The problem with Plan 4 is that there are still many limitations to this realization, for example: (1) there should be no jumps or loops in the loop body, (2) the loop program will be larger than the loop buffer zone. Must not be, (3) the number of loops is constant. Plan 5 is optimized based on Plan 4, but such a method still depends on the number of loops stored in the general register and the special state bit, and it is still data to judge whether to satisfy the jump state. There is an adventure problem. In some processors that can reach the execution stage and update the state bits, these proposals are questionable if they can be implemented.

According to an embodiment of the present invention, a revised plan for processing a loop instruction set has been submitted. In this plan, by providing two registers in the acquisition module, when the start instruction of the loop instruction set is acquired, the number of loops related to the loop instruction set is stored in the first register, and the start instruction in the loop instruction set is stored. The program counter value corresponding to the next loop instruction after that is stored in the second register, and then the loop instruction is executed. When the first end instruction indicating the end of the loop instruction set is acquired, the loop instruction set is cyclically executed based on the number of first loops in the first register and the program counter value in the second register. decide. In this way, the pipeline wait due to the condition judgment when entering the loop for the first time and the last exit from the loop, or the pipeline flush due to the failure of branch prediction is eliminated, the efficiency of instruction execution is improved, and the length is arbitrary. Supports loops, supports multi-level loop nesting, and secures loop instruction processing.

FIG. 1 is a schematic diagram showing an exemplary environment 100 for processing a loop instruction set according to an embodiment of the present invention. As shown in FIG. 1, the exemplary environment 100 includes an instruction memory 102, an acquisition module 104, and a decoding module 106.

The instruction memory 102 is used to store an instruction to be executed. The instruction memory 102 is a double speed synchronous dynamic random access memory DDR, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EEPROM), and a flash memory or other. It includes, but is not limited to, memory technology, or any other non-transmission medium that stores the required information and is accessible by the acquisition module 104.

The acquisition module 104 is used to acquire an instruction in the instruction memory 102. For example, the acquisition module 104 is an instruction acquisition module for acquiring an instruction. The acquisition module 104 also controls the acquisition process, and transmits the acquired instruction to the decoding module 106 to perform decoding. The acquisition module 104 includes a pair of register pairs, register 108 and register 110. In FIG. 1, the acquisition module 104 includes the register 108 and the register 110, which is merely an example, and is not a specific limitation of the present invention. The acquisition module 104 may include an arbitrary number of registers.

In some embodiments, the acquisition module 104 utilizes registers 108 and 110 to control a loop instruction set. When the subloop instruction set is nested in the loop instruction set, the execution of the subloop instruction set can be realized by providing another pair of registers.

When the acquisition module 104 acquires a loop instruction set, the number of loops of the loop instruction set to be executed is stored in the register 108, and the program counter of the first instruction that actually loops after the start instruction in the loop instruction set. The value can be stored in the register 110. Next, the execution of the loop instruction in the loop instruction set is started. Whether or not the number of loops stored in the register 108 is a predetermined value when the loop instruction is executed until the end, for example, when the end instruction indicating the end of the loop instruction set is acquired. To determine. In one example, the predetermined value is 0. The above-mentioned example is merely for explaining the present disclosure, and there is no specific limitation on the present disclosure, and a person skilled in the art can set the magnitude of the predetermined value as necessary. ..

When it is checked that the value in the register 108 is a predetermined value, it is displayed that the loop instruction set has completed the loop. Therefore, after leaving the loop instruction set, the acquisition module acquires the next instruction of the loop instruction set.

In some embodiments, the partial functions within register 108, register 110, and acquisition module 104 can constitute a loop state machine, which is used to execute a loop instruction set. When the start instruction of the loop instruction set is acquired, the number of loops is stored in the register 108, the program counter value of the instruction after the start instruction is stored in the register 110, and then the acquisition module 104 is stored in the loop state machine. enter. Only when the end instruction of the loop instruction set is detected and the number of loops in the register 108 becomes 0, the loop instruction is withdrawn from the loop state machine, and if not, the loop instruction is executed in the loop state machine.

Asserts that the loop instruction set needs to be looped if it is detected that the value in register 108 is not a predetermined value. Therefore, the acquisition module 104 reads out the initial position of the loop instruction to be executed in the loop instruction set stored in the register 110. Then, the loop instruction in the loop instruction set is re-executed.

The decoding module 106 decodes and executes an instruction (for example, a loop instruction) acquired from the acquisition module 104.

FIG. 1 is a schematic diagram showing an exemplary environment 100 for processing a loop instruction set according to an embodiment of the present invention. A flow chart showing a method 200 for processing a loop instruction set according to an embodiment of the present invention will be described below in combination with FIG.

As shown in FIG. 2, in step 202, the acquisition module determines whether or not the start instruction of the loop instruction set has been acquired. For convenience of explanation, the start command will be referred to as a first start command below. For example, the acquisition module 104 in FIG. 1 is used to acquire an instruction stored in the instruction memory 102. The acquisition module 104 determines whether or not the first start instruction in the loop instruction set has been acquired.

When the first start instruction of the loop instruction set is acquired, in step 204, the acquisition module stores the number of loops related to the loop instruction set in the first register. For convenience of explanation, the number of loops is also referred to as the number of first loops. For example, when the first start instruction in the loop instruction set is acquired, the acquisition module 104 stores the number of first loops in the loop instruction set in the register 108. The number of first loops in the register 108 is used to control the number of times the loop instruction set executes a loop, and the value is decremented one by one after one loop instruction set is executed.

At step 206, the acquisition module stores in the second register the first program counter value corresponding to the next loop instruction after the first start instruction in the loop instruction set. For example, when the acquisition module 104 acquires the start instruction of the loop instruction set and stores the number of loops, the program counter value corresponding to the next loop instruction after the start instruction in the loop instruction set is stored in the register 110. To do. According to the program counter value stored in the register 110, every time the loop instruction set is executed, the loop instruction is executed from the position corresponding to the program counter value.

At step 208, the acquisition module acquires the loop instruction after the first start instruction in the loop instruction set and executes the loop instruction. For example, the acquisition module 104 in FIG. 1 starts executing the loop instruction from the loop instruction after the start instruction of the loop instruction set.

In step 210, the acquisition module determines whether or not the first end instruction indicating the end of the loop instruction set has been acquired. For example, in FIG. 1, the acquisition module 104 determines whether or not the instruction acquired from the instruction memory 102 indicates the end of the loop instruction set.

If the first end instruction indicating the end of the loop instruction set is not acquired, it is declared that the execution of the loop instruction set has not been completed yet, and the execution of the loop instruction is continued.

When the first end instruction indicating the end of the loop instruction set is acquired, in step 212, the acquisition module sets the loop instruction set based on the number of first loops in the first register and the program counter value in the second register. Decide to run cyclically. For example, when the acquisition module 104 of FIG. 1 determines that an end instruction indicating the end of the loop instruction set has been acquired, it is based on the number of loops stored in the registers 108 and 110 and the program counter value. Determines whether to execute the loop instruction set cyclically. In the following, it will be described in detail to determine the process of executing the loop instruction set cyclically according to FIG.

By providing two registers in the acquisition module, the execution of the loop instruction set is controlled, and the pipeline waits based on the condition judgment when the loop instruction body first enters and the last exits, or the pipe due to the failure of branch prediction. Eliminate line flashes, control data adventure issues, and improve instruction execution efficiency.

In the above description, a flowchart showing a method 200 for processing a loop instruction set according to an embodiment of the present invention has been described with reference to FIG. In the following, the process of determining to periodically execute the loop instruction set in step 212 of the method 200 of FIG. 2 will be described in detail with reference to FIG. FIG. 3 illustrates a flowchart showing method 300 for processing a loop instruction set according to an embodiment of the present invention.

As shown in FIG. 3, in step 302, the acquisition module determines whether or not an end instruction indicating the end of the loop instruction set has been acquired, and for convenience of explanation, the end instruction is also referred to as a first end instruction. For example, in FIG. 1, when the acquisition module 104 acquires the loop instruction of the instruction memory 102, it is determined whether or not the end instruction of the loop instruction set has been acquired.

When the end instruction of the loop instruction set is acquired, in step 304, the acquisition module determines whether or not the number of loops is larger than the threshold value. For example, in FIG. 1, when the acquisition module 104 acquires the end instruction of the loop instruction set from the instruction memory 102, it is determined whether or not the number of loops of the loop instruction set stored in the register 108 is larger than the threshold value, for example. It is 0. The examples described above are merely for the purposes of explaining the present disclosure and are not specific limitations of the present disclosure.

If the number of loops is greater than the threshold, step 306 is executed. At step 306, the acquisition module reduces the number of loops in the first register. If it is determined that the number of loops is greater than the threshold, the value of the number of loops needs to be adjusted. For example, reduce the number of loops by one. After that, the number of loops in the first register is updated with the reduced number of loops. For example, in FIG. 1, when the acquisition module 104 determines that the number of loops is larger than the threshold value, the acquisition module 104 reduces the number of loops of the register 108 by one.

In step 308, the acquisition module acquires the next loop instruction corresponding to the program counter value of the second register and repeatedly executes the loop instruction set. If it determines that the number of loops is greater than the threshold, it states that the loop instruction needs to be executed repeatedly. At this time, the initial position of the loop instruction in which the loop processing needs to be executed can be determined by the program counter value stored in the second register. For example, in FIG. 1, the acquisition module 104 reads the program counter value of register 110 so as to acquire the instruction after the start instruction in the loop instruction set.

If the number of loops is less than or equal to the threshold value, step 310 is executed. At step 310, the acquisition module acquires the instructions after the loop instruction set. When the number of loops is equal to the threshold value, for example, 0, the loop of the loop instruction set is declared to be executed. The acquisition module 104 acquires an instruction after the loop instruction set so that it can be continuously executed.

By determining the number of loops in the first register, if the number of loops is not a predetermined value, the instruction to execute again is acquired by the second register, and the loop is realized by the register, and the loop is entered for the first time. There is no need to make a final withdrawal decision, which reduces pipeline wait or pipeline flush problems, guarantees instruction safety, and improves instruction execution efficiency.

In some embodiments, if there are more subloop instruction sets in the loop instruction set, when the subloop instruction set is acquired, the acquisition process of the current instruction set is stopped and the acquisition of the subloop instruction set is stopped. Enter the process. The process in which the acquisition module executes the subloop instruction set is the same as the process in which the loop instruction set is executed. At this time, it is necessary to provide another pair of registers in the acquisition module. For convenience of explanation, the other pair of registers are referred to as a third register and a fourth register.

In the process of executing the subloop instruction set, the acquisition module stores the number of second loops related to the subloop instruction set in the third register in response to the acquisition of the second start instruction in the subloop instruction set. , The second program counter value corresponding to the next subloop instruction after the second start instruction in the subloop instruction set is stored in the fourth register. For example, when the acquisition module 104 in FIG. 1 acquires the second start instruction in the subloop instruction set, the number of loops corresponding to the subloop instruction set and the program counter value of the next subloop instruction after the second start instruction are set. Store in the 3rd register and the 4th register.

After that, the acquisition module acquires the subloop instruction after the second start instruction in the subloop instruction set and executes the loop instruction. In response to the acquisition of the second end instruction indicating the end of the subloop instruction set, the acquisition module takes the subloop instruction based on the number of second loops in the third register and the second program counter value in the fourth register. Decide to execute the set cyclically.

The above examples are merely for the purpose of explaining the present disclosure and are not specific limitations of the present disclosure. When a multi-level nesting group exists, multiple registers can be installed to realize multi-level loop nesting.

It installs multiple pairs of register pairs to support loops of arbitrary length and multi-level loop nesting, and when performing multi-level loop nesting processing, it quickly executes multi-level loops and loops. It is possible to reduce the failure of the pipeline wait or branch prediction due to the number of conditional judgments when entering and leaving the instruction set.

FIG. 4 is a schematic block diagram showing an apparatus 400 for processing an embodiment loop instruction set of the present invention. The device 400 is included in the acquisition module 104 of FIG. 1 or can be implemented in the acquisition module 104. As shown in FIG. 4, the apparatus 400 stores the number of first loops related to the loop instruction set in the first register in response to the acquisition of the first start instruction of the loop instruction set, and the loop instruction set. The first storage module 402 configured to store the first program counter value corresponding to the next loop instruction after the first start instruction in the second register, and the first start instruction in the loop instruction set. In response to the acquisition of the loop instruction acquisition module 404, which is configured to acquire the later loop instruction and execute the loop instruction, and the first end instruction indicating the end of the loop instruction set, in the first register. It includes a first loop determination module 406 configured to periodically execute a loop instruction set based on the number of first loops of the first loop and the program counter value in the second register.

In some embodiments, the first loop determination module 406 determines whether the number of first loops is greater than the threshold in response to the acquisition of the first end instruction indicating the end of the loop instruction set. In response to the loop count comparison module configured as described above and the first loop count being greater than the threshold, the first loop count in the first register is gradually reduced and the loop instruction set is re-executed. Includes a count reduction / acquisition module configured to acquire the next loop instruction corresponding to the program counter value in the register.

In some embodiments, the first loop determination module 406 further provides an instruction acquisition module configured to acquire instructions after the loop instruction set in response that the number of first loops is not greater than the threshold. Including.

In some embodiments, the loop instruction acquisition module 404 further includes a subloop instruction set execution module configured to execute the subloop instruction set in response to the acquisition of the subloop instruction set.

In some embodiments, the subloop instruction set execution module stores in the third register the number of second loops associated with the subloop instruction set in response to the acquisition of the second start instruction in the subloop instruction set. , A second storage module configured to store the second program counter value corresponding to the next subloop instruction after the second start instruction in the subloop instruction set in the fourth register, and a second in the subloop instruction set. In response to the acquisition of the subloop instruction acquisition module configured to acquire the subloop instruction after the start instruction and execute the loop instruction, and the second end instruction indicating the end of the subloop instruction set, the third It includes a second loop decision module configured to periodically determine to execute the subloop instruction set based on the number of second loops in the register and the second program counter value in the fourth register.

FIG. 5 is a block diagram showing a computer device 500 in which a plurality of embodiments of the present invention can be implemented. The device 500 is used to realize the acquisition module 104 of FIG. As shown in the figure, the device 500 is suitable based on the computer program instructions stored in the read-only memory (ROM) 502 or the computer program instructions loaded from the storage unit 508 into the random access memory (RAM) 503. Includes a computing unit 501 that performs operations and processes. The RAM 503 can store each program and data used for operating the device 500. The calculation unit 501, ROM 502 and RAM 503 are connected via a total line 504. The input / output (I / O) interface 505 is also connected to the total line 504.

A device including an input unit 506 such as a keyboard and a mouse, an output unit 507 such as various displays and speakers, a storage unit 508 such as a disk and a CD, and a communication unit 509 such as a network card, a modem, and a wireless communication transceiver. The plurality of components in 500 are connected to the I / O interface 505. The communication unit 509 allows the device 500 to exchange information / data with other devices via the Internet and / or various telecommunications networks and the like. Memory unit

The calculation unit 501 may be a general-purpose or / or dedicated processing component having each processing and computing power. Some examples of calculation unit 501 are central processing unit (CPU), image processing unit (GPU), dedicated artificial intelligence (AI) calculation chip, calculation unit that executes each machine learning model algorithm, and digital signal processor. (DSP), including, but not limited to, any suitable processor, controller, microcontroller, etc. The calculation unit 501 performs the methods and processes described above, eg, methods 200 and 300. For example, in some embodiments, methods 200 and 300 can be implemented in a computer software program and are tangibly included in a machine readable storage medium such as storage unit 508. In some embodiments, some or all of the computer program can be loaded and / or mounted on the device 500 through the ROM 502 and / or the communication unit 509. One or more steps of methods 200 and 300 described above can be performed when the computer program is loaded into RAM 503 and executed in compute unit 501. Also, in other embodiments, the compute unit 501 may be configured to perform method 500 by any other suitable method (eg, by firmware).

The present invention allows the functions described above to be performed by at least one or more hardware logic components. For example, non-limiting, exemplary hardware logic components are field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), and systems. It includes an on-chip (SOC) and a logic device (CPLD) that can rewrite the program.

The program code for implementing the methods of the present disclosure can be programmed in any combination of one or more programming languages. These program codes may be provided to the processor or controller of a general purpose computer, dedicated computer, or other programmable data processor, and as a result, when the program code is executed by the processor or controller, the flow chart and / or block. The function / operation specified in the figure is performed. The program code can be run entirely on the device, partially on the device, partially on the device as a stand-alone software package, partially on the remote device, or entirely on the remote device or server. obtain.

As used herein, a device-readable medium may include or store a program used by, or in combination with, an instruction execution system, device, or device. It can be a tangible medium that can be used. The device-readable medium can be a device-readable signal medium or a device-readable storage medium. The device readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or devices, or any suitable combination of the above. More specific examples of device readable storage media are electrical connections based on one or more lines, portable computer disks, hard disks, random access memory (RAM), read-on memory (ROM), erasable programmable read-on. It can include memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination thereof.

Also, the actions have been described in a particular order, which indicates that such actions are performed in the particular order or order in which they were shown, or to achieve the desired result. It requires that the performed operation be performed. In certain situations, multitasking and parallelism can be advantageous. Similarly, details of some specific implementations are included in the above description, but these should not be construed as limiting the scope of this disclosure. Some features described in separate embodiments can also be realized in combination in a single realization. Conversely, the various features described for a single embodiment can be implemented in multiple embodiments individually or in any suitable subcombination.

Although the present application is described in a language specific to constructive features and / or method logical behaviors, the themes defined in the appended claims are not limited to the particular features or behaviors described above. Should be understood. Conversely, the particular features and behaviors described above are merely exemplary embodiments that implement the claims.

Claims (12)

In response to the acquisition of the first start instruction of the loop instruction set, the number of first loops related to the loop instruction set is stored in the first register, and after the first start instruction in the loop instruction set. The step of storing the first program counter value corresponding to the next loop instruction in the second register, and
A step of acquiring a loop instruction after the first start instruction in the loop instruction set and executing the loop instruction, and
In response to the acquisition of the first end instruction indicating the end of the loop instruction set, the loop is based on the number of times of the first loop in the first register and the program counter value in the second register. The steps that determine to execute the instruction set cyclically,
A method for processing a loop instruction set that comprises. The step that determines to execute the loop instruction set cyclically is
A step of determining whether or not the number of times of the first loop is larger than the threshold value in response to the acquisition of the first end instruction indicating the end of the loop instruction set.
In response to the number of first loops being greater than the threshold, the number of first loops in the first register is gradually reduced and the loop instruction set is re-executed in the second register. The method of claim 1, comprising the step of acquiring the next loop instruction corresponding to the program counter value. The step that determines to execute the loop instruction set cyclically is
The method of claim 2, further comprising the step of acquiring an instruction after the loop instruction set in response to the first loop count not being greater than the threshold. The step of acquiring the loop instruction after the first start instruction in the loop instruction set is
The method of claim 1, comprising the step of executing the subloop instruction set in response to the acquisition of the subloop instruction set. The step of executing the subloop instruction set is
In response to the acquisition of the second start instruction in the subloop instruction set, the number of second loops related to the subloop instruction set is stored in the third register, and the second start instruction in the subloop instruction set is stored. The step of storing the second program counter value corresponding to the next subloop instruction after the fourth register in the fourth register,
A step of acquiring a subloop instruction after the second start instruction in the subloop instruction set and executing the subloop instruction, and
In response to the acquisition of the second end instruction indicating the end of the subloop instruction set, based on the number of times of the second loop in the third register and the second program counter value in the fourth register. The method according to claim 4, comprising a step of determining to execute the subloop instruction set cyclically. In response to the acquisition of the first start instruction of the loop instruction set, the number of first loops related to the loop instruction set is stored in the first register, and after the first start instruction in the loop instruction set. A first storage module configured to store the first program counter value corresponding to the next loop instruction in the second register, and
A loop instruction acquisition module configured to acquire a loop instruction after the first start instruction in the loop instruction set and execute the loop instruction.
In response to the acquisition of the first end instruction indicating the end of the loop instruction set, the loop is based on the number of times of the first loop in the first register and the program counter value in the second register. A first loop decision module configured to determine to execute the instruction set cyclically,
A device for processing a set of loop instructions. The first loop determination module
A loop count comparison module configured to determine whether or not the first loop count is greater than a threshold in response to the acquisition of the first end instruction indicating the end of the loop instruction set.
The program in the second register to gradually reduce the number of first loops in the first register and re-execute the loop instruction set in response to the first loop count being greater than the threshold. The number-of-times reduction / acquisition module configured to acquire the next loop instruction corresponding to the counter value,
The apparatus according to claim 6. The first loop determination module
The apparatus according to claim 7, further comprising an instruction acquisition module configured to acquire an instruction after the loop instruction set in response to the first loop count not being greater than the threshold. The loop instruction acquisition module
The apparatus according to claim 6, further comprising a subloop instruction set execution module configured to execute the subloop instruction set in response to the acquisition of the subloop instruction set. The subloop instruction set execution module
In response to the acquisition of the second start instruction in the subloop instruction set, the number of second loops related to the subloop instruction set is stored in the third register, and the second start instruction in the subloop instruction set is stored. A second storage module configured to store the second program counter value corresponding to the next subloop instruction after the fourth register, and
A subloop instruction acquisition module configured to acquire a subloop instruction after the second start instruction in the subloop instruction set and execute the subloop instruction.
In response to the acquisition of the second end instruction indicating the end of the subloop instruction set, based on the number of times of the second loop in the third register and the second program counter value in the fourth register. A second loop decision module configured to determine to execute the subloop instruction set cyclically,
9. The apparatus according to claim 9. It ’s an electronic device,
With one or more processors containing at least two registers,
Equipped with a storage device for storing one or more programs,
To process the loop instruction set according to any one of claims 1 to 5, when the one or more processors are executed by the one or more processors. Electronic equipment that realizes the method of. A computer-readable storage medium that stores computer programs
A computer-readable storage medium in which a method for processing the loop instruction set according to any one of claims 1 to 5 is realized when the program is executed by a processor.

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