JP2021005077A - Manufacturing method of array substrate - Google Patents

Abstract

To provide a manufacturing method of an array substrate capable of finding a malfunction of an array substrate at an early stage.SOLUTION: There is provided a manufacturing method of an array substrate 30 in which multiple pixel electrodes 34 and multiple TFTs 32 are arranged in a matrix. The method includes the steps of: forming a source electrode 32S and a drain electrode 32D constituting TFTs 32 and a temporary electrode 94 that has substantially the same shape and size as those of the pixel electrode 34 viewed from the top, which is connected to a part of the drain electrode 32D in a plane direction on the upper layer side of an insulating substrate GS; checking the operation of the TFTs 32 by an external inspection device using the temporary electrode 94; and removing the temporary electrode 94 after checking the operation of the TFTs 32.SELECTED DRAWING: Figure 5

Description

The present invention relates to a method for manufacturing an array substrate.

In a liquid crystal display device, a large number of pixels are arranged in a matrix on a liquid crystal panel, which is a main component, and a desired voltage is adjusted by adjusting the voltage applied to each pixel to control the orientation of liquid crystal molecules in the pixels. The image is displayed. The voltage applied to each pixel is adjusted by a switching element arranged for each pixel. It is known that a switching element is formed by laminating various thin films on one of the two substrates (array substrates) constituting the liquid crystal panel, and an example thereof is described in Patent Document 1 below. Things are disclosed.

International Publication No. 2011/118515

The switching element described in Patent Document 1 is a TFT (Thin Film Transistor), which has a gate electrode, a source electrode, a drain electrode, and an oxide semiconductor layer. These components are formed by laminating a patterned conductive film, insulating film, and semiconductor film, but due to film residue due to poor etching during pattern formation, etc., between the source electrode and drain electrode, and the gate electrode. An unnecessary leakage current may occur between the and drain electrodes. As a result, proper switching may not be performed and an appropriate voltage may not be applied to each pixel.

In order to detect the malfunction of this TFT, the operation is usually checked when the array substrate is completed (before the alignment film is applied). However, if many defects are found at this stage, the actual situation is that the delay in discovery causes a delay in production and a decrease in yield.

The technique described in the present specification has been completed based on the above circumstances, and an object thereof is to detect a malfunction of the array substrate at an early stage.

(1) The method for manufacturing an array substrate according to the technique described in the present specification is a method for manufacturing an array substrate in which a plurality of pixel electrodes and a plurality of thin film transistors are arranged in a matrix, and is located on the upper layer side of the insulating substrate. , A temporary structure that forms a source electrode and a drain electrode constituting the thin film transistor, is connected to a part of the drain electrode in the in-plane direction, and has substantially the same shape and size as the pixel electrode when viewed in a plane. An electrode is formed, the operation of the thin film transistor is confirmed by an external inspection device using the temporary electrode, and after the operation of the thin film transistor is confirmed, the temporary electrode is removed.

(2) Further, in the above manufacturing method, in addition to the above (1), a source metal film composed of a plurality of metal films is formed on the upper layer side of the insulating substrate, and the source metal film is formed on the upper layer side of the source metal films. The arranged metal film of at least one layer is patterned by using the source electrode, the source wiring connected to the source electrode, and the first resist pattern corresponding to the thin film pattern of the drain electrode as a mask, and then the source metal. Among the films, the unpatterned metal film is patterned using a second resist pattern corresponding to the thin film pattern of the pixel electrode as a mask, and the source electrode, the source wiring, the drain electrode, and the temporary electrode are patterned. May be formed, and after the operation is confirmed, the temporary electrode may be removed by etching.

(3) Further, in the above manufacturing method, in addition to the above (1), a source metal film composed of at least one metal film is formed on the upper layer side of the insulating substrate, and the source metal film is used as the source. The electrode, the source wiring connected to the source electrode, the drain electrode, and the third resist pattern corresponding to the thin film pattern of the temporary electrode are patterned as a mask, and the source electrode, the source wiring, the drain electrode, and the temporary electrode are patterned. An electrode may be formed, and after the operation is confirmed, the temporary electrode may be removed by etching.

(4) Further, in the above manufacturing method, in addition to the above (3), a portion in which the shading rate of the portion corresponding to the thin film pattern of the temporary electrode corresponds to the thin film pattern of the source electrode, the source wiring and the drain electrode. When a photomask smaller than the above is used as a halftone mask, the third resist pattern forms a resist film on the source metal film after the source metal film is formed, and is one of the resist films. The portion may be formed by exposing the portion through the halftone mask and developing the exposed resist film.

(5) Further, in the manufacturing method, in addition to the above (4), after forming the source electrode, the source wiring, the drain electrode, and the temporary electrode, the temporary electrode of the third resist pattern is formed. The portion corresponding to the thin film pattern may be etched to form a fourth resist pattern, and the temporary electrode may be removed by etching using the fourth resist pattern as a mask.

(6) Further, in the above manufacturing method, in addition to the above (5), the etching on the fourth resist pattern may be performed by dry etching using a gas corrosive agent.

(7) Further, in addition to any of the above (2) to (6), the above manufacturing method is a gate electrode constituting the thin film transistor on the insulating substrate before forming the source metal film. , And a gate wiring connected to the gate electrode may be formed.

(8) In addition to any of the above (1) to (7), the manufacturing method may use a metal material for the temporary electrode and a transparent conductive material for the pixel electrode.

According to the technique described in the present specification, a malfunction of the array substrate can be detected at an early stage.

Sectional view of liquid crystal panel Enlarged plan view of the display area of the array board Section III-III sectional view of FIG. FIG. 2 is a sectional view taken along line IV-IV. The flow chart which shows the manufacturing process of the array substrate which concerns on Embodiment 1. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The flow chart which shows the manufacturing process of the array substrate which concerns on Embodiment 2. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG. The figure which shows the manufacturing process of the array substrate shown in FIG.

<Embodiment 1>
The configuration and manufacturing method of the array substrate 30 according to the first embodiment will be described with reference to FIGS. 1 to 11B. A part of each drawing except FIGS. 5 and 12 shows an X-axis, a Y-axis, and a Z-axis, and each axis direction is drawn so as to be a common direction in each drawing. In the Z-axis direction, the upper side in the figure is the front side and the lower side is the back side.

As shown in FIG. 1, the array substrate 30 is used for the liquid crystal panel 10. The liquid crystal panel 10 has at least two substrates 20 and 30, a liquid crystal layer 18, and a seal portion 40. Of the two substrates 20 and 30, the display surface side (front side) of the liquid crystal panel 10 is the CF substrate (opposing substrate, color filter substrate) 20, and the opposite side (back side) is the array substrate (active matrix substrate, TFT substrate). It is set to 30. The liquid crystal layer 18 contains liquid crystal molecules which are sandwiched in the internal space between the substrates 20 and 30 and whose optical characteristics change with the application of an electric field. The seal portion 40 is interposed between the substrates 20 and 30 so as to surround the liquid crystal layer 18, and encloses the liquid crystal layer 18. Polarizing plates 10C and 10D are attached to the outer surfaces of both substrates 20 and 30, respectively. The in-plane of the liquid crystal panel 10 has a display area (active area) AA that can display an image and is arranged on the center side, and a non-display area (frame-like) that surrounds the display area AA and forms a frame shape (frame shape) when viewed on a plane. Non-active area) It is divided into NAA and.

As shown in FIG. 1, the CF substrate 20 includes a glass substrate GS (an example of an insulating substrate) and a plurality of thin films 20A laminated and formed on the glass substrate GS. The plurality of thin films 20A include a color filter and counter electrodes in which coloring portions such as R (red), G (green), and B (blue) are arranged in a predetermined arrangement.

As shown in FIG. 1, the array substrate 30 includes a glass substrate GS and a plurality of thin films 30A laminated and formed on the glass substrate GS. As shown in FIG. 2, the array substrate 30 has a plurality of pixel electrodes 34 having a substantially rectangular shape in a plan view and a plurality of TFTs 32 (switching elements) connected to each pixel electrode 34 in the display area AA. An example), a plurality of gate wirings (scanning lines) 36G, and a plurality of source wirings (data lines, signal lines) 36S.

The plurality of pixel electrodes 34 are arranged in a matrix. Each pixel electrode 34 has a main body portion 34A and a connecting portion 34B which are rectangular when viewed in a plane. The main body portion 34A is sufficiently larger than the connecting portion 34B and has a size that occupies almost the entire pixel electrode 34. However, in each figure, in order to clearly indicate the connecting portion 34B, it is assumed that the length of the connecting portion 34B in the X-axis direction is shown larger than the actual length. The main body 34A generates an electric field with the counter electrode of the CF substrate 20. A reference potential is applied to the counter electrode, and when a predetermined voltage is applied to the pixel electrode 34, an electric field is generated between the pixel electrode 34 and the counter electrode. The electric field switches the orientation state of the liquid crystal molecules contained in the liquid crystal layer 18. The connecting portion 34B projects in the in-plane direction from a part of the main body portion 34A toward the TFT 32, and connects the main body portion 34A and the TFT 32 (drain electrode 32D described later). The application of the voltage to the pixel electrode 34 is controlled by the TFT 32.

The gate wiring (scanning line) 36G and the source wiring (data line, signal line) 36S are orthogonal to each other, and are provided in a grid pattern so as to surround each pixel electrode 34. A TFT 32 is provided at a portion where the gate wiring 36G and the source wiring 36S are superposed on a flat surface. A part of the gate wiring 36G forms a gate electrode 32G constituting the TFT 32, and a part of the source wiring 36S forms a source electrode 32S constituting the TFT 32. The gate wiring 36G is connected to the gate electrode 32G, and the source wiring 36S is connected to the source electrode 32S, which transmit a drive signal to the TFT 32.

As shown in FIGS. 3 and 4, the array substrate 30 has a configuration in which various patterned thin films are laminated on the glass substrate GS. A gate electrode 32G, a gate wiring 36G, a gate insulating film 38, a semiconductor film 33, a source metal film SM, an upper layer insulating film 39, and a pixel electrode 34 are laminated on the array substrate 30 in this order from the glass substrate GS side. The gate electrode 32G and the gate wiring 36G are made of a laminated film of an aluminum (Al) layer and a titanium (Ti) layer. The gate insulating film 38 is made of a silicon oxide film (SiOx) which is a transparent inorganic insulating material, and insulates between the gate electrode 32G and the semiconductor film 33. The semiconductor film 33 is made of IGZO (Indium Gallium Zinc Oxide), which is an oxide semiconductor. The source metal film SM is a laminated film of an Al layer and a Ti layer, and constitutes a source electrode 32S and a drain electrode 32D of the TFT 32, and a source wiring 36S. Of the source metal film SM, the Ti layer on the upper layer side is referred to as the source upper layer metal film SM1, and the Al layer on the lower layer side is referred to as the source lower layer metal film SM2. The upper insulating film 39 is made of acrylic resin (PMMA), which is a transparent organic insulating material. The pixel electrode 34 is made of ITO (Indium Tin Oxide), which is a transparent conductive material.

As shown in FIG. 4, the TFT 32 has a source electrode 32S, a drain electrode 32D, a gate electrode 32G, and a semiconductor film 33. The TFT 32 is a bottom gate type, and a semiconductor film 33 is formed on the upper layer side of the gate electrode 32G so as to bridge the source electrode 32S and the drain electrode 32D. The bridge portion between the electrodes 32S and 32D in the semiconductor film 33 functions as a channel region through which the drain current flows. If these electrodes 32S, 32D, and 32G are not patterned as designed in the manufacturing process and there is a film residue, a leak current (so-called SD leak) may occur between the source electrode 32S and the drain electrode 32D. , A leak current (so-called GD leak) may occur between the gate electrode 32G and the drain electrode 32D. This may cause malfunction of the TFT 32.

Subsequently, a method of manufacturing the array substrate 30 will be described. The array substrate 30 first forms a gate electrode 32G, a gate wiring 36G, a gate insulating film 38, and a semiconductor film 33 on a glass substrate GS by a photolithography method (FIGS. 6A and 6B). Next, as shown in S10 and S15 of FIG. 5, the source metal film SM is formed on the semiconductor film 33 in the order of the source lower layer metal film SM2 and the source upper layer metal film SM1 (FIGS. 7A and 7B). Then, as shown in S20 of FIG. 5, a first resist film is formed, exposed, and developed on the source upper metal film SM1 to form a thin film pattern of the source electrode 32S, the source wiring 32S, and the drain electrode 32D. The corresponding first resist pattern RP1 is formed. Using the formed first resist pattern RP1 as a mask, as shown in S25 and S30 of FIG. 5, the source upper layer metal film SM1 is etched, and after etching, the first resist pattern RP1 is peeled off (FIGS. 8A and 8B).

Next, as shown in S35 of FIG. 5, the second resist film is formed, exposed, and developed to form the second resist pattern RP2 corresponding to the thin film pattern of the pixel electrode 34 (FIGS. 9A and 9B). ). When the second resist film is exposed, the photoresist mask M34 used in the process of forming the pixel electrode 34 is used (FIG. 9B). Using the formed second resist pattern RP2 as a mask, as shown in S40 and S45 of FIG. 5, the source lower layer metal film SM2 is etched to peel off the second resist pattern RP2. As a result, the source electrode 32S, the source wiring 36S, and the drain electrode 32D are formed in the portion of the source metal film SM in which the source lower layer metal film SM2 and the source upper layer metal film SM1 are laminated. Further, in the source metal film SM, a temporary electrode 94 is formed in a portion where only the source lower layer metal film SM2 remains and the source upper layer metal film SM1 is not laminated (FIGS. 10A and 10B). The temporary electrode 94 is connected to a part of the drain electrode 32D in the source lower layer metal film SM2. Since the temporary electrode 94 is patterned using the photoresist mask M34 of the pixel electrode 34 as described above, it has the same shape and size as the main body 34A of the pixel electrode 34 in a plan view (substantially the same as the pixel electrode 34). Has the same shape and size).

Next, as shown in S50 of FIG. 5, the operation of the TFT 32 is confirmed by an external inspection device using the formed temporary electrode 94. For example, as an external inspection device, a device that inputs a drive signal of the TFT 32 from the gate wiring 36G and the source wiring 36S and detects the voltage (or generated electric field) of the temporary electrode 94 as an output is used. If an appropriate value is detected as the voltage of the temporary electrode 94 in the inspection device, the normal operation of the TFT 32 to which the drive signal is input can be confirmed. On the contrary, if an appropriate value is not detected as the voltage of the temporary electrode 94, it can be seen that the TFT 32 to which the drive signal is input has a malfunction.

Next, as shown in S55 of FIG. 5, the temporary electrode 94 of the source lower layer metal film SM2 is etched and removed from the array substrate 30 in which the normal operation of the TFT 32 is confirmed (FIGS. 11A and 11B). Then, the upper insulating film 39 and the pixel electrode 34 are formed by a photolithography method to form a laminated structure shown in FIGS. 2 and 3. At the same time, peripheral circuits and the like are formed in the non-display area NAA to complete the array substrate 30.

According to the manufacturing method of the array substrate 30 described above, when the TFT 32 is formed, the temporary electrode 94 is used instead of the pixel electrode 34, and the operation of the TFT 32 can be confirmed. Since the operation of the TFT 32 can be confirmed before the formation of the pixel electrode 34 and the peripheral circuit, it is possible to detect a malfunction at an early stage. Further, since the temporary electrode 94 is removed after the operation is confirmed using the temporary electrode 94, the array substrate 30 can be completed by the conventional manufacturing process thereafter. Since the temporary electrode 94 is patterned by using the photoresist mask M34 of the pixel electrode 34, it is not necessary to prepare a photoresist mask dedicated to the temporary electrode 94, and the manufacturing process can be started up at an early stage. Further, the source metal film SM is composed of a plurality of metal films, and the source upper layer metal film SM1 and the source lower layer metal film SM2 are patterned by different resist patterns (first resist pattern RP1 and second resist pattern RP2). The temporary electrode 94 can be easily formed, and the temporary electrode 94 can be easily removed after confirming the operation of the TFT 32.

<Second Embodiment>
The manufacturing method of the array substrate 30 according to the second embodiment will be described with reference to FIGS. 12 to 16B. The description of the configuration, manufacturing process, operation and effect similar to that of the first embodiment will be omitted.

The configuration of the array substrate 30 according to the present embodiment is the same as that of the first embodiment, and the manufacturing method thereof is the first embodiment up to the film formation (S15) of the source upper layer metal film SM1 as shown in FIG. Similar to form. Next, as shown in S120 of FIG. 12, a third resist film is formed, exposed, and developed on the source upper layer metal film SM1, and the source electrode 32S, the source wiring 32S, the drain electrode 32D, and the temporary electrode are formed. A third resist pattern RP3 corresponding to the thin film pattern of 94 (main body 34A of the pixel electrode 34) is formed (FIGS. 13A and 13B). A halftone mask M134 is used when exposing the third resist film. The halftone mask M134 is a photomask in which the shading rate of the portion M134A corresponding to the thin film pattern of the temporary electrode 94 is smaller than the shading rate of the portion M134B corresponding to the thin film pattern of the source electrode 32S, the source wiring 32S, and the drain electrode 32D. is there. Using this third resist pattern RP3 as a mask, the source upper layer metal film SM1 and the source upper layer metal film SM2 are etched as shown in S125 of FIG. As a result, a source electrode 32S, a source wiring 36S, a drain electrode 32D, and a temporary electrode 94 composed of the source upper layer metal film SM1 and the source lower layer metal film SM2 are formed under the third resist pattern RP3 (FIGS. 14A and 14A and FIG. 14B).

Next, as shown in S135 of FIG. 12, only the portion of the third resist pattern RP3 corresponding to the thin film pattern of the temporary electrode 94 is removed by dry etching (ashing) using a gas corrosive agent, and the fourth resist pattern RP3 is removed. The resist pattern is RP4. Since this removed portion corresponds to the portion M134A having a low shading rate of the halftone mask M134 at the time of exposure of the third resist film, it can be selectively removed. As a result, the third resist film on the temporary electrode 94 is removed (FIGS. 15A and 15B).

Next, as shown in S50 of FIG. 12, the operation of the TFT 32 is confirmed by an external inspection device as in the first embodiment using the temporary electrode 94. Then, as shown in S155 of FIG. 12, the temporary electrode 94 is etched and removed by the fourth resist pattern RP4 with respect to the array substrate 30 whose normal operation has been confirmed (FIGS. 16A and 16B). Then, after removing the fourth resist pattern RP4, the upper insulating film 39 and the pixel electrode 34 are formed in the same manner as in the first embodiment to form the laminated structure shown in FIGS. 2 and 3. At the same time, peripheral circuits and the like are formed in the non-display area NAA to complete the array substrate 30.

According to the method for manufacturing the array substrate 30 according to the present embodiment, in order to form the third resist pattern RP3 using the halftone mask M134, the fourth resist pattern RP4 etches a part of the third resist pattern RP3. Is easily formed by. Since it is not necessary to form, expose, and develop a new resist film in order to form the fourth resist pattern RP4, the formation and removal of the temporary electrode 94 can be made easier.

<Other embodiments>
The techniques described in the present specification are not limited to the embodiments described above and the drawings, and for example, the following embodiments are also included in the technical scope of the present invention.

(1) The glass substrate GS may be a heat-resistant resin substrate.

(2) The materials of the gate electrode 32G, the gate wiring 36G, the source upper layer metal film SM1 and the source lower layer metal film SM2 are Al, Ti, copper (Cu), molybdenum (Mo), silver (Ag), and tungsten (W). It may be a single-layer film of a metal such as, a single-layer film of an alloy of these, or a laminated film obtained by combining these single-layer films and laminating them in an arbitrary number of layers.

(3) The source metal film SM according to the second embodiment may be a single-layer film in which the source upper layer metal film SM1 and the source lower layer metal film SM2 are made of the same material.

(4) The material of the gate insulating film 38 may be another transparent inorganic insulating material such as Si or SiN. The material of the semiconductor film 33 may be another semiconductor material. The material of the upper insulating film 39 may be another transparent organic insulating material such as a polyimide resin. The material of the pixel electrode 34 may be a transparent conductive material other than ITO.

(5) The gate electrode 32G may be formed by branching from the gate wiring 36G. Further, the source electrode 32S may be formed by branching from the source wiring 36S.

(6) The TFT 32 may be a top date type.

(7) The liquid crystal panel 10 may also have a touch panel function for detecting a position input by the user based on a displayed image. In that case, the array substrate 30 is provided with touch panel electrodes and touch panel wiring for exerting the touch panel function.

(8) The liquid crystal panel 10 may use other operation methods such as IPS (In-Plane Switching) and FFS (Fringe Field Switching). In the case of the IPS system or the FFS system, the array substrate 30 is provided with a common electrode to which a reference potential is applied, and the CF substrate 20 is not provided with a counter electrode.

(9) The external inspection device for confirming the operation of the TFT 32 using the temporary electrode 94 may be of another detection method. If the external inspection device has specifications that allow the operation of the TFT 32 to be confirmed even when the resist film remains on the temporary electrode 94, the manufacturing process for removing the resist film on the temporary electrode 94 (first implementation). Before performing the manufacturing process S45 of FIG. 5 in the embodiment and the manufacturing process S135 of FIG. 12 in the second embodiment, the operation confirmation S50 of the TFT 32 using the temporary electrode 94 may be performed.

(10) The technique described in the present specification can also be applied to a display panel in which a functional organic molecule (medium layer) other than the liquid crystal layer 18 is sandwiched between the two substrates 20 and 30.

10 ... Liquid crystal panel (display panel), 30 ... Array substrate, 32 ... TFT (thin film), 32S ... Source electrode, 32D ... Drain electrode, 34 ... Pixel electrode, 36G ... Gate wiring, 36S ... Source wiring, 40 ... Seal , 94 ... Temporary electrode, GS ... Glass substrate (insulating substrate), M134 ... Halftone mask, RP1 ... 1st resist pattern, RP2 ... 2nd resist pattern, RP3 ... 3rd resist pattern, RP4 ... 4th resist pattern, SM ... Source metal film

Claims (8)

A method for manufacturing an array substrate in which a plurality of pixel electrodes and a plurality of thin film transistors are arranged in a matrix.
A source electrode and a drain electrode constituting the thin film transistor are formed on the upper layer side of the insulating substrate, and a part of the drain electrode is connected in the in-plane direction to be substantially the same as the pixel electrode when viewed in a plane. Form a temporary electrode with shape and size,
Using the temporary electrode, the operation of the thin film transistor was confirmed by an external inspection device.
A method for manufacturing an array substrate from which the temporary electrode is removed after confirming the operation of the thin film transistor. A source metal film composed of a plurality of metal films is formed on the upper layer side of the insulating substrate.
Of the source metal films, at least one layer of the metal film arranged on the upper layer side is masked with a first resist pattern corresponding to the thin film pattern of the source electrode, the source wiring connected to the source electrode, and the drain electrode. Patterned as
Next, among the source metal films, the unpatterned metal film is patterned using a second resist pattern corresponding to the thin film pattern of the pixel electrode as a mask, and the source electrode, the source wiring, and the drain are patterned. The electrode and the temporary electrode are formed,
The method for manufacturing an array substrate according to claim 1, wherein the temporary electrode is removed by etching after the operation is confirmed. A source metal film made of at least one metal film is formed on the upper layer side of the insulating substrate.
The source metal film is patterned using the source electrode, the source wiring connected to the source electrode, the drain electrode, and the third resist pattern corresponding to the thin film pattern of the temporary electrode as a mask, and the source electrode and the source wiring. , The drain electrode, and the temporary electrode are formed.
The method for manufacturing an array substrate according to claim 1, wherein the temporary electrode is removed by etching after the operation is confirmed. When a photomask in which the shading rate of the portion corresponding to the thin film pattern of the temporary electrode is smaller than that of the portion corresponding to the thin film pattern of the source electrode, the source wiring, and the drain electrode is used as a halftone mask.
The third resist pattern is
After forming the source metal film, a resist film is formed on the source metal film.
A part of the resist film is exposed through the halftone mask,
The method for manufacturing an array substrate according to claim 3, which is formed by developing the exposed resist film. After forming the source electrode, the source wiring, the drain electrode, and the temporary electrode,
Of the third resist pattern, the portion corresponding to the thin film pattern of the temporary electrode is etched to form the fourth resist pattern.
The method for manufacturing an array substrate according to claim 4, wherein the temporary electrode is removed by etching using the fourth resist pattern as a mask. The method for manufacturing an array substrate according to claim 5, wherein the etching for the fourth resist pattern is performed by dry etching using a gas corrosive agent. Before forming the source metal film,
The method for manufacturing an array substrate according to any one of claims 2 to 6, wherein a gate electrode constituting the thin film transistor and a gate wiring connected to the gate electrode are formed on the insulating substrate. A metal material is used for the temporary electrode,
The method for manufacturing an array substrate according to any one of claims 1 to 6, wherein a transparent conductive material is used for the pixel electrodes.

Images