JP2020533899A - CRC interleaving pattern for polar code - Google Patents

Abstract

According to some embodiments, a method of operation of a wireless transmitter in a wireless communication network uses a linear external code to generate a set of external parity bits p with a data bit u of length K. Encoding a set of information carrying u and acting to distribute some bits of the set of parity bits p before some data bits u, depending on the number of data bits K Interleaving a set of external parity bits p and data bits u using a given interleaving mapping function that is possible, and interleaving using a polar encoder to generate a set of encoded bits x. Includes encoding the bits that have been made. Various interleaving mapping functions are disclosed. [Selection diagram] FIG. 7

Description

Certain embodiments are intended for wireless communication, and more specifically for cyclic redundancy check (CRC) interleaving patterns for polar codes.

Introduction E. Arıkan, "Cannel Polization: A Method for Constructing Capacity-Achieving Codes for Symmetrical Binary-Input Mechanism Information Channels", IEEE Corporation, IEEE Polar Code, proposed by pages 55, 3051-3073, July 2009, is a constructive coding that achieves the symmetrical capacitance of a binary input discrete storage channel under a low complexity sequential elimination (SC) decoder. It is a class of a method (constractive coding scheme). However, the finite length performance of polar codes under SC is not competitive compared to other modern channel coding schemes such as low density parity check (LDPC) codes and turbo codes. .. The SC list (SCL) decoder is described in I.C. Tal and A. Vardy, "List Recording of Polar Codes", Proceedings of IEEE Symp. Inf. Proposed in Theory, pp. 1-5, 2011, SCL decoders are approaching the performance of maximum-likelihood (ML) decoders. By concatenating a simple cyclic redundancy check (CRC) coding, the performance of the linked polar code competes with the performance of the well-optimized LDPC and turbo code. As a result, Polar Code is considered a candidate for future 5th generation (5G) wireless communication systems.

Polar coding translates a pair of equivalent binary input channels into two separate channels of different qualities, one better than the original binary input channel and one worse than the original binary input channel. Repeating such a pairwise polarization operation for a set of N = 2 ⁿ independent uses of a binary input channel results in a set of 2 ⁿ "bit channels" of varying quality. Some of the bit channels are nearly complete (ie, error-free), while the rest of the bit channels are nearly useless (ie, noisy overall). Polar coding uses a nearly complete channel to send data to the receiver and sets the input to the useless channel to have a fixed or frozen value (eg 0) known to the receiver. To do. For this reason, the input bits to a nearly useless channel and the input bits to a nearly complete channel are usually referred to as frozen bits and non-frozen (or information) bits, respectively. Only non-frozen bits are used to carry data in the polar code. Loading the data into the appropriate information bit location has a direct impact on the performance of the polar code. A set of information bit locations is commonly referred to as an information set. A description of the structure of the length 8 polar cord is shown in FIG.

Original polar codes, such as those proposed by Arikan, have proven to be the capacity achieved using a low complexity sequential erase (SC) decoder, but the finite length performance of polar codes under SC is , LDPC and turbo code, etc., are not competitive compared to other modern channel coding schemes. A more complex decoder, the SC List (SCL) decoder, is available in the Proceedings of IEEE Symp. Inf. Theory, pp. 1-5, 2011 I.D. Tal and A. Proposed in Vardy, "List Recording of polar codes", where a list of two or more remaining decision paths is maintained in the decoding process, the performance obtained is still unsatisfactory. To check if any of the candidate routes in the list are correctly decoded by concatenating the linear external code, the Cyclic Redundancy Check (CRC) code, with the original polar code as the internal code. Further suggested that external code could be used for. Such a two-step decoding process significantly improves performance and makes polar code compete with the performance of well-optimized LDPC and turbocode. However, the two-step decryption process is generally suboptimal because each step does not consider the structure of other (internal or external) code.

The two-step decoding process also increases the decoding latency because the external decoder typically has to wait for the internal decoder to finish decoding before the external decoder operates. A method of improving the average decoding latency is needed to compensate for the delay caused by the extra processing. One method is to attempt to terminate decoding when one of the decoded CRC bits is found to be inconsistent with the previously decoded information bits on which the CRC bits depend. .. However, this method is not valid when all CRC bits are attached to the ends of the code block.

The embodiments described herein include applying a bit interleaver with a particular interleaving pattern between a linear external code (eg, a cyclic redundancy check (CRC) code) and a polar internal code. The interleaving pattern allows the decoder to decode early when some of the CRC bits encountered early in the sequential decoding process are used for early error detection while maintaining a low false alarm rate (FAR). Allows you to achieve an end. In addition, the interleaver is also out of the parity bits generated by the external code to ensure that it affects the decisions made in the modified sequential erase list (SCL) decoder for the polar internal code. Allows some to be used earlier. This facilitates single-step decoding for the overall linked code, which takes into account the structure of the external code, and is therefore superior to the two-step equivalent of the fully linked code.

According to some embodiments, a method of operation of a wireless transmitter in a wireless communication network uses a linear external code to generate a set of external parity bits p with a data bit u of length K. Encoding a set of information carrying u and acting to distribute some bits of the set of parity bits p before some data bits u, depending on the number of data bits K Interleaving a set of external parity bits p and data bits u using a given interleaving mapping function that is possible, and interleaving using a polar encoder to generate a set of encoded bits x. Includes encoding the bits that have been made. The method may further include transmitting a set of coded bits x to the radio receiver.

によって示されるテンプレートインターリーバの入力は、以下のビットマッピングによって与えられる。

In certain embodiments, a given interleaving mapping function includes a template interleaver for the maximum value of K, called K _max , the template interleaver includes a high index bit mapper, and K data bits are template interleavers. Loaded at the high index position of the template input, where u = [u ₀ , u ₁ , ... .. .. , U _K-1 ]

The input of the template interleaver indicated by is given by the following bit mapping.

In some embodiments, the template interleaver includes a low index bit mapper, and K data bits are loaded in reverse at the low index position of the template interleaver input, where the template interleaver input is: Given by the bit mapping of.

According to some embodiments, the radio transmitter comprises a processing circuit element. The processing circuit element uses a linear external code to encode a set of information carrying the data bits u in order to generate a set of external parity bits p with the data bits u of length K, and the data bits. External parity bits using a given interleaving mapping function that depends on a few K and is capable of acting to distribute some bits of the previous set of parity bits p for some data bits u. It can operate to interleave a set of ps with the data bits u and to encode the interleaved bits using a polar encoder to generate a set of encoded bits x. .. The processing circuit element may be further operational to transmit a set of coded bits x to the radio receiver.

In certain embodiments, the radio transmitter includes a radio device (eg, user equipment) or base station (eg, gNB).

According to some embodiments, the method of operation of a radio receiver in a wireless communication network, when decoding the received set of polar coded bits, determining a decoder reaches distributed CRC bits p _i and , Each list l, l = 0,1,. .. .. , One for L-1, dispersion and the CRC calculating the bit _{p i} of L estimates _p i (l), for each _p i _(l), info bits associated with _p i (l) ( Determining whether the info bit) leads to a normal parity check, and if it is determined that there is no normal parity check for each _pi (l), the decoding is terminated and it is determined that a normal parity check exists. Then, it includes continuing the decoding.

According to some embodiments, the method of operation of a radio receiver in a wireless communication network, when decoding the received set of polar coded bits by determining the decoder reaches the dispersion CRC bits p _i there are, dispersed CRC bits _{p i} is masked by bits _{q i, w i = (p} i + q i) becomes mod2, and determining a decoder reaches distributed CRC bits _{p i,} each list l, l = 0,1,. .. .. , One for L-1, and calculating the variance CRC bits _{p i} of L estimates _w i (l), for each _w i (l), the mask _{p i = (w i + q} i) mod2 and removing, for each p _{i (l),} and the info bit associated with the p i _(l) to determine whether lead to normal parity check, normal parity check for each p _{i (l)} If it is determined that there is no, the decoding is terminated, and if it is determined that a normal parity check exists, the decoding is continued.

In certain embodiments, the decoding comprises a template deinterleaver and a bit demapper that perform the reverse of the bit mapping of any of the interleaving functions described herein.

According to some embodiments, the radio receiver comprises a processing circuit element. Processing circuitry, when decoding the received set of polar coded bits, and determining a decoder reaches distributed CRC bits p _i, each list l, l = 0, 1,. .. .. , One for L-1, and calculating the variance CRC bits _{p i} of L estimates _p i (l), for each _p i _(l), is info bits associated with _p i (l) Determining whether it leads to a normal parity check, ending decoding if it is determined that there is no normal parity check for each _pi (l), and decoding if it is determined that a normal parity check exists. It is possible to work to do and continue.

According to some embodiments, the radio receiver comprises a processing circuit element. Processing circuitry, when decoding the received set of polar coded bits, comprising: determining a decoder reaches distributed CRC bits p _i, distributed CRC bits p _i is masked by bits q _i, w _i = become _{(p i + q i) mod2} , and determine that the decoder has reached the dispersion CRC bits _{p i,} each list l, l = 0,1 ,. .. .. , One for L-1, and calculating the variance CRC bits _{p i} of L estimates _w i (l), for each _w i (l), the mask _{p i = (w i + q} i) mod2 and removing, for each p _{i (l),} and the info bit associated with the p i _(l) to determine whether lead to normal parity check, normal parity check for each p _{i (l)} If it is determined that there is no, the decoding is terminated, and if it is determined that a normal parity check exists, the decoding can be continued.

According to some embodiments, the radio transmitter comprises coding modules (1350, 1450). The coding module uses a linear external code to encode a set of information that carries the data bits u in order to generate a set of external parity bits p with a data bit u of length K, and the data bits. External parity bits using a given interleaving mapping function that depends on a few K and can operate to distribute some bits of the previous set of parity bits p for some data bits u. It can operate to interleave a set of ps with the data bits u and to encode the interleaved bits using a polar encoder to generate a set of encoded bits x. ..

According to some embodiments, the radio receiver comprises a decoding module (1350, 1450). Decoding module, when decoding the received set of polar coded bits, and determining a decoder reaches distributed CRC bits p _i, each list l, l = 0, 1,. .. .. , One for L-1, and calculating the variance CRC bits _{p i} of L estimates _p i (l), for each _p i _(l), is info bits associated with _p i (l) Determining whether it leads to a normal parity check, ending decoding if it is determined that there is no normal parity check for each _pi (l), and decoding if it is determined that a normal parity check exists. It is possible to work to do and continue.

According to some embodiments, the radio receiver comprises a decoding module (1350, 1450). Decoding module, when decoding the received set of polar coded bits, comprising: determining a decoder reaches distributed CRC bits p _i, distributed CRC bits p _i is masked by bits q _i, w _i = become _{(p i + q i) mod2} , and determine that the decoder has reached the dispersion CRC bits _{p i,} each list l, l = 0, 1,. .. .. , One for L-1, and calculating the variance CRC bits _{p i} of L estimates _w i (l), for each _w i (l), the mask _{p i = (w i + q} i) mod2 and removing, for each p _{i (l),} and the info bit associated with the p i _(l) to determine whether lead to normal parity check, normal parity check for each p _{i (l)} If it is determined that there is no, the decoding is terminated, and if it is determined that a normal parity check exists, the decoding can be continued.

In certain embodiments, the radio receiver includes a radio device (eg, user equipment) or base station (eg, gNB).

Computer program products are also disclosed. Computer program products include instructions stored on non-temporary computer-readable media, which, when executed by a processor, are linear to generate a set of external parity bits p with data bits u of length K. The step of encoding a set of information carrying data bits u using an external code and some of the set of parity bits p before some data bits u, depending on the number of data bits K A polar step to interleave a set of external parity bits p with a set of data bits u and a set of coded bits x using a given interleaving mapping function that can operate to distribute the bits. The encoder is used to perform the steps of encoding the interleaved bits. The instruction may further perform the step of transmitting a set of coded bits x to the radio receiver.

Another computer program product comprises instructions stored on a non-temporary computer-readable medium, which, when executed by the processor, when the decoder decodes the received set of polar-encoded bits, the distributed CRC bits. determining to reach p _i, each list l, l = 0,1 ,. .. .. , One for L-1, and calculating the variance CRC bits _{p i} of L estimates _p i (l), for each _p i _(l), is info bits associated with _p i (l) A step to determine whether it leads to a normal parity check, a step to end decoding if it is determined that there is no normal parity check for each _pi (l), and a decoding if it is determined that a normal parity check exists. Carry out the steps to continue.

Another computer program product comprises instructions stored on a non-temporary computer-readable medium, which, when executed by the processor, when the decoder decodes the received set of polar-encoded bits, the distributed CRC bits. and determining to reach p _i, distributed CRC bits _{p i} is masked by bits _{q i,} becomes _{w i = (p i + q} i) mod2, determines that the decoder has reached the dispersion CRC bits _{p i} Steps and each list l, l = 0,1,. .. .. , One for L-1, and calculating the variance CRC bits _{p i} of L estimates _w i (l), for each _w i (l), the mask _{p i = (w i + q} i) mod2 removing the, for each p _{i (l),} determining whether the info bits leading to normal parity check relating to p i _(l), normal parity check for each p _{i (l)} If it is determined that there is no decoding, a step of ending the decoding and a step of continuing the decoding if it is determined that a normal parity check exists are performed.

Certain embodiments may include some or all of the following advantages, or may not include any of the following advantages: For example, if the decoded info bits in each candidate in the decryption list do not match the decoded value of the CRC bit, a particular interleaving pattern allows the decoder to terminate decoding early. This reduces the overall decryption latency. For existing methods, the length of the CRC bits K The entire _CRC vector is typically used in CRC checking after all the information bits have been decoded. For certain embodiments described herein, CRC checking may be performed bit by bit for each individual CRC bit during sequential erase list decoding. The interleaving pattern balances the early termination gain in decoding with the false alarm probability (ie, the probability of falsely accepting an incorrectly decrypted code block).

Certain embodiments also include any linear external code and polar internal code through the wise design of the interleaver, as opposed to a two-step decoding process in which the internal polar code is decrypted first and the external code is decrypted first. Allows a single-step decryption process for concatenation with. Such single-step decoding considers the structure of polar internal code and the structure of linear external (eg CRC) code together and therefore improves performance compared to a two-step solution.

For a more complete understanding of the embodiments and their features and advantages, the following description is then referenced, along with the accompanying drawings.

It is a figure which shows an example of the polar code structure of N = 8. FIG. 3 is a block diagram showing an exemplary wireless network according to a particular embodiment. It is a block diagram which shows the encoder structure of the interleaved connected polar code by a specific embodiment. It is a block diagram which shows the 1-step decoder structure of the interleaved connected polar code by a specific embodiment. It is a block diagram which shows the template interleaver of a fixed size K _max according to a specific embodiment. It is a block diagram which shows the structure of the deinterleaver by a specific embodiment. It is a flow chart which shows the exemplary method in the wireless transmitter by a specific embodiment. It is a flow diagram which shows the exemplary method in the wireless receiver by a specific embodiment. It is a block diagram which shows an exemplary embodiment of a wireless device. It is a block diagram which shows the exemplary component of a wireless device. It is a block diagram which shows the exemplary embodiment of a network node. It is a block diagram which shows the exemplary component of a network node.

The polar code achieves the symmetric capacitance of the binary input discrete storage channel under a low complexity sequential erase (SC) decoder. However, the finite length performance of polar cords under SC is not competitive compared to other modern channel coding schemes such as low density parity check (LDPC) cords and turbo cords. The SC list (SCL) decoder is approaching the performance of the optimal maximum likelihood (ML) decoder. By concatenating simple cyclic redundancy check (CRC) coding, the performance of the concatenated polar code competes with the performance of the well-optimized LDPC and turbo code. As a result, polar codes can be used for 5th generation (5G) wireless communication systems.

By concatenating a linear external code, such as a CRC code, with the original polar code as the internal code, the external code can be used to check if any of the candidate routes in the list are correctly decrypted. Although the two-step decoding process significantly improves performance, the two-step decoding process is generally suboptimal because each step does not consider the structure of other (internal or external) code.

The two-step decoding process also increases the decoding latency because the external decoder typically has to wait for the internal decoder to finish decoding before the external decoder operates. To compensate for the delay caused by the extra processing, certain embodiments improve the average decoding latency.

The particular embodiment described herein eliminates the problems described above and provides a bit interleaver with a particular interleaving pattern between a linear external code (eg, a CRC code) and a polar internal code. Including applying. The interleaving pattern allows the decoder to decode early when some of the CRC bits encountered early in the sequential decoding process are used for early error detection while maintaining a low false alarm rate (FAR). Allows you to achieve an end. In addition, the interleaver also uses some of the parity bits generated by the external code earlier to ensure that it affects the decisions made in the modified SCL decoder for the polar internal code. Make it possible. This facilitates single-step decoding for fully concatenated codes that take into account the structure of the external code, and is therefore superior to the two-step equivalent of fully concatenated codes.

The interleaving pattern balances the early termination gain in decoding with the false alarm probability (ie, the probability of falsely accepting an incorrectly decrypted code block). Certain embodiments also include any linear external code and polar internal code through the wise design of the interleaver, as opposed to a two-step decoding process in which the internal polar code is decrypted first and the external code is decrypted first. Allows a single-step decryption process for concatenation with. Such single-step decoding considers the structure of polar internal code and the structure of linear external (CRC) code together, thus improving performance compared to a two-step solution.

The following description describes a number of specific details. However, it should be understood that embodiments may be implemented without these specific details. In other cases, well-known circuits, structures and techniques are not shown in detail to avoid obscuring the understanding of this description. Those skilled in the art will be able to implement appropriate functionality without undue experimentation using the included instructions.

References herein to "one embodied", "an embodied", "exemplary embodiments", etc., are described in the embodiments described in particular feature, structure, and Alternatively, it indicates that it may include properties, but not all embodiments may necessarily include specific features, structures, or properties. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or property is described for an embodiment, implementing such feature, structure, or property for other embodiments, whether explicitly described or not. Is stated to be within the knowledge of those skilled in the art.

Specific embodiments are described with reference to FIGS. 2-10B of the drawings, and similar numbers are used for similar and corresponding parts of the various drawings. Although long term evolution (LTE) and NR are used throughout the disclosure as exemplary cellular systems, the ideas presented herein may apply to other wireless communication systems as well.

FIG. 2 is a block diagram showing an exemplary wireless network according to a particular embodiment. The wireless network 100 includes one or more wireless devices 110 (such as mobile phones, smartphones, laptop computers, tablet computers, MTC devices, or any other device capable of providing wireless communication) and (base stations). , E-node B, gNB, etc.) and include a plurality of network nodes 120. The wireless device 110 is sometimes called a UE. Network node 120 serves coverage area 115 (also referred to as cell 115).

Generally, the radio device 110 within the coverage of the network node 120 (eg, in the cell 115 served by the network node 120) communicates with the network node 120 by transmitting and receiving the radio signal 130. For example, the radio device 110 and the network node 120 may communicate with a radio signal 130 that includes voice traffic, data traffic, and / or control signals. The network node 120 that communicates voice traffic, data traffic, and / or control signals to the wireless device 110 may be referred to as a serving network node 120 for the wireless device 110. Communication between the wireless device 110 and the network node 120 is sometimes referred to as cellular communication. The radio signal 130 may include both downlink transmission (from network node 120 to wireless device 110) and uplink transmission (from wireless device 110 to network node 120).

Each network node 120 may have a single transmitter or multiple transmitters for transmitting the signal 130 to the wireless device 110. In some embodiments, the network node 120 may include a multi-input multi-output (MIMO) system. The radio signal 130 may include one or more beams. A particular beam can be beamformed in a particular direction. Each wireless device 110 may have a single receiver or multiple receivers for receiving the signal 130 from the network node 120 or another wireless device 110. The radio device 110 may receive one or more beams including the radio signal 130.

The radio signal 130 may be transmitted on a time frequency resource. Time frequency resources can be divided into radio frames, subframes, slots, and / or mini slots. The network node 120 may dynamically schedule subframes / slots / minislots as uplinks, downlinks, or combinations of uplinks and downlinks. The different radio signals 130 may include different transmission processing times.

The network node 120 may operate in a licensed frequency spectrum, such as the LTE spectrum. The network node 120 may also operate in an unlicensed frequency spectrum, such as a 5 GHz Wi-Fi spectrum. In the unlicensed frequency spectrum, the network node 120 can co-exist with other devices such as IEEE 802.11 access points and terminals. To share the unlicensed spectrum, the network node 120 may perform a listen before talk (LBT) protocol before transmitting or receiving the radio signal 130. The wireless device 110 may also operate in one or both of the licensed and unlicensed spectra, and in some embodiments, the LBT protocol may also be implemented prior to transmitting the radio signal 130. Both the network node 120 and the wireless device 110 may also operate in the licensed shared spectrum.

For example, the network node 120a may operate in the licensed spectrum and the network node 120b may operate in the unlicensed spectrum. The wireless device 110 may operate in both licensed and unlicensed spectra. In certain embodiments, network nodes 120a and 120b may be configured to operate in licensed spectrum, unlicensed spectrum, licensed shared spectrum, or any combination. The coverage area of cell 115b is shown to be included within the coverage area of cell 115a, but in certain embodiments, the coverage area of cell 115a and the coverage area of cell 115b may partially overlap. Or it may not overlap at all.

In certain embodiments, the wireless device 110 and the network node 120 may perform carrier aggregation. For example, the network node 120a may serve the wireless device 110 as a PCell, and the network node 120b may serve the wireless device 110 as a SCell. Network node 120 may perform self-scheduling or cross-scheduling. If the network node 120a is operating in the licensed spectrum and the network node 120b is operating in the unlicensed spectrum, the network node 120a may provide license-assisted access to the unlicensed spectrum (ie, network node 120a). Is the LAA PCell and the network node 120b is the LAA SCell).

In certain embodiments, the radio signal 130 may be encoded using a polar code. For example, the radio device 110 and / or the network node 120 may use a polar code to encode the radio signal 130. In some embodiments, the coding may include an interleaver. The interleaver will be described in more detail with respect to FIGS. 3-8.

In the wireless network 100, each network node 120 is of any suitability, such as long term evolution (LTE), LTE Advanced, UMTS, HSPA, GSM, cdma2000, NR, WiMax, WiFi, and / or other suitable wireless access technologies. Wireless access technology can be used. The wireless network 100 may include any suitable combination of one or more wireless access technologies. As an example, various embodiments can be described within the context of some wireless access technologies. However, the scope of the present disclosure is not limited to those examples, and other embodiments may use different wireless access techniques.

As described above, wireless network embodiments may include one or more wireless devices and one or more different types of wireless network nodes capable of communicating with the wireless device. The wireless network may also include any additional elements suitable to support communication between wireless devices, or between a wireless device and another communication device (such as a landline phone). The wireless device may include any suitable combination of hardware and / or software. For example, in certain embodiments, the wireless device, such as the wireless device 110, may include the components described with respect to FIG. 9A below. Similarly, network nodes can include any suitable combination of hardware and / or software. For example, in certain embodiments, network nodes, such as network node 120, may include the components described below with respect to FIG. 10A.

A particular embodiment includes a wisely designed interleaver with a particular interleaver pattern between the linear outer code and the polar inner code. The interleaving pattern is such that if the decoded value of some CRC bits does not match the value of the corresponding information bit, the CRC bit can be terminated earlier to reduce the average latency. To the beginning of the code block. These interleaving patterns are designed to maximize early termination gain while maintaining low FAR.

According to certain embodiments of the interleaver, single-pass or single-step decoding is performed using a slightly modified SCL polar decoder to take advantage of both internal and external coder structures together. Will be done. The interleaver ensures that some of the parity bits generated by the external code are used earlier to ensure that the decisions made in the modified SCL decoder for the polar internal code are used. to enable. This facilitates single-step decoding for fully concatenated codes and is superior to the two-step equivalent of fully concatenated codes.

A particular embodiment includes an interleaver with a particular interleaving pattern between a linear external code, such as a CRC code, and a polar internal code, for each possible number of information bits. The interleaver distributes some CRC bits before some information bits. This allows the SCL decoder to terminate the decoding process when the decoded value of any of these CRC bits does not match the information bits on which the CRC bits depend for any candidate in the list. Interleaving CRC bits also facilitates list decoding for internal polar code that takes into account the dependency structure of parity bits and data bits from external code. An example is shown in FIG.

FIG. 3 is a block diagram showing an encoder structure of interleaved and connected polar cords according to a specific embodiment. The information-carrying data bits u of length K are first encoded by the linear external encoder 10 to generate some external parity bits p with the data bits u (the linear external code is typically a CRC code). Is). All bits x _outer = [u | p] are interleaved in the interleaver 12 and placed in the polar internal encoder 14 with the freeze bits to form an input to the polar internal encoder 14, which is the entire code. Generate bit x. The interleaver 12 operates based on a predetermined interleaving mapping Φ _K (.), Which depends on the number K of data bits.

FIG. 4 is a block diagram showing a one-step decoder structure of interleaved and concatenated polar codes according to a particular embodiment. At the receiver, the input log-likelihood ratio (LLR) y of the coded bits is first decoded using the modified SCL polar decoder 16, and the output of the modified SCL polar decoder 16 is then decoded. It is passed through the deinterleaver 18 that extracts the data bits. Deinterleaver 18 depends on the interleaving mapping Φ _{K (·)} employed in the encoder 14 in a simple manner. The modified SCL polar decoder behavior, as indicated by the interleaving mapping Φ _K (.), Whenever the external parity bit is reached, its value during the continuous decoding process is the generator matrix _{Go of the} external code. Similar to a regular SCL polar decoder, except that it is calculated based on the previous data bits as indicated by the corresponding column of.

The size of the interleaver described with respect to FIG. 3 generally depends, for example, on the number of data bits K and the number of CRC bits n _CRC . To facilitate implementation, a particular embodiment implements a single template interleaver Φ _T (.) At the largest possible value of K indicated by K _max , followed by K in FIG. Use a subset of this template interleaver to implement the interleaver required for any given value.

FIG. 5 is a block diagram showing a template interleaver of fixed size K _max according to a specific embodiment. The interleaver 30 includes a bit mapper 20, a template interleaver 22, and a bit extractor 24. The bit mapper 20 maps K data bits to some input positions of the template interleaver 22 of size K _max . Bitmapper μ _K (・) depends on K. n _crc CRC bits are mapped to other input positions. The rest of the input position is filled with nulls. The template interleaver 22 rearranges the data bits, the CRC bits, and the nulls. The bit extractor 24 removes nulls from the output of the template interleaver 22 to form the output of the interleaver 30.

によって示されるテンプレートインターリーバの入力は、以下のビットマッピングによって与えられる。

図５および図６は、高インデックスビットマッパの場合のインターリービング動作およびデインターリービング動作を表す。 The design of the template interleaver is tied to the design of the bit mapper. The following are two examples of bit mappers. The high index bit mapper loads K data bits at the high index position of the template interleaver input. Specifically, u = [u ₀ , u ₁ , ... .. .. , U _K-1 ] is a data bit. In that case,

The input of the template interleaver indicated by is given by the following bit mapping.

5 and 6 show the interleaving operation and the deinterleaving operation in the case of the high index bit mapper.

Another example includes a low index bit mapper. The low index bit mapper loads K data bits in the reverse fashion at the low index position of the template interleaver input. In detail, the input of the template interleaver is given by the following bit mapping.

FIG. 6 is a block diagram showing the structure of the deinterleaver according to a specific embodiment. The deinterleaver 40 includes a null filler 26, a template deinterleaver 28, and a bit demapper 32. An exemplary deinterleaver shows the corresponding reverse operation in the deinterleaver of the decoder shown in FIG.

After the polar decoding, the output of the polar decoder is input to the deinterleaver 40. The null filler 26 fills the input with nulls according to the same null positions used in the bit extractor 24 in FIG. The template deinterleaver 40 deinterleaves a null-filled sequence (null-filled sequence).

A portion of the output of the template deinterleaver forms a decoded external (CRC) parity bit, and a portion of the output is passed through a bit demapper 32 that performs the reverse operation of the bit mapping performed in FIG. Is done. The output of the bit demapper 32 is a decoded data bit. If the external code is a CRC code used for error detection, the decoded data bits and the decoded external CRC parity bits are then passed by the CRC to detect if an error has occurred. Used to check if.

Certain embodiments may include one of several wisely designed interleaving patterns for template interleavers from which the corresponding interleaver for each possible number of information bits can be derived. The particular pattern maximizes the potential reduction in decoding latency through earlier termination while maintaining FAR.

Some exemplary interleaving patterns for template interleavers, each associated with the particular bitmapper described above, are described below. In all cases, the following two CRC polynomials are used as examples.
g _crc (D) = D ²⁴ + D ²³ + D ²¹ + D ²⁰ + D ¹⁷ + D ¹⁵ + D ¹³ + D ¹² + D ⁸ + D ⁴ + D ² + D + 1
g _crc (D) = D ¹⁹ + D ¹⁶ + D ¹⁴ + D ¹³ + D ¹² + D ¹⁰ + D ⁸ + D ⁷ + D ⁴ + D ³ + 1

Since the template interleaver Φ _T (.) Is an integer-to-integer mapping, the template interleaver Φ _T (.) Can be equivalently explained using the integer sequence indicated by Φ _T. The index corresponding to the CRC bit is underlined.

２．Ｋ_ｍａｘ＝５３についての低インデックスビットマッパの場合

３．Ｋ_ｍａｘ＝７２についての高インデックスビットマッパの場合

４．Ｋ_ｍａｘ＝７２についての低インデックスビットマッパの場合

５．Ｋ_ｍａｘ＝１４０についての高インデックスビットマッパの場合

６．Ｋ_ｍａｘ＝１４０についての低インデックスビットマッパの場合

７．Ｋ_ｍａｘ＝１６０についての高インデックスビットマッパの場合

８．Ｋ_ｍａｘ＝１６０についての低インデックスビットマッパの場合

９．Ｋ_ｍａｘ＝２００についての高インデックスビットマッパの場合

１０．Ｋ_ｍａｘ＝２００についての低インデックスビットマッパの場合

As an _example, the value of _{K max,} in order to generate the following interleaving pattern is a value that may be used in the 5G-NR system, in the set {53,72,140,160,200} It is assumed that there is.
1. 1. For high index bit mappers for K _max = 53

2. 2. For low index bit mappers for K _max = 53

3. 3. For high index bit mappers for K _max = 72

4. For low index bit mappers for K _max = 72

5. For high index bit mappers for K _max = 140

6. For low index bit mappers for K _max = 140

7. For high index bit mappers for K _max = 160

8. For low index bit mappers for K _max = 160

9. For high index bit mappers for K _max = 200

10. For low index bit mappers for K _max = 200

Certain embodiments include some of the following features and benefits: In certain embodiments, CRC checking can be done bit by bit for each individual CRC bit. This is in contrast to the existing method in which the entire CRC bit length K _CRC vector is used in CRC checking. Bit-by-bit CRC checking finds that the decoded value of any of the CRC bits does not match the decoded value of the information bit on which the CRC bit depends for all candidate paths in the list. If so, it allows the decoder to terminate the decoding process earlier. CRC checking can be performed during SCL decoding. This is in contrast to existing methods of performing CRC checking only after the end of SCL decoding.

In certain embodiments, the decoder in the receiver with the early termination feature can be performed using distributed CRC bits. In some embodiments, the distributed CRC bit does not carry the mask. When the decoder has reached the dispersion CRC bits p _i, the decoder, the decoding process is carried out below to determine whether it should be terminated early.

Step 1: The decoder has each list l, l = 0,1,. .. .. , One for L-1, calculates variance CRC bits _{p i} of L estimates _p i a (l).
Step 2: For each p _{i (l),} the decoder, info bits associated with the p i _(l) it is checked whether occurring normal parity check.
Step 3: If the parity check is not successful for each p _{i (l),} the decoding process ends, it is possible to distribute the "decoding failure" message as a decoder output. If the parity check (s) for one or more of _pi (l) is successful, the decoding process continues normally.

In another embodiment, the dispersion CRC bits, the mask (i.e., dispersion CRC bits _{q i)} conveying the _{will w i = (p i + q} i) mod2. When the decoder has reached the bit locations of a distributed CRC bits p _i, the decoder, the decoding process is carried out below to determine whether it should be terminated early.

Step 1: The decoder has each list l, l = 0,1,. .. .. , One for L-1, calculates variance CRC bits _{p i} of L estimates _w i and (l).
Step 2: For each _w i (l), the decoder removes the mask _{p i = (w i + q} i) mod2.
Step 3: For each p _{i (l),} the decoder, info bits associated with the p i _(l) it is checked whether occurring normal parity check.
Step 4: If the parity check is not successful for each p _{i (l),} the decoding process ends, it is possible to distribute the "decoding failure" message as a decoder output. If the parity check (s) for one or more of _pi (l) is successful, the decoding process continues normally.

FIG. 7 is a flow diagram illustrating an exemplary method in a wireless transmitter according to a particular embodiment. In certain embodiments, one or more steps of FIG. 7 may be performed by the network node 120 or wireless device 110 of the network 100 described with respect to FIG.

The method begins in step 712, where the radio transmitter carries the data bits u using a linear external code to generate a set of external parity bits p with the data bits u of length K. Encode a set of information. For example, network node 120 may encode a set of external parity bits and data bits (eg, using a CRC) according to any of the embodiments and examples described above with respect to FIGS. 3-6.

In step 714, the radio transmitter is capable of operating to disperse some bits of the previous set of parity bits p of some data bits u, depending on the number of data bits K. The interleaving mapping function is used to interleave the set of external parity bits p with the data bits u. For example, the network node 120 interleaves a set of external parity bits p with a data bit u using any of the embodiments and examples described above with respect to FIGS. 3-6.

In step 716, the radio transmitter uses a polar encoder to generate a set of encoded bits x to encode the interleaved bits. For example, the network node 120 may encode the interleaved bits according to any of the embodiments and examples described above with respect to FIGS. 3-6.

In step 718, the radio transmitter may transmit a set of coded bits x to the radio receiver. For example, the network node 120 transmits a set of coded bits x to the wireless device 110.

Changes, additions, or omissions may be made to the method 700 of FIG. In addition, one or more steps in the method of FIG. 7 can be performed in parallel or in any suitable order. The steps can be repeated over time as needed.

FIG. 8 is a flow chart showing an exemplary method in a wireless receiver according to a specific embodiment. In certain embodiments, one or more steps in FIG. 8 may be performed by the network node 120 or wireless device 110 of the network 100 described with respect to FIG.

The method begins at step 812, where the radio receiver, when decoding the received set of polar coded bits, determines that the decoder has reached the dispersion CRC bits p _i. For example, the wireless device 110 may decode a set of polar encoded bits according to any of the deinterleaving embodiments or examples described above, such as sequential erase list (SCL) decoding.

In step 814, the wireless receivers are listed in each list l, l = 0,1,. .. .. , One for L-1, calculates variance CRC bits _{p i} of L estimates _p i a (l). For example, the wireless device 110 may estimate a list of values for the parity bits.

In 814, for each p _{i (l),} radio receivers, info bits associated with the p i _(l) to determine whether lead to normal parity check. For example, the wireless device 110 uses a list of values for the parity bits to determine if the data bits were received correctly.
If the decoding is unsuccessful, the method proceeds to step 816, where the wireless receiver ends the decoding. If the decoding is successful, the method proceeds to step 818, where the wireless receiver continues decoding.

Changes, additions, or omissions may be made to method 800 of FIG. In addition, one or more steps in the method of FIG. 8 can be performed in parallel or in any suitable order. The steps can be repeated over time as needed.

FIG. 9A is a block diagram showing an exemplary embodiment of a wireless device. The wireless device is an example of the wireless device 110 shown in FIG. In certain embodiments, the wireless device is capable of encoding and decoding transmissions using CRC interleaving patterns for polar codes.

Specific examples of wireless devices include mobile phones, smartphones, PDAs (Personal Digital Assistants), portable computers (eg laptops, tablets), sensors, modems, machine-to-machine (M2M) devices, Includes laptop-embedded devices (LEEs), laptop-mounted devices (LMEs), USB dongle, device-to-device compatible devices, inter-vehicle devices, or any other device that can provide wireless communication. The wireless device includes a transceiver 1310, a processing circuit element 1320, a memory 1330, and a power supply 1340. In some embodiments, the transceiver 1310 allows the radio signal to be transmitted to the radio network node 120 (eg, via an antenna) and to receive the radio signal from the radio network node 120, a processing circuit element. The 1320 executes instructions to provide some or all of the functionality described herein as provided by the wireless device, and the memory 1330 stores the instructions executed by the processing circuit element 1320. The power supply 1340 powers one or more of the components of the wireless device 110, such as the transceiver 1310, the processing circuit elements 1320, and / or the memory 1330.

The processing circuit element 1320 is hardware implemented in one or more integrated circuits or modules for executing instructions and manipulating data to perform some or all of the described functions of the wireless device. Includes any suitable combination of and software. In some embodiments, the processing circuit element 1320 is, for example, one or more computers, one or more programmable logic devices, one or more central processing units (CPUs), or one or more microprocessors. It may include one or more applications, and / or other logics, and / or any suitable combination described above. The processing circuit element 1320 may include analog and / or digital circuit elements that are configured to perform some or all of the described functions of the wireless device 110. For example, the processing circuit element 1320 may include resistors, capacitors, inductors, transistors, diodes, and / or any other suitable circuit component.

Memory 1330 is generally capable of operating to store computer executable code and data. Examples of memory 1330 include computer memory (eg, random access memory (RAM) or read-only memory (ROM)), mass storage medium (eg, hard disk), removable storage medium (eg, compact disk (CD)) or digital video. Includes discs (DVDs)), and / or any other volatile or non-volatile, non-transient computer-readable and / or computer-executable memory device that stores information.

The power supply 1340 can generally operate to power the components of the wireless device 110. The power supply 1340 can be any suitable type of battery, such as lithium ion, lithium air, lithium polymer, nickel cadmium, nickel metal hydride, or any other suitable type of battery for powering wireless devices. Can include.

Other embodiments of the wireless device are any of the functionality described above and / or any additional functionality (including any functionality required to support the solution described above). It may include additional components (other than the components shown in FIG. 9A) that are responsible for providing some aspects of the functionality of the wireless device, including.

FIG. 9B is a block diagram showing exemplary components of the wireless device 110. The components may include an encoding / decoding module 1350, a transmitting module 1352, and a receiving module 1354.

The coding / decoding module 1350 may perform the coding and decoding functions of the wireless device 110. For example, the coding / decoding module 1350 may encode and decode a set of bits according to any of the CRC interleaving examples and embodiments described above. In some embodiments, the coding / decoding module 1350 may only perform coding, only decoding, or both coding and decoding. In some embodiments, the coding / decoding module 1350 may include processing circuit elements 1320 or may be included in processing circuit elements 1320. In certain embodiments, the encoding / decoding module 1350 may communicate with the transmitting module 1352 and the receiving module 1354.

The transmission module 1352 may perform the transmission function of the wireless device 110. For example, transmission module 1352 may transmit a coded set of bits to network node 120. In some embodiments, the transmit module 1352 comprises or may be included in the processing circuit element 1320. In certain embodiments, the transmit module 1352 may communicate with the scheduling module 1350 and the receive module 1354.

The receiving module 1354 may perform the receiving function of the wireless device 110. For example, the receiving module 1354 may receive a coded set of bits from the network node 120. In some embodiments, the receiving module 1354 may include processing circuit elements 1320 or may be included in processing circuit elements 1320. In certain embodiments, the transmit module 1352 may communicate with the scheduling module 1350 and the transmit module 1352.

FIG. 10A is a block diagram showing an exemplary embodiment of a network node. The network node is an example of the network node 120 shown in FIG. In certain embodiments, the network node is capable of encoding and decoding transmissions using a CRC interleaving pattern for polar code.

Network node 120 includes e-node B, node B, gNB, base station, radio access point (eg Wi-Fi access point), low power node, base transceiver station (BTS), transmission point or node, remote RF unit ( It can be an RRU), a remote radio head (RRH), or another radio access node. The network node includes at least one transceiver 1410, at least one processing circuit element 1420, at least one memory 1430, and at least one network interface 1440. Transceiver 1410 allows the radio signal to be transmitted to a radio device such as the radio device 110 (eg, via an antenna) and to receive the radio signal from the radio device such as the radio device 110, the processing circuit element 1420. Executes instructions to give some or all of the functionality described above as given by the network node 120, memory 1430 stores the instructions executed by the processing circuit element 1420 and is a network interface. The 1440 communicates signals to back-end network components such as gateways, switches, routers, the Internet, public switched telephone networks (PSTNs), controllers, and / or other network nodes 120. The processing circuit element 1420 and memory 1430 may be of the same type as described for the processing circuit element 1320 and memory 1330 of FIG. 9A above.

In some embodiments, the network interface 1440 is communicably coupled to the processing circuit element 1420 to receive an input for the network node 120, send an output from the network node 120, or input or output or a combination thereof. Refers to any suitable device capable of performing both suitable processes, communicating with another device, or operating to perform any combination described above. The network interface 1440 includes suitable hardware (eg, ports, modems, network interface cards, etc.) and software including protocol conversion and data processing capabilities to communicate over the network.

FIG. 10B is a block diagram showing exemplary components of the network node 120. The components may include an encoding / decoding module 1450, a transmitting module 1452, and a receiving module 1454.

The coding / decoding module 1450 may perform the coding and decoding functions of the network node 120. For example, the coding / decoding module 1450 may encode and decode a set of bits according to any of the CRC interleaving examples and embodiments described above. In some embodiments, the coding / decoding module 1450 may only perform coding, may only decode, or may perform both coding and decoding. In some embodiments, the encoding / decoding module 1450 may include processing circuit elements 1420 or may be included in processing circuit elements 1420. In certain embodiments, the encoding / decoding module 1450 may communicate with the transmitting module 1452 and the receiving module 1454.

The transmission module 1452 may perform the transmission function of the network node 120. For example, transmission module 1452 may transmit a coded set of bits to wireless device 110. In some embodiments, the transmit module 1452 comprises or may be included in the processing circuit element 1420. In certain embodiments, the transmitting module 1452 may communicate with the encoding / decoding module 1450 and the receiving module 1454.

The receiving module 1454 may perform the receiving function of the network node 120. For example, the receiving module 1454 may receive a coded set of bits from the wireless device 110. In some embodiments, the receiving module 1454 may include processing circuit elements 1420 or may be included in processing circuit elements 1420. In certain embodiments, the transmit module 1452 may communicate with the encoding / decoding module 1450 and the transmit module 1452.

Modifications, additions, or omissions may be made to the systems and devices disclosed herein without departing from the scope of the invention. System and equipment components can be integrated or separated. Moreover, the operation of the system and equipment may be performed by more, fewer, or other components. In addition, system and device operation can be performed using any suitable logic, including software, hardware, and / or other logic. As used herein, "each" refers to each member of a set or each member of a subset of a set.

Changes, additions, or omissions may be made to the methods disclosed herein without departing from the scope of the invention. The method may include more, fewer, or other steps. In addition, the steps can be performed in any suitable order.

Although the present disclosure has been described for some embodiments, modifications and substitutions of the embodiments will be apparent to those skilled in the art. Therefore, the above description of embodiments does not constrain the present disclosure. Other modifications, substitutions, and modifications are possible without departing from the spirit and scope of the present disclosure as defined by the following claims.

The abbreviations used in the above description include:
3GPP 3rd Generation Partnership Project BBU Baseband Unit BTS Base Transceiver Station CC Component Carrier CRC Patrol Redundancy Check CQI Channel Quality Information CSI Channel Status Information D2D Device to Device DCI Downlink Control Information DFT Discrete Fourier Transform DMRS Demodulation Reference Signal eNB enode B
FDD Frequency Division Duplex FFT Fast Fourier Transform gNB Next Generation Node B
LAA License Assisted Access LBT Listen Before Talk LDPC Low Density Parity Check LTE Long Term Evolution
LTE-U LTE in unlicensed spectrum
M2M Machine-to-Machine MCS Modulation Coding Method MIB Master Information Block MIMO Multi-Input Multi-Output MTC Machine Communication NR New Radio OFDM Orthogonal Frequency Division Multiplexed PCM Parity Check Matrix PRB Physical Resource Block RAN Radio Access Network RAN Radio Access Technology RBS Radio Base Station RNC radio network controller RRC radio resource control RRH remote radio head RRU remote radio unit SCell secondary cell SI system information SIB system information block TB transport block TBS transport block size TDD time-division duplex TTI transmission time interval UE user equipment UL up Link UTRAN Universal Terrestrial Radio Access Network WAN Radio Access Network

Claims (38)

A method of operating a wireless transmitter in a wireless communication network, wherein the method is:
Encoding the set of information carrying the data bits u with a linear external code to generate a set of external parity bits p with a data bit u of length K.
Using a given interleaving mapping function that depends on the number K of data bits and is capable of operating to disperse some of the set of parity bits p before some data bits u. Interleaving the set of external parity bits p and the data bits u,
A method comprising encoding the interleaved bits using a polar encoder to generate a set of encoded bits x. The method of claim 1, further comprising transmitting the set of coded bits x to a wireless receiver. The predetermined interleaving mapping function includes a template interleaver for the maximum value of K called K _max, and the template interleaver includes a high index bit mapper.
The K data bits are loaded at the high index position of the input of the template interleaver, where u = [u ₀ , u ₁ , ... .. .. , U _K-1 ]

The input of the template interleaver indicated by is given by the following bit mapping:

The method according to claim 1 or 2. The predetermined interleaving mapping function includes a template interleaver for the maximum value of K called K _max, and the template interleaver includes a low index bit mapper.
The K data bits are loaded in reverse at the low index position of the input of the template interleaver, where u = [u ₀ , u ₁ , ... .. .. , U _K-1 ]

The input of the template interleaver indicated by is given by the following bit mapping:

The method according to claim 1 or 2. K _max is 53, use the template interleavers, underlined index corresponding to the cyclic redundancy check (CRC) bits is pulled, the interleaving pattern comprising one of the following interleaving pattern To do,

The method according to claim 3. K _max is 53, use the template interleavers, underlined index corresponding to the cyclic redundancy check (CRC) bits is pulled, the interleaving pattern comprising one of the following interleaving pattern To do,

The method according to claim 4. K _max is 72, use the template interleavers, underlined index corresponding to the cyclic redundancy check (CRC) bits is pulled, the interleaving pattern comprising one of the following interleaving pattern To do,

The method according to claim 3. K _max is 72, use the template interleavers, underlined index corresponding to the cyclic redundancy check (CRC) bits is pulled, the interleaving pattern comprising one of the following interleaving pattern To do,

The method according to claim 4. K _max is 140, use the template interleavers, underlined index corresponding to the cyclic redundancy check (CRC) bits is pulled, the interleaving pattern comprising one of the following interleaving pattern To do,

The method according to claim 3. K _max is 140, use the template interleavers, underlined index corresponding to the cyclic redundancy check (CRC) bits is pulled, the interleaving pattern comprising one of the following interleaving pattern To do,

The method according to claim 4. K _max is 160, use the template interleavers, underlined index corresponding to the cyclic redundancy check (CRC) bits is pulled, the interleaving pattern comprising one of the following interleaving pattern To do,

The method according to claim 3. K _max is 160, use the template interleavers, underlined index corresponding to the cyclic redundancy check (CRC) bits is pulled, the interleaving pattern comprising one of the following interleaving pattern To do,

The method according to claim 4. K _max is 200, use the template interleavers, underlined index corresponding to the cyclic redundancy check (CRC) bits is pulled, the interleaving pattern comprising one of the following interleaving pattern To do,

The method according to claim 3. K _max is 200, use the template interleavers, underlined index corresponding to the cyclic redundancy check (CRC) bits is pulled, the interleaving pattern comprising one of the following interleaving pattern To do,

The method according to claim 4. The method according to any one of claims 1 to 10, wherein the wireless transmitter includes a wireless device or a network node. A wireless transmitter (110, 120) including a processing circuit element (1320, 1420), wherein the processing circuit element is
In order to generate a set of external parity bits p together with a data bit u of length K, a linear external code is used to encode the set of information carrying the data bits u.
Using a given interleaving mapping function that depends on the number K of data bits and is capable of operating to distribute some of the set of parity bits p before some data bits u. Interleaving the set of external parity bits p and the data bits u,
A radio transmitter (110, 120) capable of using a polar encoder to generate a set of coded bits x to encode the interleaved bits. 16. The wireless transmitter according to claim 16, wherein the processing circuit element can further operate to transmit the set of coded bits x to a wireless receiver (110, 120). The predetermined interleaving mapping function includes a template interleaver for the maximum value of K called K _max, and the template interleaver includes a high index bit mapper.
The K data bits are loaded at the high index position of the input of the template interleaver, where u = [u ₀ , u ₁ , ... .. .. , U _K-1 ]

The input of the template interleaver indicated by is given by the following bit mapping:

The wireless transmitter according to claim 16 or 17. The predetermined interleaving mapping function includes a template interleaver for the maximum value of K called K _max, and the template interleaver includes a low index bit mapper.
The K data bits are loaded in reverse at the low index position of the input of the template interleaver, where u = [u ₀ , u ₁ , ... .. .. , U _K-1 ]

The input of the template interleaver indicated by is given by the following bit mapping:

The wireless transmitter according to claim 16 or 17. The wireless transmitter according to claim 18, wherein the _Kmax is 53, and the template interleaver uses an interleaving pattern including any one of the interleaving patterns according to claim 5. The wireless transmitter according to claim 19, wherein the _Kmax is 53, and the template interleaver uses an interleaving pattern including any one of the interleaving patterns according to claim 6. The wireless transmitter according to claim 18, wherein K _max is 72, and the template interleaver uses an interleaving pattern including any one of the interleaving patterns according to claim 7. The wireless transmitter according to claim 19, wherein K _max is 72, and the template interleaver uses an interleaving pattern including any one of the interleaving patterns according to claim 8. The wireless transmitter according to claim 18, wherein the _Kmax is 140, and the template interleaver uses an interleaving pattern including any one of the interleaving patterns according to claim 9. The wireless transmitter according to claim 19, wherein K _max is 140, and the template interleaver uses an interleaving pattern including any one of the interleaving patterns according to claim 10. The wireless transmitter according to claim 18, wherein the _Kmax is 160, and the template interleaver uses an interleaving pattern including any one of the interleaving patterns according to claim 11. The wireless transmitter according to claim 19, wherein K _max is 160, and the template interleaver uses an interleaving pattern including any one of the interleaving patterns according to claim 12. The wireless transmitter according to claim 18, wherein the _Kmax is 200, and the template interleaver uses an interleaving pattern including any one of the interleaving patterns according to claim 13. The wireless transmitter according to claim 19, wherein the _Kmax is 200, and the template interleaver uses an interleaving pattern including any one of the interleaving patterns according to claim 14. The wireless transmitter according to any one of claims 16 to 29, wherein the wireless transmitter includes a wireless device or a network node. A method of operating a wireless receiver in a wireless communication network, wherein the method is:
When decoding a received set of polar coded bits, and determining a decoder reaches distributed CRC bits p _i,
Each list l, l = 0,1,. .. .. , One for L-1, and calculating the dispersion CRC bits _{p i} of L estimates _p i (l),
For each p _{i (l),} and determining whether the info bits leading to normal parity check relating to p i _(l),
Upon determining that there is no normal parity check for each p _{i (l),} and to terminate the decoding,
A method comprising continuing the decoding if it is determined that a normal parity check exists. 31. The method of claim 31, wherein the decoding comprises template deinterleaving using an interleaving pattern that includes any one of the interleaving patterns of any one of claims 5-14. 31 or 32. The method of claim 31 or 32, wherein the wireless receiver comprises a wireless device or network node. A wireless receiver (110, 120) including a processing circuit element (1320, 1420), wherein the processing circuit element is
When decoding a received set of polar coded bits, and determining a decoder reaches distributed CRC bits p _i,
Each list l, l = 0,1,. .. .. , One for L-1, and calculating the dispersion CRC bits _{p i} of L estimates _p i (l),
For each p _{i (l),} and determining whether the info bits leading to normal parity check relating to p i _(l),
Upon determining that there is no normal parity check for each p _{i (l),} and to terminate the decoding,
Radio receivers (110, 120) that are capable of operating to continue the decoding if it determines that a normal parity check exists. The processing circuit element can operate to perform decoding by template deinterleaving using an interleaving pattern that includes any one of the interleaving patterns according to any one of claims 5-14. The wireless receiver according to claim 34. 34. The method of claim 34 or 35, wherein the wireless receiver comprises a wireless device or network node. Radio transmitters (110, 120) with coding modules (1350, 1450).
The coding module
Encoding the set of information carrying the data bits u with a linear external code to generate a set of external parity bits p with a data bit u of length K.
Using a given interleaving mapping function that depends on the number K of data bits and is capable of operating to disperse some of the set of parity bits p before some data bits u. Interleaving the set of external parity bits p and the data bits u,
A radio transmitter (110, 120) capable of using a polar encoder to generate a set of coded bits x to encode the interleaved bits. A wireless receiver (110, 120) equipped with a decoding module (1350, 1450).
The decoding module
When decoding a received set of polar coded bits, and determining a decoder reaches distributed CRC bits p _i,
Each list l, l = 0,1,. .. .. , One for L-1, and calculating the dispersion CRC bits _{p i} of L estimates _p i (l),
For each p _{i (l),} and determining whether the info bits leading to normal parity check relating to p i _(l),
Upon determining that there is no normal parity check for each p _{i (l),} and to terminate the decoding,
Radio receivers (110, 120) that are capable of operating to continue the decoding if it determines that a normal parity check exists.

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