JP2020526948A - Multi-stage doherty power amplifier and transmitter - Google Patents

Abstract

A multi-stage Dougherty power amplifier and transmitter are provided, and the multi-stage Dougherty power amplifier is a general-purpose carrier amplifier (201) which is a nested 2-way inverting Doherty sub-amplifier and a nested single-ended sub-amplifier or a nested single-ended sub-amplifier connected to the general-purpose carrier amplifier (201). A general-purpose peaking amplifier (202), which is a nested 2-way normal Dougherty sub-amplifier, is included, and a general-purpose carrier amplifier (201) and a general-purpose peaking amplifier (202) are arranged in a general-purpose 2-way inverting Doherty power amplifier format. In the multi-stage Doherty power amplifier, the signal power probability distribution function (PDF) adapted for cost-effective multi-stage Doherty PA design is applied, and the 2-way normal and inverted Doherty PA cells are multi-stage Doherty PA with gain expansion effect. Used as a basic unit for building.
[Selection diagram] Fig. 2

Description

Embodiments of the present disclosure relate generally to the field of communications, and more specifically to multistage Dougherty power amplifiers and transmitters.

Advanced digital modulation schemes are used in cellular base stations of 4th generation (4G) and later mobile communication systems for high spectral efficiency. Radio frequency (RF) signals exhibit a large peak-to-average power ratio (PAPR), which is amplified in the power amplifier (PA). Therefore, the instantaneous transmission power changes dramatically in amplitude. Therefore, traditional RF PAs have the disadvantage of fairly low average efficiency for high PAPR stimulation.

One way to increase the efficiency of RF PA is to use a Doherty power amplifier (Dougherty PA). The classic Dougherty PA, or the normal Dougherty PA in the present disclosure, is used to improve efficiency for high PAPR signals, thereby making it far away from peak output power during backoff at 6 dB. The efficiency peak point of 2 is created. However, with the ever-increasing PAPR, a major challenge for Doherty PA is the limited Doherty region to maintain high efficiency when the PAPR is greater than 6 dB.

This section introduces aspects that can facilitate a better understanding of the present disclosure. Therefore, the statements in this section should be read in this regard and should not be understood as approvals for what is or is not prior art.

The inventor found that Dougherty's concept was extended to multi-stage (ie, three or more stages) variants. This makes it possible to maintain high efficiency over a wider range of output power levels for varying amplitude distributions. On the other hand, the average efficiency can be increased for a particular amplitude distribution and a particular power level.

However, two problems associated with multi-stage Dougherty PA have been identified: low efficiency problems when amplifiers (transistors) with limited gain are used, and poor linearity problems. The low efficiency is caused by excessive drive power dissipation to ensure high linearity in the driver stage, which is required when the conventional multi-stage Dougherty PA implementation is used. This problem is especially noticeable when the power amplifier in Dougherty PA has a low gain. Insufficient linearity is due to the fact that in traditional multi-stage Dougherty PAs, some of the amplifiers (all but the two top-level power amplifiers) saturate at some transition points and exceed these transition points. Caused by being required to remain saturated.

To solve at least some of the above problems, multi-stage Dougherty PAs and transmitters are provided in this disclosure. It can be appreciated that the embodiments of the present disclosure are not limited to multi-input, multi-output (MIMO) transmitter systems and may be applied more broadly to any application scenario in which similar problems exist.

Various embodiments of the present disclosure are primarily intended to provide multi-stage Doherty PAs and transmitters, for example in MIMO transmitter systems. The transmitter can be, for example, a terminal device or a network device. Also, other features and advantages of the embodiments of the present disclosure will be understood from the following description of the particular embodiment, when read with the accompanying drawings exemplifying the principles of the embodiments of the present disclosure, for example.

In general, embodiments of the present disclosure provide the concept of a nested multi-stage Dougherty PA to overcome the problems pointed out in the above description.

In the first aspect, a multi-stage Dougherty power amplifier is provided. The multi-stage Doherty power amplifier includes a general purpose carrier amplifier which is a nested 2-way inverting Doherty sub-amplifier and a general-purpose peaking amplifier which is a nested single-ended sub-amplifier or a nested 2-way normal Doherty sub-amplifier connected to the general-purpose carrier amplifier. The amplifier and the general-purpose peaking amplifier are arranged in the general-purpose 2-way inverting Doherty power amplifier format.

In one embodiment, the general purpose carrier amplifier includes a subcarrier amplifier and a first subpeaking amplifier connected to the subcarrier amplifier, the subcarrier amplifier being of the first semiconductor feature and the first. The sub-peaking amplifier is characterized by a second semiconductor having a harmonic termination, and the amplifier efficiency of the first sub-peaking amplifier is higher than that of the sub-carrier amplifier.

In one embodiment, the general purpose peaking amplifier includes a second sub-peaking amplifier, and the second sub-peaking amplifier is of the first semiconductor feature.

In one implementation of this embodiment, the bias voltage values of the subcarrier amplifier and the second subpeaking amplifier are positive, and the bias voltage value of the first subpeaking amplifier is negative.

In one embodiment of this embodiment, the power ratio between the subcarrier amplifier, the first subpeaking amplifier, and the second subpeaking amplifier is the applied high peak to average power ratio (PAPR) signal. It is determined according to the power distribution function (PDF).

In one implementation of this embodiment, the first semiconductor feature is LDMOS and the second semiconductor feature is GaN HEMT.

In one embodiment of this embodiment, the power gain of the first subpeaking amplifier is greater than the power gain of the subcarrier amplifier for power gain expansion, and the power gain of the subcarrier amplifier is compressed to a predetermined compression level. , The power gain of the first peaking amplifier is not compressed.

In one implementation of this embodiment, the characteristics of the power gain extension are inverse characteristics to the driver amplifier, such as performing predistortion to the driver amplifiers that are lined up or cascaded to the multistage Doherty power amplifier.

In another embodiment, the general purpose peaking amplifier comprises a plurality of sub-peaking amplifiers, the last-stage sub-peaking amplifier being the first semiconductor feature, and other stages of sub-peaking amplifiers except the last-stage sub-peaking amplifier. However, it is a feature of the second semiconductor, and the amplifier efficiency of the sub-peaking amplifiers of the other stages except the last-stage sub-peaking amplifier is higher than the amplifier efficiency of the last-stage sub-peaking amplifier.

In one implementation of this embodiment, the bias voltage values of the subcarrier amplifier and the last stage subpeaking amplifier are positive, and the first subpeaking amplifier and the subpeaking amplifiers of the other stages except the last stage subpeaking amplifier. The bias voltage value is negative.

In one embodiment of this embodiment, the power ratio between the subcarrier amplifier, the first subpeaking amplifier, and the plurality of subpeaking amplifiers is the power of the applied high peak to average power ratio (PAPR) signal. Determined according to the distribution function (PDF).

In one implementation of this embodiment, the first semiconductor feature is LDMOS and the second semiconductor feature is GaN HEMT.

In one embodiment of this embodiment, the power gain of the sub-peaking amplifiers of the other stages except the last-stage sub-peaking amplifier is higher than the power gain of the first sub-peaking amplifier for power gain expansion, and the last-stage sub The power gain of the sub-peaking amplifier in each stage of the sub-peaking amplifier in the other stages except the peaking amplifier is higher than the power gain of the sub-peaking amplifier in the previous stage for power gain expansion, and the power gain of the sub-carrier amplifier is predetermined. It is compressed to the compression level of, and the power gain of the sub-peaking amplifiers of other stages except the last-stage sub-peaking amplifier is not compressed.

In one implementation of this embodiment, the characteristics of the power gain extension are the opposite of the driver amplifier, such as performing pre-distortion to the driver amplifiers that are lined up or cascaded to the multi-stage Doherty power amplifier.

In one implementation of this embodiment, the general purpose peaking amplifier comprises three sub-peaking amplifiers for forming a four-stage Dougherty power amplifier.

In the second aspect, a transmitter is provided. The transmitter includes a signal processor configured to perform signal processing on baseband input signals of a plurality of channels and a multi-stage Doherty power amplifier as described in the first aspect.

In the third aspect, the device is provided. The device includes a processor, a memory, and a transmitter, the memory including a program containing instructions that can be executed by the processor, and the transmitter is as described in the second aspect.

In one embodiment, the device is a terminal device.

In another embodiment, the device is a network device.

According to various embodiments of the present disclosure, a signal power probability distribution function (PDF) adapted for cost-effective multi-stage Dougherty PA design is applied and the 2-way normal and inverted Dougherty PA cells have a gain-enhancing effect. It is used as a basic unit for constructing a multi-stage Dougherty PA with.

According to the various embodiments of the present disclosure, the Dougherty output power backoff range is partitioned for different designs. Different semiconductor process-based transistors are used simultaneously for different partitioned output power backoff ranges. Transistors based on different semiconductor processes are designed separately for different demands for power, efficiency and cost.

According to various embodiments of the present disclosure, a gain expansion effect is used to compensate for the non-linearity of the driver amplifier. Therefore, the overall lineup efficiency is improved.

The above and other aspects, features, and benefits of the various embodiments of the present disclosure, by way of example, refer to the accompanying drawings in which similar reference numbers or letters are used to specify similar or equivalent elements. However, it will be more fully clarified from the embodiments for carrying out the following inventions. The drawings are illustrated to facilitate a better understanding of the embodiments of the present disclosure and are not necessarily drawn to a constant scale.

It is the schematic of the cell of the wireless communication network. It is a block diagram of the multi-stage Doherty PA of this disclosure. It is a block diagram of the three-stage Dougherty PA of the present disclosure. It is a block diagram of the four-stage Dougherty PA of the present disclosure. It is a figure which shows the general-purpose three-stage Dougherty PA in this disclosure for "stepwise" handling of the divided Dougherty operating area. It is a figure which shows the general-purpose four-stage Dougherty PA in this disclosure for "stepwise" handling of a divided Dougherty operating area. FIG. 6 is a flow chart showing how PDF analysis should be used to obtain the Dougherty design parameters in the present disclosure. It is a figure of the "stepwise" division of the Dougherty movement area in this disclosure. FIG. 5 is a diagram of an input bias scheme in the present disclosure compared to an LDMOS and GaN-only solution. It is a figure of the analog predistortion system in this disclosure. FIG. 6 is a block diagram of a lineup setting (a) for an existing solution and a lineup setting (b) for a pre-distorted lineup in the present disclosure with higher driver stages and lineup efficiency. It is the schematic of the technical implementation form of this disclosure as a 4-stage Dougherty PA. It is a figure of supply current vs. output power in this disclosure. It is a figure of PAE and gain vs. output power and gain extension effect observation in this disclosure. It is a figure of the gain expansion effect observation in RF output power vs. RF input power in this disclosure. It is a figure of the transmitter of this disclosure. It is a simplified block diagram of the apparatus by one Embodiment of this disclosure.

The present disclosure will then be described with reference to some exemplary embodiments. It is understood that these embodiments do not imply limitations to the scope of the present disclosure, but are discussed only for the purpose of allowing those skilled in the art to better understand and therefore implement the present disclosure. I want to.

As used herein, the term "wireless communication network" is subject to any suitable communication standard, such as LTE Advanced (LTE-A), LTE, Broadband Code Division Multiple Access (WCDMA), High Speed Packet Access (HSPA). Refers to the network. Further, communication between the terminal device and the network device in the wireless communication network is not limited, but is limited to the first generation (1G) communication protocol, the second generation (2G) communication protocol, the 2.5G communication protocol, and 2.75G. Any suitable generation of communication protocols, including communication protocols, 3rd generation (3G) communication protocols, 4th generation (4G) communication protocols, 4.5G communication protocols, future 5th generation (5G) communication protocols, and / Or can be implemented according to any other protocol that is currently known or will be developed in the future.

The term "network device" refers to a device in a wireless communication network in which a terminal device accesses the wireless communication network through the device and receives services from the wireless communication network. Network device refers to a base station (BS), access point (AP), server, controller or any other suitable device in a wireless communication network. The BS can be, for example, a node B (node B or NB), an evolved node B (e-node B or eNB), a g-node B (gNB), a low power node such as a relay, a femto, or a pico.

Further examples of network devices include MSR radio equipment such as multi-standard radio (MSR) BS, base transceiver stations (BTS), transmission points, transmission nodes. However, more generally, a network device can allow and / or provide terminal device access to a wireless communication network, or provide some service to a terminal device that has accessed the wireless communication network, so. It may represent any suitable device (or group of devices) that is configured, configured, and / or capable of operating.

The term "terminal device" refers to any end device that can access and receive services from a wireless communication network. By way of example, but not limited to, a terminal device refers to a mobile terminal, a user device (UE), or other suitable device. The UE can be, for example, a subscriber station (SS), a portable subscriber station, a mobile station (MS), or an access terminal (AT). Terminal devices are, but not limited to, portable computers, image capture terminal devices such as digital cameras, gaming terminal devices, music storage and playback devices, mobile phones, cellular phones, smartphones, tablets, wearable devices, personal digital assistants (PDAs). , Vehicles, etc. may be included.

The terminal device may support device-to-device (D2D) communication, for example by implementing a 3GPP standard for side-link communication, in which case it may be referred to as a D2D communication device.

As yet another specific example, in the Internet of Things (IoT) scenario, a terminal device performs monitoring and / or measurements, and the results of such monitoring and / or measurements are displayed on another terminal device and / or network device. Can represent a machine or other device to send to. The terminal device can be a machine to machine (M2M) device in this case, and the M2M device is sometimes referred to as a machine to machine communication (MTC) device in the 3GPP context.

As one particular example, the terminal device can be a UE that implements the 3GPP narrowband mono Internet of Things (NB-IoT) standard. Specific examples of such machines or devices are sensors, weighing devices such as wattmeters, industrial machinery, or household or personal appliances such as personal wearable computing such as refrigerators, televisions, watches. Devices and so on. In other scenarios, the terminal device may represent a vehicle or other device, and the vehicle or other device may monitor its operating status and / or report on its operating status, or be associated with its operation. Other functions are possible.

As used herein, the terms "first" and "second" refer to different elements. The singular forms "a" and "an" shall also include the plural form, unless the context specifically indicates. As used herein, "comprises," "comprising," "has," "having," "includes," and / or "includes." The term "inclusion" specifies the presence of the described features, elements, and / or components, but the presence or combination of one or more other features, elements, components and / or combinations thereof. Do not rule out additions. The term "based on" should be read as "at least partially based on." The terms "one embodied" and "an embodied" should be read as "at least one embodiment". The term "another embodiment" should be read as "at least one other embodiment". Other explicit and implicit provisions may be included below.

Next, with reference to the drawings, some exemplary embodiments of the present disclosure will be described below. First, a reference is made to FIG. 1, which shows a schematic diagram of the wireless communication network 100. FIG. 1 shows a network device 101 and a terminal device 102 in the wireless communication network 100. In the example of FIG. 1, the network device 101 serves for the terminal device 102.

It should be understood that the settings in FIG. 1 are provided for illustrative purposes only, without suggesting any limitations regarding the scope of the present disclosure. Those skilled in the art will appreciate that the wireless communication network 100 may include any suitable number of terminal and / or network devices and may have other suitable settings.

For convenience, the following embodiments are given by taking a MIMO system as an example, but the embodiments are not limited to MIMO systems, and any system related to a multi-channel power amplifier, such as a satellite system, is all present. It is feasible in disclosure.

The present disclosure is proposed to solve at least one of the problems described in the context of the invention, namely the problem of low efficiency and the problem of poor linearity. Embodiments of the present disclosure are described below with reference to the accompanying drawings and specific embodiments.

First Embodiment In this embodiment, a multi-stage Dougherty power amplifier is provided. Multi-stage Dougherty power amplifiers are implemented in transmitters, such as multi-antenna transmitters in terminal devices or network devices.

FIG. 2 shows a block diagram of the multi-stage Dougherty power amplifier 200 of the present disclosure. As shown in FIG. 2, the multi-stage Dougherty power amplifier 200 may include a general purpose carrier amplifier 201 and a general purpose peaking amplifier 202. The general purpose carrier amplifier 201 is a nested 2-way inverting doherty sub-amplifier, and the general-purpose peaking amplifier 202 is a nested single-ended sub-amplifier or a nested 2-way normal doherty sub-amplifier. In this embodiment, the general purpose carrier amplifier 201 and the general purpose peaking amplifier 202 are arranged in the general purpose 2-way inverting Doherty power amplifier format, so that the multistage Doherty power amplifier 200 is in the general purpose inverting Doherty topology. With this arrangement, smart bias schemes, analog pre-distortion, and gradual Dougherty operation divisions can be realized as described below.

In this embodiment, the multi-stage Dougherty PA 200 includes a plurality of nested sub-amplifier cells for general purpose carrier amplification and general purpose peaking amplification, respectively. Thus, the multi-stage Doherty PA 200 is a nested Doherty PA with a global inverted Doherty setting, but with an inverted Doherty for the carrier sub-amplifier and a normal Doherty for the peaking sub-amplifier, respectively.

In this embodiment, the multi-stage Dougherty PA includes a unit amplifier as a two-way Dougherty amplifier cell. For general purpose carrier amplifiers, the doherty cell has an inverting structure. For general purpose peaking amplifiers, the Doherty cell is usually in a Doherty structure. The global structure is inverted Dougherty PA.

In this embodiment, the multiple nested sub-amplifiers of the multi-stage Doherty PA are not uniformly designed and are dedicated to a special output power backoff range based on the power distribution function (PDF) of the high PAPR signal. Therefore, some of the sub-amplifiers have different semiconductor process and design metrics. In this embodiment, the central cell along the Doherty region should be prioritized for efficiency and the side cell should be preferred for linearity, cost or high power level. For example, the side cell can be formed by using the LDMOS semiconductor process and the center cell can be formed by using the GaN HEMT semiconductor process.

In this embodiment, the power ratio is defined by the PDF, i.e. the power ratio between the sub-amplifiers is determined according to the PDF of the applied high PAPR signal, and thus the power of the sub-amplifier is applied to the high PAPR signal. Can be adapted to PDF. The higher the PDF, the higher the efficiency of the transistor should be used.

In one implementation, the general purpose carrier amplifier 201 includes a subcarrier amplifier and a first subpeaking amplifier, and the general purpose peaking amplifier 202 includes at least one subpeaking amplifier.

In this implementation, the subcarrier amplifier is of the first semiconductor feature, i.e., designed by using the first semiconductor process, and the first subpeaking amplifier is of the second semiconductor feature. That is, the amplifier efficiency of the first subpeaking amplifier is higher than that of the subcarrier amplifier, which is designed by using a second semiconductor process having a harmonic termination for efficiency improvement.

As an example, the general purpose peaking amplifier 202 includes a second sub-peaking amplifier, the second sub-peaking amplifier is of the first semiconductor feature, i.e., designed by using the first semiconductor process. To.

In this example, the amplifier efficiency of the central cell, i.e. the first sub-peaking amplifier of the general purpose carrier amplifier 201, is the side cell, i.e. the subcarrier amplifier of the general purpose carrier amplifier 201 and the second sub-peaking amplifier of the general purpose peaking amplifier 202. Higher than amplifier efficiency.

FIG. 3 shows a three-stage Dougherty PA300, and as shown in FIG. 3, in the three-stage Dougherty PA300, a subcarrier amplifier (C) and a first subpeaking amplifier (P1) construct an inverting Doherty subamplifier. It is implemented in a nested fashion so that it does. This inverting Doherty sub-amplifier can be used as a general-purpose carrier amplifier from the viewpoint of the second peaking amplifier (P2). The general-purpose carrier amplifier and the second peaking amplifier (P2) form another inverting Doherty, that is, a multi-stage Doherty power amplifier 200. Further, the first sub-peaking amplifier (P1) uses a high-efficiency semiconductor process having a harmonic termination for improving efficiency, such as GaN HEMT, and the sub-carrier amplifier (C) and the second peaking amplifier (P2). Uses an intermediate efficiency semiconductor process with lower cost, such as LDMOS.

As another example, the general purpose peaking amplifier 202 includes a plurality of sub-peaking amplifiers, the last stage sub-peaking amplifier is of the first semiconductor feature, i.e. designed by using the first semiconductor process. The sub-peaking amplifiers of the other stages, except the last-stage sub-peaking amplifier, are of the second semiconductor feature, i.e., designed by using the second semiconductor process, as described above. The amplifier efficiency of the sub-peaking amplifiers of the other stages except the last-stage sub-peaking amplifier is higher than the amplifier efficiency of the last-stage sub-peaking amplifier.

In this example, the amplifier efficiency of the central cell, i.e., the first sub-peaking amplifier of the general-purpose carrier amplifier 201 and the sub-peaking amplifiers of the other stages except the last-stage sub-peaking amplifier of the general-purpose peaking amplifier 202, is the side cell, that is, the side cell. It is higher than the amplifier efficiency of the subcarrier amplifier of the general-purpose carrier amplifier 201 and the final stage sub-peaking amplifier of the general-purpose peaking amplifier 202.

FIG. 4 shows a four-stage Dougherty PA400, and as shown in FIG. 4, the four-stage Dougherty PA400 is an inverted Doherty sub formed by a subcarrier amplifier (C) and a first subpeaking amplifier (P1). The amplifier can function as the general purpose carrier amplifier 201, and the normal Dougherty sub-amplifier formed by the second sub-peaking amplifier (P2) and the third sub-peaking amplifier (P3) functions as the general-purpose peaking amplifier 202. It is implemented in a nested fashion so that it can be done. The entire Doherty PA400 is in an inverted Doherty topology formed by general purpose sub-amplifier cells. Moreover, the central cell, i.e., the first sub-peaking amplifier (P1) and the second sub-peaking amplifier (P2), uses a high efficiency semiconductor process with harmonic termination to improve efficiency, such as GaN HEMT. However, the side cells, i.e., the subcarrier amplifier (C) and the third subpeaking amplifier (P3), use a less costly intermediate efficiency semiconductor process such as LDMOS.

By utilizing the topologies shown in FIGS. 3-4, some advanced features can be achieved in this embodiment. In detail, theoretical peak efficiency points are not always or uniformly distributed. In this embodiment, the peak efficiency points take the weight given by the PDF of the applied high PAPR signal. Peak efficiency points are prioritized and shaped by the probability of power distribution. Therefore, the PA design is more flexible to adapt to different signal characteristics. For example, FIGS. 5 and 6 show efficiency vs. output power backoff in the three-stage Doherty PA embodiment and the four-stage Doherty PA embodiment of the present disclosure, respectively, compared to the high PAPR signal PDF plot.

In FIG. 5, as shown in (a), existing solutions do not prioritize amplifier design parameters for different regions of Dougherty operation and are allocated in some low power probability areas. Efficiency and power are as high as high power probability areas. As shown in (b), in the present disclosure, the Dougherty region is divided into three, and the central peaking efficiency point uses a high efficiency PA (P1) having a harmonic termination to prioritize efficiency. .. Also, the side peaking efficiency point is only in the low power probability area. Therefore, side-peaking efficiency points can be treated with a lower priority for efficiency, which can help reduce costs.

In FIG. 6, as shown in (a), the four peaking efficiency points in the existing solution are treated or designed uniformly in the semiconductor process and design method, eg, four peaking efficiencies. The point-corresponding amplifiers are all made from GaN HEMTs, without considering the PDF of the applied high PAPR signal, thus reducing resource utilization and requiring more stages. As shown in (b), in the present disclosure, the design parameters are output powers at different low (L), intermediate (M) and high (H) levels according to the PDF profile of the applied high PAPR signal. , Gain, efficiency, linearity, and differentially selected.

In this embodiment, the design parameters for the multi-stage Doherty PA can be obtained from the PDF of the applied high PAPR signal, as shown in FIG.

For the method shown in FIG. 7, the efficiency vs. output power backoff can be divided into three regions to form a "gradual" shape mask for the Dougherty PA design. FIG. 8 shows three stages: stage 1, which sacrifices efficiency for gain and / or power and / or linearity, stage 2, which sacrifices others for efficiency, and efficiency for power. Shows step 3 at the expense of, which prioritizes different design parameters of Dougherty PA to obtain more efficient resource utilization and provides a cost-effective solution for multi-Dougherty PA design. Can bring.

In this embodiment, as shown in FIG. 8, the efficiency vs. output power backoff curve is "stepwise" by adopting different techniques, design methods, and the like. Therefore, transistors with different semiconductor characteristics are used according to the PDF of the applied high PAPR signal, providing a cost effective solution for high power amplifiers.

In this embodiment, the side cells are designed by using an intermediate efficiency semiconductor process such as LDMOS and the central cell (s) are designed by using a high efficiency semiconductor process such as GaN HEMT. Therefore, the bias voltage value of the side cell is positive, and the bias voltage value of the center cell (one or more) is negative. Therefore, the present disclosure provides a more reasonable input bias scheme as compared to existing solutions based on a single technology process. FIG. 9 shows an existing solution that cites a four-stage Doherty PA as an example and an input bias (base / gate) scheme for LDMOS and GaN HEMTs in the present disclosure (including LDMOS and GaN HEMTs).

The arrangement shown in FIG. 9 for LDMOS or GaN HEMTs can affect the first turned-on sub-amplifier (“carrier” shown in FIG. 9) in a multi-stage Dougherty PA. Provides high efficiency during low power mode. The peaking amplifiers (“Peak 1”, “Peak 2” and “Peak 3” shown in FIG. 9) can be completely shut down by applying a negative input bias. However, some PACCs (Power Amplifier Control Circuits) are unable to provide optimal negative bias due to limitations, which is the final peaking amplifier of the multistage Doherty PA (the "peak" shown in FIG. 9). 3 ”) makes it difficult to be biased in the optimum state.

In comparison, the present disclosure arranges the input bias polarity in an interleaved fashion, which uses a positive input bias for the carrier amplifier (the "carrier" shown in FIG. 9) and an intermediate peaking amplifier. ("Peak 1", "Peak 2" and "Peak 3" shown in FIG. 9) are biased with a negative input bias and the last peaking amplifier ("Peak 3" shown in FIG. 9) , Returns to positive or approaches 0 as an input bias.

With this arrangement, both positive and negative input biases can be used in a single multi-stage Dougherty PA design, which greatly extends the input bias range. The extended input bias range no longer monotonously decreases and returns to 0, which only requires a limited bias voltage range for multi-stage Dougherty PA design and has a suitable active load modulation effect. Simplify the design for. Therefore, the difficulty of the gate bias method due to the use of a uniform semiconductor process can be alleviated, and the multi-stage Doherty bias method can be realized in a simpler manner.

In this embodiment, the present disclosure provides a driver stage amplifier and an analog predistortion scheme that boosts the lineup PAE (power addition efficiency). It is a power gain extension. In the power gain expansion, the power gain of the latter sub-amplifier is larger than the power gain of the former sub-amplifier excluding the last-stage sub-amplifier.

Taking the 3-stage Doherty PA as an example, the power gain of the first sub-peaking amplifier is larger than the power gain of the sub-carrier amplifier for power gain expansion, and the power gain of the sub-carrier amplifier is compressed to a predetermined compression level. And the power gain of the first peaking amplifier is not compressed.

Taking a multi-stage Doherty PA other than the three stages as an example, the power gain of the sub-peaking amplifiers of the other stages except the last-stage sub-peaking amplifier is higher than the power gain of the first sub-peaking amplifier for power gain expansion. , The power gain of the sub-peaking amplifier of each stage of the sub-peaking amplifier of the other stages except the last stage sub-peaking amplifier is higher than the power gain of the previous stage for power gain expansion, and the power gain of the sub-carrier amplifier is predetermined. It is compressed to the compression level of, and the power gain of the sub-peaking amplifiers of other stages except the last-stage sub-peaking amplifier is not compressed. In the case of 4-stage Dougherty PA, the power gain of the first sub-peaking amplifier is larger than the power gain of the carrier sub-amplifier, and the power gain of the second sub-peaking amplifier is larger than the power gain of the first sub-peaking amplifier. large.

In this embodiment, the gain expansion characteristic is such that the power gain compression of the driver amplifier connected in line or cascade to the multi-stage Doherty power amplifier can be compensated, i.e., predistortion to the driver amplifier is performed. , The opposite characteristic to the driver amplifier.

FIG. 10 shows the analog predistortion method in the present disclosure. As shown in FIG. 10, by manipulating multiple stages in Dougherty PA, gain expansion effects can be obtained by using different semiconductor processes and design parameters in the final stage amplifier in the present disclosure. As is known, the gain compression effect is better seen with PA. In order to compensate for the gain compression performed in the driver amplifier stage, the inverse characteristics of the gain compression may be used in the series arrangement of the driver stage amplifier and the final stage amplifier (multi-stage Doherty PA in the present disclosure). In general, the driver stage amplifier will not be saturated too strongly so that acceptable linearity can be obtained in order to leave a design margin for the final stage amplifier in the lineup configuration. The main drawback of existing solutions is that the efficiency of the driver amplifier is extremely low because the driver amplifier is far from the saturation region. Since the driver amplifier efficiency contribution is essential for the lineup configuration, therefore, the placement of the driver stage amplifier in the existing solution will limit the lineup efficiency improvement.

In the present disclosure, a suitable gain expansion effect is provided in the final stage amplifier, which can be used to compensate for the compression effect that occurs in the driver amplifier, as shown in FIG. This allows the driver amplifier to draw more power under a small compression area, which will greatly help improve driver and lineup efficiency. This can be completed by using the sub-amplifier design in the present disclosure, as shown in FIG.

As shown in FIG. 11, a new line-up pre-distortion method using gain expansion of the final stage amplifier (multi-stage Dougherty PA) is provided. As previously described in the present disclosure, the gain expansion of the final stage multi-stage Doherty PA compensates for the gain compression characteristics of the driver stage PA. This compensation results in an increase in 3 dB compression point (P3 dB) levels throughout the lineup amplifier. The effect of increasing P3dB on overall linearity can be obtained.

In FIG. 11, (a) is a lineup setting for an existing solution built using a linear driver stage amplifier and a final stage amplifier. In FIG. 11, (b) is a gain expansion and proposed structure of the final stage amplifier over the same final stage amplifier as in FIG. 11 (a). As can be seen from FIG. 11 (b), the present disclosure can compensate for the AM-AM characteristics of the lineup shown in FIG. Compared with existing solutions, the gain characteristics of the proposed lineup structure show better linearity due to the gain extension that offsets the gain compression of the final stage amplifier. Compared to existing solutions, gain compensation with the final multi-stage Doherty PA improves the adjacent channel power ratio (ACPR) of the pre-distorted lineup. Also, the Complementary Cumulative Distribution Function (CCDF) curve can show how much and how often the signal exceeds the average power. When the power level of the output signal exceeds the P3dB compression point, the CCDF curve begins to clip, indicating that the frequency amplified signal is compressed. The CCDF results of the pre-distorted line-up amplifier are less clipped compared to existing solutions.

The concepts of the present disclosure have been validated by Keysight's Advanced Design System (ADS) simulation, and as an example of validation, FIG. 12 shows an exemplary 4-stage Dougherty design.

In FIG. 12, the general purpose multi-stage Doherty PA 1200 is a 2-way composite inverting Doherty PA including two sub-Dougherty amplifiers 1201 and 1202. The first sub-dougherty amplifier 1201 is a 2-way inverting doherty PA, and the second sub-dougherty amplifier 1202 is a 2-way normal doherty PA. Both are combined together using the appropriate sequence to be turned on. The carrier amplifier and peak 3 amplifier 12021 are implemented in the LDMOS process due to the cost and high power capability of the transistor. Peak 2 and Peak 1 amplifiers are implemented in a GaN HEMT process for high efficiency for the highest PDF with 2nd and 3rd harmonic terminations. There are three hybrid couplers (shown as hybrid 90 in FIG. 12) used to distribute the input power to different paths. Offset lines are used to perform phase matching on the input side of the design. FIG. 13 shows a turning on sequence by observing the amplifier supply current of each sub-amplifier.

FIG. 14 shows the power addition efficiency and transducer gain vs. output power of the 4-stage Doherty PA. The efficiency curve is no longer smooth, but is shaped according to the signal distribution histogram of the applied high PAPR signal. It is characterized as being optimized for the power probability distribution. Also, the gain expansion effect caused by the transition from the LDMOS carrier amplifier to the GaN HEMT peak 2 peaking amplifier can be observed. It is used to linearize the driver amplifier so that the driver amplifier stage can operate to saturation to provide much higher lineup efficiency.

FIG. 15 shows an RF output power vs. RF input power transfer function plot. The gain expansion effect created will be better understood using the curve shown in FIG.

In order to clarify and better understand the advantages of the present disclosure, both the problems existing in the existing solution and the advantages of the present disclosure are described below with reference to the drawings.

As shown in FIG. 8, the conventional Dougherty PA design is optimized for constant high efficiency over a wide backoff range without selectivity. This strategy can cause some waste, especially for very low power probability ranges. However, the present disclosure prioritizes Doherty PA design parameters according to the PDF of the applied high PAPR signal and optimizes those parameters, which can provide better trade-offs in parameter and resource utilization.

Moreover, existing solutions do not consider the PDF roll-off characteristics of the applied composite signal. Traditionally, only peak-to-average power ratio (PAPR) points are considered for Dougherty PA design. Therefore, the details of the PDF of the signal are ignored and, for example, the skew of the PDF of the signal is not taken into account. Therefore, the design parameters were not optimized for the PDF of the signal.

Moreover, in existing solutions, the semiconductor process is the same for all Dougherty-designed sub-amplifiers by ignoring the PDF of the signal. Therefore, cost and performance may not be optimized to maximum profit. However, the present disclosure shows the semiconductor process required for the PDF of the applied signal, and the choice of transistor may be more flexible for a cost effective solution. Based on the PDF profile of the applied signal, a hybrid mode Dougherty PA design can be realized.

In addition, existing solutions have very limited tuning parameters / degrees for Dougherty PA designs. This is because there is no room for segmented optimization for different output power backoff ranges for the Dougherty PA design. However, in the present disclosure, the design can be range-specific for different output power backoff ranges. Different processes and parameters can be introduced, which increases the performance Doherty PA design with explicit targets, i.e. more tuning parameters / degree for signal PDF oriented PA design.

Finally, in the lineup configuration, the driver amplifier used in the existing solution must operate in a very linear region, avoiding more distortion generated from the final stage, which is much more. Limit driver efficiency. In comparison, a gain-enhancing effect can be produced in the present disclosure, which means that the driver amplifier operates in a small saturation region to obtain higher driver efficiency and therefore to improve lineup efficiency. Make it possible.

Second Embodiment of the Embodiment In this embodiment, the transmitter is provided, and the same contents as those in the first embodiment are omitted.

FIG. 16 shows a diagram of transmitter 1600, which, as shown in FIG. 16, includes a signal processor 1601, a driver amplifier 1602, and a multi-stage Doherty power amplifier 1603.

Existing solutions may be referenced for the signal processor 1601 and driver amplifier 1602, and embodiment 1 may be referenced for the multi-stage Dougherty power amplifier, which is described in detail in Embodiment 1 and thus herein. Will not be explained any further.

Third Embodiments In these embodiments, the device is provided.

FIG. 17 shows a simplified block diagram of the apparatus 1700 according to an embodiment of the present disclosure. It will be appreciated that device 1700 may be implemented, for example, as at least a part of a network device or terminal device, and in particular, for example, as at least a part of a transmitter or transceiver contained within the network device or terminal device. ..

As shown in FIG. 17, device 1700 includes communication means 1730 and processing means 1750. The processing means 1750 includes a data processor (DP) 1710 and a memory (MEM) 1720 coupled to the DP 1710. The communication means 1730 is coupled to the DP1710 in the processing means 1750. The MEM1720 stores a program (PROG) 1740. The communication means 1730 is for communication with other devices, which can be implemented as a transceiver for transmitting / receiving signals.

In some embodiments in which the device 1700 acts as a network device, the processing means 1750 may be configured to perform signal processing on the input signal and acquire the output signal, and the communication means 1730 may transmit the output signal. , Or may be configured to receive an output signal transmitted by the terminal device. In some other embodiments in which device 1700 acts as a terminal device, processing means 1750 may be configured to perform signal processing on an input signal and acquire an output signal, and communication means 1730 may transmit the output signal. Or can be configured to receive output signals transmitted by network devices.

PROG1740 is assumed to include program instructions that allow device 1700 to operate in accordance with embodiments of the present disclosure when performed by the associated DP1710. Embodiments herein can be implemented by computer software run by DP1710 of device 1700, by hardware, or by a combination of software and hardware. The combination of the data processor 1710 and the MEM1720 can form processing means 1750 adapted to implement the various embodiments of the present disclosure.

The MEM1720 can be of any type suitable for the local technology environment, and non-limiting examples include any semiconductor-based memory device, magnetic memory device and system, optical memory device and system, fixed memory and removable memory. It can be implemented using suitable data storage techniques. Although only one MEM is shown in device 1700, there may be several physically separate memory modules in device 1700. The DP1710 can be of any type suitable for the local technical environment and, as a non-limiting example, among general computers, dedicated computers, microprocessors, digital signal processors (DSPs) and processors based on a multi-core processor architecture. Can include one or more of. The apparatus 1700 may have a plurality of processors, such as application-specific integrated circuit chips, which are temporally slaved to a clock that synchronizes the main processor.

A device (such as a terminal device or network device (not shown)) is provided in one embodiment, wherein the device includes device 1700 and the same content as in the first and second aspects of the embodiment is omitted. To.

The embodiments of the present invention described herein are multi with one or more conventional processors and some non-processor circuits, as described herein, having a reduced crest factor. It will be appreciated that it may consist of specific stored program instructions that control one or more processors to implement some, most, or all of the functions that generate carrier communication signals. Non-processor circuits may include, but are not limited to, wireless transmitters, signal drivers, clock circuits, power supply circuits, and user input devices. Therefore, these functions can be interpreted as a block of methods for producing a signal with a reduced crest factor. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions, or each function, or some combination of some of the functions, implemented as custom logic. Alternatively, it can be implemented in multiple application specific integrated circuits (ASICs). In addition, one of ordinary skill in the art is disclosed herein, for example, despite significant effort and numerous design choices motivated by available time, current technology, and economic considerations. Guided by these concepts and principles, it is expected that it will be readily possible to generate such software instructions and programs as well as integrated circuits (ICs) with minimal experimentation.

For example, one or more of the examples described herein may be implemented in a field programmable gate array (FPGA), which generally includes an array of programmable tiles. These programmable tiles include, for example, input / output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay locks. It can include a loop (DLL) and the like.

Each programmable tile generally contains both programmable interconnects and programmable logic. Programmable interconnects generally include a large number of varying length interconnect lines interconnected by programmable interconnect points (PIPs). Programmable logic implements user-designed logic using programmable elements, which can include, for example, function generators, registers, arithmetic logic, and so on.

Programmable interconnects and programmable logic are generally programmed by loading a stream of configuration data into internally configured memory cells that define how programmable elements are configured. The configuration data can be read from memory (eg, from an external PROM) or written to the FPGA by an external device. In that case, the overall state of the individual memory cells determines the function of the FPGA.

In general, the various embodiments of the present disclosure may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. Some embodiments may be implemented in hardware and others may be implemented in firmware or software that may be executed by a controller, microprocessor or another computing device. Various aspects of the embodiments of the present disclosure are illustrated and illustrated as block diagrams, as flowcharts, or using some other schematic representation, the blocks, devices, systems, techniques described herein. Or it will be appreciated that the method can be implemented, as a non-limiting example, in hardware, software, firmware, dedicated circuits or logic, general purpose hardware or controllers or other computing devices, or any combination thereof.

As an example, embodiments of the present disclosure can be described in the general context of machine executable instructions, such as instructions contained within a program module, executed on a device on a target real or virtual processor. In general, a program module includes routines, programs, libraries, objects, classes, components, data structures, etc. that perform a particular task or implement a particular abstract data type. The functionality of the program modules can be combined or divided between the program modules as needed in various embodiments. Machine-executable instructions for program modules can be executed within local or distributed devices. In distributed devices, program modules can be on both local and remote storage media.

Program code for performing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes are general purpose computers, dedicated computers, or other programmable data processing so that when the program code is executed by a processor or controller, it implements the functions / operations specified in the flowchart and / or block diagram. It may be provided to the processor or controller of the device. The program code may be executed entirely on the machine, as a stand-alone software package, partially on the machine, partially on the machine and partially on the remote machine, or entirely on the remote machine or server.

The above program code is on a machine-readable medium, which may be any tangible medium containing or memorizing a program for use by an instruction execution system, an instruction execution device, or an instruction execution device, or a program related thereto. Can be embodied in. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or devices, or any suitable combination of the above.

More specific examples of machine-readable storage media are electrical connections with one or more wires, portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory. It will include (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

In the context of the present disclosure, the device may be implemented in the general context of computer system executable instructions, such as program modules, executed by the computer system. In general, a program module can include routines, programs, objects, components, logic, data structures, etc. that perform a particular task or implement a particular abstract data type. The device can be performed in a distributed cloud computing environment where tasks are performed by remote processing devices linked through communication networks. In a distributed cloud computing environment, program modules can be on both local computer system storage media and remote computer system storage media, including memory storage devices.

In addition, the actions are shown in a particular order, which means that such actions are performed in the particular order or sequence shown, or all, in order to achieve the desired result. It should not be understood as requiring that the illustrated actions be performed. In some situations, multitasking and parallelism can be advantageous. Similarly, some specific implementation details are included in the discussion above, but these should not be construed as limitations to the scope of the present disclosure, but rather may be specific to a particular embodiment. It should be interpreted as a description of the features. Some features described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may be implemented separately in multiple embodiments, or in any suitable subcombination.

Although this disclosure has been described in a language specific to structural features and / or methodological acts, the disclosure as defined in the appended claims does not necessarily refer to the particular features or acts described above. Please understand that it is not always limited. Rather, the particular features and actions described above are disclosed as exemplary forms of implementing the claims.

Claims (20)

A general-purpose carrier amplifier (201), which is a nested 2-way inverting Doherty sub-amplifier,
A multi-stage Doherty power amplifier (200) comprising a nested single-ended sub-amplifier or a general-purpose peaking amplifier (202) which is a nested 2-way normal Doherty sub-amplifier connected to the general-purpose carrier amplifier (201).
A multi-stage Dougherty power amplifier (200) in which the general-purpose carrier amplifier (201) and the general-purpose peaking amplifier (202) are arranged in the form of a 2-way inverting Dougherty power amplifier. The multi-stage Dougherty power amplifier according to claim 1, wherein the general-purpose carrier amplifier (201) includes a subcarrier amplifier and a first subpeaking amplifier connected to the subcarrier amplifier. The multi-stage Doherty power amplifier according to claim 2, wherein the subcarrier amplifier has a first semiconductor feature, and the first subpeaking amplifier has a second semiconductor feature having a harmonic termination. .. The multi-stage Dougherty power amplifier according to claim 3, wherein the amplifier efficiency of the first sub-peaking amplifier is higher than the amplifier efficiency of the sub-carrier amplifier. The multi-stage Doherty power amplifier according to claim 4, wherein the general-purpose peaking amplifier (202) includes a second sub-peaking amplifier, and the second sub-peaking amplifier is characterized by the first semiconductor. The multi-stage Doherty power amplifier according to claim 5, wherein the bias voltage values of the subcarrier amplifier and the second subpeaking amplifier are positive, and the bias voltage values of the first subpeaking amplifier are negative. The power ratio between the subcarrier amplifier, the first subpeaking amplifier, and the second subpeaking amplifier is the power distribution function (PDF) of the applied high peak to average power ratio (PAPR) signal. The multi-stage Doherty power amplifier according to claim 5, which is determined according to. The multi-stage Doherty power amplifier according to claim 5, wherein the first semiconductor feature is LDMOS and the second semiconductor feature is GaN HEMT. The power gain of the first sub-peaking amplifier is larger than the power gain of the sub-carrier amplifier for power gain expansion, the power gain of the sub-carrier amplifier is compressed to a predetermined compression level, and the first The multi-stage Doherty power amplifier according to claim 3, wherein the power gain of the peaking amplifier is not compressed. The ninth aspect of the present invention, wherein the power gain expansion characteristic is an inverse characteristic to the driver amplifier so as to perform predistortion to the driver amplifier connected to the multi-stage Doherty power amplifier in a line-up or cascade. Multi-stage Doherty power amplifier. The general-purpose peaking amplifier (202) includes a plurality of sub-peaking amplifiers, the last-stage sub-peaking amplifier is the first semiconductor feature, and the sub-peaking amplifiers of other stages other than the last-stage sub-peaking amplifier are 4. The second semiconductor feature, wherein the amplifier efficiency of the sub-peaking amplifiers of the other stages excluding the last-stage sub-peaking amplifier is higher than the amplifier efficiency of the last-stage sub-peaking amplifier. Multi-stage Doherty power amplifier. The bias voltage values of the subcarrier amplifier and the last stage subpeaking amplifier are positive, and the bias voltage values of the first subpeaking amplifier and the subpeaking amplifiers of the other stages excluding the last stage subpeaking amplifier are The multi-stage Doherty power amplifier according to claim 11, which is negative. The power ratio between the subcarrier amplifier, the first subpeaking amplifier, and the plurality of subpeaking amplifiers is according to the power distribution function (PDF) of the applied high peak to average power ratio (PAPR) signal. The multi-stage Doherty power amplifier according to claim 11, which is determined. The multi-stage Doherty power amplifier according to claim 11, wherein the first semiconductor feature is LDMOS and the second semiconductor feature is GaN HEMT. The power gain of the sub-peaking amplifiers of the other stages excluding the last-stage sub-peaking amplifier is higher than the power gain of the first sub-peaking amplifier for power gain expansion, and the other stages excluding the last-stage sub-peaking amplifier. The power gain of the sub-peaking amplifier in each stage of the sub-peaking amplifier in the first stage is higher than the power gain of the previous stage for power gain expansion, and the power gain of the sub-carrier amplifier is compressed to a predetermined compression level. The multi-stage Doherty power amplifier according to claim 11, wherein the power gain of the sub-peaking amplifiers of the other stages other than the last-stage sub-peaking amplifier is not compressed. 15. The characteristic of the power gain extension is the inverse characteristic of the driver amplifier so as to perform pre-distortion to the driver amplifier connected in line or cascade to the multi-stage Dougherty power amplifier. Multi-stage Doherty power amplifier. The multi-stage Doherty power amplifier according to claim 11, wherein the general-purpose peaking amplifier (202) includes three sub-peaking amplifiers for forming a four-stage Doherty power amplifier. With a signal processor configured to perform signal processing on the baseband input signals of multiple channels,
A transmitter comprising the multi-stage Dougherty power amplifier according to any one of claims 1 to 17. With the processor (1710)
A memory (1720) containing a program (1740) containing instructions that can be executed by the processor (1710).
A device comprising the transmitter according to claim 18. 19. The device of claim 19, wherein the device is a terminal device or a network device.

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