JP2020205662A - Insulated dc/dc converter, ac/dc converter, power adapter, and electric device - Google Patents

Abstract

To realize a self-recovery even if communication abnormality occurs.SOLUTION: In an insulated DC/DC converter configured to obtain a secondary voltage from a primary voltage by switching and driving of a switching transistor connected to a primary winding of a power transformer, a secondary control circuit generates an original PWM signal (SPWM2) for the switching transistor on the basis of the secondary voltage and supplies a transmitting signal (TP2) based on the original PWM signal to a secondary winding of a communication transformer. A primary control circuit generates a received signal (RP1) on the basis of a voltage generated in a primary winding of a communication transformer and performs ON/OFF control of the switching transistor on the basis of a restoration PWM signal (SPWM1) based on the received signal. When the original PWM signal and the restoration PWM signal are mismatched, the matching therebetween is recovered by supplying a correction signal (TP2_C) to the secondary winding of the communication transformer.SELECTED DRAWING: Figure 11

Description

The present invention relates to an isolated DC / DC converter, an AC / DC converter, a power adapter, and an electric device.

In the first type isolated DC / DC converter, the feedback signal corresponding to the secondary side voltage is transmitted to the primary side using a photocoupler or the like, and the primary side control circuit is connected to the primary side winding of the power transistor. By controlling the switching of the switching transistor according to the feedback signal, the secondary voltage is stabilized (see Patent Document 1 below).

Japanese Unexamined Patent Publication No. 2006-197688

In another type of isolated DC / DC converter, the switching transistor on the primary side is controlled by the secondary side control circuit provided on the secondary side. That is, for example, in the secondary side control circuit, a switching control signal (switching control signal for the switching transistor on the primary side) for matching the secondary side voltage with a desired target voltage is generated and generated based on the secondary side voltage. A pulse signal based on the switching control signal is transmitted to the primary side via a communication transformer. In the primary side control circuit, the switching control signal generated by the secondary side control circuit can be restored based on the received pulse signal, and the switching transistor on the primary side can be turned on / off based on the restored switching control signal.

The third type of isolated DC / DC converter is a DC / DC converter that performs synchronous rectification, and a switching control signal is generated on the primary side control circuit side, and a switching transistor on the primary side is generated based on the switching control signal. Is turned on / off, and a pulse signal based on the switching control signal is transmitted to the secondary side via a communication transformer. In the secondary side control circuit, the switching control signal generated by the primary side control circuit can be restored based on the received pulse signal, and the on / off timing of the secondary side synchronous rectifier transistor is controlled based on the restored switching control signal. it can.

In the second type of isolated DC / DC converter, a communication abnormality may occur due to the influence of noise or the like. That is, for example, a pulse signal based on noise, which is not based on the pulse signal from the secondary side control circuit, may be received by the primary side control circuit. In that case, switching generated by the secondary side control circuit. The control signal and the switching control signal restored by the primary control circuit are different. As a result, a phenomenon occurs in which the switching transistor is turned off in the section where the switching transistor should be turned on or the switching transistor is turned on in the section where the switching transistor should be turned off. This causes an abnormal decrease or an abnormal increase in the secondary voltage.

The same situation applies to the third type isolated DC / DC converter. In the third type isolated DC / DC converter, timing control is performed so that the switching transistor on the primary side and the synchronous rectifying transistor on the secondary side are not turned on at the same time through signal transmission using a communication transformer. If the above communication abnormality occurs, they may be turned on at the same time.

Even if a communication error occurs, it is beneficial if it can self-return to the normal state.

An object of the present invention is to provide an isolated DC / DC converter capable of self-recovering even if a communication abnormality occurs, and an AC / DC converter, a power adapter, and an electric device using the isolated DC / DC converter.

The isolated DC / DC converter according to the present invention is primary by switching the switching transistor connected to the primary winding of the power transformer while insulating the primary side and the secondary side of the power transformer from each other. In an isolated DC / DC converter that generates a secondary side voltage on the secondary side from a primary side voltage on the side, it is arranged on the primary side, a primary side control circuit that drives the switching transistor, and a secondary side. The secondary side control circuit includes a communication transformer that realizes signal transmission from the secondary side control circuit to the primary side control circuit, and the secondary side control circuit is based on the secondary side voltage. It has a control signal generation unit that generates an original switching control signal for the switching transistor, and a secondary side transmission unit that supplies a transmission signal based on the original switching control signal to the secondary winding of the communication transformer. The primary side control circuit has a primary side receiving unit that generates a received signal based on the voltage generated in the primary side winding of the communication transformer, and a restored switching that restores the original switching control signal based on the received signal. The secondary side control circuit includes a restoration unit that generates a control signal and a drive unit that switches the switching transistor based on the restoration switching control signal, and the secondary side control circuit includes the original switching control signal and the restoration switching control signal. When it is determined that the restoration switching control signal is not consistent with the original switching control signal, the correction signal is used for the communication by using the secondary side transmission unit. This is a configuration (first configuration) in which the restored switching control signal is matched with the original switching control signal by supplying it to the secondary winding of the transformer.

In the isolated DC / DC converter according to the first configuration, in the secondary side control circuit, the first section in which the switching transistor should be controlled to be on by the original switching control signal and the switching transistor are in the off state. The second section to be controlled is alternately designated, and in the primary side control circuit, the first section and the second section are alternately designated by the restoration switching control signal, and the drive unit receives the restoration. The switching transistor is turned on in the first section designated by the switching control signal, the switching transistor is turned on in the second section specified by the restored switching control signal, and the secondary side transmitter is used. Transmits the transmission signal to the communication transformer at each of the transition timing from the second section to the first section and the transition timing from the first section to the second section designated by the original switching control signal. When it is determined that the restored switching control signal does not match the original switching control signal, the correction signal is supplied to the secondary winding of the communication transformer. The primary side receiving unit generates the received signal based on the voltage generated in the primary winding of the communication transformer by supplying the transmission signal or the correction signal to the secondary winding of the communication transformer. Then, each time the reception signal is generated by the primary side reception unit, the restoration unit switches the section designated by the restoration switching control signal between the first section and the second section (the restoration unit). The second configuration) may be used.

In the isolated DC / DC converter according to the first or second configuration, a voltage that fluctuates in response to switching of the switching transistor is generated at one terminal of the secondary winding of the power transformer. The matching determination unit has a configuration (third configuration) for determining the consistency between the original switching control signal and the restored switching control signal based on the original switching control signal and the voltage at one of the terminals. There may be.

In the isolated DC / DC converter according to the first or second configuration, the matching determination unit is based on the original switching control signal and the secondary current flowing in the secondary winding of the power transformer. , The configuration (fourth configuration) may be used to determine the consistency between the original switching control signal and the restored switching control signal.

The isolated DC / DC converter according to the present invention is primary by switching the switching transistor connected to the primary winding of the power transformer while insulating the primary side and the secondary side of the power transformer from each other. In an isolated DC / DC converter that generates a secondary side voltage on a secondary side from a primary side voltage on the side, it is arranged on the primary side and is arranged on the primary side and a secondary side to drive the switching transistor. A secondary side control circuit that drives a synchronous rectification transistor connected to the secondary winding of the power transformer, and a communication transformer that realizes signal transmission from the primary side control circuit to the secondary side control circuit. , And the primary side control circuit is a control signal generation unit that generates an original switching control signal for the switching transistor based on a feedback signal corresponding to the secondary side voltage, which performs power conversion by a synchronous rectification method. A drive unit that switches the switching transistor based on the original switching control signal, and a primary side transmission unit that supplies a transmission signal based on the original switching control signal to the primary winding of the communication transformer. The secondary side control circuit restores the secondary side receiving unit that generates a received signal based on the voltage generated in the secondary winding of the communication transformer, and the original switching control signal based on the received signal. A restoration unit that generates a restoration switching control signal and a synchronous rectification drive unit that switches the synchronous rectification transistor based on the restoration switching control signal, and the primary side control circuit includes the original switching control signal and the restoration. It further has a matching determination unit that determines consistency with the switching control signal, and when it is determined that the restored switching control signal does not match the original switching control signal, the correction signal is used by the primary side transmitter. A configuration (fifth configuration) may be used in which the restored switching control signal is matched with the original switching control signal by supplying it to the primary winding of the communication transformer.

In the isolated DC / DC converter according to the fifth configuration, in the primary side control circuit, the first section in which the switching transistor should be controlled to be turned on and the switching transistor are turned off by the original switching control signal. The second section to be controlled is alternately designated, and the drive unit turns on the switching transistor in the first section designated by the original switching control signal, and is designated by the original switching control signal. The switching transistor is turned off in the second section, and in the secondary side control circuit, the first section and the second section are alternately designated by the restoration switching control signal, and the synchronous rectification drive unit The synchronous rectification transistor is turned off in the first section designated by the restoration switching control signal, and the synchronous rectification transistor is turned on in all or a part of the second section specified by the restoration switching control signal. The primary side transmitter is turned on, and the transition timing from the second section to the first section and the transition timing from the first section to the second section specified by the original switching control signal are respectively. When the transmission signal is supplied to the primary winding of the communication transformer and it is determined that the restoration switching control signal does not match the original switching control signal, the correction signal is supplied to the communication transformer. The voltage supplied to the primary winding and the secondary receiving unit supplies the transmission signal or the correction signal to the primary winding of the communication transformer to generate a voltage in the secondary winding of the communication transformer. Based on the above, the reception signal is generated, and each time the reception signal is generated by the secondary reception unit, the restoration unit sets the section designated by the restoration switching control signal as the first section and A configuration for switching between the second sections (sixth configuration) may be used.

In the isolated DC / DC converter according to the fifth or sixth configuration, the matching determination unit performs the original switching control signal and the restoration based on the primary side current flowing through the primary side winding of the power transformer. The configuration (seventh configuration) for determining the consistency with the switching control signal may be used.

The AC / DC converter according to the present invention includes a rectifying circuit that full-wave rectifies an AC voltage, a smoothing capacitor that generates a DC voltage by smoothing the full-wave rectified voltage, and a primary side voltage as the DC voltage. It is a configuration (eighth configuration) including an isolated DC / DC converter according to any one of the first to seventh configurations, which generates a secondary side voltage of direct current as an output voltage.

The power adapter according to the present invention has a configuration including a plug that receives an AC voltage, an AC / DC converter according to the eighth configuration, and a housing that accommodates the AC / DC converter (9th configuration). Is.

The electric device according to the present invention has a configuration (10th configuration) including an AC / DC converter according to the eighth configuration and a load driven based on the output voltage of the AC / DC converter.

According to the present invention, it is possible to provide an isolated DC / DC converter capable of self-recovering even if a communication abnormality occurs, and an AC / DC converter, a power adapter, and an electric device using the isolated DC / DC converter. Become.

It is a figure which shows the whole structure of the AC / DC converter which concerns on 1st Embodiment of this invention. It is a block diagram of the DC / DC converter included in the AC / DC converter according to the 1st Embodiment of this invention. FIG. 5 is a waveform diagram of various signals when synchronous rectification is performed according to the first embodiment of the present invention. It is a figure which shows the flow | flow of the operation of the AC / DC converter which concerns on 1st Embodiment of this invention. It is a partial block diagram of the secondary side control circuit which concerns on 1st Embodiment of this invention. It is a partial block diagram of the primary side control circuit which concerns on 1st Embodiment of this invention. FIG. 5 is a configuration diagram relating to signal transmission from a secondary side control circuit to a primary side control circuit according to the first embodiment of the present invention. It is a figure which shows the relationship between some signals and the state of a switching transistor which concerns on 1st Embodiment of this invention. It is a figure which shows the example of the internal structure of the PWM control unit of FIG. FIG. 5 is a diagram showing the influence of noise on various signals according to the first embodiment of the present invention (assuming that there is no correction by the matching determination unit). FIG. 5 is a diagram showing the influence of noise on various signals according to the first embodiment of the present invention (with correction by the matching determination unit). It is a partial block diagram of the DC / DC converter which concerns on 2nd Embodiment of this invention. It is a partial block diagram of the primary side control circuit which concerns on 2nd Embodiment of this invention. It is a partial block diagram of the secondary side control circuit which concerns on 2nd Embodiment of this invention. FIG. 5 is a configuration diagram relating to signal transmission from a primary side control circuit to a secondary side control circuit according to a second embodiment of the present invention. It is a figure which shows the relationship between some signals and the state of a switching transistor which concerns on 2nd Embodiment of this invention. FIG. 5 is a diagram showing the influence of noise on various signals according to the second embodiment of the present invention (assuming that there is no correction by the matching determination unit). FIG. 5 is a diagram showing the influence of noise on various signals according to the second embodiment of the present invention (with correction by the matching determination unit). It is a figure which shows the structure of the power adapter which concerns on 4th Embodiment of this invention. It is a figure which shows the structure of the electric device which concerns on 4th Embodiment of this invention.

Hereinafter, examples of embodiments of the present invention will be specifically described with reference to the drawings. In each of the referenced figures, the same parts are designated by the same reference numerals, and duplicate explanations regarding the same parts will be omitted in principle. In this specification, for simplification of description, by describing a symbol or a code that refers to an information, a signal, a physical quantity, an element or a part, etc., the information, a signal, a physical quantity, an element or a part corresponding to the symbol or the code is described. Etc. may be omitted or abbreviated. For example, the switching transistor referred to by "M1" described later (see FIG. 2) may be referred to as switching transistor M1 or abbreviated as transistor M1, but they are all the same. Point to.

First, some terms used in the description of the embodiments of the present invention will be described. Level refers to the level of potential, where a high level has a higher potential than a low level for any signal or voltage. For any signal or voltage, a signal or voltage at a high level means that the signal or voltage level is at a high level, and a signal or voltage at a low level means that the signal or voltage level is at a low level. Means that it is in. The level for a signal is sometimes referred to as the signal level, and the level for voltage is sometimes referred to as the voltage level. For any signal or voltage, switching from low level to high level is called up edge, and timing of switching from low level to high level is called up edge timing. Similarly, for any signal or voltage, switching from high level to low level is referred to as down edge, and timing of switching from high level to low level is referred to as down edge timing.

For any transistor configured as a FET (Field Effect Transistor) including a MOSFET, the on state means that the drain and source of the transistor are in a conductive state, and the off state means the drain of the transistor. And it means that the source is in a non-conducting state (blocking state). The same applies to transistors that are not classified as FETs. Unless otherwise specified, the MOSFET may be understood as an enhancement type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". PWM is an abbreviation for Pulse Width Modulation.

Hereinafter, the on state and the off state of any transistor may be simply expressed as on and off. For any transistor, switching from the off state to the on state is expressed as turn-on, and switching from the on state to the off state is expressed as turn-off. Further, for any transistor, a section in which the transistor is in the on state may be referred to as an on section, and a section in which the transistor is in the off state may be referred to as an off section. For any signal having a high level or low level signal level, the section where the level of the signal is high level is referred to as a high level section, and the section where the level of the signal is low level is referred to as a low level section. The same is true for any voltage that has a high or low voltage level.

<< First Embodiment >>
The first embodiment of the present invention will be described. FIG. 1 is an overall configuration diagram of the AC / DC converter 1 according to the first embodiment. The AC / DC converter 1 includes a filter 2, a rectifier circuit 3, a DC / DC converter 4 which is an isolated DC / DC converter 4, a smoothing capacitor C1, and an output capacitor C2. It may be understood that the output capacitor C2 is included in the components of the DC / DC converter 4. Details will be apparent from the following description, but in the AC / DC converter 1, generates a secondary-side voltage V _S at the switching system using a transformer from the primary side voltage V _P.

The AC / DC converter 1 is composed of a primary side circuit arranged on the primary side of the AC / DC converter 1 and a secondary side circuit arranged on the secondary side of the AC / DC converter 1, and is composed of a primary side circuit and a secondary side circuit. It is electrically isolated from the side circuits. When paying attention to the DC / DC converter 4, the primary side circuit is the primary side circuit arranged on the primary side of the DC / DC converter 4, and the secondary side circuit is the DC / DC converter 4. It is understood that it is a secondary side circuit arranged on the secondary side. The filter 2, the rectifier circuit 3, and the smoothing capacitor C1 are arranged in the primary side circuit, and the output capacitor C2 is arranged in the secondary side circuit. The DC / DC converter 4 is arranged over the primary side circuit and the secondary side circuit.

The ground in the primary side circuit is referred to by "GND1", and the ground in the secondary side circuit is referred to by "GND2". It includes a primary-side voltage V _P, the voltage in the primary side circuit is a voltage referenced to ground GND1. Including secondary voltage V _S, the voltage in the secondary side circuit is a voltage referenced to ground GND2. In each of the primary side circuit and the secondary side circuit, the ground refers to a conductive portion (predetermined potential point) having a reference potential of 0 V (zero volt) or refers to the reference potential itself. However, since the ground GND1 and the ground GND2 are insulated from each other, they may have different potentials from each other.

The filter 2 removes the noise of the _AC voltage VAC input to the AC / DC converter 1. AC voltage V _AC may be a commercial AC voltage. The rectifier circuit 3 is a diode bridge circuit that full-wave rectifies the _AC voltage VAC supplied through the filter 2. The smoothing capacitor C1 generates a DC voltage by smoothing a full-wave rectified voltage. DC voltage generated by the smoothing capacitor C1 functions as a primary voltage V _P. Primary voltage _{V P} is applied between the pair of input terminals _{TM IH} and _{TM 1L.} Specifically, the terminal on the low potential side of the smoothing capacitor C1 is connected to the ground GND1 and is connected to the input terminal TM _1L, and the terminal on the high potential side of the smoothing capacitor C1 is connected to the input terminal TM _1H . Then, the primary side voltage _VP is applied to the input terminal TM _1H with reference to the potential at the input terminal TM _1L .

DC / DC converter 4, a power conversion at the switching system of the primary-side voltage V _P - a (DC-DC converter) to be to generate a secondary voltage V _S which is stabilized at a predetermined target voltage V _TG .. Secondary voltage _{V S} is equivalent to the output voltage of the AC / DC converter 1, applied between a pair of output terminals _{TM 2H} and _{TM 2L.} Specifically, the low-potential side terminal of the output capacitor C2 is connected to the ground GND2 and the output terminal TM _2L, and the high-potential side terminal of the output capacitor C2 is connected to the output terminal TM _2H . The secondary-side voltage _{V S} is applied to the output terminal _{TM 2H} based on the potential at the output terminal _{TM 2L.} The pair of input terminals TM _1H and TM _1L can be considered to correspond to the pair of input terminals in the DC / DC converter 4, and the pair of output terminals TM _2H and TM _2L are the output terminals in the AC / DC converter 1 or the DC / DC converter 4. You can think of it as a pair.

The load LD is also shown in FIG. The load LD can be considered to be the load of the AC / DC converter 1, or can be considered to be the load of the DC / DC converter 4 if the DC / DC converter 4 is focused on. Load LD is connected to a pair of output terminals _{TM 2H} and _{TM 2L,} is any load driven on the basis of the secondary voltage _{V S.} For example, the load LD is a microcomputer, a DSP (Digital Signal Processor), a power supply circuit, a lighting device, an analog circuit, or a digital circuit.

FIG. 2 shows an example of the internal configuration of the DC / DC converter 4 provided in the AC / DC converter 1. The DC / DC converter 4 includes a transformer TR which is a power transformer having a primary winding W1 and a secondary winding W2. In the transformer TR, the primary winding W1 and the secondary winding W2 are electrically insulated and magnetically coupled to each other with opposite polarities.

In the primary side circuit of the DC / DC converter 4 (in other words, the primary side circuit of the AC / DC converter 1), in addition to the primary side winding W1, the primary side control circuit 10 and the primary side power supply circuit 11 are smoothed. A capacitor C1, a switching transistor M1 as an example of a switching element, and a sense resistor _{RC S} are provided. When focusing on the DC / DC converter 4, the smoothing capacitor C1 is also referred to as an input capacitor C1. As described above, the input capacitor C1 is provided between the input terminals TM _1L and TM _1H, and the primary side voltage _VP is applied between both terminals of the input capacitor C1.

The switching transistor M1 is configured as an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor). One end of the primary winding W1 is connected to the input terminal TM _IH to receive the primary voltage V _P of the DC. The other end of the primary winding W1 is connected to the drain of the switching transistor M1, the source of the switching transistor M1 is connected to the ground GND1 through the sense resistor R _CS. The primary side power supply circuit 11 generates a power supply voltage VCS having a desired voltage value by converting the primary side voltage _VP from DC to DC, and supplies the power supply voltage to the primary side control circuit 10. The primary side control circuit 10 is driven based on the power supply voltage (drive voltage) VCS.

The primary side control circuit 10 is connected to the gate of the switching transistor M1 and switches and drives the switching transistor M1 by supplying a drive signal DRV to the gate of the switching transistor M1. The drive signal DRV is a rectangular wavy signal whose signal level switches between low level and high level. When a low level signal and a high level signal are supplied to the gate of the transistor M1, the transistor M1 is turned off and turned on, respectively.

In the secondary side circuit of the DC / DC converter 4 (in other words, the secondary side circuit of the AC / DC converter 1), in addition to the secondary side winding W2, the secondary side control circuit 20 and the synchronous rectifier transistor M2 , The diode D2, the voltage dividing resistors R1 to R4, and the output capacitor C2 are provided. The synchronous rectifying transistor M2 (hereinafter, may be referred to as SR transistor M2) is configured as an N-channel MOSFET. The diode D2 is a parasitic diode of the SR transistor M2. Therefore, the diode D2 is connected in parallel to the SR transistor M2 with the direction from the source of the SR transistor M2 toward the drain as the forward direction. The diode D2 may be a diode provided separately from the parasitic diode.

One end of the secondary winding W2 is connected to the output terminal TM _2H, hence secondary voltage V _S is applied to one end of the secondary winding W2. The other end of the secondary winding W2 is connected to the drain of the SR transistor M2. The voltage at the other end of the secondary winding W2 (in other words, the drain voltage of the SR transistor M2) is represented by " _VDR ". The connection node between the other end of the secondary winding W2 and the drain of the SR transistor M2 is connected to one end of the voltage dividing resistor R1, and the other end of the voltage dividing resistor R1 is connected to the ground GND2 via the voltage dividing resistor R2. Ru. Therefore, the voltage V _A, which is the voltage divider of the voltage V _DR , is applied to the connection node between the voltage dividing resistors R1 and R2. On the other hand, the output terminal TM _2H secondary side voltage V _S is applied is connected to one end of the voltage dividing resistors R3, the other end of the voltage dividing resistor R3 is connected to ground GND2 via the voltage dividing resistor R4. Therefore, the voltage V _B applied to a connection node between the voltage dividing resistors R3 and R4 is the partial pressure of the secondary-side voltage V _S. Of course, the voltage _V DR, _{V A} and _{V B} is a voltage to the secondary-side voltage _{V S} as well as referenced to ground GND2.

The source of the SR transistor M2 is connected to the ground GND2. As described above, the output capacitor C2 is provided between the output terminals _{TM 2H} and _{TM 2L,} thus the secondary side voltage _{V S} across the terminals of the output capacitor C2 is applied.

The secondary side control circuit 20 is driven using the secondary voltage V _S as a power supply voltage (drive voltage). The secondary side control circuit 20 controls the on / off of the SR transistor M2 by controlling the gate voltage of the SR transistor M2. The secondary side control circuit 20, the control may be performed based on the basis or the voltage V _A and V _B to the voltage V _A, this time, the gate of the SR transistor M2 as the transistors M1 and M2 are not turned ON at the same time The voltage can be controlled.

In the DC / DC converter 4, a pulse transformer unit 30 is provided over the primary side circuit and the secondary side circuit. The pulse transformer unit 30 is a communication transformer for realizing communication between the primary side control circuit 10 and the secondary side control circuit 20, and includes one or more pulse transformers. Communication via the pulse transformer unit 30 is an isolated type communication (that is, communication in a state where the primary side circuit and the secondary side circuit are insulated). Communication between the control circuits 10 and 20 is unidirectional communication capable of only transmitting a signal from one of the control circuits 10 and 20 to the other, or bidirectional communication between the control circuits 10 and 20. In the present embodiment, it is assumed that the signal can be transmitted from the secondary side control circuit 20 to the primary side control circuit 10 via the pulse transformer unit 30.

The primary side control circuit 10, a sense resistor in addition to can generate a drive signal DRV based on the current sense voltage V _CS that corresponds to the voltage drop across the R _CS, the secondary side control circuit via a pulse transformer 30 20 It is also possible to generate a drive signal DRV under the control of.

The primary side control circuit 10 is provided with a plurality of terminals, and the plurality of terminals provided in the primary side control circuit 10 include a terminal TM11 connected to the gate of the switching transistor M1 and a terminal that receives the power supply voltage VCS. and TM12, the terminal TM13 is connected to ground GND1, a terminal TM14 to receive a current sense voltage _{V CS,} a terminal TM15 is connected at the primary side of the pulse transformer unit 30, it is included. The terminal TM15 may be composed of two or more terminals.

The secondary side control circuit 20 is provided with a plurality of terminals, and the plurality of terminals provided in the secondary side control circuit 20 include a terminal TM21 connected to the gate of the SR transistor M2 and a secondary side voltage. a terminal TM22 to undergo V _S, terminal and terminal TM23 is connected to ground GND2, and the terminal TM24 receiving voltage _{V a,} a terminal TM25 to receive a voltage _{V B,} which is connected to the pulse transformer section 30 at the secondary side TM26 and are included. The terminal TM26 may be composed of two or more terminals.

In the thus configured DC / DC converter 4, by switching the switching transistor M1 (by switching control of the switching transistor M1 in other words) that the primary voltage V _P to obtain a secondary side voltage V _S Can be done. That is, energy is stored in the primary winding W1 in the on section of the switching transistor M1, and the accumulated energy is released from the secondary winding W2 in the off section of the switching transistor M1 to charge the output capacitor C2. has been secondary-side voltage V _S is obtained. Loss can be reduced by keeping the SR transistor M2 on when energy is released from the secondary winding W2.

Instead of providing the primary side power supply circuit 11, an auxiliary winding is provided in the transformer TR, and the power supply voltage VCS of the primary side control circuit 10 is generated by the self-power supply circuit including the auxiliary winding. You may do so.

Further, the current flowing through the sense resistor _{RC S} is referred to as a primary side current, and is referred to by the symbol “ _IP ”. Primary current _{I P} is the current flowing to ground GND1 through the primary winding W1 and the switching transistor M1 to the input terminal _{TM IH.} In the secondary side circuit, the current flowing from the ground GND2 to the output terminal TM _2H through the secondary side winding W2 is referred to as a secondary side current and is represented by the symbol “ _IS ”.

[Example of signal waveform during synchronous rectification]
FIG. 3 shows an example of each signal waveform during synchronous rectification that can be performed in the DC / DC converter 4. In the example of FIG. 3, the switching transistor M1 is turned on in the section between the timings t _A1 and t _A2 , and then the switching transistor M1 is turned off in the section up to the timing t _A5 .

In the on-interval of the switching transistor M1, the current _{I P} flowing in the primary winding W1, the voltage _{V DR} is higher by the voltage _{V OR @ 2} than the secondary-side voltage _{V S.} The voltage V _OR2 is an induced voltage generated in the secondary winding W2 in the on section of the switching transistor M1. When the switching transistor M1 at a timing _{t A2} is turned off, decreased sharply voltage _{V DR} and _{V A} until a voltage lower than the ground GND2, flows secondary current _{I S} through the diode D2. The secondary side control circuit 20 can quickly turn on the SR transistor M2 when the switching transistor M1 turns off. For example, when the secondary side control circuit 20 detects that the voltage _VA has fallen below a predetermined negative turn-on determination voltage (for example, -100 mV), the secondary side control circuit 20 turns on the SR transistor M2. Can be done. The timing t _A3 represents the turn-on timing of the SR transistor M2.

After SR transistor M2 is turned on, the secondary-side current I _S flows through the channel of the SR transistor M2, the magnitude of the secondary current I _S is slide into reduced with decreasing the stored energy of the transformer TR. At timing _{t A4} after timing _{t A3,} the secondary-side control circuit 20 turns off the SR transistor M2. For example, the secondary side control circuit 20 can turn off the SR transistor M2 in response to the voltage _VA becoming equal to or higher than a predetermined negative turn-off determination voltage (for example, −10 mV). The potential of the turn-off judgment voltage is higher than the potential of the turn-on judgment voltage. After that, the switching transistor M1 is turned on at the timing t _A5 . After that, the same operation is repeated.

Such a control method of the SR transistor M2 is called a comparator method. As will be described later, in the DC / DC converter 4, the secondary side control circuit 20 can mainly control the on / off of the switching transistor M1, and in this case, the comparator method is not used (however, the comparator method is not used. May be used). In any case, the transistors M1 and M2 are controlled so that the transistors M1 and M2 are not turned on at the same time.

[Operation flowchart]
FIG. 4 is an operation flowchart of the AC / DC converter 1 and the DC / DC converter 4. When the input AC voltage V _AC for the AC / DC converter 1 is started (step STP1), the primary side by the voltage V _P rises primary side control circuit 10 has the primary side is generated can drive voltage VCC start The control circuit 10 is activated (step STP2). When the primary side control circuit 10 is activated, the primary side control circuit 10 first performs a predetermined burst operation (step STP3). In the burst operation, the primary-side control circuit 10, after turning on the switching transistor M1, the voltage value of the current sense voltage V _CS is repeatedly executed periodically the operation of turning off the switching transistor M1 when it reaches a predetermined value .. Thus, the output capacitor C2 Yuki is charged, the secondary-side voltage V _S is reached to a predetermined secondary side start voltage secondary side control circuit 20 is activated (step STP4). When the secondary side control circuit 20 is activated, the start circuit (not shown) provided in the secondary side control circuit 20 becomes the main body, and a predetermined start signal is transmitted to the primary side control circuit 10 via the pulse transformer unit 30. The activation sequence process including the process to be transmitted is executed (step STP5). When the start-up sequence process is normally completed, the secondary side control in which the transistor M1 is switched and driven under the control of the secondary side control circuit 20 is started (step STP6).

An example of startup sequence processing is given. In the start-up sequence processing, the start circuit (not shown) provided in the secondary side control circuit 20 sends the first start-up signal to the pulse transformer unit during the section where the transistor M1 is determined to be in the ON state based on the voltage _VA. It is transmitted to the primary side control circuit 10 via 30. The primary control circuit 10 terminates the burst operation in response to the reception of the first start signal and immediately turns off the transistor M1. The start circuit confirms that the transistor M1 has been turned off in response to the first start signal based on the voltage _VA , and then sequentially transmits a plurality of second start signals via the pulse transformer unit 30 to the primary side control circuit 10. Send to. The primary side control circuit 10 switches the state of the transistor M1 between on and off each time the second start signal is received. When the start circuit confirms based on the voltage _VA that the state of the transistor M1 is switched between on and off each time the second start signal is transmitted, the start sequence process ends normally.

In the start-up sequence process, when the switching between on and off of the transistor M1 in response to the start-up signal is not confirmed, a predetermined error handling process is performed. In the error handling process, the start circuit can, for example, restart the start sequence process from the beginning.

It is assumed that the state of the transistor M1 at the time of normal termination of the start-up sequence processing is the off state. Hereinafter, in the present embodiment, the contents of the secondary side control after the activation sequence processing is normally completed and the configuration for performing the secondary side control will be described.

[Internal configuration of each control circuit]
The configuration related to the realization of secondary control will be described. FIG. 5 is a partial configuration diagram of the secondary side control circuit 20A, and FIG. 6 is a partial configuration diagram of the primary side control circuit 10A. In the present embodiment, it is assumed that the secondary side control circuit 20A is used as the secondary side control circuit 20 and the primary side control circuit 10A is used as the primary side control circuit 10.

As shown in FIG. 5, the secondary side control circuit 20A includes a PWM control unit (control signal generation unit) 210, a secondary side transmission unit 220, and a matching determination unit 230. As shown in FIG. 6, the primary side control circuit 10A includes a primary side receiving unit 110, a restoring unit 120, and a driving unit 130. The matching determination unit 230 will be described later, and the functions and operations of the parts other than the matching determination unit 230 among the parts shown in FIGS. 5 and 6 will be described.

PWM control unit 210 generates a signal _{S PWM2} based on the voltage _{V B} in accordance with the secondary-side voltage _{V S.} The signal S _PWM2 is a PWM signal for the switching transistor M1 and is an example of the original switching control signal. The PWM control unit 210 outputs the generated signal S _PWM2 to the secondary side transmission unit 220.

The secondary side transmission unit 220 outputs a signal based on the signal S _PWM2 generated by the PWM control unit 210 to the pulse transformer unit 30. With reference to FIG. 7, the flow of transmission of the signal based on the signal S _PWM2 from the secondary side control circuit 20A to the primary side control circuit 10A will be described. The pulse transformer unit 30 is provided with a pulse transformer 31 that enables signal transmission from the secondary side control circuit 20A to the primary side control circuit 10A. The pulse transformer 31 is composed of a primary winding 31_1 and a secondary winding 31_2 that are magnetically coupled while being insulated from each other. The primary winding 31_1 is arranged in the primary circuit and the secondary winding 31_2 is arranged in the secondary circuit.

The secondary side transmission unit 220 outputs the transmission pulse signal TP2 as a transmission signal to the pulse transformer 31 based on the signal S _PWM2 . The output of the transmission pulse signal TP2 to the pulse transformer 31 means that the transmission pulse signal TP2 is supplied to the secondary winding 31_2 of the pulse transformer 31. Supplying the transmission pulse signal TP2 to the secondary winding 31_2 of the pulse transformer 31 means that the pulsed voltage generated by the transmission pulse signal TP2 is supplied to the secondary winding 31_2 to supply the current flowing through the secondary winding 31_2. As long as there is a change in the current flowing through the secondary winding 31_2, the method of supplying the pulsed voltage is arbitrary. Due to the change in the current, a voltage is generated in the primary winding 31_1.

The primary side receiving unit 110 generates a receiving pulse signal RP1 as a receiving signal based on the voltage generated in the primary side winding 31_1 due to the supply of the transmitting pulse signal TP2. The primary side receiving unit 110 compares, for example, the magnitude of the voltage between both terminals of the primary winding 31_1 with a predetermined determination voltage using a comparator, and determines the magnitude of the voltage between both terminals of the primary winding 31_1. When the voltage is equal to or higher than the voltage, one pulse signal is generated as the received pulse signal RP1. The primary reception unit 110 outputs the generated reception pulse signal RP1 to the restoration unit 120 (see FIG. 6).

The restoration unit 120 generates the signal S _PWM1 based on the reception pulse signal RP1 generated by the primary reception unit 110. The signal S _PWM1 here corresponds to a signal (restored switching control signal) obtained by restoring the signal S _PWM2 in the primary side control circuit 10A. The drive unit 130 switches the switching transistor M1 by generating a drive signal DRV based on the signal S _PWM1 .

FIG. 8 shows the relationship between the signal S _PWM2 , the transmission pulse signal TP2, the reception pulse signal RP1, the signal S _PWM1 , the state of the transistor M1, and the voltage _VDR ( _VA ). _{Each of the} signals S _PWM1 and S _PWM2 is a binarized signal having a high level or low level signal level. In the present embodiment, in the secondary side control, PWM control for switching the transistor M1 at a predetermined PWM frequency is performed.

In the signal S _PWM2 , the generation interval of two _upedges adjacent to each other is equal to the length of the PWM cycle corresponding to the reciprocal of the PWM frequency. In the signal S _PWM2 , the section from the generation timing of one up edge to the generation timing of the next up edge is referred to as a unit control section. The length of each unit control section is equal to the length of the PWM cycle. When PWM control is performed, a plurality of unit control sections arranged in a time series are sequentially generated.

Secondary transmission section 220, the signal _S every time the falling edge occurs at and the signal _{S PWM2} each time a rising edge occurs at _PWM2, and outputs one of the transmission pulse signal TP2 with respect to the pulse transformer 31 (i.e. 1 The two transmission pulse signals TP2 are supplied to the secondary winding 31_2 of the pulse transformer 31). Therefore, sent in the primary receiver unit 110 at and the signal _{S PWM2} each time a rising edge in the signal _{S PWM2} is generated each time a falling edge occurs, the restoration unit 120 one received pulse signal RP1 is generated It will be.

The restoration unit 120 switches the level of the signal S _PWM1 between the low level and the high level each time the reception pulse signal RP1 is received from the primary reception unit 110. Here, it is assumed that the initial levels of the signals S _PWM1 and S _PWM2 at the start of the secondary side control are both low levels. Thus, the signal _{S PWM1} is a signal obtained by restoring the signal _{S PWM2,} with the waveform of the signal _{S PWM2} substantially the same waveform. Strictly speaking, the signal delay component only is the up-edge timing of the signal S _PWM1 from up-edge timing of the signal S _PWM2 is delayed, here (same for down edge timing) of the signal delay is ignored as is minute.

The drive unit 130 supplies the high-level drive signal DRV to the gate of the transistor M1 in the high-level section of the signal S _PWM1 to turn on the transistor M1, and the low-level drive signal DRV in the low-level section of the signal S _PWM1. Is supplied to the gate of the transistor M1 to turn off the transistor M1. The voltage _{V DR} varies corresponding to the drain voltage of the SR transistor M2 in accordance with the state of the transistor M1 (see FIG. 8).

The high level section of the signal S _{PWM2 and} the high level section of the signal S _PWM1 correspond to the on control section, respectively, and the low level section of the signal S _{PWM2 and} the low level section of the signal S _PWM1 correspond to the off control section, respectively. Each unit control section corresponds to the sum of one on control section and one off control section. The on control section is a section in which the transistor M1 should be controlled in the on state (first section), and the off control section is a section in which the transistor M1 should be controlled in the off state (second section).

In PWM control, the on control section and the off control section are alternately designated by the signal S _PWM2 or S _PWM1 . However, in the secondary side control circuit 20A, the on control section and the off control section are specified by the signal S _PWM2 (original switching control signal), and in the primary side control circuit 10A, the on control section and the on control section and the off control section are specified by the signal S _PWM1 (restoration switching control signal). The off control section will be specified. Thus, the drive unit 130 in the primary-side control circuit 10A includes a transistor M1 is turned on at specified by the signal _{S PWM1} ON control period (high-level period of the signal _{S PWM1),} it is designated by the signal _{S PWM1} The transistor M1 is turned off in the off control section (low level section of the signal S _PWM1 ).

FIG. 9 shows a configuration example of the PWM control unit 210. The PWM control unit 210 of FIG. 9 includes an error amplifier 211, a slope signal generation unit 212, and a PWM comparator 213.

The error amplifier 211 compares the voltage V _B with the predetermined reference voltage V _REF , generates an error signal _SERR corresponding to the difference between them, and outputs the error signal _SERR . The error amplifier 211 operates so as to increase the signal value of the error signal S _ERR if "V _B <V _REF ", and to decrease the signal value of the error signal S _ERR if "V _B > V _REF ". Operate. The error amplifier 211 does not change the signal value of the error signal _SERR when “V _B = V _REF ”. When the secondary-side voltage _{V S} is equal to a predetermined target voltage _{V TG,} the voltage _{V B} is equal to the reference voltage _{V REF.}

The slope signal generation unit 212 generates a slope signal S _SLP , which is a voltage signal having a predetermined PWM frequency. The slope signal S _SLP is a triangular wave or sawtooth voltage signal whose signal value periodically increases or decreases in a cycle of the reciprocal of the PWM frequency (hereinafter referred to as a PWM cycle).

The PWM comparator 213 includes a non-inverting input terminal, an inverting input terminal, and an output terminal. In the PWM comparator 213, the error signal _SERR is input to the non-inverting input terminal, and the slope signal S _SLP is input to the inverting input terminal. The PWM comparator 213 compares the error signal S _ERR and the slope signal S _SLP, and outputs the signal S _PWM2 , which is a PWM signal according to the height relationship between them, from its own output terminal. The signal S _PWM2 has a high level in the section where the signal value of the error signal S _RR is higher (larger) than the signal value of the slope signal S _SLP , and the signal S _{PWM 2} has a low level in the other sections. However, when "S _ERR = S _SLP ", the signal S _PWM2 can be at a high level.

With this configuration, if "V _B <V _REF ", the duty of the signal S _PWM2 increases as the error signal S _ERR rises, and if "V _B > V _REF ", the error signal S _ERR The duty of the signal S _PWM2 decreases through the decrease. As shown in FIG. 8, the duty of the signal S _PWM2 , the duty of the signal S _PWM1 , and the duty of the transistor M1 substantially match each other. Therefore, if “V _B <V _REF ”, the duty of the transistor M1 is The transmission energy to the secondary side increases, and if "V _B > V _REF ", the duty of the transistor M1 decreases and the transmission energy to the secondary side decreases. As a result, a voltage V _B reference voltage V _REF at work feedback to match the secondary-side voltage V _S is stabilized at a predetermined target voltage V _TG.

The duty of the signal _{S PWM2,} with respect to the low level period and the total period of high-level period of the signal _{S PWM2,} signal the signal high-level period of the _{S PWM2} refers to the proportion of the (in other words, the unit control section _{S PWM2} Refers to the percentage occupied by the high-level section of). The same applies to the duty of the signal S _PWM1 . The duty of the transistor M1 refers to the ratio of the on-section of the transistor M1 to the total section of the on-section and the off-section of the transistor M1 (in other words, the ratio of the on-section of the transistor M1 in each unit control section). ).

The secondary side control circuit 20A is provided with a synchronous rectification drive unit (not shown in FIG. 5) that drives the SR transistor M2 by controlling the gate voltage of the SR transistor M2. Before the start of the secondary side control, the SR transistor M2 is fixed in the off state. When the secondary-side control is started, the synchronous rectifier drive unit, the signal S the SR transistor M2 is turned off at _PWM2 high level section, SR transistor in all or part of the low-level period of the signal S _PWM2 M2 Is turned on. As a result, the loss can be reduced. However, as will be described later, the diode rectification method may be adopted in the DC / DC converter 4, and in this case, since the SR transistor M2 does not exist, the synchronous rectification drive unit is unnecessary.

[Correction by matching judgment unit]
If a communication error or the like does not occur, the signal S _PWM1 accurately restores the signal S _PWM2 , but when a communication error or the like occurs, the waveform of the signal S _PWM1 may differ from the waveform of the signal S _PWM2. .. This phenomenon will be described with reference to FIG.

In FIG. 10, it is assumed that noise NP is generated around the pulse transformer 31 and reception pulse signal RP1 based on the noise NP is generated. The received pulse signal RP1 based on the noise NP is not a pulse signal based on the transmitted pulse signal TP2 and has nothing to do with the signal S _PWM2. However, when the received pulse signal RP1 based on the noise NP is generated, the signal S _PWM1 The level is reversed when viewed from the level of the signal S _PWM2 .

FIG. 10 shows various waveforms in the virtual configuration in which the matching determination unit 230 of FIG. 5 is not provided. In the virtual configuration, once the level of the signal S _PWM1 is reversed when viewed from the level of the signal S _PWM2 , After that, the reverse state will continue. Result, PWM control is not correctly function based on the secondary-side voltage V _S, the abnormal decrease or abnormal increase in the secondary-side voltage V _S may occur. Further, when consent rectification is performed using the synchronous rectification drive unit, an overcurrent may occur due to simultaneous on of the transistors M1 and M2. In FIG. 10, the broken line waveform 511 shows the waveform of the voltage _VDR that would have been observed if the signal S _PWM1 had coincided with the signal S _PWM2 (the same applies to FIG. 11 described later).

In consideration of this, as shown in FIG. 5, the secondary side control circuit 20A is provided with a matching determination unit 230. The matching determination unit 230 executes a secondary side matching determination process for determining the consistency (presence or absence of consistency) of the signals S _PWM1 and S _PWM2 , and determines that the signal S _PWM1 and the signal S _PWM2 are not matched. When the secondary side correction process is executed. The determination of the integrity of the signal _{S PWM1} and _{S PWM2,} refers to the determination signal _{S PWM1} and signal _{S PWM2} is whether consistent. The secondary side correction process is executed only when it is determined that the signal S _PWM1 and the signal S _PWM2 do not match.

The fact that the signal S _PWM1 and the signal S _PWM2 are consistent means that the on control section and the off control section specified by the signal S _PWM1 coincide with the on control section and the off control section specified by the signal S _PWM2, respectively. Refers to the state of being. The fact that the signal S _PWM1 and the signal S _PWM2 do not match means that the on control section and the off control section specified by the signal S _PWM1 and the on control section and the off control section specified by the signal S _PWM2 are reversed. state are (i.e., the section specified by the signal _{S PWM2} in specified on control section by the signal _{S PWM1} is turned off control section, and is designated by the signal _{S PWM2} in off control section is designated by the signal _{S PWM1} It refers to a state in which the section is an on-control section), and when expressed using signal levels, it refers to a state in which one of the signals S _PWM1 and S _PWM2 is at a high level and the other is at a low level.

FIG. 11 shows an example of various signals and voltage waveforms in the configuration of the present embodiment provided with the matching determination unit 230.

In the secondary side correction process, the matching determination unit 230 outputs a predetermined correction instruction signal to the secondary side transmission unit 220. The secondary side transmitting unit 220 that has received the correction instruction signal outputs the correction pulse signal TP2_C as the correction signal regardless of the signal S _PWM2 (see FIG. 11). That is, it can be said that in the secondary side correction process, the matching determination unit 230 uses the secondary side transmission unit 220 to output the correction pulse signal TP2_C to the pulse transformer 31. The output of the correction pulse signal TP2_C to the pulse transformer 31 specifically means supplying the correction pulse signal TP2_C to the secondary winding 31_2 of the pulse transformer 31. Supplying the correction pulse signal TP2_C to the secondary winding 31_2 of the pulse transformer 31 means that the pulsed voltage generated by the correction pulse signal TP2_C is supplied to the secondary winding 31_2 to supply the current flowing through the secondary winding 31_2. As long as there is a change in the current flowing through the secondary winding 31_2, the method of supplying the pulsed voltage is arbitrary. Due to the change in the current, a voltage is generated in the primary winding 31_1. The correction pulse signal TP2_C may be a pulse-shaped signal having the same waveform as the transmission pulse signal TP2 based on the signal S _PWM2 .

As a result, the secondary side transmitter 220 receives the transition timing from the off control section to the on control section and the transition timing from the on control section to the off control section specified by the signal S _PWM2 (original switching control signal), respectively. The transmission pulse signal TP2 (transmission signal) is supplied to the secondary winding 31_2 of the pulse transformer 31 (communication transformer) (at each of the up-edge timing and the down-edge timing of the signal S _PWM2 ), and a separate signal is provided. When it is determined that the S _PWM1 (restoration switching control signal) does not match the signal S _PWM2 (original switching control signal), the correction pulse signal TP2_C (correction signal) is supplied to the secondary winding 31_2 of the pulse transformer 31. It will be.

The primary side receiving unit 110 generates the received pulse signal RP1 based on the voltage generated in the primary side winding 31_1 due to the supply of the correction pulse signal TP2_C (see FIG. 11). Therefore, the primary side receiving unit 110 also receives the correction pulse signal TP2_C based on the secondary side correction processing even when the transmission pulse signal TP2 based on the signal S _PWM2 is supplied to the secondary side winding 31_2 of the pulse transformer 31. Is also supplied, the received pulse signal RP1 is generated based on the voltage generated in the primary winding 31_1 of the pulse transformer 31.

The restoration unit 120 does not distinguish (without recognizing) whether the reception pulse signal RP1 provided from the primary reception unit 110 is based on the transmission pulse signal TP2 or the correction pulse signal TP2_C, and the reception pulse signal. switches the level of the signal S _PWM1 whenever receiving the RP1 between low level and high level, switches the interval specified words by the signal S _PWM1 between an on control section and the off control section. As a result, the consistency between the signal S _PWM1 and the signal S _PWM2 , which had been temporarily collapsed, is ensured again.

As described above, in the present embodiment, even if a communication abnormality occurs, it is possible to self-recover. That is, for example, even if a phenomenon occurs in which the level of the signal S _PWM1 is reversed when viewed from the level of the signal S _PWM2 based on the generation of noise NP, the phenomenon remains temporary and quickly returns to the normal control state. Can be made to. Result, it is possible to avoid abnormal decrease or abnormal increase in the secondary-side voltage V _S due to the phenomenon. Although noise was focused on as a factor of the level reversal phenomenon between the signals S _PWM1 and S _PWM2 , the same phenomenon occurs due to the transmission failure of the pulse signal that should be originally transmitted, and the configuration of the present embodiment is also in this case. Works effectively.

The secondary side matching determination process by the matching determination unit 230 will be described. Matching determination unit 230, a signal _{S PWM2} generated by the PWM control unit 210, based on the voltage _{V DR} that varies in response to the switching of the transistors M1, signal integrity _{S PWM1} and _{S PWM2} (integrity Presence / absence) is determined. Since there is a large difference in voltage V _DR between the case where the signal S _PWM1 and the signal S _PWM2 are matched and the case where they are not matched (see FIGS. 10 and 11), refer to the voltage V _DR together with the signal S _PWM2 . For example, the consistency (presence or absence of consistency) of the signals S _PWM1 and S _PWM2 can be easily determined. When a predetermined mismatch condition is satisfied, the matching determination unit 230 determines that the signal S _PWM1 does not match the signal S _PWM2 , and otherwise determines that the signal S _PWM1 matches the signal S _PWM2. To do.

Specifically, for example, the matching determination unit 230 compares the voltage _VA in the high level section of the signal S _PWM2 with a predetermined positive first determination voltage, and the voltage _VA in the high level section of the signal S _{PWM 2} is the first. If it is below the judgment voltage (specifically, for example, if a state in which the voltage _VA is below the first judgment voltage is continuously observed for a predetermined time or longer in the high level section of the signal S _PWM2 ), the mismatch condition is satisfied. Then judge.

Alternatively, for example, the matching determination unit 230 compares the voltage _VA in the low level section of the signal S _PWM2 with a predetermined positive second determination voltage, and the voltage _VA in the low level section of the signal S _PWM2 is equal to or higher than the second determination voltage. If (specifically, for example, if a state in which the voltage _VA is equal to or higher than the second determination voltage is continuously observed for a predetermined time or longer in the low level section of the signal S _PWM2 ), it is determined that the mismatch condition is satisfied. ..

Although different from the configuration shown in FIG. 5, the matching determination unit 230, a signal _{S PWM2} generated by the PWM control unit 210, based on the secondary current _{I S,} the signal _{S PWM1} and _{S PWM2} A modification method for determining consistency (presence or absence of consistency) may be adopted. In this case, a voltage proportional to the secondary current I _S resistor for generating (hereinafter, referred to as voltage V _IS) (not shown) to the secondary winding W2 in advance are connected in series, the voltage V _IS It may be given to the matching determination unit 230 together with the signal S _PWM2 . Even in this case, the matching determination unit 230 also determines that the signal S _PWM1 does not match the signal S _PWM2 when a predetermined mismatch condition is satisfied, and otherwise, the signal S _PWM1 matches the signal S _PWM2 . Judge that it is.

Specifically, for example, matching determination unit 230 according to the modified method, the high-level period of the signal S _PWM2, when the magnitude of the secondary current I _S shown by the voltage V _IS is the predetermined value or more (Details for example, once the state where the magnitude of the secondary current I _S at the high level period of the signal S _PWM2 is equal to or greater than a predetermined value observed continuously for a predetermined time or more), it is determined that the mismatch condition is satisfied. High-level period of the signal S _PWM2 is originally a ON period of the transistor M1, because should not flow secondary current I _S.

<< Second Embodiment >>
A second embodiment of the present invention will be described. The second embodiment and the third to fifth embodiments described later are embodiments based on the first embodiment, and the matters not particularly described in the second to fifth embodiments are the first unless there is a contradiction. The description of the embodiment also applies to the second to fifth embodiments. In interpreting the description of the second embodiment, the description of the second embodiment may be prioritized for matters that conflict between the first and second embodiments (the same applies to the third to fifth embodiments described later). .. As long as there is no contradiction, any plurality of embodiments may be combined among the first to fifth embodiments.

In the first embodiment, the secondary side master system is adopted in which the secondary side control circuit 20 functions as a master and the primary side control circuit 10 functions as a slave, but the primary side control circuit 10 functions as a master. Moreover, the primary side master system in which the secondary side control circuit 20 functions as a slave may be adopted, and the technique described in the first embodiment can be applied even when the primary side master system is adopted. An application example of the technique described in the first embodiment will be described on the premise that the primary side master method is adopted in the second embodiment.

FIG. 12 is a partial configuration diagram of the DC / DC converter 4 (see FIG. 2) according to the second embodiment. In the second embodiment, the primary side control circuit 10B of FIG. 12 is used as the primary side control circuit 10 of FIG. 2, and the secondary side control circuit 20B of FIG. 12 is used as the secondary side control circuit 20 of FIG. Be done. Further, the DC / DC converter 4 according to the second embodiment is provided with the capacitor 12, the feedback circuit 40, and the photocoupler 41 of FIG. 12 in addition to those described above with reference to FIG. The capacitor 12 is provided in the primary side control circuit, the feedback circuit 40 is provided in the secondary side circuit, and the photocoupler 41 is provided over the primary side circuit and the secondary side circuit.

The photocoupler 41 has a light emitting element arranged in the secondary side circuit and a light receiving element arranged in the primary side circuit. Feedback circuit 40 supplies a current corresponding to the secondary-side voltage V _S to the light-emitting element of the photocoupler 41. The feedback circuit 40, to those that secondary voltage V _S may be input, the voltage V _{B (see} FIG. 2) may be inputted is the partial pressure of the secondary-side voltage V _S. The primary side control circuit 10B is connected to the light receiving element of the photocoupler 41, and the feedback voltage V _FB corresponding to the feedback current I _FB flowing through the light receiving element of the photocoupler 41 is input to the primary side control circuit 10B. The capacitor 12 is connected in parallel to the light receiving element of the photocoupler 41, and a feedback voltage V _FB is generated between both terminals of the capacitor 12.

At this time, reduces the feedback voltage _{V FB} with increasing feedback current _{I FB,} the feedback voltage _{V FB} rises with a decrease of the feedback current _{I FB.} For example, the primary side control circuit 10B is provided with a current source (not shown) that supplies a constant current to a parallel circuit of the capacitor 12 and the light receiving element of the photocoupler 41. Then, as the feedback current I _FB increases, the feedback voltage V _FB decreases, and as the feedback current I _FB decreases, the feedback voltage V _FB increases (however, the feedback voltage V _FB is higher). There is a lower limit).

When the secondary-side voltage V _S with the reduction of the current consumption of the load LD is higher than the target voltage V _TG, the feedback circuit 40 increases the current supplied to the light emitting element of the photocoupler 41. Along with this, the feedback current I _FB increases and the feedback voltage V _FB decreases. Conversely, when the secondary-side voltage V _S with an increase in current consumption of the load LD is lower than the target voltage V _TG, the feedback circuit 40 decreases the current supplied to the light emitting element of the photocoupler 41. Along with this, the feedback current I _FB decreases and the feedback voltage V _FB rises.

In the second embodiment, the operation of FIG. 4 is modified as follows. In the second embodiment, the operations of steps STP5 and STP6 of FIG. 4 are not executed, and in step STP3 of FIG. 4, the primary side control circuit 10B performs a burst operation. Immediately after the start of the burst operation, the feedback voltage V _FB since the secondary-side voltage V _S is near 0V promptly reaches an upper limit voltage of the feedback voltage V _FB. Feedback voltage V _FB by secondary voltage V _S by executing a burst operation is increased to around the target voltage V _TG is lowered from the upper limit voltage of the, then, the primary-side control based on the feedback voltage V _FB is the primary It is executed by the control circuit 10. The secondary side control circuit 20B is activated in the process of secondary voltage V _S rises toward the target voltage V _TG by executing a burst operation. Hereinafter, in the second embodiment, the contents of the primary side control and the configuration for performing the primary side control will be described.

FIG. 13 is a partial configuration diagram of the primary side control circuit 10B, and FIG. 14 is a partial configuration diagram of the secondary side control circuit 20B.

As shown in FIG. 13, the primary side control circuit 10B includes a PWM control unit (control signal generation unit) 150, a drive unit 160, a primary side transmission unit 170, and a matching determination unit 180. As shown in FIG. 14, the secondary side control circuit 20B includes a secondary side receiving unit 250, a restoring unit 260, and a synchronous rectification driving unit 270. The matching determination unit 180 will be described later, and the functions and operations of the parts other than the matching determination unit 180 among the parts shown in FIGS. 13 and 14 will be described.

PWM control unit 150, based on the feedback voltage _{V FB} is an example of a feedback signal corresponding to the secondary-side voltage _{V S,} and generates a signal _{S PWM1.} The signal S _PWM1 in the second embodiment is a PWM signal for the switching transistor M1 like the signal S _PWM1 in the first embodiment. However, in the second embodiment, the signal S _PWM1 is an example of the original switching control signal, not the restoration switching control signal. The PWM control unit 150 outputs the generated signal S _PWM1 to the drive unit 160 and the primary side transmission unit 170.

The drive unit 160 switches the switching transistor M1 by generating a drive signal DRV based on the signal S _PWM1 from the PWM control unit 150.

The primary side transmission unit 170 outputs a signal based on the signal S _PWM1 generated by the PWM control unit 150 to the pulse transformer unit 30. With reference to FIG. 15, the flow of transmission of the signal based on the signal S _PWM1 from the primary side control circuit 10B to the secondary side control circuit 20B will be described. The pulse transformer unit 30 is provided with a pulse transformer 32 that enables signal transmission from the primary side control circuit 10B to the secondary side control circuit 20B. The pulse transformer 32 includes a primary winding 32_1 and a secondary winding 32_2 that are magnetically coupled while being insulated from each other. The primary winding 32_1 is arranged in the primary circuit and the secondary winding 32_2 is arranged in the secondary circuit.

The primary side transmission unit 170 outputs the transmission pulse signal TP1 as a transmission signal to the pulse transformer 32 based on the signal S _PWM1 . The output of the transmission pulse signal TP1 to the pulse transformer 32 specifically refers to supplying the transmission pulse signal TP1 to the primary winding 32_1 of the pulse transformer 32. Supplying the transmission pulse signal TP1 to the primary winding 32_1 of the pulse transformer 32 means that the pulsed voltage of the transmission pulse signal TP1 is supplied to the primary winding 32_1 to change the current flowing through the primary winding 32_1. It means to give, and as long as the current flowing through the primary winding 32_1 changes, the method of supplying the pulsed voltage is arbitrary. Due to the change in the current, a voltage is generated in the secondary winding 32_2.

The secondary reception unit 250 generates the reception pulse signal RP2 as a reception signal based on the voltage generated in the secondary winding 32_2 with the supply of the transmission pulse signal TP1. The secondary receiving unit 250 compares, for example, the magnitude of the voltage between both terminals of the secondary winding 32_2 with a predetermined determination voltage using a comparator, and the magnitude of the voltage between both terminals of the secondary winding 32_2 is large. When is equal to or higher than the determination voltage, one pulse signal is generated as the received pulse signal RP2. The secondary receiving unit 250 outputs the generated reception pulse signal RP2 to the restoring unit 260 (see FIG. 14).

The restoration unit 260 generates the signal S _PWM2 based on the reception pulse signal RP2 generated by the secondary reception unit 250. The signal S _{PWM2 according} to the second embodiment corresponds to a signal (restored switching control signal) obtained by restoring the signal S _PWM1 in the secondary side control circuit 20B. The signal S _PWM2 generated by the restoration unit 260 is sent to the synchronous rectification drive unit 270.

Synchronous drive unit 270, based on the signal _{S PWM2} provided from the restoration unit 260, the SR transistor M2 is turned off by high-level period of the signal _{S PWM2,} all or part of the low-level period of the signal _{S PWM2} The SR transistor M2 is turned on. The synchronous rectification drive unit 270 can turn on the SR transistor M2 by applying a high-level gate voltage to the SR transistor M2, and turns off the SR transistor M2 by applying a low-level gate voltage to the SR transistor M2. Can be in a state.

Specifically, the synchronous rectification drive unit 270 turns off the SR transistor M2 in the entire high level section of the signal S _PWM2 in order to avoid simultaneous on of the transistors M1 and M2. The synchronous rectification drive unit 270 may turn on the SR transistor M2 in the entire low level section of the signal S _PWM2 . Alternatively, the synchronous rectification drive unit 270 may turn on the SR transistor M2 only in a part of the low level section of the signal S _PWM2 . In this case, the synchronous rectification drive unit 270 turns on the SR transistor M2 in response to the occurrence of the down edge of the signal S _PWM2 , and the voltage _VA becomes equal to or higher than a predetermined negative turn-off determination voltage (for example, -10 mV). In response, the SR transistor M2 can be turned off.

FIG. 16 shows the relationship between the signal S _PWM1 , the transmission pulse signal TP1, the reception pulse signal RP2, the signal S _PWM2 , the state of the transistor M1, and the voltage _VDR ( _VA ) according to the second embodiment. Shown. Similar to the first embodiment, each of the signals S _PWM1 and S _PWM2 is a binarized signal having a high level or low level signal level. However, in the second embodiment, in the primary side control, PWM control for switching the transistor M1 at a predetermined PWM frequency is performed.

In the signal S _PWM1 , the generation interval of two up edges adjacent to each other is equal to the length of the PWM cycle corresponding to the reciprocal of the PWM frequency. Similar to the first embodiment, in the signal S _PWM1 (or signal S _PWM2 ), the section from the generation timing of one up edge to the generation timing of the next up edge corresponds to the unit control section. The length of each unit control section is equal to the length of the PWM cycle. When PWM control is performed, a plurality of unit control sections arranged in a time series are sequentially generated.

Primary transmission unit 170 at and the signal _{S PWM1} each time a rising edge in the signal _{S PWM1} is produced each time a falling edge occurs, the pulse transformer 32 outputs one of the transmission pulse signal TP1 (i.e. one The transmission pulse signal TP1 is supplied to the primary winding 32_1 of the pulse transformer 32). Therefore, the secondary receiver unit 250 at and the signal _{S PWM1} each time a rising edge in the signal _{S PWM1} is produced each time a falling edge occurs, one received pulse signal RP2 is generated sent to recovery section 260 Will be.

The restoration unit 260 switches the level of the signal S _PWM2 between the low level and the high level each time the reception pulse signal RP2 is received from the secondary reception unit 250. Here, it is assumed that the initial levels of the signals S _PWM1 and S _PWM2 at the start of the primary control are both low levels. Thus, the signal _{S PWM2} is a signal obtained by restoring the signal _{S PWM1,} has a waveform of the signal _{S PWM1} substantially the same waveform. Strictly speaking, the signal delay component only is the up-edge timing of the signal S _PWM2 from up-edge timing of the signal S _PWM1 is delayed, here (same for down edge timing) of the signal delay is ignored as is minute.

Driver 160, a transistor M1 by supplying a high-level drive signal DRV to the gate of the transistor M1 in high-level period of the signal _{S PWM1} is turned on, the drive signal DRV at the low level section of the low-level signal _{S PWM1} Is supplied to the gate of the transistor M1 to turn off the transistor M1. The voltage _{V DR} varies corresponding to the drain voltage of the SR transistor M2 in accordance with the state of the transistor M1 (see FIG. 16).

As described in the first embodiment, the high level section of the signal S _{PWM1 and} the high level section of the signal S _PWM2 correspond to the on control section, respectively, and the low level section of the signal S _{PWM1 and} the low level section of the signal S _PWM2. Corresponds to the off control section, respectively. Each unit control section corresponds to the sum of one on control section and one off control section. As described in the first embodiment, the on control section is the section in which the transistor M1 should be controlled in the on state (first section), and the off control section is the section in which the transistor M1 should be controlled in the off state (first section). 2 sections).

In PWM control, the on control section and the off control section are alternately designated by the signal S _PWM1 or S _PWM2 . However, in the primary side control circuit 10B, the on control section and the off control section are specified by the signal S _PWM1 (original switching control signal), and in the secondary side control circuit 20B, the on control section and the on control section and the off control section are specified by the signal S _PWM2 (restoration switching control signal). The off control section will be specified. Thus, the drive unit 160 in the primary-side control circuit 10B is a transistor M1 is turned on at specified by the signal _{S PWM1} ON control period (high-level period of the signal _{S PWM1),} is designated by the signal _{S PWM1} The transistor M1 is turned off in the off control section (low level section of the signal S _PWM1 ). On the other hand, synchronous rectification driver 270 in the secondary side control circuit 20B is the SR transistor M2 is turned off at specified by the signal _{S PWM2-on} control period (high-level period of the signal _{S PWM2),} the signal _{S PWM2} The SR transistor M2 is turned on in all or part of the off control section (low level section of the signal S _PWM2 ) specified in.

When the PWM control is performed in the primary side control circuit 10B, PWM control unit 150, so that the duty of the signal _{S PWM1} increases with increasing feedback voltage _{V FB,} signals with a decrease in the feedback voltage _{V FB} The signal S _PWM1 may be generated so that the duty of S _PWM1 is reduced. Signal _{S PWM1,} the current sense voltage _{V CS} may also be generated into account.

[Correction by matching judgment unit]
If a communication error or the like does not occur, the signal S _PWM2 accurately restores the signal S _PWM1 , but when a communication error or the like occurs, the waveform of the signal S _PWM2 may differ from the waveform of the signal S _PWM1. .. This phenomenon will be described with reference to FIG.

In FIG. 17, it is assumed that noise NP is generated around the pulse transformer 32 and reception pulse signal RP2 based on the noise NP is generated. The received pulse signal RP2 based on the noise NP is not a pulse signal based on the transmitted pulse signal TP1 and has nothing to do with the signal S _PWM2. However, when the received pulse signal RP2 based on the noise NP is generated, the signal S _PWM2 The level is reversed when viewed from the level of the signal S _PWM1 .

FIG. 17 shows various waveforms in the virtual configuration in which the matching determination unit 180 of FIG. 13 is not provided. In the virtual configuration, once the level of the signal S _PWM2 is reversed when viewed from the level of the signal S _PWM1 , After that, the reverse state will continue. As a result, synchronous rectification may not be performed correctly, and the switching transistor M1 may be in an overcurrent state.

In consideration of this, as shown in FIG. 13, a matching determination unit 180 is provided in the secondary side control circuit 20B. When the matching determination unit 180 executes the primary side matching determination process for determining the consistency (presence or absence of consistency) of the signals S _PWM1 and S _PWM2 , and determines that the signal S _PWM1 and the signal S _PWM2 are not matched. Execute the primary side correction process. The determination of the integrity of the signal _{S PWM1} and _{S PWM2,} refers to the determination signal _{S PWM1} and signal _{S PWM2} is whether consistent. The primary side correction process is executed only when it is determined that the signal S _PWM1 and the signal S _PWM2 do not match.

Significance of the signal _{S PWM1} and signal _{S PWM2} is consistent, and significance of the signal _{S PWM1} and signal _{S PWM2} do not match are as described in the first embodiment.

FIG. 18 shows an example of various signals and voltage waveforms in the configuration of the present embodiment provided with the matching determination unit 180.

In the primary side correction process, the matching determination unit 180 outputs a predetermined correction instruction signal to the primary side transmission unit 170. The primary side transmitting unit 170 that has received the correction instruction signal outputs the correction pulse signal TP1_C as the correction signal regardless of the signal S _PWM1 (see FIG. 18). That is, it can be said that in the primary side correction process, the matching determination unit 180 uses the primary side transmission unit 170 to output the correction pulse signal TP1_C to the pulse transformer 32. The output of the correction pulse signal TP1_C to the pulse transformer 32 specifically refers to supplying the correction pulse signal TP1_C to the primary winding 32_1 of the pulse transformer 32. Supplying the correction pulse signal TP1_C to the primary winding 32_1 of the pulse transformer 32 means that the pulsed voltage of the correction pulse signal TP1_C is supplied to the primary winding 32_1 to change the current flowing through the primary winding 32_1. It means to give, and as long as the current flowing through the primary winding 32_1 changes, the method of supplying the pulsed voltage is arbitrary. Due to the change in the current, a voltage is generated in the secondary winding 32_2. The correction pulse signal TP1_C may be a pulse-shaped signal having the same waveform as the transmission pulse signal TP1 based on the signal S _PWM1 .

As a result, the primary side transmitter 170 performs the transition timing from the off control section to the on control section and the transition timing from the on control section to the off control section specified by the signal S _PWM1 (original switching control signal), respectively. The transmission pulse signal TP1 (transmission signal) is supplied to the primary winding 32_1 of the pulse transformer 32 (communication transformer) (at each of the up edge timing and the down edge timing of the signal S _PWM1 ), and separately, the signal S _PWM2 When it is determined that the (restored switching control signal) does not match the signal S _PWM1 (original switching control signal), the correction pulse signal TP1_C (correction signal) is supplied to the primary winding 32_1 of the pulse transformer 32. ..

The secondary side receiving unit 250 generates the received pulse signal RP2 based on the voltage generated in the secondary side winding 32_2 with the supply of the correction pulse signal TP1_C (see FIG. 18). Therefore, the secondary receiving unit 250 receives the correction pulse signal TP1_C based on the primary side correction processing even when the transmission pulse signal TP1 based on the signal S _PWM1 is supplied to the primary winding 32_1 of the pulse transformer 32. Even when it is supplied, the received pulse signal RP2 is generated based on the voltage generated in the secondary winding 32_2 of the pulse transformer 32.

The restoration unit 260 does not distinguish (without recognizing) whether the reception pulse signal RP2 provided from the secondary reception unit 250 is based on the transmission pulse signal TP1 or the correction pulse signal TP1_C. switch between level low level and a high level signal S _PWM2 each time receiving the signal RP2, switches the interval specified words by the signal S _PWM2 between an on control section and the off control section. As a result, the consistency between the signal S _PWM1 and the signal S _PWM2 , which had been temporarily collapsed, is ensured again.

As described above, in the present embodiment, even if a communication abnormality occurs, it is possible to self-recover. That is, for example, even if a phenomenon occurs in which the level of the signal S _PWM2 is reversed when viewed from the level of the signal S _PWM1 based on the generation of noise NP, the phenomenon remains temporary and quickly returns to the normal control state. Can be made to. Although noise was focused on as a factor of the level reversal phenomenon between the signals S _PWM1 and S _PWM2 , the same phenomenon occurs due to the transmission failure of the pulse signal that should be originally transmitted, and the configuration of the present embodiment is also in this case. Works effectively.

The primary side matching determination process by the matching determination unit 180 will be described. Matching determination unit 180 can determine the current flowing through the primary winding W1 and the switching transistor M1, that is, based on the primary-side current _{I P,} signal integrity _{S PWM1} and _{S PWM2} to (whether integrity) .. When the signal S _PWM1 and the signal S _PWM2 do not match, the transistors M1 and M2 are turned on at the same time, but when the transistors M1 and M2 are turned on at the same time, a considerably large current flows through the transistor M1. .. The matching determination unit 180 determines that the signal S _PWM2 does not match the signal S _PWM1 when a predetermined mismatch condition is satisfied, and otherwise determines that the signal S _PWM2 matches the signal S _PWM1. To do.

Specifically, for example, matching determination section 180 refers to the current sense voltage V _CS corresponding to the primary-side current I _P, the high-level period of the signal S _PWM1, the predetermined threshold voltage or more current sense voltage V _CS When it is observed, it is judged that the inconsistency condition is satisfied. A current sense voltage V _CS is greater than or equal to a predetermined threshold voltage is equivalent to the primary-side current I _P with a predetermined value or more magnitude flows. In order to eliminate the influence of the surge voltage due to switching, the success or failure of the mismatch condition is not determined until a predetermined mask time elapses from the up edge timing of the signal S _PWM1 , and the mismatch condition is determined only after the mask time elapses. You may decide the success or failure of.

<< Third Embodiment >>
A third embodiment of the present invention will be described. AC / DC converters insulating synchronization as DC / DC converter 4 included in the first rectification type DC / DC converter configured to have been described above, the DC / DC converter 4, the switching from the primary voltage _{V P} applied to the primary winding W1 it is arbitrary as long as the insulation type DC / DC converter for generating a secondary voltage V _S at the secondary side of the transformer TR by scheme.

For example, in the DC / DC converter 4 shown in FIG. 2, a so-called low-side application is adopted, but a high-side application may be adopted. In the high-side application adopted DC / DC converter 4, is provided to the SR transistor M2 is connected to the output terminal _{TM 2H} side, a secondary winding W2 of the output terminal _{TM 2H} and the transformer TR to the secondary-side voltage _{V S} is applied The SR transistor M2 is inserted in series between the two. In addition, it is possible to change the arrangement position of the SR transistor M2 in the secondary circuit without impairing the gist of the present invention.

Further, for example, the DC / DC converter 4 may be a DC / DC converter (insulated diode rectification type DC / DC converter) adopting a diode rectification method (however, the second embodiment is excluded). In this case, in the DC / DC converter 4, a rectifier diode is provided in the secondary circuit instead of the SR transistor M2 and the parasitic diode D2 in FIG. The rectifying diode is inserted between the secondary winding W2 and the capacitor C2, and rectifies the electric power propagated from the primary winding W1 to the secondary winding W2.

Further, for example, the DC / DC converter 4 may be configured as a forward-type isolated DC / DC converter, and in this case, either a synchronous rectification method or a diode rectification method may be adopted.

<< Fourth Embodiment >>
A fourth embodiment of the present invention will be described.

The power adapter may be configured by using the AC / DC converter 1. FIG. 19 is a diagram showing a power adapter 620 including an AC / DC converter 1. The power adapter 620 includes an AC / DC converter 1, a plug 621, a housing 622, and an output connector 623, and the AC / DC converter 1 is housed and arranged in the housing 622. Plug 621 receives a commercial AC voltage _{V AC} from a not shown outlet, AC / DC converter 1 generates a secondary-side voltage _{V S} of the DC from the commercial AC voltage _{V AC} input via the plug 621. Secondary voltage V _S is, through the output connector 623, is supplied to any electrical equipment which is not shown. Examples of electric devices include notebook personal computers, information terminals, digital cameras, digital video cameras, mobile phones (including those classified as smartphones), and portable audio players.

An electric device including the AC / DC converter 1 may be configured. 20 (a) and 20 (b) are diagrams showing an electric device 640 including an AC / DC converter 1. The electric device 640 shown in FIGS. 20 (a) and 20 (b) is a display device, but the type of the electric device 640 is not particularly limited, and an AC / DC converter such as an audio device, a refrigerator, a washing machine, and a vacuum cleaner can be used. Any built-in device is acceptable. The electrical device 640 includes an AC / DC converter 1, a plug 641, a housing 642, and a load 643, and the AC / DC converter 1 and the load 643 are housed and arranged in the housing 642. Plug 641 receives a commercial AC voltage _{V AC} from a not shown outlet, AC / DC converter 1 generates a secondary-side voltage _{V S} of the DC from the commercial AC voltage _{V AC} input via the plug 641. The generated secondary voltage V _S is supplied to the load 643. The load 643 corresponds to the load LD in FIG. Load 643 may be any load driven on the basis of the secondary voltage V _S, for example, a microcomputer computer, DSP (Digital Signal Processor), a power supply circuit, the lighting device, an analog circuit or a digital circuit.

<< Fifth Embodiment >>
A fifth embodiment of the present invention will be described. In the fifth embodiment, applied techniques, deformation techniques, and the like applicable to the first to fourth embodiments will be described.

Although it has been described above that the DC / DC converter 4 is used as a component of the AC / DC converter 1, the present invention is not limited thereto. That is, for example, DC / DC converter 4 receives any voltage source for generating a DC voltage the output voltage (e.g., a battery) as the primary-side voltage V _P, even those that generate secondary voltage V _S I do not care.

The above-mentioned signals S _PWM1 and S _PWM2 are examples of switching control signals. As the switching control for the transistor M1, PWM control for switching the transistor M1 at a predetermined PWM frequency has been exemplified, but the present invention is not limited thereto. That is, for example, the transistor M1 may be switched by PFM (Pulse Frequency Modulation) control using an on-time control method. In this case, through the variable adjustment of the frequency of the switching control signal _{S PWM1} and _{S PWM2,} stabilization of the target voltage _{V TG} of the secondary-side voltage _{V S} is achieved.

The semiconductor device SMC1 in which the primary side control circuit 10, the secondary side control circuit 20, and the pulse transformer unit 30 are integrated on a semiconductor substrate of one chip may be configured. A one-chip semiconductor substrate in which a primary side control circuit 10, a secondary side control circuit 20, and a pulse transformer unit 30 are integrated is housed in a package (housing) made of resin and sealed to form a semiconductor. The device SMC1 is configured.

Alternatively, the first chip in which the primary side control circuit 10 is integrated on the first semiconductor substrate, the second chip in which the secondary side control circuit 20 is integrated on the second semiconductor substrate, and the pulse transformer unit 30 are third. The semiconductor device SMC2 may be configured by creating a third chip integrated on a semiconductor substrate, accommodating the first to third chips in a common package (housing), and sealing the chips.

However, the primary side control circuit 10 and the secondary side control circuit 20 may be configured as separate semiconductor devices. That is, the primary-side control circuit 10 of the first chip and the semiconductor device SMC3 _A by sealing housed in a first package integrated on the first semiconductor substrate, separately from the secondary side control to this The semiconductor device SMC3 _B may be configured by accommodating and sealing the second chip in which the circuit 20 is integrated on the second semiconductor substrate in the second package. In this case, the pulse transformer unit 30 may be a discrete component provided separately from the semiconductor devices SMC3 _A and SMC3 _B , but the third chip in which the pulse transformer unit 30 is integrated on the third semiconductor substrate is a third. The semiconductor device SMC3 _C may be configured by housing it in a package and sealing it. In the semiconductor device SM1, SMC2 and SMC3 _C, it is possible to utilize the existing integrated circuit process, constituting the pulse transformer.

A semiconductor device in which the primary-side control circuit 10 are integrated (SM1, SMC2 or SMC3 _A), to the switching transistor M1 may be included to further integration, including the sense resistor R _CS is further integrated It may be.

The SR transistor M2 may be further integrated and included in the semiconductor device (SM1, SMC2 or SMC3 _B ) in which the secondary side control circuit 20 is integrated, or the partial pressure resistors R1 and R2 are further integrated. The voltage dividing resistors R3 and R4 may be further integrated and included.

The relationship between the high level and the low level of any signal or voltage may be reversed without compromising the above-mentioned gist. Further, the channel type of the FET can be arbitrarily changed without impairing the above-mentioned purpose. That is, for example, the configuration of the DC / DC converter 4 may be modified so that the switching transistor M1 is configured as a P-channel MOSFET.

The above-mentioned arbitrary transistor may be any kind of transistor. For example, any transistor described above as a MOSFET (particularly, switching transistor M1) can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor. Any transistor has a first electrode, a second electrode and a control electrode. In the FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In the IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is the base.

The embodiments of the present invention can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present invention, and the meanings of the terms of the present invention and the respective constituent requirements are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

1 AC / DC converter 2 Filter 3 Rectifier circuit 4 DC / DC converter 10 Primary side control circuit 20 Secondary side control circuit 30 Pulse transformer part M1 Switching transistor M2 Synchronous rectifier transistor TR Transformer W1 Primary side winding W2 Secondary side winding 20A Secondary side control circuit 210 PWM control unit (control signal generation unit)
220 Secondary side transmitter 230 Matching judgment unit 10A Primary side control circuit 110 Primary side receiver 120 Restoration unit 130 Drive unit 31 Pulse transformer (communication transformer)
10B Primary side control circuit 150 PWM control unit (control signal generation unit)
160 Drive unit 170 Primary side transmitter 180 Matching judgment unit 20B Secondary side control circuit 250 Secondary side receiver 260 Restoration unit 270 Synchronous rectification drive unit

Claims (10)

By switching the switching transistor connected to the primary winding of the power transformer while insulating the primary side and the secondary side of the power transformer from each other, the voltage on the primary side on the primary side is changed to the secondary on the secondary side. In an isolated DC / DC converter that generates side voltage
A primary side control circuit arranged on the primary side and driving the switching transistor,
The secondary side control circuit located on the secondary side and
A communication transformer that realizes signal transmission from the secondary side control circuit to the primary side control circuit is provided.
The secondary side control circuit has a control signal generation unit that generates an original switching control signal for the switching transistor based on the secondary side voltage, and a transmission signal based on the original switching control signal as a secondary of the communication transformer. Has a secondary side transmitter, which supplies to the side winding,
The primary side control circuit has a primary side receiving unit that generates a received signal based on a voltage generated in the primary side winding of the communication transistor, and a restored switching control that restores the original switching control signal based on the received signal. It has a restoration unit that generates a signal and a drive unit that switches the switching transistor based on the restoration switching control signal.
The secondary side control circuit further includes a matching determination unit for determining the consistency between the original switching control signal and the restored switching control signal, and the restored switching control signal is not matched with the original switching control signal. When it is determined, the restoration switching control signal is matched with the original switching control signal by supplying the correction signal to the secondary winding of the communication transformer using the secondary side transmitter. Insulated DC / DC converter. In the secondary side control circuit, the primary switching control signal alternately designates a first section in which the switching transistor should be controlled in the on state and a second section in which the switching transistor should be controlled in the off state.
In the primary side control circuit, the first section and the second section are alternately designated by the restoration switching control signal.
The drive unit turns the switching transistor on in the first section designated by the restoration switching control signal, and turns the switching transistor on in the second section designated by the restoration switching control signal. ,
The secondary side transmitting unit transmits the transmission at each of the transition timing from the second section to the first section and the transition timing from the first section to the second section specified by the original switching control signal. When the signal is supplied to the secondary winding of the communication transformer and it is determined that the restoration switching control signal does not match the original switching control signal, the correction signal is used as the secondary winding of the communication transformer. Supply to the side winding,
The primary reception unit generates the reception signal based on the voltage generated in the primary winding of the communication transformer by supplying the transmission signal or the correction signal to the secondary winding of the communication transformer. ,
The restoration unit is characterized in that each time the reception signal is generated by the primary reception unit, the section designated by the restoration switching control signal is switched between the first section and the second section. The isolated DC / DC converter according to claim 1. A voltage that fluctuates in response to switching of the switching transistor is generated at one terminal of the secondary winding of the power transformer.
Claim 1 or claim 1, wherein the matching determination unit determines the consistency between the original switching control signal and the restoration switching control signal based on the original switching control signal and the voltage at one of the terminals. 2. The isolated DC / DC converter according to 2. The matching determination unit determines the consistency between the original switching control signal and the restoration switching control signal based on the original switching control signal and the secondary current flowing in the secondary winding of the power transformer. The isolated DC / DC converter according to claim 1 or 2. By switching the switching transistor connected to the primary winding of the power transformer while insulating the primary side and the secondary side of the power transformer from each other, the voltage on the primary side on the primary side is changed to the secondary on the secondary side. In an isolated DC / DC converter that generates side voltage
A primary side control circuit arranged on the primary side and driving the switching transistor,
A secondary side control circuit arranged on the secondary side and driving a synchronous rectifier transistor connected to the secondary side winding of the power transformer.
A communication transformer that realizes signal transmission from the primary side control circuit to the secondary side control circuit is provided, and power conversion is performed by a synchronous rectification method.
The primary side control circuit switches between a control signal generator that generates an original switching control signal for the switching transistor based on a feedback signal corresponding to the secondary side voltage and the switching transistor based on the original switching control signal. It has a drive unit and a primary side transmission unit that supplies a transmission signal based on the original switching control signal to the primary side winding of the communication transistor.
The secondary side control circuit restores the secondary side receiving unit that generates a received signal based on the voltage generated in the secondary winding of the communication transformer, and the original switching control signal based on the received signal. It has a restoration unit that generates a restoration switching control signal, and a synchronous rectification drive unit that switches the synchronous rectification transistor based on the restoration switching control signal.
The primary side control circuit further includes a matching determination unit for determining the consistency between the original switching control signal and the restored switching control signal, and the restored switching control signal is not matched with the original switching control signal. When it is determined, the isolated type is characterized in that the restoration switching control signal is matched with the original switching control signal by supplying a correction signal to the primary winding of the communication transformer by using the primary side transmitter. DC / DC converter. In the primary side control circuit, the original switching control signal alternately designates a first section in which the switching transistor should be controlled in the on state and a second section in which the switching transistor should be controlled in the off state.
The drive unit turns the switching transistor on in the first section designated by the original switching control signal, and turns the switching transistor off in the second section designated by the original switching control signal. ,
In the secondary side control circuit, the first section and the second section are alternately designated by the restoration switching control signal.
The synchronous rectification drive unit turns off the synchronous rectification transistor in the first section designated by the restoration switching control signal, and all or a part of the second section designated by the restoration switching control signal. With the synchronous rectifier transistor turned on,
The primary side transmitting unit receives the transmission signal at each of the transition timing from the second section to the first section and the transition timing from the first section to the second section specified by the original switching control signal. Is supplied to the primary winding of the communication transformer, and when it is determined that the restoration switching control signal does not match the original switching control signal, the correction signal is sent to the primary winding of the communication transformer. Supply to
The secondary receiving unit generates the received signal based on the voltage generated in the secondary winding of the communication transformer by supplying the transmission signal or the correction signal to the primary winding of the communication transformer. And
The restoration unit is characterized in that each time the reception signal is generated by the secondary reception unit, the section designated by the restoration switching control signal is switched between the first section and the second section. The isolated DC / DC converter according to claim 5. 5. The matching determination unit is characterized in that it determines the consistency between the original switching control signal and the restoration switching control signal based on the primary side current flowing through the primary winding of the power transformer. Or the isolated DC / DC converter according to 6. A rectifier circuit that full-wave rectifies AC voltage,
A smoothing capacitor that generates a DC voltage by smoothing a full-wave rectified voltage,
The AC characterized by comprising the isolated DC / DC converter according to any one of claims 1 to 7, which generates a DC secondary side voltage as an output voltage from the primary side voltage as the DC voltage. / DC converter. A plug that receives AC voltage and
The AC / DC converter according to claim 8 and
A power adapter including a housing for accommodating the AC / DC converter. The AC / DC converter according to claim 8 and
An electric device including a load driven based on the output voltage of the AC / DC converter.

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