JP2020190867A - Configuration changeable integrated circuit allocation system, configuration changeable integrated circuit allocation method and computer program - Google Patents

Abstract

To provide a configuration changeable integrated circuit allocation system that efficiently runs application programs using a configuration changeable integrated circuit.SOLUTION: A configuration changeable integrated circuit allocation system 10 with multiple virtual environments 105 for running application programs, comprises: a plurality of configuration changeable integrated circuits 104 that can be reconfigured; a queuing processing unit 111 that allocates predetermined processing of the application program instructed by a predetermined virtual environment among the multiple virtual environments for the predetermined configuration changeable integrated circuit among the plurality of configuration changeable integrated circuits; an allocation processing unit 112 that allocates the predetermined configuration changeable integrated circuit to the predetermined virtual environment; and a logic change processing unit 113 that changes the configuration of the predetermined configuration changeable integrated circuit.SELECTED DRAWING: Figure 1

Description

The present invention relates to a configuration change type integrated circuit allocation system, a configuration change type integrated circuit allocation method, and a computer program.

A service provider that provides various information processing services on a so-called cloud computer builds an execution environment for an application program (hereinafter, may be abbreviated as an application) that executes machine learning or data analysis, thereby providing a cloud service. To customers. In cloud services, it has been considered to speed up application processing by using a configurable integrated circuit (hereinafter, sometimes referred to as FPGA (Field-Programmable Gate Array)) or GPU (Graphics Processing Unit). ing. Since hardware resources such as FPGA and GPU are limited, service providers are required to control sharing FPGA and GPU among execution environments of a plurality of applications.

The computing device of Patent Document 1 has a GPU scheduler that schedules GPU commands based on a dynamically selected scheduling policy. The GPU scheduler receives GPU commands from different virtual machines, dynamically selects a scheduling policy, and schedules GPU commands to be processed by the GPU.

Special Table 2017-522655

The computing device of Patent Document 1 shares the GPU among a plurality of virtual machines by switching the scheduling policy. However, when the FPGA is shared for each execution environment, the time (overhead) required for the configuration change when switching the FPGA between the execution environments is generated.

Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to efficiently execute the processing of an application program by allocating a configuration-modifying integrated circuit.

The configuration change type integrated circuit allocation system is provided with a plurality of virtualized environments for executing application programs, and is composed of a plurality of configuration changeable integrated circuits and a predetermined configuration change type among a plurality of configuration change type integrated circuits. A queuing processing unit that assigns a predetermined process of an application program instructed by a predetermined virtual environment among a plurality of virtualized environments to an integrated circuit, and a predetermined configuration-changeable integrated circuit in the predetermined virtual environment. It has an allocation processing unit for allocating and a logic change processing unit for changing the configuration of a predetermined configuration change type integrated circuit.

According to the present invention, it is possible to efficiently execute the processing of the application program by using the configuration-modifying integrated circuit.

The schematic diagram of the management server of this embodiment. Schematic diagram of the management server hardware configuration. Explanatory diagram of the task list storage unit. Flow diagram of the queuing processing unit. Explanatory drawing of the task queue storage part. Explanatory diagram of task execution time. Explanatory diagram of priority information. Flow chart of the allocation processing unit. The schematic diagram of the management server which concerns on 2nd Example. Flow chart of schedule generation process. Explanatory diagram of the system operation history storage unit. Explanatory diagram of logic application schedule.

Hereinafter, this embodiment will be described with reference to the accompanying drawings, but the present invention is not limited to the configuration described in the drawings.

The present embodiment relates to a configuration changeable integrated circuit allocation system that efficiently executes an application program by allocating a configuration changeable integrated circuit to a virtual environment. Therefore, in the present embodiment, the tasks of the application are dynamically assigned in consideration of the time related to the configuration change of the FPGA. The tasks of the application are processed by the FPGA in separate containers. In the embodiment shown below, the configuration change type integrated circuit allocation system may be referred to as a management server.

FIG. 1 is a schematic view of the management server 10 of this embodiment. The management server 10 includes a plurality of containers 105 as an example of the “virtualized environment” and executes the application program 50 (see FIG. 2). The application program 50 may be abbreviated as application 50.

The management server 10 is connected to the operation terminals 20 (1) and 20 (2) via the communication network 30. The operation terminals 20 (1) and 20 (2) may be referred to as an operation terminal 20 unless otherwise specified.

When the user operates the operation terminal 20, a control signal for executing the application 50 is transmitted to the management server 10 via the communication network 30. The management server 10 that receives the control signal executes the application 50. The management server 10 transmits the execution result to the operation terminal 20 via the communication network 30.

The management server 10 includes, for example, a plurality of FPGA 104s as an example of "a plurality of configuration-changing integrated circuits", a plurality of containers 105, a queuing processing unit 111, an allocation processing unit 112, and a logic change processing unit 113. , A task list storage unit 121, a task queue storage unit 122, and a logic storage unit 123. The task list storage unit 121, the task queue storage unit 122, and the logic storage unit 123 shown in FIG. 1 are shown by omitting the description of the “storage unit”.

The container 105 provides an environment in which the computer resources of the management server 10 can be virtually divided and applications 50 can be processed in parallel with each other. For example, the container 105 is configured by using a virtual machine or a container technology. Will be done. The virtual machine represents, for example, the virtual hardware resources of the management server 10 set by the hypervisor-type virtualization software. The container technology shows, for example, the virtual hardware resources of the management server 10 set by the container-type virtualization software. The container-type virtualization software sets a plurality of virtual hardware resources of each independent management server 10 on one OS (Operating System).

The container 105 calculates information on the processing of the application 50 (hereinafter, may be referred to as a task) by, for example, the user operating the application 50 using the operation terminal 20. The queuing processing unit 111 acquires task information from the container 105.

The queuing processing unit 111 stores task information in the task list storage unit 121. The queuing processing unit 111 is a program that assigns tasks to each FPGA 104, as described in detail in FIG. The queuing processing unit 111 communicates bidirectionally with the task queue storage unit 122 and stores the allocation result in the task queue storage unit 122.

As described in detail in FIG. 5, the task queue storage unit 122 is a database that stores information on tasks assigned to each FPGA 104. The allocation processing unit 112 is a program that mounts the FPGA 104 on the container 105.

The allocation processing unit 112 acquires the allocation result of the queuing processing unit 111 from the task queue storage unit 122. The allocation processing unit 112 acquires the information of the container 105 from the task list storage unit 121. The allocation processing unit 112 acquires the state of the FPGA 104. Examples of the state of the FPGA 104 include a state in which the FPGA 104 executes a task, a state in which the configuration of the FPGA 104 is changed, a state in which the FPGA 104 is in standby, and the like. The allocation processing unit 112 executes the logic change processing unit 113 when changing the configuration of the FPGA 104.

The logic change processing unit 113 is a program that changes the configuration of the FPGA 104. The logic change processing unit 113 acquires the information of the FPGA 104 to be changed and the information of the logic applied to the FPGA 104 from the allocation processing unit 112. The logic change processing unit 113 acquires logic information from the logic storage unit 123.

FIG. 2 is a schematic diagram of the hardware configuration of the management server 10. The management server 10 communicates with, for example, the processor 101, the auxiliary storage device 102, the memory 103, the FPGA 104, the input / output device 106, the communication interface 107, and the devices 101-104, 106, 107 in both directions. It has a data transmission line 108 and a data transmission line 108 which can be connected to each other.

The processor 101 is, for example, a "CPU (Central Processing Unit)". The processor 101 realizes each function by reading the programs 111 to 113 or the application 50 from the auxiliary storage device 102 into the memory 103 and executing the programs.

The auxiliary storage device 102 is, for example, a hard disk or a non-volatile storage device such as an SSD (Solid State Drive). The auxiliary storage device 102 stores, for example, the programs of the queuing processing unit 111, the allocation processing unit 112, the logic change processing unit 113, and the application 50.

The auxiliary storage device 102 has, for example, a database of a task list storage unit 121, a task queue storage unit 122, and a logic storage unit 123. In each database shown in FIG. 2, the description of the “storage unit” is omitted. Application 50 refers to software created for a particular purpose, such as, for example, a "machine learning SDK (Soft Development Kit)".

At least a part of each program 111-113, application 50, or each database 121-123 may be installed on the management server 10 via the external recording medium 40. The external recording medium 40 is, for example, an IC (Integrated Circuit) card, an SD (Secure Digital) card, a DVD (Digital Versaille Disc), a Blu-ray Disc, another optical disk, or a USB (Universal Serial Bus) memory.

The programs 111 to 113, the applications 50, or the databases 121 to 123 are not limited to being stored in the same external storage medium 40, but may be stored in a plurality of external storage media 40, respectively. The memory 103 is, for example, a volatile storage device such as “RAM (Random Access Memory)”.

The input / output device 106 is, for example, a display, a keyboard, a pointer device, a mobile information terminal (tablet terminal, smartphone, etc.). At least a part of the management server 10 may be operated by voice. The communication interface 107 (may be referred to as a communication I / F in the figure) is, for example, a LAN (Local Area Network) connection terminal, a SAN (Storage Area Network) connection terminal, or a wireless communication connection device. The communication interface 107 is connected to the operation terminal 20 by wireless communication via, for example, the communication network 30. The communication interface 107 may be connected to the operation terminal 20 by wire communication.

The operation terminal 20 is a computer in which the user operates the application 50. A different operation terminal 20 may be connected to the management server 10 for each user of the application 50. The management server 10 is not limited to the two operation terminals 20 (1) and 20 (2), and three or more operation terminals 20 may be connected.

The input / output device 201 is a device operated by the user, and includes, for example, a display and a keyboard. The operation terminal 20 transmits the data input to the input / output device 201 by the user to the management server 10 via the communication network 30. The operation terminal 20 can also receive the data transmitted from the management server 10 via the communication network 30 and display it on the input / output device 201.

FIG. 3 is an explanatory diagram of the task list storage unit 121. The task list storage unit 121 stores the task information transmitted from each container 105. For example, a task ID (IDentification) 1211, a logic ID 1212, and a container ID 1213 are stored in the task list storage unit 121.

The task identification information is stored in the task ID 1211. Specifically, for example, "task_01" to "task_12" are indicated in the task ID 1211. The task ID 1211 is transmitted from each container 105 in the order of "task_01" to "task_12".

The logic ID 1212 stores the logic identification information of the FPGA 104. In the logic ID 1212, for example, "determination process_01", "model generation_01", "model generation_02", "SQL (Structured Quality Language) _Drill_01", and "SQL_Impara_01" are indicated.

The container ID 1213 stores the identification information of the container 105 that has transmitted the task to the task list storage unit 121. The container ID 1213 indicates, for example, "container _01" to "container _12" and identification information of each container 105.

When the container 105 completes the task processing, the management server 10 may delete the corresponding task information 121 to 1213 from the task list storage unit 121.

In the case of explaining the function of the queuing process 111, the "task_12" newly calculated by the "container_12" as an example of the "predetermined container" will be described as an example of the "predetermined task".

The queuing processing unit 111 is executed by the "container_12" calculating the "task_12". The queuing processing unit 111 stores the information of "task_12" in the task list storage unit 121.

FIG. 4 is a flow chart of the queuing processing unit 111. The queuing processing unit 111 refers to the task list storage unit 121 and the task queue storage unit 122, and selects the first FPGA as an example of the “first configuration change type integrated circuit” (S11). Before explaining the method of selecting the first FPGA, the task queue storage unit 122 will be described.

FIG. 5 is an explanatory diagram of the task queue storage unit 122. The task queue storage unit 122 has FPGA information (may be indicated as FPGA_ID in the figure) 1221 and task queues 1222_01 to 1222_N (N = arbitrary number). The task queues 1222_01 to 1222_N may be referred to as task queue 1222 unless otherwise specified.

The identification information of the FPGA 104 is stored in the FPGA information 1221. For example, "FPGA_01" to "FPGA_08" are shown in the FPGA information 1221.

In the task queue 1222, for example, the task ID 1211 is stored in a FIFO (First In First Out) structure. That is, the task ID 1211 is stored in the order of task queue 1222_01 to task queue 1222_N.

The task ID 1211 stored in the task queue 1222_01 is executed in, for example, the container 105. When the processing of the task ID 1211 stored in the task queue 1222_01 is completed, the task ID 1211 stored in the task queue 1222_02 moves to the task queue 1222_01 having the same FPGA information 1221.

The task queue 1222 may be added or deleted depending on the number of assigned tasks. That is, the arbitrary number N is not limited to a constant value, and may be a variable that is increased or decreased depending on the number of assigned tasks.

A method of selecting the first FPGA of the queuing processing unit 111 will be described. FIG. 6 is an explanatory diagram of a task execution time in each FPGA 104. A method of selecting the first FPGA of the queuing processing unit 111 will be described by taking "FPGA_01", "FPGA_02", and "FPGA_04" as an example from each FPGA 104.

In "FPGA_01", "task_01" is stored in the task queue 1222_01. In "FPGA_02", "task_02" and "task_09" are stored in the task queue 1222_01 and the task queue 1222_02. In "FPGA_04", "task_04" and "task_10" are stored in the task queue 1222_01 and the task queue 1222_02.

The execution time of "task_01" to "task_12" may be set by the user. The execution time of "task_01" to "task_12" may be calculated from the information of the actual results of the container 105 executing each task.

Specifically, the execution time of "task_01" to "task_12" is set to, for example, "40 seconds". The execution time of "task_01" to "task_12" is not limited to being set uniformly, and the execution time may be set for each task ID 1211.

The configuration change time 60 of the FPGA 104 may be set by the user. The configuration change time 60 of the FPGA 104 may be calculated from the actual result of the configuration change of the FPGA 104. The configuration change time 60 of the new logic ID 1212 may be calculated from the configuration change time 60 of the proven logic ID 1212 based on the proportion of the new logic occupying the area of the FPGA 104. The area of the proven logic ID 1212 is similar to the area of the new logic.

Specifically, the configuration change time 60 of the FPGA 104 is set to, for example, "50 seconds". The configuration change time 60 is not limited to being set uniformly, and may be set for each task ID 1211 based on the logic ID 1212 after the configuration change.

When the task is being executed, the queuing processing unit 111 calculates the remaining time of the execution times of "task_01" to "task_12". When the configuration change of the FPGA 104 is in progress, the queuing processing unit 111 calculates the remaining time of the configuration change time 60.

The queuing processing unit 111 calculates the total time of the task execution time and the configuration change time 60 for each of "FPGA_01", "FPGA_02", and "FPGA_04". That is, the queuing processing unit 111 calculates the total time of the task execution time and the configuration change time 60 for each FPGA 104.

The total time of "FPGA_01" is, for example, "40 seconds" which is the execution time of "task_01". Since the number of tasks of "FPGA_03" and "FPGA_06" to "FPGA_08" is "1" as in "FPGA_01", the execution time is "40 seconds".

The total time of "FPGA_02" is, for example, "80 seconds" which is the execution time of "task_02" and "task_09". As with "FPGA_02", the logic ID 1212 of "task_05" and "task_11" of "FPGA_05" is the same, so that the total time is "80 seconds".

Since the logic ID 1212 of "task_04" and "task_10" is different, the total time of "FPGA_04" includes the configuration change time 60. As a result, the total time of "FPGA_04" is, for example, "130 seconds", which is the total of the execution time of "task_04" and "task_10" and the configuration change time 60.

In this embodiment, the total time of each FPGA 10 may include the processing time of each program 111 to 113, the standby time of FPGA 104, and the like.

See FIG. For example, the queuing processing unit 111 selects "FPGA_01", "FPGA_03", "FPGA_06" to "FPGA_08" having an execution time of "40 seconds" as the first FPGA (S11). That is, the queuing processing unit 111 selects, for example, the first FPGA having the short total time of each FPGA 104.

The queuing processing unit 111 moves to the processing (S12). The queuing processing unit 111 acquires the logic ID 1212 of "task_12" from the task list storage unit 121. The logic ID 1212 of "task_12" is, for example, "model generation_02".

The queuing processing unit 111 refers to the task queue storage unit 122 to acquire the task ID 1211 at the end of the task queue 1222 of each first FPGA. The task ID 1211 at the end indicates, for example, the task ID in which the process is executed last among the task IDs stored in the task queue 1222 in each FPGA information 1221.

The queuing processing unit 111 refers to the task list storage unit 121 and acquires the value of the logic ID 1212 of each first FPGA based on the task ID 1211 at the end of each first FPGA.

The queuing processing unit 111 determines whether "model generation_02" is included in the logic ID 1212 of the task at the end of each first FPGA (S12). Since the value of "model generation_02" is not included in the logic ID 1212 of each first FPGA (S12: Yes), the queuing processing unit 111 puts "model generation_02" in the FPGA other than the first FPGA. It is determined whether or not there is a second FPGA as an example of the "second configuration change type integrated circuit" including "(S13).

Since "task_02" and "task_09" indicate "model generation_02" (S13: Yes), the queuing processing unit 111 uses "FPGA_02" having "task_09" as the last task as the second FPGA. Select (S14). That is, the queuing processing unit 111 selects the second FPGA that can execute a predetermined task by using the logic before the configuration change from the plurality of FPGAs 104 excluding the first FPGA. The queuing processing unit 111 may select a plurality of second FPGAs.

The queuing processing unit 111 calculates the execution start time of "task_12" in the first FPGA and the execution start time of "task_12" in the second FPGA (S15). The execution start time is, for example, the total of the execution time of the task ID 1211 and the configuration change time 60, which are required to start the process of "task_12".

Since the logic of "task_01" of "FPGA_01" is "determination processing_01", the queuing processing unit 111 determines that the execution start time of "FPGA_01" includes "50 seconds" of the configuration change time 60. .. The queuing processing unit 111 calculates "90 seconds", which is the total processing time of "task_01" and the configuration change time 60, in "FPGA_01" as the execution start time of "task_12". The execution start time of the "task_12" of the first FPGA may be indicated as the first execution start time.

Since the logic of "task_09" of "FPGA_02" is "model generation_02", the queuing processing unit 111 sets "80 seconds", which is the total processing time of "task_02" and "task_09", to "FPGA_02". Is calculated as the execution start time. The execution start time of "task_12" of the second FPGA may be indicated as the second execution start time.

The queuing processing unit 111 compares the first execution start time with the second execution start time (S16). Since the queuing processing unit 111 has a second execution start time shorter than the first execution start time (S16: Yes), for example, the queuing processing unit 111 has a task queue 1222_3 of the second FPGA "FPGA_02". "Task_12" is assigned to (S17).

When the first execution start time is shorter than the second execution start time (S16: No), the queuing processing unit 111 allocates a predetermined task to the first FPGA (S18). That is, the queuing processing unit 111 compares the first FPGA with the second FPGA and selects the FPGA 104 having a shorter execution start time as a predetermined FPGA (S16 to S18).

When there is a first FPGA that can execute a predetermined task with the logic before the configuration change (S12: No), or another FPGA other than the first FPGA changes the logic configuration and executes the predetermined task. In the case of (S13: No), the queuing processing unit 111 assigns a predetermined task with the first FPGA as a predetermined FPGA.

That is, the queuing processing unit 111 assigns a predetermined task to the FPGA of the processing that can execute the predetermined task earliest in each FPGA 104.

When there are a plurality of candidates for FPGA 104 to which a predetermined task is assigned, the queuing processing unit 111 selects one of the FPGA 104s and assigns the task. The queuing processing unit 111 may randomly select a predetermined FPGA 104 from each FPGA 104.

When the arbitrary container 105 exclusively uses the arbitrary FPGA 104, the queuing processing unit 111 may delete the FPGA information 1221 of the arbitrary FPGA 104 from the task queue storage unit 122. The queuing processing unit 111 may occupy the arbitrary FPGA 104 in the arbitrary container 105 by fixing the task ID 1211 of the arbitrary container 105 in the task queue 1222_01 corresponding to the arbitrary FPGA information 1221.

When the predetermined task is stored in the task queue 1222_01, the queuing processing unit 111 acquires the information of the logic before the configuration change of the FPGA 104. For example, the queuing processing unit 111 allocates a task to FPGA information 1221 in which the acquired logic information and the logic ID 1212 of a predetermined task match. When the acquired logic information and the logic ID 1212 of the predetermined task are different, the queuing processing unit 111 may select one of the FPGA 104s and assign the task. When a predetermined task is saved in the task queue 1222_01, for example, a case where a new management server 10 is started up may be mentioned.

The queuing processing unit 111 may assign a task to each FPGA 104 based on the priority of each application 50. FIG. 7A is an explanatory diagram of priority information 1312 of the application 50. The queuing processing unit 111 acquires the priority information 1312 of the application 50. The priority information 1312 is set for each application DI 1311. The identification information of each application 50 is stored in the application ID 1311.

In the priority information 1312, for example, "rank_1" to "rank_M" (M = a predetermined number) are indicated. As for the priority, for example, "Rank_1" has the highest priority in the priority information 1312, "Rank_2" and "Rank_3" gradually decrease in priority, and "Rank_M" is the priority information. It has the lowest priority in 1312. That is, the queuing processing unit 111 preferentially allocates each task to the task queue 1222 in the order of "rank _1" to "rank _M", for example. The predetermined number M is not limited to a constant value, and may be a variable changed by the user.

FIG. 7B is an explanatory diagram of the application ID 1311 and the task ID 1211. The queuing processing unit 111b acquires, for example, the application ID 1311 of "task_12". The application ID 1311 of "task_12" is "application_12". The queuing processing unit 111 acquires the priority information 1312 of "task_12". Since the priority information 1312 of "task_12" is "rank_01", the queuing processing unit 111b acquires the application ID 1311 whose priority information 1312 is "rank_02" and "rank_03".

Since the priority information of "application_11" is the processing of "rank_03", the queuing processing unit 111b acquires the task ID 1211 of "application_11" from the task list storage unit 121. Since the task ID 121 of the "application_11" is the "task_11", the queuing processing unit 111b assigns the "task_12" before the "task_11". That is, the queuing processing unit 111b moves the "task_11" stored in the task queue 1222_02 to the task queue 1222_03, and saves the "task_12" in the task queue 1222_02.

That is, the queuing processing unit 111 acquires, for example, the task of the low priority application 50, which has a lower priority than the predetermined application 50. The queuing processing unit 111 allocates a predetermined task before the task of the low priority application 50. The queuing processing unit 111b may select the location of the task queue 1222 to interrupt the predetermined task according to the waiting time until the predetermined task is executed.

FIG. 8 is a flow chart of the FPGA allocation process (S20). The FPGA allocation process (S20) includes processing of the allocation processing unit 112 (S21 to S23, S25, S26) and processing of the logic change processing unit 113 (S24). The FPGA allocation process (S20) is performed by taking as an example a case where "task_12" is saved in the task queue 1222_01 of "FPGA_02" when "task_02" and "task_09" of "FPGA_02" are completed. I will explain it by listing it.

The FPGA allocation process (S20) moves to the process (S21) of the allocation processing unit 112. The allocation processing unit 112 is executed, for example, by changing the task ID 1211 of the task queue 1222_01. The allocation processing unit 112 acquires, for example, the logic ID 1212 of “task_09” from the task list storage unit 121 (S21). The logic ID 1212 of "task_09" is "model generation_02". That is, the allocation processing unit 112 acquires the logic ID 1212 implemented in the FPGA 104 based on the task ID 1211 deleted from the task queue 1222_01.

The allocation processing unit 112 acquires, for example, the logic ID 1212 of “task_12” from the task list storage unit 121 (S22). The logic ID 1212 of "task_12" is, for example, "model generation_02". That is, the allocation processing unit 112 acquires the logic ID 1212 to be implemented based on the task ID 1211 stored in the task queue 1222_01.

The allocation processing unit 112 compares the logic ID 1212 of "task_09" with the logic ID 1212 of "task_12" and determines whether to reconfigure the logic of "FPGA_02" (S23). That is, the allocation processing unit 112 determines whether to reconfigure the predetermined FPGA 104 by comparing the logic implemented in the FPGA 104 with the logic scheduled to be implemented in the FPGA 104.

Since the logic ID 1212 of "task_02" and the logic ID 1212 of "task_09" are both "model generation_02" (S23: No), the processing of the allocation processing unit 112 moves to the processing (S25).

The allocation processing unit 112 acquires the container ID 1213 of "task_09" from the task list storage unit 121. Since "task_09" is a process executed in "container_09", the allocation processing unit 112 mounts "FPGA_02" on "container_09". The allocation processing unit 112 mounts "FPGA_02" on "container_09" when "FPGA_02" is released from the processing of the application 50. The allocation processing unit 112 transmits a control signal for starting the processing of the “application_09” of the “container_09” to the “container_09” (S26).

That is, the allocation processing unit 112 is a function of referring to the task list storage unit 121 and the task queue storage unit 122 and mounting the predetermined FPGA 104 on the predetermined container 105.

In the process of determining whether to change the configuration of the FPGA 104 (S23), when the implemented logic and the logic to be implemented have different logic ID 1212 (S23: Yes), the allocation processing unit 112 , The logic change processing unit 113 is executed (S24). The allocation processing unit 112 transmits the FPGA information 1221 of the predetermined FPGA 104 and the logic ID 1212 to be implemented to the logic change processing unit 113. The allocation processing unit 112 executes the logic change processing unit 113, for example, when the predetermined FPGA 104 is released from the task.

The logic change processing unit 113 acquires the FPGA information 1221 of the predetermined FPGA 104 and the logic ID 1212 to be implemented. The logic change processing unit 113 acquires logic information that matches the logic ID 1212 to be implemented from the logic storage unit 123. The logic change processing unit 113 changes the configuration of the FPGA 104 based on the acquired logic information.

The logic storage unit 123 records logic information. The logic information indicates, for example, connection information of terminals mounted on the circuit. Logic information may be prepared by a predetermined program. The user may, for example, convert a program written in a hardware description language (HDL: Hardware Description Language) into logic information by a logic synthesis tool. A logic synthesis tool is, for example, software that converts source code in a hardware description language into logic information.

The FPGA 104 can be shared between the containers 105 by the queuing processing unit 111 and the allocation processing unit 112 shown above. The management server 10 can efficiently execute the task of the application 50 by the queuing process 111.

By selecting a predetermined FPGA from either the first FPGA or the second FPGA, the queuing processing unit 111 can assign the predetermined task to the FPGA 104 that can execute the predetermined task earliest among the FPGAs 104.

When the queuing processing unit 111 assigns a predetermined task to the FPGA 104 based on the priority information 1312 of the application 50, the management server 10 starts the processing of the predetermined application 50 in preference to the processing of the other application 50. can do.

FIG. 9 is a schematic view of the management server 10a according to the second embodiment. Since this embodiment corresponds to a modified example of the first embodiment, the differences from the first embodiment will be mainly described. The management server 10a is connected to the operation terminals 20 (1) and 20 (2) via the communication network 30.

The management server 10a includes, for example, an FPGA 104, a container 105, a queuing processing unit 111, an allocation processing unit 112, a logic change processing unit 113a, a schedule calculation processing unit 114, a forecast / performance determination processing unit 115, and a solution. Judgment unit 116, logic design processing unit 117, task list storage unit 121, task queue storage unit 122, logic storage unit 123, system operation history storage unit 124, schedule storage unit 125, and solution storage unit 126. And have. In each database shown in FIG. 9, the description of the “storage unit” is omitted.

The system operation history storage unit 124 is a database that stores the results of the FPGA 104 and the container 105, as will be described in detail in FIG. The schedule calculation processing unit 114 is a program that calculates the schedule 1270 of the configuration change of the FPGA 104 (hereinafter, may be referred to as the logic application schedule 1270) described in detail in FIG. 12 with reference to the system operation history 124. The schedule calculation processing unit 114 stores the logic application schedule 1270 in the schedule storage unit 125.

The logic change processing unit 113a is a program that refers to the schedule storage unit 125 and changes the configuration of the FPGA 104. The logic change processing unit 113a refers to the state of the FPGA 104 and changes the configuration of the FPGA 104.

The forecast / actual determination processing unit 115 is a program that refers to the system operation history storage unit 124 and the schedule storage unit 125 and detects the difference between the actual results of the FPGA 104 and the container 105 and the logic application schedule 1270. When the difference is detected at a predetermined threshold value or more, the forecast / performance determination processing unit 115 causes the schedule calculation processing unit 114 and the solution determination processing unit 116 to be executed.

The solution determination processing unit 116 refers to the solution storage unit 126 and sets the solution to be used when creating the logic application schedule 1270. The solution determination unit 116 transmits the determination result to the schedule calculation processing unit 117.

The logic design processing unit 117 is a program that refers to the system operation history storage unit 124 and determines whether or not a plurality of logics can be implemented in one FPGA. The logic design processing unit 117 transmits the determination result to the schedule calculation processing unit 114.

FIG. 10 is a flow chart of the schedule generation process (S30). The schedule generation processing (S30) includes, for example, the processing of the schedule calculation processing unit 114 (S31), the processing of the logic change processing unit 113a (S32, S33), and the processing of the forecast / performance determination processing unit 115 (S35, S36). , The process (S37) of the solution determination unit 116.

The schedule generation process (S30) moves to the process (S31) of the schedule calculation processing unit 114. The schedule calculation processing unit 114 is a function of calculating a logic application schedule 1270 (see FIG. 12) as an example of the “configuration change schedule” based on the information of the system operation history storage unit 124, for example. Before the explanation of the schedule calculation process (S31), the system operation history storage unit 124 and the logic application schedule 1270 will be described.

FIG. 11 is an explanatory diagram of the system operation history storage unit 124. The system operation history storage unit 124 has operation history information of the IT (Information Technology) infrastructure layer and operation history information of the application 50. The operation history information of the IT infrastructure layer is, for example, operation history information of the FPGA 104, the container 105, and the like.

The system operation history storage unit 124 includes a container ID 1241, a service name 1242, a process name 1243, a logic ID 1244, FPGA information 1245 (may be indicated as FPGA_ID in the figure), execution start 1246, and execution end 1247. , With a data amount of 1248.

Information that uniquely identifies the container 105 is stored in the container ID 1241. The container ID 1241 corresponds to the container ID 1213 of the task list storage unit 121.

The service name 1242 stores information that uniquely identifies the application 50 running on the container 105. Information that identifies the process of the application 50 executed on the container 105 is stored in the process name 1243.

The logic ID 1244 stores information that identifies the logic of the FPGA 104 that executes the application 50. The logic ID 1244 corresponds to the logic ID 1212 of the task list storage unit 121. Information that identifies the FPGA 104 is stored in the FPGA information 1245. The FPGA information 1245 corresponds to the FPGA information 1221 of the task queue storage unit 122.

The execution start 1246 stores the start time of the process of the application 50 indicated by the process name 1243. In the execution end 1247, the end time of the process of the application 50 indicated by the process name 1243 is saved.

The amount of processing data of the application 50 is stored in the data amount 1248. Examples of the processed data include teacher data in machine learning. The processing data of the application 50 is loaded into the memory 103 from the auxiliary storage device 102, for example. The system operation history storage unit 124 is not limited to the actual processing results of the FPGA 104 and the container 105, but may be information accumulated manually or by another program (not shown).

FIG. 12 is an explanatory diagram of the logic application schedule 1270. The logic application schedule 1270 is stored in the schedule storage unit 127. The logic application schedule 1270 has an FPGA number of 1271, a logic ID of 1272, a start time of 1273, and a completion time of 1274.

Information on the number of FPGAs 104 is stored in the FPGA number 1271. The logic ID 1272 stores information that identifies the logic of the FPGA 104. The logic ID 1272 stores at least one or more logic identification information. At the start time 1273 and the completion time 1274, information on the time when the logic of the logic ID 1272 is implemented in the FPGA 104 is stored.

That is, the logic application schedule 1270 indicates a schedule in which the number of FPGA 104s on which the logic of the logic ID 1272 is implemented is prepared as indicated by the number of FPGAs 1271 between the start time 1273 and the completion time 1274.

Returning to FIG. 10, the schedule calculation process (S31) of the schedule calculation processing unit 114 calculates the logic application schedule 1270 based on, for example, the solution of the application 50. The schedule calculation processing unit 114 acquires the solution information from the solution determination unit 116, which will be described in detail later.

The schedule calculation processing unit 114 may calculate the logic application schedule 1270 based on the statistics of the logic ID 1244 in the predetermined period of the system operation history storage unit 124, for example. The schedule calculation processing unit 114 may calculate the logic application schedule 1270 by referring to a predetermined number of information from the information newly stored in the system operation history storage unit 124, for example.

The management server 10a executes the schedule calculation processing unit 114 when a predetermined number or more of the information stored in the system operation history storage unit 124 is stored. When the information in the system operation history storage unit 124 is less than a predetermined number, the management server 10a executes the queuing processing unit 111, the allocation processing unit 112, and the logic change processing unit 113, respectively. FPGA 104 is assigned to each container 105.

That is, the queuing processing unit 111 and the allocation processing unit 112 process independently of the schedule calculation processing unit 114. By executing the queuing processing unit 111, the allocation processing unit 112, and the logic change processing unit 113, the management server 10a supplies the system operation history storage unit 124 with the operation history information of the IT infrastructure layer and the application 50. Accumulate operation history information.

Returning to FIG. 10, the schedule generation process (S30) moves to the logic change process (S32, S33) of the logic change processing unit 113a. The logic change processing unit 113a has a first change function for changing the configuration of the FPGA 104 based on the result of the allocation processing unit 112, and a second change function for changing the configuration of the FPGA 104 according to the logic application schedule 1270. The logic change processing (S32, S33) shown in FIG. 10 shows the second change function of the logic change processing unit 113a.

The first change function of the logic change processing unit 113a is executed by transmitting a control signal from the allocation processing unit 112. The logic change processing unit 113a acquires the logic ID 1212 and the FPGA information 1221 from the allocation processing unit 112. The logic change processing unit 113a modifies the FPGA 104 in which the FPGA information 1221 is set based on the logic ID 1212 and the logic storage unit 123.

The second change function of the logic change processing unit 113a implements the logic shown in the logic application schedule 1270 when the FPGA 104 is released from the processing of the application 50. The logic change processing unit 113a determines whether or not there is an FPGA 104 released from the processing of the application 50 (S32).

When there is an FPGA 104 released from the process (S32: Yes), the logic change processing unit 113a implements the logic indicated by the logic ID 1272 on the FPGA 104 released from the process (S33).

When it is determined that the FPGA 104 is executing the process of the application 50 (S32: No), the logic change processing unit 113 waits until the FPGA 104 is released from the process. If it is determined that the FPGA 104 is executing the process even after the start time 1273, the second change function of the logic change processing unit 113a may be terminated.

The management server 10a executes the process of the application 50 (S34). The FPGA 104 and the container 105 transmit information to the system operation history storage unit 124.

The schedule generation process (S30) moves to the process (S35) of the forecast / performance determination processing unit 115. The forecast / actual determination processing unit 115 is a function of regenerating the logic application schedule 1270 when the actual result of the logic change of the FPGA 104 stored in the system operation history storage unit 124 is different from the logic application schedule 1270.

The forecast / performance determination processing unit 115 acquires information on the FPGA 104 and the container 105 from, for example, the system operation history storage unit 124. The forecast / performance determination processing unit 115 acquires the logic application schedule 1270 from the schedule storage unit 127 (S35).

The forecast / performance determination processing unit 115 determines, for example, whether the logic of each FPGA 104 has been reconfigured according to the logic application schedule 1270 (S36). That is, the forecast / actual determination processing unit 115 detects the difference between the logic application schedule 1270 and the actual result stored in the system operation history storage unit 124.

The forecast / performance determination processing unit 115 may detect from the system operation history storage unit 124 that logic other than the logic ID 1272 shown in the logic application schedule 1270 is implemented in the FPGA 104.

When the difference is equal to or greater than a predetermined threshold value (S36: No), the forecast / performance determination processing unit 115 transmits the comparison result to the solution determination unit 116, and executes the schedule calculation processing unit 114. The predetermined threshold may be set by the user.

The forecast performance determination processing unit 115 may be executed by imposing restrictions when allocating the FPGA 104 to the container 105. That is, the forecast / performance determination processing unit 115 may be executed, for example, when an arbitrary container 105 exclusively uses an arbitrary FPGA 104.

The preliminary performance determination processing unit 115 may be executed at a predetermined timing. The forecast / performance determination processing unit 115 is, for example, changed the configuration of an arbitrary FPGA 104 more than a predetermined number of times per predetermined time, is set to be executed at predetermined intervals, or is the number of tasks stored in the task queue 1222. May be executed when there is a bias between FPGAs 104.

The solution determination unit 116 is a function of acquiring the difference information of the forecast / performance determination processing unit 115 and selecting the solution to be used by the schedule calculation processing unit 114. A plurality of solution information is stored in, for example, the solution storage unit 126.

The schedule calculation processing unit 114 may calculate the logic application schedule 1270 by referring to the determination result of the logic design processing unit 117. The logic design processing unit 117 is a function of determining whether a plurality of logics can be implemented in one FPGA 104 based on the information of the system operation history storage unit 124. The logic design processing unit 117 acquires a plurality of logic information implemented in the FPGA 104 from the system operation history storage unit 124. The logic design processing unit 117 determines whether or not a plurality of logics can be mounted on one FPGA 104.

Specifically, for example, in the system operation history storage unit 124, the logic design processing unit 117 implements "model generation_01" and "model generation_02" in the FPGA 104 assigned to the "container_01". Judged to be done. The logic design processing unit 117 also determines the implemented logic ID 1244 in the container 105 other than the “container _01”.

When "model generation_01" and "model generation_02" are frequently implemented in each container 105, the logic design processing unit 117 displays "model generation_01" and "model generation_02". Is determined in one FPGA 104. That is, the logic design processing unit 117 compares the mounting area of the circuit of FPGA 104 with the mounting area of the circuit of "model generation_01" and the total mounting area of the circuit of "model generation_02".

When the total mounting area of the circuit of "model generation_01" and the mounting area of the circuit of "model generation_02" is smaller than the mounting area of the circuit of FPGA 104, the logic design processing unit 117 puts "model" on one FPGA 104. It is determined that "generation_01" and "model generation_02" can be implemented. The logic design processing unit 117 transmits the determination result to the schedule calculation processing unit 114. The schedule calculation processing unit 114 calculates the logic application schedule 1270 based on the acquired determination result.

As a result, the schedule calculation processing unit 114 allows the management server 10a to change the configuration of the FPGA 104 in advance before executing the application 50. As a result, the management server 10a can efficiently execute the processing of the application 50.
The management server 10a can improve the logic application schedule 1270 by the forecast performance determination processing unit 115.

Since the queuing processing unit 111 and the allocation processing unit 112 are independent of the schedule calculation processing unit 114, the queuing processing unit 111 and the allocation processing unit 112 perform processing even before the logic application schedule 1270 is generated. Can be done.

The logic design processing unit 117 can implement a plurality of logics in one FPGA 104. As a result, the number of FPGA 104 released from the processing of the application 50 can be increased. As a result, it can be expected that the chances of applying the logic application schedule 1270 can be increased.

Note that the processing flow exemplified in this embodiment may include processing steps (not shown) or may not have some processing steps, and execution of some processing steps. The order may be changed.

In the description of the present embodiment, the process disclosed with the program as the subject may be a process performed by a computer such as a management server or an information processing device. Part or all of the program may be implemented by dedicated hardware.

Various programs may be installed in each computer by a program distribution server or a storage medium that can be read by the computer. In this case, the program distribution server includes a processor and a storage resource, which further stores the distribution program and the program to be distributed. When the processor executes the distribution program, the processor of the program distribution server distributes the distribution target program to other computers.

Part of the configuration of one embodiment may be replaced with the configuration of another embodiment. The configuration of another embodiment may be added to the configuration of one embodiment. Other configurations may be added / deleted / replaced with respect to a part of the configurations of each embodiment.

Each of the above-described configurations, functions, processing units, processing means, etc. may be realized by hardware by designing a part or all of them by, for example, an integrated circuit, and a program in which the processor realizes each function. It may be realized by software by interpreting and executing. In addition, all the processors, processes, data, other hardware devices, and software shown may be present on another server device or storage device connected by a network (not shown). It may be executed on the server device or storage device of.

10, 10a, 10b ... management server, 20 (1), 20 (2) ... operation terminal, 30 ... communication network, 40 ... external recording medium, 104 ... FPGA, 105 ... container, 111, 111b ... queuing processing unit, 112 ... Allocation processing unit, 113, 113a ... Logic change processing unit, 114 ... Schedule calculation processing unit, 115 ... Preliminary performance judgment processing unit, 116 ... Solution judgment processing unit 117 ... Logic design processing unit, 121 ... Task list storage unit, 122 ... Task queue storage unit, 123 ... Logic storage unit, 124 ... System operation history storage unit, 125 ... Schedule storage unit, 126 ... Solution storage unit

Claims (10)

It is a configuration-changeable integrated circuit allocation system that has multiple virtualized environments for executing application programs.
Multiple reconfigurable integrated circuits and reconfigurable integrated circuits
Queuing that assigns a predetermined process of the application program instructed by a predetermined virtualization environment among the plurality of virtualized environments to a predetermined configuration-changed integrated circuit among the plurality of configuration-changed integrated circuits. Processing unit and
An allocation processing unit that allocates the predetermined configuration-changeable integrated circuit to the predetermined virtualization environment, and
A configuration change type integrated circuit allocation system having a logic change processing unit for modifying the configuration of the predetermined configuration change type integrated circuit. The queuing processing unit
A function for calculating the processing time of the application program accumulated for each of the plurality of configuration-changeable integrated circuits, and
The function of calculating the configuration change time of the configuration change type integrated circuit and
A function of calculating the execution time, which is the sum of the processing time of the application program and the time of the configuration change, for each of the plurality of configuration change type integrated circuits.
A function of selecting a first configuration-modifying integrated circuit based on the execution time of each of the plurality of configuration-modifying integrated circuits, and
A function of selecting a second configuration-changed integrated circuit capable of executing the predetermined process using the circuit before the configuration change, and
The configuration-modified integrated circuit according to claim 1, which has a function of comparing the first configuration-modifying integrated circuit and the second configuration-modifying integrated circuit and selecting the predetermined configuration-modifying integrated circuit. Allocation system. Further, the queuing processing unit is
Priority information for each virtualized environment and
The configuration-modifying integrated circuit allocation system according to claim 2, further comprising a function of allocating the predetermined processing based on the priority information. Further, the allocation processing unit is
A function for determining whether to change the configuration of the predetermined configuration change type integrated circuit, and
The configuration change type integrated circuit allocation system according to claim 2, further comprising a function of executing the logic change processing unit based on a determination result of modifying the configuration of the predetermined configuration change type integrated circuit. Further, the configuration change type integrated circuit allocation system is
A system operation history storage unit that stores the allocation results of the configuration-changeable integrated circuit for each virtualization environment, and
A schedule calculation processing unit for setting a configuration change schedule of the configuration change type integrated circuit based on the information of the system operation history storage unit is provided.
The first aspect of claim 1, wherein the logic change processing unit has a function of mounting the circuit shown in the schedule on the configuration change type integrated circuit when the configuration change type integrated circuit is released from the processing of the application program. Configuration change type integrated circuit allocation system. Further, the configuration change type integrated circuit allocation system includes a logic design processing unit.
The logic design processing unit
It has a function of determining whether a plurality of circuits can be mounted on one configuration-changed integrated circuit based on the information of the system operation history storage unit.
Further, the schedule calculation processing unit is
The configuration-modified integrated circuit allocation system according to claim 5, which has a function of calculating the schedule based on the determination result of the logic design processing unit. The configuration change type integrated circuit allocation system is
When the number of information stored in the system operation history storage unit is equal to or greater than a predetermined number, the schedule calculation processing unit is executed.
The configuration-modifying integrated circuit allocation system according to claim 5, wherein the queuing processing unit and the allocation processing unit are executed independently of the schedule calculation processing unit to store information in the system operation history storage unit. .. Further, the configuration change type integrated circuit allocation system includes a forecast / performance determination processing unit.
The forecast performance judgment processing unit
A function of comparing the schedule with the information stored in the system operation history storage unit to determine whether to reset the schedule.
The configuration-modifying integrated circuit allocation system according to claim 5, further comprising a function of executing the schedule calculation processing unit based on a determination result of resetting the schedule. A predetermined process of an application program instructed by a predetermined virtual environment in a virtual environment is assigned to a predetermined configuration change integrated circuit among a plurality of configuration change type integrated circuits.
Assigning the predetermined configuration-modifying integrated circuit to the predetermined virtualization environment,
The configuration of the predetermined configuration-changing integrated circuit is modified.
Execute the predetermined process of the application program in the predetermined virtual environment.
Configuration change type integrated circuit allocation method. A computer program for allowing a computer to function as an allocation system for reconfigured integrated circuits, which has a plurality of virtualized environments for executing application programs.
The computer is provided with a plurality of reconfigurable integrated circuits that can be reconfigured.
On the computer
A queuing processing unit that assigns a predetermined process of the application program instructed by a predetermined virtual environment in the virtual environment to a predetermined configuration change integrated circuit among the plurality of configuration change type integrated circuits. When,
An allocation processing unit that allocates the predetermined configuration-changeable integrated circuit to the predetermined virtualization environment, and
A logic change processing unit that changes the configuration of the predetermined configuration change type integrated circuit, and
A computer program to realize each of these.

Images