JP2020173511A - Data transfer device, and data transfer method and computer program - Google Patents

Abstract

To provide a data transfer device capable of preventing deterioration of data transfer efficiency likely to occur when a plurality of data transfer requests having respective block sizes being not a fixed value concurrently occur to an identical memory, and a data transfer method and a computer program thereof.SOLUTION: A data transfer device 100 includes: a prediction unit 21 which predicts a transfer destination region being a memory region of a transfer destination of transfer data with respect to the data transfer request when a data transfer request requesting data transfer to an identical memory 3 and requesting transfer of the transfer data with respective block sizes being not a fixed value; and a controller 24 which writes the transfer data to the transfer destination region predicted with respect to the data transfer request.SELECTED DRAWING: Figure 1

Description

The present invention relates to a data transfer device, a data transfer method and a computer program.

When multiple data transfer requests for transferring data to the same memory and requesting the transfer of the data to be transferred (hereinafter referred to as "transfer data") to the memory occur at the same time and multiple times, the transfer data is blocked. If the size is a fixed value, the memory area of the transfer destination of each transfer data (hereinafter referred to as "transfer destination area") will not be duplicated in multiple data transfer requests before starting data transfer. Can be decided. In this case, even when a plurality of data transfer requests are generated, the plurality of data transfer requests can be processed in parallel by transferring each transfer data to each predetermined transfer destination area.

Japanese Unexamined Patent Publication No. 2003-091497 Japanese Unexamined Patent Publication No. 2015-060589 Japanese Unexamined Patent Publication No. 2011-197788 Japanese Patent Publication No. 2008-516320 Japanese Unexamined Patent Publication No. 2009-087189

However, in such a data transfer method, when the block size is not a fixed value, a plurality of data transfer requests cannot be processed in parallel until the size of the transfer data is fixed. Therefore, when a plurality of data transfer requests whose block sizes are not fixed values occur simultaneously for the same memory, the data transfer efficiency may decrease.

Therefore, an object of the present invention is to provide a data transfer device, a data transfer method, and a computer program capable of solving the above-mentioned problems.

One aspect of the present invention is a data transfer request for the same memory, and when a data transfer request for transferring transfer data whose block size is not a fixed value occurs, the transfer data transfer destination memory area It is a data transfer device including a prediction unit that predicts a certain transfer destination area for the data transfer request, and a controller that writes the transfer data to the transfer destination area predicted for the data transfer request.

One aspect of the present invention is a data transfer request for the same memory, and when a data transfer request for transferring transfer data whose block size is not a fixed value occurs, the transfer data transfer destination memory area It is a data transfer method including a prediction step of predicting a certain transfer destination area for the data transfer request and a writing step of writing the transfer data to the transfer destination area predicted for the data transfer request.

One aspect of the present invention is a data transfer request for the same memory, and when a data transfer request for transferring transfer data whose block size is not a fixed value occurs, the transfer data is transferred in the memory area of the transfer destination. It is a computer program for causing a computer to execute a prediction step of predicting a certain transfer destination area for the data transfer request and a writing step of writing the transfer data to the transfer destination area predicted for the data transfer request.

According to the present invention, when a plurality of data transfer requests whose block sizes are not fixed values are generated simultaneously for the same memory, it is possible to suppress a decrease in data transfer efficiency.

It is a block diagram which shows the specific example of the functional structure of the data transfer apparatus in this embodiment. It is a flowchart which shows the specific example of the flow in which the data transfer apparatus in this embodiment processes data transfer requests of a plurality of masters in parallel. It is a flowchart which shows the specific example of the flow of the writing area prediction processing in this embodiment. It is a flowchart which shows the specific example of the flow of the recovery process in this embodiment. It is a figure which shows the operation example of the recovery process in this embodiment. It is a figure which shows the operation example of the writing area prediction processing in this embodiment. It is a block diagram which shows the specific example of the functional structure of the modification of the data transfer apparatus in this embodiment.

Hereinafter, a data transfer device, a data transfer method, and a computer program according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a specific example of the functional configuration of the data transfer device according to the present embodiment. The data transfer device 100 is an example of the data transfer device according to the present embodiment, and includes, for example, one or more masters 1, a bus bridge 2, a target memory 3, and a correction memory 4. The bus bridge 2 has a function as a bridge for connecting various buses inside the data transfer device 100. For example, the bus bridge 2 is connected to one or more master 1, the target memory 3, and the correction memory 4 via the buses B1, B2, and B3 so that data can be input and output from each other.

FIG. 1 shows masters 1-1 to 1-N (N is an integer of 1 or more) as master 1 of 1 or more. Each master 1 is a functional unit capable of independently making a data transfer request to the target memory 3. For example, the master 1 may be an individual process managed by the operating system or an individual I / O device. When data to be transferred to the target memory 3 is generated, each master 1 notifies the bus bridge 2 of a "data transfer request" indicating that fact. When the data transfer request is received by the bus bridge 2, each master 1 outputs the data to be transferred (hereinafter referred to as "transfer data") to the bus bridge 2.

The bus bridge 2 has a function of writing the transfer data of each master 1 to a predetermined area of the target memory 3 in response to the data transfer request notified from each master 1. By writing this transfer data, the transfer data is transferred to the target memory 3. Further, the bus bridge 2 has a function of storing the transfer data written in the target memory 3 in the correction memory 4 for a predetermined period. When the writing of the transfer data conflicts between the plurality of masters 1, the bus bridge 2 becomes invalid due to the conflict by using the transfer data (hereinafter referred to as “save data”) stored in the correction memory 4. Restore the transferred data.

The target memory 3 is a main storage device configured by using a semiconductor storage device, and is a target memory for which each master 1 requests data transfer. In FIG. 1, one memory is shown as the target memory 3 for the sake of simplicity, but this does not necessarily indicate that only one specific predetermined memory is the target of data transfer. The target memory 3 may be a plurality of memories, or may be one or more memories appropriately selected from the plurality of memories.

In FIG. 1, the square object described inside the target memory 3 schematically shows the memory block in which the transfer data of each master 1 is written, and the numerical value described inside each object. Represents the identification information of the master 1 that has requested the transfer of the data stored in each memory block, and corresponds to the codes of the masters 1-1 to 1-N, respectively.

The correction memory 4 is configured by using a storage device such as a magnetic hard disk device or a semiconductor storage device. The correction memory 4 is used as a storage unit that stores the transfer data output by the bus bridge 2 as saved data. The correction memory 4 has a storage area for saved data (hereinafter referred to as “save area”) in each of the masters 1-1 to 1-N. FIG. 1 shows an example in which the correction memory 4 manages each save area with the identification information (master index in the figure) of the master 1 corresponding to each.

Subsequently, the functional configuration of the bus bridge 2 will be described. The bus bridge 2 includes a write area prediction unit 21, an address translation unit 22, an address translation table 23, and a controller 24. The write area prediction unit 21 has a function of predicting a transfer destination area for each master 1 that has made a data transfer request. The write area prediction unit 21 generates a parameter (hereinafter referred to as “address specification parameter”) that specifies a memory address on the target memory 3 for the transfer destination area predicted for each master 1, and uses the value of the generated address specification parameter. Notify the address conversion unit 22.

The address conversion unit 22 has a function of converting the value of the address designation parameter into a memory address on the target memory 3. Specifically, the address conversion unit 22 refers to the address conversion table 23 showing the correspondence between the value of the address specification parameter and the memory address, and acquires the memory address corresponding to the value notified from the write area prediction unit 21. By doing so, the address specification parameter is converted into the memory address of the transfer destination area (hereinafter referred to as "transfer destination address"). The address translation unit 22 notifies the controller 24 of the acquired transfer destination address.

The address translation table 23 is data showing the correspondence between the value of the address specification parameter and the memory address. For example, the address translation table 23 is stored in a high-speed accessible storage device such as a cache memory, and its contents are managed by a management mechanism (not shown) of the target memory 3. For example, the address translation table 23 may be data indicating the correspondence between the virtual memory address of each master 1 and the physical memory address of the target memory 3.

The controller 24 has a function of writing the transfer data to the target memory 3 in response to the data transfer request of each master 1. Specifically, the controller 24 acquires the transfer destination address of each transfer data for each data transfer request, and writes the transfer data to the memory area of the acquired transfer destination address. Further, the controller 24 has a function of executing a recovery process when the size of the transferred data is different from the size of the predicted area.

Specifically, this recovery process includes a first process of rewriting a part of the transferred data to the target memory 3 and a second process of improving the prediction accuracy of the transfer destination area.

In the data transfer device 100 of the present embodiment having such a configuration, a plurality of masters 1 simultaneously request a data transfer request for transferring transfer data whose flock size is not a fixed value to a continuous memory area of the same target memory 3. In this case, the bus bridge 2 predicts the transfer destination area of the transfer data of each request, and by processing the writing of the transfer data to each predicted transfer destination area in parallel, it is possible to suppress the decrease in the data transfer efficiency. Become.

For the sake of simplicity in FIG. 1, the data transfer device 100 is configured as one device that connects one or more masters 1, a bus bridge 2, a target memory 3, and a correction memory 4 by an internal bus. However, the case is not limited to this. For example, the data transfer device 100 may be configured as a system in which one or more masters 1, a bus bridge 2, a target memory 3, and a correction memory 4 are connected by an external bus.

FIG. 2 is a flowchart showing a specific example of a flow in which the data transfer device 100 in the present embodiment processes data transfer requests of a plurality of masters 1 in parallel. The series of processes shown in this flowchart is a data transfer request for the same target memory 3, and when a data transfer request for transferring the transferred data to a continuous area on the target memory 3 is requested simultaneously from a plurality of masters 1. It will be started.

In this case, in the bus bridge 2, the controller 24 that has received the data transfer request first instructs the write area prediction unit 21 to execute the write area prediction process. The write area prediction process is a process of predicting the transfer destination area of each transfer data for each data transfer request. The write area prediction unit 21 executes the write area prediction process in response to the instruction of the controller 24 (step S101). The write area prediction unit 21 notifies the address conversion unit 22 of the value of the address designation parameter of each transfer destination area predicted in the write area prediction process.

Subsequently, the address translation unit 22 acquires the memory address (that is, the transfer destination address) on the target memory 3 for each transfer destination area. Specifically, the address translation unit 22 converts each value of the address designation parameter notified from the write area prediction unit 21 into a transfer destination address based on the address translation table 23. The address translation unit 22 notifies the controller 24 of the transfer destination address acquired for each transfer destination area. The controller 24 writes the corresponding transfer data to the memory area of each transfer destination address notified from the address translation unit 22 (step S102). Further, the controller 24 writes the transfer data written in the target memory 3 to the correction memory 4 (step S103).

Specifically, each master 1 divides one transfer data into a predetermined block size, and sequentially outputs a block of continuous data (hereinafter referred to as "block data") for each block size. In this case, the controller 24 sequentially inputs the block data continuously output by each master 1 and identifies the transfer destination area for each block data. The controller 24 executes input of block data output as continuous data in parallel for a plurality of masters 1, and writes each input block data in order from the start address of the corresponding transfer destination area. At this time, the controller 24 writes each block data in parallel for the plurality of masters 1 in response to the input.

When the transfer data is divided into a plurality of block data and input / output is performed in this way, if the block size is a fixed value, it is possible to estimate the size of the transfer destination area before starting the writing of the transfer data. However, if the block size is not a fixed value, the memory size required as the transfer destination area cannot be known until the block data is actually written. Therefore, at the time of step S102, the size of the transfer destination area of each block data is unknown with respect to the data transfer request of each master 1.

Therefore, the controller 24 determines whether or not the size of the block data has been determined while inputting and outputting the block data (step S104). For example, the controller 24 determines whether or not the size of the block data is fixed by detecting the presence or absence of data input and the change of a predetermined input pattern. When the size of the block data is not fixed (step S104-NO), the controller 24 returns the process to step S101 and executes the input / output of the next block data.

On the other hand, when the size of the block data is determined (step S104-YES), the controller 24 notifies the corresponding master 1 that the size of the block data has been determined (step S105). The controller 24 has predicted that the size of the transfer destination area predicted for the fixed block data (hereinafter referred to as “predicted size”) matches the actual size of the fixed block data (hereinafter referred to as “actual size”). Whether or not it is determined (step S106).

When the predicted size and the actual size match (step S106-YES), the controller 24 determines whether or not all the data transfer is completed (step S107). Specifically, the controller 24 determines whether or not the transfer of all block data has been completed for all the transfer data. When all the data transfer is completed (step S107-YES), the controller 24 notifies the writing area prediction unit 21 of the completion of the data transfer (step S108), and ends the process.

On the other hand, in step S106, when the predicted size does not match the actual size (step S106-NO), the controller 24 executes the recovery process for the block data (step S107). By executing this recovery process, the controller 24 corrects the illegal data arrangement caused by the write process of the block data.

Further, at this time (step S106-NO), the controller 24 notifies the writing area prediction unit 21 that a writing has occurred whose predicted size does not match the actual size (hereinafter referred to as “alarm”). .. The alarm notified here is held as an uncounted alarm (described later) until it is counted in the cumulative number of alarms by the writing area prediction unit 21.

After executing the recovery process or in step S107, when a part of the data transfer is not completed (step S107-NO), the controller 24 returns the process to step S101 and executes the input / output of the next block data. ..

FIG. 3 is a flowchart showing a specific example of the flow of the write area prediction process in the present embodiment. First, the write area prediction unit 21 predicts the block size of the transferred data (step S201). Specifically, the write area prediction unit 21 sets the block size as a predetermined default value at the first execution of step S201, and sets the block size as the previous predicted value (predicted size) at the next execution. The block size is predicted by setting the same value. For example, the default value of the block size may be a predetermined initial value, the block size of any one of the plurality of masters 1 at that time, or the first master. It may be the first block size of 1.

Subsequently, the write area prediction unit 21 generates an address designation parameter for the storage area (transfer destination area) on the target memory 3 that records the transfer data (block data) of the predicted block size, and the generated address designation parameter Notify the address conversion unit 22 of the value (step S202).

Subsequently, the write area prediction unit 21 determines whether or not an uncounted alarm has occurred (step S203). Here, the uncounted alarm is an alarm whose occurrence count is not counted in the cumulative alarm count, and the cumulative alarm count is a judgment target when deciding whether or not to correct the block size prediction method. The cumulative number of alarms. Further, the cumulative number of alarms is initialized to 0 according to the decision to correct the prediction method.

When an uncounted alarm has occurred (step S203-YES), the write area prediction unit 21 adds the number of uncounted alarm occurrences to the cumulative number of alarms (step S204), and has not added the alarm recorded in the cumulative number of alarms. Exclude from the count alarm. On the other hand, when the uncounted alarm has not occurred (step S203-NO), the write area prediction unit 21 proceeds to the subsequent step S204.

Subsequently, the writing area prediction unit 21 determines whether or not the cumulative number of alarms (first number of times) is equal to or greater than the first threshold value (step S205). For example, the first threshold is 10 times. When the cumulative number of alarms is less than the first threshold value (step S205-NO), the write area prediction unit 21 ends the write area prediction process.

On the other hand, when the cumulative number of alarms is equal to or greater than the first threshold value (step S205-YES), the writing area prediction unit 21 has the number of occurrences of the first alarm (second number) among the alarms corresponding to the cumulative number of alarms. It is determined whether or not it is equal to or greater than the threshold value of 2 (step S206). Here, the first alarm is an alarm that notifies that the actual size of the block data is smaller than the predicted size. In the following, the alarm that notifies that the predicted size of the block data is smaller than the actual size with respect to the first alarm is referred to as a second alarm.

The second threshold value may be a value greater than half of the cumulative number of alarms and less than or equal to the cumulative number of alarms. In addition, since the cumulative number of alarms is typically a value equal to or less than the first threshold value, the second threshold value may be a value larger than half of the first threshold value and less than or equal to the first threshold value. For example, when the first threshold value is 10 times, the second threshold value can be 7 times. In this case, the second threshold value may be a value in the range of 6 to 10 times, and which value the second threshold value should be is determined according to the correction frequency of the prediction method, the magnitude of correction, and the like. May be done.

When the number of occurrences of the first alarm is equal to or greater than the second threshold value (step S206-YES), the write area prediction unit 21 corrects the block size prediction method by the first method (step S207). For example, in the first method, the predicted size predicted by the current write area prediction process is corrected based on the following equation (1).

Predicted size after correction = average value of actual size- (average value of predicted size-average value of actual size) ・ ・ ・ (1)

For example, each average value in the equation (1) may be typically the average value in the period in which the alarm for the cumulative number of alarms is generated, but may be the average value in a longer or shorter period as necessary. You may.

Since the correction of the predicted size by the first method is performed when there is a strong tendency that the actual size <predicted size, the second term on the right side of the equation (1) is basically a positive value. The corrected predicted size is corrected to a value smaller than the average value of the actual size. Since the corrected predicted size obtained in this way is used as the predicted size in the write area prediction process from the next time onward, a smaller block size is predicted in the write area prediction process from the next time onward.

On the other hand, when the number of occurrences of the first alarm is less than the second threshold value (step S206-NO), the write area prediction unit 21 generates the second alarm out of the cumulative number of alarms (third). It is determined whether or not the number of times) is equal to or greater than the third threshold value (step S208).

As with the second threshold value, the third threshold value may be a value greater than half of the cumulative number of alarms and less than or equal to the cumulative number of alarms. Since the cumulative number of alarms is typically a value equal to or less than the first threshold value, the third threshold value may be a value larger than half of the first threshold value and less than or equal to the first threshold value. For example, when the first threshold value is 10 times, the third threshold value can be 7 times. In this case, the third threshold value may be a value in the range of 6 to 10 times, and which value the third threshold value should be is determined according to the correction frequency of the prediction method, the magnitude of correction, and the like. May be done. The third threshold value may be the same value as the second threshold value.

When the number of occurrences of the second alarm is equal to or greater than the third threshold value (step S208-YES), the write area prediction unit 21 corrects the block size prediction method by the second method (step S209). For example, in the second method, the predicted size predicted by the current writing area prediction process is corrected based on the following equation (2).

Predicted size after correction = average value of actual size + (average value of actual size-average value of predicted size) ・ ・ ・ (2)

For example, each average value in the equation (2) may be the average value in the period in which the alarm is generated for the cumulative number of alarms, as in the case of the equation (1), but if necessary, it may be the average value. It may be the average value for a longer or shorter period.

Contrary to the case of the first method, the correction of the predicted size by the second method is performed when there is a strong tendency that the predicted size <actual size, so basically the equation (2) The second term on the right side of is a positive value, and the corrected predicted size is corrected to a value larger than the average value of the actual size. Since the corrected predicted size obtained in this way is used as the predicted size in the write area prediction process from the next time onward, a larger block size is predicted in the write area prediction process from the next time onward.

On the other hand, when the number of occurrences of the second alarm is less than the third threshold value (step S208-NO), the write area prediction unit 21 corrects the block size prediction method by the third method (step S210). For example, in the third method, the predicted size predicted by the current writing area prediction process is corrected based on the following equation (3).

Predicted size after correction = average value of actual size ... (3)

For example, each average value in the equation (3) may be an average value in the period in which the alarm is generated for the cumulative number of alarms, as in the case of the equations (1) and (2), but it is necessary. It may be the average value for a longer or shorter period depending on the situation.

The correction of the predicted size by the third method does not correspond to either of the first method and the second method, that is, the predicted size <the actual size and the actual size <the predicted size. Will be done if and is about the same. In this case, the predicted size after correction is corrected to the average value of the actual size by the equation (3). Since the corrected predicted size obtained in this way is used as the predicted size in the write area prediction process from the next time onward, the block size having a more appropriate size close to the actual size is used in the write area prediction process from the next time onward. Will be predicted.

When the prediction method is corrected in any of steps S207, S209 and S210, the write area prediction unit 21 initializes the cumulative number of alarms to 0 (step S211) and ends the write area prediction process.

FIG. 4 is a flowchart showing a specific example of the flow of the recovery process in the present embodiment. First, the controller 24 suspends the data transfer process (step S301). For example, the controller 24 may suspend the data transfer process by suspending the acceptance of a new data transfer request. In this case, for example, the controller 24 may respond with an unacceptable error to the master 1 requesting new data transfer during the suspension. Further, for example, the controller 24 may be configured to notify each master 1 at the start of the suspension period that the acceptance of the data transfer request is suspended.

Further, when the bus bridge 2 has a storage unit capable of temporarily storing the transfer data for the data transfer request generated during the suspension, the controller 24 is while the data transfer process is suspended. The transfer data generated in the above may be stored in the storage unit, and when the data transfer process is restarted, the data transfer process may be performed in order from the transfer data stored in the storage unit.

Subsequently, the controller 24 corrects the invalidity of the data arrangement on the target memory 3 caused by writing the data block whose actual size is different from the predicted size by using the data stored in the correction memory 4 (). Step S302). When the correction of the data arrangement is completed, the controller 24 releases the suspension of the data transfer process (step S303).

FIG. 5 is a diagram showing an operation example of the recovery process in the present embodiment. FIG. 5A shows an example of arranging block data at a certain point in time before the recovery process is executed. In FIG. 5, the solid line block represents the block data actually written in the target memory 3. Further, the broken line block represents the transfer destination area of each block data secured in the target memory 3, and represents the area in which the block data is not written at that time.

For example, in FIG. 5A, after the block data is written to the blocks 1a, 1b, and 1c by the master # 1, the blocks 2a, 2b, and 2c, which are the transfer destination areas of the master # 2, become the block size of the master 1. It represents the situation secured accordingly. Hereinafter, the block serving as the transfer destination area in the target memory 3 is referred to as a target block.

FIG. 5B shows a situation in which block data 2a'in which the actual size is smaller than the predicted size is written in the block 2a in the target memory 3 in the state of FIG. 5A, and is hatched with dots. The area S1 represents a free area in which data has not been written. Such a free area S1 becomes a factor that lowers the utilization efficiency of the storage area. Therefore, when such an area occurs when writing the block data, that is, when the actual size is smaller than the predicted size, the controller 24 rearranges the written subsequent block data in the free area.

Here, the block data written in the target memory 3 is stored in the correction memory 4 for each master 1. For example, in the right figure of FIG. 5B, the block data already written in the blocks 1a, 1b, and 1c of the target memory 3 by the data transfer request of the master # 1 is the block of the correction memory 4 for the master # 1. It shows the situation that is stored in 1a, 1b, and 1c, respectively. Hereinafter, the data block for storing block data secured in the correction memory 4 is referred to as a storage block.

For example, in this case, the controller 24 rearranges the block data as shown in FIG. 5C by transferring the block data stored in the storage block 1b to the free area S1. As a result, the block data following the free area is moved to the free area, and the target block 2b secured in the target memory 3 is increased by the size of the free area S1 (that is, the difference between the predicted size and the actual size). Reorganized as'. By relocating the data in this way, the bus bridge 2 of the embodiment can integrate the free area generated at the time of writing the block data and suppress the decrease in the utilization efficiency of the storage area.

Subsequently, FIG. 5D shows a situation in which block data 2b ”whose actual size is larger than the predicted size is written in the target block 2b'secured in FIG. 5C. The shaded area S2 in (D) represents an overlapping area in which a part of the already written data block 1c is overwritten (that is, missing) by the writing of the target block 2b. Since the block data 1c has become invalid data due to the writing of the block data 2b ", it is necessary to restore the block data 1c to the correct data.

For example, in this case, as shown in FIG. 5 (E), the controller 24 transfers the block data stored in the storage block 1c to the continuous area following the target block 2b ”, whereby the block data in FIG. 5 (F) is transferred. As a result, the target block 2c secured in the target memory 3 is reorganized as a block 2c'reduced by the size of the overlapping area S2. Such data rearrangement. By performing the above, the bus bridge 2 of the embodiment can restore the block data overwritten by the block data whose actual size is larger than the predicted size to another area.

By recovering the free area and repairing the overwritten data, the bus bridge 2 of the embodiment has a data size of the data transfer request even when a data transfer request of unknown block size occurs. The data transfer process can be started without waiting for confirmation.

FIG. 6 is a diagram showing an operation example of the write area prediction process in the present embodiment. Specifically, FIG. 6 shows a specific example of the operation of correcting the prediction method of the transfer destination area. FIG. 6A shows an example of arranging data in the target memory 3 at a certain timing when the cumulative number of alarms reaches 10 during execution of the write area prediction process. At this timing, for example, if the first alarm is generated eight times, the second alarm is generated twice, and the first threshold position is seven times, the write area prediction unit 21 is the first. Correct the prediction method of the transfer destination area by the method.

As described above, the method of predicting the transfer destination area is corrected according to the frequency of occurrence of the alarm, so that the bus bridge 2 of the embodiment can improve the prediction accuracy of the transfer destination area. In addition, by improving the prediction accuracy of the transfer destination area, the occurrence of recovery processing is suppressed, and more stable data transfer processing can be realized.

(Modification example)
A part or all of the data transfer device in this embodiment may be realized by software. For example, the data transfer device includes a CPU (Central Processing Unit), a memory, an auxiliary storage device, and the like connected by a bus, and executes a program. The data transfer device functions as a device provided with a bus bridge by executing a program. All or part of each function of the data transfer device may be realized by using hardware such as ASIC (Application Specific Integrated Circuit), PLD (Programmable Logic Device), and FPGA (Field Programmable Gate Array). The program may be recorded on a computer-readable recording medium. The computer-readable recording medium is, for example, a flexible disk, a magneto-optical disk, a portable medium such as a ROM or a CD-ROM, or a storage device such as a hard disk built in a computer system. The program may be transmitted over a telecommunication line.

FIG. 7 is a block diagram showing a specific example of the functional configuration of the modified example of the data transfer device in the present embodiment. The data transfer device 100a of the modified example may be configured as, for example, a bus bridge 2a connected to one or more masters 1, a target memory 3, and a correction memory 4. Further, in this case, the bus bridge 2a may be configured as a device including the writing area prediction unit 21 and the controller 24. Further, in this case, the write area prediction unit 21 may be configured to include the address translation unit 22 and the address translation table 23, and the address translation unit 22 and the address translation table 23 may inform the bus bridge 2a of information. It may be configured as an external device that inputs and outputs.

It is a device that processes a data transfer request to a memory, and is applicable to a data transfer device that processes a data transfer request in which the block size of the transfer data is not a fixed value.

100 ... Data transfer device, 1,1-1 to 1-N ... Master, 2 ... Bus bridge, 21 ... Write area prediction unit, 22 ... Address conversion unit, 23 ... Address conversion table, 24 ... Controller, 3 ... Target memory 4, ... Correction memory, B1 to B3 ... Bus

Claims (10)

When a data transfer request for data transfer to the same memory and a request for transfer of transfer data whose block size is not a fixed value occurs, the transfer destination area which is the memory area of the transfer destination of the transfer data is the data. A predictor that predicts transfer requests and
A controller that writes the transfer data to the transfer destination area predicted for the data transfer request, and
A data transfer device comprising. The prediction unit records the transfer data written in the transfer destination area as save data in the save area.
When the actual size, which is the block size determined for the transfer data, is different from the predicted size, which is the block size of the transfer destination area predicted by the prediction unit, the controller sets the data arrangement on the memory to the save area. Correct using the recorded saved data.
The data transfer device according to claim 1. When the actual size of the first transfer data is larger than the predicted size, the controller is written before the first transfer data, and the transfer destination area overlaps with the transfer destination area of the first transfer data. The second transfer data, which is partially lost, is restored to a new transfer destination area that does not overlap with the first transfer data.
The data transfer device according to claim 2. When the actual size of the first transfer data is smaller than the predicted size, the controller causes the second transfer data written before the first transfer data by the difference between the predicted size and the actual size. Move to the resulting free space,
The data transfer device according to claim 2 or 3. When the first number of times, which is the number of times the actual size and the predicted size are different from each other, is equal to or greater than the first threshold value, the controller corrects the method of predicting the transfer destination region according to the first number of times.
The data transfer device according to any one of claims 2 to 4. In the controller, the predicted size is smaller than the average value of the actual size when the second number of times the actual size becomes larger than the predicted size among the first times is equal to or larger than the second threshold value. Correct the prediction method to be predicted,
The data transfer device according to claim 5. The controller has a predicted size larger than the average value of the actual size when the third number of times the actual size is smaller than the predicted size among the first times is equal to or larger than the third threshold value. Correct the prediction method to be predicted,
The data transfer device according to claim 5 or 6. In the controller, the second number of times the actual size becomes larger than the predicted size in the first number of times is less than the second threshold value, and the actual size of the first number of times is less than the second threshold value. When the third number of times the size becomes smaller than the predicted size is less than the third threshold value, the prediction method is corrected so that the predicted size is predicted as the average value of the actual size.
The data transfer device according to any one of claims 5 to 7. When a data transfer request for data transfer to the same memory and a request for transfer of transfer data whose block size is not a fixed value occurs, the transfer destination area which is the memory area of the transfer destination of the transfer data is the data. Prediction steps for predicting transfer requests and
A write step of writing the transfer data to the transfer destination area predicted for the data transfer request, and
Data transfer method having. When a data transfer request for data transfer to the same memory and a request for transfer of transfer data whose block size is not a fixed value occurs, the transfer destination area which is the memory area of the transfer destination of the transfer data is the data. Prediction steps for predicting transfer requests and
A write step of writing the transfer data to the transfer destination area predicted for the data transfer request, and
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