JP2020170904A - Semiconductor device and system - Google Patents

Abstract

To reduce the power consumption of a semiconductor device without reducing the efficiency of data transmission.SOLUTION: A semiconductor device includes a first inversion portion that inverts the logic of first partial data in which data is divided into a plurality of pieces of data and enables first inversion information assigned to each first partial data when the number of changes in the bit value exceeds half of the number of bits for each of first partial data compared with the previous transmission, a second inversion portion that determines whether to invert the logic of second partial data in which data is divided into a plurality of pieces of data, which is supplied as the first partial data to the first inversion portion according to the ratio in which the number of changes in the bit value exceeds half of the number of bits compared to the previous transmission, and enables second inversion information when the logic is inverted, and a transmission portion that transmits the first inversion information and the second inversion information together with the first partial data generated by the first inversion portion.SELECTED DRAWING: Figure 1

Description

The present invention relates to semiconductor devices and systems.

In order to reduce the frequency with which data transmitted between devices via the data bus is driven to "0" and suppress an increase in power consumption, the bit value is inverted using the cycle after the data transmission cycle. A data bus inversion vector indicating that is transmitted. In addition, a global data bus inversion indicator indicating that the bit value of the dabus inversion vector has been inverted is transmitted using the data mask line. (See, for example, Patent Document 1).

In order to increase the appearance rate of a predetermined logical value in the data transmitted between the memory and the CPU (Central Processing Unit), data inversion processing is performed, and an inversion / non-inversion signal indicating data inversion is data. Is output together with (for example, see Patent Document 2).

Special Table 2013-524383 Japanese Unexamined Patent Publication No. 2006-203756

When a data bus inversion vector transmission cycle is provided in addition to the data transmission cycle, the data logic cannot be reproduced in the cycle in which the data is received. As a result, by inserting a cycle that does not contribute to data transmission, the data transmission efficiency is lowered and the power consumed per unit data transmission is increased.

In one aspect, the present invention aims to reduce the power consumption of a semiconductor device without reducing the efficiency of data transmission.

According to one viewpoint, in the semiconductor device, when the number of changes in the bit value exceeds half of the number of bits in each of the first partial data in which the data is divided into a plurality of data, the first partial data In the first inversion part that inverts the logic of and enables the first inversion information assigned to each first partial data, and in the second partial data in which the data is divided into a plurality of data, compared with the previous transmission. It is determined whether to invert the logic of the second partial data supplied as the first partial data to the first inversion portion according to the ratio in which the number of changes in the bit value exceeds half of the number of bits, and the logic is determined. In the case of inversion, the first inversion information and the second inversion information are provided together with the second inversion portion that enables the second inversion information and the first partial data generated by the first inversion portion. It is characterized by having a transmission unit for transmitting and.

In one aspect, the present invention can reduce the power consumption of a semiconductor device without reducing the data transmission efficiency.

It is a block diagram which shows an example of the system including the semiconductor device in one Embodiment. It is a side view which shows an example of the system-in-package which has a semiconductor device in another embodiment. It is explanatory drawing which shows an example of the structure of the data which is transmitted and received between the stacked memory of FIG. 2 and a processor chip. It is explanatory drawing which shows an example of the allocation of all inversion bits to a data mask area. It is a block diagram which shows an example of the processor chip of FIG. It is explanatory drawing which shows an example of the data transmitted from the processor chip of FIG. 2 to the stacked memory. It is explanatory drawing which shows another example of the data transmitted from the processor chip of FIG. 2 to the stacked memory. It is explanatory drawing which shows another example of the data transmitted from the processor chip of FIG. 2 to the stacked memory. It is a flow chart which shows an example of the operation when the processor chip of FIG. 2 transmits data to a stacked memory. It is a flow chart which shows an example of the operation when the processor chip of FIG. 1 receives data from a stacked memory. It is explanatory drawing which shows an example of the allocation of the data mask area in the semiconductor device of another embodiment. It is a block diagram which shows an example of the processor chip to which the allocation of the data mask area of FIG. 11 is applied. It is explanatory drawing which shows the outline of the operation of the processor chip to which the allocation of the data mask area of FIG. 11 is applied. It is explanatory drawing which shows an example of the data which is transmitted to the stacked memory from the processor chip to which the allocation of the data mask area of FIG. 11 is applied. FIG. 5 is a flow chart showing an example of an operation when data is transmitted from the processor chip to which the allocation of the data mask area of FIG. 11 is applied to the stacked memory. FIG. 5 is a flow chart showing an example of an operation when the processor chip to which the allocation of the data mask area of FIG. 11 is applied receives data from the stacked memory.

Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 shows an example of a system including a semiconductor device in one embodiment. In the example shown in FIG. 1, the system 100 has a pair of semiconductor devices 1a and 1b. For example, the semiconductor device 1a is a processor such as a CPU, and the semiconductor device 1b is a memory. However, the semiconductor devices 1a and 1b are not limited to the above, and may be, for example, a CPU and a GPU (Graphics Processing Unit), or a CPU and a logic device.

FIG. 1 shows an interface portion for transmitting and receiving data DT in semiconductor devices 1a and 1b. In addition to the elements shown in the drawings, the semiconductor devices 1a and 1b include a circuit for processing data DT, a circuit for storing data DT, and the like. Since the interface portions of the semiconductor devices 1a and 1b have the same configuration as each other, the semiconductor device 1a will be described below. When the system 100 is a system-in-package, the interface portion for transmitting and receiving data DT corresponds to the input / output interface portion PHY of FIG. 2 described later.

The semiconductor device 1a has a second inversion unit 2, a first inversion unit 3, a transmission unit 4, a reception unit 5, a third inversion unit 6, and a fourth inversion unit 7.

The first inversion unit 3 calculates the number of changes in the bit value of the data DT transmitted this time with respect to the data DT transmitted last time. In the first inversion unit 3, the number of changes in the bit value (that is, the number of logic inversions) is half of the number of bits for each of the first partial data DT10-DT13 obtained by dividing the data DT into a plurality of data DT10-DT13. Determine if it exceeds. Then, the first inversion unit 3 inverts the logic of the first partial data DT in which the number of changes in the bit value exceeds half of the number of bits. The first inversion unit 3 sets the first inversion information IV (IV10-IV13) assigned corresponding to the first partial data DT whose logic is inverted to the valid state (for example, logic 1). Then, the first inversion unit 3 outputs the first partial data DT10-DT13 and the inversion information IV10-IV13 to the transmission unit 4.

The second inversion unit 2 calculates the number of changes in the bit value of the data DT predicted to be transmitted this time with respect to the previously transmitted data DT. Although not shown, the second inversion unit 2 may receive the previously transmitted data DT from the first inversion unit 3. The second inversion unit 2 determines whether the number of changes in the bit value exceeds half of the number of bits in the second partial data DT (DT20-DT23) in which the data DT is divided into a plurality of parts as compared with the previous transmission. .. In FIG. 1, the number of the first partial data DT and the number of the second partial data DT are equal to each other. For example, the number of the second partial data DT is the number of the first partial data DT. It may be more than the number. In the example shown in FIG. 1, the relationship of data DT = first partial data DT10-DT13 = second partial data DT20-DT23 is established.

The second inversion unit 2 is attached to the first inversion unit 3 according to the ratio of the second partial data DT in which the number of changes in the bit value exceeds half of the number of bits among the plurality of second partial data DTs. It is determined whether to invert the logic of the second partial data DT to be supplied. For example, when the ratio exceeds 0.5, the second inversion unit 2 inverts the logic of the second partial data DT supplied to the first inversion unit 3. When the logic of the second partial data DT is inverted, the second inversion unit 2 sets the second inversion information IV2 to the valid state (for example, the logic 1).

In the following, the first reversing unit 3 sets the first reversing information IV10-IV12 of the reversing information IV10-IV13 to the valid state based on the determination result, and sets the first reversing information IV set to the valid state. It is assumed that the logic of the corresponding first partial data DT10-DT12 is reversed. In this case, for example, in the second inversion unit 2, when the number of changes in the bit value of the second partial data DT20-DT22 corresponding to the first partial data DT10-DT12 exceeds half as compared with the previous transmission. judge.

That is, the second inversion unit 2 determines that the ratio of the number of the second partial data DTs in which the number of changes in the bit value exceeds half exceeds 50%. In this example, in 75% of the second partial data DT, the number of changes in the bit value exceeds half. The second inversion unit 2 inverts in advance the logic of the second partial data DT supplied to the first inversion unit 3 when the number of changes in the bit value exceeds half in the majority of the second partial data DT. ..

The first inversion unit 3 determines that among the received second partial data DTs, there is no second partial data DT in which the number of changes in the bit value exceeds half, and the logic of the first inversion information IV10-IV12. Keeps disabled. As a result, it is possible to prevent the logic of the first partial data DT10-DT12 from being inverted and the logic of the inverted information IV10-IV12 being inverted to the valid state.

The transmission unit 4 transmits, for example, the first partial data DT10-DT13 generated by the first inversion unit 3 and the first inversion information IV10-IV13, and the second inversion unit 2 generates the second inversion information IV10-IV13. Inversion information IV2 of is transmitted. The second inversion information IV2 may be directly output to the transmission unit 4 without passing through the first inversion unit 3.

For example, when the transmission unit 4 transmits additional information having a predetermined number of bits for which the purpose is not defined, in addition to the first partial data DT and the first inversion information IV, the second inversion information IV2 is included in the additional information. Will be sent. When the semiconductor device 1a has a code generation unit that generates an error detection / correction code of the first partial data DT, the transmission unit 4 transmits the error detection / correction code as a part of the additional information, and the second The inverted information IV of the above may be transmitted as another part of the additional information.

In this embodiment, since the number of the first inversion information IV whose logic is inverted can be reduced by the operation of the second inversion unit 2, the signal transmitted from the semiconductor device 1a to the semiconductor device 1b can be reduced. The number of bits whose logic changes can be reduced. Further, the second inversion information IV2 is transmitted together with the first partial data DT10-DT13 and the first inversion information IV10-IV13. In other words, there is no new cycle for transferring the second inversion information IV2 to the semiconductor device 1b. Therefore, the power consumption of the interface portion of the semiconductor devices 1a and 1b can be reduced without lowering the transmission efficiency of the data DT.

On the other hand, the receiving unit 5 receives the first inverted information IV10-IV13 and the second inverted information IV2 together with the first partial data DT10-DT13 from the semiconductor device 1b from which the data is transmitted. The receiving unit 5 outputs the received first partial data DT10-DT13, the first inverted information IV10-IV13, and the second inverted information IV2 to the third inverted unit 6. The second inversion information IV2 may be directly output to the fourth inversion unit 7 without passing through the third inversion unit 6.

The third reversing unit 6 corresponds to the first reversing information IV in the valid state based on the first partial data DT10-DT13 received from the receiving unit 5 and the first reversing information IV10-IV13. The logic of the partial data DT of is reversed. The third inversion unit 6 outputs the data DT including the first partial data DT whose logic is inverted to the fourth inversion unit 7 as the second partial data DT20-DT23.

The fourth inversion unit 7 inverts the logic of the second partial data DT corresponding to the second inversion information IV in the valid state based on the second inversion information VI2 received from the transmission source semiconductor device 1b. As a result, the data DT received from the semiconductor device 1b of the transmission source is generated.

As described above, in the embodiment shown in FIG. 1, the number of first inversion information IV whose logic is inverted can be reduced, and the number of bits whose logic changes in the signal transmitted from the semiconductor device 1a to the semiconductor device 1b. Can be reduced. As a result, the charge / discharge amount can be reduced and the power consumption of the system 100 can be reduced without providing a new signal line for transmitting the inverted information IV in the transmission line between the semiconductor devices 1a and 1b. .. Further, since the first inversion information IV and the second inversion information IV are transmitted and received together with the first partial data DT, the interface portion of the semiconductor devices 1a and 1b is consumed without lowering the transmission efficiency of the data DT. Power can be reduced.

FIG. 2 shows an example of a system-in-package with semiconductor devices in another embodiment. The system-in-package 102 shown in FIG. 2 includes a stacked memory 30 in which a plurality of memory chips 10 and one logic chip 20 are laminated, a processor chip 40, a silicon interposer 50, and a package substrate 60. The processor chip 40 and the stacked memory 30 are examples of semiconductor devices. The number of stacked memory chips 10 is not limited to four. Hereinafter, the processor chip 40 and the stacked memory 30 are also referred to as devices.

For example, the memory chip 10 and the logic chip 20 each have a TSV (Through-Silicon Via), and the memory chip 10 and the logic chip 20 are connected to each other via bumps and TSVs. FIG. 2 shows the system-in-package 102 viewed from the side, with bumps indicated by circles. The logic chip 20 has an input / output interface unit PHY for inputting / outputting signals to / from the processor chip 40.

For example, the processor chip 40 is a GPU (Graphics Processing Unit), a CPU, a SoC (System on a Chip), or the like, and has an input / output interface unit PHY for inputting / outputting signals to / from the logic chip 20. .. The input / output interface PHY of the processor chip 40 and the input / output interface PHY of the logic chip 20 are connected to each other via a silicon interposer 50.

The logic chip 20 of the stacked memory 30 is connected to the silicon interposer 50 via bumps, and the processor chip 40 is connected to the silicon interposer 50 via bumps. A part of the external terminal (bump) of the logic chip 20 and a part of the external terminal (bump) of the processor chip 40 are connected to the package substrate 60 via the silicon interposer 50. In the package substrate 60, the bump shown on the lower side of FIG. 2 is connected to, for example, a motherboard or the like of an information processing device or the like (server or the like) (not shown).

FIG. 3 shows an example of the configuration of data transmitted / received between the stacked memory 30 of FIG. 2 and the processor chip 40.

The processor chip 40 shown in FIG. 2 issues a read access request or a write access request to the stacked memory 30. The stacked memory 30 shown in FIG. 2 has a burst function of continuously outputting read data for four cycles based on reception of an address (for example, a column address) included in a read access request (burst length BL =). 4). The processor chip 40 has a burst function of receiving read data output from the stacked memory 30 for four consecutive cycles. Therefore, FIG. 3 shows the data output from the stacked memory in four cycles by one burst operation corresponding to the read access request.

Further, the processor chip 40 outputs the write data to the stacked memory 30 together with the write access request including the address of the data write destination. In the write operation, the processor chip 40 has a burst function of continuously outputting write data to the stacked memory 30 for four cycles based on the column address, similar to the read operation. The stacked memory 30 has a burst function of receiving write data output from the processor chip 40 for four consecutive cycles.

Note that FIG. 3 shows, for example, the data DQ per channel of the stacked memory 30, and 160 bits of data DQ per channel is input / output to and from the stacked memory 30 in each memory access cycle. For example, when the stacked memory 30 has 8 channels, eight times as many data DQs as shown in FIG. 3 are transmitted and received between the stacked memory 30 and the processor chip 40. The 160-bit data DQ corresponding to one channel includes 128-bit data DQ (data itself on which information processing is performed), 16-bit inverted bit DBI (Data Bus Inversion), and 8-bit data mask DM (8-bit data mask DM). Data Mask) and included. Hereinafter, the area in which the data mask DM is set is also referred to as a data mask area DM, and the bit set in the data mask area DM is also referred to as a data mask bit DM. The data mask DM is an example of additional information. Half of the 160-bit data shown in bold is assigned as a Pseudo Channel. That is, one channel of data includes two puddle channels.

One inverting bit DBI is provided for every 8-bit data DQ. The device that transmits the data DQ sets the inverting bit DBI to logic 0 when transmitting the 8-bit data DQ without inverting the logic, and the inverting bit when transmitting the 8-bit data logic in inverting. Set DBI to logic 1. Here, the device that transmits the data DQ is the logic chip 20 or the processor chip 40. The logic of the inverted bit DBI ("0" or "1") is, for example, the bit value of the data DQ and the inverted bit DBI transmitted this time with respect to the logic of the data DQ and the inverted bit DBI transmitted in the previous cycle. It is set to the one where the change in the logic of is small.

For example, in an 8-bit data DQ, when the number of bits whose logic changes compared to the previous cycle is 5 bits or more, the logic of the output data DQ is inverted and the inverted bit DBI is set to logic 1. To. Further, when the number of bits whose logic changes in the 8-bit data DQ is 4 bits and the inverted bit DBI is logical 1, the logic of the output data DQ is inverted and the inverted bit DBI is set to logical 1. .. In other cases, the logic of the data DQ to be output is left as it is, and the inverting bit DBI is set to logic 0.

As a result, the number of bits whose logic changes can always be 4 bits or less out of a total of 9 bits of 8-bit data DQ and 1-bit inversion bit DBI. Of the data DQ and the inverting bit DBI transmitted on the data line between the devices 30 and 40, the interface portion (for example, PHY in FIG. 2) for transmitting and receiving the data DQ by always setting the toggle bit to 4 bits or less. Power consumption can be suppressed.

When the device (logic chip 20 or processor chip 40) that receives the data DQ receives the inverted bit DBI of the logic 1 together with the 8-bit data DQ, it inverts the logic of the received DQ. Further, when the device that receives the data DQ receives the inversion bit DBI of logic 0 together with the 8-bit data DQ, the device does not invert the logic of the received DQ.

In the original usage, the data mask DM is provided with 1 bit for each 8-bit data DQ, and is used to set whether or not to mask the 8-bit data DQ. On the other hand, in the present embodiment, a 24-bit data mask area DM is used for error detection / correction of 256-bit data DQ for two cycles of burst operation. Hereinafter, 256 bits (broken line frame in FIG. 3) for two cycles of burst operation, which is a unit of error detection / correction, will be referred to as an ECC (Error Correction Code) group.

Although not particularly limited, in this embodiment, a block error correction code such as S8EC-D8ED (288,256) is used. Of the 32-bit data mask area DM in the ECC group, 24 bits are used for error detection / correction, so the remaining 8 bits can be used for purposes other than error detection / correction. In the present embodiment, as described with reference to FIG. 4, the remaining 8 bits are used to set an all-inverted bit DAI (Data All Inversion) for reducing the toggle of the inverted bit DBI, thereby performing a data interface. The power consumption of the part can be further reduced.

FIG. 4 shows an example of allocating the fully inverted bit DAI to the data mask area DM. In each cycle of the burst operation described above, a fully inverted bit DAI (DAI0-DAI3) is assigned to each 128-bit data DQ in the free 4-bit data mask area DM. Each of the fully inverted bit DAIs is set corresponding to a 32-bit data DQ and a 4-bit inverted bit DBI assigned to each 8 bits of the 32-bit data DQ.

In the example shown in FIG. 4, the fully inverted bit DAI0 is assigned corresponding to the uppermost 32 bits of the 128-bit data DQ and the 4-bit DBI. All inverting bits DAI1 are assigned corresponding to the second highest 32-bit and 4-bit DBI of the 128-bit data DQ. Further, the fully inverted bit DAI2 is assigned corresponding to the third upper 32 bits and the 4-bit DBI of the 128-bit data DQ. Then, the fully inverted bit DAI3 is assigned corresponding to the lowest 32 bits of the 128-bit data DQ and the 4-bit DBI.

The fully inverted bit DAI of logic 1 indicates that the logic of the corresponding 32-bit data DQ is inverted separately from the inversion by the inversion bit DBI. The fully inverted bit DAI of logic 0 indicates that the logic of the corresponding 32-bit data DQ is not inverted except by inversion by the inversion bit DBI. Therefore, when the received total inversion bit DAI is logic 1, the device on the receiving side of the data DQ inverts the 32-bit data DQ separately from the inversion by the inversion bit DBI. When the received all-inverted bit DAI is logic 0, the device on the receiving side of the data DQ treats the 32-bit data DQ inverted or uninverted by the inverted bit DBI as received data.

The transfer order of the data DQ read from the stacked memory 30 and the data DQ written to the stacked memory 30 by the burst operation is guaranteed within the range of 4-cycle CYC corresponding to the burst length = 4. On the other hand, the data transfer order is not guaranteed between burst operations adjacent to each other. Therefore, in the first cycle CYC0 of the burst operation, the data DQ of the previous cycle CYC to be compared does not exist, and it cannot be determined whether or not the 32-bit data DQ is inverted. Therefore, the free 4 bits of the data mask area DM are used in the cycles CYC1, CYC2, and CYC3, but not in the cycle CYC0.

FIG. 5 shows an example of the processor chip 40 of FIG. The processor chip 40 includes a latch circuit 41, an inverting prediction circuit 42, an inverting processing circuit 43, an ECC generation circuit 44, a DBI inverting circuit 45, a data input / output circuit 46 (PHY), a DBI inverting circuit 47, an ECC correction circuit 48, and an inverting process. It has a circuit 49. The inverting prediction circuit 42 and the inverting processing circuit 43 are examples of the second inverting section, and the DBI inverting circuit 45 is an example of the first inverting section. The data input / output circuit 46 is an example of a transmitting unit and a receiving unit. The DBI inverting circuit 47 is an example of a third inverting unit, and the inverting processing circuit 49 is an example of a fourth inverting unit. The ECC generation circuit 44 is an example of a code generation unit.

The latch circuit 41 holds the inverting bit DBIp and the data DQp output from the inverting processing circuit 43 as the inverting bit DBI and the data DQp transmitted by the processor chip 40 to the stacked memory 30 in the previous cycle CYC. The latch circuit 41 outputs the held inverting bit DBIp and data DQp to the inverting prediction circuit 42.

The inverting prediction circuit 42 operates based on the data DQ (written data) written to the stacked memory 30 and the information of the previous cycle CYC from the latch circuit 41. The inverting prediction circuit 42 determines how many bits the logic of the data DQ transmitted in the current cycle CYC (CYC1, CYC2 or CYC3) is inverted (changed) with respect to the data DQ transmitted in the previous cycle CYC every 8 bits. Ask for.

Then, the inverting prediction circuit 42 predicts whether or not the logic of the inverting bit DBI corresponding to each of the 8-bit data DQs is inverted by the DBI inverting circuit 45. The inversion prediction circuit 42 outputs the predicted inversion number (change number) of the logic of the inversion bit DBI to the inversion processing circuit 43 together with the data DQ.

The inversion processing circuit 43 has a 4-bit inversion bit DBI logic inversion number of 3 bits for every 32 bits (4 bytes) of data DQ based on the inversion number of the inversion bit DBI logic received from the inversion prediction circuit 42. Judge whether or not it is the above. When the number of inversions of the logic of the inversion bit DBI is 3 bits or more, the inversion processing circuit 43 inverts the logic of the corresponding 32-bit data DQ and generates the all-inverted bit DAI of the logic 1. When the number of inversions of the logic of the inversion bit DBI is 2 bits or less, the inversion processing circuit 43 does not invert the logic of the corresponding 32-bit data DQ, and generates all inversion bits DAI of logic 0. The fully inverted bit DAI is an example of the second inverted information.

Here, the inverting processing circuit 43 generates a total inverting bit DAI (DAI0-DAI3) for every 32 bits of the 128-bit data DQ transmitted in each cycle CYC. Then, the inverting processing circuit 43 outputs the generated total inverting bit DAI to the ECC generation circuit 44 together with the data DQ processed in the inverting processing circuit 43. Further, the inverting processing circuit 43 outputs the predicted value of the inverting bit DBI generated by the DBI inverting circuit 45 corresponding to the data DQ processed in the inverting processing circuit 43 to the latch circuit 41 as the inverting bit DBIp. Further, the inverting processing circuit 43 outputs the predicted value of the transmission data DQ generated by the DBI inverting circuit 45 together with the inverting bit DBI as the transmission data DQp to the latch circuit 41.

The ECC generation circuit 44 generates a 24-bit error detection / correction code based on the data DQ received from the inverting processing circuit 43, and uses the generated error detection / correction code together with the data DQ and the total inverting bit DAI as a DBI inverting circuit. Output to 45. Here, the ECC generation circuit 44 generates an error detection / correction code in units of 256-bit data DQ in the ECC group shown in FIG.

The DBI inverting circuit 45 generates an inverting bit DBI for each 8-bit data DQ based on the data DQ received via the ECC generation circuit 44, and when the generated inverting bit DBI is logic 1, the corresponding data DQ Invert the logic of. The inverting bit DBI is an example of the first inverting information. The DBI inversion circuit 45 does not invert the logic of the corresponding data DQ when the generated inversion bit DBI is logic 0. Then, the DBI inverting circuit 45 outputs the generated inverting bit DBI and the data DQ processed based on the inverting bit DBI to the data input / output circuit 46.

Further, the DBI inverting circuit 45 includes an error detection / correction code (24-bit data mask bit DM) generated by the ECC generation circuit 44 and a total inverting bit DAI (data mask bit of the remaining 8 bits) generated by the inverting processing circuit 43. DM) is output to the data input / output circuit 46. For example, the DBI inverting circuit 45 may output the data DQ or the like to the data input / output circuit 46 every one cycle (160 bits).

The data input / output circuit 46 sequentially transfers the data DQ, the inverting bit DBI, the error detection / correction code, and the total inverting bit DAI received from the DBI inverting circuit 45 to the stacked memory 30. Further, the data input / output circuit 46 outputs the data DQ, the inverting bit DBI, the error detection / correction code, and the all inverting bit DAI sequentially received from the stacked memory 30 to the DBI inverting circuit 47.

The DBI inverting circuit 47 inverts the data DQ based on the inverting bit DBI received from the data input / output circuit 46, or outputs the data DQ to the ECC correction circuit 48 without inverting the data DQ. Further, the DBI inverting circuit 47 outputs the error detection / correction code and the total inverting bit DAI received from the data input / output circuit 46 to the ECC correction circuit 48.

The ECC correction circuit 48 detects an error in the data DQ processed by the DBI inversion circuit 47 using an error detection / correction code, and if there is an error in the data DQ, corrects the error and outputs it to the inversion processing circuit 49. To do. The ECC correction circuit 48 outputs the fully inverted bit DAI received from the data input / output circuit 46 to the inverting processing circuit 49.

The inverting process circuit 49 performs a process of inverting the logic of the data DQ received from the ECC correction circuit 48 based on the total inverting bit DAI. When the all-inverted bit DAI is logic 1, the inversion processing circuit 49 inverts the logic of the 32-bit data DQ corresponding to the all-inverted bit DAI and outputs it as read data. When the all-inverted bit DAI is logic 0, the inverting processing circuit 49 outputs the logic of the 32-bit data DQ corresponding to the all-inverted bit DAI as read data as it is without inverting the logic.

Each element represented by reference numerals 41 to 49 included in the processor chip 40 shown in FIG. 5 is also mounted on the stacked memory 30. That is, an example of the stacked memory 30 is shown by using the processor chip 40 of FIG. 5 as the stacked memory 30, the stacked memory 30 of FIG. 5 as the processor chip 40, the write data as the read data, and the read data as the write data. Is done.

In this case, the stacked memory 30 together with the data DQ to be transmitted to the processor chip 40 by using the latch circuit 41, the inverting prediction circuit 42, the inverting processing circuit 43, the ECC generation circuit 44, the DBI inverting circuit 45, and the data input / output circuit 46. , Generates information associated with the data DQ. Further, the stacked memory 30 restores the data received from the processor chip 40 by using the data input / output circuit 46, the DBI inverting circuit 47, the ECC correction circuit 48, and the inverting processing circuit 49.

FIG. 6 shows an example of data DQ transmitted from the processor chip 40 of FIG. 2 to the stacked memory 30. For the sake of clarity, FIG. 6 shows a 32-bit (4 byte) data DQ of the 128-bit (16-byte) data DQ transferred in each cycle CYC. Actually, the process shown in FIG. 6 is executed four times corresponding to the 128-bit (16 bytes) data DQ for each cycle CYC. In the unit of error detection / correction, 256 bits (32 bytes) of data are transferred every two cycles of CYC. In FIG. 6, the description of the processing of the ECC generation circuit 44 and the ECC correction circuit 48 will be omitted. When the data DQ is transferred from the stacked memory 30 to the processor chip 40, the same process as in FIG. 6 is executed.

The “transmission data one cycle before” in FIG. 6A shows the data DQ and the inverting bit DBI transmitted by the data input / output circuit 46 to the stacked memory 30 in the cycle CYC0 when the data DQ is transmitted in the cycle CYC1. .. Further, the "transmission data one cycle before" indicates the data DQ and the inversion bit DBI transmitted by the data input / output circuit 46 to the stacked memory 30 in the cycle CYC2 when the data DQ is transmitted in the cycle CYC3.

The “data to be transmitted in the cycle” in FIG. 6B is data generated by the processor chip 40 by arithmetic processing or the like, and is data actually written in the stacked memory 30. In other words, the logic of "data to be transmitted in the cycle" may be different from the logic of data DQ transmitted (output) from the processor chip 40 to the stacked memory 30. Also in the following description, the logic of "data to be transmitted" is the logic of data DQ handled by the device that receives the data DQ, and the logic of "data to be transmitted" is on the transmission path to the device that receives the data DQ. This is the logic of the data DQ to be transmitted.

The “number of inverted bits of DQ and DBI” in FIG. 6C is calculated by the inverted prediction circuit 42 of FIG. 5, and each byte of the data DQ to be transmitted in the cycle and the inverted bit DBI are transmitted one cycle before. It shows how many bits change from the data DQ and the inverted bit DBI. Each byte of the data DQ is an example of the second partial data in which the data DQ to be transmitted is divided into a plurality of parts. The numbers in parentheses indicate whether or not the DBI inversion circuit 45 inverts the data DQ. The inverting prediction circuit 42 outputs the calculated number of inverting bits for each byte to the inverting processing circuit 43. The inversion prediction circuit 42 may output information indicating "with inversion" and "without inversion" to the inversion processing circuit 43 for each byte.

As described above, the DBI inverting circuit 45 determines that the logic of the data DQ is inverted when, for example, the number of bits of the data DQ whose logic changes is 5 bits or more. Further, the DBI inverting circuit 45 determines that the logic of the data DQ is inverted when the number of bits of the data DQ whose logic changes is 4 bits and the inverting bit DBI one cycle before is logic 1.

Based on the information from the inverting prediction circuit 42, the inverting processing circuit 43 sets the total inverting bit DAI to logic 1 when the inverting of the data DQ by the DBI inverting circuit 45 is 3 bytes or more among the 4-byte data DQ. To do. Further, based on the information from the inverting prediction circuit 42, the inverting processing circuit 43 logically sets the all inverting bit DAI to 0 when the inverting of the data DQ by the DBI inverting circuit 45 is 2 bytes or less among the 4-byte data DQ. Set to.

In other words, for example, the inverting processing circuit 43 sets all inverting bits DAI to logic 1 when the ratio of the number of inverting bits DBI set in logic 1 by the DBI inverting circuit 45 exceeds half (50%). .. When the ratio of the number of inverting bits DBI set in logic 1 by the DBI inverting circuit 45 is less than half (50%), the inverting processing circuit 43 sets all inverting bits DAI to logic 0.

However, in the inverting prediction circuit 42, the number of inverting bits of the data DQ, the inverting bit DBI, and the inverting bit DAI when the logic 1 of the all inverting bit DAI is set is larger than that when the logic 0 of the all inverting bit DAI is set. If so, the fully inverted bit DAI is set to logical 0. As a result, not only the data DQ transmitted one cycle before, but also the total number of changes in the logic of the data DQ, the inverted bit DBI, and the totally inverted bit DAI can be reduced, and the power consumption of the interface portion of the data DQ can be further reduced. can do. An example of exceptionally setting the all-inverted bit DAI to logic 0 will be described with reference to FIG.

In FIG. 6C, it is expected that the data DQ is inverted by 3 bytes or more by the DBI inversion circuit 45. Therefore, in FIG. 6D, the inversion processing circuit 43 inverts the logic of each byte of the data to be transmitted in the cycle of FIG. 6B, and sets the all-inverted bit DAI to logic 1.

In FIG. 6E, the DBI inverting circuit 45 determines how many bits the logic of the data DQ is inverted for each byte with respect to the data DQ transmitted one cycle before, based on the data DQ received from the inverting processing circuit 43. Judge to. Bits whose logic is inverted are underlined. The byte determined by the DBI inverting circuit 45 is an example of the first partial data.

Then, the DBI inverting circuit 45 determines the logic of the data DQ to be transmitted in the cycle and the inverting bit DBI byte by byte according to the determination result. In the example of FIG. 6, since the number of inverting bits for the logic of the data DQ transmitted one cycle before is 4 bits or less in each byte, the DBI inverting circuit 45 does not invert the data DQ of each byte. The inverting bit DBI corresponding to each byte is set to logical 0.

That is, as described with reference to FIGS. 6 (i) to 6 (m), when the fully inverted bit DAI is logic 0, the three inverted bits DBI are set to logic 1, whereas the fully inverted bit DAI is set. Can be maintained at logic 0 by setting the inverting bit DBI to logic 1. As a result, the number of changes in the logic of the signal transmitted between the devices can be reduced, and the power consumption can be reduced.

Then, the DBI inverting circuit 45 outputs the determined logic data DQ and the inverting bit DBI to the data input / output circuit 46 via the ECC generation circuit 44. The data input / output circuit 46 transmits the data DQ and the inverting bit DBI generated by the DBI inverting circuit 45 and the fully inverting bit DAI generated by the inverting processing circuit 43 to the stacked memory 30.

FIG. 6 (f) shows the number of inverted bits of the data DQ, the inverted bit DBI, and the total inverted bit DAI, which are the transmission data of FIG. 6 (e) with respect to one cycle before. In this example, the total number of inverted bits corresponding to the 32-bit data DQ is 14 bits.

FIG. 6 (g) shows the logic of the data DQ output by the DBI inverting circuit 47 provided in the logic chip 20 of the stacked memory 30 that has received the data DQ and the like from the processor chip 40 byte by byte. As shown in FIG. 6E, since the inverting bit DBI of each byte has logic 0, the DBI inverting circuit 47 outputs the logic of the data DQ received from the processor chip 40 as it is.

FIG. 6H shows the logic of the data DQ output by the inverting processing circuit 49 provided in the logic chip 20 of the stacked memory 30 byte by byte. The inverting processing circuit 49 inverts and outputs the logic of the data DQ output by the DBI inverting circuit 47 based on the all-inverted bit DAI of the logic 1 received from the processor chip 40. As a result, the "data to be transmitted in the cycle" shown in FIG. 6B is written in the stacked memory 30.

6 (i) to 6 (m) show an example of data DQ transferred from the processor chip 40 to the stacked memory 30 when the fully inverted bit DAI is set to logic 0. In FIG. 6 (i), the inverting processing circuit 43 outputs the logic of the “data transmitted in the cycle” of FIG. 6 (b) to the DBI inverting circuit 45 as it is.

In FIG. 6 (j), similarly to FIG. 6 (e), the DBI inverting circuit 45 transmits the data DQ in the cycle according to the number of bits whose logic changes with respect to the data DQ transmitted one cycle before. Determines the logic of and the inverted bit DBI. Also in FIG. 6 (j), the bits whose logic is inverted are underlined. In the example of FIG. 6, for bytes 3, bytes 2, and bytes 1 whose logic is inverted by 5 bits, the logic of the data DQ is inverted, and the inverted bit DBI is set to logic 1. For byte 0 in which the logic is inverted by 4 bits, the logic of the original data DQ is set in the transmission data, and the inversion bit DBI is set in logic 0.

In this case, as shown in FIG. 6 (k), the total number of inverting bits corresponding to the 32-bit data DQ is 16 bits, and the logic is inverted when the all inverting bits DAI are set to logic 1. The number will decrease. Therefore, the transfer of the data DQ from the processor chip 40 to the stacked memory 30 is carried out according to FIGS. 6A to 6H.

In FIG. 6 (l), similarly to FIG. 6 (g), the DBI inverting circuit 47 provided in the logic chip 20 of the stacked memory 30 determines the logic of the received data DQ based on the logic of the received inverting bit DBI. Generate. When the total inverting bit DAI is logic 0, the DBI inverting circuit 47 outputs the data DQ of the logic shown in "data to be transmitted in the cycle" shown in FIG. 6 (b).

In FIG. 6M, since the all-inverted bit DAI is logic 0, the inverting processing circuit 49 provided in the logic chip 20 of the stacked memory 30 outputs the logic of the data DQ received from the DBI inverting circuit 47 as it is. Then, "data to be transmitted in the cycle" is written in the stacked memory 30.

FIG. 7 shows another example of the data DQ transmitted from the processor chip 40 of FIG. 2 to the stacked memory 30. A detailed description of the same processing as in FIG. 6 will be omitted. When the data DQ is transferred from the stacked memory 30 to the processor chip 40, the same process as in FIG. 7 is executed. In FIG. 7, the logic of the data DQ of the “transmission data one cycle before” in FIG. 7A and the inversion bit DBI is different from that in FIG. 6A. Further, the logic of the data DQ of "data to be transmitted in the cycle" in FIG. 7 (b) is different from that in FIG. 6 (b).

In FIG. 7C, the inversion prediction circuit 42 determines that bytes 3 to 1 are inverted, byte 0 is determined not to be inverted, and outputs the number of inverted bits of each byte to the inversion processing circuit 43 together with the data DQ. To do. As shown in FIG. 7 (c), it is expected that the data DQ is inverted by 3 bytes or more by the DBI inversion circuit 45. Therefore, in FIG. 7 (d), the inversion processing circuit 43 "data to be transmitted in the cycle". The logic of each byte of "is inverted, and the fully inverted bit DAI is set to logic 1.

In FIG. 7 (e), similarly to FIG. 6 (e), the DBI inverting circuit 45 has data in bytes 3 to 1 in which the number of inverting bits with respect to the logic of the data DQ transmitted one cycle before is 4 bits or less. The inverted bit DBI corresponding to each byte is set to logical 0 without inverting the DQ. On the other hand, the DBI inverting circuit 45 inverts the data DQ and sets the corresponding inverting bit DBI to logic 1 at byte 0 where the number of inverting bits with respect to the logic of the data DQ transmitted one cycle before is 5 bits or more. The data DQ and the inverting bit DBI generated by the DBI inverting circuit 45 are output to the data input / output circuit 46 via the ECC generation circuit 44. The data input / output circuit 46 transmits the data DQ and the inverting bit DBI generated by the DBI inverting circuit 45 and the fully inverting bit DAI generated by the inverting processing circuit 43 to the stacked memory 30.

As shown in FIG. 7 (f), the total number of inverted bits of the 32-bit data DQ, the inverted bit DBI corresponding to each byte of the data DQ, and the total inverted bit DAI with respect to one cycle before is 12 bits.

In FIG. 7 (g), the DBI inverting circuit 47 provided in the logic chip 20 of the stacked memory 30 outputs the logic of the data DQ as it is in bytes 3 to 1 in which the inverting bit DBI is logic 0. The DBI inversion circuit 47 inverts the logic of the data DQ and outputs it when the inversion bit DBI is byte 0 of the logic 1.

In FIG. 7 (h), the inverting processing circuit 49 provided in the logic chip 20 of the stacked memory 30 inverts the logic of the data DQ output by the DBI inverting circuit 47 based on the all inverting bits DAI of the logic 1 and outputs the logic. To do. As a result, similarly to FIG. 6, "data to be transmitted in the cycle" shown in FIG. 7B is written in the stacked memory 30.

7 (i) to 7 (m) show an example of data DQ transferred from the processor chip 40 to the stacked memory 30 when the fully inverted bit DAI is set to logic 0. As shown in FIG. 7 (k), when the fully inverted bit DAI is set to logic 0, the total number of inverted bits corresponding to the 32-bit data DQ is 16 bits, and the fully inverted bit DAI is set to logic 1. The number of bits for which the logic is inverted is smaller when set. Therefore, the transfer of the data DQ from the processor chip 40 to the stacked memory 30 is carried out according to FIGS. 7 (a) to 7 (h).

FIG. 8 shows yet another example of data DQ transmitted from the processor chip 40 of FIG. 2 to the stacked memory 30. A detailed description of the same processing as in FIG. 6 will be omitted. In FIG. 8, the logic of the inverted bit DBI of bytes 3 to 2 of the “transmission data one cycle before” in FIG. 8A is different from that in FIG. 6A. The logic of the data DQ of "data to be transmitted in the cycle" in FIG. 8 (b) is the same as that in FIG. 6 (b). When the data DQ is transferred from the stacked memory 30 to the processor chip 40, the same process as in FIG. 8 is executed.

Since the logic of the data DQ in FIGS. 8 (a) and 8 (b) is the same as that in FIGS. 6 (a) and 6 (b), the number of inverted bits in FIG. 8 (c) is FIG. 6 (c). ) Is the same. 8 (d) is the same as FIG. 6 (d), and FIG. 8 (e) is the same as FIG. 6 (e). However, since the logic of the inverted bit DBI of bytes 3 to 2 is different from the logic of the inverted bit DBI of "transmission data one cycle before", the number of inverted bits in FIG. 8 (f) is 2 bits larger than that in FIG. It becomes 16 bits. 8 (g) and 8 (h) are the same as FIGS. 6 (g) and 6 (h), respectively.

On the other hand, in FIGS. 8 (i) to 8 (m) in which the all inversion bits DAI are set to logic 0, FIGS. 6 (i) to 6 (m) except that the number of inversion bits in FIG. 8 (k) is different. ) Is the same. In FIG. 8 (k), the logic of the inverted bit DBI of bytes 3 to 2 is the same as the logic of the inverted bit DBI of "transmission data one cycle before", so that the total number of inverted bits is shown in FIG. It becomes "14" which is two less than k). As a result, it is possible to reduce the total number of inverted bits by setting the all-inverted bit DAI to logic 0 as compared to setting the all-inverted bit DAI to logic 1.

Therefore, the inverting processing circuit 43 outputs the logic shown in FIG. 8 (i) to the DBI inverting circuit 45 instead of the logic shown in FIG. 8 (d). The DBI inverting circuit 45 outputs not the logic shown in FIG. 8 (e) but the logic shown in FIG. 8 (j) toward the stacked memory 30.

In this way, even when the inversion of the data DQ by the DBI inversion circuit 45 is 3 bytes or more, the number of inversion bits of the data or the like output from the data input / output circuit 46 is larger than that in the case where the total inversion bit DAI is logic 0. , The fully inverted bit DAI is set to logical 0. In other words, even when 3 or more bits of the inverting bit DBI are set to logic 1, if the total number of signals whose logic is inverted increases compared to the previous transmission, the all inverting bits DAI are set to logic 0. .. As a result, as described above, the total number of changes in the logic of the data DQ, the inverting bit DBI, and the total inverting bit DAI can be reduced, and the power consumption of the interface portion of the data DQ can be further reduced.

FIG. 9 shows an example of the operation when the processor chip 40 of FIG. 2 transmits data DQ to the stacked memory 30. Note that FIG. 9 also shows an example of the operation of the stacked memory 30 that transmits data DQ to the processor chip 40. That is, FIG. 9 shows an example of a method of transferring the write data DQ to the stacked memory 30 by the processor chip 40 and a method of transferring the read data DQ to the processor chip 40 by the stacked memory 30.

An example in which the stacked memory 30 transfers data DQ to the processor chip 40 will be described by replacing the "processor chip 40" in the following description with the "stacked memory 30". The operation shown in FIG. 9 is started based on the start of the burst operation. The operation shown in FIG. 9 is executed for each 32-bit data DQ, and in one cycle of 128-bit data DQ, the operation shown in FIG. 9 is executed four times in parallel.

First, in step S10, the processor chip 40 shifts the operation to step S24 in the case of the burst operation cycle CYC0, and shifts the operation to step S12 in the case of the burst operation cycle CYC1-CYC3.

In step S12, the inverting prediction circuit 42 of the processor chip 40 calculates the number of bits for which the DBI inverting circuit 45 inverts the logic based on the data DQ one cycle before and the inverting bit DBI held by the latch circuit 41. Here, the number of bits for which the DBI inverting circuit 45 inverts the logic is a predicted value calculated using "data DQ to be transmitted in the cycle" and data DQ transmitted one cycle before, and the DBI inverting circuit 45 Is not the number of bits that actually invert the logic. The inverting prediction circuit 42 outputs the calculated number of bits to the inverting processing circuit 43 in correspondence with each byte.

Next, in step S14, the inversion processing circuit 43 determines whether or not the number of bytes whose logic is inverted by 5 bits or more is 3 bytes or more based on the number of inversion bits received from the inversion prediction circuit 42. That is, the inversion processing circuit 43 determines whether or not the ratio of bytes in which the number of changes in the bit value exceeds half of the number of bits exceeds 50% as compared with the previous transmission. When the number of bytes in which the logic is inverted by 5 bits or more is 3 bytes or more, the operation is shifted to step S16, and when the number of bytes in which the logic is inverted by 5 bits or more is 2 bytes or less, the operation is shifted to step S20.

In step S16, the inverting processing circuit 43 determines whether or not the total number of inverting bits is smaller when the all-inverted bit DAI is set to logic 1 than when the all-inverted bit DAI is set to logic 0. Here, the data DQ, the inverting bit DBI, and the total inverting bit DAI are used to determine the total number of inverted bits.

If the total number of inverted bits is smaller when the all-inverted bit DAI is set to logic 1, the operation is shifted to step S18, and the total number of inverted bits does not decrease even if the all-inverted bit DAI is set to logic 1. , The operation is shifted to step S20.

In step S18, the inversion processing circuit 43 outputs the all-inverted bit DAI of the logic 1 and the data DQ in which the logic of the "data DQ to be transmitted in the cycle" is inverted to the DBI inversion circuit 45, and steps the operation. Move to S22. On the other hand, in step S20, the inverting processing circuit 43 outputs the all-inverted bit DAI of logic 0 and the "data DQ to be transmitted in the cycle" to the DBI inverting circuit 45, and shifts the operation to step S22.

In step S22, the DBI inverting circuit 45 determines whether to invert the logic of the data DQ based on the data DQ received from the inverting processing circuit 43 and the data DQ transmitted one cycle before, and inverts the logic. , The inverting bit DBI is set to logic 1. The DBI inverting circuit 45 outputs the data DQ whose logic is set according to the logic of the inverting bit DBI to the data input / output circuit 46, and shifts the operation to step S24.

In step S24, the data input / output circuit 46 transmits the data DQ and the inverting bit DBI received from the DBI inverting circuit 45 and the fully inverting bit DAI generated by the inverting processing circuit 43, and ends the operation. In the case of the burst operation cycle CYC0, for example, the inverting bit DBI and the fully inverting bit DAI are set to logic 0.

FIG. 10 shows an example of the operation when the processor chip 40 of FIG. 1 receives data DQ from the stacked memory 30. Note that FIG. 10 also shows an example of the operation of the stacked memory 30 that receives the data DQ from the processor chip 40. That is, FIG. 10 shows an example of a method of receiving read data DQ from the stacked memory 30 by the processor chip 40 and a method of receiving write data DQ from the processor chip 40 by the stacked memory 30.

An example in which the stacked memory 30 receives the write data DQ output from the processor chip 40 will be described by replacing the "processor chip 40" in the following description with the "stacked memory 30". The operation shown in FIG. 10 is started based on the start of the burst operation. The operation shown in FIG. 10 is executed for each 32-bit data DQ, and in one cycle of 128-bit data DQ, the operation shown in FIG. 10 is executed four times in parallel.

First, in step S30, the data input / output circuit 46 of the processor chip 40 receives the data DQ, the inverted bit DBI, and the fully inverted bit DAI. Next, in step S32, the processor chip 40 ends the operation in the case of the burst operation cycle CYC0, and shifts the operation to step S34 in the case of the burst operation cycle CYC1-CYC3. In the case of cycle CYC0, the inverting bit DBI and the fully inverting bit DAI are invalid, and the processor chip 40 executes data processing or the like using the data DQ received by the data input / output circuit 46.

In step S34, the DBI inverting circuit 47 of the processor chip 40 inverts the logic of the received data DQ and outputs it to the inverting processing circuit 49 for each byte of the data DQ when the received DBI is logic 1. Next, in step S36, when the received total inversion bit DAI is logic 1, the inverting processing circuit 49 of the processor chip 40 inverts the logic of the received 32-bit data DQ and ends the operation.

As described above, even in the embodiments shown in FIGS. 2 to 10, the same effects as those in the embodiment shown in FIG. 1 can be obtained. For example, the number of inverting bit DBIs whose logic is inverted can be reduced, and the number of bits of a signal whose logic changes can be reduced in the signal transmitted between the devices 30 and 40. As a result, the power consumption of the data input / output circuit 46 can be reduced, and the power consumption of the system-in-package 102 can be reduced. Further, by transmitting the fully inverted bit DAI together with the data DQ in one cycle, it is possible to eliminate the need for a dedicated cycle for transmitting the fully inverted bit DAI. As a result, the power consumption of the data input / output circuit 46 can be reduced without lowering the transmission efficiency of the data DQ.

Further, in the embodiments shown in FIGS. 2 to 10, the following effects can be obtained. For example, in the inverting prediction circuit 42, the number of inverting bits of the data DQ, the inverting bit DBI, and the inverting bit DAI when the logic 1 of the inverting bit DAI is set is larger than that when the logic 0 of the inverting bit DAI is set. If so, the all-inverted bit DAI is set to logical 0. As a result, not only the data DQ transmitted one cycle before but also the total number of changes in the logic of the data DQ, the inverted bit DBI and the fully inverted bit DAI can be reduced, and the power consumption of the interface portion of the data DQ can be further reduced. can do.

Further, by using 8 bits of the data mask bit DM that are not used for the error detection / correction code and setting the fully inverted bit DAI to reduce the toggle of the inverted bit DBI, the interface portion of the data DQ can be set. The power consumption can be further reduced.

FIG. 11 shows an example of allocation of a data mask area in the semiconductor device of another embodiment. Detailed description of the contents similar to those described with reference to FIGS. 2 to 10 will be omitted. For example, the semiconductor device to which the data mask area allocation of FIG. 11 is applied is the processor chip 40A or the stacked memory 30A (FIG. 12) mounted on the system-in-package 102, as in FIG. That is, the processor chip 40A can be mounted in the system-in-package 102 instead of the processor chip 40 of FIG.

In FIG. 11, the four 64-bit data DQs in the ECC group are divided into main groups A, B, C, D, E, F, G, and H of 32 bits each. For example, the data DQs of the main groups A, B, C, and D are the data DQs transmitted and received in the burst operation cycles CYC0 and CYC2, and the data DQs of the main groups E, F, G, and H are the burst operation cycles. It is a data DQ transmitted and received by CYC1 and CYC3.

Further, each main group AH is divided into eight subgroups S (S0, S1, S2, S3, S4, S5, S6, S7) of 4 bits each. The data of the subgroups S0-S7 is an example of the second partial data. On the other hand, in the data mask area DM, the empty bits that are not used for the error detection / correction code are used as follows. A 2-bit basic inversion pattern BRP [1: 0] is assigned to the empty 4 bits of the cycle CYC0. The inverting bits RB-E, RB-F, RB-G, and RB-H (1 bits each) of the main groups E, F, G, and H are assigned to the empty 4 bits of the cycle CYC1.

The inverting bits RB-A, RB-B, RB-C, and RB-D (1 bits each) of the main groups A, B, C, and D are assigned to the empty 4 bits of the cycle CYC2. Similar to cycle CYC1, the empty 4 bits of cycle CYC3 have inverted bits RB-E, RB-F, RB-G, and RB-H (1 bit each) of the main groups E, F, G, and H, respectively. Assigned.

Hereinafter, when the inverting bits RB-A, RB-B, RB-C, RB-D, RB-E, RB-F, RB-G, and RB-H are described without distinction, they are referred to as inverting bits RB. The basic inversion pattern BRP is an example of group identification information, the inversion bit RB is an example of inversion pair information, and the basic inversion pattern BRP and the inversion bit RB are an example of the second inversion information.

An example of how the transmitted / received data is controlled by the basic inversion pattern BRP and the inversion bit RB assigned to the data mask area DM shown in FIG. 11 will be described with reference to FIG.

FIG. 12 shows an example of the processor chip 40A to which the allocation of the data mask area DM of FIG. 11 is applied. The same elements as those of the processor chip 40 of FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted. The processor chip 40A includes an inverting processing circuit 43A, an ECC generation circuit 44, a DBI inverting circuit 45, a data input / output circuit 46 (PHY), a DBI inverting circuit 47, an ECC correction circuit 48, and an inverting processing circuit 49A. The inverting processing circuit 43A is an example of a second determination unit, and the inverting processing circuit 49A is an example of a fourth inverting unit.

The inverting processing circuit 43A determines the logic of the data DQ to be transmitted for each cycle CYC for the 512-bit data DQ transferred in one burst operation using the four cycles CYC0-CYC3. In order to determine the logic of the data DQ to be transmitted for each unit of burst operation, the inversion processing circuit 43A operates based on the reception of 512-bit data DQ (data by writing). An example of the operation of the inverting processing circuit 43A will be described with reference to FIGS. 13 and 14.

The ECC generation circuit 44, the DBI inverting circuit 45, the data input / output circuit 46, the DBI inverting circuit 47, and the ECC correction circuit 48 are the ECC generation circuit 44, the DBI inverting circuit 45, the data input / output circuit 46, and the DBI inverting circuit 47 of FIG. And has the same function as the ECC correction circuit 48.

The inverting process circuit 49A performs a process of inverting the logic of the data DQ received from the ECC correction circuit 48 for each subgroup S based on the basic inverting pattern BRP and the inverting bit RB. When the basic inversion pattern BRP is "00", the inversion processing circuit 49A inverts the logic of the data DQ corresponding to the inversion bit RB of the logic 1 among the data DQ belonging to the even numbered subgroup S, and reads out the data DQ. Output as. When the basic inversion pattern BRP is "10", the inversion processing circuit 49A inverts the logic of the data DQ corresponding to the inversion bit RB of the logic 1 among the data DQ belonging to the odd-numbered subgroup S, and reads out the data DQ. Output as. When the basic inversion pattern BRP is "11" (invalid information), the inverting processing circuit 49A outputs the read data DQ without changing the logic of the received data DQ.

The even-numbered subgroups S0, S2, S4, and S6 are examples of the first group (even-numbered group), and the odd-numbered subgroups S1, S3, S5, and S7 are of the second group (odd-numbered group). This is an example. Each of the subgroups S0 / S1, S2 / S3, S4 / S5, and S6 / S7 is an example of a partial data pair. The even-numbered subgroup S or the odd-numbered subgroup S indicated by the basic inversion pattern BRP [1: 0] is an example of the dominant group.

Each element represented by reference numerals 43A, 44 to 48, and 49A included in the processor chip 40A shown in FIG. 12 is also mounted on the stacked memory 30. That is, an example of the stacked memory 30A is shown by using the processor chip 40A as the stacked memory 30A, the stacked memory 30A as the processor chip 40A, the write data DQ as the read data DQ, and the read data DQ as the write data DQ.

In this case, the stacked memory 30A uses the inverting processing circuit 43A, the ECC generation circuit 44, the DBI inverting circuit 45, and the data input / output circuit 46 to transmit the data DQ to be transmitted to the processor chip 40A and the information accompanying the data DQ. Generate. Further, the stacked memory 30A restores the data received from the processor chip 40 by using the data input / output circuit 46, the DBI inverting circuit 47, the ECC correction circuit 48, and the inverting processing circuit 49A.

FIG. 13 shows an outline of the operation of the processor chip 40A to which the allocation of the data mask area DM of FIG. 11 is applied. FIG. 13 shows a case where 512-bit data DQ is transmitted to the stacked memory 30A in the cycle CYC0-CYC3 in one burst operation.

In the cycle CYC0, the processor chip 40 does not operate the logic of the data DQ to be transmitted in the cycle, but transmits the data to the stacked memory 30A via the DBI inverting circuit 45. The value of the basic inversion pattern BRP transmitted in the cycle CYC0 is determined by the inversion processing circuit 43A before the burst operation is started, as described with reference to FIG.

When the basic inversion pattern BRP is "00" in binary, in the cycle CYC1-CYC3, the data DQ of the even-numbered subgroup S of the main group (any of AH) corresponding to the inversion bit RB of logic 1. Indicates that the logic is reversed. In the example shown in FIG. 13, the logic of the data DQ of the even-numbered subgroup S shown in the thick frame corresponding to the inversion bit RB of the logic 1 is inverted based on the basic inversion pattern BRP of “00”, and the DBI inversion circuit It is transmitted to the stacked memory 30A via 45.

When the basic inversion pattern BRP is "10" in binary, in the cycle CYC1-CYC3, the data DQ of the odd-numbered subgroup S of the main group (any of AH) corresponding to the inversion bit RB of the logic 1. The logic is reversed. When the basic inversion pattern BRP is "11" in binary, in the cycle CYC1-CYC3, the logic inversion of the data DQ in the subgroup unit is not executed, and the same operation as the cycle CYC0 is executed.

The basic inversion pattern BRP of "01" in binary is not used. Therefore, when the basic inversion pattern BRP is "11" or "01" in binary, the same operation as in the case of "11" described above may be executed.

In this embodiment, the inversion processing circuit 43A performs the logic of the data DQ every 16 bits in each of the 32-bit main groups AH based on the tendency of the logic of the 512-bit data DQ to change in each burst operation. You can decide whether or not to flip.

FIG. 14 shows an example of data DQ transmitted from the processor chip 40A to which the allocation of the data mask area DM of FIG. 11 is applied to the stacked memory 30A. The data DQ to be transmitted to the stacked memory 30A is determined by the inverting processing circuit 43A. In FIG. 14, the description of the processing of the ECC generation circuit 44 and the ECC correction circuit 48 will be omitted. When data DQ is transmitted from the stacked memory 30A to the processor chip 40A, the same processing as in FIG. 14 is executed.

The inversion processing circuit 43A compares the logic of the data DQ transmitted in the cycle CYC0 (FIG. 14 (a)) with the logic of the data DQ to be transmitted in the cycle CYC1 (FIG. 14 (b)), and logics each subgroup S. Calculates the number of inverted bits in which is inverted (FIG. 14 (c)). Based on the number of inverting bits, the inverting processing circuit 43A determines which of (determination formula 1) and (determination formula 2) is valid, or whether either (determination formula 1) or (judgment formula 2) is valid. judge.

(Determination formula 1): (Number of inverted bits in S0> 2) & (Number of inverted bits in S1 <2) & (Number of inverted bits in S2> 2) & (Number of inverted bits in S3 <2) & (Inversion of S4) Number of bits> 2) & (Number of inverted bits in S5 <2) & (Number of inverted bits in S6> 2) & (Number of inverted bits in S7 <2)
(Determination formula 2): (Number of inverted bits in S0 <2) & (Number of inverted bits in S1> 2) & (Number of inverted bits in S2 <2) & (Number of inverted bits in S3> 2) & (Inversion of S4) Number of bits <2) & (Number of inverted bits in S5> 2) & (Number of inverted bits in S6 <2) & (Number of inverted bits in S7> 2)

In (judgment formula 1), in all the subgroups S of the even-numbered group, the number of changes in the bit value exceeds half of the number of bits compared to the previous transmission, and in all the subgroups S of the odd-numbered group, the previous transmission is performed. By comparison, it is determined that the number of changes in the bit value is less than half of the number of bits. In (judgment formula 2), in all the subgroups S of the odd-numbered group, the number of changes in the bit value exceeds half of the number of bits compared to the previous transmission, and in all the subgroups S of the even-numbered group, the previous transmission is performed. By comparison, it is determined that the number of changes in the bit value is less than half of the number of bits. Then, when the inversion processing circuit 43A satisfies (determination formula 1) or (determination formula 2), the inversion processing circuit 43A determines that the group in which the number of changes in the bit value exceeds half of the number of bits is the dominant group.

Next, the inversion processing circuit 43A tentatively determines the data DQ to be transmitted in the cycle CYC1 based on the determination results by (determination formula 1) and (determination formula 2) (FIG. 14 (d)).

When the inverting processing circuit 43A determines that (determination formula 1) is valid, the data DQ transmitted in the cycle CYC1 by inverting the logic of the data DQ in which the number of inverted bits of the even-numbered subgroup S is 3 bits or more. To generate. That is, when (judgment formula 1) is valid, among the four even-numbered subgroups S, the data of the subgroup S in which the number of changes in the bit value of the data DQ exceeds half of the number of bits compared to the previous transmission. The logic of DQ is reversed.

When the inversion processing circuit 43A determines that (determination formula 2) is valid, the inversion processing circuit 43A inverts the logic of the data DQ in which the number of inversion bits of the odd-numbered subgroup S is 3 bits or more and transmits the data DQ in the cycle CYC1. Generate. That is, when (judgment formula 2) is valid, among the four odd-numbered subgroups S, the data of the subgroup S in which the number of changes in the bit value of the data DQ exceeds half of the number of bits compared to the previous transmission. The logic of DQ is reversed.

When it is determined that neither (determination formula 1) nor (determination formula 2) is valid, the inverting processing circuit 43A sets the data DQ to be transmitted in the cycle CYC1 as the data DQ to be transmitted in the cycle CYC1.

Next, the inversion processing circuit 43A compares the logic of the data DQ (provisional determination) transmitted in the cycle CYC1 with the logic of the data DQ to be transmitted in the cycle CYC2 (FIG. 14 (e)), and logics each subgroup S. Calculates the number of inverted bits in which is inverted (FIG. 14 (f)). The inverting processing circuit 43A determines whether (determination formula 1) or (determination formula 2) is valid or neither is valid based on the number of inverting bits. Then, the inversion processing circuit 43A tentatively determines the data DQ to be transmitted in the cycle CYC2 by using the determination formula determined to be valid in the same manner as when the data DQ to be transmitted in the cycle CYC1 is determined (FIG. 14 (g)). ).

Next, the inverting processing circuit 43A compares the logic of the data DQ transmitted in the cycle CYC2 (tentative determination) with the logic of the data DQ to be transmitted in the cycle CYC3 (FIG. 14 (h)) in the same manner as described above, and substituting the logic. The number of inverted bits whose logic is inverted is calculated for each group S (FIG. 14 (i)). The inverting processing circuit 43A tentatively determines the data DQ to be transmitted in the cycle CYC3 by using (determination formula 1) and (determination formula 2) in the same manner as described above (FIG. 14 (j)).

Next, the inversion processing circuit 43A inverts the logic of the data DQ of the even-numbered subgroup S when there are two or more cycle CYCs determined by (determination formula 1) to be valid in the cycles CYC1-CYC3. Is determined to be valid, and the basic inversion pattern BRP is set to "00". In this case, the inverting processing circuit 43A sets the inverting bit RB corresponding to the even-numbered subgroup S having an inverting bit number of 3 bits or more in logic 1, and the inverting bit number of the even-numbered subgroup S having 2 bits or less. The inverting bit RB corresponding to is set to logical 0.

When the inverting processing circuit 43A has two or more cycle CYCs determined by (determination formula 2) to be valid among the cycles CYC1-CYC3, it is effective to invert the logic of the data DQ of the odd-numbered subgroup S. Judgment is made, and the basic inversion pattern BRP is set to "10". In this case, the inverting processing circuit 43A sets the inverting bit RB corresponding to the odd-numbered subgroup S having an inverting bit number of 3 bits or more in logic 1, and the inverting bit number is an odd-numbered subgroup S having 2 bits or less. The inverting bit RB corresponding to is set to logical 0.

The inverting processing circuit 43A determines the logic of the data DQ of each subgroup S when the number of cycle CYCs determined to be valid by (determination formula 1) and (judgment formula 2) is one or less among the cycles CYC1-CYC3. It is judged that it is effective not to reverse. Then, the inverting processing circuit 43A sets the basic inverting pattern BRP to "11". In this case, the logic of the inverting bit RB may be set to any.

Then, when the basic inversion pattern BRP is "00", the inversion processing circuit 43A inverts the logic of the data DQ of the even numbered subgroup S having 3 or more inversion bits in the data DQ to be transmitted, and the DBI inversion circuit. Output toward 45. FIG. 14 shows an example when the basic inversion pattern BRP is set to “00”, and the logic of the data DQ of the even-numbered subgroup S in which the number of inverted bits shown underline is 3 or more is inverted. It is supplied to the DBI inverting circuit 45.

When the basic inversion pattern BRP is "10", the inversion processing circuit 43A inverts the logic of the data DQ of the odd number subgroup S having 3 or more inversion bits in the data DQ to be transmitted, and causes the DBI inversion circuit 45. Output toward. When the basic inverting pattern BRP is "11", the inverting processing circuit 43A outputs the data DQ to be transmitted to the DBI inverting circuit 45 as the data DQ to be transmitted without inverting.

FIG. 15 shows an example of an operation when data DQ is transmitted from the processor chip 40 to which the allocation of the data mask area DM of FIG. 11 is applied to the stacked memory 30. Note that FIG. 15 also shows an example of the operation of the stacked memory 30A that transmits data DQ to the processor chip 40A. That is, FIG. 15 shows an example of a method of transferring the write data DQ to the stacked memory 30A by the processor chip 40A and a method of transferring the read data DQ to the processor chip 40A by the stacked memory 30A.

An example in which the stacked memory 30A transfers data DQ to the processor chip 40A will be described by replacing the "processor chip 40A" in the following description with the "stacked memory 30A". The operation shown in FIG. 15 is started based on the fact that the inversion processing circuit 43A receives the 512-bit data DQ transferred in the burst operation when the burst operation is started.

First, in step S40, the inverting processing circuit 43A of the processor chip 40A calculates the number of inverting bits in the cycle CYC1 for each subgroup S. Next, in step S42, the inverting processing circuit 43A determines which of (determination formula 1) and (determination formula 2) is valid, and uses the determination formula determined to be valid to use the determination formula determined to be valid, and the DBI inverting circuit 45 in cycle CYC1. Tentatively determine the logic of the data DQ to be output to.

Next, in step S44, the inverting processing circuit 43A calculates the number of inverting bits in the cycle CYC2 for each subgroup S. Next, in step S46, the inverting processing circuit 43A determines which of (determination formula 1) and (determination formula 2) is valid, and uses the determination formula determined to be valid to use the determination formula determined to be valid, and the DBI inverting circuit 45 in cycle CYC2. Tentatively determine the logic of the data DQ to be output to.

Next, in step S48, the inverting processing circuit 43A calculates the number of inverting bits in the cycle CYC3 for each subgroup S. Next, in step S50, the inverting processing circuit 43A determines which of (determination formula 1) and (determination formula 2) is valid, and uses the determination formula determined to be valid to use the determination formula determined to be valid, and the DBI inverting circuit 45 in cycle CYC3. Tentatively determine the logic of the data DQ to be output to.

Next, in step S52, the inversion processing circuit 43A determines the basic inversion pattern BRP based on the numbers of (determination formula 1) and (determination formula 2) determined to be valid in the cycles CYC1, CYC2, and CYC3. Next, in step S54, the inversion processing circuit 43A corresponds to the subgroup S of either an even number or an odd number having an inversion bit number of 3 bits or more based on the basic inversion pattern BRP determined in step S52. Bit RB is set to logic 1.

Next, in step S56, the inversion processing circuit 43A inverts the logic of the data DQ of the even-numbered subgroup S or the odd-numbered subgroup S corresponding to the inversion bit RB of the logic 1 based on the basic inversion pattern BRP. To do.

Next, in step S58, the inverting processing circuit 43A outputs 512-bit data DQ including the data DQ generated in step S54 to the DBI inverting circuit 45 for each cycle CYC. Then, the DBI inverting circuit 45 determines whether or not to invert the logic for each 8-bit data DQ, and when the logic is inverted, the inverting bit DBI is set to logic 1 and output to the data input / output circuit 46. .. Then, the data input / output circuit 46 sequentially transmits the data DQ, the inverting bits DBI, RB, and the all inverting bits DAI for each cycle, and the data DQ transmission process in the burst operation is completed.

FIG. 16 shows an example of the operation when the processor chip 40 to which the allocation of the data mask area DM of FIG. 11 is applied receives the data DQ from the stacked memory 30. Note that FIG. 16 also shows an example of the operation of the stacked memory 30A that receives the data DQ from the processor chip 40A. That is, FIG. 16 shows an example of a method of receiving read data DQ from the stacked memory 30A by the processor chip 40A and a method of receiving write data DQ from the processor chip 40A by the stacked memory 30A.

An example in which the stacked memory 30A receives the write data DQ output from the processor chip 40A will be described by replacing the "processor chip 40A" in the following description with the "stacked memory 30A". The operation shown in FIG. 16 is started based on the start of the burst operation.

First, in step S60, the inverting processing circuit 49A of the processor chip 40A receives the data DQ and the basic inverting pattern BRP via the DBI inverting circuit 47 in the cycle CYC0. Next, in step S62, the inverting processing circuit 49A outputs the received data DQ as read data.

Next, in step S64, the inverting processing circuit 49A receives the data DQ and the inverting bit RB in the cycle CYC1 via the DBI inverting circuit 47. Next, in step S66, the inverting processing circuit 49A performs the logic of the data DQ of the even-numbered or odd-numbered subgroup S corresponding to the inverting bit RB of the logic 1 based on the basic inverting pattern BRP and the inverting bit RB. Invert. Then, the inverting processing circuit 49A reads out the 128-bit data DQ in the cycle CYC1 and outputs it as the data DQ.

Next, in step S68, the inverting processing circuit 49A receives the data DQ and the inverting bit RB via the DBI inverting circuit 47 in the cycle CYC2. Next, in step S70, the inverting processing circuit 49A performs the logic of the data DQ of the even-numbered or odd-numbered subgroup S corresponding to the inverting bit RB of the logic 1 based on the basic inverting pattern BRP and the inverting bit RB. Invert. Then, the inverting processing circuit 49A outputs the 128-bit data DQ in the cycle CYC2 as read data.

Next, in step S72, the inverting processing circuit 49A receives the data DQ and the inverting bit RB via the DBI inverting circuit 47 in the cycle CYC3. Next, in step S74, the inverting processing circuit 49A performs the logic of the data DQ of the even-numbered or odd-numbered subgroup S corresponding to the inverting bit RB of the logic 1 based on the basic inverting pattern BRP and the inverting bit RB. Invert. Then, the inverting processing circuit 49A outputs the 128-bit data DQ in the cycle CYC3 as read data, and the reception processing of the data DQ in the burst operation is completed.

As described above, also in the embodiments shown in FIGS. 11 to 16, the number of inverting bit DBIs whose logic is inverted can be reduced as in the embodiments shown in FIGS. 1 to 10, and transmission is performed between the devices 30A and 40A. It is possible to reduce the number of bits whose logic changes in a signal. As a result, the power consumption of the data input / output circuit 46 can be reduced, and the power consumption of the system-in-package 102 can be reduced. Further, by transmitting the basic inversion pattern BRP and the inversion bit RB together with the data DQ, it is possible to eliminate the need for a dedicated cycle for transmitting the basic inversion pattern BRP and the inversion bit RB. As a result, the power consumption of the data input / output circuit 46 can be reduced without lowering the transmission efficiency of the data DQ.

Further, in the embodiment shown in FIGS. 11 to 16, the inversion processing circuit 43A is used for every 16 bits in each main group AH based on the tendency of the logic change of the 512-bit data DQ in each burst operation. It is possible to decide whether or not to invert the logic of the data DQ.

The above detailed description will clarify the features and advantages of the embodiments. It is intended that the claims extend to the features and advantages of the embodiments as described above, without departing from their spirit and scope of rights. Also, anyone with ordinary knowledge in the art should be able to easily come up with any improvements or changes. Therefore, there is no intention of limiting the scope of the embodiments having invention to those described above, and it is possible to rely on suitable improvements and equivalents included in the scope disclosed in the embodiments.

1a, 1b Semiconductor device 2 Second inversion unit 3 First inversion unit 4 Transmission unit 5 Reception unit 6 Third inversion unit 7 Fourth inversion unit 7
10 Memory chip 20 Logic chip 30 Stacked memory 40 Processor chip 41 Latch circuit 42 Inversion prediction circuit 43 Inversion processing circuit 44 ECC generation circuit 45 DBI inversion circuit 46 Data input / output circuit (PHY)
47 DBI inverting circuit 48 ECC correction circuit 49 inverting circuit 50 Silicon interposer 60 Package board 100 System 102 System-in-package BRP Basic inverting pattern DAI Full inverting bit DBI inverting bit DM data mask bit, data mask area DQ data DT data IV10 -IV13 First inversion information IV2 Second inversion information RB Inversion bit S (S0-S7) Subgroup

Claims (10)

When the number of changes in the bit value exceeds half of the number of bits for each of the first partial data in which the data is divided into a plurality of data, the logic of the first partial data is inverted and the first partial data is inverted. A first reversing part that enables the first reversing information assigned to each
In the second partial data obtained by dividing the data into a plurality of pieces, the data is supplied as the first partial data to the first inversion portion according to the ratio in which the number of changes in the bit value exceeds half of the number of bits as compared with the previous transmission. When determining whether to invert the logic of the second partial data to be performed and inverting the logic, a second inversion part that enables the second inversion information and
A semiconductor device comprising: a transmission unit for transmitting the first inversion information and the second inversion information together with the first partial data generated by the first inversion unit. A receiving unit that receives the first partial data, the first inverted information, and the second inverted information from the semiconductor device that transmits the data.
A third that inverts the logic of the first partial data corresponding to the first inverted information in the valid state based on the first partial data received by the receiving unit and the first inverted information. Inverted part and
By inverting the logic of the data output by the third inverting unit based on the second inversion information received from the semiconductor device of the transmission source, the data from the semiconductor device of the transmission source is generated. The semiconductor device according to claim 1, further comprising an inversion portion of 4. When the total number of changes in the bit values of the first partial data, the first inversion information, and the second inversion information increases as compared with the previous transmission, the second inversion unit is irrespective of the ratio. The semiconductor device according to claim 1 or 2, wherein the second inversion information is prevented from being effectively set. Two of the second partial data are assigned to the partial data pair.
The second partial data of each of the partial data pairs is assigned to a first group or a second group.
The second reversing part is
Of the first group and the second group in a plurality of transmissions, the dominant group having a large number of the second partial data in which the number of changes in the bit value exceeds half of the number of bits as compared with the previous transmission. Judging,
In the determined superior group, the logic of the second partial data exceeding half of the above is reversed.
The group identification information indicating the determined superior group and the inverted pair information indicating the partial data pair including the second partial data whose logic is inverted are set as the second inverted information. The semiconductor device according to claim 2. 4. The fourth inversion portion is characterized in that, in the partial data pair indicated by the inverted pair information, the logic of the second partial data belonging to the group indicated by the group identification information is inverted. The semiconductor device described. The second reversing part is
In each of the plurality of transmissions, the number of changes in the bit value of all the second partial data of one of the first group or the second group exceeds half of the number of bits as compared with the previous transmission. When the number of changes in the bit value is less than half of the number of bits in all the other second partial data of the first group and the second group as compared with the previous transmission, the number exceeds half of the above. Judged as the superior group
The semiconductor device according to claim 4, wherein invalid information is set in the group identification information when the superior group does not exist. The semiconductor device according to claim 6, wherein the fourth inversion unit suppresses the logic inversion processing of the second partial data when the group identification information is invalid information. In each of the plurality of transmissions, the transmission unit transmits additional information having a predetermined number of bits for which the purpose is not specified, in addition to the first partial data and the first inversion information.
The semiconductor device according to any one of claims 1 to 7, wherein the second inversion information is included in the additional information. The semiconductor device further has a code generation unit that generates an error detection / correction code of the first partial data.
The eighth aspect of the present invention is characterized in that the transmission unit transmits the error detection / correction code as a part of the additional information, and transmits the second inversion information as another part of the additional information. The semiconductor device described. In a system having multiple semiconductor devices that send and receive data
Each of the plurality of semiconductor devices
When the number of changes in the bit value exceeds half of the number of bits for each of the first partial data in which the data is divided into a plurality of data, the logic of the first partial data is inverted and the first partial data is inverted. A first reversing part that enables the first reversing information assigned to each
In the second partial data obtained by dividing the data into a plurality of pieces, the data is supplied as the first partial data to the first inversion portion according to the ratio in which the number of changes in the bit value exceeds half of the number of bits as compared with the previous transmission. When determining whether to invert the logic of the second partial data to be performed and inverting the logic, a second inversion part that enables the second inversion information and
A transmission unit that transmits the first inversion information and the second inversion information together with the first partial data generated by the first inversion unit.
A receiving unit that receives the first partial data, the first inverted information, and the second inverted information from the semiconductor device that transmits the data.
A third that inverts the logic of the first partial data corresponding to the first inverted information in the valid state based on the first partial data received by the receiving unit and the first inverted information. Inverted part and
The second inversion information received from the semiconductor device of the transmission source is used to invert the logic of the data output by the third inversion unit to generate data from the semiconductor device of the transmission source. A system characterized by having an inversion portion of 4.

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