JP2020167529A - Timing generator and semiconductor integrated circuit - Google Patents

Abstract

To provide a highly accurate timing generator.SOLUTION: A timing generator 100 includes a plurality of phase interpolators PI. Each phase interpolator PI is configured to receive a first signal having an edge at a first timing and a second signal having an edge at a second timing, and to be capable of generating an output signal having an edge at a timing according to a control code. The timing generator 100 includes M (M≥2) stages, and each stage includes a first phase interpolator 112 and a second phase interpolator 114. In at least one stage, a code scrambler 130 is configured to dynamically replace a pair of delay amounts to be set to a pair of the phase interpolators 112 and 114.SELECTED DRAWING: Figure 3

Description

The present invention relates to a timing generator.

In a semiconductor integrated circuit (hereinafter, IC), there is a case where it is desired to digitally control the timing (phase) of an internal signal with high accuracy. In the present specification, a circuit that generates an arbitrary timing (phase) is referred to as a timing generator.

1 (a) to 1 (c) are circuit diagrams of a conventional timing generator. The timing generator 10 of FIG. 1A includes a digital counter 12 and a determination device 14. An initial value INIT corresponding to a target timing is set in the counter 12. When the counter 12 is activated at the reference timing, the counting operation starts. The determination device 14 changes the output OUT when the count value of the counter 12 reaches a predetermined value. The output OUT is a signal delayed by T _CK × INIT from the reference timing. The time resolution in the timing generator 10 is T _CK , and is restricted by the frequency of the clock signal CLK given to the counter 12.

The timing generator 20 of FIG. 1B includes a plurality of delay elements (buffers) D _{1 to DN} connected in series and a selector 22 for selecting output taps of the plurality of delay elements. The time resolution in this configuration is constrained by the delay time τ _d of the delay element. Since the delay time τ _d varies greatly depending on the manufacturing variation, temperature, and power supply voltage conditions, a feedback loop for stabilizing the delay time τ _d is usually constructed.

The timing generator 30 of FIG. 1C includes a PLL (Phase Locked Loop) circuit. The PLL circuit includes a phase comparator PC, a charge pump CP, a VCO (Voltage Controlled Oscillator) 32 and a frequency divider 34. The VCO 32 includes a ring oscillator, and one clock can be selected by the selector 36 from a plurality of taps provided on the ring oscillator. The timing generator 30 of FIG. 1C has a large circuit area and consumes a large amount of power. In addition, since it takes time for the feedback loop to stabilize, there is a problem that the startup time is long.

When the timing generators of FIGS. 1A to 1C are used, the upper limit or the minimum delay value of the speed of the application circuit using the timing generator is restricted by the timing generator. Therefore, as another approach, a circuit using a phase interpolator (PI: Phase Interpolator) has been proposed (Non-Patent Document 1). Non-Patent Document 1 discloses a circuit configuration in which a two-input, three-output phase interpolator (also referred to as a phase blender) is connected in multiple stages. 2 (a) and 2 (b) are circuit diagrams of a timing generator using a conventional phase interpolator. The timing generator 40 of FIG. 2A is composed of a plurality of phase interpolation machines 42 arranged in a tournament shape. In the case of this method, in order to obtain the resolution of M bits (2 ^M gradation), (2 × 2 ^M -1) phase interpolators 42 are required, and the circuit area becomes enormous. In addition, a multiplexer 44 is required to select one of the ^2M phase outputs φ _out with different timings. Further, since the phase interpolator 42 of the signal path that does not contribute to the final output also operates, wasteful power consumption is generated.

The timing generator 50 of FIG. 2B is composed of a pipeline type including a plurality of phase interoperators 52 and multiplexers 54 connected in series. In the case of this method, in order to obtain the resolution of M bits (2 ^M gradation), only (M + 1) phase interoperators 52 and M multiplexer 54 are required, so that the timing generator 40 in FIG. 2 (a) is used. Compared with this, the circuit area can be significantly reduced.

Japanese Unexamined Patent Publication No. 2001-273048 JP-A-2002-190724 Japanese Unexamined Patent Publication No. 2003-87113 Japanese Unexamined Patent Publication No. 2006-319966 Japanese Unexamined Patent Publication No. 2001-339280 Japanese Unexamined Patent Publication No. 2011-259286 Japanese Unexamined Patent Publication No. 2013-46271 Japanese Unexamined Patent Publication No. 2012-2313894 International Publication WO2012 / 167239

Aravind Tharayil Narayanan et al., "A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of .250 dB", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 7, JULY 2016

As a result of examining the timing generator 50 of FIG. 2B, the present inventor has come to recognize the following problems. In the timing generator 50 of FIG. 2B, an intermediate signal passes through the multiplexer (analog switch) 54.

Each multiplexer 54 always selects two signal paths, but the delay amounts of the two selected signal paths are required to be exactly the same. In other words, the linearity of the timing control of the timing generator 50 (that is, the effective time resolution) is limited by the variation in the delay amount of the multiplexer 54.

In addition, waveform distortion occurs when the pulse signal passes through the multiplexer. This waveform distortion also causes deterioration of the linearity of the timing control of the timing generator 50.

Further, every time the time resolution is increased by 1 bit, it is necessary to add one step of the combination of the phase interpolator 52 and the multiplexer 54. This means that the variation in the amount of delay increases in exchange for the improvement of the time resolution of 1 bit, and the improvement of the time resolution is greatly restricted by this trade-off relationship.

The present invention has been made in view of the above problems, and one of the exemplary objects of the embodiment is to provide a highly accurate timing generator.

One aspect of the present invention relates to a timing generator. The timing generator receives the first reference timing signal and the second reference timing signal, and generates an output timing signal having an edge at the timing according to the control code. The timing generator is a code scramble that generates a code to be set in the plurality of phase interpolators based on the control code and a plurality of phase interpolators that form M stages (M is an integer of M ≧ 2). With a bra. The delay stages of the first stage to the (M-1) stage include the pair of phase interpolators. The phase interpolator has a first input node, a second input node, and an output node, and the output node receives the signal of the first input node and the signal of the second input node, whichever is earlier, according to the set code. It is configured to be able to generate a delayed signal for a long time. In the first stage, the first and second reference timing signals are input to the first and second input nodes of the phase interpolator, respectively. In the i-th stage (2 ≦ i ≦ M), the first and second input nodes of the phase interpolator are connected to one or the other output node of the phase interpolator pair in the (i-1) stage, respectively. Will be done. The chord scrambler is configured so that the pair of the delay amount set in the pair of the phase interpolators can be dynamically exchanged in at least one of the delay stages of the M stage.

According to this aspect, the propagation paths of the two timing signals are dynamically switched. As a result, the variation of the pair of phase interpolators forming the same stage is time-averaged, the influence of the variation can be reduced, and highly accurate timing generation becomes possible.

The order of the first reference timing signal and the second reference timing signal may be scrambled. This makes it possible to reduce the influence of variations in the pair of phase interpolators in the first stage.

M = 2, (i) a state in which the first reference timing signal precedes the second reference timing signal and the delay amount of one of the first-stage phase interpolators is smaller than the delay amount of the other, (ii). ) The first reference timing signal follows the second reference timing signal, and the delay amount of one of the first-stage phase interpolators is smaller than the delay amount of the other. (Iii) The first reference timing signal is the first. A state in which one delay amount of the first-stage phase interpolator pair is larger than the other delay amount prior to the two reference timing signals, and (iv) the first reference timing signal follows the second reference timing signal. A state in which one delay amount of the first-stage phase interpolator pair is larger than the other delay amount may be dynamically switched.

M ≧ 3, and 2 × M states may be switchable.

The phase interpolator inputs to the first input node, the first line to which the first voltage is supplied, the second line to which the second voltage is supplied, the intermediate line, the capacitor whose one end is connected to the intermediate line, and the first input node. The initialization circuit that initializes the voltage of the capacitor and the intermediate line corresponding to each bit included in the code during the period when both the first signal to be input and the second signal input to the second input node are at the first level. A plurality of circuit units connected in parallel between the second line and the second line, and an output circuit that generates an output signal whose level changes when the voltage of the capacitor crosses a predetermined threshold value may be provided. Each circuit unit may include a resistor and a first path provided in series between the intermediate line and the second line, and a second path provided in parallel with the first path. The first path is configured to be turned on when the first signal is at the second level and the corresponding bit of the code is the first value, and the second path is configured so that the second signal is at the second level. And it may be configured to be turned on when the corresponding bit of the code is the second value.

The code may be a thermometer code. The code scrambler may scramble the bits to be marked. As a result, the element variation inside the phase interpolator is time-averaged, the influence of the variation can be reduced, and the timing accuracy can be further improved.

Another aspect of the invention relates to semiconductor integrated circuits. The semiconductor integrated circuit includes a delay pulse generator. The delay pulse generator includes a set signal generator that generates a set signal, a reset signal generator that generates a reset signal, and a pulse signal that transitions to the first level according to the set signal and to the second level according to the reset signal. It may be provided with an output circuit for outputting. At least one of the set signal generator and the reset signal generator may include a timing generator.

The pulse signal may be a pulse width modulated signal. When modulating the edges on both sides, both the set signal generator and the reset signal generator may be configured with the timing generator described above. When only one edge is modulated, only one of the set signal generator and the reset signal generator may be configured by the timing generator described above, and the other may be configured by a fixed delay circuit.

The semiconductor integrated circuit may be a class D amplifier controller, a DC / DC converter controller, an LED driver controller, or a motor controller.

It should be noted that an arbitrary combination of the above components or a conversion of the expression of the present invention between methods, devices and the like is also effective as an aspect of the present invention.

Furthermore, the description of this item (means for solving the problem) does not explain all the essential features of the present invention, and therefore subcombinations of these features described may also be the present invention. ..

According to an aspect of the present invention, a highly accurate timing generator can be provided.

1 (a) to 1 (c) are circuit diagrams of a conventional timing generator. 2 (a) and 2 (b) are circuit diagrams of a timing generator using a conventional phase interpolator. It is a block diagram of the timing generator which concerns on embodiment. It is a figure explaining the basic operation of a phase interpolator. It is an operation waveform diagram of the timing generator of FIG. It is a figure explaining the pipeline operation of the timing generator of FIG. It is a figure explaining another operation of a phase interpolator PI. 8 (a) to 8 (d) are diagrams for explaining dynamic path matching of the timing generator. It is a circuit diagram of the phase interpolator which concerns on 1st Embodiment. It is a circuit diagram of the phase interpolator which concerns on 1st Example. 11 (a) to 11 (c) are circuit diagrams of a configuration example of an output circuit. It is a circuit diagram of another configuration example of an output circuit. It is a circuit diagram of another configuration example of an output circuit. It is an operation waveform figure of a phase interpolator. 15 (a) and 15 (b) are equivalent circuit diagrams for explaining the operation of the phase interpolator. It is a figure explaining the dependency of the control code of the operation of a phase interpolator. It is a simplified circuit diagram of the phase interpolator which concerns on the 1st comparison technique. It is a simplified circuit diagram of the phase interpolator which concerns on the 2nd comparison technique. It is a circuit diagram of the phase interpolator which concerns on 1st Example. It is a circuit diagram of the phase interpolator which concerns on 2nd Example. 21 (a) to 21 (c) are operation waveform diagrams of each of the phase interpolators according to the first to third embodiments. 22 (a) and 22 (b) are diagrams showing the relationship between the input code and the delay amount of each of the phase interpolators according to the first to third embodiments. FIG. 23 (a) is a diagram showing the DNL of each of the phase interpolators according to the first to third embodiments, and FIG. 23 (b) is an INL of each of the phase interpolators according to the first to third embodiments. It is a figure which shows. It is a circuit diagram of the phase interpolator which concerns on 2nd Embodiment. It is a circuit diagram of the phase interpolator which concerns on 4th Embodiment. It is a circuit diagram of the phase interpolator which concerns on 5th Embodiment. It is a circuit diagram of the phase interpolator which concerns on 3rd Embodiment. It is a circuit diagram of the phase interpolator which concerns on 6th Embodiment. It is an operation waveform figure of the phase interpolator of FIG. It is a circuit diagram of the delay pulse generator using the timing generator. It is a block diagram of a digitally controlled switching power supply. It is a block diagram of a motor drive system. 33 (a) and 33 (b) are block diagrams of an audio circuit. It is a block diagram of a light emitting device.

Hereinafter, the present invention will be described with reference to the drawings based on preferred embodiments. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. Further, the embodiment is not limited to the invention but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

In the present specification, the "state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, and the member A and the member B are electrically connected. It also includes the case of being indirectly connected via another member that does not affect the connection state or interfere with the function.

Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and also electrically. It also includes the case of being indirectly connected via another member that does not affect the connection state or interfere with the function.

FIG. 3 is a block diagram of the timing generator 100 according to the embodiment. The timing generator 100 receives a first reference timing signal .phi.a ₀ and the second reference timing signal .phi.b _0, to generate an output timing signal phi _OUT having edges in timing corresponding to the control code _{D CNT.} The time difference between the two reference signals φa ₀ and φb ₀ is constant ΔT ₀ .

The timing generator 100 includes an M-stage (M ≧ 2) delay stage 110 and a code scrambler 130. The delay stages 110_1 to 110_ (M-1) of the first to first (M-1) stages include pairs 112 and 114 of the phase interpolators PI. The delay stage 110_M of the final stage (Mth stage) includes one phase interpolator 112. In the modified example, two phase interoperators 112 and 114 may be provided in the delay stage 110_M of the final stage, and one of the outputs may be unused.

The timing generator 100 is composed of a combination of a plurality of phase interpolators PI having the same configuration. The phase interpolator PI has a first input node I1, a second input node I2, and an output node O. The phase interpolator PI sets the output node O from the outside of the signal of the first input node I1 (referred to as the first signal φa) and the signal of the second input node I2 (also referred to as the second signal φb). It is configured to be able to generate a delayed signal for a time Td according to the controlled control code (called a code).

FIG. 4 is a diagram illustrating the basic operation of the phase interpolator PI. Edge of the first signal φa is generated in the input nodes IN1 at time _{t 0,} from time _{t 0} to time _{t 1} after a predetermined time ΔT elapses, the edge of the second signal φb input node IN2 is generated. When the number of gradations of the phase interpolator PI is N (N ≧ 2) and the time resolution is Δt, the time difference ΔT between the two input timing signals φa and φb is N × Δt. A control code (code) CODE is given to the phase interpolator PI. The phase interoperator PI is a digital-time conversion that generates a delay amount that changes linearly with respect to d when the value of the control code CODE is d (d = 0,1, ..., N-1) in decimal. It is a device (DTC: Digital to Time Converter). Td of the delay amount of the output signal φo with respect to the first signal φa is given by the following equation.
Td = τ + d × Δt
τ is a predetermined offset delay amount and is a constant satisfying τ ≧ ΔT.

The configuration of the phase interpolator PI is not particularly limited, and a known technique may be used, or a configuration described later may be adopted.

Return to FIG. The first reference timing signal φa ₀ is input to the first input node I1 of the pair 112, 114 of the phase interpolators of the first stage delay stage 110_1, and the second reference timing is input to the second input node I2. The signal φb ₀ is input. Regarding the delay stages 110_j (2 ≦ j ≦ M) of the second and subsequent stages, the first input node I1 of the pair of phase interpolators 112 and 114 is the phase interpolator pair 112 of the previous stage delay stages 110_ (j-1). , 114 is connected to the output node O of 112, and the second input node I2 of the pair of phase interpolators 112 and 114 is the other of the phase interpolators pairs 112 and 114 of the delay stage 110_ (j-1) in the previous stage. It is connected to the output node O of 114.

Code scrambler 130, based on the control code _{D CNT,} each delay stage 110 _ # (# = 1, ..., M) Code _Da # to be set in each phase interpolator 112 and 114, to generate the Db _#. The values (decimal numbers) of the codes Da _# and Db _# are written as a _# and b _# .

Code scrambler 130, timing signal .phi.a _i for each phase interpolator 112 and 114 included in the i-th delay stage 110_i is generated, as .phi.b _i has a predetermined time difference [Delta] T _i, code _Da i, Db _i To generate. Code values _a i, a difference of _{b i} is constant, for example when the two values _a i, a difference _{b i} 1, the time difference [Delta] T _i of the two timing signals .phi.a _i and .phi.b _i is the stage equal to the resolution Delta] t _i.

Each stage may have a different number of gradations N, representing the number of gradations of the i-th stage and N _i. At this time,
ΔT _i = Δt _{i + 1} × _{Ni + 1}
It is assumed that the relationship of

Subsequently, the basic operation of the entire timing generator 100 will be described. FIG. 5 is an operation waveform diagram of the timing generator 100 of FIG. Here, for ease of understanding, the number of stages is set to M = 2 and N ₁ = N ₂ = 4. In the example of FIG. 5, the values of the codes Da ₁ and Db ₁ set in the delay stage 110_1 are a ₁ = 1 and b ₁ = 2. The code Da ₂ value set in the delay stage 110_2 is a ₂ = 3.

At time _{t 0,} the first reference timing signal .phi.a ₀ is input, then the time _{t 1} after [Delta] T _0, the first reference timing signal .phi.b ₀ is input.

The edge of the output φa ₁ of one of the phase interpolators 112 of the first stage delay stage 110_1 occurs at time t ₂ after the delay time Td ₁ elapses from the time t ₀ .
Td ₁ = τ ₁ + a ₁ × Δt ₁
The edge of the output φb ₁ of the other phase interpolator 114 of the first-stage delay stage 110_1 occurs at the time t ₃ after the lapse of ΔT ₁ = Δt ₁ from the time t _{2 at which} φa ₁ occurs.

The edge of the output φ _OUT of the phase interpolator 112 of the second stage delay stage 110_2 is generated from the time t ₂ to the time t ₄ after the delay time Td _{2 has} elapsed.
Td ₂ = τ ₂ + a ₂ × Δt ₂

Therefore, the total delay time Td _(TOTAL) from time t ₀ to time t ₄ is
Td _(TOTAL) = τ ₁ + a ₁ x Δt ₁ + τ ₂ + a ₂ x Δt ₂
Will be. τ ₁ and τ ₂ are delays peculiar to each stage.

Generalized to the timing generator 100 provided with the delay stage 110 of an arbitrary M stage (M ≧ 2), the delay amount of the output signal φ _OUT with respect to the first reference timing signal φa ₀ is expressed by the following equation.
Td _(TOTAL) = Σ _{i = 1: M} (τ _i + Δt _i × a _i )

FIG. 6 is a diagram illustrating the pipeline operation of the timing generator of FIG. L _i represents the resolution of the i-th _stage, the relationship of N i ^{= 2 Li} holds. As the stage progresses, the time difference ΔT between the two outputs φa and φb of the previous stage becomes 1/2 ^Li times, and the time resolution becomes higher.

The above is the operation of the timing generator 100. According to the timing generator 100, in accordance with increasing the number of stages M of the stage, also in accordance with increasing the resolution N _i of each stage, it is possible to increase the resolution of the phase. Generalizing, the number of gradations of timing generator 100, a _{N 1 × N 2 × ··· ×} N M. If the number of stages N, the resolution and _{N 1 = N 2 = ··· =} N M = N, it is possible to phase control in ^{N M} gradations, time resolution is [Delta] T ₀ / ^{N M.} For example, when N = 16 and M = 2, 256 gradations (equivalent to 8 bits) can be controlled.

The timing generator 100 has the following advantages.
First, the timing generator 100 does not necessarily require a high speed clock in order to obtain fine time resolution. Slow clock only absent, two reference signals .phi.a _0, the greater the time difference [Delta] T ₀ of .phi.b ₀ is increasing the number of stages M, and / or by increasing the number of gradations N of each stage, the time The resolution can be increased.

Second, the timing generator 100 has the advantages of a small circuit area and low power consumption. Specifically, in comparison with the timing generator 40 of FIG. 2A, the number of phase interpolators PI required to obtain the same time resolution can be significantly reduced. Further, in the comparison including the timing generator 50 of FIG. 2B, the number of stages required to obtain the same time resolution can be reduced by increasing the resolution N for each stage.

In addition, in the timing generator 100, all the phase interpolators PI contribute to the output, wasteful power consumption is not generated, and it is advantageous from the viewpoint of power consumption.

Further, in relation to the power consumption, the timing generator 100 operates only when the two reference signals φa ₀ and φb ₀ change, so that unnecessary power consumption does not occur.

Third, the timing generator 100 is unnecessary analog switch (multiplexer) within the signal path, and both resolution N _i and the stage number M of each stage, may be a design parameter. As described above, the timing generator 50 of FIG. 2B has a reduced or restricted time resolution due to the multiplexer (switch) 52 on the signal path. Further, in the timing generator 50 of FIG. 2B, the number of stages must be increased according to the required time resolution. As the number of stages increases, the amount of delay is greatly varied, the linearity of timing control deteriorates, and the effective time resolution deteriorates. On the other hand, in the timing generator 100, it is not necessary to switch the signal path, a multiplexer is not required, and even if the time resolution is improved, the increase in the number of stages can be suppressed, so that the time is several ps or less. Resolution can be achieved with high linearity. However, the timing generator 100 may be used in an application that requires a time resolution of several tens of ps to sub ns.

Fourth, since the timing generator 100 does not have a feedback loop, there is an advantage that the startup is fast.

<Dynamic path matching>
Subsequently, scrambling of the signal path (hereinafter, referred to as dynamic path matching) in the timing generator 100 will be described.

The phase interpolator PI is used not only when the first signal φa of the first input node I1 precedes the second signal φb of the second input node I2, but also when the first signal φa follows the second signal φb. Is also operational. FIG. 7 is a diagram illustrating another operation of the phase interpolator PI. Edge of the second signal φb is generated at the input node IN2 at time _{t 0,} from time _{t 0} to time _{t 1} after a predetermined time ΔT elapses, the edge of the first signal φa of the input node IN1 is generated. Output signal phi _O is generated based on the second signal φb preceding delay amount of the output signal φo to the second signal φb is Td is given by the following equation.
Td = τ + d × Δt
Thus the phase interpolator PI is the first signal .phi.a, among the second signal .phi.b, from one that changes quickly, which can be regarded as one that generates a signal phi _O delayed amount Td delay.

The order of the two reference timing signals φa ₀ and φb ₀ input to the timing generator 100 can be exchanged because the connected phase interpolators 112 and 114 have symmetrical wiring connections and circuit configurations.

8 (a) to 8 (d) are diagrams for explaining dynamic path matching of the timing generator 100. Here, consider the timing generator 100 with M = 2. The timing generator 100 has four states that generate the same delay amount. 8 (a) to 8 (d) show the first state (i) to the fourth state (iv). Hereinafter, the phase interpolator 112 is referred to as a first phase interpolator, and the phase interpolator 114 is referred to as a second phase interpolator.

Code scrambler 130, at each stage, has become interchangeable delay amount is two phase interpolators 112 and 114 to produce, specifically, it is possible to replace the value of the code Da _i and Db _i ..

(I) First state The first reference timing signal φa ₀ precedes the second reference timing signal φb ₀ . The code scrambler 130 sets the delay amount of the first phase interpolator 112_1 to be smaller than the delay amount of the second phase interpolator 114_1, and causes φa ₁ to precede.
(Ii) Second state The first reference timing signal φa ₀ follows the second reference timing signal φb ₀ . The code scrambler 130 sets the delay amount of the first phase interpolator 112_1 to be smaller than the delay amount of the second phase interpolator 114_1, and causes φa ₁ to precede.
(Iii) Third state The first reference timing signal φa ₀ precedes the second reference timing signal φb ₀ . Code scrambler 130, a delay amount of the first phase interpolator 112_1, set larger than the delay amount of the second phase interpolator 114_1, it is preceded the .phi.b _1.
(Iv) fourth state the first reference timing signal .phi.a ₀ is followed to the second reference timing signal .phi.a _b. Code scrambler 130, a delay amount of the first phase interpolator 112_1, set larger than the delay amount of the second phase interpolator 114_1, it is preceded the .phi.b _1.

The timing generator 100 switches between these four states in a predetermined order or randomly for each generation of φ _OUT . By dynamically switching the propagation paths of the two timing signals at the input or output of each delay stage 110, the variations of the first phase interpolator 112 and the second phase interpolator 114 of the same stage are time-averaged, and the influence of the variations. Can be reduced and highly accurate timing can be generated.

When generalized to the M-stage timing generator 100, 2 × M states can be dynamically switched.

The relationship between the reference timing signals φa ₀ and φb ₀ may be fixed, and only the code given to the delay stages 110_1 to 110_ (M-1) may be scrambled. In this case, 2 × (M-1) states are switched. Alternatively, the code replacement (that is, the reversal of the delay amount) does not necessarily have to be performed in all stages, and may be performed in only some stages.

<Phase Interpolator PI>
The configuration of the phase interpolator PI is not particularly limited, and for example, a known phase interpolator as described in Patent Documents 1 to 9 can be used. However, in order to realize higher linearity of the timing generator 100, the phase interpolator PI described below can be used.

(First Embodiment)
FIG. 9 is a circuit diagram of the phase interpolator 700 according to the first embodiment. The phase interpolator 700 has a first input node IN1, a second input node IN2, and an output node OUT. The two input nodes IN1, IN2, and the signal _{S 1} having an edge in the first timing phi _A, the signal _{S 2} having the edge is input to the second timing phi _B. The phase interpolator 700 generates an output signal S _OUT having an edge at the timing φ _OUT corresponding to the input code D _CNT , and outputs the output signal S _OUT from the output node OUT.

First, a case where the first timing φ _A precedes the second timing φ _B will be described. Let the time difference between the two timings be T _P. This time difference T _P is also referred to as a reference time T _P. Further, in this embodiment, the edge that defines the timing (phase) is a positive edge (rising edge, leading edge).

The phase interpolator 700 includes a first line 702, a second line 704, an intermediate line 706, a capacitor C ₁ , an initialization circuit 710, a plurality of circuit units 720_1 to 720_N, an output circuit 730, and an input buffer 740. The number N of the circuit units 720 corresponds to the number of gradations (time resolution) of the phase interpolator 700, in other words, the number of gradations of the input code D _CNT , and when the input code D _CNT is expressed by a thermometer code. Equal to the number of bits. This input code is a code generated by the code scrambler 130.

A first voltage is supplied to the first line 702, and a second voltage is supplied to the second line 704. In the present embodiment, the first voltage is the power supply voltage _VDD and the second voltage is the ground voltage _VSS (V _GND ). Therefore, the first line 702 is the power supply line and the second line 704 is the ground line.

One end of the capacitor C ₁ is connected to the intermediate line 706, and the other end is grounded to fix its potential.

The initialization circuit 710 is provided between the first line 702 and the intermediate line 706, and the voltage of the capacitor C ₁ during the period when both the first signal S ₁ and the second signal S ₂ are at the first level (low level). Initialize (referred to as capacitor voltage _VC1 ). Here, the initialization voltage is the power supply voltage _VDD of the first line 702.

A plurality of circuit units 720_1 to 720_N are connected in parallel between the intermediate line 706 and the second line 704. A plurality of circuit units 720_1~720_N has a function of discharging the electric charge of the capacitor _{C 1.}

The output circuit 730, the capacitor voltage _{V C1} generates an output signal _{S OUT} whose level changes when crosses the predetermined threshold _{V TH.} The timing at which the capacitor voltage _VC1 and the predetermined threshold value _VTH cross is the output timing φ _OUT , and the output signal S _OUT has an edge at the output timing φ _OUT . Without this limitation, for example, the output circuit 730 can be configured by a voltage comparison means for binarizing a voltage signal, such as a CMOS inverter or a buffer, a voltage comparator, a dynamic latch circuit, and a level shift circuit.

The plurality of circuit units 720_1 to 720_N are similarly configured. Each circuit unit 720 includes a resistor R _g , a first path 724, and a second path 726.

One end of the resistor R _g is connected to the second line 704. The first path 724 is provided between the other end of the resistor R _g and the intermediate line 706. The first path 724, first signal _{S 1} is a second level (high), and the corresponding bit sel input code _{D CNT [0: N-1} ] is the first value (here, 1) Turns on at one point.

The second path 726 is provided in parallel with the first path 724 between the other end of the resistor R _g and the intermediate line 706. The second path 726, the signal _{S 2} is a second level (high), and the corresponding bit sel input code _{D CNT} is turned on when the second value (in this case 0 to) a.

The signal _{S 1} of the edge, if subsequent to the signal _{S 2} of the edge, all bits sel [0: N-1] may be given the input code _{D CNT} obtained by inverting. This inversion can be done in the code scrambler 130.

The above is the basic configuration of the phase interpolator 700.
Since the phase interpolator 700 has a simple circuit configuration and does not have a current source, it can operate at a low voltage. Further, as will be described in detail later, it is not easily affected by process variation, power supply voltage variation, and temperature variation, and can be started at high speed.

Further, since the variation of the resistance R _g appears compressed within the relative time difference of the edge timings φ _A and φ _B of the first signal S ₁ and the second signal S ₂ , its influence can be substantially ignored. This eliminates the need for processing such as trimming the resistor R _g with high accuracy.

Since the variation in the resistance R _g appears compressed within the relative time difference between the edge timings φ _A and φ _B of the first signal S ₁ and the second signal S ₂ , its influence can be substantially ignored. This eliminates the need for processing such as trimming the resistor R _g with high accuracy.

(First Example)
FIG. 10 is a circuit diagram of the phase interpolator 700A according to the first embodiment. Initialization circuit 710 includes an initialization transistor _{M P1} is a PMOS transistor, the logic gate 712. The logic gate 712 outputs a signal corresponding to the logical sum of the first signal S ₁ and the second signal S ₂ to the gate of the initialization transistor _MP1 . The logic gate 712 in this example is an OR gate, the signal _{S 1} and the signal _{S 2} is the period of both the low level, the initialization transistor _{M P1} is turned on, the capacitor voltage _{V C1} is initialized to _{V DD} To.

The first path 724 includes a first switch SW _A1 to a third switch SW _A3 connected in series. Similarly, the second path 726 includes the first switch SW _B1 to the third switch SW _B3 connected in series.

The first switches SW _A1 and SW _B1 are NMOS transistors, and the first signals S ₁ and S ₂ are input to their respective gates. The first switch _{SW A1} of the first path 724, the first signal _{S 1} is turned on during the second level (high), the first switch _{SW B1} of the second path 726, the signal _{S 2} is the second Turns on during the level (high) period. Input buffer 740, the first signal _{S 1,} and drives the plurality of first switch _SW A1, _{SW B1} included in the plurality of circuit units 720 in response to the second signal _{S 2.} If the output impedance of the circuit that generates the first signal S ₁ and the second signal S ₂ is sufficiently low (when the drive capability is high), the input buffer 740 may be omitted.

The pair of the second switch SW _A2 and the third switch SW _A3 of the first path 724 is complementarily turned on (off) with the pair of the second switch SW _B2 and the third switch SW _B3 of the second path 726. The second switch and the third switch SW _A2 , SW _A2 , SW _B2 , and SW _B2 may use transistors of the same type as the first switches SW _A1 and SW _B1 (that is, NMOS transistors).

Input code _{D CNT} supplied to the phase interpolator 700 can be a thermometer code of N bits, thermometer code comprises N bits sel [0] ~sel [N- 1]. Each bit sel is supplied to the corresponding one of the plurality of circuit units 720. In each circuit unit 720_i (1 ≦ i ≦ N), the pair of the second switch SW _A2 and the third switch SW _A3 of the first path 724 is controlled according to the corresponding bit sel [i-1], and the second The pair of the second switch SW _B2 and the third switch SW _B3 of the path 726 is controlled according to the inverting signal # sel [i-1] of the corresponding bit sel [i-1]. The inverting signal #sel can be generated by the inverter 722.

For a plurality of circuit units 720_1 to 720_N, when the first path 724 (or the second path 726) is in a conductive state, the impedances of the paths are assumed to be equal, and the impedance is R. The impedance R of the first path 724 is the sum of the resistance value of the resistor R _{g and} the on-resistance of the plurality of switches SW _{A1 to} SW _A3 , and the impedance R of the second path 726 is the resistance value of the resistor R _g . It is the total of the on-resistance of a plurality of switches SW _{B1 to} SW _B3 .

11 (a) to 11 (c) are circuit diagrams of a configuration example of the output circuit 730. The output circuit 730 of FIG. 11A is a CMOS inverter. The output circuit 730 of FIG. 11B is a voltage comparator using a differential amplifier. The output circuit 730 of FIG. 11C is configured by using a level shift circuit.

FIG. 12 is a circuit diagram of a configuration example of the output circuit 730. The output circuit 730 of FIG. 12 is configured by utilizing a dynamic latch circuit. The capacitor voltage _VC1 is input to the enable terminal (latch terminal, clock input) of the dynamic latch circuit. A reset signal RST (inversion logic) is further input to the output circuit 730, and the output circuit 730 can be initialized before the voltage comparison operation. In the initialized state, the output S _OUT is high. When the capacitor voltage _{V C1} crosses the threshold _{V TH,} activated dynamic latch _circuit, a voltage comparator of _{V DD} and _{V GND} are performed, the output _{S OUT} changes to the low level.

The output circuit 730 may be integrally formed with the circuit after the phase interpolator 700. For example, when the differential flip-flop is arranged after the phase interpolator 700, the output circuit 730 can be incorporated in the differential flip-flop. FIG. 13 is a circuit diagram of a differential flip-flop incorporating an output circuit 730. The configuration of the output circuit 730 of FIG. 13 is the same as that of the dynamic latch circuit of FIG.

The above is the configuration of the phase interpolator 700A. Subsequently, the operation of the phase interpolator 700A will be described.
FIG. 14 is an operation waveform diagram of the phase interpolator 700A. Here, N = 4 is taken as an example. Before the time t ₀ , both the first signal S ₁ and the second signal S ₂ are at a low level, and therefore the capacitor voltage _VC1 is initialized to the initial value of the power supply voltage _VDD . Since the first signal S ₁ and the second signal S ₂ are at low level, both the first switch SW _A1 and SW _B1 are off, the first path 724 and the second path 726 are in the cutoff state, and the capacitor C ₁ The charge is retained in.

15 (a) and 15 (b) are equivalent circuit diagrams for explaining the operation of the phase interpolator 700. FIG. 15A shows a state in which the first signal S ₁ is at a high level and the second signal S ₂ is at a low level, that is, the times t _{0 to} t ₁ in FIG. And FIG. 15 (b) represents the first signal _{S 1} and second signal _{S 2} both a high level state, i.e., a time _{t 1} after the Figure 14. When the capacitor voltage _{V C1} crosses a threshold voltage _{V TH,} the output signal _{S OUT} is changed.

Of the thermometer code sel [N-1: 0] input to the phase interpolator 700, the number of bits having a value of 1 (referred to as a mark) is K (0 ≦ K ≦ N-1). The value K corresponds to the values a and b of the codes Da and Db in FIG.

In the state of FIG. 15 (a), the capacitor _{C 1} is discharged by the parallel connection circuit 721a of the K resistors R. The resistance of the parallel connection circuit 721a is R / K, and the time constant is CR / K. Therefore, the capacitor voltage _VC1 (t ₁ ) at time t ₁ in FIG. 14 is represented by the equation (1).
_{V C1 (t 1) = V} DD · exp (-T P / (C R / K)) ... (1)

In the state of FIG. 15 (b), the independent of the value of the control code _{D CNT} (i.e. K), the capacitor _{C 1} is discharged by the parallel connection circuit 721b of all N resistors R. The resistance of the parallel connection circuit 721b is R / N, and the time constant is CR / N.

As the initial value voltage _V C1 _{(t 1)} of the formula (1), the time τ required for the voltage _{V C1} drops to the threshold voltage _{V TH,} the formula (2).
τ = CR / N ln ( _VC1 (t ₁ ) / V _TH )… (2)

Substituting equation (1) into equation (2) gives equation (3).
_{τ = C R / N ln (} V DD · exp (-T P / (C R / K)) / V TH)
_{= C R / N {ln (} V DD / V TH) -T P / (C R / K))}
_{= C R / N ln (V} DD / V TH) -T P K / N (3)

Therefore, the delay time T _DELAY from the time t ₀ to the time t ₃ is expressed by the equation (4).
T _DELAY = T _P + τ
= CR / N ln ( _VDD / _VTH ) + T _P (NK) / N (4)

The first term on the right side of the equation (4) is a constant (offset delay) that does not depend on the control code. Therefore, according to the phase interpolator 700 according to the embodiment, the phase φ _OUT of the output signal S _OUT can be controlled with the reference time T _P / N as the time resolution (unit delay width).

When a capacitor is discharged (or charged) with a constant current source, the capacitor voltage changes linearly. On the other hand, when the capacitor is discharged (or charged) by the resistor, the capacitor voltage changes non-linearly according to the exponential function determined by the CR time constant with the CR time constant. Therefore, intuitively, it seems that the accuracy of using a resistor deteriorates as compared with the case of using a constant current source. However, Eq. (4) mathematically shows that the delay time can be accurately controlled in steps of unit delay width T _P / N, and there is no demerit of using a resistor. The merits of using a resistor will be described later.

In order for the phase interpolator 700 to generate an accurate phase delay, the delay time T _DELAY when (NK) = 1 must be larger than the reference time T _P. Then, the reference time T _P can be used in the following range.
T _P <CR ln (V _DD / V _TH ) / (N-1)

Incidentally, a capacitor C ₁ which is initialized when discharged at all N circuit unit 720, after a reference time T _P from the discharge start, so that the capacitor voltage V _C1 crosses a threshold voltage V _TH The impedance R and the capacitor C may be defined. In other words, R and C may be defined so that the following relational expression holds.
T _P = CR / N ln (V _DD / V _TH )… (5)

Substituting equation (5) into equation (4) gives equation (6).
T _DELAY = T _P + T _P / N × (NK)… (6)
To get. That is, when K = N, the phase of the output signal S _OUT can be matched with the phase of the second signal S ₂ .

FIG. 16 is a diagram illustrating the dependence of the control code for the operation of the phase interpolator 700. Here it represents a linear voltage change of the capacitor voltage V _C1 for ease of understanding. Further, it is assumed that the circuit is designed so as to satisfy the equation (5). FIG. 16 shows the waveforms of the control codes sel [3: 0] = [1111] to [0000]. It should be noted that the control code is a thermometer code, and only the number of 1s has a meaning, and the order of the bits has no essential meaning. As is clear from FIG. 16, the phase φ _OUT of the output signal S _OUT can be controlled according to the control code sel [3: 0].

The above is the operation of the phase interpolator 700A. Subsequently, the advantages of the phase interpolator 700A will be described. The advantages of the phase interpolator 700 are clarified by comparison with some comparison techniques.

(First comparison technique)
FIG. 17 is a simplified circuit diagram of the phase interpolator 700R according to the first comparison technique. The comparative technology must not be recognized as a known technology. Circuit unit 720R phase interpolator 700R, instead of the resistor _{R g} of the circuit unit 720, the current source CS is provided. In this phase interpolator 700R, the voltage ΔV between both ends of the current source CS must be maintained larger than the saturation voltage V _SAT . Therefore, the power supply voltage _VDD cannot be reduced and the power consumption becomes large.

On the other hand, in the phase interpolator 700 according to the embodiment, since the current source CS does not exist, the power supply voltage _VDD can be lowered and the power consumption can be lowered. For example, in the process generation of 0.18 μm to 28 nm, the threshold value of the MOS transistor is Vth = 0.25 to 0.7 V, and the overdriver voltage is about Vod = 0.15 to 0.2 V. Therefore, the phase interpolator 700 according to the embodiment can operate at _VDD = 1V or less, and the produced sample can operate at 0.6V or less.

Further, when the current source CS is used as in the comparative technique, a bias circuit 750 for biasing the current source CS is required, which is advantageous in terms of circuit area. Further, since it is not necessary to consider the influence of the noise of the bias voltage, the layout becomes easy.

Further, in the comparative technique, the phase interpolator 700R can be operated only after the bias circuit 750 is activated after the power of the IC is turned on.

On the other hand, the phase interpolator 700 according to the embodiment can be operated immediately after the power of the IC is turned on.

(Second comparison technique)
FIG. 18 is a simplified circuit diagram of the phase interpolator 700S according to the second comparison technique. The circuit unit 720S of the phase interpolator 700S has a configuration in which the current source CS is omitted from the phase interpolator 700R of FIG. In this comparative technique, the impedance R of the first path 724 is defined by the sum of the on-resistances of the first switch SW _A1 and the switch SW _A2 , and the impedance R of the second path 726 is the first switch SW _B1 and the switch SW _B2. It is defined by the total on-resistance of.

In order to reduce the power consumption of the phase interpolator 700S, it is desirable to increase the impedance R and reduce the discharge current. However, in the phase interpolator 700S, in order to increase the on-resistance of the switches SW _A1 and SW _A2 (SW _B1 and SW _B2 ), the gate length L of the MOS transistor must be lengthened. When the gate length L becomes long, the gate capacitance of the MOS transistor increases, so that the slew rate of the gate voltage decreases and the switching loss increases. It also increases the gate drive current required to turn the switch on or off. Therefore, in the phase interpolator 700S of FIG. 18, there is a limit to the reduction of power consumption.

On the other hand, it is possible to take a method of adjusting the charge / discharge current based on the channel width W of the MOS transistor, but reducing the channel width W in order to reduce the current causes an increase in variation and a decrease in performance. Will be done. In addition, the minimum width of the channel width W has a process manufacturing limit. Therefore, it is difficult to achieve both low power consumption and high performance by the charge / discharge current design method using only the MOSFET parameter W / L.

On the other hand, according to the phase interpolator 700 (700A or 700B, 700C described later), if the resistance value of the resistor R _g is increased, the gate length L of SW _A1 to SW _A3 and SW _{B1 to} SW _B3 can be increased. Since it is not necessary to lengthen it, the switching loss can be reduced, the gate drive current can be reduced, and the channel width W does not need to be reduced, so that an increase in variation and a corresponding deterioration in performance can be suppressed.

Return to FIG. When the phase interpolator PI is configured by the phase interpolator 700A, the codes Da and Db become thermometer codes. The code scrambler 130 may change the bits marked by the codes Da and Db cyclically or randomly (DEM: Dynamic Element Matching). By the DEM processing, the influence of the variation of the plurality of circuit units 720_1 to 720_N can be reduced. The DEM process can be used in combination with the above-mentioned dynamic path matching process. The method of DEM processing is not particularly limited, but for example, a DWA (Data Weighted Averaging) method may be used.

(Second Example)
FIG. 19 is a circuit diagram of the phase interpolator 700B according to the second embodiment. In this embodiment, the third switches SW _A3 and SW _B3 on the intermediate line 706 side are omitted from the circuit unit 720 of FIG. Other configurations are the same as those of the phase interpolator 700A. Also in the second embodiment, the output signal S _OUT having a phase corresponding to the control code can be generated. It also has the same advantages as described in connection with the first embodiment.

(Third Example)
FIG. 20 is a circuit diagram of the phase interpolator 700C according to the third embodiment. In this embodiment, the second switches SW _A2 and SW _B2 on the resistor _Rg side are omitted from the circuit unit 720 of FIG. Other configurations are the same as those of the phase interpolator 700A. Also in the third embodiment, the output signal S _OUT having the phase corresponding to the control code can be generated. It also has the same advantages as described in connection with the first embodiment.

(Comparative evaluation)
Subsequently, the characteristics of the phase interpolators 700A, 700B, and 700C according to the first to third embodiments are compared.

21 (a) to 21 (c) are operation waveform diagrams of the phase interpolators 700A to 700C according to the first to third embodiments. 21 (a) to 21 (c) are simulation results, and _VDD = 1.5V and N = 16. In comparison to FIG. 21 (a) ~ (c) , the first signal _{S 1,} the signal _{S 2} is different behavior of the capacitor voltage _{V C1} at the timing of transition.

22 (a) and 22 (b) are diagrams showing the relationship between the input code and the delay amount of each of the phase interlacers 700A to 700C according to the first to third embodiments. FIG. 22B shows the relative delay time offset so that the delay amount when the input code is zero becomes zero.

FIG. 23 (a) is a diagram showing the DNL of each of the phase interpolators 700A to 700C according to the first to third embodiments, and FIG. 23 (b) is a diagram showing the DNLs of the phase interpolators 700A to 700C according to the first to third embodiments. It is a figure which shows each INL of 700A to 700C.

The simulation results will be described.
-For more details, referring to FIG. 21 (a) related to the first embodiment 700A, the waveform operates with the most ideal waveform as shown in FIG. Focusing on the first path 724 side, by the switch _SW A2, _{SW A3} is provided on both sides of the first switch _{SW A1,} due to the clock feed-through and charge injection in the first switch _{SW A1} is suppressed ..

That is, since it is possible to turn off the upper and lower switch _SW A2, _{SW A3} of the first switch _{SW A1} of the first signal _{S 1} is input, the clock feedthrough of the first switch _{SW A1,} unnecessary due to charge injection into the intermediate line 706 Or, undesired charges are suppressed and unnecessary voltage fluctuations are suppressed.

Furthermore, since the upper and lower switches SW _A2 and SW _A3 can be turned off, unnecessary or unfavorable charges for the node between SW _A1 and SW _A2 and the node between SW _A1 and SW _A3 are suppressed, thereby suppressing the unnecessary or unfavorable charge of the intermediate line 706. It is not required impact on the voltage V _C1 has been removed. The same applies to the second path 726 side.

In the first embodiment, as described above, the effects of charge injection and clock feedthrough on both the upper side and the lower side are suppressed. Therefore, as shown in FIGS. 23 (a) and 23 (b), both INL and DNL are suppressed. , Shows very good characteristics near zero.

Second Example With reference to FIG. 21 (b) related to the second embodiment 700B, since there is no upper switch SW _A3 , the clock feedthrough and charge injection of the first switch SW _A1 to the intermediate line 706 are performed. unnecessary charge is generated, the capacitor voltage _{V C1} is varied (action 1).

Further, since there is no upper switch SW _A3 , when the first switch SW _A1 is turned on, an unnecessary or unfavorable charge is generated for the node between SW _A1 and SW _A2, and an unnecessary discharge is generated from the charge of the intermediate line 706. (Action 2).

Referring to FIG. 23 (a), the deviation is large in the first chord of DNL, gradually decreases and approaches the ideal, but finally does not intersect the ideal, and the middle chord (6 to 7) is used as a boundary. , DNL increases. This is because the action 1 and the action 2 cancel each other out, but the action 1 has a slightly larger effect, and the delay is slightly larger, resulting in an increase in DNL. Since DNL is larger than ideal, INL shows a monotonous increase as shown in FIG. 23 (b).

3rd Example In FIG. 21C related to the 3rd Example 700C, since the upper switch SW _A3 is present, clock feedthrough and charge injection from the first switch SW _A1 to the intermediate line 706 are suppressed. ing.

On the other hand, since there is no lower switch SW _A2 , when the first switch SW _A1 is turned on, an extra charge of the node between SW _A1 and SW _A3 is generated. Due to this charge, the voltage of the upper node of the resistor R _g decreases, the gate-source voltage V _gs of the first switch SW _A1 increases, the on-resistance decreases, and the discharge of the intermediate line 706 is accelerated.

With reference to FIG. 23 (a), in the third embodiment, the deviation of the DNL becomes large on the minus side. This is due to the large effect of discharge, unlike the second embodiment. Therefore, as shown in FIG. 23 (b), INL also decreases significantly.

From these comparison results, excellent characteristics are shown in the order of the first, second, and third examples. Therefore, when the number of circuit elements may be large, the first embodiment may be adopted. On the other hand, if the characteristics can be compromised, the circuit area can be reduced by adopting the second embodiment. There is no reason to actively adopt the third embodiment, but depending on the required performance, even the third embodiment is sufficiently useful.

(Second Embodiment)
FIG. 24 is a circuit diagram of the phase interpolator 700C according to the second embodiment. The phase interpolator 700C has a different arrangement of resistors R _{g from} the phase interpolator 700 (FIG. 1) according to the first embodiment. That is, in the first embodiment, the resistor R _g is provided on the second line 704 side of the first path 724, whereas in the phase interpolator 700C according to the second embodiment, the resistor R _g is provided. _g is provided on the intermediate line 706 side of the first path 724. The same effect as that of the first embodiment can be obtained by this phase interpolator 700C.

(Fourth Example)
Subsequently, a specific configuration example of the phase interpolator 700C according to the second embodiment will be described. FIG. 25 is a circuit diagram of the phase interpolator 700D according to the fourth embodiment. In the phase interpolator 700D, the configurations of the first path 724 and the second path 726 are the same as those in FIG. As a result, the effects of clock feedthrough and charge injection can be suppressed, and DNL (differential nonlinearity error) and INL (integral nonlinearity error) can be reduced.

(Fifth Example)
FIG. 26 is a circuit diagram of the phase interpolator 700E according to the fifth embodiment. In the phase interpolator 700E, the switch SW _A2 on the second line 704 side is omitted from the first path 724, and the switch SW _B2 on the second line 704 side is also omitted from the second path 726.

In the fifth embodiment, the third switch SW _A3 is provided between the first switch SW _A1 and the resistor R _g , and the third switch SW _B3 is provided between the first switch SW _B1 and the resistor R _g. .. Therefore, the effects of clock feedthrough and charge injection on the resistance side can be suppressed by the third switches SW _A3 and SW _B3 .

On the other hand, when the second line 704 is a ground line (or power supply line), its impedance is sufficiently low, so that charge injection and clock feedthrough to the source side of the first switch SW _A1 and the first switch SW _B1 occur. However, the fluctuation of the potential of the second line 704 can be ignored. Therefore, even if the second switch SW _A2 and the second switch SW _B2 are omitted, DNL and INL comparable to those of the fourth embodiment can be realized. In the fifth embodiment, the number of transistors can be reduced, so that the circuit area can be reduced.

(Third Embodiment)
FIG. 27 is a circuit diagram of the phase interpolator 700F according to the third embodiment. In the first and second embodiments, the first signal S _1, but focusing on the signal S ₂ of the positive edge of the phase, in the third embodiment, negative edge (the falling edge, a trailing edge) Acts as a trigger. The phase interpolator 700F has a configuration in which the phase interpolator 700 of FIG. 1 is inverted upside down.

(6th Example)
FIG. 28 is a circuit diagram of the phase interpolator 700G according to the sixth embodiment. In the circuit unit 720, the first path 724 and the second path 726 include three switches SW _{A1 to} SW _A3 and SW _{B1 to} SW _B3 , respectively, as in the first embodiment. Each switch is a NMOS transistor.

The initialization circuit 710 includes an initialization transistor _MN1 which is an NMOS transistor and a logic gate 712. In this embodiment, the logic gate 712 is an AND (logical product) gate.

FIG. 29 is an operation waveform diagram of the phase interpolator 700G of FIG. 28. As described with reference to FIGS. 27 to 29, a phase interpolator 700 triggered by a negative edge can also be configured. Further, the switches SW _A3 and SW _B3 may be omitted from the phase interpolator 700G of FIG. 28. Alternatively, switches SW _A2 and SW _B2 may be omitted from the phase interpolator 700G of FIG. 28.

The phase interpolator has been described above based on the embodiment. This embodiment is an example, and it will be understood by those skilled in the art that various modifications are possible for each of these components and combinations of each processing process, and that such modifications are also within the scope of the present invention. is there. Hereinafter, such a modification will be described.

Also in the second embodiment (FIGS. 24 to 26), a configuration in which the P channel and the N channel are interchanged by reversing the top and bottom is also effective as one aspect of the present invention.

A resistor R _g may be inserted on both the upper side and the lower side of the first path 724, and the second path 726 may be connected in parallel with the first path 724.

When the control code D _CNT is given as an M-bit binary code, the control code D _CNT may be expanded into a plurality of bits sel [0] to sel [N-1]. For this, a decoder that converts a binary code into a thermometer code may be used, but the following processing may be simply performed. For example, when M = 3, N = 2 ^M = 8 gradations can be controlled. In this case, the binary MSB (Most Significant Bit) is set to sel [0] to sel [3], the second bit of the binary is set to sel [4] to sel [5], and the binary LSB (Least Significant Bit). May be set to sel [6].

<Use>
Subsequently, the use of the timing generator 100 will be described. FIG. 30 is a circuit diagram of a delay pulse generator 200 using the timing generator 100. The delay pulse generator 200 includes a set signal generator 210, a reset signal generator 220, an output circuit 230, and a reference signal generator 240. At least one of the set signal generator 210 and the reset signal generator 220 includes the timing generator 100 of FIG.

The reference signal generator 240 generates reference timing signals φa ₀ and φb ₀ having a predetermined frequency and supplies them to the set signal generator 210 and the reset signal generator 220. The set signal generator 210 generates a set signal S _SET having an edge at timing t ₁ corresponding to the control code D _{CNT_SET} . The reset signal generator 220 generates a reset signal S _RESET having an edge at timing t ₂ corresponding to the control code D _{CNT_RESET} . The output circuit 230 is the first level (e.g., high) in response to the set signal _{S SET,} generates a pulse signal _{S OUT} to transition to the second level in response (e.g., low) to the reset signal _{S RESET.} The configuration of the output circuit 230 is not limited, and can be configured by a flip-flop or a latch.

The delay pulse generator 200 can set the edge of the pulse signal S _OUT at arbitrary timings t ₁ and t ₂ according to the control codes D _{CNT_SET} and D _{CNT_RESET} . The delay pulse generator 200 can be used, for example, as a digital pulse width modulator (DPMW).

When used as a digital pulse width modulator, since the period of the pulse signal S _OUT is constant, one of the values of the control codes D _{CNT_SET} and D _{CNT_RESET} (that is, the positive edge (rising edge, leading edge) of the pulse signal S _OUT ). And the negative edge (one timing of the falling edge, the trailing edge) is fixed, and the other is variable, so that the pulse width (the length of the high section or the low section) can be changed.

Alternatively, when fixing the timing of the positive edge of the pulse signal S _OUT , only the reset signal generator 220 may be configured by using the timing generator 100, and the set signal generator 210 may be configured by a delay circuit. On the contrary, when the timing of the negative edge of the pulse signal S _OUT is fixed, only the set signal generator 210 may be configured by using the timing generator 100, and the reset signal generator 220 may be configured by a delay circuit.

Subsequently, the use of the delay pulse generator 200 will be described. The delay pulse generator 200 can be used for various digital controller ICs (Integrated Circuits).

FIG. 31 is a block diagram of a digitally controlled switching power supply 550. The switching power supply 550 includes a peripheral circuit 552 in addition to the controller 560. Although the buck converter is shown in FIG. 31, the topology of the peripheral circuit 552 is not limited to that, and various circuit configurations such as a boost converter, a buck-boost converter, a flyback converter, and a forward converter can be adopted.

The controller 560 is an IC (Integrated Circuit) integrated in one semiconductor chip. Transistor _M H, _{M L} may be integrated in the controller 560. A feedback signal V _FB corresponding to the output voltage V _OUT is input to the feedback (FB) pin of the controller 560. The A / D converter 562 converts the feedback signal V _FB into a digital signal D _FB . The digital controller 564 feedback-controls the duty ratio command value DUTY so that the digital signal D _FB approaches the target value D _REF . The digital controller 564 includes a PI (proportional / integral) controller or a PID (proportional / integral / derivative) controller.

Digital pulse width modulator 566 is configured using the architecture of the delay pulse generator 200 of Figure 30, the high-side pulse S _H having a pulse width corresponding to the duty ratio command value DUTY, therewith complementary low-side pulses S Generate _L. High-side driver 568H, respectively low-side driver 568L, depending high side pulse _{S H,} the low-side pulse _{S L,} the transistor _M H of the peripheral circuit 552, drives the _{M L.}

FIG. 31 is a block diagram of a digitally controlled switching power supply 300. The switching power supply 300 includes a peripheral circuit 310 in addition to the controller 400. Although the buck converter is shown in FIG. 31, the topology of the peripheral circuit 310 is not limited to that, and various circuit configurations such as a boost converter, a buck-boost converter, a flyback converter, and a forward converter can be adopted.

The controller 400 is an IC (Integrated Circuit) integrated in one semiconductor chip. The transistors MH and ML may be integrated in the controller 400. A feedback signal VFB corresponding to the output voltage VOUT is input to the feedback (FB) pin of the controller 400. The A / D converter 410 converts the feedback signal VFB into a digital signal DFB. The digital controller 420 feedback-controls the duty ratio command value DUTY so that the digital signal DFB approaches the target value DREF. The digital controller 420 includes a PI (proportional / integral) controller or a PID (proportional / integral / derivative) controller.

Digital pulse width modulator 430 is configured using the architecture of the delay pulse generator 200 of Figure 30, the high-side pulse S _H having a pulse width corresponding to the duty ratio command value DUTY, therewith complementary low-side pulses S Generate _L. High-side driver 440H, respectively low-side driver 440L is a high-side pulse _{S H,} in accordance with the low-side pulse _{S L,} the transistor _M H of the peripheral circuit 310, drives the _{M L.}

Although the constant voltage output has been described in this example, the present invention can also be applied to the constant current output.

FIG. 32 is a block diagram of the motor drive system 500. The motor drive system 500 includes a three-phase motor 502, a three-phase inverter 510, a rotation speed detector 520, and a motor controller 600.

The rotation speed detector 520 generates a rotation speed signal S _DET indicating the rotation speed of the three-phase motor 502. The motor controller 600 controls the three-phase inverter 510 so that the current rotation speed indicated by the rotation speed signal S _DET approaches the target rotation speed.

The motor controller 600 is an IC (Integrated Circuit) integrated in one semiconductor chip. The motor controller 600 includes a digital controller 610, a digital pulse modulator 620U to 620W, and a gate driver 630U to 630W.

The digital controller 610 generates duty ratio command values DUTY_U to DUTY_W so that the current rotation speed indicated by the rotation speed signal S _DET approaches the target rotation speed. The configuration and control method of the digital controller 610 are not particularly limited, and a known technique may be used. Digital pulse modulator 620U~630W generates a pulse signal _{S OUT _U~S} OUT _W having a pulse width corresponding to a corresponding duty ratio command value DUTY_U～DUTY_W. The gate driver 630U~630W, depending on the corresponding pulse signal _{S OUT _U~S} OUT _W, drives the corresponding leg of the three-phase inverter 510.

In this example, the rotation speed control system has been described, but the present invention can also be applied to a motor drive system for torque control and position control. Further, the digital pulse modulator 620 and the gate driver 630 may be integrated into one IC.

33 (a) and 33 (b) are block diagrams of an audio circuit. FIG. 33 (a) is a single-ended system, and FIG. 33 (b) is a BTL (Bridged Transformerless) system, but the basic configuration is the same. The audio circuit 800 includes an electroacoustic conversion element 802, a filter 804, and an audio IC 820. The electroacoustic conversion element 802 is a speaker or headphones, and converts an electric signal into an acoustic signal. The filter 804 removes the high frequency component of the PWM (Pulse Width Modulation) signal generated by the audio IC 820 and supplies it to the electroacoustic conversion element 802.

The audio IC 820 includes a digital pulse width modulator 822, a gate driver 824, and a class D amplifier 826. The digital pulse width modulator 822 converts the digital audio signal _DIN into the PWM signal S _PWM . The gate driver 824 drives the class D amplifier 826 in response to the PWM signal.

In FIGS. 33 (a) and 33 (b), the digital pulse width modulator 822 can be configured using the architecture of the delay pulse generator 200 described above.

FIG. 34 is a block diagram of the light emitting device. The light emitting device 900 includes an LED 902, a dimming circuit 904, a DC / DC converter 906, and an LED driver controller 920.

The DC / DC converter 906 supplies the drive voltage V _OUT to the _LED 902 and outputs a constant amount of the stabilized current I _LED . The topology of the DC / DC converter 906 is not limited, and a synchronous rectification type step-down converter may be used. Alternatively, the DC / DC converter 906 may be a boost converter or a flyback converter. The sense resistor _RS is provided in series with the _LED 902 to detect the current I _LED flowing through the _LED 902 (or dimming circuit 910). The dimming circuit 910 switches the current I _LED flowing through the _LED 902 at a duty ratio according to the target brightness. The dimming circuit 910 includes a bypass switch 912 parallel to the LED 902 and a digital pulse width modulator 914. The digital pulse width modulator 914 generates a PWM signal having a duty ratio corresponding to the target brightness of the LED 902, and drives the bypass switch 912 according to the PWM signal. The digital pulse width modulator 914 can be configured using the architecture of the delay pulse generator 200 described above.

The LED driver controller 920 drives the switching element 908 of the DC / DC converter 906 so that the output current I _LED of the DC / DC converter 906 is constant. The A / D converter 922 converts one of the current detection signals _VCS into a digital value in the operating region where the current I _LED is large to some extent. The controller 924, the current detection signal _{V CS} so as to approach the target value, and generates a duty ratio command value DUTY (constant current mode). Current _{I LED} is a small operation region, because the detection of the current detection signal _{V CS} is difficult, A / D converter 922 converts the output voltage _{V OUT} to a digital value. The controller 924 generates a duty ratio command value DUTY so that the output voltage V _OUT approaches the target value (constant voltage mode). The digital pulse width modulator 926 generates a PWM signal S _PWM according to the duty ratio command value DUTY. The driver 928 drives the switching element of the DC / DC converter 906 in response to the PWM signal S _PWM . The digital pulse width modulator 926 may be configured using the architecture of the delay pulse generator 200 described above.

Although the present invention has been described using specific terms and phrases based on the embodiments, the embodiments merely indicate the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangement changes are permitted without departing from the ideas of the present invention.

100 Timing Generator 102 Phase Interchangeer 110 Delay Stage 112, 114, PI Phase Interpreter 130 Code Scrambler 200 Delay Pulse Generator 210 Set Signal Generator 220 Reset Signal Generator 230 Output Circuit 300 Switching Power Supply 310 Peripheral Circuit 400 Controller 410 A / D Converter 420 Digital Controller 430 Digital Pulse Width Modulator 440 Driver 500 Motor Drive System 502 Three-Phase Motor 510 Three-Phase Inverter 520 Rotation Detector 600 Motor Controller 610 Digital Controller 620 Digital Pulse Modulator 630 Gate Driver 700 Phase Interpolator 702 1st line 704 2nd line 706 Intermediate line 710 Initialization circuit 712 Logic gate 720 Circuit unit 722 Inverter 724 1st path 726 2nd path 730 Output circuit 800 Audio IC
802 Digital Pulse Width Modulator 804 Gate Driver 806 Class D Amplifier 900 Light Emitting Device 902 LED
906 DC / DC Converter 910 Dimming Circuit 912 Bypass Switch 914 Digital Pulse Width Modulator 920 LED Driver 922 A / D Converter 924 Controller 926 Digital Pulse Width Modulator 928 Driver

Claims (12)

A timing generator that receives a first reference timing signal and a second reference timing signal and generates an output timing signal having an edge at a timing corresponding to a control code.
A plurality of phase interpolators forming M stages (M is an integer of M ≧ 2) and
A code scrambler that generates a code to be set in the plurality of phase interpolators based on the control code, and
With
The delay stages of the first stage to the (M-1) stage include the pair of phase interpolators.
The phase interpolator has a first input node, a second input node, and an output node, and the output node is set to the earlier of the signal of the first input node and the signal of the second input node. It is configured to be able to generate a delayed signal for a time corresponding to the code.
In the first stage, the first reference timing signal is input to the first input node of the phase interpolator, and the second reference timing signal is input to the second input node of the phase interpolator. ,
In the i-th stage (2 ≦ i ≦ M), the first and second input nodes of the phase interpolator are one of the pair of the phase interpolators in the (i-1) stage, and the other output node, respectively. Connected with
The code scrambler is a timing generator characterized in that, in at least one of the delay stages of the M stage, a pair of delay amounts set in the pair of phase interpolators can be dynamically exchanged. The timing generator according to claim 1, wherein the order of the first reference timing signal and the second reference timing signal can be scrambled. M = 2
(I) A state in which the first reference timing signal precedes the second reference timing signal and the delay amount of one of the first-stage phase interpolators pair is smaller than the delay amount of the other.
(Ii) A state in which the first reference timing signal follows the second reference timing signal, and the delay amount of one of the pairs of the first-stage phase interpolators is smaller than the delay amount of the other.
(Iii) A state in which the first reference timing signal precedes the second reference timing signal and the delay amount of one of the pairs of the first-stage phase interpolators is larger than the delay amount of the other.
(Iv) A state in which the first reference timing signal follows the second reference timing signal, and the delay amount of one of the pairs of the first-stage phase interpolators is larger than the delay amount of the other.
The timing generator according to claim 1 or 2, wherein is dynamically switchable. The timing generator according to claim 1 or 2, wherein M ≧ 3, and 2 × M states can be switched. The phase interpolator is
The first line to which the first voltage is supplied and
The second line to which the second voltage is supplied and
With the middle line
A capacitor whose one end is connected to the intermediate line,
An initialization circuit that initializes the voltage of the capacitor while the first signal input to the first input node and the second signal input to the second input node are both at the first level.
A plurality of circuit units corresponding to each bit included in the code and connected in parallel between the intermediate line and the second line,
An output circuit that generates an output signal whose level changes when the voltage of the capacitor crosses a predetermined threshold value.
With
Each circuit unit
A resistor and a first path provided in series between the intermediate line and the second line,
A second path provided in parallel with the first path,
Including
The first path is configured to be turned on when the first signal is at the second level and the corresponding bit of the code is the first value, and the second path is such that the second signal is said. The timing generator according to any one of claims 1 to 4, which is at the second level and is configured to be turned on when the corresponding bit of the code is the second value. The timing generator according to claim 5, wherein the code is a thermometer code, and the code scrambler scrambles a bit to be marked. A set signal generator that generates a set signal and
A reset signal generator that generates a reset signal and
An output circuit that outputs a pulse signal that transitions to the first level according to the set signal and to the second level according to the reset signal.
With
A semiconductor integrated circuit, wherein at least one of the set signal generator and the reset signal generator includes the timing generator according to any one of claims 1 to 6. The semiconductor integrated circuit according to claim 7, wherein the pulse signal is a pulse width modulated signal. The semiconductor integrated circuit according to claim 7 or 8, wherein the controller is a class D amplifier. The semiconductor integrated circuit according to claim 7 or 8, wherein the controller is a DC / DC converter. The semiconductor integrated circuit according to claim 7 or 8, wherein the controller is an LED driver. The semiconductor integrated circuit according to claim 7 or 8, wherein the controller is a motor.