JP2020167462A - High voltage clock generation circuit - Google Patents

Abstract

To provide a sampling clock generation circuit capable of suppressing a delay caused when shifting a level of a low voltage clock to a level of a high voltage clock.SOLUTION: A high voltage clock generation circuit 100 comprises a clock generation unit which generates a first clock signal whose signal level changes according to a clock timing of a base clock signal, and generates a low voltage clock signal having the same voltage level as the basic clock signal on the basis of the basic clock signal, a DLL circuit which generates a second clock signal having a different phase from the first clock signal, and a level shifter which generates a high voltage clock signal by shifting the level of the second clock signal and supplies the generated high voltage clock signal to the DLL circuit. The DLL circuit receives supply of the first clock signal, the low voltage clock signal, and the high voltage clock signal, and generates the second clock signal by delaying the first clock signal according to a phase difference between the low voltage clock signal and the high voltage clock signal.SELECTED DRAWING: Figure 1

Description

The present invention relates to a high voltage clock generation circuit.

In recent years, the drive circuits of LCD (Liquid Crystal Display) drivers and OLED (Organic Light Emitting Diode) drivers have become highly integrated, and while the drive circuits are driven by high voltage power supplies, the low voltage side that drives logic elements The power supply voltage of OLED is getting lower and lower.

Further, in a large OLED used for a TV or the like, the characteristics of the panel element vary and deterioration with time occurs. Therefore, in order to correct the pixel characteristics, the OLED driver is equipped with an ADC (Analog to Digital Converter) for measuring the characteristics of the panel element, and the element characteristics are measured. As the speed of AD conversion by the ADC is increased, a clock generation circuit that generates a clock for sampling the voltage and current of the display panel is required. For example, a clock generation circuit that outputs a plurality of clocks having a constant phase relationship according to the period of an external clock has been proposed (for example, Patent Document 1).

JP-A-2010-128988

In a clock generation circuit mounted on a large-sized OLED driver or the like, a clock created by a low-voltage logic circuit is converted into a high-voltage clock by a level shifter. By turning the switch on and off using such a high-voltage clock, it becomes possible to sample a high-voltage signal in the sample hold circuit.

However, there is a clock delay due to the operation of Sao and the level shifter, which converts the clock generated by the low-voltage logic circuit into a high-voltage clock, and the clock timing varies greatly depending on the temperature, voltage, and process. This variation causes an obstacle to speeding up the sampling operation.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a high-voltage clock generation circuit capable of suppressing a delay generated when a low-voltage clock is level-shifted to a high-voltage clock. To do.

The high-voltage clock generation circuit according to the present invention generates a first clock signal whose signal level changes according to the clock timing of the basic clock signal based on the basic clock signal, and has the same voltage level as the basic clock signal. A clock generation unit that generates a low-voltage clock signal having the above, a PLL circuit that generates a second clock signal having a phase different from that of the first clock signal, and a level-shifted second clock signal to produce the high-voltage clock signal. It has a level shifter that is generated, outputs the high-voltage clock signal, and supplies the DLL circuit, and the DLL circuit supplies the first clock signal, the low-voltage clock signal, and the high-voltage clock signal. In response to the above, the second clock signal is generated by delaying the first clock signal according to the phase difference between the low voltage clock signal and the high voltage clock signal.

According to the high-voltage clock generation circuit of the present invention, it is possible to suppress the delay that occurs when the low-voltage clock is level-shifted to the high-voltage clock.

It is a block diagram which shows the structure of the high voltage clock generation circuit of this Example. It is a circuit diagram which shows the structure of the DLL circuit of this Example. It is a circuit diagram which shows the structure of the sample hold circuit of this Example. It is a time chart which shows the time change of each signal. It is a graph which shows the relationship between the voltage of a control node and a delay time.

Hereinafter, preferred embodiments of the present invention will be described in detail. In the description and the accompanying drawings in each of the following examples, substantially the same or equivalent parts are designated by the same reference numerals.

The high-voltage clock generation circuit of this embodiment is a clock signal as a high-voltage signal (hereinafter, referred to as a high-voltage clock signal) based on a clock signal (hereinafter, referred to as a low-voltage clock signal) generated by a low-voltage logic circuit. ) Is a circuit that generates. The high-voltage clock signal generated by the high-voltage clock generation circuit of this embodiment is used as a sampling clock for AD conversion for measuring the characteristics of the elements of the display panel in, for example, a display driver.

FIG. 1 is a block diagram showing a configuration of a high voltage clock generation circuit 100 of this embodiment. The high-voltage clock generation circuit 100 is composed of a clock generation unit 11, a DLL (Delayed Locked Loop) circuit 12, and a level shifter 13.

The clock generation unit 11 receives an input of a basic clock signal CLK generated by a clock signal source (not shown) which is a low voltage logic circuit provided outside the high voltage clock generation circuit 100. Then, the clock generation unit 11 generates low-voltage clock signals S3CK and H3CK based on the basic clock signal CLK. Further, the clock generation unit 11 generates the first clock signal CK1 based on the basic clock signal CLK and outputs it from the output terminal HVO.

The first clock signal CK1 output from the clock generation unit 11 is supplied to the input terminal IN of the DLL circuit 12. Further, the low voltage clock signal H3CK output from the clock generation unit 11 is supplied to the first terminal T1 of the DLL circuit 12.

The DLL circuit 12 receives the supply of the high voltage clock signal H3CK_HV output from the level shifter 13 to the second terminal T2. Then, the phase is adjusted so that the rising edge of the low voltage clock signal H3CK and the high voltage clock signal H3CK_HV have the same timing. The DLL circuit 12 supplies the level shifter 13 with a second clock signal CK2 that reflects the result of the phase adjustment.

FIG. 2 is a circuit diagram showing the configuration of the DLL circuit 12. The DLL circuit 12 is composed of a phase comparison block 21, a charge pump block 22, and a DL block 23.

The phase comparison block 21 includes a NAND gate ND1, a first D flip-flop DFF1, a second D flip-flop DFF2, and an inverter INV1.

The NAND gate ND1 is a 2-input NAND gate circuit. The NAND gate ND1 receives the input of the low voltage clock signal H3CK at one input end and the high voltage clock signal H3CK_HV at the other input end, and resets the negative logical product of the low voltage clock signal H3CK and the high voltage clock signal H3CK_HV. Output to RSTB.

The first D flip-flop DFF1 takes in the power supply voltage VDD according to the rise of the low voltage clock signal H3CK and outputs it as an output signal UP. The first D flip-flop DFF1 has a reset terminal connected to the reset node RSTB, and is reset (initialized) according to the fall of the potential of the reset node RSTB.

The second D flip-flop DFF2 takes in the power supply voltage VDD according to the rise of the high voltage clock signal H3CK_HV and outputs it as an output signal DOWN. The second D flip-flop DFF2 has a reset terminal connected to the reset node RSTB, and is reset (initialized) according to the fall of the potential of the reset node RSTB.

The input end of the inverter INV1 is connected to the output terminal of the first D flip-flop DFF1. The inverter INV1 outputs an inverted signal obtained by inverting the output signal UP output from the first D flip-flop DFF1.

The charge pump block 22 has transistors M1, M2, M3, M4, M5 and M6, a resistor R0, and a capacitor C0.

The transistor M1 is composed of, for example, a P-channel MOSFET, and the drain is connected to the control node CTRL. The transistor M1 receives an inverted signal obtained by inverting the output signal UP of the first D flip-flop DFF1 at the gate, and is controlled to be turned on and off according to the signal level of the inverted signal. That is, the transistor M1 is turned on when the signal level of the inverted signal is logic level 0, and turned off when the signal level of the inverted signal is logic level 1.

The transistor M2 is composed of, for example, an N-channel MOSFET, and the drain is connected to the control node CTRL. The transistor M2 receives the output signal DOWN of the second D flip-flop DFF2 from the gate, and is controlled to be turned on and off according to the signal level of the output signal DOWN. That is, the transistor M2 is turned on when the signal level of the output signal DOWN is logic level 1, and is turned off when the signal level of the output signal DOWN is logic level 0.

The transistors M3 and M4 are composed of, for example, a P-channel MOSFET. The sources of the transistors M3 and M4 are connected to each other and receive a power supply voltage VDD. Further, the gates of the transistors M3 and M4 are connected to each other. The drain of the transistor M4 is connected to the source of the transistor M1. The transistors M3 and M4 have a function as a current mirror for passing a current corresponding to the current flowing between the source and drain of the transistor M3 between the source and drain of the transistor M1.

The transistors M5 and M6 are composed of, for example, N-channel MOSFETs. The sources of the transistors M5 and M6 are connected to each other and receive the ground potential VSS applied. Further, the gates of the transistors M5 and M6 are connected to each other. The drain of the transistor M6 is connected to the source of the transistor M2. The transistors M5 and M6 have a function as a current mirror for passing a current corresponding to the current flowing between the drain sources of the transistor M5 between the drain sources of the transistor M2.

One end of the resistor R0 is connected to the drain of the transistor M3, and the other end is connected to the drain of the transistor M5. The resistor R0 has a predetermined resistance value, and has a function as a constant current transmission unit that transmits a constant current to a current line including the transistor M3, the resistor R0, and the transistor M5.

One end of the capacitor C0 is connected to the control node CTRL, and the other end is grounded. The capacitor C0 is charged and discharged by the current flowing through the control node CTRL. The potential of the control node CTRL changes depending on the charging / discharging of the capacitor C0.

The DL block 23 is a variable delay circuit composed of inverters INV2, INV3, INV4 and INV5. The input end of the inverter INV2 is connected to the input terminal IN of the DLL circuit 12 and receives the input of the first clock signal CK1. The inverter INV2 outputs a signal obtained by inverting the first clock signal CK1.

The input end of the inverter INV3 is connected to the output end of the inverter INV2. The inverter INV3 outputs a signal obtained by inverting the output signal of the inverter INV2. The input end of the inverter INV4 is connected to the output end of the inverter INV3. The inverter INV4 outputs a signal obtained by inverting the output signal of the inverter INV3. The input end of the inverter INV4 is connected to the output end of the inverter INV3. The inverter INV4 outputs a signal obtained by inverting the output signal of the inverter INV3.

From the DL block 23, a signal in which the first clock signal CK1 is delayed via INV2 to INV5 is output as the second clock signal CK2. Then, the delay time (delay time) is adjusted according to the voltage of the control node CTRL.

Referring to FIG. 1 again, the level shifter 13 generates high-voltage clock signals S3CK_HV and H3CK_HV by level-shifting the second clock signal CK2 supplied from the PLL circuit 12 to the input terminal IN to a high-voltage signal. The level shifter 13 outputs both the high-voltage clock signals S3CK_HV and H3CK_HV to the sample hold circuit provided outside the high-voltage clock generation circuit 100, while the high-voltage clock signal H3CK_HV is fed back to the PLL circuit 12 via the buffer 14. To do.

FIG. 3 is a circuit diagram showing a configuration of a sample hold circuit 200 that receives inputs of high voltage clock signals S3CK_HV and H3CK_HV.

The sample hold circuit 200 includes an amplifier circuit AMP1, capacitors C1, C2, C3 and C4, and switches SW1, SW2, SW3, SW4, SW5, SW6 and SW7.

The switches SW1 and SW2 are switches that are turned on and off based on the high voltage clock signal S3CK_HV. SW4, SW5, SW6 and SW7 are switches that are turned on and off based on the low voltage clock signal S3CK. The low-voltage clock signal S3CK and the high-voltage clock signal S3CK_HV of this embodiment are also signals whose rising timings are synchronized. Therefore, the switches SW1 and SW2 and the switches SW4, SW5, SW6 and SW7 are controlled to be turned on at the same timing.

On the other hand, the switch SW3 is a switch that turns on and off based on the high voltage clock signal H3CK_HV. In this embodiment, the high-voltage clock signal H3CK_HV has a signal waveform that falls in response to the rise of the high-voltage clock signal S3CK_HV and rises in response to the fall of the high-voltage clock signal S3CK_HV. Therefore, the switch SW3 is controlled so that the switches SW1 and SW2 are turned off during the on period and the switches SW1 and SW2 are turned on (that is, complementarily turned on and off) during the off period.

One end of the capacitor C1 is connected to the switch SW2 and receives a negative input voltage INN via the switch SW2. The other end of the capacitor C1 is connected to the inverting input end of the amplifier circuit AMP1 and receives the bias voltage bias via the switch SW5. When the switches SW2 and SW5 are on, the capacitor C1 stores an electric charge based on the potential difference between the negative input voltage INN and the bias voltage bias.

One end of the capacitor C2 is connected to the switch SW1 and receives a positive input voltage INP via the switch SW1. The other end of the capacitor C2 is connected to the non-inverting input end of the amplifier circuit AMP1 and receives the bias voltage bias via the switch SW4. When the switches SW1 and SW4 are on, the capacitor C2 stores an electric charge based on the potential difference between the positive input voltage INP and the bias voltage bias.

Further, one end of the capacitor C1 and the other end of the capacitor C2 are connected via the switch SW3. When the switch SW3 is turned on and one end of each of the capacitors C1 and C2 is connected, the electric charge stored in the capacitors C1 and C2 is retained.

One end of the capacitor C3 is connected to the inverting input end of the amplifier circuit AMP1, and the bias voltage bias is supplied via the switch SW5. The other end of the capacitor C3 is connected to the switch SW7 and receives the supply of the common voltage CM via the switch SW7. When the switches SW5 and SW7 are on, the capacitor C3 stores an electric charge based on the potential difference between the common voltage CM and the bias voltage bias.

One end of the capacitor C4 is connected to the non-inverting input end of the amplifier circuit AMP1, and the bias voltage bias is supplied via the switch SW4. The other end of the capacitor C4 is connected to the switch SW6 and receives the supply of the common voltage CM via the switch SW6. When the switches SW5 and SW7 are on, the capacitor C4 stores an electric charge based on the potential difference between the common voltage CM and the bias voltage bias.

The amplifier AMP1 amplifies the voltage supplied to the non-inverting input terminal and the inverting input terminal, and outputs the voltage from the positive output terminal O1P and the negative output terminal O1N. During the sample period when switches SW1, SW2, SW4, SW5, SW6 and SW7 are on and switch SW3 is off, each capacitor is charged. On the other hand, during the hold period when the switches SW1, SW2, SW4, SW5, SW6 and SW7 are off and the switch SW3 is on, the output voltages of the positive output end O1P and the negative output end O1N are held.

Next, the operation of the high voltage clock generation circuit 100 of this embodiment will be described. FIG. 4 is a time chart showing signals generated and input / output in each part of the high voltage clock generation circuit 100 of this embodiment.

The clock generation unit 11 generates the internal clock signal S0CK based on the basic clock signal CLK supplied from the outside of the high voltage clock generation circuit 100. The internal clock signal S0CK is, for example, a signal whose signal level transitions to the logic level 1 and the logic level 0 at the same timing as the basic clock signal CLK.

Further, the clock generation unit 11 delays the basic clock signal CLK by an internal delay circuit (not shown) provided inside the clock generation unit 11 to generate delay clock signals DL1, DL2 and DL3. For example, the delay clock signals DL1, DL2, and DL3 are signals in which the basic clock signal CLK is sequentially delayed at a predetermined delay interval.

The clock generation unit 11 generates the low voltage clock signal S3CK based on the delay clock signals DL1, DL2 and DL3. For example, the low-voltage clock signal S3CK is generated by the logical product of the delay clock signals DL2 and DL3, and has a signal waveform that rises at the timing when the delay clock signal DL3 rises and falls at the timing when the delay clock signal DL2 falls. That is, the low-voltage clock signal S3CK is a signal waveform in which both the delay clock signals DL2 and DL3 have a logic level 1 signal level during the logic level 1 period. On the other hand, the low-voltage clock signal H3CK is generated by the logical product of the delay clock signals DL2 and DL3, and has a signal waveform that rises at the timing when the delay clock signal DL3 falls and falls at the timing when the delay clock signal DL2 rises. That is, the low-voltage clock signal H3CK is a signal waveform in which both the delay clock signals DL2 and DL3 have a signal level of logic level 1 in a period of logic level 0.

The clock generation unit 11 generates the first clock signal CK1 based on the internal clock signal S0CK and outputs it from the output terminal HVO. The first clock signal CK1 is, for example, a clock signal in which the signal level of the internal clock signal S0CK is inverted. The first clock signal CK1 is supplied to the input terminal IN of the DLL circuit 12.

The low-voltage clock signal H3CK output from the clock generation unit 11 is supplied to the first terminal T1 of the DLL circuit 12. The high-voltage clock signal H3CK_HV feedback-supplied from the level shifter 13 is supplied to the second terminal T2 of the DLL circuit 12.

The PLL circuit 12 adjusts the phases so that the phases of the low-voltage clock signal H3CK and the high-voltage clock signal H3CK_HV are aligned. The operation of each part (see FIG. 2) of the DLL circuit 12 differs depending on which of the low-voltage clock signal H3CK and the high-voltage clock signal H3CK_HV rises faster.

[When the rise of H3CK is earlier than the rise of H3CK_HV]
When the rise of the low-voltage clock signal H3CK is earlier than the rise of the high-voltage clock signal H3CK_HV, first, the output signal UP of the first D flip-flop DFF1 of the DLL circuit 12 rises in response to the rise of the low-voltage clock signal H3CK. The inverter INV1 outputs an inverted signal obtained by inverting the output signal UP of the first D flip-flop DFF1.

The transistor M1 is turned on by receiving the supply of the inverting signal of logic level 0 to the gate. As a result, the constant current generated by the resistor R0 flows between the source and drain of the transistor M1. The constant current flowing between the source and drain of the transistor M1 charges the control node CTRL to raise the voltage.

Next, the output signal DOWN of the second D flip-flop DFF2 rises in response to the rise of the high voltage clock signal H3CK_HV. The output signal DOWN is supplied to the gate of the transistor M2.

The transistor M2 is turned on in response to the output signal DOWN of the logic level 1, and a constant current generated by the resistor R0 flows between the drain sources of the transistor M2. The constant current flowing between the drain and source of the transistor M2 discharges the control node CTRL and slightly reduces the voltage.

At the same time, the potential of the reset node RSTB drops due to the output of the NAND gate ND1, and the first D flip-flop DFF1 and the second D flip-flop DFF2 are reset.

When the voltage of the control node CTRL rises, the delay (delay time) in the DL block 23 changes, and the timing at which the signal input from the input terminal IN is output from the output terminal OUT becomes earlier. As shown in FIG. 4, the higher the voltage of the control node CTRL, the shorter the delay time.

When the DL transition timing is earlier in this way, the transition timing of the high-voltage clock signal H3CK_HV is earlier, and the transition timing of the low-voltage clock signal H3CK is approached.

[When the rise of H3CK_HV is faster than the rise of H3CK]
When the rise of the high voltage clock signal H3CK_HV is earlier than the rise of the low voltage clock signal H3CK, first, the output signal DOWN of the second D flip-flop DFF2 rises according to the rise of the high voltage clock signal H3CK_HV.

The transistor M2 is turned on by receiving the output signal DOWN of logic level 1 from the gate. As a result, a constant current generated by the resistor R0 flows between the drain sources of the transistor M2. The constant current flowing between the drain and source of the transistor M2 discharges the control node CTRL to reduce the voltage.

Next, the output signal UP of the first D flip-flop DFF1 rises in response to the rise of the low voltage clock signal H3CK. The output signal UP is supplied to the gate of the transistor M1. The inverter INV1 outputs an inverted signal obtained by inverting the output signal UP of the first D flip-flop DFF1.

The transistor M1 is turned on by receiving the supply of the inverting signal of logic level 0 to the gate. As a result, the constant current generated by the resistor R0 flows between the source and drain of the transistor M1. The constant current flowing between the source and drain of the transistor M1 charges the control node CTRL and slightly raises the voltage.

At the same time, the potential of the reset node RSTB drops due to the output of the NAND gate ND1, and the first D flip-flop DFF1 and the second D flip-flop DFF2 are reset.

When the voltage of the control node CTRL decreases, the delay (delay time) in the DL block 23 changes, and the timing at which the signal input from the input terminal IN is output from the output terminal OUT is delayed. As shown in FIG. 4, the lower the voltage of the control node CTRL, the longer the delay time.

When the DL transition timing is delayed in this way, the transition timing of the high-voltage clock signal H3CK_HV is delayed, and the transition timing of the low-voltage clock signal H3CK is approached.

By the above operation, the phase adjustment of the low voltage clock signal H3CK and the high voltage clock signal H3CK_HV is performed. The second clock signal CK2 reflecting the phase adjustment is output from the output terminal OUT. In the time chart of FIG. 4, the portion shown as “DLL” schematically shows the period during which the phase adjustment is performed.

The second clock signal CK2 is input to the input terminal IN of the level shifter 13. The level shifter 13 level-shifts the second clock signal CK2 to a high voltage signal and outputs the high voltage clock signals S3CK_HV and H3CK_HV.

As shown in the elliptical portion of the time chart of FIG. 4, the high-voltage clock signal H3CK_HV is a signal that rises at the same timing as the rise of the low-voltage clock signal H3CK. Further, the high-voltage clock signal S3CK_HV is a signal that falls at the same timing as the rise of the low-voltage clock signal H3CK.

The high-voltage clock signals S3CK_HV and H3CK_HV output from the level shifter 13 are supplied to the sample hold circuit 200. The period of logic level 1 of the high voltage clock signal S3CK_HV is the sample period by the sample hold circuit 200. Further, the period of the logic level 1 of the high voltage clock signal H3CK_HV is the hold period by the sample hold circuit 200.

In the sample hold circuit 200 shown in FIG. 3, the switches SW1, SW2, SW4, SW5, SW6 and SW7 are turned on during the sample period. On the other hand, the switch SW3 is turned off. As a result, the capacitor C1 is charged, and charges corresponding to the potential difference between the positive input voltage INP and the bias voltage bias are stored. Further, the capacitor C2 is charged, and charges corresponding to the potential difference between the negative input voltage INN and the bias voltage bias are stored. Further, the capacitors C3 and C4 are charged, and charges corresponding to the potential difference between the common voltage CM and the bias voltage bias are stored.

During the hold period, the switch SW3 is turned off, and the other switches SW1, SW2, SW4, SW5, SW6 and SW7 are turned off. As a result, the voltages of the positive output end O1P and the negative output end O1N of the amplifier circuit AMP1 are maintained.

As described above, the low-voltage clock signal H3CK and the high-voltage clock signal H3CK_HV are phase-adjusted by the PLL circuit 12, so that the low-voltage clock signal S3CK and the high-voltage clock signal S3CK_HV are also phase-adjusted in the same manner. Then, the sample hold circuit 200 is controlled by the low-voltage clock signal S3CK, the high-voltage clock signal S3CK_HV, and the high-voltage clock signal H3CK_HV whose phases are adjusted in this way, so that the hold period by the sample hold circuit 200 can be lengthened. it can. As a result, the charge rate of the hold switch and the amplifier can be sufficiently taken, so that highly accurate sampling can be performed.

As described above, according to the high-voltage clock generation circuit 100 of this embodiment, the low-voltage clock signal H3CK is generated by the PLL circuit 12 provided between the clock generation unit 11 and the level shifter 13 performing phase adjustment. It is possible to suppress the occurrence of a deviation (that is, delay) between the clock timing and the clock timing of the high voltage clock signal H3CK_HV.

Assuming that, unlike the present embodiment, the low-voltage clock signals S3CK and H3CK output from the clock generator are level-shifted to the high-voltage clock signals S3CK_HV and H3CK_HV by the level shifter as they are, each low-voltage clock signal and each A delay occurs due to the operation of the level shifter with the high voltage clock signal.

The amount of delay due to the level shifter varies greatly depending on the voltage level of the low voltage power supply (LV power supply), the voltage level of the high voltage power supply, the temperature, the process conditions, and the like. For example, suppose that the low-voltage power supply is set to a high voltage under a low-voltage condition, and the circuit constant is set so that the clock timings of the low-voltage clock signal H3CK and the high-voltage clock signal H3CK_HV are simultaneous under the process FAST condition. Then, when the low voltage power supply is set to a low voltage under the high temperature condition and the circuit is finished under the process SLOW condition, the clock timing of the high voltage clock signal H3CK_HV is significantly delayed from the clock timing of the low voltage clock signal H3CK. Therefore, the hold period by the sample hold circuit 200 is shortened, and the charge rate of the hold switch and the amplifier cannot be sufficiently taken.

On the other hand, according to the high-voltage clock generation circuit 100 of the present embodiment, even if the conditions such as process, temperature, and voltage are different, the clock timing of the low-voltage clock signal H3CK and the clock timing of the high-voltage clock signal H3CK_HV Is adjusted to have the same timing, so that the hold period is maximized. Therefore, since the charge rate of the hold switch and the amplifier can be maximized, highly accurate sampling is possible.

The high-voltage clock generation circuit of this embodiment can be applied to the application of sampling a high-voltage signal by generating a control signal from a controller or the like operating with a low-voltage power supply in order to sample the high-voltage signal. For example, in a display driver such as an LCD (Liquid Crystal Display) driver or an OLED driver, a low voltage signal is generated from an I / F such as a timing controller, a sampling signal is generated by a logic circuit inside the display driver, and a sampling signal is generated via a level shifter. A high voltage sampling control signal is generated.

The present invention is not limited to that shown in the above examples. For example, in the above embodiment, the case where the high voltage clock signal generated in this embodiment is used as the sampling clock for AD conversion in the display driver has been described as an example. However, in addition to this, it can be widely applied to products including high-voltage circuits such as power supply controllers and boost controllers.

Further, the configurations of the DLL circuit and the sample hold circuit shown in the above embodiment are merely examples, and a high voltage clock generation circuit can be configured by using a circuit that performs the same operation as these.

100 High-voltage clock generation circuit 11 Clock generation unit 12 DLL circuit 13 Level shifter 21 Phase comparison block 22 Charge pump block 23 DL block

Claims (4)

Based on the basic clock signal, a first clock signal whose signal level changes according to the clock timing of the basic clock signal is generated, and a low voltage clock signal having the same voltage level as the basic clock signal is generated. Department and
A DLL circuit that generates a second clock signal whose phase is different from that of the first clock signal.
A level shifter that level-shifts the second clock signal to generate the high-voltage clock signal, outputs the high-voltage clock signal, and supplies the high-voltage clock signal to the DLL circuit.
Have,
The PLL circuit receives the supply of the first clock signal, the low voltage clock signal, and the high voltage clock signal, and the first clock is supplied according to the phase difference between the low voltage clock signal and the high voltage clock signal. A high-voltage clock generation circuit characterized in that the second clock signal is generated by delaying the signal. The low-voltage clock signal is a pair of clock signals including a first low-voltage clock signal and a second low-voltage clock signal.
The clock generator supplies the first low-voltage clock signal to the DLL circuit.
The high voltage clock signal includes a first high voltage clock signal having a clock timing corresponding to the first low voltage clock signal and a second high clock signal having a clock timing corresponding to the second low voltage clock signal. It is a pair of clock signals consisting of a voltage clock signal and
The level shifter generates the first high-voltage clock signal and the second high-voltage clock signal based on the second clock signal, and supplies the first high-voltage clock signal to the DLL circuit.
The high voltage clock generation circuit according to claim 1. The PLL circuit charges or discharges the capacitance connected to the predetermined node according to the phase difference between the first low-voltage clock signal and the first high-voltage clock signal, and the potential of the predetermined node. The high-voltage clock generation circuit according to claim 2, wherein the second clock signal is generated by delaying the first clock signal with a delay time based on the above. It is connected to the sample hold circuit that performs AD by switching the charge and discharge of the capacitor.
The first low-voltage clock signal, the second low-voltage clock signal, the first high-voltage clock signal, and the second high-voltage clock signal are used as control signals for controlling charging / discharging of the capacitor. The high voltage clock generation circuit according to claim 2 or 3, wherein the sample hold circuit is supplied.

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