JP2020162041A - Output circuit and operational amplifier - Google Patents

Abstract

To simply and effectively suppress a wasteful heavy current flow inside an output circuit or an operational amplifier.SOLUTION: A class AB output circuit 10 includes an output control circuit 12, a minimum selector circuit 14 and a push-pull circuit 16. Between a positive electrode power terminal 20 and a negative electrode power terminal 22, the minimum selector circuit 14 connects in series a PMOS transistor M5, a PMOS transistor M4 and an NMOS transistor M3 of diode connection on one current route P1, and connects in series a PMOS transistor M7, an NMOS transistor M6 and a constant current source I4 on another current route P2.SELECTED DRAWING: Figure 1

Description

The present invention relates to a transistor integrated circuit that amplifies and outputs a signal, and more particularly to an output circuit composed of a CMOS circuit and an operational amplifier.

Many operational amplifiers used for amplifying various signals are provided with a push-pull class AB output circuit in the output stage in order to increase the output of amplification and reduce distortion. Generally, a push-pull type AB class output circuit has a pair of transistors that are connected in series with each other and operate in a complementary manner, and a bias circuit for setting the operating points of both transistors to class AB.

Conventionally, a class AB output circuit that employs a minimum selector circuit for this type of bias circuit has been known in response to a reduction in power supply voltage. A typical minimum selector circuit consisting of a CMOS analog circuit includes a NMOS transistor for an output forming a push-pull circuit and a MOSFET transistor and an NMOS transistor for a monitor that detect the drain currents of the NMOS transistors, respectively, and the MOSFET for those monitors. The one with the smaller monitor current obtained from the transistor and the NMOS transistor is passed through a MOS transistor connected to a diode to generate a minimum selector voltage by current-voltage conversion, and this minimum selector voltage is set to the reference voltage corresponding to the set operating point of class AB. It is configured to variably control the control voltage for the MOSFET transistor and the NMOS transistor in the output stage so as to match (for example, FIG. 1 of Patent Document 1).

In such a minimum selector circuit, the same conductive type monitoring MOS transistor is assigned to the output MOSFET transistor and the output NMOS transistor of the push-pull circuit, respectively. More specifically, the output MOSFET transistor is assigned to the monitor MOSFET transistor, and the gate electrodes of both are commonly connected. As a result, the control voltage applied to the gate electrode of the output MOSFET transistor is also applied to the gate electrode of the monitor MOSFET transistor at the same time. On the other hand, a monitor NMOS transistor is assigned to the output MOSFET transistor, and both gate electrodes are commonly connected. As a result, the control voltage applied to the gate electrode of the output NMOS transistor is also applied to the gate electrode of the monitor NMOS transistor at the same time.

Then, among the monitoring NMOS transistors and the monitoring NMOS transistors, the monitoring transistors having different conductivity types from the diode-connected MOS transistors are directly connected in series on the same current path as the diode-connected MOS transistors. On the other hand, the same conductive type monitoring transistor as the diode-connected MOS transistor is provided on a different current path, and is diode-connected via a current mirror circuit composed of a pair of MOS transistors having different conductive types from the diode-connected MOS transistor. It is indirectly connected in series with the MOS transistor of.

For example, when the diode-connected MOS transistor is an NMOS, the monitoring NMOS transistor is directly connected in series with the diode-connected NMOS transistor on the first current path. Then, the monitoring NMOS transistor is connected in series with one (reference side) MOSFET of the current mirror circuit on the second current path, and the other (dependent side) MOSFET of the current mirror circuit is connected to the first current path. Above, it is connected in series with a diode-connected NMOS transistor and a monitoring MOSFET transistor.

U.S. Pat. No. 7,557,658

When the class AB output circuit or the arithmetic amplifier including it amplifies and outputs a DC signal, for example, a pulse signal, push-pull when the pulse signal is not input or when the logic level of the pulse signal being input is "L". The output voltage of the circuit is clipped to the negative power supply potential (for example, ground potential) side via the output NMOS transistor on the sink side.

Also in this case, a minute current, that is, an idle current, corresponding to the operating point of the AB class flows through the output MOSFET transistor and the output NMOS transistor of the push-pull circuit. Here, the output NMOS transistor has an extremely small source-drain voltage (close to zero volt) and operates in an unsaturated (linear) characteristic region. Nevertheless, in order to obtain the required idle current, in the minimum selector circuit as described above, feedback control works and the control voltage applied to the output NMOS transistor rises to a considerably high level.

However, since the monitor NMOS transistor in which the output NMOS transistor and the gate electrode are commonly connected operate in the saturation characteristic region under a sufficiently large source-drain voltage, the control voltage for the output NMOS transistor is as described above. When it jumps to a considerably high level, it receives the same control voltage at its own gate electrode and causes a very large drain current to flow. This large current flows through only in the current path (second current path) of the monitoring NMOS transistor and the reference side MIMO transistor for the current mirror connected in series with the monitoring NMOS transistor, and generates a minimum selector voltage. It is not transmitted to the current path (first current path) of the diode-connected NMOS transistor. At this time, a small drain current of the monitor MOSFET transistor reflecting the drain current of the output MOSFET transistor selectively flows on the first current path. Therefore, there is no particular problem in terms of the functions of the minimum selector circuit or the AB class output circuit. However, the steady flow of such a meaningless large current in the bias circuit is not preferable in terms of power consumption reduction and power supply voltage reduction.

In this regard, the invention described in Patent Document 1 (FIG. 2) has a MOSFET in which the threshold value is particularly low between the MOSFET for monitoring and the reference-side MOSFET transistor for the current mirror on the second current path. Transistors are added in series, and the gate electrode of this added MOSFET transistor is commonly connected to the gate electrode of the output MOSFET transistor and the monitor MOSFET transistor. According to this configuration, when the output voltage of the push-pull circuit is clipped to the negative power supply potential side as described above and the control voltage for the output NMOS transistor jumps to a level considerably higher than the reference level, the output MOSFET transistor, The control voltage for the monitoring MOSFET transistor and the additional MOSFET transistor also jumps to a level considerably higher than the reference level, so that the additional MOSFET transistor cuts off the current on the second current path.

However, according to the solution method of Patent Document 1, since the threshold value of the additional MOS transistor is particularly low as compared with other MOS transistors, not only the design and manufacture of the integrated circuit becomes complicated, but also the additional MOS transistor is complicated. Bias conditions around the transistor ・ It is difficult to set. Furthermore, when the additional epitaxial transistor cuts off the current in the second current path, the current is also cut off in the current path (first current path) of the diode-connected NMOS transistor via the current mirror circuit, so that it is the minimum. The operation of the entire selector circuit or the entire class AB output circuit becomes unstable.

The present invention solves the above-mentioned problems of the prior art, and provides an output circuit capable of easily and effectively suppressing the flow of an unnecessary large current inside the bias circuit, and an operational amplifier including the output circuit. ..

The output circuit according to the first aspect of the present invention includes a first constant current source provided between the first power supply voltage terminal and the first node, the first power supply voltage terminal, and the second. A second constant current source provided between the nodes, a third constant current source provided between the third node receiving the signal current and the second power supply voltage terminal, and a source electrode. Is connected to the third node, the drain electrode is connected to the first node, and the first conductive type first MOS transistor that receives the reference voltage to the gate electrode and the source electrode are connected to the third node. The first conductive type second MOS transistor connected, the drain electrode is connected to the second node, and the gate electrode is connected to the fourth node, and the source electrode is connected to the second power supply voltage terminal. A first conductive type third MOS transistor that is connected and has a drain electrode and a gate electrode connected to the fourth node is provided between the first power supply voltage terminal and the fourth node. , A second conductive type fourth MOS transistor whose gate electrode is connected to the first node, and the fourth MOS transistor between the first power supply voltage terminal and the fourth node. A second conductive type fifth MOS transistor provided in series with the above, and a gate electrode provided between the first power supply voltage terminal and the second power supply voltage terminal, and a gate electrode is the second node. A first conductive type sixth MOS transistor connected to the above, and the sixth MOS transistor are connected in series between the first power supply voltage terminal and the second power supply voltage terminal. The drain electrode and the gate electrode are connected to the gate electrode of the fifth MOS transistor, the second conductive type seventh MOS transistor, the source electrode is connected to the first power supply voltage terminal, and the drain electrode is a signal. The second conductive type eighth MOS transistor connected to the output terminal and the gate electrode connected to the first node, the source electrode connected to the second power supply voltage terminal, and the drain electrode output a signal. The first conductive type ninth MOS transistor connected to the terminal and the gate electrode connected to the second node, and the first power supply voltage terminal and the second power supply voltage terminal. It has a fourth constant current source provided in series with the sixth and seventh MOS transistors.

In the output circuit having the above configuration, the minimum selector circuit is configured by the third to seventh MOS transistors. That is, the smaller monitor current flowing through the fourth and sixth MOS transistors for monitoring according to the drain current of the eighth and ninth MOS transistors for output is supplied to the third MOS transistor connected by the diode. A minimum selector voltage is obtained at the drain electrode of the third MOS transistor or at the fourth node. Then, a negative feedback operation is performed between the first to ninth MOS transistors so that the reference voltage given to the gate electrode of the first MOS transistor is equal to the minimum selector voltage given to the gate electrode of the second MOS transistor. Is performed, and a drain current or an idle current equal to or higher than the set operating point corresponding to the reference voltage flows through the 8th and 9th MOS transistors for output.

However, in the output circuit having the above configuration, when the potential of the signal output terminal or the output voltage is clipped near the potential of the second power supply voltage terminal, the ninth MOS transistor for output has an unsaturated (linear) characteristic. It operates in the region, and the negative feedback operation of the minimum selector circuit causes the control voltage applied from the second node to the gate electrode of this ninth MOS transistor to jump to a considerably high level, which causes the sixth MOS transistor for monitoring to jump. Attempts to pass a large monitor current. However, since the fourth constant current source is connected in series with the sixth MOS transistor, the current flowing through the sixth MOS transistor is limited to the maximum permissible current value set for the fourth constant current source. To.

The output circuit according to the second aspect of the present invention has first and second transistors which are connected in series between the first power supply voltage terminal and the second power supply voltage terminal to form a push-pull circuit. , The first and second control voltages are applied to the control electrodes of the first and second transistors, respectively, and the minimum selector voltage corresponding to the smaller current flowing through the first and second transistors is generated. An output circuit that variably controls the first and second control voltages so that the minimum selector voltage matches the reference voltage, and the first power supply voltage terminal and the first power supply voltage terminal to generate the minimum selector voltage. A third transistor of the diode connection provided on the first current path between the two power supply voltage terminals and the third transistor are provided in series on the first current path. A fourth transistor that receives the first control voltage on the control electrode, a fifth transistor provided in series with the third and fourth transistors on the first current path, and the first A sixth transistor provided on the second current path between the power supply voltage terminal and the second power supply voltage terminal and receiving the second control voltage on the control electrode, and the second current path. A seventh transistor, which is provided above in series with the sixth transistor and whose control and output electrodes are connected to the control terminal of the fifth transistor, and the second current path. It has a constant current source provided in series with the sixth and seventh transistors.

In the output circuit having the above configuration, the minimum selector circuit is configured by the third to seventh transistors. That is, the smaller monitor current flowing through the fourth and sixth transistors for monitoring is supplied to the third transistor connected by the diode according to the current flowing through the first and second transistors for output, and the third transistor is supplied. A minimum selector voltage is obtained at the output electrode of the transistor. Then, a negative feedback operation is performed between the first to seventh transistors so that the minimum selector voltage becomes equal to the reference voltage, and the setting operation corresponding to the reference voltage is performed on the first and second transistors for output. A drain current or idle current above the point flows.

However, the output voltage is clipped near the potential of the second power supply voltage terminal, and the control voltage applied to the gate electrode of the sixth transistor for monitoring with respect to the second transistor for output by the negative feedback operation of the minimum selector circuit is applied. It jumps to a fairly high level, which causes the sixth transistor to carry a large current monitor current over the second current path. However, since the constant current source is provided on the second current path, a current exceeding the maximum allowable current value set in the constant current source does not flow on the second current path.

The operational amplifier of the present invention includes a differential input circuit that differentially inputs a pair of signals, and an output circuit of the present invention that amplifies and outputs a signal extracted from the differential input circuit.

According to the output circuit or operational amplifier of the present invention, the above configuration and operation can easily and effectively suppress the flow of a large amount of unnecessary current inside, complicating integrated circuit design / manufacturing and bias conditions. -It can be adapted to the reduction of power consumption and power supply voltage without setting restrictions.

It is a circuit diagram which shows the basic structure of the output circuit in one Embodiment of this invention. It is a circuit diagram which shows the structure of the operational amplifier in one Embodiment of this invention. It is a circuit diagram which shows the structure of the operational amplifier of the comparative example. It is a figure which shows the condition around the voltage follower which performed the simulation about embodiment and comparative example. It is a waveform diagram which shows the waveform of each part which shows the simulation result of the comparative example. It is a waveform diagram which shows the waveform of each part which shows the simulation result of an embodiment.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[Basic configuration of output circuit in the embodiment]

FIG. 1 shows a basic configuration of an output circuit according to an embodiment of the present invention. The output circuit 10 is configured as a low-voltage operation class AB output circuit composed of a CMOS circuit that can be incorporated into various amplifiers such as an operational amplifier. The class AB output circuit 10 includes an output control circuit 12, a minimum selector circuit 14, and a push-pull circuit 16.

The output control circuit 12 includes three constant current sources I ₁ , I ₂ , I ₃ , two NMOS transistors M ₁ , M _2, and one constant voltage source 18. Specifically, the output control circuit 12 has a constant current source I between the power supply voltage terminal (hereinafter referred to as “positive electrode power supply terminal”) 20 that gives a constant positive power potential _VDD and the nodes N ₁ and N ₂ . _1, provided _{I 2,} respectively, the nodes _N 1, _{N 2} and the node respectively provided NMOS transistors _M 1, _{M 2} of the differential pair between the _{N 3,} the node _{N 3} and the negative polarity constant power supply voltage _{V SS} of A constant current source (tail current source) I ₃ is provided between the power supply voltage terminal (hereinafter referred to as “negative electrode power supply terminal”) 22 that provides

More specifically, one of the NMOS transistor M ₁ of the differential pair, its source electrode connected to the node N _3, the drain electrode connected to the node N _1, the gate electrode provides a constant reference voltage V _AB It is connected to the constant voltage source 18. The source electrode of the other NMOS transistor M ₂ is connected to the node N ₃ , the drain electrode is connected to the node N ₂ , and the gate electrode is connected to the node N ₄ of the minimum selector circuit 14. Signal current input terminal 24 is connected to the node N _3. Signal current CS taken out from the preceding circuit (not shown) is inputted from the signal current input terminal 24 to the node N _3.

The minimum selector circuit 14 includes one diode-connected NMOS transistor M ₃ , one NMOS transistor M ₆ , three MOSFET transistors M ₄ , M ₅ , M _7, and one constant current source I ₄ . I'm out.

For details, minimum selector circuit 14, between the positive power supply terminal 20 and the negative electrode power terminal 22, a PMOS transistor _{M 5} and the PMOS transistor _{M 4} and the NMOS transistor _{M 3} of diode-connected on one current path _{P 1} connected in series, it is connected to the PMOS transistor _{M 7} and the NMOS transistor _{M 6} and the constant current source _{I 4} in series on another current path _{P 2.}

More specifically, the current path _{P 1,} the PMOS transistor _{M 5} has its source electrode connected to the positive power supply terminal 20, the gate electrode of the PMOS transistor _{M 7} to the gate electrode is provided on the current path _{P 2} next Is commonly connected to. The source electrode of the MOSFET transistor M ₄ is connected to the drain electrode of the MOSFET transistor M ₅ , the drain electrode is connected to the node N ₄ , and the gate electrode is connected to the node N ₁ of the output control circuit 12. NMOS transistor M ₃ of the diode connection is connected its source electrode to the negative electrode power terminal 22, a drain electrode and a gate electrode connected to the node N ₄ in terms of being short-circuited.

On the other hand, in the current path P _2, PMOS transistor M ₇ has its source electrode connected to the positive power supply terminal 20, its drain electrode and the gate electrode is connected to the gate electrode of the PMOS transistor M ₅ in terms of being short-circuited There is. As a result, in both MOSFET transistors M ₅ and M ₇ , a current mirror circuit is formed with M ₇ on the reference side and M ₅ on the subordinate side, and the current mirror ratio is set to 1: 1. Further, the source electrode of the NMOS transistor M ₆ is connected to the constant current source I ₄ , the drain electrode is connected to the drain electrode of the NMOS transistor M ₇ , and the gate electrode is connected to the node N ₂ of the output control circuit 12. Has been done.

The constant current source I ₄ is connected between the source electrode of the NMOS transistor M ₆ and the negative electrode power supply terminal 22. The constant current source _{I 4,} the maximum allowable current value _{i MAX} or less of the current value the drain current of the monitor NMOS transistor _{M 6} and the PMOS transistor _{M 7} current mirror on the current path _{P 2} is set to the constant current source _{I 4} If both MOS transistors M ₆ and M ₇ can operate normally in the saturation characteristic region, it is possible to configure an arbitrary constant current circuit.

As an example, the constant current source I ₄ can be composed of one NMOS transistor. In that case, the NMOS transistor of the constant current source I ₄ has its source electrode connected to the negative power supply terminal 22, its drain electrode connected to the source electrode of the NMOS transistor M _6, a constant from the constant voltage circuit to the gate electrode Receives a bias voltage. Maximum allowable current value i _MAX is set to the constant current source I ₄ is dependent on the bias voltage (gate voltage), The lower the bias voltage (the closer to the threshold), lower the maximum allowable current value i _MAX Can be set to a value.

The push-pull circuit 16 in the output stage has a MOSFET transistor M ₈ and an NMOS transistor M ₉ connected in series between the positive electrode power supply terminal 20 and the negative electrode power supply terminal 22. The source electrode of the MOSFET transistor M ₈ is connected to the positive electrode power supply terminal 20, the drain electrode thereof is connected to the signal output terminal 26, and the gate electrode thereof is connected to the node N ₁ of the output control circuit 12. On the other hand, the source electrode of the NMOS transistor M ₉ is connected to the negative electrode power supply terminal 22, the drain electrode is connected to the drain electrode and the signal output terminal 26 of the NMOS transistor M ₈ , and the gate electrode is the node of the output control circuit 12. It is connected to N ₂ .

In this way, the MOSFET M ₄ and the NMOS transistor M _{6 of} the minimum selector circuit 14 are allotted for monitoring to the output MOSFET M ₈ and the NMOS transistor M ₉ forming the push-pull circuit 16. .. That is, the output MOSFET transistor M ₈ and the monitor MOSFET transistor M ₄ are commonly connected to their respective gate electrodes, and receive a common control voltage V ₁ from the node N ₁ of the output control circuit 12. On the other hand, the output NMOS transistor M ₉ and the monitor MOSFET transistor M ₆ are commonly connected to their respective gate electrodes, and receive a common control voltage V ₂ from the node N ₂ of the output control circuit 12.

The class-AB output circuit 10 the current path _{P 1} to the _reference, operates in conditions of _{V DD ≧ 1V gs + 2V ds} . Here, V _DD is the power supply voltage (where V _SS = 0), V _gs is the gate-source voltage (threshold value) of the diode-connected NMOS transistor M ₃ , and V _ds is the NMOS transistors M ₄ and M _5. Source-drain voltage (saturation value).

[Action of output circuit in the embodiment]

In the class AB output circuit 10 having the above configuration, the one having the smaller idle current flowing through the MOSFET transistor M ₈ and the NMOS transistor M ₉ of the push-pull circuit 16 in the idle state in which the amplified signal is not input to the amplifier is the class AB. Each part in the output control circuit 12 and the minimum selector circuit 14 operates so as to correspond to the set operating point of, and in particular, all of the MOS transistors M _{1 to} M ₇ operate in the saturation characteristic region.

Specifically, the monitoring epitaxial transistor M ₄ receives the same control voltage applied to the output epitaxial transistor M ₈ from the node N ₁ of the output control circuit 12 to its gate electrode, and the drain current of the output epitaxial transistor M ₈ is received. A drain current (hereinafter referred to as “first monitor current”) having a current value i ₁ corresponding to the above is attempted to flow on the current path P ₁ .

On the other hand, the monitoring NMOS transistor M ₆ receives the same control voltage applied to the output NMOS transistor M ₉ from the node N ₂ of the output control circuit 12 to its gate electrode, and corresponds to the drain current of the NMOS transistor M _9. A drain current having a current value i ₂ (referred to as a “second monitor current”) is attempted to flow on the current path P ₂ . When the current value i ₂ of the second monitor current to be passed by the monitoring NMOS transistor M ₆ is equal to or less than the maximum allowable current value i _MAX set in the constant current source I ₄ , the current value i ₂ is the _second . 2 Monitor current flows on the current path P ₂ .

At this time, since the constant current source I ₄ has a very low on-resistance (drain-source resistance when configured with an NMOS transistor), other MOS transistors (M ₆ , M ₇ ) on the current path P ₂ ) Does not affect the operation.

The second monitor current flowing on the current path P ₂ is mirrored in the current path P ₁ by the current mirror circuits [M ₅ , M ₇ ]. PMOS transistor _{M 5} is a PMOS transistor _{M 7} and the current value equal _{i 2} on current path _{P 1} attempts to pass the drain current, that the second monitor current.

As a result, on the current path _{P 1,} the second monitor current and a series of first monitor current and the PMOS transistor _{M 5} the PMOS transistor _{M 4} is made to flow at a current value _{i 1} is made to flow at a current value _{i 2} The smaller monitor current flows selectively or predominantly. That is, when i ₁ <i ₂ , the first monitor current flows on the current path P ₁ , and when i ₁ > i ₂ , the second monitor current flows on the current path P ₁ . Then, the current path P ₁ on selectively flows NMOS transistor M ₃ of the diode connected to monitor current at its current - voltage conversion (voltage drop) by generating a minimum selector voltage V _MS to node N _4.

Minimum selector voltage _{V MS} obtained in the node _{N 4} Minimum selector circuit 14 is inputted to one side of the gate electrode of the NMOS transistor _{M 2} of the output control circuit 12. On the other hand, the reference voltage _{V AB} is input to the gate electrode of the NMOS transistor _{M 1} on the opposite side.

In the output control circuit 12, both the NMOS transistors M ₁ and M ₂ of the differential pair have substantially the same transistor characteristics. On the other hand, although the constant current sources I ₁ and I ₂ have substantially the same constant current characteristics, their on-resistances or voltage drops are different. That is, a state in which the current value of the signal current CS input from the signal input terminal 24 is at the magnitude of the reference current value, and the differential pair of both NMOS transistors M ₁ and M ₂ are flowing the same drain current. that assuming an idle state, the output PMOS transistor _{M 8} and the output NMOS transistor _{M 9} receives the node _N 1, respectively obtained control voltages _V 1 to _{N 2, V 2} under the idle state to the gate electrode AB Class setting The on-resistance or voltage drop of the constant current sources I ₁ and I ₂ is set so that the drain current, that is, the idle current, which is equal to or higher than the reference value corresponding to the operating point, flows.

When a drain current equal to that of the disparate pair of NMOS transistors M ₁ and M ₂ is flowing, it is when the minimum selector voltage V _MS is equal to the reference voltage V _AB . When minimum selector voltage _{V MS} becomes lower than the reference voltage _{V AB,} relatively drain current of the NMOS transistor _{M 1} becomes larger than the drain current of the NMOS transistor _{M 2,} control voltages _{V 1} While fall below the reference level , The control voltage V ₂ becomes higher than the reference level. As a result, the drain currents of the output MOSFET transistor M ₈ and the output NMOS transistor M ₉ become larger than the reference current value. Then, the action of the minimum selector circuit 14 (monitoring of the output stage drain current selection with the smaller monitor current, the current - voltage conversion) by changes in the direction of minimum selector voltage V _MS becomes high.

Conversely, when the minimum selector voltage _{V MS} is higher than the reference voltage _{V AB,} the drain current of relatively NMOS transistor _{M 1} becomes smaller than the drain current of the NMOS transistor _{M 2,} control voltages _{V 1} is higher than the reference level On the other hand, the control voltage V ₂ becomes lower than the reference level. As a result, the drain currents of the output MOSFET transistor M ₈ and the output NMOS transistor M ₉ become smaller than the reference current value. Then, by the action of the minimum selector circuit 14, minimum selector voltage V _MS is changed in the direction to decrease.

As described above, when the signal current CS input from the signal input terminal 24 is in the idle state (that is, when the amplified signal is not input to the amplifier), the output control circuit 12 and the minimum selector circuit are as described above. by 14 is negative feedback operation so as to match the minimum selector voltage _{V MS} to the reference voltage _{V AB,} the reference current value corresponding to the set operating point of the class AB output PMOS transistor _{M 8} and the output NMOS transistor _{M 9} The above idle current is flowing.

Then, when the amplified signal is input to the amplifier and the current value of the signal current CS input from the signal current input terminal 24 changes from the reference current value in the idle state, the differential pair's NMOS transistors M ₁ and M ₂ both the drain current changes to the signal current CS and backward, and the node N _1, both the control voltages respectively to N ₂ to obtain V _1, V ₂ changes to both the drain current and the reverse direction (i.e. the signal current CS It changes in the same direction). By controlling the voltage V _1, V ₂ are changed from the respective reference level thus, one larger drain than the idle current of the output PMOS transistor M ₈ or the output NMOS transistor M ₉ depending on the direction of the change A current, that is, an output current (source current or sink current) is passed through the signal output terminal 26 into a load (not shown). The current value of this output current corresponds to the amount of change in the signal current CS (the signal level of the signal to be amplified).

In this class AB output circuit 10, when a DC signal, for example, a pulse signal is amplified and output, when the pulse signal is not input or the logic level of the pulse signal being input is “L”, the signal output terminal The potential or output voltage V _{OUT of} 26 is clipped to the negative power supply potential _VSS (for example, ground potential) side via the output NMOS transistor M ₉ on the sink side.

Here, the output NMOS transistor M ₉ operates in an unsaturated (linear) characteristic region because its drain-source voltage is extremely low (near zero volt). On the other hand, the output MOSFET transistor M ₈ has a sufficiently large source-drain voltage and operates in the saturation characteristic region. In this case, the output control circuit 12 and the minimum selector circuit 14 perform the above-mentioned negative feedback operation so that the required drain current or idle current also flows through the output NMOS transistor M ₉ in the unsaturated state. , The control voltage V ₂ applied to the gate electrode of the output NMOS transistor M ₉ jumps to a considerably high level.

At this time, the monitoring NMOS transistor M ₆ on the current path P ₂ is operating in the saturation characteristic region, and is controlled by inputting the control voltage V ₂ common to the output NMOS transistor M ₉ to the gate electrode. A second monitor current is attempted to flow at a considerably large current value i ₂ corresponding to the voltage level of the voltage V ₂ .

However, a constant current source I ₄ is provided on the current path P ₂ . The monitoring NMOS transistor M ₆ cannot pass the second monitor current at a current value i ₂ that exceeds the maximum allowable current value i _MAX set in the constant current source I ₄ . That is, even if the drain current (second monitor current) is to flow at the current value i ₂ corresponding to the control voltage V ₂ received by the monitoring NMOS transistor M ₆ at the gate electrode, if i ₂ > i _MAX , the second is 2 monitors current flowing on the current path _{P 2} at a current value _{i MAX.} Second monitor current of the current value _{i MAX} is copied to the current path _{P 1} through the current mirror circuit _[M 5, M _7].

Thus, on the current path P ₁ may include a second monitor current conflict that attempts to pass the first monitor current and the PMOS transistor M ₅ is made to flow the PMOS transistor M _4, a relatively smaller monitor current selectively flow, minimum selector voltage V _MS is obtained at the node N ₄ corresponding to the selected monitor current.

As described above, in the class AB output circuit 10 of this embodiment, when the potential of the signal output terminal 26 or the output voltage V _OUT is clipped near the negative electrode power supply potential ( _VSS ), the sink becomes unsaturated. The control voltage V ₂ with respect to the output NMOS transistor M ₉ rises remarkably, and the monitor NMOS transistor M ₆ allocated to the output NMOS transistor M ₉ tries to pass a large current second monitor current. However, the current value of the second monitor current that actually flows is set to the preset upper limit current value (maximum allowable current) by the constant current source I ₄ provided in series on the same current path P ₂ as the monitoring NMOS transistor M _6. It is limited to a current _{value) i MAX.} Thus, it is possible to meaningless large current to no generation of minimum selector voltage V _MS in this class-AB output circuit 10. does not contribute to the bias control of the class AB operation is effectively prevented from flowing constantly.

In the class AB output circuit 10 of this embodiment, replacing the constant current source I ₄ with another current limiting circuit or a current limiting element such as a resistance element is not only difficult to obtain the required current limiting effect, but also. other components, particularly to provide a undesirable influence on the operation of the monitor NMOS transistor M ₆ and the PMOS transistor M ₇ current mirror is provided on the same current path P _2, which is not preferable.

That is, if the resistance element is to have a current limiting function equivalent to that of the constant current source I ₄ , a high resistance of at least several kΩ must be used. However, the source electrode and the positive source terminal 22 of the source electrode and the structure provided between the anode power supply terminal 22 or the current mirror PMOS transistor M _7, the monitoring NMOS transistor M ₆ resistance element of such a high-resistance The configuration provided between them cannot be adopted. This is because those MOS transistors M ₆ and M ₇ do not operate normally due to an abnormal reduction or increase in the source voltage. Further, even if such a high resistance resistance element is provided between the drain electrode of the MOSFET transistor M _{7 and} the drain electrode of the NMOS transistor M ₆ , the source-drain voltage of both MOS transistors M ₇ and M ₆ is provided. Is significantly narrowed and stable operation in the saturation characteristic region becomes difficult.

[Configuration of operational amplifier in the embodiment]

FIG. 2 shows the configuration of the operational amplifier 30 according to the embodiment of the present invention. The operational amplifier 30 has a differential input circuit 32, a constant voltage circuit 34, and a class AB output circuit 10A.

The differential input circuit 32 has a tail current source I ₁₀ and a differential pair of MOSFET transistors MP ₁ and MP ₂ , and shares the NMOS transistors MN ₆ and MN ₇ for a constant current source with the class AB output circuit 10A.

More specifically, the tail current source I ₁₀ is connected to the positive electrode power supply terminal 20. In the MOSFET transistors MP ₁ and MP ₂ , their source electrodes are commonly connected to the tail current source I ₁₀ , and their drain electrodes are connected to the drain electrodes of the NMOS transistors MN ₇ and MN ₆ or the nodes N ₃ and N ₅ , respectively. , The gate electrodes are connected to the pair of signal input terminals 36 and 38, respectively. Voltage signals V _IN1 and V _{IN 2} are input to the signal input terminals 36 and 38, respectively.

Constant voltage circuit 34 includes a first bias voltage generating circuit 40 for generating a constant bias voltage V _L of the negative power potential V _SS closer, generates a constant bias voltage V _H of the positive polarity power supply potential V _DD closer It has a second bias voltage generation circuit 42.

The first bias voltage generation circuit 40 has a constant current source I ₁₁ and an NMOS transistor MN ₉ connected in series between the positive electrode power supply terminal 20 and the negative electrode power supply terminal 22. Here, the constant current source I ₁₁ is provided on the positive electrode power supply terminal 20 side. The source electrode of the NMOS transistor MN ₉ is connected to the negative electrode power supply terminal 22, and the gate electrode and drain electrode thereof are commonly connected (that is, diode-connected) and then connected to the constant current source I ₁₁ . The gate electrode and the drain electrode of the NMOS transistor MN _9, constant first bias voltage _{V L} of the negative power potential _{V SS} closer is obtained. This first bias voltage _VL is applied to the gate electrodes of the NMOS transistors MN ₁ , MN ₂ , and MN ₁₀ of the class AB output circuit 10A.

The second bias voltage generation circuit 42 has a MOSFET transistor MP ₁₀ and a constant current source I ₁₂ connected in series between the positive electrode power supply terminal 20 and the negative electrode power supply terminal 22. Here, the constant current source I ₁₂ is provided on the negative electrode power supply terminal 22 side. The source electrode of the MOSFET transistor MP ₁₀ is connected to the positive electrode power supply terminal 20, and the gate electrode and drain electrode thereof are commonly connected (that is, diode-connected) and then connected to the constant current source I ₁₂ . A constant second bias voltage V _H closer to the positive power supply potential V _DD is obtained at the gate electrode and drain electrode of the MOSFET transistor MP ₁₀ . This second bias voltage _VH is applied to the gate electrodes of the MOSFET transistors MP ₄ , MP ₃ , and MP ₅ in the class AB output circuit 10A.

The class AB output circuit 10A includes an output control circuit 12A, a minimum selector circuit 14A, a push-pull circuit 16A, and a cascode half circuit 44. Of these, the output control circuit 12A, the minimum selector circuit 14A, and the push-pull circuit 16A correspond to the output control circuit 12, the minimum selector circuit 14, and the push-pull circuit 16 in the AB class output circuit 10 of FIG. 1 described above, respectively.

Specifically, in the output control circuit 12A, the tail current source I ₁₃ and the epitaxial transistor MP ₃ correspond to the constant current source I ₁ of FIG. 1, and the tail current source I ₁₃ and the MIMO transistor MP ₅ correspond to the constant current source of FIG. Corresponds to I ₂ . Here, in the epitaxial transistors MP ₃ and MP ₅ , each source electrode is commonly connected to the tail current source I ₁₃ , and each drain electrode is connected to nodes N ₁ and N ₂ , and a constant voltage circuit is connected to each gate electrode. from 34 receiving the second bias voltage V _H, and functions as a constant current source.

The NMOS transistors MN ₂ and MN ₃ correspond to the NMOS transistors M ₁ and M ₂ of the differential pair shown in FIG. Here, the first bias voltage _VL from the constant voltage circuit 34 is input to the gate electrode of the NMOS transistor MN ₂ as the reference voltage _{VA B} for setting the class AB operating point. Further, the gate electrode of the NMOS transistor MN _3, minimum selector voltage _{V MS} is input from the node _{N 4.}

The NMOS transistor MN ₇ corresponds to the constant current source (tail current source) I ₃ in FIG. Here, the source electrode of the NMOS transistor MN ₇ is connected to the negative electrode power supply terminal 22, the drain electrode is connected to the node N ₃ , and the gate electrode is the gate electrode of the NMOS transistor MN ₆ of the cascode semi-circuit 44 described later. It is commonly connected to and functions as a constant current source.

In this embodiment, the drain electrode of the reference side polyclonal transistor MP ₁ of the differential input circuit 32 corresponds to the signal current input terminal 24 of FIG. 1, and the drain current CS _a of the epitaxial transistor MP ₁ is the signal of FIG. Corresponds to the current CS.

In the minimum selector circuit 14A, the diode-connected NMOS transistor MN ₈ , the NMOS transistor MP ₈ and the NMOS transistor MP ₆ provided in series on the current path P ₁ are the diode-connected NMOS transistor M ₃ in FIG. 1, and the monitor. respectively correspond to use PMOS transistors _{M 4} and the PMOS transistor _{M 5} current mirror.

Further, the NMOS transistors MP ₇ , the NMOS transistor MN ₄ and the NMOS transistor MN ₁₀ provided in series on the current path P ₂ are the current mirror MOSFET M ₇ and the monitor NMOS transistor M ₆ in FIG. respectively correspond to the current source I _4. Here, the source electrode of the NMOS transistor MN ₁₀ is connected to the negative electrode power supply terminal 22, the drain electrode is connected to the source electrode of the NMOS transistor MN ₄ , and the first bias voltage from the constant voltage circuit 34 is connected to the gate electrode. It receives _VL and functions as a constant current source.

The MPLS transistor MP ₉ and the NMOS transistor MN ₅ of the push-pull circuit 16A correspond to the MOSFET transistor M ₈ and the NMOS transistor M ₉ of FIG. 1, respectively.

The cascode semi-circuit 44 is combined with the output control circuit 12A (particularly the NMOS transistors MN ₂ and MN ₃ ) to form a fold-back cascode circuit for the differential input circuit 32 (particularly the differential pair of NMOS transistors MP ₁ and MP ₂ ). Is forming.

More specifically, the cascode semi-circuit 44 comprises a constant current source I ₁₄ connected in series between the positive electrode power supply terminal 20 and the negative electrode power supply terminal 22, a MOSFET transistor MP ₄ , an NMOS transistor MN ₁ and an NMOS transistor MN ₆ . Have. Here, the constant current source I ₁₄ is provided on the positive electrode power supply terminal 20 side. PMOS transistor MP ₄ has its source electrode connected to the constant current source _{I 14,} its drain electrode connected to the drain electrode of the NMOS transistor MN _1, the second bias voltage _{V H} from the constant voltage circuit 34 to the gate electrode In response, it functions as a constant current source. The source electrode of the NMOS transistor MN ₁ is connected to the node N ₅ , the drain electrode is connected to the drain electrode of the NMOS transistor MP ₄ , and the gate electrode receives the first bias voltage _VL from the constant voltage circuit 34. .. The source electrode of the NMOS transistor MN ₆ was connected to the negative electrode power supply terminal 22, the drain electrode was connected to the node N _5, and the gate electrode was commonly connected to the gate electrode of the NMOS transistor MN ₇ of the output control circuit 12A. Then, it is connected to the drain electrode of the NMOS transistor MN ₁ and functions as a constant current source.

Between the cascode half circuit 44 and the output control circuit 12A, those facing each other have the same configuration and characteristics. That is, a constant current source I ₁₄ and a constant current source I _{13, a} MOSFET transistor MP ₄ and a MOSFET transistor [MP ₃ , MP ₅ ], an NMOS transistor MN ₁ and an NMOS transistor [MN ₂ , MN ₃ ], an NMOS transistor MN ₆ and an NMOS. The transistor MN ₇ has the same configuration and characteristics as each other.

The node _{N 5} cascode half circuit 44 is opposed to the node _{N 3} of the output control circuit 12A. This node N ₅ is connected to the drain terminal of the NMOS transistor MP ₂ of the differential input circuit 32. The drain current of the NMOS transistor MP ₂ is input to the node N ₅ as a second signal current CS _b .

In the differential input circuit 32 of the operational amplifier 30, drain currents CS _a and CS _b flow through the disparate pair of NMOS transistors MP ₁ and MP ₂ in a balanced manner according to the voltage difference between the input signals V _{IN 1} and V _{IN 2} . That is, when V _IN1 = V _IN2 , CS _a ≈ CS _b , when V _IN1 > V _IN2 , CS _a <CS _b , and when V _IN1 <V _IN2 , CS _a > CS _b. The signal currents CS _a and CS _b are taken out from (MP ₁ , MP ₂ ).

In the class AB output circuit 10A, in the output control circuit 12A, the signal current CS _a from the differential input circuit 32 and the drain currents of the differential pair NMOS transistors MN ₂ and MN ₃ merge at the node N ₃ to form an NMOS transistor. It flows through MN ₇ . Further, in the cascode half circuit 44, the signal current CS _b from the differential input circuit 32 and the drain current of the NMOS transistor MN ₁ merge at the node N ₅ and flow through the NMOS transistor MN ₆ .

Now, when the relationship between the input signals V _IN1 and V _IN2 changes from the state of V _IN1 = V _IN2 to the relationship of V _IN1 > V _IN2 , the signal current CS _a changes in the direction of decreasing, which causes the output control circuit 12A. The drain currents of the differential pairs of NMOS transistors MN ₂ and MN ₃ that merge with the signal current CS _a at node N ₃ change in the direction of increase. On the other hand, the signal current CS _b changes in the direction of increasing, and the drain current of the NMOS transistor MN ₁ merging with the signal current CS _b at the node N ₅ of the cascode half circuit 44 changes in the direction of decreasing. As a result, the drain voltage and gate voltage of the NMOS transistor MN ₁ and thus the gate voltage of the NMOS transistor MN ₇ of the output control circuit 12A change in the direction of increasing, and as a result, the drain currents of the disparate pair of NMOS transistors MN ₂ and MN ₃ change. Changes in the direction of further increase.

In the output control circuit 12A, when the drain currents of the differential pair NMOS transistors MN ₂ and MN ₃ increase, the control voltages V ₁ and V ₂ obtained at the nodes N ₁ and N ₂ change in the direction of decreasing, respectively. In the push-pull circuit 16A of the output stage, the drain current (source current) of the source side epitaxial transistor MP ₉ changes in the direction of increasing.

In this way, the output current increases while the relationship of V _IN1 > V _IN2 is maintained, and for example, when the load is a resistance circuit, the output voltage V _OUT continues to increase. Then, when the relationship of V _IN1 > V _IN2 becomes V _IN1 = V _IN2 , the change of each part stops in the operational amplifier 30 and the state becomes a steady state.

When the relationship between the input signals V _IN1 and V _IN2 changes from the state of V _IN1 = V _IN2 to the relationship of V _IN1 <V _IN2 , a change in the opposite direction to the above occurs in each part of the operational amplifier 30. The output current decreases and the output voltage V _OUT decreases. Then, when the relationship of V _IN1 = V _IN2 is reached, the change of each part stops in the operational amplifier 30 and the steady state is reached.

As described above, the arithmetic amplifier 30 of this embodiment includes a differential input circuit 32 that can obtain a large gain under a low power supply voltage, a folding cascode circuit (44, 12A), and a class AB output circuit 10A. AB class output circuit 10A is capable of (especially current path P ₂₎ by inhibiting simple and effectively from flowing unnecessary large current, limiting the integrated circuit design and manufacture complicated and bias conditions and setting of It is possible to reduce the power consumption and adapt to the reduction of the power supply voltage without any trouble.

[Simulation in Embodiment]

As shown in FIG. 4, the present inventor has set the positive power supply potential _VDD under the voltage follower connection for the arithmetic amplifier 30 (FIG. 2) of this embodiment and the arithmetic amplifier 50 (FIG. 3) of the comparative example. 5 volts, the negative power potential _{V SS} to the ground potential (zero volts), the signal 10kΩ resistor to the output terminal 26 _{R L,} the non-inverting input terminal connected respectively to the pulsed power supply (Fig. 2, the signal input terminal 36 in FIG. 3) Then, a pulse signal _VIN with an amplitude of 3 volts (H level = 3 volts, L level = 0 volts) and a repetition frequency of 50 Hz was given from the pulse power supply, and a simulation was performed to calculate the voltage or current of each part in the arithmetic amplifier. .. Incidentally, the operational amplifier 50 (FIG. 3) of the comparative example corresponds to the configuration obtained by omitting the operational amplifier 30 (FIG. 2) NMOS transistor on the current path _{P 2} from the (constant current source) _{MN 10} embodiment.

5 and 6 show the simulation results of the comparative example and the embodiment, respectively. In the figure, "V _IN " is the voltage waveform of the input pulse signal V _IN , "V _OUT " is the voltage waveform of the output pulse signal V _OUT , and "MP ₉ " is the current waveform of the drain current of the output epitaxial transistor MP _9. “MN ₅ ” indicates the current waveform of the drain current of the output NMOS transistor MN ₅ , and “P ₂ ” indicates the current waveform of the current flowing on the current path P ₂ of the class AB output circuit 10A.

In the arithmetic amplifier 50 of the comparative example, as shown in FIG. 5, the current values of the drain currents of the output MIMO transistor MP ₉ and the output NMOS transistor MN ₅ are normal, and the waveforms are substantially similar to the input pulse signal _VIN. Although the output pulse signal V _{OUT of} is obtained, the current path of the class AB output circuit 10A during the period when the pulse signals V _IN and V _OUT are at the L level (zero volt) (during the period when the output voltage is clipped near the ground potential). current of about 3mA on P ₂ (mA) flows. Pulse signal V _IN is not input, even when the non-inverting input terminal of the operational amplifier is at the ground potential, similar current (approximately 3mA) is on the current path P ₂ continues to flow.

On the other hand, in the arithmetic amplifier 30 of the embodiment, as shown in FIG. 6, the current values of the drain currents of the output MIMO transistor MP ₉ and the output NMOS transistor MN ₅ are normal, and the output pulse signal V _OUT . after the voltage waveforms is normal, the pulse signal V _iN is a current flowing on the current path P ₂ of the class AB output circuit 10A is slightly during the L level (during the period when the output voltage is clipped to near ground potential) 40 .mu.A It is suppressed to the extent of (microampere). Even when the pulse signal V _IN is not input, only the flow again 40μA about current on the current path P _2. As described above, according to the embodiment, the useless current flowing on the current path P _{2 of} the operational amplifier or the class AB output circuit can be reduced to about 1/1000 of the comparative example.

Although the preferred embodiment of the present invention has been described above, the above-described embodiment does not limit the present invention. Those skilled in the art can make various modifications and changes in a specific embodiment without departing from the technical idea and technical scope of the present invention.

In the operational amplifier 30 of the above embodiment, the first bias voltage _VL generated by the first bias voltage generation circuit 40 of the constant voltage circuit 34 is shared by the three constant current source NMOS transistors MN ₁ , MN ₂ , and MN ₁₀ . did. However, it is also possible to provide a unique or dedicated bias voltage generation circuit for the constant current source NMOS transistor MN _{10 of} the minimum selector circuit 14A.

Arrangement of the class AB output circuit 10 for a current mirror is connected in series with the current path _{P 1} of (10A) PMOS transistors _{M 5} and monitor PMOS transistor _{M 4} (connected) in series on the position and / or the current path _{P 2} PMOS transistor _{M 7} current mirror is _connected, the arrangement of the monitoring NMOS transistor _{M 6} and the constant current source _{I 4} (connection) can be modified to replace the position appropriately.

Thus, a current path _{P 1,} the source electrode of the PMOS transistor _{M 5} current mirror is connected to the positive power supply terminal 20, the source electrode of the monitor PMOS transistor _{M 4} is connected to the drain electrode of the PMOS transistor _{M 5,} PMOS transistors The configuration of the above embodiment in which the drain electrode of M ₄ is connected to the node N ₄ is one aspect, and is not limited to this configuration. For example, the source electrode of the monitor PMOS transistor _{M 4} is connected to the positive power supply terminal 20, the source electrode of the PMOS transistor _{M 5} current mirror is connected to the drain electrode of the PMOS transistor _{M 4,} the drain electrode of the PMOS transistor _{M 5} A configuration connected to the node N ₄ is also possible.

Further, a current path _{P 2,} the source electrode of the PMOS transistor _{M 7} current mirror is connected to the positive power supply terminal 20, the drain electrode of the monitor NMOS transistor _{M 6} is connected to the drain electrode of the PMOS transistor _{M 7,} NMOS transistor The configuration of the above embodiment in which the constant current source I ₄ (NMOS transistor MN ₁₀ ) is connected between the source electrode of M ₆ and the negative electrode power supply terminal 22 is also one embodiment, and is not limited to this configuration. For example, the source electrode of the current mirror epitaxial transistor M ₇ is connected to the positive power supply terminal 20, the source electrode of the monitoring NMOS transistor M ₆ is connected to the negative electrode power supply terminal 22, and the drain electrode of the epitaxial transistor M ₇ and the NMOS transistor M are connected. _A constant current source I ₄ may be connected to the drain electrode of ₆ . Alternatively, a constant current source I ₄ is connected between the positive electrode power supply terminal 20 and the source electrode of the current mirror epitaxial transistor M ₇ , the source electrode of the monitoring NMOS transistor M ₆ is connected to the negative electrode power supply terminal 22, and the epitaxial transistor is connected. It is also possible to connect the drain electrode of the NMOS transistor M ₆ to the drain electrode of M ₇ .

Further, a configuration in which a non-folding type cascode circuit is provided or a configuration in which a cascode circuit is not provided is also possible, and a configuration in which a single output signal is taken out from the differential input circuit 32 and directly input to the class AB output circuit 10A is also possible. It is possible.

Further, in the output circuit or the operational amplifier of the above embodiment, it is possible to replace the NMOS transistor of each part with the NMOS transistor and replace the NMOS transistor of each part with the NMOS transistor. Alternatively, all or part of the transistors used can be composed of bipolar transistors. The output circuit of the present invention can be incorporated into various amplifiers other than operational amplifiers.

10,10A Class AB output circuit 12,12A Output control circuit 14,14A Minimum selector circuit 16, 16A Push-pull circuit 20 Positive power supply terminal 22 Negative power supply terminal 24 Signal current input terminal 26 Signal output terminal 30 Arithmetic amplifier 36, 38 Signal input Terminals I ₁ , I ₂ , I ₃ , I ₄ Constant current source M ₁ , M ₂ , M ₆ , M ₉ NMOS transistor M ₃ Diode-connected NMOS transistor M ₄ , M ₅ , M ₇ , M ₈ MOSFET transistor I ₁₀ , I ₁₁ , I ₁₂ , I ₁₃ , I ₁₄ Constant current source MN _{1 to} MN ₇ , MN ₉ NMOS transistor MN ₈ Diode-connected NMOS transistor MN ₁₀ NMOS transistor for constant current source MP _{1 to} MP ₁₀ NMOS transistor N ₁ ~ N ₅ nodes

Claims (6)

A first constant current source provided between the first power supply voltage terminal and the first node,
A second constant current source provided between the first power supply voltage terminal and the second node,
A third constant current source provided between the third node that receives the signal current and the second power supply voltage terminal, and
A first conductive type first MOS transistor in which the source electrode is connected to the third node, the drain electrode is connected to the first node, and the gate electrode receives a reference voltage.
A first conductive type second MOS transistor in which the source electrode is connected to the third node, the drain electrode is connected to the second node, and the gate electrode is connected to the fourth node.
A first conductive type third MOS transistor in which the source electrode is connected to the second power supply voltage terminal and the drain electrode and gate electrode are connected to the fourth node.
A second conductive type fourth MOS transistor provided between the first power supply voltage terminal and the fourth node and having a gate electrode connected to the first node.
A second conductive type fifth MOS transistor provided in series with the fourth MOS transistor between the first power supply voltage terminal and the fourth node, and
A first conductive type sixth MOS transistor provided between the first power supply voltage terminal and the second power supply voltage terminal and having a gate electrode connected to the second node.
The sixth MOS transistor is provided in series between the first power supply voltage terminal and the second power supply voltage terminal, and the drain terminal and the gate electrode are connected to the gate electrode of the fifth MOS transistor. The second conductive type seventh MOS transistor and
A second conductive type eighth MOS transistor in which the source electrode is connected to the first power supply voltage terminal, the drain electrode is connected to the signal output terminal, and the gate electrode is connected to the first node.
A first conductive type ninth MOS transistor in which a source electrode is connected to the second power supply voltage terminal, a drain electrode is connected to the signal output terminal, and a gate electrode is connected to the second node.
An output circuit having a fourth constant current source provided in series with the sixth and seventh MOS transistors between the first power supply voltage terminal and the second power supply voltage terminal. The source electrode of the fifth MOS transistor is connected to the first power supply voltage terminal,
The source electrode of the fourth MOS transistor is connected to the drain electrode of the fifth MOS transistor,
The drain electrode of the fourth MOS transistor is connected to the fourth node,
The source electrode of the seventh MOS transistor is connected to the first power supply voltage terminal,
The drain electrode of the sixth MOS transistor is connected to the drain electrode and the gate electrode of the seventh MOS transistor.
The fourth constant current source is connected between the source electrode of the sixth MOS transistor and the second power supply voltage terminal.
The output circuit according to claim 1. In the fourth constant current source, the source electrode is connected to the second power supply voltage terminal, the drain electrode is connected to the source electrode of the sixth MOS transistor, and the gate electrode receives a constant voltage. The output circuit according to claim 1 or 2, further comprising a tenth MOS transistor of the type. It has first and second transistors which are connected in series between a first power supply voltage terminal and a second power supply voltage terminal to form a push-pull circuit, and control electrodes of the first and second transistors. The first and second control voltages are applied to the first and second control voltages, respectively, and a minimum selector voltage corresponding to the smaller current flowing through the first and second transistors is generated so that the minimum selector voltage matches the reference voltage. An output circuit that variably controls the first and second control voltages.
A diode-connected third transistor provided on the first current path between the first power supply voltage terminal and the second power supply voltage terminal to generate the minimum selector voltage.
A fourth transistor provided on the first current path in series with the third transistor and receiving the first control voltage on its control electrode,
A fifth transistor provided in series with the third and fourth transistors on the first current path, and a fifth transistor.
A sixth transistor provided on the second current path between the first power supply voltage terminal and the second power supply voltage terminal and receiving the second control voltage on the control electrode thereof,
A seventh transistor provided on the second current path in series with the sixth transistor, and its control electrode and output electrode are connected to the control electrode of the fifth transistor.
An output circuit having a constant current source provided in series with the sixth and seventh transistors on the second current path. A differential input circuit that differentially inputs a pair of input signals,
An operational amplifier having the output circuit according to any one of claims 1 to 4, which amplifies and outputs a signal extracted from the differential input circuit. The operational amplifier according to claim 5, wherein the output circuit has a folding cascode circuit for amplifying a signal extracted from the differential input circuit.