JP2020160182A - Display device - Google Patents

Abstract

To provide a display device capable of suppressing a crash in a display output.SOLUTION: The display device includes: a liquid crystal display panel disposed to be capable of transmitting light; a pixel disposed in the liquid crystal display panel and having a pixel electrode and a common electrode to which a potential to control the alignment of a liquid crystal is applied; a switching element having a source and a drain, one of which is connected to the pixel electrode; a signal line connected to the other of the source and the drain; a scanning line to which a potential to open and close between the source and drain is applied; and a control part disposed to be capable of controlling a potential difference between the pixel electrode and the common electrode. The potential of the common electrode is switched between a relatively high potential and a relatively low potential at inversion drive timings at a predetermined interval; just before the inversion drive timing, the pixel electrode and the common electrode have the same potential; and a first potential applied to the scanning line in a period when a signal to control the pixel electrode and the common electrode to be at the same potential is applied to the signal line is higher than a potential in other periods.SELECTED DRAWING: Figure 4

Description

The present invention relates to a display device.

A liquid crystal display device that outputs a display by a so-called Field Sequential Color (FSC) method that controls pixels so that light of a plurality of colors is transmitted from the same pixel at different timings is known (for example, Patent Documents). 1).

Japanese Unexamined Patent Publication No. 2010-097420

Generally, in a liquid crystal display device, an inversion drive is performed in which the direction of the voltage applied to the liquid crystal is reversed at predetermined time intervals. Here, the greater the potential difference between the two electrodes that apply voltage to the liquid crystal, the greater the degree of amplitude of the potential of each of the two electrodes due to inversion. Depending on the relationship between the degree of the amplitude of the potential and the driving potential for opening the gate of the switching element of the pixel, an unintended leakage of the pixel potential may occur at a level at which the display output is disrupted. That is, even at the timing when the drive potential is not applied to the gate of the switching element of the pixel, the potential difference between the two electrodes may decrease to a considerable extent due to the amplitude of the potential of each of the two electrodes due to the inversion drive. ..

The present invention has been made in view of the above problems, and an object of the present invention is to provide a display device capable of suppressing failure of display output.

The display device according to one aspect of the present invention includes a liquid crystal display panel, a pixel provided on the liquid crystal display panel and having a pixel electrode and a common electrode provided with a potential for controlling the orientation of the liquid crystal, and the pixel electrode. A control unit provided so as to control the potential difference of the common electrode, a switching element in which one of the source and drain is connected to the pixel electrode, and a source-drain of the switching element connected to the gate of the switching element. The common electrode comprises a scanning line to which a potential for opening and closing is provided, and a signal line connected to the source or the other of the drain to supply a signal corresponding to the potential given to the pixel electrode. The high potential and the low potential can be switched at the reversal drive timing at predetermined time intervals, the pixel electrode and the common electrode have the same potential immediately before the reversal drive timing, and the pixel electrode and the common electrode have the same potential. The first potential given to the scanning line during the period in which the signal is given to the signal line is higher than the potential in other periods.

FIG. 1 is a schematic circuit diagram showing a main configuration of a display device according to an embodiment. FIG. 2 is a schematic cross-sectional view of the liquid crystal display panel. FIG. 3 is a timing chart showing an example of the flow of FSC control. FIG. 4 is a timing chart showing a control example of the pixel signal potential, the common potential, and the drive potential in the period of the first frame. FIG. 5 is a timing chart showing a control example of the pixel signal potential, the common potential, and the drive potential in the second frame period.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention are naturally included in the scope of the present invention. Further, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example, and the interpretation of the present invention is used. It is not limited. Further, in the present specification and each of the drawings, the same elements as those described above with respect to the above-described drawings may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

FIG. 1 is a schematic circuit diagram showing a main configuration of the display device 100 according to the embodiment. The display device 100 includes a liquid crystal display panel P and a light source device L. The liquid crystal display panel P includes a display unit 7, a signal output circuit 8, a scanning circuit 9, a VCOM drive circuit 10, a timing controller 13, and a power supply circuit 14. Hereinafter, one side of the liquid crystal display panel P facing the display unit 7 is referred to as a display surface, and the other surface is referred to as a back surface.

A plurality of pixels Pix are arranged in a matrix on the display unit 7, and are arranged in the row direction and the column direction. The pixel Pix includes a switching element 1 and two electrodes. In FIG. 1 and FIG. 2 described later, a pixel electrode 2 and a common electrode 6 are shown as two electrodes.

FIG. 2 is a schematic cross-sectional view of the liquid crystal display panel P. The liquid crystal display panel P has two opposing substrates and a liquid crystal 3 enclosed between the two substrates. Hereinafter, one of the two substrates will be referred to as a first substrate 30, and the other will be referred to as a second substrate 20.

The first substrate 30 is a transparent glass substrate 35, a pixel electrode 2 laminated on the second substrate 20 side of the glass substrate 35, and a second substrate 20 laminated on the second substrate 20 side so as to cover the pixel electrode 2. 1 Alignment film 55 is included. The pixel electrode 2 is individually provided for each pixel Pix. The second substrate 20 has a translucent glass substrate 21, a common electrode 6 laminated on the first substrate 30 side of the glass substrate 21, and a second substrate 20 laminated on the first substrate 30 side so as to cover the common electrode 6. Includes a bialignment film 56. The common electrode 6 has a plate-like or film-like shape shared by a plurality of pixels Pix. Although the first substrate 30 is omitted in FIG. 2, each switching element 1 connected to each pixel electrode 2 is formed between the pixel electrode 2 and the glass substrate 35.

The liquid crystal 3 of the first embodiment is a polymer-dispersed liquid crystal. Specifically, the liquid crystal 3 contains a bulk 51 and fine particles 52. The orientation of the fine particles 52 changes in the bulk 51 according to the potential difference between the pixel electrode 2 and the common electrode 6. By individually controlling the potential of the pixel electrode 2 for each pixel Pix, at least one degree of light transmission or dispersion is controlled for each pixel Pix. The liquid crystal display panel P of the embodiment is a so-called normally white liquid crystal display panel in which the degree of light dispersion is maximized when a voltage is not applied to the liquid crystal 3, but the present invention is not limited to this. The liquid crystal display panel P may be a so-called normally black liquid crystal display panel in which the degree of light transmission is maximized when no voltage is applied to the liquid crystal 3. In the first embodiment, the liquid crystal display panel P using the polymer-dispersed liquid crystal 3 is a transmissive liquid crystal display panel, and the transmissive liquid crystal display panel has, for example, the above-mentioned display surface as the first surface 351 of the first substrate 30. When the above-mentioned back surface is the second surface 211 of the second substrate, the background of the back surface can be seen through when viewed from the display surface side, and the background of the display surface can be seen through when viewed from the back surface side. It is a display panel that can be seen. Further, the display surface may be the second surface 211 and the back surface may be the first surface 351. Since the above-mentioned light source device L irradiates light from the back side toward the display surface like a backlight attached to a normal liquid crystal display panel, the background of the back surface cannot be seen through from the display surface. In order to realize the transmissive liquid crystal display panel, the light source device L is a side light arranged on the side surface side perpendicular to the first surface 351 and the second surface 211 of the first substrate 30 and the second substrate 20, and is a side light. A light that irradiates light toward the side surfaces of the first substrate 30 and the second substrate 20 is used.

In the first embodiment described with reference to FIG. 2, the pixel electrode 2 and the common electrode 6 face each other so as to sandwich the liquid crystal 3, but the liquid crystal display panel P has the pixel electrode 2 and the common electrode 6 on one substrate. The orientation of the liquid crystal 3 may be controlled by the electric field generated by the pixel electrode 2 and the common electrode 6. Further, the liquid crystal 3 may be a liquid crystal other than the polymer-dispersed liquid crystal. Further, when not used as the above-mentioned transmissive liquid crystal display panel, the light source device L may be a backlight.

Next, a mechanism for controlling the potentials of the pixel electrode 2 and the common electrode 6 will be described. As shown in FIG. 1, the switching element 1 is a switching element using a semiconductor such as a thin film transistor (TFT). One of the source and drain of the switching element 1 is connected to one of the two electrodes (pixel electrode 2). The other of the source or drain of the switching element 1 is connected to the signal line 4. The gate of the switching element 1 is connected to the scanning line 5. The scanning line 5 provides a potential (driving potential) for opening and closing between the source and drain of the switching element 1 under the control of the scanning circuit 9. The scanning circuit 9 controls the drive potential. Details of the control of the drive potential by the scanning circuit 9 will be described later.

In the example shown in FIG. 1, the plurality of signal lines 4 are arranged along one of the arrangement directions of the pixels Pix (row direction). The signal line 4 extends along the other (column direction) of the arrangement directions of the pixels Pix. The signal line 4 is shared by the switching elements 1 of a plurality of pixels Pix arranged in the column direction. The plurality of scanning lines 5 are arranged along the column direction. The scanning line 5 extends along the row direction. The scanning line 5 is shared by the switching elements 1 of a plurality of pixels Pix arranged in the row direction.

The common electrode 6 is connected to the VCOM drive circuit 10. The VCOM drive circuit 10 applies a reference potential to the common electrode 6. The signal output circuit 8 outputs a pixel signal to the signal line 4 at the timing when the scanning circuit 9 gives the scanning line 5 a potential (first potential) that functions as a drive signal, which is common to the pixel electrode 2. The stored capacity formed between the electrodes 6 and the liquid crystal (fine particles 52) which is a capacitive load are charged. As a result, the voltage of the pixel Pix becomes a voltage corresponding to the pixel signal. After the application of the first potential is completed, the liquid crystal (fine particles 52), which is the storage capacity and the capacitive load, holds the pixel signal. The orientation of the liquid crystal (fine particles 52) is controlled according to the electric field generated by the voltage of each pixel Pix and the voltage of the common electrode 6.

A light source device L having a light source 11 is arranged on the side surface side or the back surface side of the display device 100. The light source 11 includes a first light source 11R that emits red light, a second light source 11G that emits green light, and a third light source 11B that emits blue light. The first light source 11R, the second light source 11G, and the third light source 11B each emit light under the control of the light source drive circuit 12. The first light source 11R, the second light source 11G, and the third light source 11B of the first embodiment are light sources using a light emitting element such as a light emitting diode (LED), but are not limited thereto. Any light source may be used as long as the light emission timing can be controlled. The light source drive circuit 12 controls the light emission timings of the first light source 11R, the second light source 11G, and the third light source 11B under the control of the timing controller 13.

The timing controller 13 controls the operation timing of the signal output circuit 8, the scanning circuit 9, the VCOM drive circuit 10, and the light source drive circuit 12. In the first embodiment, FSC-type operation control is performed.

FIG. 3 is a timing chart showing an example of the flow of FSC-type operation control performed in the embodiment. FIG. 3 illustrates a schematic timing chart for a two-frame period. The timing chart of FIG. 3 includes information indicating frame signal output, field signal output, drive signal switching, common potential switching, and lighting timings of the first light source 11R, the second light source 11G, and the third light source 11B. The switching of the drive signal indicates the switching of the potential of the scanning line 5. The switching of the common potential indicates the switching of the potential of the common electrode 6.

The frame signal is a signal indicating the start timing of each frame period. In FIG. 3, a frame signal is output at the start of the period FL1 of the first frame, at the start of the period FL2 of the second frame, and at the start of the period of the next frame (third frame) following the end of the second frame. It shows that it will be done. The time (frame time) in which one frame image is displayed, such as the period FL1 of the first frame and FL2 of the second frame, is a predetermined time. That is, the frame image is updated at predetermined time intervals. From the third frame onward, a period in which control is performed by the same mechanism as the period FL1 in the first frame and a period in which control is performed by the same mechanism as the period FL2 in the second frame alternately occur.

The field signal is a signal indicating the start timing of the field period included in each frame period. The one-frame period includes a number of field periods corresponding to the number of colors of light emitted by the light source 11. In FIG. 3, the first frame period FL1, the first field period FI11, the second field period FI12, the third field period FI13 and the fourth field period FI14, the second frame period FL2, the first field period FI21, the second Includes field period FI22, third field period FI23 and fourth field period FI24. By repeating the period of the two frames, the display control of continuous frame images is performed.

Each field period includes a pixel signal writing period and a pixel signal holding period due to the storage capacity. The writing (R +) in FIG. 3 is the writing period of the first field period FI11. Retention (R +) is the retention period of the first field period FI11. The writing (G +) is the writing period of the second field period FI12. Retention (G +) is the retention period of the second field period FI12. The writing (B +) is the writing period of the third field period FI13. Retention (B +) is the retention period of the third field period FI13. Writing (K +) is the writing period of the fourth field period FI14. Retention (K +) is the retention period of the 4th field period FI14. Writing (R−) is the writing period of the first field period FI21. Retention (R-) is the retention period of the first field period FI21. Writing (G−) is the writing period of the second field period FI22. Retention (G-) is the retention period of the second field period FI22. Writing (B−) is the writing period of the third field period FI23. Retention (B-) is the retention period of the third field period FI23. Writing (K−) is the writing period of the fourth field period FI24. Retention (K-) is the retention period of the fourth field period FI24.

Of the plurality of field periods in the period of one frame, the writing period included in the field periods excluding the fourth field periods FI14 and 24 is a period in which pixel signals corresponding to the gradation values of different colors are written. For example, it is assumed that (R, G, B) = (r1, g1, b1) when the pixel signal of the first frame is represented by the RGB gradation value. In this case, the pixel signal corresponding to the gradation value of "r1" is written in the writing period of the first field period FI11. Further, the pixel signal corresponding to the gradation value of "g1" is written in the writing period of the second field period FI12. Further, the pixel signal corresponding to the gradation value of "b1" is written in the writing period of the third field period FI13. The retention period included in the plurality of field periods in the period of one frame is a period in which pixel signals corresponding to gradation values of different colors are retained.

The light sources of a plurality of colors included in the light source 11 (for example, the first light source 11R, the second light source 11G, and the third light source 11B) are controlled to be lit within the retention period of the corresponding field period. For example, the first light source 11R is a red light source, the second light source 11G is a green light source, and the third light source 11B is a blue light source. In the period FL1 of the first frame, the first light source 11R lights up during the holding period of the first field period F11. As a result, red scattered light corresponding to the voltage corresponding to the red (R) gradation value (r1) written in the writing period of the first field period F11 is emitted. Further, in the period FL1 of the first frame, the second light source 11G lights up in the second field period F12. As a result, green scattered light corresponding to the voltage corresponding to the gradation value (g1) of green (G) written in the writing period of the second field period F12 is emitted. Further, in the period FL1 of the first frame, the third light source 11B lights up in the third field period F13. As a result, blue scattered light corresponding to the voltage corresponding to the gradation value (b1) of blue (B) written in the writing period of the third field period F13 is emitted. In this way, by including the writing and holding of the pixel signals of R, G, and B and the illumination by the light from the light source of the corresponding color within one frame period, the RGB image data can be obtained within one frame period. Corresponding color reproduction is performed. Color reproduction is performed by the same mechanism for the period FL2 and after in the second frame.

The frequency in the field period is the frequency in the frame period multiplied by the number of colors of the light emitted by the light source 11 + 1. In the first embodiment, the frequency of the frame period is, for example, 60 Hz, but the frequency is not limited to this, and may be 120 Hz or another frequency. When the frequency of the frame period is 60 Hz, the frequency of the field period of the first embodiment is 240 Hz, but the frequency of the field period is appropriately changed according to the frequency of the frame period and the number of colors of the light emitted by the light source 11. It is possible.

Further, in FIG. 3, the writing period and the holding period are shown as apparently the same period, but the writing period and the holding period do not have to be the same period. For example, the retention period may be longer than the writing period or may be shorter.

In the liquid crystal display panel P using the liquid crystal, the inversion drive for switching between the relative high potential and the relative low potential of the common electrode 6 is performed at the inversion drive timing at predetermined time intervals. In FIG. 3, VCOM drive is performed so that the common potential is zero (0) or negative (-) potential during the first frame period FL1 and the common potential is positive (+) potential during the second frame period FL2. The circuit 10 controls the potential of the common electrode 6. Correspondingly, the pixel signal is written so that the potential of the pixel electrode 2 becomes a relative high potential (+) corresponding to the common potential of zero (0) or minus (-) in the period FL1 of the first frame. A pixel signal is written in the second frame period FL2 so that the potential of the pixel electrode 2 becomes a relative low potential (−) corresponding to a positive (+) common potential. The reference numerals in parentheses in the description of the drive signal shown in FIG. 3 indicate the combination of the color and potential of the RGB gradation value corresponding to the pixel signal to be written.

FIG. 3 shows an example in which the common potential is inverted so as to switch between plus (+) and minus (-), but as shown in FIGS. 4 and 5 described later, the minus (-) common potential is It can be replaced with zero (0).

In the first embodiment, in the pixel Pix, the potential control of the pixel electrode 2 is performed in order to correspond to the inversion drive. Specifically, the signal output circuit 8 outputs a pixel signal for inverting drive to the signal line 4. That is, the signal output circuit 8 outputs a pixel signal so that the voltage between the pixel electrode 2 and the common electrode 6 has the same amplitude and different polarities according to the timing when the common electrode 6 is inverted driven. Further, the VCOM drive circuit 10 switches the potential of the common electrode 6 for inverting drive. Then, the timing controller 13 synchronizes the potential switching timing of the pixel electrode 2 by the inverting drive circuit with the potential switching timing of the common electrode 6 by the VCOM drive circuit 10 in the frame period cycle. These function as the reversing drive unit of the first embodiment. The relative high potential (+) of the pixel electrode 2 is not limited to the positive potential, but is controlled to be equal to or higher than the negative (−) common potential. Further, the relative low potential (−) of the pixel electrode 2 is not limited to the negative potential, and is controlled to be equal to or less than the common potential of the plus (+).

The image signal (RGB data) that is the source of the pixel signal is input to the liquid crystal display panel P via, for example, an input circuit 15 included in an external image output device. The input circuit 15 outputs a signal indicating the gradation value of each of the red (R), green (G), and blue (B) colors of each pixel Pix to the signal output circuit 8 based on the image signal. Further, the input circuit 15 outputs a synchronization signal and other control signals synchronized with the signal input timing for the signal output circuit 8 to the timing controller 13. The timing controller 13 controls the operations of the signal output circuit 8, the scanning circuit 9, the VCOM drive circuit 10, and the like based on the signal input from the input circuit 15. The input circuit 15 may be provided on the liquid crystal display panel P. Further, the input circuit 15 may be provided as a function of a DDIC (Display Driver Integrated Circuit) designed to integrate other circuits such as a timing controller 13.

FIG. 4 is a timing chart showing a control example of the pixel signal potential SV1, the common potential CV1 and the drive potential GV1 in the period FL1 of the first frame. The pixel signal potential SV1 and the pixel signal potential SV2 (see FIG. 5) are potentials given to the pixel electrode 2 from the signal line 4 via the switching element 1 under the control of the signal output circuit 8. The common potential CV1 and the common potential CV2 (see FIG. 5) are potentials given to the pixel electrode 2 under the control of the VCOM drive circuit 10. The drive potential GV1 and the drive potential GV2 (see FIG. 5) are potentials given to the scanning line 5 under the control of the scanning circuit 9.

As shown in FIG. 4, the drive potential GV1 becomes the second potential V2 during the writing period included in each of the first field period FI11, the second field period FI12, and the third field period FI13. The second potential V2 is a potential that opens between the source and drain of the switching element 1. A pixel signal is given to the pixel Pix according to the timing when the drive potential GV1 becomes the second potential V2.

Specifically, for example, with respect to the common potential CV1 of 0 [V], a voltage of 0 [V] or more is applied to the signal line 4 during the writing period (writing (R +)) included in the first field period FI11. As a result, the pixel signal potential SV1 is controlled so as to generate the potential difference Ra. The potential difference Ra is the potential difference between the pixel electrode 2 and the common electrode 6 for controlling the light transmittance of the light from the first light source 11R that lights up during the holding period (holding (R +)) included in the first field period FI 11. Correspond. That is, the pixel signal given in the writing period (writing (R +)) included in the first field period FI 11 is a signal that causes a potential difference Ra.

Similarly, the pixel signal potential SV1 is controlled so as to generate a potential difference Ga in the writing period (writing (G +)) included in the second field period FI12 with respect to the common potential CV1 of 0 [V]. Further, the pixel signal potential SV1 is controlled so as to generate a potential difference Ba in the writing period (writing (B +)) included in the third field period FI13 with respect to the common potential CV1 of 0 [V].

Further, the drive potential GV1 becomes the fourth potential V4 during the holding period included in each of the first field period FI11, the second field period FI12, and the third field period FI13. The fourth potential V4 is a potential that closes the source and drain of the switching element 1. The first light source 11R, the second light source 11G, and the third light source 11B are turned on according to the timing when the drive potential GV1 becomes the fourth potential V4. As described above, the period in which the light source 11 that illuminates the liquid crystal display panel P is turned on is the potential holding period of the pixel electrode 2 set after the opening period in which the source and drain are opened at the second potential V2. Here, the opening period is a writing period included in each field period. The potential retention period is a retention period included in each field period.

Further, as shown in FIG. 4, the drive potential GV1 becomes the first potential V1 during the write period (write (K +)) included in the fourth field period FI14. The pixel signal potential SV1 is controlled so that the pixel electrode 2 and the common electrode 6 have the same potential according to the timing when the drive potential GV1 becomes the first potential V1. Specifically, the pixels so that the writing period (writing (K +)) included in the fourth field period FI14 has the same potential as the common potential CV1 (for example, 0 [V]) of the period FL1 of the first frame. The signal potential SV1 is controlled. As a result, the light transmittance of the pixel Pix included in the liquid crystal display panel P which is normally white as in the embodiment becomes high, and it becomes extremely difficult for the user to recognize the reflected light from the pixel Pix. Therefore, for example, when there is no light from the side surface side or the back surface side of the liquid crystal display panel P, the pixel Pix is in a state of performing black display in the holding period (holding (K +)) included in the fourth field period FI14. During the holding period (holding (K +)) included in the fourth field period FI 14, the light source 11 is turned off without being turned on.

In this way, the pixel signal potential SV1 is controlled so that the pixel electrode 2 and the common electrode 6 have the same potential before the inversion drive timing T1. Therefore, when the potential of the common potential CV1 changes at the inversion drive timing T1 and the pixel signal potential SV1 changes accordingly, it becomes difficult to maintain the potential difference between the pixel electrode 2 and the common electrode 6, and the display output collapses. Can be suppressed. That is, it is possible to control the potential before and after the inversion drive without performing difficult control of switching the two potentials at the same time while maintaining the potential difference between the two potentials having different potentials.

Further, the scanning line is included in the writing period (writing (K +)) included in the fourth field period FI14, which is the period in which the pixel signal E1 for making the pixel electrode 2 and the common electrode 6 have the same potential is given to the signal line 4. The first potential V1 given to 5 is a potential of another period (for example, a second potential V2 of a writing period included in each of the first field period FI11, the second field period FI12, and the third field period FI13). Higher potential. As a result, the response speed of the switching element 1 in the writing period (writing (K +)) included in the fourth field period FI 14 becomes faster. Therefore, after the holding period (holding (B +)) included in the third field period FI 13, the pixel electrode 2 and the common electrode 6 of the pixel Pix are likely to have the same potential faster. Therefore, it becomes easier to shorten the potential control period (for example, the fourth field period FI14) for suppressing the failure of the display output.

In the example shown in FIG. 4, during the holding period (holding (K +)) included in the fourth field period FI14, the driving potential GV1 first becomes the third potential V3 and then becomes the fourth potential V4. Here, the third potential V3 is a potential that closes the source and drain of the switching element 1 and is higher than the fourth potential V4. This sets the drive potential GV1 set to the first potential V1 during the write period (write (K +)) included in the fourth field period FI14 for the purpose of further increasing the response speed of the switching element 1 of the pixel Pix. This is because it is easier and more reliable to drop from the first potential V1 to the third potential V3 than to drop from the potential V1 to the fourth potential V4 in terms of potential control. By setting the third potential V3, the source and drain of the switching element 1 are closed in a hurry, and then by setting the fourth potential V4, the first field period of the second frame performed after the inversion drive timing T1 is performed. Switching between the source and drain of the switching element 1 by switching the second potential V2-fourth potential V4 (see FIG. 5) in the FI 21, the second field period FI22, and the third field period FI23 enables easy and reliable transition. ..

The first potential V1, the second potential V2, the third potential V3, and the fourth potential V4 are generated by, for example, the power supply circuit 14 (see FIG. 1). The power supply circuit 14 receives power W from the outside and supplies potentials corresponding to each of the first potential V1, the second potential V2, the third potential V3, and the fourth potential V4 to the scanning circuit 9. Although not shown, the power supply circuit 14 may generate a potential suitable for the operation of each configuration included in the display device 100 to supply power to each configuration. Further, the scanning circuit 9 may have a function of receiving a power supply from the outside to generate a first potential V1, a second potential V2, a third potential V3, and a fourth potential V4.

The first potential V1 is, for example, 55 [V]. The second potential V2 is, for example, 45 [V]. The third potential V3 is, for example, 0 [V]. The fourth potential V4 is, for example, −10 [V]. Each of these illustrated potentials is merely an example and is not limited to this. We have seen V1> V2> V3> V4, and the source of the switching element 1 according to the first potential V1 and the second potential V2. The space between the drains may be opened, and the space between the source and the drain of the switching element 1 may be closed according to the third potential V3 and the fourth potential V4.

The VCOM drive circuit 10 outputs a VCOM drive signal 301 so as to switch the potential of the common electrode 6 according to the inverting drive timing T1 and the inverting drive timing T2. In the examples shown in FIGS. 3 and 4, the potential of the common electrode 6 is switched from minus (−) to plus (+) at the inversion drive timing T1. Further, the potential of the common electrode 6 is switched from positive (+) to negative (−) at the reversal drive timing T2.

In FIG. 4, the pixel signal is for the purpose of making it easy to distinguish the potential (pixel signal potential SV1) of the pixel signal E1 and the common potential CV1 in the writing period (writing (K +)) included in the fourth field period FI14. Although the potential SV1 and the common potential CV1 are described together, they are actually the same potential or almost the same potential. The same applies to the relationship between the potential of the pixel signal E2 (pixel signal potential SV2) and the common potential CV2 shown in FIG. 5, which will be described later.

FIG. 5 is a timing chart showing a control example of the pixel signal potential SV2, the common potential CV2, and the drive potential GV2 in the period FL2 of the second frame. As shown in FIG. 5, the drive potential GV2 becomes the second potential V2 during the writing period included in each of the first field period FI21, the second field period FI22, and the third field period FI23. A pixel signal is given to the pixel Pix according to the timing when the drive potential GV1 becomes the second potential V2. Further, the drive potential GV2 becomes the fourth potential V4 during the holding period included in each of the first field period FI21, the second field period FI22, and the third field period FI23. The first light source 11R, the second light source 11G, and the third light source 11B are turned on according to the timing when the drive potential GV2 becomes the fourth potential V4.

Specifically, for example, with respect to the common potential CV2 having a potential higher than the third potential V3 and lower than the second potential V2, the common potential is included in the writing period (writing (R-)) included in the first field period FI21. The pixel signal potential SV2 is controlled so as to generate a potential difference Rb by applying a potential of CV2 or less to the signal line 4. Similarly, for the common potential CV2, a potential difference Gb is generated in the writing period (writing (G−)) included in the second field period FI22, and the writing period (writing) included in the third field period FI23 is generated. The pixel signal potential SV2 is controlled so as to cause a potential difference Bb in (B−)).

Further, as shown in FIG. 5, the driving potential GV2 becomes the first potential V1 during the writing period (writing (K−)) included in the fourth field period FI24. The pixel signal potential SV2 is controlled so that the pixel electrode 2 and the common electrode 6 have the same potential according to the timing when the drive potential GV1 becomes the first potential V1. Specifically, the pixel signal potential SV2 is controlled so as to have the same potential as the common potential CV2 of the period FL1 of the first frame during the writing period (writing (K-)) included in the fourth field period FI24. .. As a result, the pixel Pix is in a state of displaying black. In this way, the pixel signal potential SV2 is controlled so that the pixel electrode 2 and the common electrode 6 have the same potential before the inversion drive timing T2. Therefore, when the potential of the common potential CV2 changes at the inversion drive timing T2 and the pixel signal potential SV2 changes accordingly, it becomes difficult to maintain the potential difference between the pixel electrode 2 and the common electrode 6, and the display output collapses. Can be suppressed. That is, it is possible to control the potential before and after the inversion drive without performing difficult control of switching the two potentials at the same time while maintaining the potential difference between the two potentials having different potentials.

Further, scanning is performed during the writing period (writing (K−)) included in the fourth field period FI24, which is the period in which the pixel signal E2 for making the pixel electrode 2 and the common electrode 6 have the same potential is given to the signal line 4. The first potential V1 given to the line 5 is the second potential V2 of the writing period included in each of the potentials of other periods (for example, the first field period FI21, the second field period FI22, and the third field period FI23). ) Higher potential. As a result, the response speed of the switching element 1 in the writing period (writing (K−)) included in the fourth field period FI24 becomes faster. Therefore, after the holding period (holding (B−)) included in the third field period FI23, the pixel electrode 2 of the pixel Pix and the common electrode 6 are likely to have the same potential faster. Therefore, it becomes easier to shorten the potential control period (for example, the fourth field period FI24) for suppressing the failure of the display output.

Similar to the retention period (retention (K +)) included in the fourth field period FI14, the light source 11 is turned off during the retention period (retention (K−)) included in the fourth field period FI24. In the example shown in FIG. 5, the drive potential GV2 becomes the third potential V3 during the retention period (retention (K−)) included in the fourth field period FI24. The drive potential GV2 becomes the fourth potential V4 at the inversion drive timing T2. In this way, the timing of switching from the third potential V3 to the fourth potential V4 may be the same as the inversion drive timing. In particular, in the case of the fourth field period FI24, even if the drive potential GV2 is the third potential V3 during the retention period (holding (K-)), the common potential CV2 and the pixel signal potential SV and the drive potential GV2 before the inversion drive are used. A sufficient potential difference can be secured.

In the embodiment, the timing at which the pixel signal is given to the plurality of pixel Pix sharing the scanning line 5, that is, the driving timing of the switching element 1 by the driving signal from the scanning circuit 9 is common. In other words, the drive timing of the switching element 1 by the drive signal from the scanning circuit 9 does not share the scanning line 5, and can be individually set for each pixel Pix provided at a different position in the column direction. In the embodiment, the scanning circuit 9 gives a drive signal to each of the scanning lines 5 at different timings, but the present invention is not limited to this, and a driving signal may be given to a predetermined number of scanning lines 5 at the same time.

On the other hand, in the embodiment, the timing at which the potentials of the pixel electrode 2 and the common electrode 6 are switched by the inversion drive is the same regardless of the position of the pixel Pix. Further, in the embodiment, the change of the potential of the drive potential GV1 in the fourth field period FI14 and the change of the potential of the drive potential GV2 in the fourth field period FI24 are performed at the same timing in all the scanning lines 5.

As described above, according to the embodiment, the two electrodes (pixel electrode 2 and common electrode 6) have the same potential immediately before the inversion drive timing T1 and the inversion drive timing T2. Therefore, it is possible to suppress the occurrence of failure of the display output due to the difficulty in maintaining the potential difference between the pixel electrode 2 and the common electrode 6 due to the inversion drive.

Further, the first potential V1 given to the scanning line 5 during the period when the signals (pixel signals E1 and E2) for making the pixel electrode 2 and the common electrode 6 have the same potential is the potential of another period. (For example, the potential is higher than the second potential V2, the third potential V3, and the fourth potential V4). Therefore, it becomes easier to shorten the potential control period (for example, the fourth field period FI14 and the fourth field period FI24) for suppressing the failure of the display output.

Further, in the embodiment, the first potential V1 is given to all the scanning lines 5 at the same timing. Therefore, it becomes easier to shorten the potential control period (for example, the fourth field period FI14 and the fourth field period FI24) for suppressing the failure of the display output.

Further, the scanning circuit 9 includes a scanning circuit 9 that gives the scanning line 5 a first potential V1, a second potential V2, a third potential V3, or a fourth potential V4. The second potential V2 is a potential that opens between the source and drain of the switching element 1. The third potential V3 is a potential that closes the source and drain of the switching element 1. The fourth potential V4 is a potential that closes the source and drain of the switching element 1 and is lower than the third potential V3. The source and drain of the switching element 1 are opened and closed a plurality of times within a predetermined time (frame time). The third potential V3 is given to the scanning line 5 after the first potential V1 is given within a predetermined time (frame time). The second potential V2 and the fourth potential V4 are given to the scanning line 5 within a predetermined time (frame time) before the first potential V1 is given. As a result, the display output content can be controlled at a potential lower than the first potential V1.

Further, in the example shown in FIG. 4, the scanning circuit 9 applies the fourth potential V4 to the scanning line 5 after applying the third potential V3 to the scanning line 5 and before the inverting drive timing (for example, the inverting drive timing T1). .. By passing through the third potential V3 before shifting to the fourth potential V4, the potential control becomes easier and more reliable. The scanning circuit 9 does not have to apply the fourth potential V4 to the scanning line 5 after applying the third potential V3 to the scanning line 5 and before the inversion drive timing. As described with reference to FIG. 5, the reverse drive timing may be performed at the same time.

Further, the period during which the light source device L that illuminates the liquid crystal display panel P is lit is set after the opening period (writing period) in which the source and drain of the switching element 1 are opened at the second potential V2 of the two electrodes. One potential retention period (retention period). As a result, the period in which the potential of the pixel Pix is maintained and the display output content is stable can be made to correspond to the period in which the liquid crystal display panel P is illuminated.

Further, the light source 11 includes light sources of a plurality of colors (for example, the first light source 11R, the second light source 11G, and the third light source 11B), and the number of times that the opening period and the potential holding period occur within a predetermined time (frame time) is determined. Corresponds to the number of colors of the light source. Specifically, the number of times that the opening period and the potential holding period occur within a predetermined time (frame time) (excluding the black display) is the same as the number of colors of the light source. The number of times that the opening period and the potential holding period occur within a predetermined time (frame time) is the number obtained by adding 1 to the number of colors of the light source. The opening period and the potential holding period within the predetermined time are the first period (first field period FI11, first field period FI21) corresponding to the first light source 11R and the second period corresponding to the second light source 11G (first field period FI11, first field period FI21). The second field period FI12, the second field period FI22) and the third period corresponding to the third light source 11B (third field period FI13, third field period FI23) are included. Therefore, it is possible to output each pixel Pix corresponding to the RGB gradation value.

The combination of light sources of a plurality of colors included in the light source 11 is not limited to the combination of red (R), green (G), and blue (B). For example, the light source 11 may have a light source corresponding to each of the three colors in combination with cyan, magenta, and yellow.

Further, the specific numerical values including the first potential V1, the second potential V2, the third potential V3, the fourth potential V4, and other potentials exemplified above are merely examples and are not limited to these, and are positive and negative and positive and negative. It can be changed as appropriate as long as the relative relationship between the two opposing values is maintained.

Further, in the example shown in FIG. 3, the potential of the pixel electrode 2 becomes relatively higher than that of the common electrode 6 during the period FL1 of the first frame, and the potential of the pixel electrode 2 becomes higher than that of the common electrode 6 during the period FL2 of the second frame. Inversion drive is performed in units of frame periods so that the value is relatively low with respect to the above, but this is just a specific control example of the inversion drive method and is not limited to this. For example, the relative heights of the potentials of the pixel electrode 2 and the common electrode 6 may be inverted in units of a plurality of frame periods.

Further, in the description of the embodiment, the first potential V1 is given to all the scanning lines 5 at the same time, but the timing at which the first potential V1 is given is controlled by the same method as the second potential V2. May be good. That is, the first potential V1 may be given to each scanning line 5 at different timings. Further, it may be controlled to switch the timing of applying the first potential V1 in 5 units of a predetermined number of scanning lines.

In addition, other actions and effects brought about by the aspects described in the present embodiment are clearly understood from the description of the present specification, or those which can be appropriately conceived by those skilled in the art are naturally understood to be brought about by the present invention. ..

1 Switching element 2 Pixel electrode 3 Liquid crystal 4 Signal line 5 Scan line 6 Common electrode 7 Display unit 8 Signal output circuit 9 Scan circuit 10 VCOM drive circuit 11 Light source 11R 1st light source 11G 2nd light source 11B 3rd light source 12 Light source drive circuit 13 Timing controller 14 Power supply circuit 100 Display device P Liquid crystal display panel L, LA Light source device

Claims (8)

Liquid crystal display panel and
A pixel provided on the liquid crystal display panel and having a pixel electrode and a common electrode provided with a potential for controlling the orientation of the liquid crystal, and
A control unit provided so as to be able to control the potential difference between the pixel electrode and the common electrode,
A switching element in which one of the source and drain is connected to the pixel electrode,
A scanning line that is connected to the gate of the switching element and is provided with a potential for opening and closing between the source and drain of the switching element.
A signal line connected to the source or the other of the drain and supplied with a signal corresponding to a potential given to the pixel electrode.
The common electrode can be switched between high potential and low potential at the reversal drive timing at predetermined time intervals.
Immediately before the inversion drive timing, the pixel electrode and the common electrode have the same potential.
The first potential given to the scanning line during the period when the signal for making the pixel electrode and the common electrode have the same potential is a potential higher than the potential of the other period. .. With the plurality of the pixels
With a plurality of the scanning lines
The display device according to claim 1, wherein the first potential is given to all the scanning lines at the same timing. With the plurality of the pixels
A plurality of the scanning lines arranged in the arrangement direction of the plurality of pixels are provided.
The display device according to claim 1, wherein the first potential is given at different timings for each scanning line. A scanning circuit for applying the first potential, the second potential, the third potential, or the fourth potential to the scanning line is provided.
The second potential is a potential that opens between the source and the drain.
The third potential is a potential that closes between the source and the drain.
The fourth potential is a potential that closes between the source and the drain and is lower than the third potential.
The source and drain are opened and closed a plurality of times within the predetermined time.
The third potential is applied to the scanning line after the first potential is applied within the predetermined time.
The display device according to any one of claims 1 to 3, wherein the second potential and the fourth potential are given to the scanning line before the first potential is given within the predetermined time. The display device according to claim 4, wherein the scanning circuit applies the fourth potential to the scanning line after applying the third potential to the scanning line and before the reversal drive timing. The period in which the light source that illuminates the liquid crystal display panel is turned on is the potential holding period of the pixel electrode, which is set after the opening period in which the source and drain are opened at the second potential, according to claim 4 or 5. Display device. The light source includes light sources of multiple colors.
The display device according to claim 6, wherein the number of times the opening period and the potential holding period occur within the predetermined time corresponds to the number of colors of the light source. The multi-colored light source includes a red light source, a green light source, and a blue light source.
The opening period and the potential holding period within the predetermined time include a first period corresponding to the red light source, a second period corresponding to the green light source, and a third period corresponding to the blue light source. 7. The display device according to claim 7.

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