JP2020153940A - Optical sensor and electronic apparatus equipped with the same - Google Patents

Abstract

To provide an optical sensor with which it is possible for a photodiode to suitably receive light from an optical window even when the optical window is arranged near the outer edge of an electronic apparatus, and an electronic apparatus equipped with the optical sensor.SOLUTION: An optical sensor includes a chip 3 having a plurality of photodiodes 10A. The plurality of photodiodes 10A are lopsidedly arranged on one side of the chip 3 in a first direction X rather than at center, as seen from the light receiving direction of the photodiodes, and are arrayed in elongated form composed of the direction X as a lateral direction and a second direction Y orthogonal to the first direction X as a longitudinal direction.SELECTED DRAWING: Figure 8

Description

The present disclosure relates to an optical sensor and an electronic device including the optical sensor.

Patent Document 1 discloses, for example, a photodetector mounted on a smartphone. The photodetector is mounted so that when the smartphone is viewed from the front, the photodiode can receive light from the optical window provided in the portion between the outer edge of the housing and the display panel provided in the housing in the housing of the smartphone. There is. Further, the photodiodes of the photodetector are arranged so as to form four substantially squares in the vertical direction and four in the horizontal direction.

Japanese Unexamined Patent Publication No. 2018-25408

By the way, depending on the electronic device, it may be difficult to arrange the photodetector in which the photodiodes are arranged as described above. For example, in a smartphone, if the optical window is provided near the outer edge of the housing, it is difficult to arrange the photodetector so that the photodiode can receive light from the optical window. The above-mentioned problems are not limited to smartphones, but are common to electronic devices on which optical sensors are mounted and optical windows are formed.

An object of the present invention is to provide an optical sensor in which a photodiode can suitably receive light from the optical window even if the optical window is arranged near the outer edge of the electronic device, and an electronic device including the optical sensor.

An optical sensor that solves the above problems is an optical sensor including a chip having a plurality of photodiodes, and the plurality of photodiodes are in a first direction from the center of the chip when viewed from the light receiving direction of the photodiode. They are arranged so as to be biased to one side, and are arranged in an elongated shape with the first direction as the lateral direction and the second direction orthogonal to the first direction as the longitudinal direction.

According to this configuration, a plurality of photodiodes are arranged so as to be biased toward the first direction of the chip, so that, in the first direction, one side surface of the chip in the first direction and the plurality of photodiodes are arranged. The distance between them becomes smaller. Further, since the plurality of photodiodes are arranged in an elongated shape with the first direction as the lateral direction and the second direction as the longitudinal direction, all of the plurality of photodiodes are on one side of the first direction of the chip. It will be placed near the side of. As a result, even if an optical window is formed near the outer edge of the electronic device, the optical sensor can be arranged so that the photodiode can suitably receive light from the optical window.

According to the above-mentioned optical sensor and the electronic device provided with the optical sensor, the photodiode can suitably receive light from the optical window even if the optical window is arranged near the outer edge of the electronic device.

The block diagram which shows typically the electrical structure of the optical sensor of one Embodiment. The graph which shows the relationship between the light receiving sensitivity and the wavelength in the photodiode of the 1st diode group of an optical sensor. The graph which shows the relationship between the light receiving sensitivity and the wavelength in the photodiode of the 2nd diode group of an optical sensor. Perspective view of the optical sensor. The plan view which shows typically the internal structure of an optical sensor. Bottom view of the optical sensor. Sectional view of the optical sensor. The plan view which shows typically the layout of the circuit element of the chip of an optical sensor. Layout diagram of multiple photodiodes. The circuit diagram which shows typically the circuit structure of the conversion part connected to the photodiode of the 1st diode group. The circuit diagram which shows typically the circuit structure of the conversion part connected to the photodiode of the 2nd diode group. The circuit diagram which shows typically the circuit structure of the conversion part connected to the photodiode of the 2nd diode group. (A) is a perspective view of a smartphone which is an example of an electronic device equipped with an optical sensor, and (b) is an enlarged view of the optical window of the smartphone and its surroundings. (A) is a layout diagram of a plurality of photodiodes of a modified example, and (b) is a layout diagram of a part of a plurality of photodiodes obtained by further modifying (a). Layout diagram of multiple photodiodes in the modified example. Layout diagram of multiple photodiodes in the modified example. Bottom view of the optical sensor of the modified example.

Hereinafter, an embodiment of the optical sensor will be described with reference to the drawings. The embodiments shown below exemplify configurations and methods for embodying the technical idea, and do not limit the materials, shapes, structures, arrangements, dimensions, etc. of each component to the following. Absent. The following embodiments can be modified in various ways.

In the present specification, the "state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, and the member A and the member B are electrically connected. This includes the case of being indirectly connected via another member that does not affect the connection state.

(Embodiment)
As shown in FIG. 1, the optical sensor 1 has a light receiving unit 10, a conversion unit 20, a logic unit 30, a voltage generating unit 40, and a plurality of (8 in this embodiment) external terminals 2. The optical sensor 1 is a semiconductor integrated circuit in which a light receiving unit 10, a conversion unit 20, a logic unit 30, and a voltage generating unit 40 are formed on one semiconductor substrate. An example of the optical sensor 1 is an illuminance sensor that detects the illuminance of external light. A plurality of external terminals 2 include a power supply terminal VCC, a ground terminal GND, and the terminal of the interface of the communication bus (e.g., ^{I 2} C bus), and an interrupt output terminal.

The light receiving unit 10 has a plurality of (16 in this embodiment) photodiodes 10A for detecting external light, and an infrared transmission filter 10B. The infrared transmission filter 10B is a filter that absorbs visible light of external light and transmits infrared light of external light. The plurality of photodiodes 10A include a first photodiode group 11 having a first light receiving characteristic and a second photodiode group 12 having a second light receiving characteristic different from the first light receiving characteristic.

An example of the first light receiving characteristic is shown in FIG. 2, and an example of the second light receiving characteristic is shown in FIG. In FIGS. 2 and 3, the horizontal axis is the wavelength (nm) and the vertical axis is the light receiving sensitivity. The light receiving sensitivity of FIG. 3 is shown by normalizing the maximum sensitivity in the wavelength range of 400 nm to 1100 nm as 1. The light receiving sensitivity of FIG. 2 is shown by normalizing the maximum sensitivity in the wavelength range of 400 nm to 1100 nm of FIG. 3 as 1.

As shown in the first light receiving characteristic of FIG. 2, the light receiving sensitivity of the first photodiode group 11 gradually increases from 400 nm as the wavelength becomes longer, and becomes maximum at the wavelength of 850 nm. Then, the light receiving sensitivity of the first photodiode group 11 decreases from the wavelength of 850 nm as the wavelength becomes longer. As shown in the second light receiving characteristic of FIG. 3, the light receiving sensitivity of the second photodiode group 12 increases sharply as the wavelength becomes longer from 400 nm, and becomes maximum at a wavelength of 600 nm. Then, the light receiving sensitivity of the second photodiode group 12 decreases from a wavelength of 600 nm as the wavelength becomes longer. As shown in FIGS. 2 and 3, the light receiving sensitivity at the sensitivity peak (600 nm) of the second light receiving characteristic is higher than the light receiving sensitivity at the sensitivity peak (850 nm) of the first light receiving characteristic.

The first photodiode group 11 and the second photodiode group 12 each include a photodiode whose light receiving surface is covered with an infrared transmission filter 10B and a photodiode whose light receiving surface is not covered with an infrared transmission filter 10B. ..

As shown in FIG. 1, the conversion unit 20 converts an analog signal (photocurrent) from the light receiving unit 10 into a digital signal (output signal) and outputs it to the logic unit 30. The conversion unit 20 is, for example, an integral type analog / digital conversion circuit, and has a plurality of input channels. In this embodiment, the conversion unit 20 is a 4-channel analog / digital conversion circuit. The conversion unit 20 converts the analog signal of each channel into a digital signal. For convenience, each channel will be described as one analog / digital conversion circuit. The conversion unit 20 of the present embodiment has four analog / digital conversion circuits (denoted as “ADC” in the figure) 21 to 24. The analog / digital conversion circuit 21 converts the photocurrent of the photodiode not covered by the infrared transmission filter 10B in the first photodiode group 11 into a digital signal. The analog / digital conversion circuit 22 converts the photocurrent of the photodiode covered by the infrared transmission filter 10B in the first photodiode group 11 into a digital signal. The analog / digital conversion circuit 23 converts the photocurrent of the photodiode not covered by the infrared transmission filter 10B in the second photodiode group 12 into a digital signal. The analog / digital conversion circuit 24 converts the photocurrent of the photodiode covered by the infrared transmission filter 10B in the second photodiode group 12 into a digital signal.

The logic unit 30 has a function of controlling the conversion unit 20 and a function of communicating with the outside of the optical sensor 1. The logic unit 30 includes various circuit elements such as transistors, capacitors, and registers. The logic unit 30 is electrically connected to some of the external terminals 2 among the plurality of external terminals 2. A signal output from the logic unit 30, a power input to the light receiving unit 10, the conversion unit 20, the logic unit 30, and the like are performed via some of the external terminals 2.

The voltage generation unit 40 is connected to the power supply terminal (VCC) of the plurality of external terminals 2. The voltage generation unit 40 raises or lowers the voltage applied to the power supply terminal to generate a predetermined power supply voltage, and supplies the power supply voltage to the light receiving unit 10, the conversion unit 20, and the logic unit 30.

Next, the structure of the optical sensor 1 will be described with reference to FIGS. 4 to 7.
As shown in FIG. 4, the optical sensor 1 includes a chip 3, a heat radiating plate 4, a plurality of (8 in this embodiment) external terminals 2, a chip 3, a heat radiating plate 4, and a plurality of external terminals 2. A sealing resin 5 for sealing is provided. The number of external terminals 2 can be changed arbitrarily.

As shown in FIG. 5, the chip 3 is formed in a rectangular plate shape having a first side surface 3a to a fourth side surface 3d constituting each side surface of the chip 3. The chip 3 is rectangular in the plan view of the optical sensor 1 (hereinafter, simply referred to as “plan view”). In the chip 3 of the present embodiment, the long side direction is the first direction X and the short side direction is the second direction Y. Here, the plan view of the present embodiment coincides with the direction seen from the light receiving direction of the photodiode 10A (see FIG. 1).

In the chip 3, the first side surface 3a is parallel to the third side surface 3c, and the second side surface 3b is parallel to the fourth side surface 3d. The first side surface 3a is a side surface connecting one ends of the second side surface 3b and the fourth side surface 3d, and the third side surface 3c is a side surface connecting the other ends of the second side surface 3b and the fourth side surface 3d. The first side surface 3a and the third side surface 3c are side surfaces along the first direction X, and the second side surface 3b and the fourth side surface 3d are side surfaces along the second direction Y. In the present embodiment, the first side surface 3a is one side surface of the chip 3 in the second direction Y, and the second side surface 3b is the other side surface of the chip 3 in the second direction Y. Further, the second side surface 3b is a side surface on one side of the first direction X in the chip 3, and the fourth side surface 3d is a side surface on the other side of the first direction X in the chip 3. In an example of the size of the chip 3, the length of the chip 3 in the long side direction (the length of the first side surface 3a and the third side surface 3c in the first direction X) is 1.2 mm, which is in the short side direction of the chip 3. The length (the length of the second side surface 3b and the fourth side surface 3d in the second direction Y) is 0.8 mm.

The shape of the chip 3 in a plan view can be arbitrarily changed. In one example, the shape of the chip 3 in a plan view may be square. In this case, the direction along the first side surface 3a and the third side surface 3c of the chip 3 is defined as the first direction X. Further, the chip 3 may be a rectangle having the first direction X as the lateral direction and the second direction Y as the longitudinal direction in a plan view. In this case, the lengths of the first side surface 3a and the third side surface 3c are shorter than the lengths of the second side surface 3b and the fourth side surface 3d, respectively.

The chip 3 has the semiconductor substrate 50 shown in FIG. 7. The semiconductor substrate 50 is formed with a light receiving unit 10, a conversion unit 20, a logic unit 30, and a voltage generating unit 40 shown in FIG.
A plurality of (9 in this embodiment) electrode pads 61 to 69 are formed on the surface portion 3X of the chip 3. In the present embodiment, five electrode pads 61 to 65 are provided at the end of the chip 3 on the first side surface 3a side, and four electrode pads 66 to 69 are provided at the end of the chip 3 on the third side surface 3c side. It is provided.

The sealing resin 5 is made of, for example, a transparent epoxy resin or a silicone resin. The sealing resin 5 is formed in a rectangular shape having a first side surface 5a to a fourth side surface 5d constituting each side surface of the sealing resin 5. The sealing resin 5 is a rectangle in which the first direction X is the short side direction and the second direction Y is the long side direction in a plan view. As described above, in the present embodiment, the long side direction of the sealing resin 5 and the short side direction of the chip 3 are parallel, and the short side direction of the sealing resin 5 and the long side direction of the chip 3 are parallel.

In the sealing resin 5, the first side surface 5a is parallel to the third side surface 5c, and the second side surface 5b is parallel to the fourth side surface 5d. The first side surface 5a is a side surface connecting one ends of the second side surface 5b and the fourth side surface 5d, and the third side surface 5c is a side surface connecting the other ends of the second side surface 5b and the fourth side surface 5d. The first side surface 5a and the third side surface 5c are side surfaces along the first direction X, and the second side surface 5b and the fourth side surface 5d are side surfaces along the second direction Y. In the present embodiment, the first side surface 5a is the side surface on one side of the sealing resin 5 in the second direction Y, and the second side surface 5b is the side surface on the other side of the sealing resin 5 in the second direction Y. The second side surface 5b is one side surface of the sealing resin 5 in the first direction X, and the fourth side surface 5d is the other side surface of the sealing resin 5 in the first direction X. As shown in FIG. 5, in the second direction, the first side surface 5a of the sealing resin 5 is formed on the first side surface 3a side of the chip 3, and the third side surface 5c of the sealing resin 5 is on the third side surface 3c side of the chip 3. Is formed in. In the first direction X, the second side surface 5b of the sealing resin 5 is formed on the second side surface 3b side of the chip 3, and the fourth side surface 5d of the sealing resin 5 is formed on the fourth side surface 3d side of the chip 3. .. In one example, the length of the sealing resin 5 in the short side direction (the length of the first side surface 5a and the third side surface 5c in the first direction X) is 2.0 mm, and the length of the sealing resin 5 in the long side direction. (The length of the second side surface 5b and the fourth side surface 5d in the second direction Y) is 2.1 mm. The shape of the sealing resin 5 in a plan view may be square due to a manufacturing error of the sealing resin 5.

The chip 3 is closer to the second side surface 5b, which is one side surface of the side surfaces 5b and 5d of the sealing resin 5 in the first direction X, than the center of the first direction X of the sealing resin 5. Is located in. In other words, the chip 3 is biased with respect to the sealing resin 5 in the first direction X. In the present embodiment, the chip 3 is arranged so as to be biased toward the second side surface 5b side with respect to the fourth side surface 5d of the sealing resin 5 in the first direction X. The center line L11 extending along the second direction Y at the center of the first direction X of the chip 3 is sealed more than the center line L21 extending along the second direction Y at the center of the first direction X of the sealing resin 5. It can be said that it is located on the second side surface 5b side of the resin 5. Further, in the first direction X, the distance W1 between the second side surface 3b of the chip 3 and the second side surface 5b of the sealing resin 5 is the fourth side surface 3d of the chip 3 and the fourth side surface 5d of the sealing resin 5. The distance between and is smaller than W2.

In a plan view, the chip 3 is arranged so as to be located at the center of the sealing resin 5 in the second direction Y. In other words, the position of the center line L12 extending along the first direction X at the center of the second direction Y of the chip 3 is the center line extending along the first direction X at the center of the second direction Y of the sealing resin 5. It will be the same as the position of L22. In the second direction Y, the distance W3 between the first side surface 3a of the chip 3 and the first side surface 5a of the sealing resin 5 is the third side surface 3c of the chip 3 and the third side surface 5c of the sealing resin 5. The distance between them is equal to W4. Here, the fact that the distance W3 is equal to the distance W4 means that the difference between the distance W3 and the distance W4 is within 5% of the distance W3.

The position of the chip 3 in the second direction Y can be arbitrarily changed. In the second direction Y, the chip 3 may be arranged closer to the first side surface 5a of the sealing resin 5 or may be arranged closer to the third side surface 5c of the sealing resin 5.

The plurality of external terminals 2 are made of a conductive material such as copper or aluminum. The plurality of external terminals 2 are arranged on both sides of the chip 3 in the second direction Y. In the present embodiment, the four external terminals 2 are arranged on one side of the second direction Y with respect to the chip 3, that is, on the side of the first side surface 5a of the sealing resin 5, and the second direction Y with respect to the chip 3. Four external terminals 2 are arranged on the other side, that is, on the third side surface 5c side of the sealing resin 5. The four external terminals 2 are arranged at intervals in the first direction X. Two of the four external terminals 2 arranged on one side of the second direction Y with respect to the chip 3 are connected to the electrode pads 61 and 62 of the chip 3 by the conductive wires 6A and 6B. ing. Three of the four external terminals 2 arranged on the other side of the second direction Y with respect to the chip 3 have the electrode pads 66, 67 of the chip 3 formed by the conductive wires 6C, 6D, 6E. It is connected to 69. The conductive wires 6A to 6E are made of, for example, aluminum, gold, copper or the like. The conductive wires 6A to 6E are formed by, for example, wire bonding.

The heat radiating plate 4 is made of a material having excellent heat radiating properties, such as copper and aluminum. For the heat radiating plate 4, for example, the same material as that of the external terminal 2 is used. The semiconductor substrate 50 (see FIG. 7) of the chip 3 is attached to the surface 4A (see FIG. 4) of the heat radiating plate 4 by a joining member such as solder.

As shown in FIG. 6, the eight external terminals 2 and the heat radiating plate 4 have exposed surfaces 2A and 4B exposed from the sealing resin 5. The exposed surface 4B of the heat radiating plate 4 is formed with a notch 4C for allowing the user to recognize the orientation of the optical sensor 1. The area of the exposed surface 4B is smaller than the area of the portion of the heat radiating plate 4 shown by the broken line that is not exposed from the sealing resin 5. As shown in FIG. 6, the portion (broken line portion) on which the chip 3 is placed on the heat radiating plate 4 extends from the base portion 4X of the heat radiating plate 4 formed of the exposed surface 4B toward both sides in the second direction Y. Further, as shown in FIG. 6, the optical sensor 1 of the present embodiment is a surface mount type.

As shown in FIGS. 6 and 7, the base portion 4X of the heat radiating plate 4 has a rectangular plate shape having a first side surface 4a to a fourth side surface 4d. The base portion 4X of the heat radiating plate 4 is a rectangle having the first direction X as the long side direction and the second direction Y as the short side direction in the bottom view of the optical sensor 1. Note that in FIG. 7, hatching of the cross section is omitted for convenience.

In the base portion 4X of the heat radiating plate 4, the first side surface 4a is parallel to the third side surface 4c, and the second side surface 4b is parallel to the fourth side surface 4d. The first side surface 4a is a side surface connecting one ends of the second side surface 4b and the fourth side surface 4d, and one end of the third side surface 4c is connected to the other end of the fourth side surface 4d. The first side surface 4a and the third side surface 4c are side surfaces along the first direction X, and the second side surface 4b and the fourth side surface 4d are side surfaces along the second direction Y. In the present embodiment, the first side surface 4a is the side surface on one side of the second direction Y in the base portion 4X of the heat radiating plate 4, and the second side surface 4b is the side surface on the other side of the second direction Y in the base portion 4X of the heat radiating plate 4. Is. Further, the second side surface 4b is a side surface on one side of the first direction X in the base portion 4X of the heat radiating plate 4, and the fourth side surface 4d is a side surface on the other side of the first direction X in the base portion 4X of the heat radiating plate 4. Therefore, the first side surface 4a of the base portion 4X of the heat radiating plate 4 is formed on the first side surface 3a side of the chip 3 (the first side surface 5a side of the sealing resin 5), and the third side surface 4c of the base portion 4X of the heat radiating plate 4 is formed. Is formed on the third side surface 3c side of the chip 3 (the third side surface 5c side of the sealing resin 5). The second side surface 4b of the base 4X of the heat radiating plate 4 is formed on the second side surface 3b side of the chip 3 (the second side surface 5b side of the sealing resin 5), and the fourth side surface 4d of the base 4X of the heat radiating plate 4 is the chip 3. It is formed on the 4th side surface 3d side (4th side surface 5d side of the sealing resin 5).

Further, the base portion 4X of the heat radiating plate 4 has a fifth side surface 4e constituting the notch portion 4C. One end of the fifth side surface 4e is connected to the other end of the third side surface 4c, and the other end of the fifth side surface 4e is connected to the other end of the second side surface 4b. The cutout portion 4C is formed at the center of the first direction X of the chip 3 on the second side surface 3b side of the chip 3 with respect to the center line L11 extending along the second direction Y. The cutout portion 4C is formed at the center of the second direction Y of the chip 3 on the third side surface 3c side of the chip 3 with respect to the center line L12 extending along the first direction X. The position of the notch portion 4C can be arbitrarily changed. In one example, the cutout portion 4C (fifth side surface 4e) may be connected to one end of the first side surface 4a of the base portion 4X of the heat radiating plate 4 and the other end of the fourth side surface 4d.

The size of the heat radiating plate 4 in the first direction X is larger than the size of the first direction X of the chip 3. The size of the heat radiating plate 4 in the second direction Y is equal to the size of the second direction Y of the chip 3. Here, the size of the heat radiating plate 4 in the second direction Y is equal to the size of the second direction Y of the chip 3 is the size of the heat radiating plate 4 in the second direction Y and the size of the second direction Y of the chip 3. The difference is within 5% of the size of the heat radiating plate 4 in the second direction Y. Further, the size of the base portion 4X of the heat radiating plate 4 in the second direction Y is smaller than the size of the second direction Y of the chip 3. In the present embodiment, the size of the base portion 4X of the heat radiating plate 4 in the second direction Y is smaller than the size of the heat radiating plate 4 in the second direction Y, but the present invention is not limited to this, and the base portion of the heat radiating plate 4 in the second direction Y is not limited to this. The size of 4X may be larger than the size of the heat radiating plate 4 in the second direction Y.

The chip 3 is a second side surface 4b which is one side surface arranged on one side of both side surfaces 4b and 4d of the first direction X of the base portion 4X of the heat radiating plate 4 with respect to the center of the first direction X of the heat radiating plate 4. It is located nearby. In other words, the chip 3 is biased with respect to the heat radiating plate 4 in the first direction X. The chips 3 are arranged so as to be biased toward the second side surface 4b side with respect to the fourth side surface 4d of the base portion 4X of the heat radiating plate 4 in the first direction X. In the present embodiment, the chip 3 is arranged at the end of the base portion 4X of the heat radiating plate 4 on the second side surface 4b side in the first direction X. The center line L11 extending along the second direction Y at the center of the first direction X of the chip 3 is a heat radiating plate 4 more than the center line L31 extending along the second direction Y at the center of the first direction X of the heat radiating plate 4. It can be said that it is located on the second side surface 4b side of the base portion 4X. In the present embodiment, the position of the center line L31 extending along the second direction Y at the center of the first direction X of the heat radiating plate 4 is along the second direction Y at the center of the first direction X of the sealing resin 5. It becomes the same as the position of the extending center line L21. Further, in the first direction X, the distance W5 between the second side surface 3b of the chip 3 and the second side surface 4b of the base portion 4X of the heat radiation plate 4 is the distance W5 between the fourth side surface 3d of the chip 3 and the base portion 4X of the heat radiation plate 4. It is smaller than the distance W6 between the fourth side surface 4d.

The chip 3 is arranged so as to be located at the center of the heat radiating plate 4 in the second direction Y. In other words, the position of the center line L12 extending along the first direction X at the center of the second direction Y of the chip 3 is along the first direction X at the center of the second direction Y of the heat dissipation plate 4. It is equal to the position of the center line L32 extending in the second direction Y. Here, the position of the center line L12 in the second direction Y is equal to the position of the center line L32 in the second direction Y means that the distance between the center line L12 and the center line L32 in the second direction Y is the chip 3. The relationship is within 5% of the dimension of the second direction Y.

As shown in FIG. 7, the photodiode 10A has an n-type region 51 formed on the surface 50A of the p-type semiconductor substrate 50. The p-type semiconductor substrate 50 is connected to the ground. The n-type region 51 is formed by doping the surface 50A of the semiconductor substrate 50 with n-type impurities. As a result, the photodiode 10A that generates a photocurrent is formed on the semiconductor substrate 50. The photodiode 10A includes a pn junction surface 52 between the p-type semiconductor substrate 50 and the n-type region 51.

Since the conversion unit 20, the logic unit 30, and the like are also formed on the semiconductor substrate 50, for example, an impurity region of the transistor constituting the logic unit 30 may be formed. In this case, the n-type region 51 may be formed in the same process as the impurity region such as the source region, drain region, and embedded layer (L / I, B / L) for element separation constituting the transistor.

An interlayer insulating film 53 is formed on the surface 50A of the semiconductor substrate 50. The interlayer insulating film 53 is formed so as to cover the entire surface 50A of the semiconductor substrate 50. The interlayer insulating film 53 is made of an insulating material such as silicon oxide (SiO ₂ ). The interlayer insulating film 53 may be a single layer or a plurality of layers.

An infrared transmission filter 10B is formed on a part of the surface 53A of the interlayer insulating film 53. The infrared transmission filter 10B covers the light receiving surface 14 of one of the two photodiodes 10A shown in FIG. 7. The light receiving surface 14 of the photodiode is formed on the surface 50A of the semiconductor substrate 50. The infrared transmission filter 10B is configured by, for example, superimposing two or more types of color filters. Specifically, the infrared transmission filter 10B is configured by superimposing two or more types of filters among a yellow filter, a red filter, a green filter, and a blue filter.

Next, the layout of the light receiving portion 10 and the like in the chip 3 will be described with reference to FIGS. 7 and 8. In the following description, the center of the chip 3 in the first direction X is the position of the center line L11 in the chip 3 in the first direction X.

As shown in FIG. 8, the light receiving unit 10, the conversion unit 20, and the logic unit 30 are arranged in the first direction X. The light receiving unit 10, the conversion unit 20, and the logic unit 30 are arranged in the order of the light receiving unit 10, the conversion unit 20, and the logic unit 30 from the second side surface 3b to the fourth side surface 3d of the chip 3 in the first direction X. Has been done.

The plurality of photodiodes 10A (light receiving unit 10) have a second side surface 3b which is one side surface of both side surfaces 3b and 3d of the first direction X of the chip 3 with respect to the center of the chip 3 in the first direction X. It is located near. In other words, the plurality of photodiodes 10A (light receiving units 10) are arranged so as to be biased toward one side of the first direction X with respect to the center of the chip 3. In the present embodiment, the light receiving unit 10 is arranged on the second side surface 3b side of the chip 3 with respect to the center of the chip 3 in the first direction X. The light receiving unit 10 is arranged at the end on the second side surface 3b side of the chip 3 in the first direction X.

The conversion unit 20 is arranged between the light receiving unit 10 and the logic unit 30 in the first direction X. The analog / digital conversion circuits 21 to 24 are arranged in the second direction Y. In the present embodiment, the analog / digital conversion circuit 21 and the analog / digital conversion circuit 22 are arranged adjacent to each other in the second direction Y, and the analog / digital conversion circuit 23 and the analog / digital conversion circuit 24 are adjacent to each other. It is arranged like this. In the present embodiment, the conversion unit 20 is arranged closer to the light receiving unit 10 than the logic unit 30 in the first direction X. In other words, the analog / digital conversion circuits 21 to 24 are arranged closer to the light receiving unit 10 than to the logic unit 30. Further, the conversion unit 20 is arranged on the second side surface 3b side of the chip 3 with respect to the center of the chip 3 in the first direction X. In other words, the analog / digital conversion circuits 21 to 24 are arranged on the second side surface 3b side of the chip 3 with respect to the center of the chip 3 in the first direction X. As described above, the light receiving unit 10 and the conversion unit 20 are arranged on the second side surface 3b side of the chip 3 with respect to the center of the chip 3 in the first direction X.

The logic unit 30 is arranged on the 4th side surface 3d side of the chip 3 with respect to the center of the chip 3 in the first direction X. In the present embodiment, the center line LC1 extending in the second direction Y at the center of the logic unit 30 in the first direction X, that is, at the center of the first direction X of the logic unit 30, is the center of the chip 3 and the chip in the first direction X. It is located on the second side surface 3b side of the chip 3 with respect to the center of the third side surface 3d. In the first direction X, the center of the chip 3 and the center of the fourth side surface 3d of the chip 3 are located at the center of the first direction X between the center line L11 of the chip 3 and the fourth side surface 3d of the chip 3. This is the position of the center line L13 extending in two directions Y.

The position of the center line LA extending in the first direction X at the center of the light receiving portion 10 in the second direction Y, that is, at the center of the second direction Y of the light receiving portion 10, is the center of the second direction Y of the chip 3. Is equal to the position of the center line L12 extending in the first direction X in the second direction Y. Here, the position of the center line LA in the second direction Y is equal to the position of the center line L12 in the second direction Y means that the distance between the center line LA and the center line L12 in the second direction Y is the chip 3. The relationship is within 5% of the dimension of the second direction Y.

The position of the center line LB2 extending in the first direction X at the center of the conversion unit 20 in the second direction Y, that is, the center of the second direction Y of the conversion unit 20, is the center of the second direction Y of the chip 3. Is equal to the position of the center line L12 extending in the first direction X in the second direction Y. Here, the position of the center line LB2 in the second direction Y is equal to the position of the center line L12 in the second direction Y means that the distance between the center line LB2 and the center line L12 in the second direction Y is the chip 3. The relationship is within 5% of the dimension of the second direction Y.

The position of the center line LC2 extending in the first direction X at the center of the logic unit 30 in the second direction Y, that is, at the center of the second direction Y of the logic unit 30, is the center of the second direction Y of the chip 3. Is equal to the position of the center line L12 extending in the first direction X in the second direction Y. Here, the position of the center line LC2 in the second direction Y is equal to the position of the center line L12 in the second direction Y means that the distance between the center line LC2 and the center line L12 in the second direction Y is the chip 3. The relationship is within 5% of the dimension of the second direction Y.

As shown in FIG. 9, in the present embodiment, the photodiode 10A of the light receiving unit 10 includes 16 photodiodes PD1 to PD16. In the photodiode 10A, eight photodiodes arranged in the second direction Y are arranged in two rows in the first direction X. In FIG. 9, the photodiodes PD1 to PD8 form the photodiode in the first row, and the photodiodes PD9 to PD16 form the photodiode in the second row. As described above, the photodiodes PD1 to PD16 are arranged in an elongated shape with the first direction X as the lateral direction and the second direction Y orthogonal to the first direction X as the longitudinal direction in a plan view.

In the first direction X, the photodiodes PD1 to PD8 are arranged on the second side surface 3b side of the chip 3 with respect to the photodiodes PD9 to PD16. The photodiodes PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8 are arranged in this order from the third side surface 3c of the chip 3 in the second direction Y toward the first side surface 3a. The photodiodes PD9, PD10, PD11, PD12, PD13, PD14, PD15, and PD16 are arranged in this order from the third side surface 3c of the chip 3 in the second direction Y toward the first side surface 3a.

The infrared transmission filter 10B covers the photodiodes PD1, PD3, PD5, PD7 of the photodiodes PD1 to PD8. Further, the infrared transmission filter 10B covers the photodiodes PD10, PD12, PD14, and PD16 among the photodiodes PD9 to PD16. As described above, in the first direction X, the photodiodes PD1 to PD16 are arranged so that the photodiodes covered with the infrared transmission filter 10B and the photodiodes not covered with the infrared transmission filter 10B are adjacent to each other. ing. Further, in the second direction Y, the photodiodes PD1 to PD8 and the photodiodes PD9 to PD16 are alternately alternating with the photodiodes covered with the infrared transmission filter 10B and the photodiodes not covered with the infrared transmission filter 10B, respectively. Have been placed. As described above, the infrared transmission filters 10B are arranged in a staggered manner with respect to the photodiodes PD1 to PD16.

The photodiodes PD1 to PD16 are divided into a first photodiode group 11 and a second photodiode group 12. The first photodiode group 11 is composed of photodiodes PD4, PD5, PD12, and PD13. The second photodiode group 12 is composed of photodiodes PD1 to PD3, PD6 to PD8, PD9 to PD11, and PD14 to PD16. As shown in FIG. 9, the second photodiode group 12 is arranged on both sides of the first photodiode group 11 in the second direction Y. The second photodiode group 12 including the photodiodes PD1 to PD3 and PD9 to PD11 is arranged on the third side surface 3c side of the chip 3 with respect to the first photodiode group 11. The second photodiode group 12 including the photodiodes PD6 to PD8 and PD14 to PD16 is arranged on the first side surface 3a side of the chip 3 with respect to the first photodiode group 11. As shown in FIG. 9, in the present embodiment, the first photodiode group 11 is arranged on one side of the first photodiode group 11 (for example, the third side surface 3c side of the chip 3 with respect to the first photodiode group 11) in the second direction Y. The number of photodiodes in the two photodiode group 12 is larger than the number of photodiodes in the first photodiode group 11. Further, in the second direction Y, the photodiode of the second photodiode group 12 arranged on the other side of the first photodiode group 11 (for example, the first side surface 3a side of the chip 3 with respect to the first photodiode group 11). The number is larger than the number of photodiodes in the first photodiode group 11. Further, the number of photodiodes of the second photodiode group 12 arranged on one side of the first photodiode group 11 in the second direction Y is arranged on the other side of the first photodiode group 11 in the second direction Y. It is equal to the number of photodiodes in the second photodiode group 12.

As shown in FIG. 8, in the present embodiment, in the region where the plurality of photodiodes 10A are arranged, that is, the region R1 where the light receiving portion 10 is formed, the second direction Y is the long side direction in the plan view, and the first It is a rectangle whose direction X is the short side direction. The region where the analog / digital conversion circuits 21 to 24 are arranged, that is, the region R2 where the conversion unit 20 is formed, is a rectangle in which the second direction Y is the long side direction and the first direction X is the short side direction in a plan view. Is. The region R3 in which the logic portion 30 is formed is a rectangle in which the second direction Y is the long side direction and the first direction X is the short side direction.

The shapes of the regions R2 and R3 in a plan view can be arbitrarily changed. For example, the shape of the region R2 in a plan view may be a square. The shape of the region R3 in a plan view may be a square or a rectangle in which the first direction X is the long side direction and the second direction Y is the short side direction.

In the second direction Y, the size of the region R1 is larger than the size of the region R2 and the size of the region R3. In the first direction X, the size of the region R1 is smaller than the size of the region R2 and the size of the region R3. In the first direction X, the size of the region R2 is smaller than the size of the region R3. The size of the region R2 in the first direction X may be larger than the size of the region R3 in the first direction X.

The region R1 is formed on the second side surface 3b side of the chip 3 with respect to the straight line L14 extending in the second direction Y at the center of the first direction X between the center of the chip 3 in the first direction X and the second side surface 3b of the chip 3. Has been done. That is, the plurality of photodiodes 10A are arranged on the second side surface 3b side of the chip 3 with respect to the straight line L14 in the first direction X. Further, the region R2 is formed on the fourth side surface 3d side of the chip 3 with respect to the straight line L14 in the first direction X.

The plurality of electrode pads 61 to 69 are formed in a region of the chip 3 that does not overlap with the plurality of photodiodes 10A when viewed from the second direction Y. More specifically, the plurality of electrode pads 61 to 69 are arranged on the 4th side surface 3d side of the chip 3 with respect to the light receiving portion 10 in the first direction X. The plurality of electrode pads 61 to 69 are arranged on both sides of the logic portion 30 in the second direction Y. In the present embodiment, the electrode pads 61 to 65 are arranged on the first side surface 3a side of the chip 3 with respect to the logic portion 30 in the second direction Y. The electrode pads 66 to 69 are arranged on the third side surface 3c side of the chip 3 with respect to the logic portion 30 in the second direction Y.

In the present embodiment, the electrode pad 61 is arranged on the second side surface 3b side of the chip 3 with respect to the center of the chip 3 in the first direction X. Specifically, the electrode pad 61 is arranged at a position overlapping the conversion unit 20 when viewed from the second direction Y. In the present embodiment, the electrode pad 61 is the fourth side surface of the chip 3 with respect to the center line LB1 extending in the second direction Y at the center of the conversion unit 20 in the first direction X, that is, at the center of the first direction X of the conversion unit 20. It is arranged on the 3d side. When viewed from the first direction X, the electrode pad 61 is arranged at a position overlapping the region R1 in which the plurality of photodiodes 10A are arranged.

The electrode pads 62 to 65 are arranged on the fourth side surface 3d side of the chip 3 with respect to the center of the chip 3 in the first direction X. Specifically, the electrode pads 62 to 65 are arranged at positions that overlap with the logic portion 30 when viewed from the second direction Y. The electrode pads 62, 63, 64, and 65 are arranged in this order in the direction from the second side surface 3b of the chip 3 to the fourth side surface 3d in the first direction X. The electrode pads 62 to 65 are arranged at positions where they overlap each other when viewed from the first direction X. In the second direction Y, the positions of the electrode pads 62 and 65 and the positions of the electrode pads 63 and 64 are different. In the second direction Y, the electrode pads 62 and 65 are arranged closer to the logic portion 30 than the first side surface 3a of the chip 3. In the second direction Y, the electrode pads 63 and 64 are arranged closer to the first side surface 3a of the chip 3 than the logic portion 30. The electrode pads 61, 62, and 65 are arranged so as to overlap the region R1 in which the plurality of photodiodes 10A are arranged when viewed from the first direction X. The electrode pads 63 and 64 are arranged closer to the first side surface 3a of the chip 3 than the region R1 when viewed from the first direction X.

The electrode pads 66 to 69 are arranged on the fourth side surface 3d side of the chip 3 with respect to the center of the chip 3 in the first direction X. Specifically, the electrode pads 66 to 69 are arranged at positions that overlap with the logic portion 30 when viewed from the second direction Y. The electrode pads 66, 67, 68, and 69 are arranged in this order in the direction from the second side surface 3b of the chip 3 to the fourth side surface 3d in the first direction X. The electrode pads 66 to 69 are arranged at positions overlapping each other when viewed from the first direction X. In the second direction Y, the positions of the electrode pads 66, 67, 69 and the positions of the electrode pads 68 are different. In the second direction Y, the electrode pads 66, 67, 69 are arranged closer to the logic portion 30 than the third side surface 3c of the chip 3. In the second direction Y, the electrode pad 68 is arranged closer to the third side surface 3c of the chip 3 than the logic portion 30. The electrode pads 66, 67, 69 are arranged so as to overlap the region R1 in which the plurality of photodiodes 10A are arranged when viewed from the first direction X. The electrode pad 68 is arranged closer to the third side surface 3c of the chip 3 than the region R1 when viewed from the first direction X.

Next, an outline of the circuit configuration and operation of the light receiving unit 10 and the conversion unit 20 will be described with reference to FIGS. 10 to 12.
The conversion unit 20 is an output circuit that outputs the total value of the photocurrents generated by the photodiodes PD1 to PD16. As described above, the conversion unit 20 has four analog / digital conversion circuits 21 to 24. The connection correspondence between the four analog / digital conversion circuits 21 to 24 and the first photodiode group 11 and the second photodiode group 12 is as follows. That is, the analog / digital conversion circuits 21 and 22 are connected to the first photodiode group 11, and the analog / digital conversion circuits 23 and 24 are connected to the second photodiode group 12.

The analog / digital conversion circuits 21 and 22 shown in FIG. 10 include an amplifier 71, a capacitor 74, and a reference voltage application unit 75. An example of the amplifier 71 is an operational amplifier. The capacitor 74 is connected between the first input terminal 71a and the output terminal 71c of the amplifier 71. The analog-to-digital conversion circuit 21 has an integrator including an amplifier 71 and a capacitor 74. The reference voltage application unit 75 applies the first reference voltage to the second input terminal 71b of the amplifier 71. An example of the first reference voltage is 0.6V.

As shown in FIG. 10, the analog / digital conversion circuit 21 is connected to the photodiodes PD4 and PD13, which are photodiodes not covered by the infrared transmission filter 10B in the first photodiode group 11. The cathodes of the photodiodes PD4 and PD13 are connected to the first input terminal 71a of the amplifier 71 of the analog / digital conversion circuit 21. The anodes of the photodiodes PD4 and PD13 are connected to the ground. The analog / digital conversion circuit 22 is connected to the photodiodes PD5 and PD12, which are photodiodes covered with an infrared transmission filter 10B in the first photodiode group 11. The cathodes of the photodiodes PD5 and PD12 are connected to the first input terminal 71a of the amplifier 71 of the analog / digital conversion circuit 22. The anodes of the photodiodes PD5 and PD12 are connected to the ground. The total photocurrent of the photodiodes PD4 and PD13 is input to the analog / digital conversion circuit 21. The total photocurrent of the photodiodes PD5 and PD12 is input to the analog / digital conversion circuit 22.

The analog / digital conversion circuits 23 and 24 shown in FIGS. 11 and 12 each have an amplifier 71, a reference voltage application unit 72, and a capacitor 74, respectively. The connection configuration of the amplifier 71 and the capacitor 74 of the analog / digital conversion circuits 23 and 24 is the same as that of the analog / digital conversion circuits 21 and 22. The reference voltage application unit 72 is connected to the second input terminal 71b of the amplifier 71. The reference voltage application unit 72 applies a second reference voltage to the second input terminal 71b of the amplifier 71. An example of the second reference voltage is 1.2V.

As shown in FIG. 11, the analog / digital conversion circuit 23 is attached to the photodiodes PD2, PD6, PD8, PD9, PD11, PD15, which are photodiodes not covered by the infrared transmission filter 10B in the second photodiode group 12. It is connected. The anodes of the photodiodes PD2, PD6, PD8, PD9, PD11, and PD15 are connected to the first input terminal 71a of the amplifier 71 of the analog / digital conversion circuit 23. The cathodes of the photodiodes PD2, PD6, PD8, PD9, PD11, and PD15 are connected to the power supply wiring 41 of the voltage generation unit 40 (see FIG. 1).

As shown in FIG. 12, the analog / digital conversion circuit 24 is connected to the photodiodes PD1, PD3, PD7, PD10, PD14, PD16, which are photodiodes covered with the infrared transmission filter 10B in the second photodiode group 12. Has been done. The anodes of the photodiodes PD1, PD3, PD7, PD10, PD14, and PD16 are connected to the first input terminal 71a of the amplifier 71 of the analog / digital conversion circuit 24. The cathodes of the photodiodes PD1, PD3, PD7, PD10, PD14, and PD16 are connected to the power supply wiring 41 of the voltage generation unit 40 (see FIG. 1).

In the analog-to-digital conversion circuit 21, the integrated signal, which is the output of the integrator including the amplifier 71 and the capacitor 74, rises based on the charge of the capacitor 74 accumulated by the photocurrent generated by the photodiodes PD4 and PD13 due to the light reception. To do. The analog / digital conversion circuit 21 converts a voltage proportional to the amount of light received by the photodiodes PD4 and PD13 into a digital value (output signal) based on the integrated signal and outputs the voltage to the logic unit 30 (see FIG. 1). Similar to the analog / digital conversion circuit 21, the analog / digital conversion circuit 22 outputs an output signal based on the photocurrents of the photodiodes PD5 and PD12 to the logic unit 30.

In the analog / digital conversion circuit 23, the integrator signal, which is the output of the integrator composed of the amplifier 71 and the capacitor 74, drops based on the photocurrent generated in the photodiodes PD2, PD6, PD8, PD9, PD11, and PD15 by receiving light. To do. The analog / digital conversion circuit 23 converts a voltage proportional to the amount of light received by the photodiodes PD2, PD6, PD8, PD9, PD11, and PD15 into a digital value (output signal) based on the integrated signal and outputs the voltage to the logic unit 30. To do. Similar to the analog / digital conversion circuit 23, the analog / digital conversion circuit 24 outputs an output signal based on the photocurrents of the photodiodes PD1, PD3, PD7, PD10, PD14, and PD16 to the logic unit 30. The logic unit 30 outputs the output signals of the analog / digital conversion circuits 21 to 24 to an external device of the optical sensor 1.

(Electronic equipment equipped with an optical sensor)
The optical sensor 1 of the present embodiment can be mounted on an electronic device such as a smartphone, a mobile phone, a tablet PC, a laptop personal computer, a digital camera, a car navigation device, and a television. FIG. 13A is a perspective view showing the appearance of the smartphone 100, which is an example of the electronic device.

The smartphone 100 is configured by accommodating electronic components inside a flat rectangular parallelepiped housing 101. The housing 101 has a pair of rectangular main surfaces on the front side and the back side, and the pair of main surfaces are connected by four side surfaces. The display surface of the display panel 102 composed of a liquid crystal panel, an organic EL panel, or the like is exposed on one main surface of the housing 101. The display surface of the display panel 102 constitutes a touch panel and provides an input interface for the user.

A microphone 103 is provided on one side surface of the housing 101. The microphone 103 provides a mouthpiece for telephone functions and can also be used as a microphone for recording. A speaker 104 is arranged in the vicinity of the short side of the pair of short sides of the display panel 102 opposite to the side on which the microphone 103 is located. The speaker 104 provides an earpiece for a telephone function and is also used as an acoustic unit for reproducing music data or the like. An optical window 105 is arranged next to the speaker 104. The optical sensor 1 is arranged in the housing 101 at a position facing the optical window 105.

Further, in the present embodiment, the smartphone 100 calculates the illuminance based on the output signal output from the optical sensor 1. The illuminance calculation is performed by a known method. In one example, the photocurrent generated by the light reception of the second photodiode group 12 having a sensitivity peak in the visible light region and the first photodiode group 11 having a sensitivity peak in the infrared region is measured, and two types of photos are measured. The illuminance is calculated based on the comparison calculation of each measured value in the diode. The logic unit 30 of the optical sensor 1 may calculate the illuminance.

The operation of this embodiment will be described.
The chips 3 are arranged so as to be biased toward the second side surface 5b side of the sealing resin 5 in the first direction X with respect to the sealing resin 5. Therefore, the distance W1 (see FIG. 5) between the second side surface 5b of the sealing resin 5 and the second side surface 3b of the chip 3 can be reduced in the first direction X. Further, the light receiving portion 10 of the chip 3 is arranged so as to be biased toward the end portion on the second side surface 3b side of the chip 3 in the first direction X. Since the second side surface 5b side of the sealing resin 5 and the second side surface 3b side of the chip 3 are the same side in the first direction X, the light receiving portion 10 is further biased toward the second side surface 5b side of the sealing resin 5. It will be arranged like this. In addition, since the plurality of photodiodes 10A are arranged in an elongated shape with the first direction X as the lateral direction and the second direction Y as the longitudinal direction, the second side surface 3b of the chip 3 in the first direction X The distance W7 (see FIG. 8) from the region R1 to the side of the chip 3 on the 4d side 3d side in the region R1 where the plurality of photodiodes 10A are formed can be reduced. That is, by arranging the plurality of photodiodes 10A in the elongated shape, the region R1 in which the plurality of photodiodes 10A are formed is formed at the end on the second side surface 3b side of the chip 3 in the first direction X. It will be.

By reducing the distance W1 and the distance W7 in this way, the region R1 in which the plurality of photodiodes 10A are formed is formed on one side surface of the side surfaces 5b and 5d of the sealing resin 5 in the first direction X. It can be arranged near the second side surface 5b.

By the way, as the occupancy rate of the display panel 102 with respect to the total area of the smartphone 100 when the smartphone 100 is viewed from the front increases, the space in which the optical window 105 can be arranged is reduced. In other words, the distance XD between the edge 101a of the housing 101 of the smartphone 100 and the outer edge of the display panel 102 is small. Therefore, since the optical window 105 is provided near the edge 101a of the housing 101, it is difficult to arrange the optical sensor so that the plurality of photodiodes 10A can receive light from the optical window 105.

In view of such a situation, in the present embodiment, when the optical sensor 1 is mounted on the smartphone 100, the distance W8, which is the total of the distance W1 and the distance W7 in the optical sensor 1, becomes smaller as described above. As shown in 13 (b), the optical sensor 1 can be arranged so as to approach the edge 101a of the housing 101. Therefore, the distance XD between the edge 101a of the housing 101 and the display panel 102 is small, and even if the optical window 105 is provided near the edge 101a of the housing 101, the light receiving unit is located at a position facing the optical window 105. The optical sensor 1 can be arranged in the housing 101 so that the 10 is arranged.

According to this embodiment, the following effects can be obtained.
(1) In a plan view, the plurality of photodiodes 10A are closer to the second side surface 3b, which is one side surface of both side surfaces 3b and 3d of the first direction X of the chip 3, than the center of the chip 3. Be placed. In addition, the plurality of photodiodes 10A are arranged in an elongated shape with the first direction X as the lateral direction and the second direction Y orthogonal to the first direction X as the longitudinal direction. According to this configuration, the distance W7 between the plurality of photodiodes 10A in the first direction X and the second side surface 3b of the chip 3 becomes small. As a result, the positions of the plurality of photodiodes 10A with respect to the optical sensor 1 can be set to positions biased in the first direction X in the sealing resin 5. Therefore, even if the optical window 105 is arranged near the edge 101a of the smartphone 100, the plurality of photodiodes 10A can suitably receive light from the optical window 105.

(2) In a plan view, the light receiving unit 10, the conversion unit 20, and the logic unit 30 are arranged in the first direction X of the chip 3. In a plan view, the conversion unit 20 is arranged between the light receiving unit 10 and the logic unit 30 in the first direction X. According to this configuration, since the plurality of photodiodes 10A and the conversion unit 20 are adjacent to each other and the conversion unit 20 and the logic unit 30 are adjacent to each other, the light receiving unit 10, the conversion unit 20, and the logic unit 30 are the light receiving units 10. , The arrangement is similar to the electrical connection configuration of the conversion unit 20 and the logic unit 30. Therefore, the wiring pattern for connecting the plurality of photodiodes 10A and the conversion unit 20 and the wiring pattern for connecting the conversion unit 20 and the logic unit 30 are shortened, so that the generation of noise due to the wiring pattern can be reduced. .. Therefore, the optical sensor 1 can detect the illuminance with high accuracy.

(3) In a plan view, the analog / digital conversion circuits 21 to 24 are arranged in the second direction Y. According to this configuration, the chip 3 can be miniaturized in the first direction X as compared with the configuration in which at least one of the analog / digital conversion circuits 21 to 24 is arranged in the first direction X.

(4) In a plan view, the conversion unit 20 is arranged closer to the light receiving unit 10 than the logic unit 30 in the first direction X. According to this configuration, since a space is formed between the conversion unit 20 and the logic unit 30 in the first direction X, a circuit element such as a clock oscillation circuit can be formed in the space. Further, the wiring pattern for connecting the plurality of photodiodes 10A and the conversion unit 20 can be further shortened.

(5) In the first direction X, the size of the region R1 in which the plurality of photodiodes 10A are arranged is the size of the region R2 in which the conversion unit 20 is formed and the size of the region R3 in which the logic unit 30 is formed. Greater than each of them. According to this configuration, the number of photodiodes that can be arranged in the region R1 is larger than that in the case where the size of the region R1 is smaller than the size of the regions R2 and R3 in the first direction X. Therefore, the accuracy of detecting the illuminance by the optical sensor 1 can be improved.

(6) The plurality of electrode pads 61 to 69 of the chip 3 are formed in a region not overlapping the plurality of photodiodes 10A when viewed from the second direction Y. According to this configuration, the region R1 in which the plurality of photodiodes 10A are arranged can be increased in the first direction X. Therefore, the number of arrayable photodiodes in the region R1 can be increased.

(7) The plurality of electrode pads 61 to 69 are arranged so as to overlap the region R1 in which the plurality of photodiodes 10A are arranged when viewed from the first direction X. In other words, the region R1 extends to a position overlapping the plurality of electrode pads 61 to 69 in the second direction Y. Therefore, the number of arrayable photodiodes in the region R1 can be increased.

(8) The plurality of electrode pads 61 to 69 are arranged so as to overlap the logic unit 30 or the conversion unit 20 when viewed from the second direction Y. According to this configuration, the chip 3 can be miniaturized in the first direction X.

(9) The plurality of electrode pads 61 to 69 are arranged on both sides of the logic portion 30 in the second direction Y. According to this configuration, it is possible to secure the arrangement space of the plurality of electrode pads 61 to 69, and it is possible to suppress the chip 3 from becoming large in the first direction X.

(10) The plurality of electrode pads 61 to 69 are arranged only on one side of the conversion unit 20 in the second direction Y. According to this configuration, a circuit such as a voltage generation unit 40 can be formed in a space on the other side of the second direction Y (the third side surface 3c side of the chip 3) with respect to the conversion unit 20 of the chip 3.

(11) The plurality of photodiodes 10A are arranged in two rows in the first direction X. According to this configuration, the light receiving unit 10 can be configured with the minimum number of rows capable of suppressing the variation in the output signal output by the optical sensor 1 depending on the light receiving direction of the photodiode 10A. Therefore, the size of the first direction X of the region R1 in which the plurality of photodiodes 10A are arranged can be reduced.

(12) The photodiode covered by the infrared transmission filter 10B in the plurality of photodiodes 10A and the photodiode covered by the infrared transmission filter 10B are adjacent to each other in the first direction X and are adjacent to each other in the second direction Y. Are arranged alternately in. According to this configuration, it is possible to suppress that the output signal output by the optical sensor 1 varies depending on the direction in which the photodiode 10A receives light.

(13) The plurality of photodiodes 10A have a first photodiode group 11 having a first light receiving characteristic and a second photodiode group 12 having a second light receiving characteristic. According to this configuration, the illuminance can be detected based on the output signals of the diodes having different light receiving characteristics, so that the optical sensor 1 can detect the illuminance with high accuracy.

(14) The first photodiode group 11 has a sensitivity peak at a wavelength in the infrared region, and the second photodiode group 12 has a sensitivity peak at a wavelength in the visible light region. According to this configuration, it is possible to detect the illuminance according to the human visual sensitivity characteristic.

(15) Second photodiode groups 12 are arranged on both sides of the first photodiode group 11 in the second direction Y. According to this configuration, it is possible to suppress variations in the output signal output by the optical sensor 1 depending on whether light of the same light intensity is received from one side of the second direction Y or from the other side of the second direction Y. ..

(16) The number of photodiodes in the second photodiode group 12 arranged on one side of the first photodiode group 11 in the second direction Y is larger than the number of photodiodes in the first photodiode group 11. According to this configuration, more light receiving information in the visible light region can be acquired, so that the optical sensor 1 can detect the illuminance with high accuracy.

(17) The number of photodiodes of the second photodiode group 12 arranged on one side of the first photodiode group 11 in the second direction Y is arranged on the other side of the first photodiode group 11 in the second direction Y. It is equal to the number of photodiodes in the second photodiode group 12 obtained. According to this configuration, it is possible to suppress variations in the output signal output by the optical sensor 1 depending on whether light of the same light intensity is received from one side of the second direction Y or from the other side of the second direction Y. ..

(18) The chip 3 has a second side surface 5b which is one side of the side surfaces 5b and 5d of the sealing resin 5 in the first direction X with respect to the sealing resin 5. It is arranged so as to be biased toward the side). According to this configuration, the light receiving portion 10 of the chip 3 can be arranged on one side of the first direction X of the sealing resin 5, and the second side surface 5b of the sealing resin 5 and the second side surface 3b of the chip 3 The distance W1 between them can be reduced. In addition, by combining the configuration of the light receiving unit 10 described in (1) above, the total distance W8 (see FIG. 13B) of the distance W1 and the distance W7 can be reduced, so that a plurality of distances W8 can be reduced in the first direction X. The photodiode 10A of the above can be arranged near the second side surface 5b of the sealing resin 5. Therefore, even if the optical window 105 is arranged near the edge 101a of the smartphone 100, the plurality of photodiodes 10A can more preferably receive light from the optical window 105.

(19) The plurality of external terminals 2 are arranged on both sides of the chip 3 in the second direction Y. According to this configuration, the distance between the adjacent external terminals 2 can be secured in the plurality of external terminals 2, and the optical sensor 1 can be miniaturized in the first direction X.

(20) In a plan view, the area of the heat radiating plate 4 is larger than the area of the chip 3. According to this configuration, when the chip 3 generates heat, heat can be suitably radiated from the chip 3 to the heat radiating plate 4. Further, the heat radiating plate 4 can be suitably radiated from the chip 3 to the outside of the optical sensor 1 when the chip 3 generates heat by being exposed from the sealing resin 5.

(Change example)
The above-described embodiment is an example of possible embodiments of the optical sensor according to the present disclosure, and is not intended to limit the embodiments. The optical sensor according to the present disclosure may take a form different from the form exemplified in the above embodiment. An example thereof is a form in which a part of the configuration of the above embodiment is replaced, changed, or omitted, or a new configuration is added to the above embodiment. In the following modification examples, the parts common to the above-described embodiment are designated by the same reference numerals as those in the above-described embodiment, and the description thereof will be omitted.

-In the above embodiment, the shape of the sealing resin in the plan view is a rectangle in which the first direction X is the short side direction and the second direction Y is the long side direction, but the sealing is not limited to this. The shape of the stop resin 5 can be changed arbitrarily. In one example, the shape of the sealing resin in a plan view is a rectangle in which the first direction X is the long side direction and the second direction Y is the short side direction.

-In the above embodiment, the number of photodiodes per row along the second direction Y of the light receiving unit 10 can be arbitrarily changed. The number of photodiodes per row may be 3 or more. In one example, the number of photodiodes per row along the second direction Y is 10.

-In the above embodiment, the shape of the region R1 in which the plurality of photodiodes 10A are arranged is rectangular in a plan view, but the shape is not limited to this. For example, as a configuration of a plurality of photodiodes 10A having a region R1 having a shape other than a rectangular shape, the photodiodes per row may be configured to be different from each other. In one example, as shown in FIG. 14A, the photodiodes PD17 and PD18 may be added to the rows of the photodiodes PD1 to PD8 and PD9 to PD16. Further, as shown in FIG. 14B, the photodiode PD17 may be arranged so as to overlap the photodiode PD1 and the photodiode PD9 when viewed from the second direction Y. Similar to the photodiode PD17 in FIG. 14B, the photodiode PD18 may be arranged so as to overlap the photodiode PD8 and the photodiode PD16 when viewed from the second direction Y. In FIG. 14A, the photodiodes PD17 and PD18 are not covered by the infrared transmission filter 10B, but are not limited to this, and at least one of the photodiodes PD17 and PD18 is covered by the infrared transmission filter 10B. May be good. Further, in the plurality of photodiodes 10A shown in FIG. 14A, one of the photodiodes PD17 and PD18 may be omitted.

-In the above embodiment, the arrangement mode of the infrared transmission filter 10B with respect to the plurality of photodiodes 10A can be arbitrarily changed. In one example, as shown in FIG. 15, the infrared transmission filter 10B covers the photodiodes PD2, PD4, PD6, PD8, PD9, PD11, PD13, PD15, and the photodiodes PD1, PD3, PD5, PD7, PD10, PD12. , PD14 may be arranged so as not to cover it.

-In the above embodiment, when the number of photodiodes per row is 10, the arrangement mode of the infrared transmission filter 10B may be changed as follows.
As shown in FIG. 16, the plurality of photodiodes 10A include photodiodes PD1 to PD20. In the photodiode 10A, ten photodiodes arranged in the second direction Y are arranged in two rows in the first direction X. In FIG. 16, the photodiodes PD1 to PD10 form the first row of photodiodes, and the photodiodes PD11 to PD20 form the second row of photodiodes. In the first direction X, the photodiodes PD1 to PD10 are arranged on the second side surface 3b side of the chip 3 with respect to the photodiodes PD11 to PD20. The photodiodes PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, and PD10 are arranged in this order from the third side surface 3c of the chip 3 in the second direction Y toward the first side surface 3a. The photodiodes PD11, PD12, PD13, PD14, PD15, PD16, PD17, PD18, PD19, and PD20 are arranged in this order from the third side surface 3c of the chip 3 in the second direction Y toward the first side surface 3a.

The photodiodes PD1 to PD20 are divided into a first photodiode group 11 and a second photodiode group 12. The first photodiode group 11 is composed of photodiodes PD5, PD6, PD15, and PD16. The second photodiode group 12 is composed of photodiodes PD1 to PD4, PD7 to PD10, PD11 to PD14, and PD17 to PD20. As shown in FIG. 16, in a plan view, the second photodiode group 12 is arranged on both sides of the first photodiode group 11 in the second direction Y. The second photodiode group 12 including the photodiodes PD1 to PD4 and PD11 to PD14 is arranged on the third side surface 3c side of the chip 3 with respect to the first photodiode group 11. The second photodiode group 12 composed of the photodiodes PD7 to PD10 and PD17 to PD20 is arranged on the first side surface 3a side of the chip 3 with respect to the first photodiode group 11.

The infrared transmission filter 10B covers the photodiodes PD1, PD2, PD5, PD7, and PD8 of the photodiodes PD1 to PD10. Further, the infrared transmission filter 10B covers the photodiodes PD13, PD14, PD16, PD19, and PD20 among the photodiodes PD11 to PD20. As described above, in the first photodiode group 11, in the first direction X, the photodiode covered with the infrared transmission filter 10B and the photodiode not covered with the infrared transmission filter 10B are arranged so as to be adjacent to each other. Has been done. Further, in the second direction Y, the photodiodes covered with the infrared transmission filter 10B and the photodiodes not covered with the infrared transmission filter 10B are alternately arranged. In the second photodiode group 12, in the first direction X, the photodiode covered with the infrared transmission filter 10B and the photodiode not covered with the infrared transmission filter 10B are arranged so as to be adjacent to each other. Further, in the second direction Y, two photodiodes covered with the infrared transmission filter 10B and two photodiodes not covered with the infrared transmission filter 10B are alternately arranged.

-In the above embodiment, the positions of the light receiving unit 10, the conversion unit 20, and the logic unit 30 in the second direction Y can be arbitrarily changed. The position of the second direction Y of the center line LA extending in the first direction X at the center of the second direction Y of the light receiving unit 10 is the second of the center line LB2 extending in the first direction X at the center of the second direction Y of the conversion unit 20. It may be different from the position in the two directions Y. The position of the center line LA in the second direction Y may be different from the position of the center line LC2 extending in the first direction X at the center of the second direction Y of the logic unit 30 in the second direction Y. The position of the center line LB2 in the second direction Y may be different from the position of the center line LC2 in the second direction Y.

-In the above embodiment, the position of the chip 3 with respect to the sealing resin 5 in the second direction Y can be arbitrarily changed. The center line L12 extending in the first direction X at the center of the second direction Y of the chip 3 is the first of the sealing resin 5 than the center line L22 extending in the first direction X at the center of the second direction Y of the sealing resin 5. The chip 3 may be arranged so as to be located on the side surface 5a side or the third side surface 5c side.

-In the above embodiment, the electrode pad 61 may be arranged on the 4th side surface 3d side of the chip 3 with respect to the conversion unit 20 in the first direction X. In one example, the electrode pad 61 is arranged at a position that does not overlap with the conversion unit 20 and overlaps with the logic unit 30 when viewed from the second direction Y.

-In the above embodiment, at least one of the plurality of electrode pads 61 to 69 may be arranged in the region between the logic unit 30 and the fourth side surface 3d of the chip 3 in the chip 3.
-In the above embodiment, the shape of the heat radiating plate 4 can be arbitrarily changed. In one example, as shown in FIG. 17, the size of the first direction X of the heat radiating plate 4 in a plan view may be equal to the size of the first direction X of the chip 3. Here, the size of the first direction X of the heat radiating plate 4 is equal to the size of the first direction X of the chip 3 is the size of the first direction X of the heat radiating plate 4 and the size of the first direction X of the chip 3. The difference is within 5% of the size of the first direction X of the heat radiating plate 4. In this case, the heat radiating plate 4 is biased to one side of the first direction X from the center of the sealing resin 5, that is, to the second side surface 5b side of the sealing resin 5 from the center of the sealing resin 5 in the first direction X. Is arranged.

1 ... Optical sensor 2 ... External terminal 3 ... Chip 3b ... Second side surface (both sides in the first direction, one side surface)
3d ... 4th side surface (both sides in the 1st direction)
4 ... Heat dissipation plate 5 ... Encapsulating resin 6A to 6E ... Conductive wire 10 ... Light receiving part 10A ... Multiple photodiodes 10B ... Infrared transmission filters PD1 to PD20 ... Photodiodes 11 ... First photodiode group 12 ... Second photodiodes Group 14 ... Light receiving surface 20 ... Conversion unit 21 to 24 ... Analog / digital conversion circuit 30 ... Logic unit 61 to 69 ... Electrode pad 100 ... Smartphone (electronic device)
101 ... Housing R1 ... Area where a plurality of photodiodes are arranged R2 ... Area where a conversion unit is formed R3 ... Area where a logic unit is formed X ... First direction Y ... First direction

Claims (24)

An optical sensor with a chip having multiple photodiodes.
The plurality of photodiodes are arranged so as to be biased toward one side of the first direction from the center of the chip when viewed from the light receiving direction of the photodiode, and the first direction is the lateral direction and the first direction is the short direction. Optical sensors arranged in an elongated shape with the second direction orthogonal to the direction as the longitudinal direction. The chip is formed in a rectangular plate shape with the first direction as the longitudinal direction and the second direction as the lateral direction.
The chip has one side surface arranged on one side of both side surfaces in the first direction.
The optical sensor according to claim 1, wherein the plurality of photodiodes are arranged closer to the one side surface than the center of the chip. The chip is
A conversion unit that converts the photocurrent that flows when the photodiode receives light into an output signal,
The logic unit that controls the conversion unit and
Have more
The plurality of photodiodes, the conversion unit, and the logic unit are arranged in the first direction.
The optical sensor according to claim 1 or 2, wherein the conversion unit is arranged between the plurality of photodiodes and the logic unit in the first direction. The conversion unit has a plurality of analog / digital conversion circuits.
The optical sensor according to claim 3, wherein the plurality of analog / digital conversion circuits are arranged in the second direction. The optical sensor according to claim 3 or 4, wherein the conversion unit is arranged closer to the plurality of photodiodes than the logic unit in the first direction. In the second direction, the size of the region where the plurality of photodiodes are arranged is larger than the size of the region where the conversion unit is formed and the size of the region where the logic unit is formed. Item 3. The optical sensor according to any one of Items 3 to 5. The chip further comprises a plurality of electrode pads.
The optical sensor according to any one of claims 3 to 6, wherein the plurality of electrode pads are formed in a region of the chip that does not overlap with the plurality of photodiodes when viewed from the second direction. The optical sensor according to claim 7, wherein at least one of the plurality of electrode pads is arranged so as to overlap a region in which the plurality of photodiodes are arranged when viewed from the first direction. The optical sensor according to claim 7 or 8, wherein the plurality of electrode pads are arranged so as to overlap the logic unit or the conversion unit when viewed from the second direction. The optical sensor according to claim 9, wherein the plurality of electrode pads are arranged on both sides of the logic portion in the second direction. The optical sensor according to claim 9 or 10, wherein the plurality of electrode pads are arranged only on one side of the conversion unit in the second direction. The optical sensor according to any one of claims 1 to 11, wherein the plurality of photodiodes are arranged in two rows in the first direction. The optical sensor according to claim 12, wherein three or more of the plurality of photodiodes are arranged in one row in the second direction. The optical sensor has an infrared transmission filter that covers each light receiving surface of some of the photodiodes among the plurality of photodiodes.
Claims that the photodiode covered with the infrared transmission filter and the photodiode not covered with the infrared transmission filter are adjacent to each other in the first direction and alternately arranged in the second direction. Item 13. The optical sensor according to item 13. Any one of claims 1 to 14, wherein the plurality of photodiodes have a first photodiode group having a first light receiving characteristic and a second photodiode group having a second light receiving characteristic different from the first light receiving characteristic. The optical sensor according to one item. The first light receiving characteristic has a sensitivity peak in the infrared region and has a sensitivity peak.
The optical sensor according to claim 15, wherein the second light receiving characteristic has a sensitivity peak in the visible light region. The optical sensor according to claim 16, wherein the second photodiode group is arranged on both sides of the first photodiode group in the second direction. The number of photodiodes of the second photodiode group arranged on one side of the second direction of the first photodiode group is larger than the number of photodiodes of the first photodiode group. Optical sensor. The number of the second photodiode group arranged on one side of the second direction of the first photodiode group is the number of the second photo arranged on the other side of the second direction of the first photodiode group. The optical sensor according to claim 18, which is equal to the number of diode groups. The optical sensor is
The sealing resin that seals the chip and
A plurality of external terminals electrically connected to the chip and exposed from the sealing resin,
With more
The optical sensor according to any one of claims 1 to 19, wherein the chip is arranged so as to be biased to one side in the first direction with respect to the sealing resin. The plurality of external terminals are arranged on both sides of the chip in the second direction.
The optical sensor according to claim 20, wherein the plurality of external terminals and the chip are connected by a conductive wire. The optical sensor further comprises a heat radiating plate to which the chip is attached.
The optical sensor according to any one of claims 1 to 21, wherein the area of the heat radiating plate is larger than the area of the chip. The optical sensor according to claim 22, wherein the chip is arranged so as to be biased to one side in the first direction with respect to the heat radiating plate. The optical sensor according to any one of claims 1 to 23,
A housing that houses the optical sensor and
Electronic equipment equipped with.