JP2020150001A - Light receiving circuit, light receiving element, and apd array device - Google Patents

Abstract

To multiply an incident light signal an avalanche multiplier layer, and secure an appropriate multiplication factor of, for example, about 100 to 200 times.SOLUTION: A light receiving circuit includes an APD, and a temperature sensor BGR circuit that detects the temperature using a BGR circuit and changes and outputs a cathode bias voltage of the APD on the basis of the detected temperature. The APD has a guard ring region between a Pwell layer in an anode region and a Nwell layer in a cathode region, which is provided with an impurity concentration portion of a semiconductor substrate on the wafer surface side of a Deep Nwell layer conducting with the Nwell layer, and in the APD, the impurity concentration of the Pwell layer is higher than the impurity concentration of the Deep Nwell layer in order to make a breakdown voltage between the Pwell layer and the Nwell layer formed through the guard ring region higher than the breakdown voltage in an avalanche multiplier layer between the Pwell layer and the Deep Nwell layer.SELECTED DRAWING: Figure 3C

Description

The present invention relates to a light receiving circuit including an avalanche photodiode (hereinafter referred to as APD), a light receiving element used in the light receiving circuit, and an APD array device used in the light receiving circuit.

An avalanche photodiode (APD) is already known as a device that can obtain sufficient signal strength due to the avalanche multiplier effect even if the received signal is weak (see, for example, Patent Document 1).

Japanese Patent No. 6260917

However, in the conventional APD, since the electrodes are formed on both the front and back surfaces of the chip, it is difficult to make one chip by using a general CMOS process in which the electrodes are formed only on the wafer surface side. On the other hand, there is a special process in which chips are laminated and electrodes on both the front and back sides can be used, but the manufacturing cost is high and it is difficult to apply as compared with a general CMOS process.

Therefore, if the electrodes formed on the back surface are formed on the front surface side and incorporated in the IC by using the CMOS process and integrated into one chip with the peripheral control circuit, there are the following problems.
(1) The withstand voltage in the wafer surface direction is low, and the avalanche breakdown occurs in the wafer surface direction before the avalanche breakdown occurs in the wafer depth direction, which is the original avalanche multiplier layer. This is called "edge breakdown".
(2) Therefore, since the cathode bias voltage cannot be increased, the incident light signal cannot be multiplied by the avalanche multiplier layer, and an appropriate multiplication factor of about 100 to 200 times cannot be secured.

An object of the present invention is to solve the above problems and to provide a light receiving circuit capable of multiplying an incident light signal by an avalanche multiplier layer and ensuring an appropriate magnification of, for example, about 100 to 200 times.

The light receiving circuit according to the present invention is
An avalanche photodiode (APD) having an avalanche multiplier having N-type or P-type impurities in the PN junction layer and outputting a photoelectric conversion current,
A light receiving circuit including a temperature sensor BGR circuit that detects a temperature using a bandgap reference circuit (BGR circuit) and changes and outputs the cathode bias voltage of the APD based on the detected temperature.
The APD is a guard ring provided with an impurity concentration portion of a semiconductor substrate between the Pwell layer in the anode region and the Nwell layer in the cathode region on the wafer surface side of the Deep Nwell layer conducting with the Nwell layer in the cathode region. Has an area and
In the APD, the breakdown voltage between the Pwell layer in the anode region and the Nwell layer in the cathode region, which is formed via the guard ring region, is set between the Pwell layer in the anode region and the Deep Nwell layer in the cathode region. In order to make it higher than the breakdown voltage in the avalanche multiplier layer, the impurity concentration of the Pwell layer in the anode region is higher than the impurity concentration of the Deep Nwell layer in the cathode region.

Therefore, according to the present invention, it is possible to provide a light receiving circuit capable of multiplying an incident light signal by an avalanche multiplying layer and ensuring an appropriate multiplication factor of, for example, about 100 to 200 times.

It is a block diagram which shows the structural example of the light receiving circuit which concerns on embodiment. It is a graph which shows the temperature characteristic of the cathode bias voltage of APD when the multiplication factor is controlled to be constant. It is a graph which shows the temperature characteristic of the multiplication factor of APD when the cathode bias voltage is controlled to be constant. (A) is a plan view of APD according to a conventional example, and (b) is a vertical sectional view along AA'of (a). (A) is a plan view of APD according to a comparative example, and (b) is a vertical cross-sectional view along BB'of (a). (A) is a plan view of the APD according to the embodiment, and (b) is a vertical sectional view along CC'of (a). It is a flowchart which shows the wafer test process including the cathode bias control operation which concerns on embodiment. It is a block diagram which shows the structural example of the light receiving circuit which concerns on the modification. It is a top view which shows the line sensor apparatus which was configured with the plurality of APD30s of FIG. 3C. It is a top view which shows the area sensor apparatus which was configured with the plurality of APD30s of FIG. 3C. It is a block diagram which shows the structural example of the distance measuring apparatus 100 which used the ToF sensor apparatus for LiDAR use which used the APD array apparatus which arranged APD30 in one dimension.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. The same or similar components are designated by the same reference numerals.

(Embodiment)
This embodiment is miniaturized when the APD30, which will be described later with reference to FIG. 3A, is built into the IC, the electrodes 51 and 52 are formed only on the wafer surface side, and the peripheral control circuit is integrated into one chip. At the same time, a guard ring region 53 is provided between the Pwell layer 43 of the anode region 51A and the Nwell layer 47 of the cathode region 52A on the wafer surface side of the Deep Nwell layer 46 so as to suppress edge breakdown. By forming the avalanche multiplier layer 48 with a gradient of impurity concentration, a structure that causes avalanche breakdown in the wafer depth direction is formed. Therefore, the incident light signal can be multiplied by the avalanche multiplication layer 48, and an appropriate multiplication factor of, for example, about 100 to 200 times can be secured. Hereinafter, the present embodiment will be described in detail.

FIG. 1 is a block diagram showing a configuration example of a light receiving circuit according to an embodiment.

In FIG. 1, the light receiving circuit integrated into one chip using the CMOS process includes an APD 30, a temperature sensor bandgap reference circuit (hereinafter referred to as a temperature sensor BGR circuit) 32, and a cathode bias control circuit 31 having a memory of 31 m. It is composed of. Here, one chip means that each component is built on one Si wafer. Further, the APD 30 according to the present embodiment has a function of receiving a weak light and generating a signal of a photoelectric conversion current.

The temperature sensor BGR circuit 32 is a known BGR circuit including a bipolar transistor. The temperature sensor BGR circuit 32 measures the temperature of the APD 30 and outputs a temperature detection signal indicating the measured temperature to the cathode bias control circuit 31. In response to this, the cathode bias control circuit 31 controls the cathode bias voltage Vcb supplied to the APD 30 according to the temperature indicated by the temperature detection signal. Therefore, when the light is input to the APD 30, a current corresponding to the input light is output as a signal So of the photoelectric conversion current from the light receiving circuit integrated into one chip.

FIG. 2A is a graph showing the temperature characteristics of the cathode bias voltage of the APD when the multiplication factor is controlled to be constant. Further, FIG. 2B is a graph showing the temperature characteristics of the APD multiplication factor when the cathode bias voltage Vcb is controlled to be constant.

Since the amplification factor of the APD30 varies greatly depending on the temperature, it is necessary to control the cathode bias voltage Vcb. Here, the cathode bias control circuit 31 includes an operational amplifier, controls the cathode bias voltage Vcb according to the temperature detection signal from the temperature sensor BGR circuit 32, and outputs it to the APD 30. Since the temperature sensor BGR circuit 32 is built in one chip with the APD 30 using a CMOS process, it can be built on the Si semiconductor substrate in the immediate vicinity of the APD 30, and the temperature of the APD 30 can be detected more accurately.

FIG. 2A shows the temperature characteristics of the cathode bias voltage Vcb of the APD 30 when the multiplication factor M is controlled to be constant (M = 100). As is clear from FIG. 2A, the breakdown voltage Vbd of the APD30 is temperature-dependent, and when operated in the linear mode (reverse bias application below the breakdown voltage), the cathode bias voltage Vcb is the breakdown voltage Vbd. Must be controlled so that it does not exceed. The breakdown voltage Vbd is a voltage at which the APD 30 causes an avalanche breakdown, and is in a direct proportional relationship with the temperature.

When the cathode bias voltage Vcb is applied in excess of the breakdown voltage Vbd, the avalanche multiplication factor of the APD 30 becomes large to a value of tens of thousands to hundreds of thousands. Theoretically, the multiplication factor becomes infinitely large, but in reality, it settles down to a finite value because of the presence of parasitic components in the wiring part. For example, when the APD30 is used as an indirect ToF sensor device, the distance is calculated using the amount of received signal, so if the multiplication factor becomes a value of tens of thousands to hundreds of thousands, the exact amount of received charge cannot be known. , Cannot be used to calculate distance.

FIG. 2B shows the temperature characteristics of the multiplication factor of APD30 when the cathode bias voltage Vcb is controlled to be constant. In the present embodiment, the breakdown voltage Vbd of the APD30 created by the CMOS process has a temperature coefficient of 8.7 mV / ° C in the case of FIG. 2B. Therefore, unless the cathode bias control is performed accurately, FIG. 2B As shown in, the breakdown voltage Vbd is reached, and the multiplication factor becomes tens of thousands to hundreds of thousands.

As shown in FIG. 2B, when the cathode bias voltage Vcb is 12.3 V, the breakdown voltage is Vbd or less in the temperature range of 20 to 100 ° C. Therefore, the multiplication factor does not change drastically, but it becomes 12.5 V. Then, in the temperature range of 50 ° C. or less, the multiplication factor becomes infinitely large.

3A (a) is a plan view of the APD according to the conventional example, FIG. 3A (b) is a vertical sectional view taken along the line AA'of FIG. 3A (a), and FIGS. 3A (a) and 3A are shown. (B) is collectively referred to as FIG. 3A.

In FIG. 3A, the N + semiconductor layer 44, which is a cathode region, is formed on the front surface side of the chip, and the N + semiconductor layer 44 is electrically connected to the cathode electrode 52, while the P + semiconductor, which is an anode region, is on the back surface side of the chip. A layer 41 is formed, and the P + semiconductor layer 41 is electrically connected to the anode electrode 51. A high voltage of several hundred V is applied between the anode electrode 51 and the cathode electrode 52 in order to cause avalanche multiplication. An electric field is formed from the front surface side to the back surface side of the chip, the photoelectric conversion signal due to the incident light is multiplied by the avalanche, and a signal current is generated from the cathode electrode 52 to the anode electrode 51. Reference numeral 42 denotes a P-type semiconductor layer, and 45 is an STI (Shallow Trench Isolation) structural part that separates elements.

In the conventional example of FIG. 3A, since the P + semiconductor layer 41 and the N + semiconductor layer 44 for connecting to both electrodes 51 and 52 are formed on both the front and back surfaces of the chip, it is difficult to make one chip using the CMOS process. , APD30 only is provided as a packaged discrete component. On the other hand, there is a special process in which chips are laminated and semiconductor layers for electrodes on both the front and back surfaces can be used, but the manufacturing cost is high and it is difficult to apply as compared with a general CMOS process.

FIG. 3B (a) is a plan view of an APD according to a comparative example in which electrodes 51 and 52 are arranged on the surface side using a CMOS process, and FIG. 3B (b) is shown in FIG. 3B (a) BB'. It is a vertical sectional view along the line, and FIGS. 3B (a) and 3B (b) are collectively referred to as FIG. 3B.

In FIG. 3B, a Deep Nwell layer 46 in the cathode region is formed on the deeper side of the wafer surface of the Pwell layer 43 in the anode region, and the Deep Nwell layer 46 is a wafer via the Nwell layer 47 and the N + semiconductor layer 44 in the cathode region. It is electrically connected to the cathode electrode 52 on the front surface side. With such a structure, the semiconductor layers 54 and 44 for both the anode electrode 51 and the cathode electrode 52 can be arranged on the wafer surface side, so that the manufacturing flow of the CMOS process can be applied and the peripheral circuit can be applied. It is possible to make one chip with. However, in this structure, the boundary between the Pwell layer 43 in the anode region and the Nwell layer 47 in the cathode region exists on the wafer surface side, and the wafer surface side has many crystal defects, so that the withstand voltage is low, and the anode electrode 51 and the cathode There was a possibility that the electrodes 52 would break down through the path on the wafer surface.

3C (a) is a plan view of the APD30 according to the embodiment, FIG. 3C (b) is a vertical cross-sectional view taken along the line CC'of FIG. 3C (a), and FIGS. 3C (a) and 3C (B) is collectively referred to as FIG. 3C.

In FIG. 3C, the APD30 according to the present embodiment is
(1) The N + semiconductor layer 44, which is a cathode region and is electrically connected to the cathode electrode 52,
(2) A P + semiconductor layer 54, which is an anode layer and is electrically connected to the anode electrode 51,
(3) A guard ring region 53 having a DTI (Deep Trench Insolation) structure, and
(4) It has an avalanche multiplier layer 48 formed between the Deep Nwell layer 46 and the Pwell layer 43, and these are characterized in that they are formed as follows.

The APD 30 is configured to include an avalanche multiplier 48 having N-type or P-type impurities in the PN junction layer. Further, since the avalanche multiplier layer 48 is provided deep from the surface of the Pwell layer 43, it is not shown in FIG. 3C (a), which is a plan view.

The cathode region 52A includes a Deep Nwell layer 46 and a Nwell layer 47 in order from the deepest side of the surface of the P-type semiconductor substrate 40, and the Nwell layer 47 is electrically connected to the cathode electrode 52 via the N + semiconductor layer 44. Is connected. Here, the cathode electrode 52 is formed in a ring shape so as to surround the anode electrode 51 and the guard ring region 53. Here, the Deep Nwell layer 46 is formed so as to cover the entire APD 30, and is in contact with the P + semiconductor layer 54, which is the anode region 51A, via the avalanche multiplier layer 48 and the Pwell layer 43.

The anode region 51A includes a Pwell layer 43 and a P + semiconductor layer 54, and is a Pwell layer via a Deep Nwell layer 46 and an avalanche multiplier layer 48 in order from the deepest side of the surface of the P-type semiconductor substrate 40. 43 is formed. The Pwell layer 43 is electrically connected to the anode electrode 51 via the P + semiconductor layer 54 at the center of the APD 30.

Since a high voltage of several tens of volts is applied between the anode electrode 51 and the cathode electrode 52, as shown in FIG. 3B according to the comparative example, the Pwell layer 43 and the cathode region 52A of the anode region 51A where the electric field is easily concentrated. Edge breakdown is more likely to occur between the Nwell layers 47 than the Deep Nwell layer 46 via the layer on the surface of the wafer. If an edge breakdown occurs, a predetermined voltage is not applied to the original avalanche multiplier 48, so that the APD30 cannot perform the operation of detecting weak light.

Therefore, as shown in FIG. 3C, a guard ring region 53 is formed between the anode region 51A and the cathode region 52A to suppress edge breakdown. The guard ring region 53 is formed at the boundary between the anode region 51A and the cathode region 52A with a depth up to the Deep Nwell layer 46 and has a so-called DTI structure portion, and is composed of a dimension having a constant width without a break. ..

Further, ion implantation and impurity diffusion are not performed at all in the guard ring region 53 in the chip manufacturing process, and the guard ring region 53 becomes a structural part of the impurity concentration in the P-type semiconductor substrate 40. Here, the impurity concentration of the P-type semiconductor substrate 40 is, for example, 7 × 10 ¹⁴ [cm ^-3 ]. Therefore, the P-type semiconductor substrate 40 is a high-resistance Si substrate, and the voltage that breaks down when a high voltage is applied between the anode electrode 51 and the cathode electrode 52 is higher than the breakdown voltage in the avalanche multiplier 48. can do. Further, a DTI structure can be formed in the center of the guard ring region 53, for example, with a width of 0.5 um to increase the breakdown voltage.

As described above, at the boundary between the anode region 51A and the cathode region 52A, a guard ring region 53 is formed near the wafer surface from the Deep Nwell layer 46 between the Pwell layer of the anode region 51A and the Nwell layer of the cathode region 52A. There is. Therefore, the avalanche multiplier 48 illustrated in the cross-sectional view of FIG. 3C (b) has a structure that causes breakdown at a voltage lower than the voltage that causes edge breakdown in the guard ring region 53, and is weak light. The optical signal when the light is incident can be multiplied by the avalanche.

An avalanche multiplier layer 48 is formed between the Pwell layer 43 in the anode region 51A and the Deep Nwell layer 46 in the cathode region 52A, and is formed by, for example, the following impurity injection step.
(1) Boron injection: injection energy = 180 keV; injection tilt angle = 0 °; injection amount = 1.1 × 10 ¹² cm- ² ;
(2) Phosphorus injection: injection energy = 140 keV; injection tilt angle = 7 °; injection amount = 3.0 × 10 ¹² cm- ² .

In addition, the diffusion conditions of the Avalanche multiplier layer 48 are
(1) is 60 minutes of well drive step at ^{N 2} atmosphere at 1180 ° C,
(2) Finally, the impurity concentration should be set within the range of 1 × 10 ¹⁵ to 1 × 10 ¹⁷ [cm ^-3 ] so that the impurity concentration in the anode region 51A is at least twice as high as the impurity concentration in the cathode region 52A. Is.

Here, when the impurity concentration is not more than the lower limit value, the breakdown voltage Vbd becomes high, but the avalanche multiplication between the Pwell layer 43 and the Deep Nwell layer 46 cannot occur. That is, it works as a light receiving element, but does not amplify it. On the other hand, when the impurity concentration of the avalanche multiplier layer 48 is equal to or higher than the upper limit value, the breakdown voltage Vbd becomes low, but an appropriate value such as 100 to 200 times cannot be secured. That is, the voltage applied up to the breakdown voltage Vbd does not multiply, and when the breakdown voltage Vbd is exceeded, the multiplication factor becomes a value of tens of thousands to hundreds of thousands.

In this way, by combining the impurity species to be injected into the avalanche multiplier layer 48 and the injection amount, the impurity concentration profile between the Pwell layer 43 and the Deep Nwell layer 46 has an impurity concentration gradient, so that a higher voltage breakdown can be achieved. realizable.

FIG. 4 is a flowchart showing a wafer test process including the cathode bias control operation according to the embodiment.

Hereinafter, the cathode bias control operation will be described with reference to FIG. In each light receiving circuit chip, the performance of the electrical characteristics of the APD 30 is different, and variations occur. Therefore, it is necessary to correct the temperature characteristics. For example, as shown below, correction is performed in the wafer test process of FIG. 4 after the chip making step.

In step S1 of FIG. 4, the multiplication factor M of APD30 is determined at room temperature. That is, it is determined at what amplification factor the APD30 is used. Then, the cathode bias voltage Vcb at room temperature is measured. Next, in step S2, the temperature characteristics of the cathode bias voltage Vcb of the APD30 of each chip are measured. The temperature is changed to four points, for example, normal temperature (25 ° C), 50 ° C, 75 ° C, and 100 ° C, and the cathode bias voltage Vcb at which the multiplication factor M is determined in step S1 is measured, and the memory is 31 m. Store it in the table inside.

Next, in step S3, the temperature coefficient of the cathode bias voltage Vcb of the APD30 of each chip is calculated. The temperature coefficient is calculated using the temperature of the table prepared in step S2 and the value of the cathode bias voltage Vcb, for example, 8.7 mV / ° C, and stored in the memory 31 m. Next, in step S4, the circuit constant of the temperature sensor BGR circuit 32 is changed so as to be the same as the temperature coefficient of the cathode bias voltage Vcb.

Next, in step S5, the temperature characteristic of the output voltage of the cathode bias control circuit 31 is measured. Similar to steps S2 and S3, the output voltage of the cathode bias control circuit 31 is measured by changing the temperature, stored in a table in the memory 31 m, and the temperature coefficient is calculated from those values. If the temperature coefficient value is the same as the value stored in the memory 31m in step S3, the process is OK and the process is terminated as it is. If they are different, a failure is displayed in step S6 as NG, and the process is terminated.

With the above configuration, even if the breakdown voltage Vbd of the APD 30 changes depending on the temperature, the cathode bias voltage Vcb can be increased accordingly, so that the multiplication factor of the APD 30 is maintained constant regardless of the temperature. can do.

FIG. 5 is a block diagram showing a configuration example of a light receiving circuit according to a modified example. The light receiving circuit of FIG. 5 is characterized in that an AD converter 33 is further provided after the APD 30 as compared with the light receiving circuit of FIG.

In FIG. 5, the light receiving circuit is a light receiving circuit integrated into one chip by using a CMOS process, and includes an APD 30, a temperature sensor BGR circuit 32, a cathode bias control circuit 31, and an AD converter 33. .. In this modification, the output signal current from the APD 30 can be input to the AD converter 33 and output as a digital signal Sod. Digitizing the signal in the chip has the effect of making it less susceptible to noise.

FIG. 6A is a plan view showing a line sensor device configured with the plurality of APD30s of FIG. 3C. Further, FIG. 6B is a plan view showing an area sensor device configured with the plurality of APD30s of FIG. 3C.

As shown in FIG. 6A, for example, by arranging 12 APD30s side by side in one dimension, the distribution of weak light in the one-dimensional direction can be seen. That is, it is possible to perform imaging of weak light in the one-dimensional direction. This sensor device is called a line sensor device.

Further, as shown in FIG. 6B, by arranging a plurality of APD30s in two dimensions, it is possible to see the distribution of weak light in two dimensions. This sensor device is called an area sensor device.

A temperature sensor BGR circuit 32 is arranged in the vicinity of each APD 30 so that the temperature can be measured with high accuracy. Further, since the temperature sensor BGR circuit 32 is smaller than the APD 30, the APD 30 and the temperature sensor BGR circuit 32 can be closely arranged.

FIG. 7 is a block diagram showing a configuration example of a distance measuring device 100 using a ToF (Time Of Flight) sensor for LiDAR applications using an APD array device in which the APD 30 is arranged one-dimensionally.

In FIG. 7, the distance measuring device 100 receives the light projecting unit 1 that projects the light from the light source, the light receiving unit 2 that receives the reflected light from the projected object, and the output signal from the light receiving unit 2. It includes an integrator 25 that integrates time, and a control circuit 3 that controls the light projecting unit 1 and measures a distance based on a reflected signal. In FIG. 7, the output of the light receiving unit 2 is connected to the input of the integrator 25, and the time-integrated reflected signal is input to the control circuit 3.

The light emitting unit 1 and the light receiving unit 2 are generally arranged in the front part of the vehicle so as to detect an object existing in front of the vehicle as a distance measuring device, but are arranged on the side or rear of the vehicle. It can be installed anywhere in the vehicle, such as when detecting an object. The light projecting unit 1 includes a light source 11, a coupling lens 13, an optical scanner 14, a light source drive circuit 16, an optical scanner drive circuit 17, and a scanning angle monitor 18.

In the light source 11, a plurality of light emitting element groups are arranged apart from each other in the light scanning direction. Each light emitting element group is formed by a plurality of surface emitting lasers (VCSEL). The light source 11 is connected to the control circuit 3 via the light source drive circuit 16, and the light emission timing of the light emitting element group is controlled independently of each other by the control circuit 3. The coupling lens 13 couples the laser light emitted from the light source 11 to the optical scanner (optical scanning unit) 14. The optical scanner 14 scans the laser beam output from the plurality of light emitting element groups of the light source 11 toward the same detection layer in the XZ plane. The beam deflection given by the optical scanner 14 detects an object existing in a predetermined angle range, and makes it possible to measure the distance to the detected object.

The scanning angle of the laser beam by the optical scanner 14 may be detected by the scanning angle monitor 18 and supplied to the control circuit 3. In this case, the monitor result is fed back to the optical scanner drive signal to control the scanning angle, scanning frequency, and the like. The light receiving unit 2 has a light receiving element 21 and a light receiving lens 22. The light receiving lens 22 couples the laser light reflected from an object existing in the beam scanning direction to the light receiving element 21. The light receiving element 21 is the APD array device shown in FIGS. 6A and 6B. Other optical elements such as a mirror may be arranged between the light receiving lens 22 and the light receiving element 21.

The light projecting unit 1 and the light receiving unit 2 are arranged close to each other, and the optical axes of the light emitting unit 1 and the light receiving unit 2 can be considered to be in a coaxial relationship from a position separated by several meters or more. The light reflected by the detection object is scattered in various directions at the reflection point, but the light component that returns by following an optical path equal to the laser light output from the distance measuring device 100 causes the light receiving lens 22. It is guided to the light receiving element 21 via the light receiving element 21 and detected as a reflected signal.

The light receiving element 21 outputs a photoelectric conversion current corresponding to the intensity of the input reflected light. The photoelectric conversion current output from the light receiving element 21 is converted into a voltage signal by a transimpedance amplifier (not shown), amplified by the amplifier 23, and then input to the integrator 25. The integrator 25 is output from a plurality of light emitting element groups at different light emission timings in one scan, integrates the detection signals reflected from the object, and outputs the total value of the detection signals to the control circuit 3.

The control circuit 3 reaches the detected object based on the time from the output of the drive timing signal of the light source to the acquisition of the detection signal, that is, the difference between the time when the laser beam is emitted and the time when the reflected light is received. Measure the distance of.

In the distance measuring device 100 configured as described above, the quality of the laser beam output from each light emitting element group is guaranteed, and the angular resolution is maintained high. Further, by irradiating the same detection area with a plurality of laser beams at different timings, the total intensity can be improved and the measurement distance can be extended. By integrating the detection signals based on the reflected light, it is possible to acquire the detection signals with a high S / N ratio and perform distance measurement with high accuracy.

The control circuit 3 is realized by, for example, an integrated circuit chip such as an LSI chip or a microprocessor, a logic device such as a field programmable gate array (FPGA: Field Programmable Gate Array), a combination of an integrated circuit chip and a logic device, or the like. May be good.

(Differences from Patent Document 1)
Patent Document 1 discloses a method of forming an APD using a CMOS process for the purpose of providing a highly sensitive optical receiver. However, in Patent Document 1, "APD in which the electrodes are arranged only on the surface side of the wafer is formed without using a special process of stacking chips and using electrodes on both the front and back surfaces of the wafer, and the incident light by the avalanche multiplier layer is formed. The problem of "it is not possible to secure an appropriate multiplication factor of about 100 to 200 times by multiplying the signal" has not been solved.

Since the conventional APD forms electrodes on both the front and back sides of the chip, it has been difficult to make one chip using a general CMOS process in which electrodes are formed only on the wafer surface side. On the other hand, there is a special process in which chips are laminated and electrodes on both the front and back sides can be used, but the manufacturing cost is high and it is difficult to apply as compared with a general CMOS process. Therefore, in the present embodiment, by forming the electrode formed on the back surface side on the front surface side, it is possible to incorporate the electrode into the IC by using the CMOS process and integrate it into one chip with the peripheral control circuit. Further, since the cathode bias voltage can be increased at the same time as the miniaturization, the incident light signal can be multiplied by the avalanche multiplier layer, and an appropriate multiplication factor of, for example, about 100 to 200 times can be secured.

In the present embodiment, specifically, a guard ring region is formed on the wafer surface from the Deep Nwell layer 46 between the Pwell layer 43 of the anode region 51A and the Nwell layer 47 of the cathode region 52A so as to suppress edge breakdown. 53 is provided. Further, by forming the avalanche multiplier layer 48 with an impurity concentration gradient, the structure is such that the avalanche breakdown occurs in the wafer depth direction. As a result, the cathode bias voltage Vcb can be increased, so that the incident light signal by the avalanche multiplier 48 can be multiplied, and an appropriate multiplication factor of, for example, about 100 to 200 times can be secured.

1 Light projecting unit 2 Light receiving unit 3 Control circuit 11 Light source 13 Coupling lens 14 Optical scanner (optical scanning unit)
16 Light source drive circuit 17 Optical scanner drive circuit 18 Scanning angle monitor 21 Light receiving element 22 Light receiving lens 23 Amplifier 25 Integrator 30 Avalanche photodiode (APD)
31 Cathode bias control circuit 32 Temperature sensor bandgap reference circuit (Temperature sensor BGR circuit)
33 AD converter (ADC)
40 Semiconductor substrate 41 P + Semiconductor layer 42 P Semiconductor layer 43 Pwell layer 44 N + Semiconductor layer 45 STI structure 46 Deep Nwell layer 47 Nwell layer 48 Avalanche multiplier layer 51 Anode electrode 51A Anode region 52 Cathode electrode 52A Cathode region 53 Guard ring region 100 distance measuring device

Claims (5)

An avalanche photodiode (APD) having an avalanche multiplier having N-type or P-type impurities in the PN junction layer and outputting a photoelectric conversion current,
A light receiving circuit including a temperature sensor BGR circuit that detects a temperature using a bandgap reference circuit (BGR circuit) and changes and outputs the cathode bias voltage of the APD based on the detected temperature.
The APD is a guard ring provided with an impurity concentration portion of a semiconductor substrate between the Pwell layer in the anode region and the Nwell layer in the cathode region on the wafer surface side of the Deep Nwell layer conducting with the Nwell layer in the cathode region. Has an area and
In the APD, the breakdown voltage between the Pwell layer in the anode region and the Nwell layer in the cathode region, which is formed via the guard ring region, is set between the Pwell layer in the anode region and the Deep Nwell layer in the cathode region. A light receiving circuit characterized in that the impurity concentration of the Pwell layer in the anode region is higher than the impurity concentration of the Deep Nwell layer in the cathode region in order to make it higher than the breakdown voltage in the avalanche multiplier layer. In the APD, the impurity concentration of the avalanche multiplier layer is in the range of 1 × 10 ¹⁵ to 10 ¹⁷ [cm ^-3 ], and the impurity concentration in the anode region is twice or more higher than the impurity concentration in the cathode region. The light receiving circuit according to claim 1. The light receiving circuit according to claim 1 or 2, wherein the light receiving circuit further includes an AD converter that AD-converts a signal of a photoelectric conversion current from the APD into a digital signal. The light receiving element for the light receiving circuit according to claim 1.
In the APD, the impurity concentration of the avalanche multiplier layer is within the range of 1 × 10 ¹⁵ to 10 ¹⁷ [cm ^-3 ], and the impurity concentration in the anode region is twice or more higher than the impurity concentration in the cathode region. A light receiving element characterized by. The APD array device for the light receiving circuit according to any one of claims 1 to 3.
An APD array device characterized in that a plurality of the APDs are arranged one-dimensionally or two-dimensionally.

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