JP2020126477A - Electronic control device - Google Patents

Abstract

To provide an electronic control device capable of suppressing deterioration of real-time property.SOLUTION: A microcomputer includes a plurality of cores, a shared resource that can be used by the plurality of cores, a plurality of multipliers that set the operating clock of each core, and a monitoring core that sets the values of the multipliers. When each core acquires a right to use the shared resource, the core occupies the shared resource so that other cores cannot use the shared resource until the usage right is released. The monitoring core detects an occupying core that occupies the shared resource among the multiple cores, and sets values of the multipliers in order to make the operating clock of the occupying core faster than the one set when the occupying core does not occupy the shared resource (S10 to S16).SELECTED DRAWING: Figure 3

Description

The present disclosure relates to electronic control devices.

Conventionally, there is an electronic control device including a plurality of cores disclosed in Patent Document 1. The electronic control unit can connect to each of the frequency generation circuit capable of generating a plurality of different frequencies and the plurality of cores by switching any one of the plurality of different frequencies generated by the frequency generation circuit. And a switching device.

JP, 2017-199221, A

By the way, in an electronic control device having a plurality of cores, the plurality of cores may share resources. In this case, in the electronic control device, one core among the plurality of cores can occupy the shared resource. Then, when another core tries to occupy the shared resource, it has to wait for the core occupying the shared resource to release the shared resource.

Therefore, in the electronic control device of Patent Document 1, release of the shared resource is delayed when the core whose frequency is set slow occupies the shared resource. That is, the electronic control device takes a long time to wait for the core, which is trying to occupy the shared resource, to release the shared resource. Therefore, the electronic control device has a problem that the real-time property is impaired.

The present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide an electronic control device that can suppress deterioration of real-time property.

In order to achieve the above object, the present disclosure provides
A plurality of processing units (11, 12, 13, 14),
At least one shared resource (40, 41, 42) usable by a plurality of processing units,
An operation clock management unit (10, 31, 32, 33, 34) that manages the operation clock of each processing unit,
When each processing unit acquires the usage right of the shared resource, it occupies the shared resource so that other processing units cannot use the shared resource until the usage right is released.
The operation clock management unit detects an occupancy processing unit that occupies the shared resource among the plurality of processing units, and speeds up the operation clock of the occupancy processing unit as compared with the case where the shared resource is not occupied. Characterize.

As described above, according to the present disclosure, the operation clock of the occupancy processing unit is made faster than that in the case where the shared resource is not occupied. The time spent can be shortened. Therefore, the present disclosure can suppress the loss of real-time property.

It should be noted that the claims and the reference numerals in parentheses described in this section indicate the corresponding relationship with the specific means described in the embodiments described below as one aspect, and the technical scope of the present disclosure. Is not limited.

It is a block diagram showing a schematic structure of a display system including a microcomputer in a 1st embodiment. FIG. 3 is a state machine diagram showing state transitions of a microcomputer in the first embodiment. 6 is a flowchart showing the processing operation of the monitoring core in the first embodiment. It is a flow chart which shows speed-up core decision processing of a surveillance core in a 1st embodiment. 6 is a time chart showing the processing operation of the microcomputer in the first embodiment. It is a block diagram which shows schematic structure of the microcomputer in 2nd Embodiment. It is a flowchart which shows the speed-up core determination process of the monitoring core in 2nd Embodiment. 9 is a time chart showing the processing operation of the microcomputer in the second embodiment. It is a flowchart which shows the speed-up core determination process of the monitoring core in a modification.

Hereinafter, a plurality of modes for carrying out the present disclosure will be described with reference to the drawings. In each form, parts corresponding to the matters described in the preceding form may be assigned the same reference numerals and overlapping description may be omitted. In each mode, when only a part of the configuration is described, the other modes described earlier can be applied to other parts of the configuration.

The electronic control unit of the present embodiment will be described with reference to FIGS. In this embodiment, as an example, an example applied to an electronic control device including the microcomputer 100 in the display system is adopted. Further, as the display system, for example, one installed in a vehicle can be adopted. However, the present disclosure is not limited to this, and can be applied to a system that controls a control target different from the display device 400.

As shown in FIG. 1, the display system includes a microcomputer 100, an oscillator 200, a first video processing device 310, a second video processing device 320, a display device 400, and the like. The display system is a system that controls display in the display device 400. The display device 400 can employ, for example, a liquid crystal display or an organic EL display.

The first video calculation device 310 includes a second microcomputer 311 and the like. The second video calculation device 320 includes a third microcomputer 321 and the like. In each of the video calculation devices 310 and 320, each of the microcomputers 311 and 321 performs a calculation process based on a control signal from the microcomputer 100. Each of the microcomputers 311 and 321 performs display control for drawing on the display device 400 based on the processing result of the arithmetic processing.

The display system is required to have real-time drawing on the display device 400. That is, the electronic control device is required to actually draw on the display device 400 in a short time after the drawing instruction to the display device 400 is issued. Further, when the electronic control device controls a control target different from the display device 400, real-time control of a control instruction to the control target is required.

Further, in the electronic control device, it is necessary to reduce the power consumption of the microcomputer 100. In other words, in the electronic control device, it is necessary to suppress heat generation due to the microcomputer 100 consuming electric power.

The microcomputer 100 includes a monitoring core 10, a first core 11, a second core 12, a third core 13, a first ROM 21, a second ROM 22, a third ROM 23, a first multiplier 31, a second multiplier 32, a third multiplier 33, The shared resource 40 and the spin lock unit 50 are provided. As described above, since the microcomputer 100 includes the plurality of cores 10 to 13, it can be said that it is a multi-core microcomputer. Further, the microcomputer 100 is connected to an oscillator 200 that generates an operation clock for each of the cores 10 to 13.

The shared resource 40 is a resource that can be used by the plurality of cores 11 to 13. The shared resource 40 can be used by the plurality of cores 11 to 13, but exclusive processing is performed so that the plurality of cores 11 to 13 are not used at the same time. This exclusive processing will be described later. As the shared resource 40, for example, a memory or an input/output device (I/O) can be adopted. The memory as the shared resource 40 may be a partial area of the memory device. In this embodiment, the microcomputer 100 having one shared resource 40 is adopted. However, the microcomputer 100 may include a plurality of shared resources.

The spin lock unit 50 is a unit for the cores 11 to 13 to occupy and exclude the shared resource 40. The spin lock unit 50 is configured to be capable of transitioning between a mode indicating that the shared resource 40 is in the occupied state and a mode indicating that it is in the released state. For example, the spin lock unit 50 is configured such that the cores 11 to 13 can store, as the spin lock occupancy information, information indicating an occupied state and information indicating a released state.

The spin lock unit 50 does not store the information indicating the occupied state and the information indicating the released state at the same time. The spin lock unit 50 always stores only one of the information indicating the occupied state and the information indicating the released state.

That is, the spinlock unit 50 associates the information indicating the occupied state with the dedicated core by the core (hereinafter, the dedicated core) that has acquired the right to use the shared resource 40 among the plurality of cores 11 to 13. Is stored. In the spin lock unit 50, when the dedicated core releases the shared resource 40, the dedicated core stores information indicating that the shared resource 40 is in the released state. As described above, the occupied state is a state in which any of the plurality of cores 11 to 13 has acquired the right to use the shared resource 40. On the other hand, the released state is a state in which the dedicated core releases the right to use the shared resource 40.

Note that, for example, the spin lock unit 50 stores 1 as the information indicating the occupied state in association with the occupied core and 0 as the information indicating the released state. Therefore, the spin lock unit 50 can employ, for example, a register. The spinlock occupation information can be said to be exclusive information. The dedicated core corresponds to the dedicated processing unit.

The microcomputer 100 uses, as the plurality of cores 10 to 13, a first core 11 to a third core 13 that performs processing relating to display control of the display device 400, and operating clocks of the cores 11 to 13 using the multipliers 31 to 33. The monitoring core 10 for setting

The first core 11 is connected to the first ROM 21 as a storage unit for the first core 11, and is also connected to the first multiplier 31 as a portion for setting an operation clock for the first core 11. The shared resource 40 and the spin lock unit 50 are connected to the first core 11.

The first core 11 operates by being supplied with an operation clock from the first multiplier 31. The first multiplier 31 is a part that can independently change the operation clock of the first core 11. The first multiplier 31 is a device for multiplying the frequency of the reference clock supplied from the oscillator 200. The first multiplier 31 supplies an operation clock having a frequency according to the set value set by the monitoring core 10 to the first core 11.

The first multiplier 31 is configured such that, for example, two values, a set value in the high speed mode and a set value in the low speed mode, can be set as the set values. The high speed mode and the low speed mode are operation modes of the cores 11 to 13. The high speed mode and the low speed mode show a relative difference in operating clock. Therefore, the high speed mode indicates an operation mode in which the operation clock is raised as compared with the low speed mode. The first core 11 operates in the high speed mode when the set value in the high speed mode is set in the first multiplier 31, and operates in the low speed mode when the set value in the low speed mode is set in the first multiplier 31. Works with.

The operation mode of the first core 11 is set to the high speed mode when the first core 11 acquires the right to use the shared resource 40, and the first core 11 does not acquire the right to use the shared resource 40. In addition, the operation mode is set to the low speed mode. That is, the operation mode of the first core 11 is set to the low speed mode in the normal case where the first core 11 has not acquired the right to use the shared resource 40. Therefore, the low speed mode can be restated as the normal mode.

The first core 11 executes, for example, a program stored in the first ROM 21 to execute arithmetic processing while using the data stored in the first ROM 21 and the shared resource 40.

The first core 11 can use the shared resource 40 only when the shared resource 40 is in the released state. When the first core 11 can acquire the right to use the shared resource 40, the first core 11 stores the information indicating the occupied state in the spin lock unit 50 in association with the first core 11. When the first core 11 acquires the usage right of the shared resource 40, the first core 11 can occupy the shared resource 40 so that the other cores 12 and 13 cannot use the shared resource 40 until the usage right is released. Then, when releasing the shared resource 40, the first core 11 stores information indicating that it is in the released state in the spin lock unit 50. In this way, the first core 11 performs exclusive processing. Note that the exclusive processing is not limited to the above, and even a mutex or the like can be adopted.

The second core 12 is connected to the second ROM 22 as a storage unit for the second core 12, and is also connected to the second multiplier 32 as a portion for setting an operation clock for the second core 12. The shared resource 40 and the spin lock unit 50 are connected to the second core 12. The third core 13 is connected to the third ROM 23 as a storage unit for the third core 13, and is also connected to the third multiplier 33 as a portion for setting an operation clock for the third core 13. The shared resource 40 and the spin lock unit 50 are connected to the third core 13.

The second core 12 and the third core 13 are configured similarly to the first core 11. Further, the second ROM 22 and the third ROM 23 are configured similarly to the first ROM 21. Further, the second multiplier 32 and the third multiplier 33 are configured similarly to the first multiplier 31. Therefore, when each core acquires the usage right of the shared resource 40, it can occupy the shared resource 40 so that other cores cannot use the shared resource 40 until the usage right is released.

As described above, the microcomputer 100 is configured as a multi-core microcomputer including the plurality of cores 11 to 13 in view of the performance of the display system. However, it is desirable for the microcomputer 100 to avoid operating the plurality of cores 11 to 13 in the high speed mode all the time from the viewpoint of heat generation.

The monitoring core 10 has a function of detecting the occupied state of the shared resource 40 and a function of changing the settings of the multipliers 31 to 33. FIG. 2 shows a state machine of the multipliers 31 to 33 of the cores 11 to 13 controlled by the monitoring core 10.

The monitoring core 10 acquires spin lock occupation information stored in the spin lock unit 50, which indicates two states (spin lock states) of the shared resource 40. Then, the monitoring core 10 detects whether any of the plurality of cores 11 to 13 occupies the shared resource 40 from the spin lock occupancy information. One state in the shared resource 40 is an occupied state in which one of the cores 11 to 13 occupies the shared resource 40. The other state is a state in which none of the plurality of cores 11 to 13 occupies the shared resource 40, that is, a released state in which the shared resource 40 is released.

Note that occupying the shared resource 40 by any of the plurality of cores 11 to 13 is also referred to as spin lock occupancy of the shared resource 40. On the other hand, releasing the shared resource by the dedicated core is also referred to as releasing the spinlock of the shared resource 40.

Further, as shown in FIG. 2, the monitoring core 10 changes the operation mode of each of the cores 11 to 13 to the high speed mode or the low speed mode by changing the set value of each of the multipliers 31 to 33. The monitoring core 10 puts the multiplier corresponding to the dedicated core occupying the shared resource 40 into the high speed mode. Further, when the dedicated core occupying the shared resource 40 releases the usage right, the monitoring core 10 puts the multiplier corresponding to the dedicated core into the low speed mode.

Each of the first core 11, the second core 12, and the third core 13 corresponds to a processing unit. The monitoring core 10, the first multiplier 31, the second multiplier 32, and the third multiplier 33 correspond to an operation clock management unit.

Here, the processing operation of the microcomputer 100 and the monitoring core 10 will be described with reference to FIGS. 3, 4, and 5. The monitoring core 10 executes the processing shown in the flowchart of FIG. 3 every predetermined time.

In step S10, the spin lock state is detected (operation clock management unit). The monitoring core 10 acquires the spin lock occupancy information stored in the spin lock unit 50, and detects the spin lock state based on the acquired spin lock occupancy information. That is, the monitoring core 10 is in an occupied state in which one of the plurality of cores 11 to 13 occupies the shared resource 40, or a released state in which none of the plurality of cores 11 to 13 occupies the shared resource 40. Is detected.

In step S11, it is determined whether or not there is a core occupying the shared resource (operation clock management unit). The monitoring core 10 determines whether or not there is a core occupying the shared resource 40 based on the detection result in step S10. Then, if the monitoring core 10 determines that there is a core that occupies the shared resource 40, the process proceeds to step S12, and if it does not determine that there is a core that occupies the shared resource 40, the process proceeds to step S17. ..

In step S12, the core occupying the shared resource is specified (operation clock management unit). The monitoring core 10 identifies the core occupying the shared resource 40 based on the detection result in step S10. That is, the monitoring core 10 identifies the dedicated core that occupies the shared resource 40 among the plurality of cores 11 to 13 based on the spinlock occupation information.

The monitoring core 10 may store the specified dedicated core in a memory or the like in order to determine whether the current dedicated core and the previous dedicated core are the same.

In step S13, it is determined whether it is the same as the previously occupied core. If the monitoring core 10 does not determine that the current dedicated core and the previous dedicated core are the same, the monitoring core 10 proceeds to step S14, and if it determines that the current dedicated core and the previous dedicated core are the same. The process of FIG. 3 is terminated.

As will be described later, the monitoring core 10 sets the operation mode of the dedicated core to the high speed mode. However, when the occupied core of this time is the same as the occupied core of the previous time, the monitoring core 10 maintains the current operation mode without setting the operation mode of the occupied core of this time to the high speed mode. Note that the present disclosure can be adopted even in the monitoring core 10 that does not execute step S13. Further, when the occupied core is the same as the previous one, the operation mode of the occupied core is already set to the high speed mode, and it is not necessary to change the operation mode. Accordingly, the present disclosure maintains the current operation mode (does not change the operation mode setting) in order to reduce the processing load due to the operation mode change of the monitoring core 10.

In step S14, the core to be accelerated is determined (operation clock management unit). Here, the accelerated core determination process will be described with reference to FIG. When determining the core to be accelerated in step S14, the monitoring core 10 executes the process shown in the flowchart of FIG.

In step S20, the core occupying the shared resource is confirmed. The monitoring core 10 confirms the core occupying the shared resource 40 based on the spinlock occupancy information stored in the spinlock unit 50. Then, the monitoring core 10 proceeds to step S21 when the occupied core is the first core 11, proceeds to step S22 when the occupied core is the second core 12, and proceeds to step S23 when the occupied core is the first core 11. move on.

In step S21, the first core is targeted for speed-up. In step S22, the second core is targeted for speed-up. In step S23, the third core is targeted for speeding up. In this way, the monitoring core 10 detects the occupied core that occupies the shared resource 40 among the plurality of cores 11 to 13. In addition, when not performing step S13, the monitoring core 10 determines the dedicated core identified in step S12 as a core to be accelerated.

Here, the description returns to the flowchart of FIG. When the monitoring core 10 determines the core to be accelerated, the monitoring core 10 proceeds to step S15.

In step S15, all the cores are set to the low speed mode (operation clock management unit). The monitoring core 10 once sets all the cores 11 to 13 in the low speed mode. The monitoring core 10 sets all the cores 11 to 13 in the low speed mode by setting the setting values in the low speed mode for the respective multipliers 31 to 33.

As will be described later, the monitoring core 10 sets the dedicated core in the high speed mode. Therefore, when detecting the occupied core, the monitoring core 10 reduces the operation clocks of all the cores 11 to 13 and then increases the operation clock of only the occupied core. As a result, the electronic control device can speed up only the occupied core, so that the power consumption of the microcomputer 100 can be reliably suppressed. Note that the present disclosure can be adopted even in the monitoring core 10 that does not execute step S15.

In step S16, the determined core is set to the high speed mode (operation clock management unit). The monitoring core 10 sets the dedicated core in the high speed mode by setting the set value in the high speed mode for the multiplier corresponding to the occupied core. That is, the monitoring core 10 speeds up the operation clock of the occupied core as compared with the case where the shared resource 40 is not occupied. Therefore, the dedicated core uses the shared resource 40 in the high speed mode.

In this way, the microcomputer 100 speeds up the operating clock of the dedicated core more than when it does not occupy the shared resource 40. Therefore, the microcomputer 100 occupies the shared resource 40 more than when it does not speed up the operating clock of the dedicated core. The time spent can be shortened. Therefore, the electronic control device can suppress the deterioration of the real-time property. Further, by this, the electronic control device can ensure real-time rendering of the display device 400.

That is, for example, when the monitoring core 10 checks the spin lock unit 50 and detects that the occupied core is the first core 11, the monitoring core 10 sets the first multiplier 31 to the set value in the high speed mode. As a result, the first core 11 operates faster than in the low speed mode and can occupy the shared resource 40 for a shorter time than in the case of operating in the low speed mode. Therefore, the microcomputer 100 can maintain the real-time property of the display system.

Next, the case where NO is determined in step S11 will be described. In step S17, it is determined whether or not the return condition is satisfied (operation clock management unit). The monitoring core 10 determines whether or not a predetermined return condition is satisfied. If it is determined that the return condition is satisfied, the process proceeds to step S18, and if it is determined that the return condition is not satisfied, the process of FIG. 3 ends. To do. The return condition is a condition for determining whether or not the operation mode of the dedicated core set to the high speed mode can be returned to the low speed mode. The return condition corresponds to the speed reduction condition.

As the return condition, for example, the exclusive core releasing the right to use the shared resource 40 can be adopted. In this case, the monitoring core 10 confirms the spin lock occupation information of the spin lock unit 50, and when the information indicating the released state is stored, that is, the dedicated core releases the right to use the shared resource 40. If so, it is determined that the speed reduction condition is satisfied. That is, the monitoring core 10 determines that the return condition is satisfied by making the NO determination in step S11. As a result, the microcomputer 100 can immediately reduce the operating clock of the dedicated core, and thus can suppress power consumption.

Further, as the return condition, for example, it is possible to adopt that a situation in which the plurality of cores 11 to 13 do not occupy the shared resource 40 continues for a predetermined time. In other words, the return condition can be that the predetermined time has elapsed since the dedicated core released the shared resource 40.

In this case, the monitoring core 10 confirms the spin lock occupation information of the spin lock unit 50, and if the information indicating the released state is stored, starts the time measurement using a timer or the like. The monitoring core 10 clears the counted time when the information indicating the occupied state is stored before a predetermined time has elapsed from the start of the counting. Then, the monitoring core 10 determines that the return condition is satisfied when the situation in which the information indicating the released state is stored continues for a predetermined time. As a result, the microcomputer 100 can suppress continuous changes in the operation clock. Note that the present disclosure can be adopted even in the monitoring core 10 that does not execute step S17.

In step S18, all the cores are set to the low speed mode (operation clock management unit). The monitoring core 10 sets the dedicated core in the low speed mode by setting the setting value in the low speed mode for the multiplier corresponding to the occupied core. In other words, the monitoring core 10 makes the operating clock of the dedicated core slower than when it occupies the shared resource 40. Therefore, the core that has released the shared resource 40 performs processing in the low speed mode. As a result, the microcomputer 100 can suppress power consumption because the core that has released the shared resource 40 operates slower than in the high speed mode.

When the high speed mode is set for the occupied core, the other cores are set for the low speed mode. Therefore, the monitoring core 10 sets all the cores 11 to 13 in the low speed mode by setting the setting value in the low speed mode for the multiplier corresponding to the occupied core.

Here, the effect of the microcomputer 100 of the present embodiment will be described with reference to FIG. 5 in comparison with a microcomputer of a comparative example (hereinafter, comparative example) in which the operation clock is not speeded up. FIG. 5A is a time chart showing the processing operation of the comparative example, and FIG. 5B is a time chart showing the processing operation of the microcomputer 100. In the following, reference numerals are not given to the microcomputer, the first core to the third core, and the shared resource of the comparative example.

Each of the first core to the third core performs the same processing as that of each of the first core 11 to the third core 13. However, unlike the first core 11 to the third core 13, the first core to the third core do not operate in the high speed mode but always operate in the low speed mode.

In FIG. 5, the period during which each core is processing is indicated by a white square, and the period during which the dedicated core is processing the shared resource is indicated by a hatched square. Further, in FIG. 5, the core processing start is indicated by a white arrow, and the processing between the core and the shared resource is indicated by a broken arrow. Further, in FIG. 5, the occupation of the shared resource is indicated by a circle, and the failure of occupation of the shared resource is indicated by a cross (x).

For example, the second core 12 in FIG. 5B is performing the process during the period from timing t14 to timing t21. The first core 11 in FIG. 5B occupies the shared resource 40 at the timing t12, performs the processing on the shared resource 40 until the timing t16, and releases the shared resource 40 at the timing t16. The second core 12 in FIG. 5B attempts to occupy the shared resource 40 at the timing 15, but the shared resource 40 has already been occupied by the first core 11, and therefore the occupancy has failed.

The timing t1 corresponds to the timing t11. That is, FIG. 5 can be said to be a drawing comparing the processing times of the microcomputer of the comparative example including the first to third cores and the microcomputer 100 including the first to third cores 11 to 13. Further, the timing t8 in FIG. 5(b) indicates the timing t8 in FIG. 5(a).

As shown in FIG. 5A, the first core starts processing at timing t1. Then, the first core occupies the shared resource during the period from the timing t2 to the timing t5 and releases the shared resource at the timing t5. Since the first core does not speed up the operation clock, it operates in the low speed mode not only between timings t1 and t2 but also between timings 2 and t5.

On the other hand, as shown in FIG. 5B, the first core 11 starts processing at timing t11. Then, the first core 11 occupies the shared resource 40 during the period from the timing t12 to the timing t16, and releases the shared resource 40 at the timing t16.

At this time, the monitoring core 10 sets the first multiplier 31 to the set value in the high speed mode at the timing t13 when the first core 11 occupies the shared resource 40. Therefore, the first core 11 uses the shared resource 40 in the high speed mode in which the operation clock is speeded up.

Therefore, the first core 11 performs the same processing as the first core, but the occupied time of the shared resource 40 is shorter than that of the first core. Therefore, the time during which the first core 11 occupies the shared resource 40 (t12 to t16) is shorter than the time during which the first core 11 occupies the shared resource (t2 to t5).

It should be noted that the present embodiment adopts an example in which the occupied cores are transited to the low speed mode when a plurality of cores 11 to 13 do not occupy the shared resource 40 for a predetermined time. Therefore, the low speed mode is set for the first core 11, which is the occupied core, at the timings t17 and t20. As a result, the microcomputer 100 can suppress power consumption because the core that has released the shared resource 40 operates slower than in the high speed mode.

As described above, the first core 11 and the first core execute the same processing, and when they do not occupy the shared resource 40, they operate in the low speed mode. Therefore, the timing t12 corresponds to the timing t2. That is, the elapsed time from the timing t1 to the timing t2 is the same as the elapsed time from the timing t11 to the timing t12.

Further, as shown in FIG. 5A, the second core starts processing at timing t3 and tries to occupy the shared resource at timing t4. However, the shared resource is already occupied by the first core. Therefore, the second core fails to occupy and waits until the shared resource is released.

Then, the second core occupies the shared resource at timing t6 after the first core releases the shared resource at timing t5. After that, the second core occupies the shared resource until the timing t7, releases the shared resource at the timing t7, and performs the process until the timing t8. Like the first core, the second core does not speed up the operation clock, and therefore operates in the low speed mode during the entire period from timing t3 to timing t8.

On the other hand, as shown in FIG. 5B, the second core 12 starts processing at timing t14 and tries to occupy the shared resource 40 at timing t15. However, as in the comparative example, the shared resource 40 is already occupied by the first core 11. Therefore, the second core 12 fails to occupy and waits until the shared resource 40 is released. Then, the second core 12 waits until the shared resource is released, and occupies the shared resource at timing t17.

However, as described above, the first core 11 occupies the shared resource 40 for a shorter time than the first core. Therefore, the second core 12 has a shorter waiting time than the second core until the shared resource 40 is released. Therefore, the second core 12 can occupy the shared resource 40 earlier than the second core.

Further, the monitoring core 10 sets the second multiplier 32 to the set value in the high speed mode at the timing t18 when the second core 12 occupies the shared resource 40. Therefore, the second core 12 uses the shared resource 40 in the high speed mode in which the operation clock is speeded up. Therefore, like the first core 11, the second core 12 can shorten the occupied time of the shared resource 40 more than the second core. Therefore, the time during which the second core 12 occupies the shared resource 40 (t17 to t19) is shorter than the time during which the second core 12 occupies the shared resource (t6 to t7).

The cores 11 to 13 and the cores of the comparative example execute the same processing. Therefore, the timing t14 when the second core 12 starts the processing corresponds to the timing t3 when the second core starts the processing. That is, the elapsed time from the timing t1 to the timing t3 is the same as the elapsed time from the timing t11 to the timing t14.

Further, the second core 12 and the second core perform the same processing, and when they do not occupy the shared resource 40, they operate in the low speed mode. Therefore, the elapsed time from timing t7 to timing t8 is the same as the elapsed time from timing t19 to timing t21.

In this way, each core 11 to 13 not only has a shorter occupied time of the shared resource 40 than each core, but also has a shorter waiting time to wait for the shared resource 40 to be released. Therefore, in the example of the present embodiment, the microcomputer completes the processing of the second core at the timing t8, whereas the microcomputer 100 completes the processing of the second core 12 at the timing t21 earlier than the timing t8. .. Therefore, the microcomputer 100 can suppress the loss of real-time property.

The preferred embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present disclosure. The second and third embodiments will be described below as other embodiments of the present disclosure. The above-described embodiments and the second and third embodiments can be carried out independently, but can also be carried out in an appropriate combination. The present disclosure is not limited to the combinations shown in the embodiments and can be implemented by various combinations.

(Second embodiment)
The electronic control unit according to the second embodiment will be described with reference to FIGS. 6 to 8. The electronic control unit according to the present embodiment is different from the above-described embodiment in that it includes a microcomputer 110. The microcomputer 110 mainly includes a plurality of shared resources 41 and 42, and the processing operation of the monitoring core 10 is different from that of the microcomputer 100. In FIG. 6, the ROMs 21 to 23 provided corresponding to the cores 11 to 14 are not shown.

In this embodiment, the shared resources 41 and 42 include the fourth core 14 and the fourth multiplier 34 provided corresponding to the fourth core 14. The fourth core 14 operates similarly to the cores 11 to 13. The fourth multiplier 34, like the multipliers 31 to 33, supplies the fourth core 14 with an operation clock having a frequency according to the set value set by the monitoring core 10. However, the present disclosure can be adopted even for the microcomputer 110 that does not include the fourth core 14 and the fourth multiplier 34.

The shared resources 41 and 42 are similar to the shared resource 40. The spin lock units 51 and 52 are similar to the spin lock unit 50. Then, the monitoring core 10 is configured to be able to confirm the spin lock occupation information stored in both the spin lock units 51 and 52.

Note that in FIG. 6, the second shared resource 42 is illustrated so that it can be used only by the third core 13. However, the second shared resource 42 may be usable by the first core 11, the second core 12, and the fourth core 14.

Here, the speed-up core determination process in the monitoring core 10 will be described with reference to FIG. 7. When determining the core to be accelerated in step S14, the monitoring core 10 executes the process shown in the flowchart of FIG.

First, in step S30, the monitoring core 10 determines whether the first core 11 occupies the first shared resource 41. When the monitoring core 10 determines that the first core 11 occupies the first shared resource 41, the monitoring core 10 proceeds to step S31 and sets the first core 11 as a target for speeding up. On the other hand, when the monitoring core 10 does not determine that the first core 11 occupies the first shared resource 41, the monitoring core 10 proceeds to step S32.

Next, the monitoring core 10 determines in step S32 whether the second core 12 occupies the first shared resource 41. When the monitoring core 10 determines that the second core 12 occupies the first shared resource 41, the monitoring core 10 proceeds to step S33 and sets the second core 12 as a target for speeding up. On the other hand, when the monitoring core 10 does not determine that the second core 12 occupies the first shared resource 41, the monitoring core 10 proceeds to step S34.

Next, the monitoring core 10 determines in step S34 whether the third core 13 occupies the second shared resource 42. When the monitoring core 10 determines that the third core 13 occupies the second shared resource 42, the monitoring core 10 proceeds to step S35 and sets the third core 13 as a target for speeding up. On the other hand, when the monitoring core 10 does not determine that the third core 13 occupies the second shared resource 42, the monitoring core 10 ends the process of FIG. 7.

The monitoring core 10 does not speed up the operation clocks of other cores even if the other cores occupy other shared resources while speeding up the operation clocks of the occupied cores (operation clock management unit). The third core 13 uses the second shared resource 42 instead of the first shared resource 41. Therefore, the third core 13 can occupy the second shared resource 42 even if the first core 11 or the second core 12 occupies the first shared resource 41. Similarly, the first core 11 or the second core 12 can occupy the first shared resource 41 even if the third core 13 occupies the second shared resource 42.

However, as shown in FIG. 8, in the monitoring core 10, even when the third core 13 occupies the second shared resource 42 while the operation clock of the first core 11 or the second core 12 is being accelerated, The operation clock of the third core 13 is not accelerated. Similarly, when the monitoring core 10 accelerates the operation clock of the third core 13, even if the first core 11 or the second core 12 occupies the first shared resource 41, The operating clock of the occupied core (first core 11 or second core 12) is not accelerated.

That is, the monitoring core 10 preferentially speeds up the operation clock of the core that has previously occupied the shared resource. In other words, the monitoring core 10 preferentially speeds up the operation clock of the core when a certain core occupies the shared resource in a situation where no shared resource is occupied. Therefore, when a certain core occupies a shared resource, the monitoring core 10 does not speed up the operation clock of the other core even if the other core occupies another shared resource.

As described above, the microcomputer 110 has only one core that speeds up the operation clock among the plurality of cores 11 to 13. As a result, the microcomputer 110 can suppress an increase in power consumption by speeding up operation clocks of a plurality of cores (for example, the first core 11 and the third core 13). Further, since the microcomputer 110 can suppress an increase in power consumption, it is necessary to suppress heat generation accordingly.

(Modification)
Here, a modification of the second embodiment will be described with reference to FIG. The modified monitoring core 10 differs from the second embodiment in the speed-up core determination process. When determining the core to be accelerated in step S14, the monitoring core 10 executes the process shown in the flowchart of FIG.

In step S40, the monitoring core 10 determines whether the first shared resource 41 is occupied. Then, when it is determined that the first shared resource 41 is occupied, the monitoring core 10 speeds up the core occupying the first shared resource 41 in step S41. In this case, the monitoring core 10 speeds up the operation clock of one of the first core 11 and the second core 12 that occupies the first shared resource 41. On the other hand, when the monitoring core 10 does not determine that the first shared resource 41 is occupied, the monitoring core 10 speeds up the core occupying the second shared resource 42 in step S42. In this case, the monitoring core 10 speeds up the operation clock of the third core 13. The modified microcomputer 110 can achieve the same effects as those of the second embodiment.

10... Monitoring core, 11... First core, 12... Second core, 13... Third core, 14... Fourth core, 21... First ROM, 22... Second ROM, 23... Third ROM, 31... First multiplier , 32... Third multiplier, 33... Third multiplier, 34... Fourth multiplier, 40... Shared resource, 41... First shared resource, 42... Second shared resource, 50... Spinlock unit, 51... 1 spin lock part, 52... 2nd spin lock part, 100, 110... Microcomputer, 200... Oscillator, 310... 1st image processing device, 311... 2nd microcomputer, 320... 2nd image processing device, 321... 3rd microcomputer , 400... Display device

Claims (6)

A plurality of processing units (11, 12, 13, 14),
At least one shared resource (40, 41, 42) usable by a plurality of the processing units;
An operation clock management unit (10, 31, 32, 33, 34) that manages the operation clock of each processing unit,
Each processing unit, when acquiring the usage right of the shared resource, occupies the shared resource so that the other processing units cannot use the shared resource until the usage right is released,
The operation clock management unit detects an occupation processing unit that occupies the shared resource from among the plurality of processing units, and sets the operation clock of the occupation processing unit to be less than that when the shared resource is not occupied. An electronic control unit that speeds up. The operation clock management unit slows down the operation clock of the occupancy processing unit if it is determined that the speed-down condition is satisfied while the operation clock of the occupancy processing unit is being speeded up. Electronic control unit. The electronic device according to claim 2, wherein the operation clock management unit, when the exclusive processing unit releases the usage right, determines that the speed-down condition is satisfied, and decreases the operation clock of the exclusive processing unit. Control device. When a plurality of the processing units do not occupy the shared resource for a predetermined time, the operation clock management unit determines that the speed reduction condition is satisfied, and the operation clock of the occupation processing unit is set to a low speed. The electronic control device according to claim 2, which is realized. 5. The operation clock management unit, when detecting the occupancy processing unit, reduces the operation clocks of all the processing units and then speeds up only the operation clock of the occupancy processing unit. 2. The electronic control device according to item 1. Comprising a plurality of said shared resources,
The operation clock management unit controls the operation clocks of the other processing units even when the other processing units occupy the other shared resources while increasing the operation clocks of the occupation processing units. The electronic control device according to claim 1, wherein the speed is not increased.

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