JP2020119361A - Flash storage, computer, data erasure method for flash storage and flash storage control program - Google Patents

Abstract

To materialize a flash storage that allows for automatic and perfect erasure of data even in the flash storage performing wear leveling.SOLUTION: The flash storage comprises: at least one SSD; and at least one piece of flash storage control means that is connected to external equipment. The SSD comprises: a flash memory; and SSD control means that can acquire total capacity of the flash memory. When the flash storage control means receives a signal including an instruction indicating the erasure of data stored by the flash storage from the external equipment, the flash storage control means acquires information of the total capacity of the flash memory from the SSD control means, and transmits, to the SSD control means, a signal which instructs writing of pseudo data exceeding the total capacity of the flash memory.SELECTED DRAWING: Figure 1

Description

The present invention relates to a flash storage, a flash storage data erasing method, and a flash storage control program.

In recent years, there has been a demand for strengthening data security, and there is an increasing need to completely erase data at the time of carrying out or discarding a data holding device.

Hard disk drive (HDD) data erasing technology erases magnetic data by writing random data over the entire surface multiple times like the US Department of Defense (DoD5220.22-M) It is known how to do it.

However, recently, instead of the HDD, a flash storage (Flash Storage) using an SSD (Solid State Drive) configured by a flash memory (Flash Memory) that can be accessed at higher speed has been used.

Unlike an HDD, a flash memory is characterized in that when writing or erasing data, it can only be accessed in block units and the number of writes is limited.

Therefore, in order to improve the reliability, the SSD has a wear leveling function in which a flash memory larger than the range accessible from the host device is mounted and the block arrangement of data is dynamically distributed to perform writing.

FIG. 7 shows an example of wear leveling.

Of the memory area accessible from the controller (left figure), the block B of data is initially written in the block (old B) within the range managed by the SSD (right figure).

When the wear leveling operates, the data of the block B is written in the right block (new B), and the left block B is allocated to the block (new B).

Here, when the allocation change from the block (old/B) to the block (new/B) is performed in the background to prevent performance degradation, the data in the block (old/B) is not immediately deleted. Then, it remains for a while.

The allocation of the block B has been changed to the block (new/B), and the data of the block (old/B) cannot be read from the higher-level device by the usual means.

Therefore, if the SSD is maliciously disassembled and the contents of the flash memory are directly read, it is possible to read the data of the block (old B) before erasing.

Thus, due to wear leveling, some data remains in the SSD.

Patent Document 1 discloses a technique related to SSD data erasure.

JP, 2011-205295, A

However, according to the technique disclosed in Patent Document 1, it is necessary for the operator to specify the number of SSD overwrites.

In view of the above problems, it is an object of the present invention to provide a flash storage that automatically erases data completely.

To achieve the above object, the flash storage of the present invention comprises at least one SSD (Solid State Drive) and at least one flash storage control means connected to an external device, and the SSD is a flash. A memory and an SSD control unit capable of acquiring the total capacity of the flash memory, and the flash storage control unit receives a signal including an instruction to erase data stored in the flash storage from the external device; Information on the total capacity of the flash memory is acquired from the SSD control means, and a signal for instructing the SSD control means to write pseudo data that exceeds the total capacity of the flash memory is transmitted.

In order to achieve the above object, a computer of the present invention is equipped with a flash storage including at least one SSD and at least one flash storage control means connected to an external device, and the SSD is a flash memory. And an SSD control unit capable of acquiring the total capacity of the flash memory, wherein the flash storage control unit receives the signal including an instruction to erase the data stored in the flash storage from the external device, Information on the total capacity of the flash memory is acquired from the SSD control means, and a signal for instructing the SSD control means to write pseudo data that exceeds the total capacity of the flash memory is transmitted.

To achieve the above object, a method of erasing data in a flash storage according to the present invention includes a flash memory included in an SSD included in the flash storage when a signal including an instruction to erase data stored in the flash storage is received from an external device. Of the total capacity of the flash memory is acquired, and writing of pseudo data exceeding the total capacity of the flash memory is executed.

In order to achieve the above object, the flash storage control program of the present invention receives a signal including an instruction to erase data stored in the flash storage from an external device, and stores the flash memory in the SSD included in the flash storage. The computer is made to obtain the information of the total capacity and write the pseudo data that exceeds the total capacity of the flash memory.

According to the present invention, even in a flash storage which performs wear leveling, complete erasing of data can be automatically performed.

It is a figure which shows the structural example of 1st Embodiment. It is a figure which shows the structural example of 2nd Embodiment. It is a figure explaining operation|movement of 2nd Embodiment. It is a figure explaining operation|movement of 2nd Embodiment. It is a figure explaining operation|movement of 2nd Embodiment. It is a figure explaining operation|movement of 2nd Embodiment. It is a figure explaining operation|movement of 2nd Embodiment. It is a figure explaining operation|movement of 2nd Embodiment. It is a figure explaining operation|movement of 2nd Embodiment. It is a figure which shows the structural example of 3rd Embodiment.

[First Embodiment]
Next, an embodiment of the present invention will be described in detail with reference to FIG.

FIG. 1 is a configuration example of the first embodiment.

The flash storage 10 of the present invention includes at least one SSD 20 and at least one flash storage control means 30 connected to an external device.

The SSD 20 has a flash memory 21 and SSD control means 22 that can acquire the total capacity of the flash memory 21.

Then, when the flash storage control means 30 receives a signal including an instruction to erase the data stored in the flash storage 10 from the external device, the flash storage control means 30 sends information on the total capacity of the flash memory 21 from the SSD control means 22. get. Further, the flash storage control means 30 sends a signal for instructing the SSD control means 22 to write pseudo data that exceeds the total capacity of the flash memory 21.

By doing so, the flash storage 10 of the present embodiment writes pseudo data in all blocks of the flash memory 21 even if the flash storage performs wear leveling. As a result, the flash storage 10 can be completely erased without any unerased data. Further, when the flash storage 10 receives a signal including a command for erasing data, erasing is automatically performed, so that it is not necessary for the operator to specify the number of overwrites.
[Second Embodiment]
Next, a second embodiment will be described with reference to FIGS. 2 to 9.
[Description of configuration]
FIG. 2 shows a configuration example of the second embodiment.

The flash storage 100 includes a controller 130 and an SSD 120.

In the configuration example shown in FIG. 2, two controllers 130 and a plurality of SSDs 120 are provided, but the configuration may be one controller 130 and one SSD 120.

A RAID (Redundant Arrays of Inexpensive Disks) configuration can also be adopted by a configuration including a plurality of controllers 130 and a plurality of SSDs 120.

The controller 130 is for exchanging data between the SSD 120 and the server 200, which is an external device for the flash storage 100, and corresponds to the flash storage control means 30 described in the first embodiment.

The controller 130 includes a host I/F (I/F; interface) control chip 131, a disk I/F control chip 132, a CPU 133, and a memory 134.

The host I/F control chip 131 is an interface that sends and receives data to and from the server 200. Further, the disk I/F control chip 132 is an interface for transmitting/receiving data to/from the SSD 120.

The CPU 133 is a CPU (Central Processing Unit), controls the hardware of the flash storage 100, and performs software processing.

A memory (memory) 134 is a storage element, and stores FW (firmware) 135 for the CPU 133.

Next, a configuration example of the SSD 120 will be described with reference to FIG.

The SSD 120 includes a disk I/F control chip 121, a CPU 122, a memory 123, a flash controller 126, and a plurality of flash memories 127.

The disk I/F control chip 121 is an interface for transmitting/receiving data to/from the controller 130.

The CPU 122 is a CPU that controls the hardware of the SSD 120 and performs software processing.

The memory 123 is a storage element and stores an FW (firmware) 124 for the CPU 122. The memory 123 has an area capable of storing the value of the total capacity of the flash memory 127 as the capacity 125.

The flash memory 127 is a readable/writable flash memory that stores data used by the server 200.
[Description of operation]
Next, the operation of the flash storage 100 of this embodiment will be described with reference to FIGS. 4 to 9.

FIG. 4 is a diagram showing the operation of the flash storage 100.

In the configuration of FIG. 2, the SSD 120 is connected to the disk I/F control chip 132, but in the description of the operation of FIG. It is also supposed to be connected.

When the host I/F control chip 131 of the controller 130 receives a signal instructing the data erasing from the server 200, the flash storage 100 starts erasing the data of the SSD 120.

First, the CPU 133 confirms the type of the disk connected to the disk I/F control chip 132 (S101).

The CPU 133 determines whether the disk connected to the disk I/F control chip 132 is an SSD (S102).

If it is determined to be SSD in step S102 (Y in S102), the process proceeds to step S104.

When it is determined in step S102 that the SSD is not the SSD (N in S102), the process proceeds to step S103.

In step S103, the CPU 133 sends to the disc a signal for erasing the disc data by general writing, and erases the disc (S103).

In step S104, the CPU 133 sends a signal including a command for confirming the total capacity of the SSD 120 to the SSD 120, and the SSD 120 returns a signal including the value of the total capacity of the SSD 120 to the CPU 133 (S104).

Here, SAS (Serial Attached SCSI) is generally known as a disk I/F of the controller 130 and the SSD 120. In the description of step S104, the signal for confirming the total capacity of the SSD 120 with respect to the SSD 120 is one that defines C0h that is the Vendor Specific Operation Code of the SCSI command as in the command example on the left of FIG. May be.

Further, the signal returned by the SSD 120 to the controller may be an example of response data as shown on the right of FIG.

In step S105, the CPU 133 instructs the SSD 120 to write the erasing pseudo data equal to or larger than the total capacity value obtained in step S104. The SSD 120 executes the writing of the erasing pseudo data having the total capacity of the SSD 120 or more (S105).

Here, the manner of writing the erasing pseudo data in step S105 will be described.

First, it is assumed that the wear leveling operates in the background and the data of the block (old/B) remains without being erased, as shown in FIG. 7 described in the description of the background art.

Next, in step S105 of the present embodiment, the erasing pseudo data having a capacity larger than the total capacity of the SSD 120 is written, and the block A is allocated to the block (old/B) in which the data remains as shown in FIG. Suppose Here, in the block (new A), the pseudo data of the block A is written and the data is erased.

It should be noted that the block (old A) is intended to be erased in the background, and even if data remains for a while, writing is performed with the total capacity of the SSD 120 or more. Then, the pseudo data is written in the block (old-A).

In this way, as shown in FIG. 9, the erase pseudo data is written in all the blocks of the SSD 120, and the entire flash memory 127 of the SSD 120 is erased.

Next, the operation of the SSD 120 will be described with reference to FIG.

When the SSD 120 is activated, the SSD 120 activation process is performed (S201).

Next, the flash controller 126 acquires the total capacity of the flash memory 127 and stores it in the capacity 125 of the memory 123 (S202).

After step S202, the process waits for a command from the controller 130 (S203).

When the disk I/F control chip 121 receives the command, the CPU 122 determines whether the command is for checking the total capacity of the SSD (S204).

If it is determined in step S204 that the command is for checking the total capacity of the SSD (Y in S204), the process proceeds to step S205.

If it is determined in step S204 that the command is not the SSD erase command (N in S204), the process returns to step S203.

In step S205, the CPU 122 transmits a signal including the value of the total capacity of the flash memory 127 stored in the capacity 125 of the memory 123 to the controller 130 (S205).

The signal transmitted by the CPU 122 in step S205 may be the response data shown on the right side of FIG. 6 described above.

The above is the operation of the SSD 120.

In step S105 of FIG. 4, in order to perform writing over the total capacity of the flash memory held by the SSD 120, not only writing to an area accessible by the controller 130, but also writing to all actually held flash memories. Therefore, all the flash memories of the SSD 120 can be erased.

As described above, the flash storage 100 of the present embodiment writes pseudo data in all blocks of the flash memory 127 even if the flash storage performs wear leveling. As a result, the flash storage 100 can perform complete erasing without erasing data. Further, when the flash storage 100 receives a signal including a command for erasing data, erasing is automatically performed, so that it is not necessary for the operator to specify the number of overwrites.
[Third Embodiment]
Next, a third embodiment will be described with reference to FIG.

FIG. 10 is a configuration example of the personal computer 300.

Although a personal computer is used here, another computer may be used.

The personal computer 300 includes a CPU 310, a disk I/F control chip 320, a memory 330, and an SSD 120.

The CPU 310 controls the hardware of the personal computer 300 and executes software.

The memory 330 is a memory of the personal computer 300 and stores an erasing program 331 of the SSD 120. The erasing program 331 is a program that causes the CPU 310 to execute the same operation as the SSD erasing operation described in the description of the operation of the second embodiment.

The SSD 120 is the same as the SSD 120 of the second embodiment.

With such a configuration, it is possible to realize the personal computer 300 capable of complete erasing without erasing unerased SSD data. In addition, when erasing data, it is not necessary for the operator to specify the number of overwrites on the SSD.

Although the preferred embodiment of the present invention has been described above, the present invention is also applicable to a case where an information processing program that realizes the functions of the embodiment is directly or remotely supplied to a system or an apparatus.

10 flash storage 21 flash memory 22 SSD control means 30 flash storage control means 100 flash storage 121 disk I/F control chip 123 memory 125 capacity 126 flash controller 127 flash memory 130 controller 131 host I/F control chip 132 disk I/F control Chip 134 memory
135 memory 200 server 300 personal computer 310 CPU
320 disk I/F control chip 330 memory 331 erase program

Claims (4)

Flash storage
At least one SSD (Solid State Drive),
And at least one flash storage control means connected to an external device,
The SSD is a flash memory,
An SSD control unit capable of acquiring the total capacity of the flash memory,
When the flash storage control unit receives a signal including an instruction to erase the data stored in the flash storage from the external device, the flash storage control unit acquires the information on the total capacity of the flash memory from the SSD control unit and performs the SSD control. A flash storage, which transmits a signal for instructing the device to write pseudo data that exceeds the total capacity of the flash memory.
A computer equipped with the flash storage according to claim 1.
When a signal including an instruction to erase the data stored in the flash storage is received from an external device, information on the total capacity of the flash memory included in the SSD included in the flash storage is acquired, and pseudo data that exceeds the total capacity of the flash memory is acquired. Erasing the data in the flash storage.
When a signal including an instruction to erase the data stored in the flash storage is received from an external device, information about the total capacity of the flash memory included in the SSD included in the flash storage is acquired, and pseudo data that exceeds the total capacity of the flash memory And a control program for the flash storage that causes a computer to execute writing.

Images