JP2020112840A - Data processing device, data processing system, data processing method and program - Google Patents

Abstract

To implement a decision tree efficiently in a data processing device.SOLUTION: A data processing device comprises a comparator, a combination operation unit, and a data controller. Each comparator receives a plurality of input data vectors and outputs a comparison result vector. The combination operation unit combines the comparison result vectors output from the comparator and outputs a binary output vector. The data controller controls data processing based on the binary output vector.SELECTED DRAWING: Figure 3

Description

The present invention relates to a data processing device, a data processing system, a data processing method and a program.

Image and motion classification algorithms based on decision trees are widely used in many different technical fields such as image processing and motion recognition. A decision tree is a decision support tool that uses a dendritic graph or decision model and their possible outcomes.

Image classification (eg, ACF (aggregated channel features) algorithm) is based on decision trees. This algorithm approximates features at a higher level while achieving leading edge performance and is faster than previous HOG (histogram of gradient) algorithms.

In Patent Document 1, a conditional move mask for a conditional move involving operand selection is generated based on the generated mask. The generated mask is the output of a single SIMD (Single Instruction/Multiple Data) style operation with multiple operands.

Patent Document 2 describes how to speed up a code composed of a large number of conditional instructions, which executes a SIMD-style function based on an evaluation under one comparison condition. The solution is to add branching capability by the compiler.

Patent Document 3 discloses a method of mapping elements of an input vector to elements of an output vector in the SIMD style. This mapping is controlled using one status bit compare, one output per vector.

Non-Patent Document 1 discloses an ACF (aggregated channel features) algorithm based on a decision tree. This document shows that the ACF algorithm achieves state-of-the-art performance in pedestrian detection.

Non-Patent Document 2 shows that real-time multi-view face detection is possible by using the ACF algorithm.

US Pat. No. 7,480,787 JP, 2009-128989, A U.S. Patent Publication No. 2013/0212355

R. Zabih and J. Woodfill, "Fast Feature Pyramids for Object Detection," in IEEE Transactions on Pattern Analysis and Machine Intelligence. 2014; 36(8):1532-1545. B.Yang, J.Yan, Z. Lei, S.Z.Li, "Aggregate Channel Features for Multi-view Face Detection" in: 2014 IEEE International Joint Conference on Biometrics (IJCB), 2014, pp.1-8.

Non-Patent Documents provide the internal structure of the ACF algorithm itself and how to use the algorithm in real-time applications. However, nothing is provided about the details of the ACF hardware implementation.

In Patent Documents 1 to 3, a single operation output is used in the control path of each element of the SIMD vector. Non-Patent Documents 1 and 2 introduce the concept of a decision tree without providing implementation details. The problem is to evaluate one or more decisions when implementing the decision tree. The currently possible solutions to Patent Documents 1 to 3 can be processed only by sequentially performing a single arithmetic process, taking a great amount of time. Considering processing based on a two-level decision tree (that is, having three feature nodes), it takes a relatively large number of cycles to sequentially perform a single arithmetic operation for this decision tree. ..

The reachable execution speed is important in real-time applications, since the decision tree operation is the main processing performed inside the ACF algorithm.

A data processing device according to an embodiment is configured to combine a plurality of comparators, which receive a plurality of input data vectors and output a comparison result vector, and the comparison result vectors output from the comparators, and to output a binary output. It has a combination operation unit that outputs a vector and a data controller that controls data processing based on the binary output vector.

A data processing system according to an embodiment includes a memory unit, a bus, and a data processing device that communicates with the memory unit via the bus, and each of the data processing devices has a plurality of input data. A plurality of comparators that receive a vector and output a comparison result vector, a combining operation unit that combines the comparison result vectors output from the comparators and outputs a binary output vector, and data based on the binary output vector And a data controller for controlling processing.

A data processing method according to an embodiment is to receive a plurality of input data vectors, output a comparison result vector, combine the comparison result vectors output from a comparator to output a binary output vector, and output the binary output vector. The data processing is controlled based on the vector.

A data processing program according to an embodiment includes a process of receiving a plurality of input data vectors and outputting a comparison result vector, and a process of combining the comparison result vectors output from a comparator and outputting a binary output vector. , A process for controlling data processing based on the binary output vector, and a computer.

According to one embodiment, a decision tree can be efficiently implemented in a data processing device.

It is a figure which shows typically mounting of the data processing apparatus concerning Embodiment 1 in a data processing system. FIG. 3 is a diagram showing application of a decision tree to the data processing device according to the first exemplary embodiment. FIG. 1 is a diagram schematically showing a configuration of a data processing device according to a first exemplary embodiment. FIG. 3 is a diagram schematically showing data processing in the data processing device according to the first exemplary embodiment. FIG. 3 is a diagram schematically showing the configuration of a data processing device according to a second exemplary embodiment. It is a figure which shows typically the structure of the data processing apparatus concerning Embodiment 3.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the drawings, the same reference numerals are given to the same elements, and redundant description will be omitted as necessary.

Embodiment 1
The data processing apparatus according to the first embodiment will be described. The data processing device 100 according to the first embodiment is configured to perform processing for a decision tree. FIG. 1 schematically shows the mounting of the data processing device 100 according to the first embodiment in a data processing system 1000.

As shown in FIG. 1, the data processing system 1000 includes a central processing unit (CPU) 101, a memory 102, a processor 103, and a bus 104. The data processing system 1000 is configured to be capable of executing SIMD (Single Instruction/Multiple Data) processing.

The CPU 101, the memory 102, the processor 103, and other modules and components of the data processing system 1000 are connected via a bus 104, and these devices can mutually exchange data, parameters, programs, algorithms, and the like. The CPU 101 performs various processes for controlling the calculation in the data processing system 1000. The memory 102 stores data, parameters, programs, algorithms, etc., and sends data, parameters, and data to these devices in response to requests from the CPU 101, the memory 102, the processor 103, and other modules and components of the data processing system 1000. Programs, algorithms, etc. can be provided.

The processor 103 includes the data processing device 100. For example, the processor 103 may include a logical operation unit, and the data processing device 100 may be included in the logical operation unit.

In the present embodiment, the data processing device 100 controls the data to be output based on the decision tree. Here, the decision tree applied to the data processing device 100 will be described. FIG. 2 shows application of a decision tree to the data processing device 100 according to the first exemplary embodiment.

First, the first input data Y, which is a single value, is compared with the first threshold TH1. When the first input data Y is smaller than the first threshold TH1 (Y<TH1), the comparison result of the first comparison C1 is “true” (output Y from the first comparison C1). When the first input data Y is greater than or equal to the first threshold TH1 (Y≧TH1), the comparison result of the first comparison C1 is “false” (output N from the first comparison C1).

When the comparison result of the first comparison C1 is "true" (that is, Y<TH1), the second input data U having a single value is compared with the second threshold value TH2. When the second input data U is smaller than the second threshold TH2 (U<TH2), the comparison result of the second comparison C2 is “true” (output Y from the second comparison C2) and “0x1”. Is output as the result value R. In addition, "0x**" represents the hexadecimal number, and "*" is either 1-9 or AF. When the second input data U is greater than or equal to the second threshold TH2 (U≧TH2), the comparison result of the second comparison C2 is “false” (output N from the second comparison C2) and “0x2”. Is output as the result value R.

When the comparison result of the first comparison C1 is “false” (that is, Y≧TH1), the second input data U is compared with the third threshold value TH3. When the second input data U is smaller than the third threshold TH3 (U<TH3), the comparison result of the third comparison C3 is “true” (output Y from the third comparison C3), and “0x3”. Is output as the result value R. When the second input data U is greater than or equal to the third threshold TH3 (U≧TH3), the comparison result of the third comparison C3 is “false” (output N from the third comparison C3), and “0x4”. Is output as the result value R.

In the present embodiment, the data processing device 100 executes the data move operation based on the result of the processing on the decision tree. The configuration and operation of the data processing device 100 will be described. FIG. 3 schematically shows the configuration of the data processing device 100 according to the first embodiment. FIG. 4 schematically shows the data processing of the data processing device 100 according to the first embodiment.

The data processing device 100 includes a comparator 11, a comparator 12, a combination operation unit 1, and a data controller 2.

The comparator 11 reads the input data vector Yin from the memory unit 102, for example. The input data includes multiple values. In this case, the input data vector Yin is assumed to include four 8-bit values Y1 to Y4 represented by a 2-digit hexadecimal number “0x**” when “*” is a hexadecimal number. That is, Yin={Y1, Y2, Y3, Y4}. For example, if Y1=0x20, Y2=0xA0, Y3=0x60 and Y4=0xC0, then Yin=0x20A060C0.

Further, the comparator 11 reads the threshold value input data vector T1 from, for example, the memory unit 102. The threshold input data vector T1 includes a plurality of values. In this case, the threshold input data vector T1 also includes four 8-bit values T11 to T14 represented by a 2-digit hexadecimal number. In the present embodiment, T11 to T14 have the same value. That is, T1={T11, T12, T13, T14} and T11=T12=T13=T14=TH1. For example, when TH1=0x80, T1=0x80808080.

The comparator 11 compares the input data vector Yin with the threshold input data vector T1. That is, the values Y1 to Y4 are respectively compared with the threshold value TH1. In the present embodiment, the comparator 11 determines whether each input value (each of Y1 to Y4) is smaller than the threshold value TH1. As described above, since Yin=0x20A060C0 and T1=0x80808080, Y1, Y3<TH1 (“true”), and Y2, Y4≧TH1 (“false”). In this case, the comparator 11 outputs 0x0000000A as the comparison result vector R1. Here, A is represented by a binary number “1010”.

The comparator 12 reads the input data vector Uin from, for example, the memory unit 102. In this case, the input data vector Uin also includes four 8-bit values U1 to U4 represented by a 2-digit hexadecimal number. That is, Uin={U1, U2, U3, U4}. For example, if U1=0x10, U2=0x30, U3=0xE0 and U4=0xF0, then Uin=0x1030E0F0.

The comparator 12 reads the threshold value input data vector T2 from, for example, the memory unit 102. In this case, the threshold value input data vector T2 also includes four 8-bit values T21 to T24 represented by a 2-digit hexadecimal number. In the present embodiment, T21 to T24 have the same value. That is, T2={T21, T22, T23, T24} and T21=T22=T23=T24=TH2. For example, when TH2=0xC0, T1=0xC0C0C0C0.

The comparator 12 compares the input data vector Uin with the threshold input data vector T2. That is, the values U1 to U4 are respectively compared with the threshold value TH2. In the present embodiment, the comparator 12 determines whether each input value (each of U1 to U4) is smaller than the threshold value TH2. As described above, since Uin=0x1030E0F0 and T2=0xC0C0C0C0, U1, U1<TH2 (“true”) and U3, U4≧TH2 (“false”). In this case, the comparator 12 outputs 0x00000000C as the comparison result vector R2. Here, C is represented by a binary number "1100".

The combination operation unit 1 performs a logical sum operation (AND) on the comparison result vectors R1 and R2, and outputs the obtained data as a binary output vector BIN. In this case, the join operation unit 1 performs a logical sum operation (AND) on R1=1010 and R2=1100 and outputs a binary output vector BIN=1000.

The data controller 2 controls the output data vector DC by using the input data vectors DA and DB according to the binary output vector BIN. The input data vector DA, the input data vector DB, and the output data vector DC are 8-bit values represented by two-digit hexadecimal numbers like the input data vectors Yin and Uin and the threshold input data vectors T1 and T2. That is, input data vector DA={DA1, DA2, DA3, DA4}, input data vector DB={DB1, DB2, DB3, DB4}, output data vector DC={DC1, DC2, DC3, DC4}. However, DA1 to DA4, DB1 to DB4, and DC1 to DC4 are two-digit hexadecimal numbers.

When the bit of the binary output vector BIN is "1", the value of the bit at the corresponding position of the input data vector DA is transferred to the bit at the corresponding position of the output data vector DC. On the other hand, when the bit of the binary output vector BIN is “0”, the value of the bit at the corresponding position of the input data vector DB is transferred to the bit at the corresponding position of the output data vector DC.

In this case, since the binary output vector BIN is "1000", the value of the first position "DA1" of the input data vector DA is transferred to the first position "DC1" of the output data vector DC, and 2 of the input data vector DB is transferred. The values of the fourth to fourth positions "DA2", "DA3" and "DA4" are transferred to the second to fourth positions "DC2", "DC3" and "DC4" of the output data vector DC, respectively. Therefore, the data controller 2 outputs the output data DC={DC1, DC2, DC3, DC4}={DA1, DB2, DB3, DB4}.

That is, the bit “1” of the binary output vector BIN functions as a flag that replaces the value of the input data vector DB transferred to the corresponding position of the output data vector DC with the value of the corresponding position of the input data vector DA. When the binary output vector BIN does not include any bit "1" (that is, BIN=0000), all the values (DB1 to DB4) of the input data vector DB are transferred to the output data vector DC without any change. It goes without saying that (that is, DC={DC1, DC2, DC3, DC4}={DB1, DB2, DB3, DB4}).

Further, although the input data vector DA is assumed to be a vector, the input data DA may be a scalar value. In this case, when the binary output vector BIN is bit "1", the scalar value DA0 is transferred to the corresponding position of the output data vector DC. That is, when the binary output vector BIN is "1010", for example, the output data vector DC may be {DA, DB2, DA, DB4}.

In this configuration, the output data vector DC may be returned to the input data vector DB. In other words, the input data vector DB may be continuously updated by the output data vector DC generated in the previous cycle.

The data processing device 100 performs the above-described data move (conditional move) operation for each value (that is, a set of values (Yk, Uk, T1k, T2k), where 1≦k≦4) in one cycle. It can be carried out. As a result, the data processing device 100 can perform the data move operation on all of the sets of four values read at the same time in only four cycles.

On the other hand, according to a general configuration based on patent documents, non-patent documents, etc., as shown in FIG. 2, the decision tree process of two layers requires three comparison nodes (C1 to C3). This general configuration requires one instruction that requires at least one cycle for each of Y reading, U reading, and each of the comparison nodes C1 to C3. Therefore, in such a decision tree, according to the decision branch, 5 or 6 cycles are required. Further, in the comparison nodes C1 to C3, when a stop cycle associated with a comparison and branch instruction is required, each of these comparison nodes requires at least two cycles. As a result, typical configurations require eight, nine, or more cycles per value set (Y and U) to perform a two-tier decision tree process. Here, it is assumed that the general configuration requires 10 cycles for each value set for two-layer decision tree processing. In this case, if the same operation is performed on a set of four values as in the data processing device 100, the data processing device 100 requires only 4 cycles, whereas in the general configuration, 10×4=40 cycles. Is required.

That is, since it is possible to process a plurality of input data vectors and threshold input data vectors each containing a plurality of values in a small number of cycles, it is possible to improve the processing speed of the data move calculation.

The number of values of each vector read simultaneously is not limited to four. The number of values in each vector loaded at the same time may be 2, 3, 5 or higher.

In the present embodiment, the join operation unit 1 executes the logical sum operation (AND), but the join operation unit 1 performs the logical product operation (OR), the exclusive OR operation (XOR), and the negative logical product operation ( NAND), NOR operation (NOR), or exclusive NOR operation (XNOR) may be executed.

In the present embodiment, the operation of the data processing device 100 is based on the two-layer decision tree that provides the two masks shown in FIG. 2, but this is merely an example. The operation of the data processing device 100 may be based on a deeper hierarchy of decision trees that provide more than one mask.

In the present embodiment, the input data vector and the output data vector include four 8-bit values. However, the values contained in the input data vector and the output data vector are not limited to 8-bit values. The input data vector and output data vector may include four 16-bit values. Each of the values included in the input data vector and the output data vector is a 4-digit hexadecimal number “0x***”. However, "*" is a hexadecimal number.

The input data and threshold input data are not limited to 8-bit values or 16-bit values. The input data, the threshold input data, and the output data may be configured by other multi-bit values such as 2 bits, 4 bits, and 32 bits.

Embodiment 2
Next, a data processing device according to the second embodiment will be described. FIG. 5 schematically shows the configuration of the data processing device 200 according to the second embodiment. The data processing device 200 has a configuration in which the pipeline register unit 3 is added to the data processing device 100 according to the first embodiment.

The pipeline register unit 3 is inserted between the comparators 11 and 12 and the combining operation unit 1. The pipeline register unit 3 stores the comparison results output from the comparators 11 and 12 continuously and temporarily. The pipeline register unit 3 continuously outputs the comparison results R1 and R2 output from the comparators 11 and 12 to the data controller 2 in the same cycle.

Therefore, according to this configuration, the data processing device 300 can realize a high allowable operating frequency by the pipeline processing, and therefore the data processing device 300 can execute continuous data move calculation with higher throughput than that in the first embodiment. ..

Embodiment 3
Next, a data processing device according to the third embodiment will be described. FIG. 6 schematically shows the configuration of the data processing device 300 according to the third embodiment. The data processing device 300 has a configuration in which comparators 13 and 14 are added to the data processing device 100 according to the first embodiment.

The comparator 13 receives and compares the input data vector Xin and the threshold data vector T3, and outputs the comparison result R3. The input data vector Xin and the threshold data vector T3 correspond to the input data vector Yin and the threshold data vector T1, respectively.

The comparator 14 receives and compares the input data vector Zin and the threshold data vector T4, and outputs the comparison result R4. The input data vector Zin and the threshold data vector T4 correspond to the input data vector Uin and the threshold data vector T2, respectively.

The combination operation unit 1 performs a logical sum operation (AND) on the comparison result vectors R1 to R4. As a result, the value at the same position in the comparison result vectors R1 to R4 becomes "1" (true), and the corresponding bit in the binary output vector BIN becomes "1".

According to this configuration, it is possible to handle four pairs of input vectors. In this case, the data processing device 300 can deal with data processing based on the decision tree of four layers.

The number of input vector pairs is not limited to two or four, and the number of input vector pairs may be three, five, or more as appropriate.

Other Embodiments It should be noted that the present invention is not limited to the above-described embodiments, and can be modified as appropriate without departing from the spirit of the invention. For example, in the above-described embodiment, the operation in the data controller has been described as the conditional move operation. However, this is merely an example. The data controller may perform other operations such as conditional add/subtract operations that perform addition (ADD) or subtraction (SUB).

In the above embodiment, each of the comparators 11 and 12 uses the same threshold value to compare the values of the input data vector. However, the threshold value may be appropriately changed to correspond to the purpose of data processing. In addition, the comparator, each input value is less than or equal to the threshold value, each input value is equal to the threshold value, each input value is not equal to the threshold value, each input value is greater than the threshold value, or each input value is You may judge whether it is more than a threshold value.

1 Combined Operation Unit 2 Data Controller 3 Pipeline Register Units 11-14 Comparators 100, 300 Data Processing Device 101 Central Processing Unit (CPU)
102 memory 103 processor 104 bus 1000 data processing system

Claims (9)

A plurality of comparators, each of which receives a plurality of input data vectors and outputs a comparison result vector;
A combining operation unit that combines the comparison result vectors output from the comparator and outputs a binary output vector,
A data controller that controls data processing based on the binary output vector,
Data processing device. Each comparator compares two input vectors with each other,
The value contained in one input vector is compared with the corresponding value contained in the other input vector,
The comparison result of each comparator includes a value indicating a comparison result of two values,
The data processing device according to claim 1. The join operation unit performs an OR operation on the comparison result vector,
If the value at the same position in the comparison result vector indicates that the comparison result is true, the corresponding bit in the binary output vector is "1",
If the value at the same position of the comparison result vector indicates that at least one of the comparison results is false, the corresponding bit of the binary output vector is "0".
The data processing device according to claim 1. The data controller receives a first input data vector and a second input data vector and outputs an output data vector,
If the bit of the binary output vector is “1”, the value of the corresponding position in the first input data vector is passed to the corresponding position in the output data vector,
If the bit of the binary output vector is "0", the value of the corresponding position in the second input data vector is passed to the corresponding position in the output data vector,
The data processing device according to claim 3. The data controller receives the first input data and the second input data vector, which are scalar values, and outputs an output data vector,
If the bit of the binary output vector is "1", the scalar value of the first input data is passed to the corresponding position in the output data vector,
If the bit of the binary output vector is "0", the value of the corresponding position in the second input data vector is passed to the corresponding position in the output data vector,
The data processing device according to claim 3. Further comprising a register unit for continuously storing the value at the same position of the comparison result vector and continuously outputting the stored value output from the comparator in the same cycle,
The data processing device according to claim 2. Memory part,
A bus
The data processing device according to claim 1,
Data processing system. Receives multiple input data vectors and outputs a comparison result vector,
Combining the comparison result vectors output from the comparator to output a binary output vector,
Controlling data processing based on the binary output vector,
Data processing method. A process of receiving a plurality of input data vectors and outputting a comparison result vector,
A process of combining the comparison result vectors output from the comparator and outputting a binary output vector;
Causing a computer to perform a process of controlling data processing based on the binary output vector,
Data processing program.

Images