JP2020098848A - Semiconductor element joining member - Google Patents

Abstract

To provide a semiconductor element joining member that can be used for joining a semiconductor device having a maximum operating temperature of 300°C with an electrode substrate or the like on which the semiconductor device is mounted.SOLUTION: A semiconductor element joining member 10 for joining a semiconductor element 11 and a substrate 12 on which the semiconductor element 11 is mounted uses at least one kind of Ag, Cu, and Au, and Sn as a main component, consists of an alloy 102 having a melting point of 500°C or more, includes a plurality of a void 101 having a total volume of 5% or more and 40% or less, and a thermal conductivity is 120 W/m K or more and electrical conductivity is 50% IACS or more after conducting a heat cycle test in which cooling to -40°C and heating to 300°C are repeated 300 times.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor element joining member used for joining a semiconductor element and a substrate.

2. Description of the Related Art In recent years, electric vehicles (EVs) have become widespread in countries around the world, following HV (Hybrid Vehicle) vehicles. Under such circumstances, research and development of a compact, high-performance, and inexpensive insulated gate bipolar transistor (IGBT) module using a SiC semiconductor device is underway.

For the first-generation IGBT module, initially a DBC (Direct Bonded Cupper, which is an insulating ceramic substrate joined with Cu with excellent conductivity as the circuit layer) was considered as the insulating circuit substrate, but it was more severe. DBA (Direct Bonded Aluminum, which has a highly conductive Al bonded as a circuit layer to a ceramic substrate.) that can be used in the operating environment has come to be used. After that, by omitting the heat dissipation board and thermal grease, and adopting a structure in which the DBA and the cooler are joined with Al punching metal, the second-generation IGBT module reduces thermal resistance by 30% compared to the first-generation IGBT module. Was put to practical use. A structure in which a heat dissipation path (hereinafter, referred to as “heat path”) is provided on one surface of a semiconductor device, like the first-generation IGBT module and the second-generation IGBT module, is called a single-sided cooling structure.

The 3rd generation IGBT module has a double-sided cooling structure in which Cu thin plates are soldered on both sides of the semiconductor device, and the semiconductor device is insulated by Si ₄ N ₃ ceramic (hereinafter referred to as “SIN ceramic”). Then, it is joined to the cooler with an insulating resin adhesive (insulating grease). By adopting such a new structure, the thermal resistance of the IGBT module is reduced by 65% compared to the 1st generation IGBT module, and the thermal resistance is reduced by 50% compared to the 2nd generation IGBT module. Was put to practical use.

The heat dissipation path from the semiconductor device used in the third-generation IGBT module has a simple structure in which the electrode substrate, the radiator of the cooler, and the plate material of SIN ceramic are joined. The joining of semiconductor devices to semiconductor devices and substrates such as electrode substrates is called die bonding (or die attachment or chip bonding). The material used for die bonding is called a die bond material. The electrode substrate, the radiator of the cooler, and the plate material of the SIN ceramic are bonded with a resin adhesive. Since the heat path composed of these members can be used for both double-sided cooling structure and single-sided cooling structure, it is considered to be widely used in the future as a heat path for IGBT modules.

The present inventor has proposed a heat dissipation electrode substrate containing a metal and diamond as main components, in which the thermal resistance of the Cu electrode is reduced (the thermal conductivity is higher than Cu) in order to improve the heat dissipation efficiency in the IGBT module ( Patent Document 1). Further, a high thermal conductive insulating resin composite member used for joining a heat dissipation substrate or an electrode to a cooler is also proposed (Patent Document 2). This high thermal conductive insulating resin composite member has a main layer in which diamond or ceramic is placed in an insulating resin material, and protective bonding layers placed on the front and back surfaces of the main layer. By using this high heat conductive insulating resin composite member in place of the conventional insulating member made of a resin adhesive and ceramic, the thermal resistance can be significantly reduced.

International Publication No. 2018/190023 Japanese Patent No. 6384979

Morisha Toshiaki, "High heat and low heat resistance Pb-free bonding technology using Ag nanoparticles and its application to power semiconductor module mounting", December 2008, Graduate School of Engineering, Osaka University Kanto Bureau of Economy, Trade and Industry, Alpha Design Co., Ltd., 2014 Strategic Basic Technology Advancement Support Project "Development of low-temperature sintering bonding technology and manufacturing equipment using fine metal powder for next-generation power semiconductors" R&D results, etc. Report March 2015

The thermal resistance of the heat path in the IGBT module is reduced by using the heat dissipation substrate and the high heat conductive insulating resin composite member proposed by the present inventors in Patent Documents 1 and 2. However, in addition to these, the main heat path also includes a die bond for joining a semiconductor device and a substrate (for example, an electrode substrate). The thermal resistance of the die bond material must be reduced in order to further reduce the size and improve the performance of the IGBT module by mounting the semiconductor device whose maximum operating temperature reaches 300°C. Further, reliability during operation of the semiconductor device is also required.

In the conventional IGBT module, the Si semiconductor device, which has a maximum operating temperature of about 150°C, is mounted on the DBA. The coefficient of linear expansion of Si, which is the material for semiconductor devices, is 4.5 ppm/K. The linear expansion coefficient of DBA is 7 ppm/K. Conventionally, soft solder is used as a die-bonding material for joining a semiconductor device and an insulating circuit board to alleviate a thermal stress caused by a difference in linear expansion coefficient between the semiconductor device and the insulating circuit board, which occurs when the semiconductor device operates. ..

As described above, conventionally, when a semiconductor device and an electrode substrate are joined, molten solder is poured between the two to perform joining (melt joining). The reliability of the die bond of the solder thus formed can be ensured by confirming the meniscus state of the solder on the outer periphery and confirming defects such as voids by measuring the inside of the solder with X-rays or ultrasonic waves. , Has been used for a long time. The meniscus state of the solder means a state in which the solder flows to the outer periphery of the joint.

If a Cu electrode substrate is used instead of DBA to reduce the thermal resistance of the electrode, the linear expansion coefficient increases to 17 ppm/K. Further, the difference in linear expansion coefficient between the Si semiconductor device and the Cu electrode is as large as 12.5 ppm/K. Therefore, when the maximum operating temperature becomes high, it becomes difficult for the die bond material such as solder to relax the thermal stress generated between them.

Here, some of the typical solders and other bonding materials that have been conventionally used will be outlined.

(Sn solder)
In-vehicle IGBT modules are Pb-free, Sn-based solder (Sn-based solder) such as SnCu (melting point 228°C), SnAg-based (melting point 221°C), SnAgCu-based (melting point 219°C). , SnSb-based (melting point 240 ℃) solder is used. Further, those Sn-based solders filled with Ni balls to adjust the thickness of the die bond are also used. However, all of these have melting points below 300°C. Moreover, the thermal conductivity is as low as 60 W/mK or less. Furthermore, the electric conductivity is also extremely low at 25% IACS or less. This value is lower than the electrical conductivity of 30% IACS of W used as a heating material in an electric furnace. In addition, IACS (International Annealed Copper Standard) represents the electrical conductivity of various materials with the electrical conductivity of annealed standard annealed copper (volume resistivity: 1.7241×10 ⁻² μΩm) being 100% IACS. Sn has a melting point of 234° C., a thermal conductivity of 66 ppm/m·K, and an electrical conductivity of 15% IACS. Therefore, it is difficult to use the Sn-based solder containing Sn as a main component to release heat emitted from a semiconductor device having a maximum operating temperature of 300° C. or to use for joining such a semiconductor device and an electrode.

(Au solder)
A solder that uses a eutectic of Au and an additive material, which has higher heat resistance than Sn-based solder, is also used. However, AuSi solder containing Si as an additive has a melting point of 370° C., but is brittle, and has a low thermal conductivity of 53 W/m·K and a low electrical conductivity of 22% IACS. The AuGe solder containing Ge as an additive also has a melting point of 356° C., but is brittle, and has a low thermal conductivity of 44 W/m·K and a low electrical conductivity of 17% IACS. In addition, these Au-based solders are expensive and unsuitable for use as a material for joining semiconductor devices having particularly large dimensions.

(Ag wax material)
In addition to the above, there is also a method of joining the semiconductor device and the electrode with Ag wax material having high heat resistance. Ag wax has good properties in that it has high thermal conductivity and high electrical conductivity. However, the melting point of Ag wax material is generally 600° C. or higher, and there is a problem in that when a semiconductor device and an electrode are fusion-bonded using Ag wax material, the semiconductor device is damaged by heat.

(Nano Ag)
Universities, research institutes, companies, and the like have attempted to use new materials in place of the above Sn-based solder, Au-based solder, and Ag solder for die bonding of power semiconductor IGBT modules and LEDs. For example, in Non-Patent Document 1, nano-sized Ag particles (including those generated by reduction of silver oxide) and flake-shaped Ag particles are sintered at a temperature lower than the melting point of the bulk material due to their surface activity. It has been proposed to utilize the low temperature fusion phenomenon of being (low temperature sintered). The sintered body that is sintered by utilizing the low temperature fusion phenomenon of nano Ag does not melt up to the melting point of the bulk material. In this method, at a low temperature of about 300° C., the nano Ag particles are gradually bonded to each other to form secondary particles. When the secondary particles are formed, the particles do not sinter at the low temperature any more, so that the grain boundaries between the secondary particles clearly appear in the microscope image of the sintered body.

In Non-Patent Document 1, a power semiconductor module using nano Ag as a die bond material is the same as the case of using solder as a die bond material based on the result of a heat cycle test in which cooling to -40°C and heating to 125°C are repeated. It is said that some degree of reliability can be obtained. However, at a low temperature as described in Non-Patent Document 1, the secondary particles grown from the nano Ag particles are not sintered, and there are clear grain boundaries and voids of the nanoparticles inside. Therefore, sufficient strength cannot be obtained, and a heat cycle test reaching 300° C. tends to cause cracks and chips starting from the grain boundaries. Therefore, it is difficult to use as a die-bonding material for joining semiconductor devices whose maximum operating temperature reaches 300°C. Further, as described in Non-Patent Document 2, there are problems that it is an expensive material, it is difficult to handle, it is difficult to thicken the die bond, and the bonding strength is not uniform.

(Ag ₃ Sn alloy)
Non-Patent Document 2 discusses the use of Ag ₃ Sn, which is a mixture of fine powders of Ag and Sn, which is sintered by utilizing the low temperature fusion phenomenon as described above, as a die bond material. The Ag ₃ Sn thus produced has few voids and has a high melting point after sintering (hereinafter referred to as “remelting point”) of 480° C. The thermal conductivity is about 70 W/m·K, which is higher than that of conventional solder (60 W/m·K or less). Further, it is also reported that high die shear strength (bonding strength between a semiconductor device and an electrode substrate) can be obtained. However, in the material described in Non-Patent Document 2, brittle Ag ₃ Sn particles are agglomerated at the grain boundaries, and cracks or chips starting from the grain boundaries are likely to occur in the heat cycle test (described later). Further, it is difficult to use it as a die-bonding material because the bonded portion with a semiconductor device or a substrate is easily peeled off.

As described above, various die-bonding materials have been developed, but at present, the die-bonding material and the die-bonding technology for joining the semiconductor devices having the maximum operating temperature of 300° C. have not been established yet. Further, most of the characteristic evaluations of conventional die bond materials are evaluations of the material alone, and do not necessarily consider the state of mounting the semiconductor device bonded to an electrode substrate or the like.

The problem to be solved by the present invention is to provide a semiconductor element bonding member that can be used for bonding a semiconductor element having a maximum operating temperature of 300° C. and a substrate such as an electrode substrate.

(Target characteristic)
In order to sufficiently dissipate the heat generated by a semiconductor device whose maximum operating temperature reaches 300°C, the thermal conductivity of the die bond of the semiconductor device whose maximum operating temperature is 150°C (the thermal conductivity of solder is 60 W/mK It is required to have a thermal conductivity more than twice that of the following), that is, a thermal conductivity of 120 W/m·K or more. In addition, since the semiconductor device may locally generate heat during operation, the heat resistance temperature of the die bond is preferably 500° C. or higher in order to ensure reliability during operation. In the conventional IGBT module, the problem caused by electric conductivity has not yet become apparent, but as the current flowing through the semiconductor device (chip) increases to 100A, 200A, 300A, the module generated at the junction with the semiconductor device Considering that the heat increases in proportion to the square of the current value and the electric resistance value, the electric conductivity is preferably 50% IACS or more.

(Evaluation)
The linear expansion coefficients of the main materials constituting semiconductor devices are 4.1 ppm/K for Si, 4.5 ppm/K for SiC, and 3.2-5.6 ppm/K for GaN, which are all small. On the other hand, Cu, which is a typical electrode material, has a high thermal conductivity of 17 ppm/K. Therefore, the die bond for joining the semiconductor device and the electrode substrate must be capable of relieving a large thermal stress generated during the operation of the semiconductor device due to the difference in linear expansion coefficient between the two. Conventionally, in the development of die bonds, in addition to the characteristics of heat resistance and melting point, it is possible to hold at 300°C for a predetermined time to test for cracks and chips, or to perform a die shear test (shear strength measurement) at room temperature. , Instead of the characteristic evaluation at the time of mounting. In some cases, in addition to these, a test (heat cycle test) has been performed in which cooling to -40°C and heating to 250°C are repeated to confirm whether cracks or chips occur. In the present invention, it is assumed that Ni plating layers are respectively provided on the bonding surfaces of the SiC semiconductor device and the electrodes and die bonding is performed as described later. Therefore, in order to perform a test assuming mounting on an IGBT module, the characteristics at the time of mounting are determined by performing a heat cycle test in which cooling to -40°C and heating to 300°C are repeated with the above-mentioned bonding layer provided. Need to judge. Further, it is required to have the above-mentioned thermal conductivity and electrical conductivity even after the heat cycle test.

(Product form)
The characteristics required of the die bond material differ depending on the size and performance of the semiconductor device, but if the die bond is too thin, the thermal stress generated between the semiconductor device and the electrode may not be sufficiently relaxed. On the other hand, if the die bond is too thick, it becomes difficult to improve the parallelism and the dimensional accuracy, and the characteristics tend to vary. Considering these points, the thickness of the die bond is preferably 0.01 mm or more and 0.3 mm or less.

(Manufacturing history)
Although some conventional bonding examples have a peak temperature at the time of bonding reaching about 350° C., the maximum temperature at the time of bonding is preferably 300° C. or less in order to reliably prevent damage to the semiconductor device. Regarding the limit value of the pressure applied to the semiconductor device mounted on the IGBT module (the maximum value of the pressure that does not cause the destruction of the semiconductor device), no specific value has been reported, but it is applied when the semiconductor device is bonded. The applied pressure is preferably 5 MPa or less, and is preferably as low as possible.

(Study item 1: Material selection)
The present inventors, in the study of the die bond, first, it is possible to sinter at a temperature lower than the melting point of the bulk material, also sufficient thermal conductivity and electrical conductivity after the heat cycle test at -40 ~ 350 ℃. Materials that are expected to have Ag (melting point 961° C., thermal conductivity 105 ppm/m·K, electrical conductivity 110% IACS) based materials were investigated. A melting point of BAg-18 (JIS standard. Ag content: 60 mass%, Cu content: 30 mass%, Sn content: 10 mass%), which is one of Ag waxes manufactured by the melting method. Solidus temperature) is about 671°C. When its thermal conductivity was measured, it was 215 W/m·K and its electrical conductivity was 57% IACS. Each of these exceeds the target value. Although the melting temperature (melting point) of the bulk material is as high as 671° C., it was considered that this can be solved by using the low temperature fusion phenomenon (Non-Patent Document 2) in the pressure sintering method of Ag ₃ Sn composed of Ag and Sn. The low-temperature fusion phenomenon mentioned here is a phenomenon in which the melting point decreases from the melting point of Ag of the bulk material as the Sn content increases, as seen in the phase diagram of Ag and Sn. The method utilizing this low temperature fusion phenomenon is referred to as "low temperature pressure sintering method" in the present specification. The low-temperature fusion phenomenon referred to here is different from the low-temperature fusion phenomenon caused by the surface activity of the particles as seen in nano Ag.

The melting point of Ag is 961°C, the melting point of Sn is 232°C, and the melting point of Cu is 1083°C. Therefore, the melting temperature at the time of joining can be lowered by appropriately changing the content ratio of these. However, it is known that when Sn is mixed with Ag, the thermal conductivity greatly decreases. Further, as described in Non-Patent Document 2, heat of Ag ₃ Sn alloy of 60Ag40Sn (Ag content: 60 weight percent, Sn content: 40 weight percent) produced by a pressure sintering method. It has a low conductivity of 70 W/mK, which is far from the thermal conductivity of BAg-18 (215 W/mK). Furthermore, the thermal conductivity of 60Ag40Sn (Ag content: 60 weight percent, Sn content: 40 weight percent) produced by the melting method is as low as 83 W/mK. On the other hand, the thermal conductivity of 90Ag10Sn (Ag content: 60% by weight, Sn content: 40% by weight) was 310 W/mK, which was extremely high.

Based on these facts, 10 kinds of mixed powder materials (each having an average particle size of 2 μm) were placed between the SiC semiconductor device (having a Ni plating layer on one side) and the electrode (having a Ni plating layer on one side). Samples 1 to 10 in which a die bond having a thickness of 0.2 mm was formed between the SiC semiconductor device and the electrode were prepared by disposing them and maintaining them in a vacuum atmosphere at 300° C. under a pressure of 1 MPa or 5 MPa for 10 minutes. Then, in order to confirm the suitability of use in the mounted state, each remelting temperature was measured, and subsequently, a heat cycle test was performed to judge the pass/fail. Then, the reliability of Samples 1 to 10 was confirmed from the results of the remelting temperature and the heat cycle test. Table 1 shows the compositions of Samples 1 to 10, the pressurization conditions, the remelting temperature, and the results of the heat cycle test.

In the sample 1-3, although there were many voids (voids) inside, cracks and chips did not occur in the heat cycle test. The present inventor has found that this result consists of DBA (coefficient of linear expansion of 7 ppm/K) and Al alloy (coefficient of linear expansion of 21 ppm/K) when omitting the heat dissipation board in the second-generation IGBT module for vehicle installation. The fact that when the cooler (radiator) was joined with Al solder, the joint surface peeled off on the Al plate, while on the Al punching plate (the one in which a large number of through holes were formed in the Al plate material), the joint surface did not peel off. , And that the through holes (voids) formed in the Al punching plate alleviated the stress. In addition, it has been found that voids such as voids and through holes of punching metal, which have been conventionally problematic with solder and Ag ₃ Sn alloys, have the effect of relaxing the thermal stress caused by the difference in linear expansion coefficient between the joining members. .. Then, the present invention was conceived by examining the results of manufacturing and evaluating the semiconductor element bonding member while changing the conditions variously.

The present invention obtained from the above study is a semiconductor element joining member for joining a semiconductor element and a substrate on which the semiconductor element is mounted,
Ag, Cu, and at least one kind of Au and Sn as a main component, consisting of an alloy having a melting point of 500 ℃ or more,
Inside, having a plurality of voids having a total volume of 5% or more and 40% or less,
It is characterized by having a thermal conductivity of 120 W/mK or more and an electrical conductivity of 50% IACS or more after 300 times of a heat cycle test in which cooling to -40°C and heating to 300°C are repeated. ..

The semiconductor element bonding member according to the present invention is mainly composed of at least one kind of Ag, Cu, and Au and Sn, and is composed of an alloy having a melting point of 500° C. or higher. It has sufficient heat resistance as a material for bonding semiconductor devices whose temperature is 300°C or higher.

Further, the total volume has a plurality of voids of 5% or more and 40% or less of the whole inside, deformation of the semiconductor element bonding member is allowed by these voids, and the semiconductor device and a substrate such as an electrode substrate The thermal stress caused by the difference in linear expansion coefficient is relaxed. If the proportion of voids is less than 5% by volume, the effect of relaxing the thermal stress is not sufficient, and if it exceeds 40% by volume, the material itself easily breaks. The shape and number of the voids may be appropriately determined depending on the use environment of the object to be joined, the manufacturing process, etc., but the size of one void is determined by approximating the voids to a sphere of the same volume. The diameter is preferably in the range of 0.1 mm or more and 3 mm or less. If it is smaller than 0.1 mm, the effect of relieving stress tends to decrease. If it is larger than 3 mm, the thermal resistance tends to increase at the position of the void. The size of one void is more preferably 0.2 mm or more and 2 mm or less.

Furthermore, after conducting a heat cycle test in which cooling to -40°C and heating to 300°C are repeated 300 times, the thermal conductivity is 120 W/mK or more, and the electrical conductivity is 50% IACS or more, The heat generated during the operation of the semiconductor device can be efficiently released, and excessive Joule heat is not generated in the semiconductor element joining member. Since the semiconductor element bonding member according to the present invention has these requirements, it can be used for bonding a semiconductor device whose maximum temperature during operation reaches 300° C. and a substrate on which the semiconductor device is mounted.

The semiconductor element bonding member according to the present invention preferably has a Sn content of 2% by weight or more and 20% by weight or less. According to the results of the test conducted by the present inventor variously set the content of Sn, the Ag plate material provided with a plurality of through holes, the content of Sn is in the range of 2% by weight to 20% by weight of the whole. The Sn plates melted on the surface of the Ag plate are alloyed with Ag by stacking Sn plates of the size adjusted so that they are heated above the melting point of Sn (eg 300°C) and then applying a pressure of 0.5 to 5 MPa. As a result, a semiconductor element bonding member satisfying the above requirements such as a melting point of 500° C. or higher could be obtained. In the present specification, this method is referred to as “melt reaction method”. As can be seen from the phase diagram of Ag, Cu, or Au and Sn, when the Sn content is as low as 20% by weight or less, the formation of eutectic substances is suppressed. The presence of eutectic at grain boundaries is likely to be the origin of cracks. By setting the Sn content in the above range, it becomes difficult for eutectic to exist at the grain boundaries. Thereby, generation of cracks can be suppressed and durability can be improved. On the other hand, if the Sn content is less than 2 weight percent, the low-temperature fusion phenomenon (the phenomenon in which the melting point decreases from the melting point of Ag of the bulk material as the Sn content increases) does not sufficiently appear, and the semiconductor does not melt at low temperatures. It becomes difficult to manufacture the element bonding member. The characteristics of the semiconductor element bonding member after manufacturing differ depending on the conditions such as the pressure applied during manufacturing. The range of the Sn content and the pressure condition at the time of production are examples, and can be appropriately changed as long as the above characteristics are satisfied.

By using the semiconductor element bonding member according to the present invention, a semiconductor device having a maximum operating temperature of 300° C. and an electrode substrate or the like on which the semiconductor device is mounted can be bonded. Further, in the semiconductor element bonding member according to the present invention, expensive nano Ag does not necessarily have to be used. Furthermore, the technology and equipment cultivated up to now for soldering can be used.

In the solder, generally, when 5% or more of voids (voids) are present, the voids become the starting points in the heat cycle test, and the eutectic alloy portions with low strength existing at the grain boundaries are chained and broken. Further, also in Ag ₃ Sn, when a void is present, the void becomes a starting point in the heat cycle test, and the portion of the Ag ₃ Sn eutectic alloy with low strength existing in the grain boundary is chained and broken. In the case of nano Ag, the primary particles are sintered at a temperature lower than the melting point of Ag of the bulk material, but the secondary particles formed by sintering do not sinter at a temperature lower than the melting point of Ag of the bulk material. Grain boundaries occur. When such voids are present, the voids become the starting points in the heat cycle test, and the cracks of the secondary particles having low strength are chained and destroyed.

In the conventional die bond, if there were voids such as voids, there was a problem that the cracks would be chained and broken starting from there, and the heat cycle could not be passed, so research and development to reduce voids such as voids as much as possible has been done. .. However, according to the findings found by the present inventor, even if there are voids and the like, if the strength of the alloy is sufficiently high, it passes the heat cycle test, and also the thermal conductivity and the electrical conductivity after the heat cycle test. Have the required properties for.

The present invention is based on the idea opposite to the conventional material development that eliminates defects such as voids so far, and by surrounding the voids with a strong material, the voids do not become the origin of defects. The voids are used for relaxing thermal stress.

FIG. 3 is a configuration diagram showing a state in which a semiconductor device and an electrode member are joined by an embodiment of a semiconductor element joining member according to the present invention.

The semiconductor element bonding member according to the present invention is as described above, but its technical idea can be generalized. Specifically, the technical idea of the present invention is to provide a semiconductor element bonding member for bonding a semiconductor element and a substrate on which the semiconductor element is mounted,
An alloy containing a first metal and a second metal having a melting point lower than that of the first metal as main components, a content of the second metal of 2% by weight or more and 20% by weight or less, and a melting point of 500° C. or more. Consists of
Inside, having a plurality of voids having a total volume of 5% or more and 40% or less,
Satisfies the requirement that the thermal conductivity is 120W/mK or more and the electrical conductivity is 50%IACS or more after the heat cycle test in which cooling to -40℃ and heating to 300℃ are repeated 300 times. Can be expressed as

Examples of the semiconductor element bonding member according to the present invention will be described. The semiconductor element bonding member 10 of this embodiment is a so-called die bond and is used for bonding the semiconductor device 11 to a substrate such as the electrode substrate 12 as shown in FIG. The semiconductor element joining member 10 of the present embodiment is one in which voids (voids) 102 are provided in a predetermined ratio inside an alloy 101. Note that, in FIG. 1, the structure of the semiconductor element bonding member 10 in the case of being manufactured by introducing the second metal into the through hole provided in the plate material of the first metal, that is, an example in which the voids 102 are arranged in the vertical direction of the drawing. Although noted, the voids 102 may be randomly located inside the alloy 101. Further, it is not necessary that the size and shape of the voids are constant. Further, it is not always necessary that the voids (voids) 102 are uniformly distributed over the entire semiconductor element bonding member 10. For example, if there is a place where stress is likely to increase during operation, many voids are concentrated in that place. It may be arranged in a desired manner.

(Core material of the first metal)
The core material is composed of a first metal, which is one or more of Ag, Cu, Au, and alloys thereof, for example. A metal having a high melting point, a high thermal conductivity, and a high electrical conductivity is used as the first metal. Particularly, Ag can be preferably used as the first metal. On the other hand, by using Cu, the amount of Ag used can be reduced and a semiconductor element bonding member can be manufactured at low cost. The shape at the time of use may be plate-like or powder-like. If a plate-shaped member is used, a high-strength semiconductor element bonding member can be manufactured, and the manufacturing itself becomes easy. By using a powdery material, voids (voids) formed inside the semiconductor element bonding member can be uniformly distributed.

When using a plate-shaped material, for example, a material having a thickness of 0.02 to 0.3 mm can be used. When a plate-shaped member is used, holes having a size and number corresponding to the void ratio to be formed inside the semiconductor element bonding member to be obtained are formed in advance. The perforation can be performed by, for example, laser processing, drill processing, etching processing, punching processing.

When a powdery material is used, for example, a particle diameter in the range of 10 nm to 0.3 mm can be used. The powder used may have a uniform size, or may be a mixed powder having different particle sizes. The pressure sintering method, the impregnation method, and the core material manufacturing method are not limited as long as the purpose can be achieved as the core material. Although details of the manufacturing method will be described later, for example, a core material containing voids can be manufactured by heating and sintering at 900° C. in a hydrogen atmosphere.

(Second metal)
It is a metal (corresponding to the second metal) with which the core material is impregnated, and for example, Sn can be preferably used. The ratio of the second metal is preferably in the range of 2% by weight or more and 20% by weight or less of the semiconductor element joining member to be obtained, although it depends on the pressure applied when the semiconductor element joining member is manufactured. As a result, no problem occurs in the heat cycle test, and the required characteristics can be obtained. Further, in addition to the first metal and the second metal, one or more of Zn, Sb, Ni, Mn, Ti, In, Mo, Si, V, Ge and Li may be further contained as an additive metal.

(Parts to be joined)
One of the members to be joined is a semiconductor device, and the other is a substrate (for example, an electrode substrate) on which the semiconductor device is mounted. Conventionally, when these are joined by solder, a metal layer made of Ni, Pt, Co or the like is provided on the joint surface. An IGBT module often has a Ni layer with a thickness of about 2 μm. In addition to Ni, a metal layer made of Ti, W, Co or the like may be provided on the bonding surface of the electrode substrate or the heat dissipation substrate. Furthermore, when joining with an Ag brazing material, a metal layer made of Ni, Pt, Co or the like may be provided in order to prevent reaction with the Ag brazing material. In many cases, electrolytic Ni plating, which is a Ni-based plating, electroless Ni-P, Ni-B, or the like is used. In addition, one or more plating layers of Ag, Au, Cu, Zn, etc. may be provided on each of the above layers. When the semiconductor device and the base material are bonded by the semiconductor element bonding member according to the present invention, each layer can be appropriately used as described above.

(Process of alloying and joining)
Die bonding is required not only to bond the semiconductor device and the substrate, but also to transfer the heat to the cooler by die bonding. For that purpose, it is necessary that the bondability with the members to be bonded and the heat transfer property are high. This object was achieved by using an alloy structure containing Ag and Sn as main components and having voids inside. There are various methods for producing this alloy, such as a pressure sintering method, an infiltration method, and a method of reacting molten Sn with an Ag plate (hereinafter referred to as “Ag plate Sn reaction method”). The manufacturing method is not limited as long as the purpose can be achieved. Further, not only a single method but also a plurality of methods may be combined.

The pressure sintering method uses a mixed powder of Ag, Sn, etc., and melts Sn to form an alloy while pressurizing, while joining a semiconductor device and a cooler. Further, in the infiltration method, Sn is placed above and below the skeleton of Ag, and the semiconductor device and the cooler are joined while melting and alloying Sn, and the target can be achieved with low pressure. Further, in the Ag plate Sn reaction method, the semiconductor device and the cooler are joined while melting the Sns arranged above and below and reacting with Ag to form an alloy, and the AgSn alloy with the highest strength can be obtained. Further, the target can be achieved with a low pressure. In addition, in order to smooth the surface of the alloy and improve the bondability with the object to be bonded, one or more plating layers made of Ag or/and Sn may be provided on the surface of the prepared alloy.

When the plate-shaped first metal is used, the second metal is arranged by, for example, disposing plate materials of the second metal above and below the core material, or plating the surface of the core material with the second metal. be able to. When the powdery first metal is used, the powder of the first metal and the powder of the second metal may be mixed and sintered to produce a skeleton of the mixed powder. As a result, the second metal and the first metal can be effectively impregnated with Sn. Alternatively, the bonding surface of the semiconductor device and/or the bonding surface of the substrate (electrode substrate or the like) may be plated with the second metal, and they may be arranged above and below the core material. Even if one or a plurality of plating layers made of Ni, Ag, Ti or the like are formed on the bonding surface of the semiconductor device and/or the bonding surface of the substrate before the second metal is plated on the bonding surface. Good. In particular, by forming the Ni plating layer, the bondability with the AgSn alloy can be improved.

When performing metal joining, reaction, sintering, impregnation, etc., it is fundamental to optimize conditions such as temperature, pressure, holding time, etc. to produce an alloy with a good joining state, and also in this example. The same is true. When an alloy containing the first metal and the second metal as main components is produced by the impregnation method, the second metal is melted and flows into the skeleton hole made of the first metal due to the capillary phenomenon. The weight of the device is sufficient. When the melted second metal enters the hole of the first metal, the first metal gradually dissolves from the surface of the hole, and the second metal is impregnated inside the core material of the first metal. Similarly, on the surface of the core material, the first metal is gradually dissolved and impregnated with the second metal. Further, when the thickness is controlled with high accuracy, pressure may be applied. On the other hand, if excessive pressure is applied, the semiconductor element may be damaged, so the applied pressure is preferably 5 MPa or less, more preferably 0.5 to 4.0 Mpa. The second metal melted by the impregnation reacts with the first metal forming the core material to be alloyed, whereby the semiconductor device and the electrode substrate are die-bonded with high strength. Also, when the mixed powder of the first metal and the second metal is used, the second metal is melted to be alloyed, whereby the semiconductor device and the electrode substrate are die-bonded with high strength.

The melting point of the semiconductor element bonding member of this embodiment is set to 500° C. or higher because heat may be locally generated during the operation of the semiconductor device. Also, in the case of AgSn alloy, brittle Ag ₃ Sn particles agglomerate at grain boundaries in alloys with a melting point of 500°C or lower, causing damage such as cracks and chips in the heat cycle test, and lowering properties such as thermal conductivity. There is also the problem of As can be seen from the phase diagram of Ag and Sn, and as shown in Examples and Comparative Examples described later, in the case of AgSn alloy, if the Sn content is 2 wt% or more and 20 wt% or less, by utilizing the low temperature fusion phenomenon A semiconductor element joining member having the above-mentioned required characteristics can be obtained.

Die bonding can be performed in a vacuum atmosphere, a non-oxidizing atmosphere, a nitrogen atmosphere, a hydrogen atmosphere, a hydrogen-nitrogen atmosphere, or the like. Although the melting point of Sn is 235° C., the re-melting point of AgSn alloy becomes 500° C. or higher by reacting with Ag to form an alloy.

(Evaluation 1: Reliability)
In this example, Sn was melted and alloyed while applying the own weight of the semiconductor device. In the process, a part of Sn comes out to the outer circumference, so the reliability of the joining was secured by managing the state.

(Evaluation 2: Heat resistance evaluation)
The test piece was heated to 500° C., and it was confirmed whether or not the joint was melted. The one in which no dissolution was observed at the joint was regarded as acceptable. In addition, a heat cycle test was performed on a material in which dissolution was not observed in the bonded portion.

(Evaluation 3: heat cycle test)
In each of the examples described below, a heat cycle test was performed assuming bonding of semiconductor devices with a maximum operating temperature of 300°C. In the heat cycle test, the bonding surface of the 12 mm square, 0.3 mm thick SiC semiconductor device was plated with Ni and Sn, and the bonding surface of the 30 mm square, 1.5 mm thick Cu electrode substrate was bonded with Ni and Sn. The one subjected to the plating treatment was placed on both sides, and each joining surface was joined with a die bond having a thickness of 0.2 mm. Then, every time the cooling to -40°C and the heating to 300°C were repeated 100 times, the test of confirming the state of the joint was performed a total of 3 times (that is, cooling and heating were performed 300 times in total). Those that did not cause problems such as cracks and chips in the heat cycle test were accepted, and those that had cracks and chips were rejected.

(Evaluation 4: thermal conductivity)
A test piece with a diameter of 10 mm and a thickness of 2.0 mm was cut out from the one that passed the heat cycle test (hereinafter referred to as "passed product") with a laser processing machine, and a heat conduction measuring instrument (Advance Riko FTC-RT) was used. The thermal conductivity was measured by the laser flash method used. Separately from this test piece, a SiC comparison piece (having a Ni plating layer on one side) and a Cu comparison piece (having a Ni plating layer on one side) having a diameter of 10 mm and a thickness of 2.0 mm were prepared. The thermal conductivity was measured in the same manner as above. Then, the thermal conductivity of the semiconductor element bonding member (die bond) included in the test piece was determined by comparing the thermal conductivity of the test piece with the thermal conductivity of the SiC comparative piece and the Cu comparative piece. In this evaluation, a thermal conductivity of 120 W/m·K was used as a standard, and one having a thermal conductivity of more than this was regarded as a pass.

(Evaluation 5: electric conductivity)
Since SiC is a semiconductor, it is difficult to measure the electrical conductivity of the test piece used for the heat cycle test (a SiC semiconductor device and a Cu electrode substrate bonded together). Therefore, for the test piece having a thermal conductivity of 120 W/mK or more, a W plate material having a linear expansion coefficient (4.5 ppm/K) similar to that of the SiC semiconductor device was used instead of the SiC semiconductor device, A test piece for measuring electric conductivity was prepared. Then, after conducting a heat cycle test similar to the above, the electrical conductivity was measured. All the test pieces for electrical conductivity measurement corresponding to the passed products in the test pieces using the SiC semiconductor device passed the heat cycle test.

When measuring the electrical conductivity, a laser processing machine cuts out a test piece with a diameter of 10 mm and a thickness of 2.0 mm, and the electrical conductivity is measured by the four-terminal method using an electrical conductivity measuring device (RT70V manufactured by Napson Corporation). did. Separately from this test piece, a W comparison piece (having a Ni plating layer on one side) and a Cu comparison piece (having a Ni plating layer on one side) having a diameter of 10 mm and a thickness of 2.0 mm were prepared. The electrical conductivity was measured in the same manner as above. Then, the electrical conductivity of the test piece was determined by comparing the electrical conductivity of the test piece with the electrical conductivity of the W comparative piece and the Cu comparative piece. In this evaluation, an electric conductivity of 50% IACS was used as a standard, and a material having an electric conductivity of the above was regarded as acceptable. A method of measuring eddy currents with a sigma tester, which is widely used in the measurement of electrical conductivity, was also examined. The electrical conductivity was measured by the four-terminal method because it was judged that it was not suitable for the measurement of conductivity.

Next, the manufacturing procedure of Examples 1 to 15 will be described. The value of each parameter is the value related to Example 2. Examples 1 and 3 to 15 were produced by appropriately changing the parameter values as shown in Table 2 below.

(Producing procedure of Examples 1 to 15)
Step 1: A 12 mm square Ag plate material having a thickness of 0.2 mm and one through hole having a diameter of 0.36 mm per 1 mm square was opened by laser processing (hereinafter referred to as a core material).
Process 2: A 30 μm square, 1.5 mm thick Cu plate material was provided with a 2 μm thick Ni plating layer on one surface (joint surface), and a 12 mm square, 0.009 mm thick Sn plating layer was provided in the center thereof. The thing (henceforth this is called an electrode substrate) was produced.
Process 3: 12 mm square, a 2 μm-thick Ni plating layer is provided on one surface (bonding surface) of the SiC plate material, and a 0.009 mm-thick Sn plating layer is further provided thereon (hereinafter referred to as a semiconductor device. Called a plate).
Step 4: A laminated body in which the electrode substrate, the core material, and the semiconductor device plate are sequentially stacked is manufactured.
Step 5: The laminate was heated to 300° C. in a vacuum atmosphere, kept at 300° C., a pressure of 1 MPa was applied, kept for 5 minutes and gradually cooled.
Step 6: A heat resistance test, a heat cycle test, a measurement of thermal conductivity, and a measurement of electrical conductivity were performed on the semiconductor device plate and the electrode substrate joined by the above treatment.

The void ratios shown in Table 2 below will be described below. For the sake of clarity, the size of the core material will be described as 1 mm square.

In Example 1, the void ratio is 5 vol% and the Sn content is 3.7 wt% (5 vol%).
When 10vol% voids are formed on a 1mm square, 0.2mm thick plate, the Ag volume is 1mm × 1mm × 0.2mm × 0.9=0.18mm ³ , and the weight is 1.888μg (Ag density: 10.49g/cm ^-3 ). In Example 1, a 0.005 mm-thick Sn layer was formed on each bonding surface of the electrode substrate and the semiconductor device plate, the volume of Sn was 1 mm×1 mm×0.005 mm×2=0.01 mm ³ , and the weight was 0.073 μg ( Sn density: 7.31 g/cm ^-3 ). The total volume of Ag and Sn is 0.19 mm ³ , and the total weight is 1.961 μg. Here, the Sn content is 0.01/0.19=0.052 (5.2 vol%) and 0.073/1.961=0.037 (3.7 wt%).

The volume of voids formed in the core material is 1 mm × 1 mm × 0.2 mm × 0.1 = 0.02 mm ³ . Since a volume of 0.01 mm ³ of Sn is introduced into this to form an AgSn alloy, the finally remaining void becomes 0.01 mm ³ . Therefore, the void ratio inside the semiconductor element bonding member having a volume including voids of 0.2 mm ³ is 5 vol %.

As described above, in order to manufacture a semiconductor element bonding member with a Sn content of 3.7 wt% (5 vol%) and a void ratio of 5 vol%, a 10% void is formed on a plate material with a 1 mm square and a thickness of 0.2 mm. It can be seen that it is sufficient to form a 0.005 mm thick Sn layer. If the voids formed in the plate material are approximated to cylindrical through holes, it is understood that one through hole having a diameter of 0.36 mm should be provided for each 1 mm square.

In Example 2, the void ratio is 10 vol% and the Sn content is 7.2 wt% (10 vol%).
If a 19 vol% void is formed on a 1 mm square, 0.2 mm thick plate material, the Ag volume will be 1 mm × 1 mm × 0.2 mm × 0.81 = 0.162 mm ³ , and the weight will be 1.699 μg (Ag density: 10.49 g/cm ^-3 ). In Example 2, a 0.009 mm-thick Sn layer was formed on each bonding surface of the electrode substrate and the semiconductor device plate, the volume of Sn was 1 mm×1 mm×0.009 mm×2=0.018 mm ³ , and the weight was 0.132 μg ( Sn density: 7.31 g/cm ^-3 ). The total volume of Ag and Sn is 0.18 mm ³ , and the total weight is 1.831 μg. Here, the Sn content is 0.018/0.18=0.1 (10.0 vol%) and 0.132/1.831=0.072 (7.2 wt%).

The void volume formed in the core material is 1 mm×1 mm×0.2 mm×0.19=0.038 mm ³ . This, because the Sn volume 0.018 mm ³ is AgSn alloy is introduced is formed, voids which finally remains is the 0.02 mm ^3. Therefore, the void ratio inside the semiconductor element bonding member having a volume including voids of 0.2 mm ³ is 10 vol %.

As described above, in order to fabricate a semiconductor element bonding member with a Sn content of 7.21 wt% (10 vol%) and a void ratio of 10 vol%, 19 vol% voids were formed on a 1 mm square, 0.2 mm thick plate material. It can be seen that it is sufficient to form a Sn layer having a thickness of 0.009 mm. If this void is approximated to a cylindrical through hole, it will be understood that one through hole having a diameter of 0.35 mm should be provided for each 1 mm square.

Although only the first and second embodiments have been described in detail here, the diameter of the through hole may be determined by the same method as described above for other embodiments (and comparative examples). The core material of Example 9 (AgCu described in Table 2) is an alloy containing 30% by weight of Ag and 70% of Cu. Further, in this embodiment, the ratio of the voids is determined in advance, and the size of the material used and the size of the through-hole to be formed in advance are determined. However, the voids (voids) of the semiconductor element bonding member after the fabrication are determined. The ratio of can be evaluated by various measurements. For example, the cross section of the semiconductor element joining member is photographed by an electron microscope or the like, and the proportion of the voids that the semiconductor element joining member has is evaluated by using the proportion of the voids appearing in the cross section as a representative value. The ratio of the voids in the semiconductor element bonding member can be evaluated from the theoretical density of the non-alloy and the density of the manufactured semiconductor element bonding member.

Table 2 shows the produced Examples 1 to 15 and their evaluation results, and the Comparative Examples 1 to 9 produced for comparison and their evaluation results. In Comparative Example 1, the semiconductor device and the electrode substrate could not be joined, and in Comparative Example 6, the powder was not sintered, so that neither test piece could be produced. Further, in Comparative Examples 2 to 5 and 7 to 9, the test pieces could be produced, but when the sample was heated to 500° C., dissolution was observed in the joint portion, and therefore the heat cycle test was not performed. On the other hand, in each of Examples 1 to 15, no melting was observed at the joint even when heated to 500° C., the thermal conductivity after the heat cycle test was 120 W/m·K or more, and the electrical conductivity was 50%. More than IACS.

As described above, the semiconductor element joining member of each of the above-described embodiments satisfies the requirements required when joining a semiconductor device having a maximum operating temperature of 300° C. to a substrate. Conventionally, voids inside a semiconductor element bonding member have been considered to be defects, and development of void-free materials has been advanced. However, the present invention has found that voids are effective in alleviating thermal stress. ..

Each of the above examples is an exemplification of a specific embodiment, and can be appropriately modified in accordance with the gist of the present invention. For example, since the characteristics of the semiconductor element bonding member after manufacturing differ depending on conditions such as pressure applied during manufacturing, the range of the Sn content in each of the above examples and the pressure condition during manufacturing are the semiconductor element bonding member. It can be appropriately changed as long as the required characteristics required for the above are satisfied.

In addition, this semiconductor element bonding member is used for modules in the field of semiconductors (communication, arithmetic, memory, lasers, LEDs, sensors, etc.) of the plane conduction type other than the junction with the power semiconductor module vertical conduction type IGBT electrode substrate (conduction). It can also be suitably used in a heat dissipation board (non-energized). Further, in the IGBT module, it is also possible to use semiconductor devices such as Si, GaN, GaAs other than the SiC semiconductor device mounted. This will greatly contribute to the miniaturization and high performance of semiconductor modules and cost reduction in the future. Further, in the present specification, the semiconductor module has been mainly described, but the semiconductor element bonding member according to the present invention can be similarly used for the semiconductor package.

10... Semiconductor element joining member 101... Core material 102... Void 11... Semiconductor device 12... Electrode substrate

Claims (4)

A semiconductor element joining member for joining a semiconductor element and a substrate on which the semiconductor element is mounted,
Ag, Cu, and at least one kind of Au and Sn as a main component, consisting of an alloy having a melting point of 500 ℃ or more,
Inside, having a plurality of voids having a total volume of 5% or more and 40% or less,
It is characterized by having a thermal conductivity of 120 W/mK or more and an electrical conductivity of 50% IACS or more after conducting a heat cycle test in which cooling to -40°C and heating to 300°C are repeated 300 times. Semiconductor element joining member. The semiconductor element bonding member according to claim 1, wherein the Sn content is 2% by weight or more and 20% by weight or less of the whole. A semiconductor module comprising the semiconductor element bonding member according to claim 1. A semiconductor package comprising the semiconductor element bonding member according to claim 1.

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