JP2020095186A - Semiconductor device - Google Patents

Abstract

To improve the reliability of a semiconductor device having an optical waveguide.SOLUTION: A semiconductor comprises a first insulator layer, an optical waveguide, a second insulator layer, and a heater. The optical waveguide and the second insulator layer are formed on the first insulator layer. The second insulator layer has a groove. The heater is formed so as to be spaced from the optical waveguide. The heater has a first extension portion, a second extension portion, and a connection portion. The first extension portion is formed so as to cross the optical waveguide in a plan view. The second extension portion is formed so as to be in parallel with the first extension portion in a plan view. The connection portion electrically connects the first extension portion and the second extension portion.SELECTED DRAWING: Figure 3

Description

The present invention relates to a semiconductor device, for example, a semiconductor device having an optical waveguide.

Silicon photonics technology is known as an optical communication technology. A semiconductor device adopting the silicon photonics technology includes, for example, a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, an optical waveguide formed on the first insulating layer, and a thermal control type optical device. And a modulator (see, for example, Patent Document 1).

The light modulation unit described in Patent Document 1 has a heater formed directly above the optical waveguide and separated from the optical waveguide. The shape of the heater in plan view is a rectangular shape formed so as to overlap a part of the optical waveguide in plan view (see, for example, FIG. 17 described later). The heater heats the optical waveguide by the Joule heat generated by the heater and modulates the phase of light passing through the inside of the optical waveguide.

JP, 2017-181849, A

Examples of heater characteristics include heat capacity. The heat capacity of the heater is preferably large from the viewpoint of realizing stable heat supply to the optical waveguide regardless of the influence from the external environment. However, with a heater having a rectangular shape in plan view, it is difficult to adjust the heat capacity of the heater, and desired heater characteristics may not be realized. From the viewpoint of improving the reliability of semiconductor devices, there is room for improvement.

An object of the present invention is to improve the reliability of a semiconductor device. Other problems and novel features will be apparent from the description of the present specification and the drawings.

A semiconductor device according to one embodiment includes a first insulating layer, an optical waveguide formed on the first insulating layer, a second insulating layer having a groove formed on the first insulating layer, A heater formed in the groove so as to be separated from the optical waveguide. The heater has a first extending portion formed to cross the optical waveguide in a plan view, and a second extending portion formed to be in parallel with the first extending portion in a plan view, A connecting portion electrically connecting the first extending portion and the second extending portion.

In the semiconductor device according to the embodiment, the reliability of the semiconductor device having the optical waveguide can be improved.

FIG. 1 is a block diagram showing an example of the circuit configuration of the opto-electric hybrid device according to the first and second embodiments. FIG. 2 is a main part plan view showing an example of the configuration of the semiconductor device according to the first embodiment. FIG. 3 is a partially enlarged view of the area surrounded by the alternate long and short dash line shown in FIG. FIG. 4 is a main-portion cross-sectional view showing an example of the structure of the semiconductor device in Embodiment 1. FIG. 5 is a main-portion cross-sectional view showing an example of the structure of the semiconductor device in Embodiment 1. FIG. 6 is a main-portion cross-sectional view showing an example of the steps included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 7 is a main-portion cross-sectional view showing an example of the steps included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a fragmentary cross-sectional view showing an example of steps included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 9 is a main-portion cross-sectional view showing an example of the steps included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a main-portion cross-sectional view showing an example of the steps in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 11 is a main-portion cross-sectional view showing an example of the steps included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 12 is a main-portion cross-sectional view showing an example of the steps in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 13 is a main-portion cross-sectional view showing an example of the steps in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 14 is a main-portion cross-sectional view showing an example of the steps included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 15 is a main-portion cross-sectional view showing an example of the steps included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 16 is a fragmentary cross-sectional view showing an example of a step included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 17 is a main-portion cross-sectional view showing an example of the steps in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 18 is a fragmentary cross-sectional view showing an example of a step included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 19 is a main-portion cross-sectional view showing an example of the steps in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 20 is a fragmentary cross-sectional view showing an example of a step included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 21 is a main-portion cross-sectional view showing an example of the steps in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 22 is a main-portion cross-sectional view showing an example of the steps in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 23 is a main-portion cross-sectional view showing an example of the steps included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 24 is a fragmentary cross-sectional view showing an example of a step included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 25 is a fragmentary cross-sectional view showing an example of a step included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 26 is a main-portion cross-sectional view showing an example of the steps included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 27 is a main-portion cross-sectional view showing an example of the steps included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 28 is a main-portion cross-sectional view showing an example of the steps in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 29 is a fragmentary cross-sectional view showing an example of a step included in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 30 is a main-portion cross-sectional view showing an example of the steps in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 31 is a main-portion cross-sectional view showing an example of the steps in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 32 is a principal part plan view showing an example of the configuration of a semiconductor device according to a comparative example. FIG. 33 is a main-portion cross-sectional view showing an example of the structure of a semiconductor device according to a comparative example. FIG. 34 is a main-portion cross-sectional view showing an example of the structure of a semiconductor device in a comparative example. FIG. 35 is a partial enlarged cross-sectional view showing an example of the configuration of the semiconductor device according to the first modification of the first embodiment. FIG. 36 is a partial enlarged cross-sectional view showing an example of the configuration of the semiconductor device according to the second modification of the first embodiment. FIG. 37 is a main-portion plan view showing an example of the structure of the semiconductor device in Embodiment 2. 38 is a main-portion plan view showing an example of the structure of the semiconductor device in Embodiment 2. FIG. FIG. 39 is a main-portion cross-sectional view showing an example of the structure of the semiconductor device in Embodiment 2. FIG. 40 is a main-portion cross-sectional view showing an example of the structure of the semiconductor device in Embodiment 2.

Hereinafter, a semiconductor device according to one embodiment will be described in detail with reference to the drawings. In the specification and the drawings, the same or corresponding constituent elements are designated by the same reference numerals, and duplicated description will be omitted. Further, in the drawings, the configuration may be omitted or simplified for convenience of description. Moreover, at least a part of each embodiment and each modified example may be arbitrarily combined with each other.

[Embodiment 1]
In the semiconductor device SD1 according to the first embodiment, the first extending portion EXP1, the second extending portion EXP2, and the connecting portion CNP forming the heater HT1 are formed integrally with each other.

(Circuit configuration of the opto-electric hybrid device)
FIG. 1 is a block diagram showing an example of a circuit configuration of the opto-electric hybrid device LE1 according to the first embodiment.

As shown in FIG. 1, the opto-electric hybrid device LE1 (LE2) has a first electronic circuit EC1, a semiconductor device SD1 (SD2), an optical waveguide OW, a light source LS, and an IC chip CP. The semiconductor device SD1 according to the first embodiment has a light modulation unit LM1 (LM2), a light output unit LO, a light input unit LI, and a light receiving unit PR. The IC chip CP has a second electronic circuit EC2 and a third electronic circuit EC3. Details of the configuration of the semiconductor device SD1 will be described later. The opto-electric hybrid device LE2, the semiconductor device SD2, and the optical modulator LM2 will be described in the second embodiment.

The first electronic circuit EC1 outputs electric signals (control signals) for controlling the second electronic circuit EC2 and the third electronic circuit EC3, respectively. The first electronic circuit EC1 also receives the electrical signal output from the third electronic circuit EC3. The first electronic circuit EC1 is electrically connected to the second electronic circuit EC2 and the third electronic circuit EC3. The first electronic circuit EC1 is configured by, for example, a known Central Processing Unit (CPU) including a control circuit and a storage circuit or a field-programmable gate array (FPGA).

The light source LS emits light. Examples of the type of the light source LS include a laser diode (LD). The wavelength of the emitted light from the light source LS may be set so that the emitted light can pass through the inside of the optical waveguide OW and can be appropriately set according to the material forming the optical waveguide OW. For example, the peak wavelength of the light emitted from the light source LS is 1.0 μm or more and 1.6 μm or less. The light source LS is optically connected to the light modulator LM1.

The second electronic circuit EC2 outputs an electric signal (control signal) for controlling the operation of the light modulator LM1. More specifically, the second electronic circuit EC2 controls the light modulator LM1 based on the control signal received from the first electronic circuit EC1. The second electronic circuit EC2 is electrically connected to the light modulator LM1. The second electronic circuit EC2 is composed of, for example, a known transceiver IC including a control circuit.

The light modulator LM1 modulates the phase of the light emitted from the light source LS based on the control signal received from the second electronic circuit EC2. The light modulator LM1 generates an optical signal including the information included in the control signal. Examples of the type of the light modulator LM1 include a Mach-Zehnder type light modulator and a ring type light modulator. The light modulator LM1 may be an electrically controlled light modulator, a heat controlled light modulator, or a combined light modulator that uses both electrical control and thermal control. Good. The light modulator LM1 according to the present embodiment is a heat control type light modulator. The light modulator LM1 is optically connected to the light output unit LO via the optical waveguide OW.

The optical output unit LO outputs the optical signal modulated by the optical modulator LM1 to the outside of the semiconductor device SD. For example, the light output unit LO emits an optical signal toward an external optical fiber. Examples of the type of light output unit LO include a grating coupler (GC), a spot size converter (SSC), and a mirror.

The light input unit LI inputs light from the outside into the semiconductor device SD1. For example, an optical signal emitted from an external optical fiber is input into the semiconductor device SD1. Examples of types of the light input unit LI include a grating coupler (GC) and a spot size converter (SSC). The light input section LI is optically connected to the light receiving section PR via an optical waveguide.

The light receiving section PR generates electron-hole pairs based on the optical signal received from the light input section LI. The light receiving section PR converts an optical signal into an electric signal. The light receiving part PR only needs to have photoelectric conversion characteristics. Examples of the type of the light receiving section PR include an avalanche photodiode type light receiving section. The light receiving portion PR is electrically connected to the third electronic circuit EC3.

The third electronic circuit EC3 processes the electric signal received from the light receiving unit PR, and outputs the processed electric signal to the first electronic circuit EC1. More specifically, the third electronic circuit EC3 amplifies the electric signal received from the light receiving unit PR and outputs the amplified electric signal to the first electronic circuit EC1. The third electronic circuit EC3 is composed of, for example, a known receiver IC including an amplifier circuit.

(Operation of opto-electric hybrid device)
Next, an operation example of the optical-electrical hybrid device LE1 according to the first embodiment will be described.

First, the transmitting portion of the optical-electrical hybrid device LE1 will be described. The light emitted from the light source LS reaches the light modulator LM1 via the optical waveguide OW. The second electronic circuit EC2 controls the operation of the light modulator LM1 based on the control signal received from the first electronic circuit EC1, and modulates the light that has reached the light modulator LM1. As a result, the electric signal is converted into an optical signal. Then, the optical signal reaches the optical output unit LO via the optical waveguide OW and is emitted to the outside of the semiconductor device SD1 at the optical output unit LO. The optical signal output from the semiconductor device SD1 is guided to another semiconductor device via an optical fiber or the like.

Next, the receiving portion of the optical-electrical hybrid device LE1 will be described. An optical signal guided from another semiconductor device via an optical fiber or the like reaches the optical input unit LI. The optical signal is guided to the inside of the optical waveguide OW at the optical input unit LI. The optical signal reaches the light receiving portion PR via the optical waveguide OW and is converted into an electric signal. Then, the electric signal is processed by the third electronic circuit EC3 and then transmitted to the first electronic circuit EC1.

(Structure of semiconductor device)
Next, the configuration of the semiconductor device SD1 according to the first embodiment will be described.

2 to 5 are schematic diagrams showing an example of the configuration of the semiconductor device SD1 according to the first embodiment. 2 is a plan view of an essential part of the semiconductor device SD1, and FIG. 3 is a partial enlarged view of a region surrounded by a dashed line shown in FIG. 4 is a sectional view of the semiconductor device SD1 taken along the line AA in FIG. 2, and FIG. 5 is a sectional view of the semiconductor device SD1 taken along the line BB in FIG. 2 and 3, part of the multilayer wiring layer MWL is omitted.

As shown in FIGS. 2 to 5, the semiconductor device SD1 has a substrate SUB, a first insulating layer CL, a light modulation section LM1, a light receiving section PR, and a multilayer wiring layer MWL. Although details will be described later, the light modulation unit LM1 according to the first embodiment has optical waveguides OW1 and OW2 and a heater HT1.

2 to 5, the width direction of the optical waveguide OW2 located immediately below the heater HT1 is the x direction, the extending direction of the optical waveguide OW2 is the y direction, and the height direction of the optical waveguide OW2 is the z direction. To do. The z direction is also the stacking direction of the interlayer insulating layers forming the multilayer wiring layer MWL and the thickness direction of the interlayer insulating layers. The x direction, the y direction, and the z direction are orthogonal to each other.

The substrate SUB is a support body that supports optical elements such as the light modulation section LM1 and the light receiving section PR via the first insulating layer CL. Examples of the type of the substrate SUB include a silicon substrate. The silicon substrate is, for example, a silicon single crystal substrate containing p-type impurities such as boron (B) and phosphorus (P). For example, the plane orientation of the main surface of the silicon substrate is (100), and the resistivity of the silicon substrate is 5 Ω·cm or more and 50 Ω·cm or less. The thickness of the substrate SUB is, for example, 100 μm or more and 900 μm or less.

The first insulating layer CL is formed on the substrate SUB. The first insulating layer CL is a clad layer for substantially confining the light propagating inside the optical waveguides OW1 and OW2 inside the optical waveguides OW1 and OW2. The first insulating layer CL is made of a material having a refractive index smaller than that of the material forming the optical waveguides OW1 and OW2. Examples of the material constituting the first insulating layer CL, includes silicon oxide (SiO _2). The refractive index of the material forming the first insulating layer CL is, for example, 1.46 (SiO ₂ ). The refractive index in this specification is a numerical value for light having a wavelength of 1.5 μm.

The thickness of the first insulating layer CL is preferably larger than the distance that light leaks from the optical waveguides OW1 and OW2. From the viewpoint of reducing the stress applied to the semiconductor device SD1 and suppressing the sticking of the semiconductor wafer by the electrostatic chuck during the manufacturing of the semiconductor device SD1, it is preferable that the thickness of the first insulating layer CL is small. For example, the thickness of the first insulating layer CL is 2 μm or more and 3 μm or less.

Note that when the first insulating layer CL functions as a support, the semiconductor device SD1 may not have the substrate SUB. In this case, the first insulating layer CL is, for example, a sapphire substrate.

The light modulator LM1 modulates the phase of light passing through the inside of the optical waveguide OW2. The configuration of the light modulator LM1 may include the optical waveguides OW1 and OW2 and the heater HT1. For example, a known configuration employed as the light modulator in the silicon photonics technology can be adopted. The light modulator LM1 may include a combination of the heater HT1, a pn-type light modulator, a pin-type light modulator, and a Semiconductor-Insulator-Semiconductor (SIS)-type light modulator. In the first embodiment, the heat control type optical modulator is composed of the optical waveguides OW1 and OW2 and the heater HT1.

As shown in FIGS. 2 and 3, the optical modulator LM1 includes an input optical waveguide Lin, two optical waveguides (branch waveguides) OW1 and OW2 branched from the optical waveguide Lin, and two optical waveguides OW1. , OW2, and an optical waveguide Lout for output and a heater HT1. In the optical modulator LM1, the light traveling inside the input optical waveguide Lin is demultiplexed into two optical waveguides OW1 and OW2, and a phase difference is given to one or both of the two optical waveguides OW1 and OW2. After that, they are multiplexed by the output optical waveguide Lout. Then, the amplitude of light is controlled by the interference of light generated in the optical waveguide Lout, and as a result, an optical signal can be generated.

The light modulator LM1 can control the phase of light passing through the inside of the optical waveguide OW2 by the thermo-optic effect. Specifically, the optical waveguide OW2 is heated by the Joule heat generated by the heater HT1. Thereby, the refractive index of the optical waveguide OW2 can be controlled. The phase of light passing through the inside of the optical waveguide OW2 changes according to the amount of change in the refractive index of the optical waveguide OW2.

An example of the configuration (shape, material, etc.) of the optical waveguide Lin of the light modulator LM1, the optical waveguide OW2, and the optical waveguide Lout of the light modulator LM1 is the same as that of the optical waveguide OW1. In the present embodiment, the optical waveguide Lin, the optical waveguide Lout, and the optical waveguide OW2 are different from the optical waveguide OW1 at least in position. Therefore, only the optical waveguide OW1 will be described below, and redundant description will be omitted. In the first embodiment, the heater is not formed directly above the optical waveguide OW1, but the heater HT1 is formed directly above the optical waveguide OW2.

The optical waveguide OW1 is a path through which light can be transmitted. The optical waveguide OW1 is formed on the first insulating layer CL. The optical waveguide OW1 is covered with the first insulating layer CL and the first interlayer insulating layer IL1. In the first embodiment, the upper surface and both side surfaces of the optical waveguide OW1 are in direct contact with the first interlayer insulating layer IL1, and the lower surface of the optical waveguide OW1 is in direct contact with the first insulating layer CL. The optical waveguide OW1 is covered with the first insulating layer CL and the first interlayer insulating layer IL1 having a refractive index smaller than that of the material forming the optical waveguide OW1. Thereby, the light can travel inside the optical waveguide OW1 while being substantially confined inside the optical waveguide OW1. However, the light travels inside the optical waveguide OW1 while seeping out to the outside of the optical waveguide OW1 by the wavelength order of the light.

The width and height of the optical waveguide OW1 should be such that light can appropriately pass through the inside of the optical waveguide OW1. The width and height of the optical waveguide OW1 can be appropriately set according to conditions such as the wavelength of light passing through the inside of the optical waveguide OW1 and the mode of the light. The width of the optical waveguide OW1 is, for example, 300 nm or more and 500 nm or less. The height of the optical waveguide OW1 is, for example, 200 nm or more and 300 nm or less.

The material forming the optical waveguide OW1 is a semiconductor material which is transparent to the light passing through it. Examples of the semiconductor material forming the optical waveguide OW1 include silicon and germanium. The crystal structure of the semiconductor material forming the optical waveguide OW1 may be a single crystal or a polycrystal. The refractive index of the material forming the optical waveguide OW1 is, for example, 3.5 (Si).

The heater HT1 is a conductive film for heating the optical waveguide OW2 by Joule heat. The position of the heater HT1 is not particularly limited as long as it can heat the optical waveguide OW2. The heater HT1 is formed so as to be separated from the optical waveguide OW2. For example, the heater HT1 may or may not overlap the optical waveguide OW2 in a plan view. In the first embodiment, the heater HT1 is formed so as to overlap the optical waveguide OW2.

From the viewpoint of suppressing the leakage light from the optical waveguide OW2 from being scattered by the heater HT1, the heater HT1 is preferably formed far from the optical waveguide OW2. For example, the distance (shortest distance) between the heater HT1 and the optical waveguide OW2 in the z direction is 300 nm or more, and preferably 400 nm or more. On the other hand, from the viewpoint of efficiently heating the optical waveguide OW2, the heater HT1 is preferably formed near the optical waveguide OW2. For example, the distance between the heater HT1 and the optical waveguide OW2 is 600 nm or less, preferably 500 nm or less.

The heater HT1 is formed in a groove portion GP formed in a second interlayer insulating layer IL2 described later. The heater HT1 is formed in the same layer as the first via Via1. The configuration of the heater HT1 is not particularly limited as long as it can exhibit the above-mentioned function as the heater HT1. For example, as shown in FIGS. 4 and 5, the heater HT1 has a barrier film BF and a conductive film CF formed on the barrier film BF.

The barrier film BF suppresses diffusion of the conductive film CF into the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2. For example, the barrier film BF is formed on the bottom surface (the upper surface of the second insulating layer STP) and the side surface of the groove portion GP formed in the second interlayer insulating layer IL2. The thickness and material of the barrier film BF are not particularly limited as long as the function can be exhibited. The thickness of the barrier film BF is 10 nm or more and 40 nm or less. Examples of the material of the barrier film include titanium (Ti) and titanium nitride (TiN).

The conductive film CF is formed on the barrier film BF in the groove portion GP. The material forming the conductive film CF is not particularly limited. The material forming the conductive film CF is any one selected from the group consisting of tungsten (W), copper (Cu), cobalt (Co), ruthenium (Ru), and aluminum (Al).

The material forming the heater HT1 (barrier film BF and conductive film CF) is preferably the same as the material forming the first via Via1 formed in the same layer as the heater HT1. Accordingly, the heater HT1 and the first via Via1 can be formed in a common process, and as a result, the ease of manufacturing the semiconductor device SD1 can be improved.

As shown in FIG. 3, the heater HT1 has three first extending portions EXP1, two second extending portions EXP2, and four connecting portions CNP. The constituent elements of the heater HT1 may be electrically connected to each other. In the first embodiment, the first extending portion EXP1, the second extending portion EXP2, and the connecting portion CNP forming the heater HT1 are integrally formed with each other.

The first extending portion EXP1 is formed so as to cross the optical waveguide OW2 in a plan view. In other words, the first extension part EXP1 extends from one region adjacent to the optical waveguide OW2 to the other region adjacent to the optical waveguide OW2 in the width direction (x direction) of the optical waveguide OW2 when seen in a plan view. It extends all over. In the first embodiment, the first extending portion EXP1 is formed along the first direction (−x direction). The planar view shape of the 1st extension part EXP1 is a straight line shape, for example.

The second extending portion EXP2 is formed so as to be in parallel with the first extending portion EXP1 in a plan view. That is, the second extending portion EXP2 is also formed so as to cross the optical waveguide OW2 in a plan view. The second extending portion EXP2 extends from the other region adjacent to the optical waveguide OW2 to the one region adjacent to the optical waveguide OW2 in the width direction (x direction) of the optical waveguide OW2 when seen in a plan view. Existence In the first embodiment, the second extending portion EXP2 is formed along the second direction (x direction) that is the opposite direction to the first direction (−x direction). The planar view shape of the 2nd extension part EXP2 is a linear shape, for example.

The width of the first extending portion EXP1 and the width of the second extending portion EXP2 may be the same as or different from each other. In the first embodiment, the width of the first extending portion EXP1 and the width of the second extending portion EXP2 are the same as each other.

The connecting portion CNP electrically connects the first extending portion EXP1 and the second extending portion EXP2 to each other. The connection portion CNP is formed along the extending direction of the optical waveguide OW2. The plan view shape of the connection portion CNP is not particularly limited as long as the above function can be exhibited. Examples of the plan view shape of the connection portion CNP include a linear shape, a curved shape, and a polygonal line shape. In the first embodiment, the plan view shape of the connection portion CNP is a polygonal line shape.

The finger length L, the finger interval P, the width W, and the thickness T of the heater HT1 can be appropriately designed according to the ease of manufacture, the desired heat capacity, the desired resistance value, and the like.

Here, the "finger length L" of the heater HT1 is the maximum length of the heater HT1 in the extending direction in which the first extending portion EXP1 (second extending portion EXP2) extends.

The “finger spacing P” of the heater HT1 is the spacing (shortest distance) between the first extending portion EXP1 and the second extending portion EXP2 adjacent to each other immediately above the optical waveguide OW2.

Further, the “width W” of the heater HT1 is the length of a portion of the first extension portion EXP1 (second extension portion EXP2) that is located immediately above the optical waveguide OW2 in the width direction of the optical waveguide OW2. Say. The width direction of the optical waveguide OW2 is a direction in which both side surfaces of the optical waveguide OW2 face each other.

Further, the “thickness T” of the heater HT refers to the length of the first extending portion EXP1 (second extending portion EXP2) in the thickness direction of the second interlayer insulating layer IL2.

The cross-sectional area of the heater HT1 is obtained by the product of the width W of the heater HT1 and the thickness T of the heater HT1.

By increasing the heat capacity of the heater HT1, it becomes easier to retain heat in the heater HT1. As a result, the heater HT1 is less likely to be affected by the outside, and Joule heat can be stably supplied to the optical waveguide OW2.

Also, by increasing the resistance value of the heater HT1, it becomes easy to generate Joule heat. The resistance value of the heater HT1 can be increased by decreasing the cross-sectional area (width W×thickness T) of the heater HT1 and increasing the total length of the heater HT1. The total length and sectional area of the heater HT1 can be adjusted according to the material forming the heater HT1. For example, when the resistance value of the material itself forming the heater HT1 is small, the desired Joule heat can be obtained by increasing the total length of the heater HT1 and decreasing the cross-sectional area of the heater HT1.

The finger length L of the heater HT1 is preferably large from the viewpoint of increasing the heat capacity of the heater HT1. Further, the finger length L of the heater HT1 is preferably small from the viewpoint of reducing the influence of heat on the optical element (for example, the optical waveguide OW1) located near the heater HT1. From these viewpoints, the finger length L of the heater HT is preferably 3 times or more and 10 times or less the width of the optical waveguide OW2. For example, the finger length L of the heater HT is preferably 0.8 μm or more and 3.0 μm or less.

The finger pitch P of the heater HT1 is preferably large from the viewpoint of stably forming the groove portion GP and the viewpoint of suppressing a short circuit between the first extending portion EXP1 and the second extending portion EXP2. Further, the finger pitch P of the heater HT1 is preferably small from the viewpoint of reducing the power consumption of the heater HT1. For example, the finger pitch P of the heater HT is preferably 0.6 μm or more and 3.0 μm or less.

The width W of the heater HT1 can be appropriately designed from the viewpoint of facilitating the heater HT1 to be embedded in the groove portion GP and the viewpoint of adjusting the resistance value of the heater HT1. For example, when the material forming the conductive film CF is tungsten, the width W of the heater HT1 is preferably 0.3 μm or more and 0.5 μm or less.

The finger pitch P of the heater HT1 may be larger than the width W of the heater HT1 (the width of the first extension part EXP1 or the second extension part EXP2), or may be smaller than the width W of the heater HT1. It is preferable that the finger pitch P of the heater HT1 is larger than the width W of the heater HT1 from the viewpoint of reducing the consumption electrode. It is preferable that the finger pitch P of the heater HT1 is smaller than the width W of the heater HT1 from the viewpoint of increasing the heat capacity.

The thickness T of the heater HT is preferably large from the viewpoint of increasing the heat capacity of the heater HT1 and the viewpoint of reducing the resistance value of the heater HT1. The thickness T of the heater HT1 is preferably small from the viewpoint of reducing the propagation loss in the optical waveguide OW2 immediately below the heater HT. For example, the thickness T of the heater HT is preferably 0.6 μm or more and 1.2 μm or less.

The ratio of the thickness of the heater HT1 to the width W of the heater HT1 can be appropriately adjusted from the viewpoint of ease of embedding the material forming the heater HT1 into the groove portion GP. For example, the ratio of the thickness T of the heater HT1 to the width W of the heater HT1 is 1 or more and 5 or less.

In the thickness direction of the second interlayer insulating layer IL2, the distance between the heater HT1 and the first insulating layer CL is preferably smaller than the distance between the upper surface of the light receiving portion PR and the first insulating layer CL. In other words, in the thickness direction of the second interlayer insulating layer IL2, the lower end surface of the heater HT1 is closer to the upper surface of the first insulating layer CL than the upper surface of the light receiving portion PR. Accordingly, the heater HT1 can be arranged near the optical waveguide OW2, and the optical waveguide OW2 can be efficiently heated.

The light receiving section PR is an optical element having a photoelectric conversion function. The configuration of the light receiving section PR is not particularly limited as long as the function can be exhibited. As the light receiving part PR, a known configuration adopted as a light receiving part in silicon photonics can be appropriately adopted. Examples of types of the light receiving section PR include a pn type light receiving section and a pin type light receiving section. In the first embodiment, the light receiving section PR is a pn type light receiving section PR, and includes a p type semiconductor section PRp and an n type semiconductor section PRn formed on the p type semiconductor section PRp.

The p-type semiconductor portion PRp is a semiconductor layer containing p-type impurities such as boron (B) and boron difluoride (BF ₂ ) and having an impurity concentration of 1×10 ¹⁷ /cm ³ or more. Examples of the material of the semiconductor layer forming the p-type semiconductor portion PRp include silicon and germanium. In the present embodiment, the material of the semiconductor layer forming the p-type semiconductor portion PRp is silicon.

The n-type semiconductor portion PRn is a semiconductor layer containing an n-type impurity such as arsenic (As) or phosphorus (P) and having an impurity concentration of 1×10 ¹⁷ /cm ³ or more. Germanium is contained in the example of the material of the semiconductor layer which comprises the n-type semiconductor part PRn.

When the light receiving part PR is a pin type light receiving part, the light receiving part PR has an i type semiconductor part formed between the p type semiconductor part PRp and the n type semiconductor part PRn. The i-type semiconductor portion is a semiconductor layer having an impurity concentration of less than 1×10 ¹⁷ /cm ³ . Examples of the material of the semiconductor layer forming the i-type semiconductor portion include germanium.

The multilayer wiring layer MWL is a layer including two or more wiring layers. The multilayer wiring layer MWL is formed on the first insulating layer CL. The wiring layer is a layer including an insulating layer and one or both of a wiring and a via (also referred to as a “plug”) formed in the same layer as the insulating layer. The via is a conductor that electrically connects two wirings formed in layers that overlap each other.

In the first embodiment, the multilayer wiring layer MWL includes the first interlayer insulating layer IL1 (referred to as “third insulating layer” in claims) and the second insulating layer STP (referred to as “third insulating layer” in claims). A fourth insulating layer), a second interlayer insulating layer IL2 (referred to as a "second insulating layer" in the claims), a first via Via1, a first wiring WR1, and a second via Via2. , The second wiring WR2 and the protective film PF. In the first embodiment, the heater HT1 is formed in the same layer as the second interlayer insulating layer IL2.

The first interlayer insulating layer IL1 is formed on the first insulating layer CL so as to cover the optical waveguides OW1 and OW2 and the light receiving portion PR. The first interlayer insulating layer IL1 is formed between the first insulating layer CL and the second insulating layer STP. The first interlayer insulating layer IL1 is made of a material having a refractive index smaller than that of the material forming the optical waveguides OW1 and OW2. An example of a material forming the first interlayer insulating layer IL1 includes silicon oxide (SiO ₂ ). The refractive index of the material forming the first interlayer insulating layer IL1 is, for example, 1.46 (SiO ₂ ). The thickness of the first interlayer insulating layer IL1 is, for example, 0.4 μm or more and 0.6 μm or less.

The second insulating layer STP is formed on the first interlayer insulating layer IL1. The second insulating layer STP is formed between the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2. The second insulating layer STP functions as an etching stopper when forming the groove portion GP that defines the shape and size of the heater HT1. The thickness, size and material of the second insulating layer STP are not particularly limited as long as the function can be exhibited. For example, the thickness of the second insulating layer STP is 30 nm or more and 100 nm or less. The second insulating layer STP may be formed immediately below the heater HT1, may be formed on the entire first interlayer insulating layer IL1, or may be formed on a part of the first interlayer insulating layer IL1. It may be formed. The material forming the second insulating layer STP is preferably different from the material forming the second interlayer insulating layer IL2. Examples of the material forming the second insulating layer STP include silicon nitride, silicon oxynitride, and carbon-added silicon oxide.

The second interlayer insulating layer IL2 is formed on the first interlayer insulating layer IL1. The second interlayer insulating layer IL2 has a groove portion GP. The thickness of the second interlayer insulating layer IL2 can be appropriately adjusted according to the desired thickness T of the heater HT1. For example, the thickness of the second interlayer insulating layer IL2 is 0.8 μm or more and 1.0 μm or less. The example of the material forming the second interlayer insulating layer IL2 is the same as the material forming the first interlayer insulating layer IL1.

A first through hole CT1 is formed in the first interlayer insulating layer IL1, the second insulating layer STP and the second interlayer insulating layer IL2. The first through hole CT1 penetrates the first interlayer insulating layer IL1, the second insulating layer STP, and the second interlayer insulating layer IL2 in the thickness direction of the first interlayer insulating layer IL1.

The first via Via1 electrically connects the light receiving portion PR and the first wiring WR1 to each other. The first via Via1 is formed so as to reach the light receiving portion PR along the thickness direction of the first interlayer insulating layer IL1. The first via Via1 is composed of a conductive film embedded in the first through hole CT1. For the first via Via1, a known configuration adopted as a via in semiconductor technology can be adopted. Examples of the material of the first via Via1 include aluminum (Al) and tungsten (W).

The groove portion GP defines the size and shape of the heater HT1. The width, depth and shape of the groove portion GP can be appropriately set according to the size and shape of the heater HT1. The groove GP may or may not penetrate the second interlayer insulating layer IL2 in the thickness direction of the second interlayer insulating layer IL2. When the groove GP penetrates the second interlayer insulating layer IL2, the heater HT1 is in direct contact with the upper surface of the second insulating layer STP, and when the groove GP does not penetrate the second interlayer insulating layer IL2, the heater HT1 is , And contacts the second insulating layer STP through a part of the second interlayer insulating layer IL2. In the first embodiment, trench GP penetrates second interlayer insulating layer IL2 in the thickness direction of second interlayer insulating layer IL2.

The first wiring WR1 is formed on the second interlayer insulating layer IL2. In FIG. 2, the first wiring WR1 located directly above the light receiving portion PR and the first wiring WR1 located directly above the heater HT1 are shown. The first wiring WR1 on the light receiving portion PR is electrically connected to the light receiving portion PR via the first vias Via1. The first wiring WR1 on the heater HT1 is electrically connected to the end portion of the heater HT1. The first wiring WR1 may have a known configuration used as a wiring in semiconductor technology. Examples of the first wiring WR1 include an aluminum wiring in which a titanium layer, a titanium nitride layer, an aluminum layer, a titanium nitride layer, and a titanium layer are stacked in this order. Also, instead of the aluminum layer, a copper layer or a tungsten layer may be used. In the first embodiment, the first wiring WR1 is the aluminum wiring described above.

The third interlayer insulating layer IL3 is formed on the second interlayer insulating layer IL2 so as to cover the first wiring WR1. An example of the material forming the third interlayer insulating layer IL3 is the same as that of the first interlayer insulating layer IL1. The thickness of the third interlayer insulating layer IL3 is, for example, 0.8 μm or more and 1.2 μm or less. A second through hole CT2 is formed in the third interlayer insulating layer IL3. The second through hole CT2 is formed so as to reach the first wiring WR1 along the thickness direction of the third interlayer insulating layer IL3.

The second via Via2 electrically connects the first wiring WR1 and the second wiring WR2 to each other. The second via Via2 is formed to reach the first wiring WR1 along the thickness direction of the third interlayer insulating layer IL3. The second via Via2 is composed of a conductive film embedded in the second through hole CT2. A well-known configuration adopted as a via in the semiconductor technology can also be adopted for the second via Via2. Examples of the material of the second via Via2 include aluminum (Al) and tungsten (W).

The second wiring WR2 is formed on the third interlayer insulating layer IL3. The second wiring WR2 is electrically connected to the first wiring WR1 via the second vias Via2. The second wiring WR2 may also have a known configuration used as a wiring in semiconductor technology. An example of the material of the second wiring WR2 is the same as that of the first wiring WR1.

The protective film PF is formed on the third interlayer insulating layer IL3 so as to cover the second wiring WR2. A pad opening POP that exposes the second wiring WR2 to the outside is formed in the protective film PF. The protective film PF has only to protect the semiconductor device SD1. Examples of the material of the protective film PF include silicon oxide, silicon oxynitride, silicon nitride, and Phospho Silicate Glass (PSG). The thickness of the protective film PF is, for example, 0.3 μm or more and 0.7 μm or less. A part of the second wiring WR2 is exposed inside the pad opening POP formed in the protective film PF. The exposed portion of the second wiring WR2 constitutes a pad portion for connecting to an external wiring such as a bonding wire.

(Method of manufacturing semiconductor device)
Next, an example of a method of manufacturing the semiconductor device SD1 according to the first embodiment will be described. 6 to 31 are main-portion cross-sectional views showing an example of steps included in the method for manufacturing the semiconductor device SD1. 6, FIG. 8, FIG. 10, FIG. 12, FIG. 14, FIG. 16, FIG. 18, FIG. 20, FIG. 22, FIG. 24, FIG. 26, FIG. 28, and FIG. FIG. 7, FIG. 11, FIG. 11, FIG. 13, FIG. 15, FIG. 17, FIG. 19, FIG. 21, FIG. 23, FIG. 25, FIG. is there.

(1) Step of Preparing Semiconductor Wafer SW First, as shown in FIGS. 6 and 7, the substrate SUB, the first insulating layer CL formed on the substrate SUB, and the semiconductor formed on the insulating layer CL. A semiconductor wafer SW having a layer SL is prepared. The semiconductor wafer SW may be manufactured or may be purchased as a commercial product.

The semiconductor wafer SW is, for example, a Silicon On Insulator (SOI) substrate. The method for manufacturing the SOI substrate can be appropriately selected from known manufacturing methods for manufacturing SOI substrates. Examples of the method for manufacturing an SOI substrate include the Separation by Implantation of Oxygen (SIMOX) method and the smart cut method.

Examples of the material of the substrate SUB are as described above. The thickness of the substrate SUB is, for example, 700 to 900 μm. Examples of the material and thickness of the first insulating layer CL are as described above. Examples of the material of the semiconductor layer SL include silicon and germanium. The crystal structure of the material of the semiconductor layer SL may be single crystal or polycrystal.

Next, as shown in FIGS. 8 and 9, the semiconductor layer SL of the prepared semiconductor wafer SW is processed to form the optical waveguides OW1 and OW2 and the p-type semiconductor portion PRp in the light receiving portion PR. For example, the optical waveguides OW1 and OW2 can be formed by patterning the semiconductor layer SL by a known photolithography technique and etching technique. For example, the p-type semiconductor portion PRp can be formed by patterning the semiconductor layer SL by a well-known photolithography technique and etching technique, and then performing ion implantation of p-type impurities.

Next, as shown in FIGS. 10 and 11, the n-type semiconductor portion PRn in the light receiving portion PR is formed on the p-type semiconductor portion PRp. For example, the n-type semiconductor portion PRn can be formed on the p-type semiconductor portion PRp by the selective epitaxial growth method. From the viewpoint of forming the n-type semiconductor portion PRn only on the p-type semiconductor portion PRp, an insulating layer having an opening may be previously formed on the p-type semiconductor portion PRp. The n-type impurity contained in the n-type semiconductor portion PRn may be introduced into the i-type semiconductor layer by ion implantation after the i-type semiconductor layer is formed by the selective epitaxial growth method, or may be introduced in the process of the selective epitaxial growth. May be done.

Next, as shown in FIGS. 12 and 13, a first interlayer insulating layer IL1 is formed on the first insulating layer CL so as to cover the optical waveguides OW1 and OW2 and the light receiving portion PR. For example, the first interlayer insulating layer IL1 can be formed by a chemical vapor deposition (CVD) method.

Next, as shown in FIGS. 14 and 15, the second insulating layer STP is formed on the first interlayer insulating layer IL1. For example, the second insulating layer STP can be formed by the Chemical Vapor Deposition (CVD) method.

Next, as shown in FIGS. 16 and 17, the second interlayer insulating layer IL2 is formed on the second insulating layer STP. For example, the second interlayer insulating layer IL2 can be formed by forming an insulating layer by a CVD method and then planarizing the insulating layer by a chemical mechanical polishing (CMP) method.

Next, the first via Via1 and the heater HT1 are formed. An example of a method of forming the first via Via1 and the heater HT1 will be described with reference to FIGS.

First, an example of a method of forming the first via Via1 will be described. For example, as shown in FIG. 19, for vias reaching the light receiving portion PR with respect to the first interlayer insulating layer IL1, the second insulating layer STP, and the second interlayer insulating layer IL2 by known photolithography technology and etching technology. To form the first through hole CT1. Next, as shown in FIG. 21, a conductive film is formed by the CVD method so as to fill the first through hole CT1, and then the conductive film formed outside the first through hole CT1 is removed by the CMP method. As described above, the first via Via1 can be formed.

An example of a method of forming the heater HT1 will be described. For example, as shown in FIGS. 18 and 19, a groove portion GP is formed in first interlayer insulating layer IL1 by a known photolithography technique and etching technique. Next, as shown in FIGS. 20 and 21, a barrier film BF is formed on the inner surface of the groove portion GP by a sputtering method, a conductive film is formed by the CVD method so as to fill the groove portion GP, and then the groove portion GP is formed by a CMP method. The conductive film formed on the outside of the substrate is removed. From the above, the heater HT1 can be formed.

The first vias Via1 and the heater HT1 may be formed in the same process at the same timing, or may be formed in different processes at different timings.

Next, as shown in FIG. 23, the first wiring WR1 is formed over the heater HT1 and the second interlayer insulating layer IL2. In the first embodiment, the first wiring WR1 electrically connected to the first via Via1 and the first wiring WR1 electrically connected to the heater HT1 are formed. For example, for the first wiring WR1, after forming a conductive film on the heater HT1 and the second interlayer insulating layer IL2 by a sputtering method, the conductive film is processed into a desired pattern by a known photolithography technique and etching technique. Can be formed by

Next, as shown in FIGS. 24 and 25, a third interlayer insulating layer IL3 is formed on the second interlayer insulating layer IL2. For example, the third interlayer insulating layer IL3 can be formed by the CVD method.

Next, as shown in FIG. 27, a second via Via2 is formed inside the third interlayer insulating layer IL3. For example, the second through hole CT2 for a via reaching the first wiring WR1 is formed in the third interlayer insulating layer IL3 by a known photolithography technique and etching technique. Next, for example, a conductive film is formed by the CVD method so as to fill the second through hole CT2, and then the conductive film formed outside the second through hole CT2 is removed by the CMP method. From the above, the second via Via2 can be formed.

Next, as shown in FIGS. 28 and 29, the second wiring WR2 is formed on the third interlayer insulating layer IL3. In the first embodiment, as shown in FIG. 29, the second wiring WR2 electrically connected to the second via Via2 is formed. For example, the second wiring WR2 is formed by forming a conductive film on the third interlayer insulating layer IL3 by a sputtering method and then processing the conductive film into a desired pattern by a known photolithography technique and etching technique. Can be done.

Next, as shown in FIGS. 30 and 31, a protective film PF is formed on the third interlayer insulating layer IL3. For example, the protective film PF can be formed by a sputtering method. Next, as shown in FIG. 31, a pad opening POP exposing a part (pad portion) of the second wiring WR2 is formed in the protective film PF by a known photolithography technique and etching technique.

Finally, the semiconductor wafer SW is diced to obtain a plurality of individual semiconductor devices SD1.

The semiconductor device SD1 according to the first embodiment can be manufactured by the above manufacturing method. The method for manufacturing the semiconductor device SD1 may further include other steps, if necessary. For example, examples of other steps include a step of arranging a laser diode as a light source, a step of forming a light modulator, and a step of forming a spot size converter.

(effect)
As described above, the semiconductor device SD1 according to the first embodiment has the heater HT1 including the first extending portion EXP1 and the second extending portion EXP2 formed so as to cross the optical waveguide OW2 in a plan view. Heater characteristics such as heat capacity and resistance value of the heater HT1 can be adjusted according to parameters such as the finger length L, the finger interval P, the width W, and the thickness T. That is, in the first embodiment, a desired heat capacity and resistance value can be realized according to the application of the heater HT1. For example, in the combined light modulator, when the heater HT1 is used for the purpose of constantly heating the optical waveguide OW2, the heat supply from the heater HT1 is stabilized by increasing the heat capacity of the heater HT1. You can

Here, from the viewpoint of describing other characteristics of the semiconductor device SD1 according to the first embodiment, a semiconductor device SD′ having a heater HT′ having a rectangular planar shape (hereinafter, “semiconductor device according to comparative example”). (Also called).

32 to 34 are schematic diagrams showing an example of the configuration of a semiconductor device SD' according to a comparative example. FIG. 32 is a plan view of an essential part of the semiconductor device SD'. 33 is a sectional view of the semiconductor device SD' taken along the line AA in FIG. 32, and FIG. 34 is a sectional view of the semiconductor device SD' taken along the line BB in FIG. Note that in FIG. 32, a part of the multilayer wiring layer MWL is omitted. In the comparative example, an LM reference code is added to the light modulator.

The heater HT' in the semiconductor device SD' according to the comparative example has a rectangular shape in plan view. The heater HT' is formed on the first interlayer insulating layer IL1'. In the semiconductor device SD′ according to the comparative example, the upper surface of the first interlayer insulating layer IL1′, which is the surface on which the heater HT′ is formed, is previously subjected to the planarization process by the CMP method before the heater HT′ is formed. In the flattening process, from the viewpoint of avoiding damage to the light receiving portion PR, the upper surface of the first interlayer insulating layer IL1′ (the surface where the heater HT′ is formed) is received in the thickness direction of the first interlayer insulating layer IL1′. It is necessary to separate from the part PR to some extent. Therefore, it is difficult to form the heater HT' near the optical waveguide OW2. Even if the heater HT' can be formed near the optical waveguide OW2, the overlapping portion of the heater HT' and the optical waveguide OW2 is large in plan view (see FIG. 32). Therefore, the ratio of the leaked light from the optical waveguide OW2 scattered by the heater HT' also increases.

On the other hand, since the heater HT1 according to the first embodiment is formed inside the groove portion GP formed in the second interlayer insulating layer IL2, the distance between the heater HT1 and the optical waveguide OW2 can be reduced. . As a result, the optical waveguide OW2 can be efficiently heated by the heater HT1, so that the response speed of the heater HT1 (switching speed of the light modulator LM1) can be increased. Further, the heater HT1 according to the first embodiment has a small overlapping portion with the optical waveguide OW2 in a plan view. As a result, it is possible to suppress the leakage light from the optical waveguide OW2 from being scattered by the heater HT1. As described above, as compared with the semiconductor device SD′ according to the comparative example, in the semiconductor device SD1 according to the embodiment, the heater HT1 can be formed closer to the optical waveguide OW2, and the heater HT1 and the optical device Even if the space between the waveguides OW2 is small, the amount of leaked light from the optical waveguide OW2 scattered by the heater HT1 can be reduced.

[Modification 1]
FIG. 35 is a partial enlarged cross-sectional view showing an example of the configuration of the semiconductor device according to the first modification of the first embodiment.

As shown in FIG. 35, in the semiconductor device according to Modification 1, the first width W1 of the end portion EXT1 of the heater MHT1 is larger than the second width W2 of the portion located between the end portions EXT1. It is preferable that the first width W1 is larger than the second width W2 from the viewpoint of reducing the potential difference in the thickness direction of the heater MHT1. For example, the ratio of the first width W1 to the second width W2 is 2 or more and 4 or less.

[Modification 2]
FIG. 36 is a partial enlarged cross-sectional view showing an example of the configuration of the semiconductor device according to the second modification of the first embodiment.

As shown in FIG. 36, in the semiconductor device according to the second modification, a slit is formed at the end portion EXT2 of the heater MHT2. As a result, the semiconductor device according to Modification 2 can achieve the same effect as the semiconductor device according to Modification 1, and in the end portion EXT2 of the heater MHT2, the material forming the heater MHT2 is inside the groove portion GP. It becomes easy to embed in.

[Embodiment 2]
In the semiconductor device SD2 according to the second embodiment, the first extension part EXP1 and the second extension part EXP2 in the heater HT2 are formed as separate bodies, and via the connection part CNP2 formed by the first wiring WR1. Are electrically connected.

The opto-electric hybrid device LE2 according to the second embodiment differs from the opto-electric hybrid device LE1 according to the first embodiment only in the configuration of the semiconductor device SD2 (see FIG. 1). The semiconductor device SD2 according to the second embodiment differs from the semiconductor device SD1 according to the first embodiment in the configuration of the heater HT2. Therefore, the same components as those of the semiconductor device SD1 according to the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

37 to 40 are schematic diagrams showing an example of the configuration of the semiconductor device SD2 according to the second embodiment. 37 is a plan view of relevant parts of the semiconductor device SD2, and FIG. 38 is a partially enlarged view of a region surrounded by a chain line shown in FIG. 39 is a sectional view of the semiconductor device SD2 taken along the line AA in FIG. 37, and FIG. 40 is a sectional view of the semiconductor device SD2 taken along the line BB in FIG. Note that, in FIGS. 37 and 38, a part of the multilayer wiring layer MWL is omitted.

As shown in FIGS. 37 to 40, the semiconductor device SD2 has a substrate SUB, a first insulating layer CL, a light modulation section LM2, a light receiving section PR, and a multilayer wiring layer MWL. Although details will be described later, the light modulation unit LM2 according to the second embodiment has optical waveguides OW1 and OW2 and a heater HT2.

The heater HT2 has three first extending portions EXP1, two second extending portions EXP2 and four connecting portions CNP2. In the second embodiment, the first extending portion EXP1 and the second extending portion EXP2 are formed as separate bodies.

The connecting portion CNP2 electrically connects the first extending portion EXP1 and the second extending portion EXP2 to each other. The connection portion CNP2 is configured by a part of the first wiring WR1. The connection portion CNP2 is formed along the extending direction of the optical waveguide OW2. The shape of the connecting portion CNP2 is not particularly limited as long as the above function can be exhibited. Examples of the shape of the connection portion CNP2 include a linear shape, a curved shape, and a polygonal line shape. In the second embodiment, the connecting portion CNP2 has a linear shape.

The semiconductor device SD2 according to the second embodiment can be manufactured in the same manner as the method for manufacturing the semiconductor device SD1 according to the first embodiment, except that the connection portion CNP2 is formed by the first wiring WR1.

(effect)
The semiconductor device SD2 according to the second embodiment also has the same effect as the semiconductor device SD1 according to the first embodiment. In the semiconductor device SD2 according to the second embodiment, since the heat capacity of the heater HT2 can be adjusted according to the size of the connection portion CNP2, the material (resistance value), arrangement, and the like of the first extension portion EXP1 and the second extension portion EXP2 The heat capacity of the heater HT2 can be finely adjusted without changing the size and shape.

It should be noted that the present invention is not limited to the above-described embodiment, and can be variously modified without departing from the gist thereof. For example, in the above embodiment, the case where the wiring layer included in the multilayer wiring layer is two layers has been described, but the number of wiring layers forming the multilayer wiring layer may be three or more. In the above embodiment, the heaters HT1 and HT2 are described as being formed directly above the optical waveguide OW2, but the heater is formed directly above both the optical waveguide OW1 and the optical waveguide OW2. Good.

Further, the multilayer wiring layer MWL may not have the second insulating layer STP. In this case, the groove portion GP having a desired depth can be formed by adjusting etching conditions such as etching time.

Further, even when a specific numerical example is described, it may be a numerical value exceeding the specific numerical value or less than the specific numerical value unless theoretically limited to the numerical value. It may be a numerical value. In addition, the term “component” means “B containing A as a main component” and the like, and does not exclude an aspect including other components.

BF Barrier film CF Conductive film CL First insulating layer CNP1, CNP2 Connection part CP IC chip CT1 First through hole CT2 Second through hole EC1 First electronic circuit EC2 Second electronic circuit EC3 Third electronic circuit EXP1 First extended part EXP2 2nd extension part GP Groove part HT1, HT2, HT' Heater IL1, IL1' 1st interlayer insulation layer IL2 2nd interlayer insulation layer IL3 3rd interlayer insulation layer LE1, LE2 Opto-electric hybrid device LM1, LM2 Light modulation part LO Light output part MWL Multi-layer wiring layer OW, OW1, OW2, Lin, Lout Optical waveguide POP Pad opening PR Light receiving part PRn n-type semiconductor part PRp p-type semiconductor part SD1, SD2, SD' Semiconductor device SL Semiconductor layer STP Second insulation Layer SUB Substrate SW Semiconductor Wafer Via1 First Via Via2 Second Via WR1 First Wiring WR2 Second Wiring

Claims (18)

A first insulating layer,
An optical waveguide formed on the first insulating layer,
A second insulating layer having a groove formed on the first insulating layer;
A heater formed in the groove so as to be separated from the optical waveguide,
Have
The heater is
A first extending portion formed so as to cross the optical waveguide in a plan view,
A second extending portion formed in parallel with the first extending portion in a plan view,
A connecting portion electrically connecting the first extending portion and the second extending portion,
A semiconductor device having: The semiconductor device according to claim 1, wherein the first extending portion, the second extending portion, and the connecting portion are integrally formed with each other. The heater has a conductive film,
The semiconductor device according to claim 2, wherein the material forming the conductive film is any one selected from the group consisting of tungsten, copper, cobalt, ruthenium, and aluminum. The heater further includes a barrier film that is in direct contact with the bottom surface and the side surface of the conductive film,
The material forming the barrier film is titanium or titanium nitride,
The semiconductor device according to claim 3. Further comprising a wire electrically connected to the end of the heater,
The material forming the wiring is copper or aluminum,
The semiconductor device according to claim 1. The connection portion is configured by wiring,
The first extending portion and the second extending portion are formed separately from each other,
The semiconductor device according to claim 1. The first extending portion and the second extending portion each have a conductive film,
The material forming the conductive film is any one selected from the group consisting of tungsten, copper, cobalt, ruthenium and aluminum,
The material forming the connecting portion is copper or aluminum,
The semiconductor device according to claim 6. The first extending portion and the second extending portion each further include a barrier film that is in direct contact with the bottom surface and the side surface of the conductive film,
The material forming the barrier film is titanium or titanium nitride,
The semiconductor device according to claim 7. A third insulating layer formed between the first insulating layer and the second insulating layer,
A fourth insulating layer formed between the second insulating layer and the third insulating layer,
Further has
The material forming the fourth insulating layer is different from the material forming the third insulating layer,
The semiconductor device according to claim 1. The material forming the third insulating layer is silicon oxide, and
The material forming the fourth insulating layer is silicon nitride,
The semiconductor device according to claim 9. The semiconductor device according to claim 1, wherein a distance between the first extending portion and the second extending portion is larger than a width of the first extending portion. The semiconductor device according to claim 1, wherein a distance between the first extending portion and the second extending portion is smaller than a width of the first extending portion. Further comprising a light receiving portion formed on the first insulating layer and having a photoelectric conversion function,
In the thickness direction of the second insulating layer, the distance between the heater and the first insulating layer is smaller than the distance between the upper surface of the light receiving portion and the first insulating layer.
The semiconductor device according to claim 1. The semiconductor device according to claim 1, wherein the ratio of the thickness of the first extending portion to the width of the first extending portion is 1 or more and 5 or less. The semiconductor device according to claim 1, wherein the thickness of the first extending portion is 0.6 μm or more and 1.2 μm or less. The semiconductor device according to claim 1, wherein a distance between the first extending portion and the second extending portion is 0.6 μm or more and 3.0 μm or less immediately above the optical waveguide. The semiconductor device according to claim 1, wherein the maximum length of the heater in the extending direction of the first extending portion is 0.8 μm or more and 3.0 μm or less. The semiconductor device according to claim 1, wherein the width of the first extending portion is 0.3 μm or more and 0.5 μm or less.

Images